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asmkit/aarch64/
emit.rs

1//! Top-level emit path: InstInfo lookup, signature validation, operand
2//! analysis, and dispatch to the emit handlers (port of AsmJit's
3//! `Assembler::_emit` from `a64assembler.cpp`).
4//!
5//! AsmJit's `goto EmitOp` / `goto EmitOp_DispImm` / `goto EmitOp_Rel` targets
6//! become the [`Handler`] enum: the encoding arms (a `match` on [`Encoding`])
7//! validate operands and compose the opcode in [`A64EmitState`], while the
8//! actual word emission is done by the handlers in [`super::encoder`].
9//!
10//! Derived from AsmJit (Zlib license) — this file is an altered version; see LICENSE notices.
11
12#![allow(clippy::eq_op, clippy::erasing_op, dead_code, unused)]
13use crate::AsmError;
14use crate::aarch64::encoder::*;
15use crate::aarch64::encoder_tables::*;
16use crate::aarch64::operands::*;
17use crate::aarch64::{Assembler, Gp, Reg, ShiftOp, instdb::*};
18use crate::core::arch_traits::Arch;
19use crate::core::buffer::CodeBuffer;
20use crate::core::buffer::{Constant, LabelUse, Reloc, RelocDistance, RelocTarget};
21use crate::core::globals::CondCode;
22use crate::core::operand::*;
23
24macro_rules! B {
25    ($e: expr) => {
26        1 << $e
27    };
28}
29
30macro_rules! check_signature {
31    ($op0: expr, $op1: expr) => {
32        $op0.signature() == $op1.signature()
33    };
34    ($op0: expr, $op1: expr, $op2: expr) => {
35        $op0.signature() == $op1.signature() && $op1.signature() == $op2.signature()
36    };
37
38    ($op0: expr, $op1: expr, $op2: expr, $op3: expr) => {
39        $op0.signature() == $op1.signature()
40            && $op1.signature() == $op2.signature()
41            && $op2.signature() == $op3.signature()
42    };
43}
44
45macro_rules! enc_ops {
46    ($op0: ident) => {
47        OperandType::$op0 as u32
48    };
49
50    ($op0: ident, $op1: ident) => {
51        OperandType::$op0 as u32 | (OperandType::$op1 as u32) << 3
52    };
53    ($op0: ident, $op1: ident, $op2: ident) => {
54        OperandType::$op0 as u32 | (OperandType::$op1 as u32) << 3 | (OperandType::$op2 as u32) << 6
55    };
56    ($op0: ident, $op1: ident, $op2: ident, $op3: ident) => {
57        OperandType::$op0 as u32
58            | (OperandType::$op1 as u32) << 3
59            | (OperandType::$op2 as u32) << 6
60            | (OperandType::$op3 as u32) << 9
61    };
62}
63
64/// Emit handler selected by an encoding arm (AsmJit's `goto EmitXxx` labels).
65#[derive(Clone, Copy, PartialEq, Eq, Debug)]
66pub(crate) enum Handler {
67    /// `EmitOp`: write the composed opcode word.
68    Op,
69    /// `EmitOp_DispImm`: pack the displacement immediate, then `EmitOp`.
70    OpDispImm,
71    /// `EmitOp_Rel`: resolve a label/immediate pc-relative operand, then
72    /// `EmitOp_DispImm`. Falls through when `rm_rel` is not relative.
73    OpRel,
74    /// Multi-word emission (mov sequences in `multiple_op_data`).
75    Multi,
76}
77
78impl<'a> Assembler<'a> {
79    /// Port of AsmJit's `Assembler::_emit`: validates the instruction's
80    /// operand signature, composes the opcode, and dispatches to the emit
81    /// handlers. Errors are recorded in `last_error`.
82    pub(crate) fn _emit(&mut self, id: u32, ops: &[&Operand]) {
83        if id & !(InstId::REAL_ID | InstId::ARM_COND) != 0 {
84            self.last_error = Some(AsmError::InvalidInstruction);
85            return;
86        }
87
88        let inst_cc = InstId::extract_cc(id);
89        let inst_id = InstId::extract_real_id(id);
90
91        if inst_id == InstId::None as u32 || inst_id >= InstId::_Count as u32 {
92            self.last_error = Some(AsmError::InvalidInstruction);
93            return;
94        }
95
96        let inst_info = &INST_INFO_TABLE[inst_id as usize];
97        let mut encoding_index = inst_info.encoding_data_index as usize;
98
99        let mut st = A64EmitState::new();
100
101        let isign4;
102        let inst_flags;
103
104        const NOREG: &Operand = &Operand::new();
105
106        let op0 = *ops.get(0).unwrap_or(&NOREG);
107        let op1 = *ops.get(1).unwrap_or(&NOREG);
108        let op2 = *ops.get(2).unwrap_or(&NOREG);
109        let op3 = *ops.get(3).unwrap_or(&NOREG);
110        let op4 = *ops.get(4).unwrap_or(&NOREG);
111        let op5 = *ops.get(5).unwrap_or(&NOREG);
112
113        isign4 = op0.op_type() as u32
114            + ((op1.op_type() as u32) << 3)
115            + ((op2.op_type() as u32) << 6)
116            + ((op3.op_type() as u32) << 9);
117        inst_flags = inst_info.flags;
118
119        macro_rules! check_features {
120            () => {{
121                let (required, context) =
122                    required_features_for_form(inst_id as usize, st.opcode.get(), ops);
123                if !self.environment().supports_aarch64_features(required) {
124                    self.last_error = Some(AsmError::MissingCpuFeature { feature: context });
125                    return;
126                }
127            }};
128        }
129
130        macro_rules! emit_op {
131            () => {{
132                check_features!();
133                self.emit_handler(Handler::Op, &mut st);
134                return;
135            }};
136        }
137
138        macro_rules! emit_disp_imm {
139            () => {{
140                check_features!();
141                self.emit_handler(Handler::OpDispImm, &mut st);
142                return;
143            }};
144        }
145
146        macro_rules! emit_rel {
147            () => {{
148                check_features!();
149                if self.emit_handler(Handler::OpRel, &mut st) {
150                    return;
151                }
152            }};
153        }
154
155        macro_rules! emit_rd0 {
156            () => {
157                st.opcode.add_reg(op0.id(), 0);
158                emit_op!();
159            };
160        }
161
162        macro_rules! emit_rn5 {
163            () => {
164                st.opcode.add_reg(op0.id(), 5);
165                emit_op!();
166            };
167        }
168
169        macro_rules! emit_rn5_rm16 {
170            () => {
171                st.opcode.add_reg(op0.id(), 5);
172                st.opcode.add_reg(op1.id(), 16);
173                emit_op!();
174            };
175        }
176
177        macro_rules! emit_rd0_rn5 {
178            () => {
179                st.opcode.add_reg(op0.id(), 0);
180                st.opcode.add_reg(op1.id(), 5);
181                emit_op!();
182            };
183        }
184
185        macro_rules! emit_rd0_rn5_rm16_ra10 {
186            () => {
187                st.opcode.add_reg(op0.id(), 0);
188                st.opcode.add_reg(op1.id(), 5);
189                st.opcode.add_reg(op2.id(), 16);
190                st.opcode.add_reg(op3.id(), 10);
191                emit_op!();
192            };
193        }
194
195        macro_rules! emit_rd0_rn5_rm16 {
196            () => {
197                st.opcode.add_reg(op0.id(), 0);
198                st.opcode.add_reg(op1.id(), 5);
199                st.opcode.add_reg(op2.id(), 16);
200                emit_op!();
201            };
202        }
203
204        macro_rules! emit_mem_base_rn5 {
205            () => {
206                st.opcode.add_reg(op0.as_::<Mem>().base_id(), 5);
207                emit_op!();
208            };
209        }
210
211        macro_rules! emit_mem_base_index_rn5_rm16 {
212            () => {
213                st.opcode.add_reg(op0.as_::<Mem>().base_id(), 5);
214                st.opcode.add_reg(op0.as_::<Mem>().index_id(), 16);
215                emit_op!();
216            };
217        }
218
219        macro_rules! emit_mem_base_no_imm_rn5 {
220            () => {
221                st.opcode.add_reg(st.rm_rel.as_::<Mem>().base_id(), 5);
222                emit_op!();
223            };
224        }
225
226        let mut encoding = match Encoding::try_from(inst_info.encoding) {
227            Ok(encoding) => encoding,
228            Err(()) => unreachable!("instdb encoding index is always a valid Encoding"),
229        };
230
231        macro_rules! simd_insn {
232            () => {
233                if isign4 == enc_ops!(Reg, Reg) && op0.as_::<Reg>().is_vec128() {
234                    if !op0.as_::<Vec>().has_element_index() {
235                        self.last_error = Some(AsmError::InvalidInstruction);
236                        return;
237                    }
238                    let element_type = op0.as_::<Vec>().element_type() as u32;
239                    let dst_index = op0.as_::<Vec>().element_index();
240                    let lsb_index = element_type - 1;
241                    let imm5 = ((dst_index << 1) | 1) << lsb_index;
242                    if imm5 > 31 {
243                        self.last_error = Some(AsmError::InvalidOperand);
244                        return;
245                    }
246                    if op1.as_::<Reg>().is_gp() {
247                        // INS - Vec[N] <- GP register.
248                        st.opcode.reset(0b0100111000000000000111 << 10);
249                        st.opcode.add_imm(imm5, 16);
250                        emit_rd0_rn5!();
251                        return;
252                    } else if op1.as_::<Reg>().is_vec128() && op1.as_::<Vec>().has_element_index() {
253                        // INS - Vec[N] <- Vec[M].
254                        if op0.as_::<Vec>().element_type() != op1.as_::<Vec>().element_type() {
255                            self.last_error = Some(AsmError::InvalidInstruction);
256                            return;
257                        }
258                        let src_index = op1.as_::<Vec>().element_index();
259                        if op0.as_::<Reg>().reg_type() != op1.as_::<Reg>().reg_type() {
260                            self.last_error = Some(AsmError::InvalidInstruction);
261                            return;
262                        }
263                        let imm4 = src_index << lsb_index;
264                        if imm4 > 15 {
265                            self.last_error = Some(AsmError::InvalidOperand);
266                            return;
267                        }
268                        st.opcode.reset(0b0110111000000000000001 << 10);
269                        st.opcode.add_imm(imm5, 16);
270                        st.opcode.add_imm(imm4, 11);
271                        emit_rd0_rn5!();
272                        return;
273                    }
274                }
275            };
276        }
277
278        macro_rules! simd_dup {
279            () => {
280                if isign4 == enc_ops!(Reg, Reg) {
281                    let k_valid_encodings = B!(VecElementType::B as u32 + 0)
282                        | B!(VecElementType::H as u32 + 0)
283                        | B!(VecElementType::S as u32 + 0)
284                        | B!(VecElementType::B as u32 + 8)
285                        | B!(VecElementType::H as u32 + 8)
286                        | B!(VecElementType::S as u32 + 8)
287                        | B!(VecElementType::D as u32 + 8);
288
289                    let q =
290                        (op0.as_::<Reg>().reg_type() as u32).wrapping_sub(RegType::Vec64 as u32);
291
292                    if op1.as_::<Reg>().is_gp() {
293                        let element_type = op0.as_::<Vec>().element_type() as u32;
294                        if q > 1 || !bit_test(k_valid_encodings, (q << 3) | element_type) {
295                            self.last_error = Some(AsmError::InvalidInstruction);
296                            return;
297                        }
298
299                        let lsb_index = element_type - 1;
300                        let imm5 = 1u32 << lsb_index;
301
302                        st.opcode.reset(0b0000111000000000000011 << 10);
303                        st.opcode.add_imm(q, 30);
304                        st.opcode.add_imm(imm5, 16);
305                        emit_rd0_rn5!();
306                    } else if !op1.as_::<Reg>().is_vec() || !op1.as_::<Vec>().has_element_index() {
307                        self.last_error = Some(AsmError::InvalidInstruction);
308                        return;
309                    } else {
310                        let dst_index = op1.as_::<Vec>().element_index();
311                        if !op0.as_::<Vec>().has_element_type() {
312                            let lsb_index = (op0.as_::<Reg>().reg_type() as u32)
313                                .wrapping_sub(RegType::Vec8 as u32);
314                            if lsb_index
315                                != op1.as_::<Vec>().element_type() as u32 - VecElementType::B as u32
316                                || lsb_index > 3
317                            {
318                                self.last_error = Some(AsmError::InvalidInstruction);
319                                return;
320                            }
321
322                            let imm5 = ((dst_index << 1) | 1u32) << lsb_index;
323                            if imm5 > 31 {
324                                self.last_error = Some(AsmError::InvalidOperand);
325                                return;
326                            }
327
328                            st.opcode.reset(0b0101111000000000000001 << 10);
329                            st.opcode.add_imm(imm5, 16);
330                            emit_rd0_rn5!();
331                        } else {
332                            let element_type = op0.as_::<Vec>().element_type() as u32;
333                            if q > 1 || !bit_test(k_valid_encodings, (q << 3) | element_type) {
334                                self.last_error = Some(AsmError::InvalidInstruction);
335                                return;
336                            }
337
338                            let lsb_index = element_type - 1;
339                            let imm5 = ((dst_index << 1) | 1u32) << lsb_index;
340                            if imm5 > 31 {
341                                self.last_error = Some(AsmError::InvalidOperand);
342                                return;
343                            }
344
345                            st.opcode.reset(0b0000111000000000000001 << 10);
346                            st.opcode.add_imm(q, 30);
347                            st.opcode.add_imm(imm5, 16);
348                            emit_rd0_rn5!();
349                        }
350                    }
351                }
352            };
353        }
354
355        macro_rules! simd_umov {
356            () => {
357                let op_data = &SIMD_SMOV_UMOV[encoding_index];
358                if isign4 == enc_ops!(Reg, Reg)
359                    && op0.as_::<Reg>().is_gp()
360                    && op1.as_::<Reg>().is_vec()
361                {
362                    let size_op = element_type_to_size_op(
363                        op_data.vec_op_type,
364                        op1.as_::<Reg>().reg_type(),
365                        op1.as_::<Vec>().element_type(),
366                    );
367                    if !size_op.is_valid() {
368                        self.last_error = Some(AsmError::InvalidInstruction);
369                        return;
370                    }
371                    if !op1.as_::<Vec>().has_element_index() {
372                        self.last_error = Some(AsmError::InvalidInstruction);
373                        return;
374                    }
375                    let x = op0.as_::<Gp>().is_gp64() as u32;
376                    let gp_must_be_x = (size_op.size() >= 3u32 - op_data.is_signed as u32) as u32;
377                    if op_data.is_signed != 0 {
378                        if gp_must_be_x != 0 && x == 0 {
379                            self.last_error = Some(AsmError::InvalidInstruction);
380                            return;
381                        }
382                    } else {
383                        if x != gp_must_be_x {
384                            self.last_error = Some(AsmError::InvalidInstruction);
385                            return;
386                        }
387                    }
388                    let element_index = op1.as_::<Vec>().element_index();
389                    let max_element_index = 15u32 >> size_op.size();
390                    if element_index > max_element_index {
391                        self.last_error = Some(AsmError::InvalidOperand);
392                        return;
393                    }
394                    let imm5 = (1u32 | (element_index << 1)) << size_op.size();
395                    st.opcode.reset((op_data.opcode as u32) << 10);
396                    st.opcode.add_imm(x, 30);
397                    st.opcode.add_imm(imm5, 16);
398                    emit_rd0_rn5!();
399                    return;
400                }
401            };
402        }
403
404        match encoding {
405            Encoding::BaseOp => {
406                let op_data = &BASE_OP[encoding_index];
407                if isign4 == 0 {
408                    st.opcode.reset(op_data.opcode);
409                    emit_op!();
410                }
411            }
412
413            Encoding::BaseOpX16 => {
414                let op_data = &BASE_OP_X16[encoding_index];
415                if isign4 == enc_ops!(Reg) && op0.as_::<Reg>().is_gp64() && op0.id() == 16 {
416                    st.opcode.reset(op_data.opcode);
417                    emit_op!();
418                }
419            }
420
421            Encoding::BaseOpImm => {
422                let op_data = &BASE_OP_IMM[encoding_index];
423                if isign4 == enc_ops!(Imm) {
424                    let imm = op0.as_::<Imm>().value() as u64;
425                    let imm_max = 1u64 << op_data.imm_bits as u32;
426                    if imm >= imm_max {
427                        self.last_error = Some(AsmError::TooLarge);
428                        return;
429                    }
430                    st.opcode.reset(op_data.opcode);
431                    st.opcode.add_imm(imm as u32, op_data.imm_offset as _);
432                    emit_op!();
433                }
434            }
435
436            Encoding::BaseR => {
437                let op_data = &BASE_R[encoding_index];
438                if isign4 == enc_ops!(Reg) {
439                    st.opcode.reset(op_data.opcode);
440                    st.opcode.add_reg(op0.id(), op_data.r_shift);
441                    emit_op!();
442                }
443            }
444
445            Encoding::BaseRR => {
446                let op_data = &BASE_RR[encoding_index];
447                if isign4 == enc_ops!(Reg, Reg) {
448                    let mut x = 0;
449                    if !check_gp_typex(op0, op_data.a_type, &mut x) {
450                        self.last_error = Some(AsmError::InvalidOperand);
451                        return;
452                    }
453                    if !check_gp_type(op1, op_data.b_type) {
454                        self.last_error = Some(AsmError::InvalidOperand);
455                        return;
456                    }
457
458                    if op_data.uniform != 0 && !check_signature!(op0, op1) {
459                        self.last_error = Some(AsmError::InvalidOperand);
460                        return;
461                    }
462
463                    if !check_gp_id(op0, op_data.a_hi_id) || !check_gp_id(op1, op_data.b_hi_id) {
464                        self.last_error = Some(AsmError::InvalidOperand);
465                        return;
466                    }
467                    st.opcode.reset(op_data.opcode);
468                    st.opcode.add_imm(x, 31);
469                    st.opcode.add_reg(op1.id(), op_data.b_shift);
470                    st.opcode.add_reg(op0.id(), op_data.a_shift);
471                    emit_op!();
472                }
473            }
474
475            Encoding::BaseRRR => {
476                let op_data = &BASE_RRR[encoding_index];
477                if isign4 == enc_ops!(Reg, Reg, Reg) {
478                    let mut x = 0;
479                    if !check_gp_typex(op0, op_data.a_type, &mut x) {
480                        self.last_error = Some(AsmError::InvalidOperand);
481                        return;
482                    }
483                    if !check_gp_type(op1, op_data.b_type) || !check_gp_type(op2, op_data.c_type) {
484                        self.last_error = Some(AsmError::InvalidOperand);
485                        return;
486                    }
487
488                    if op_data.uniform != 0 && !check_signature!(op0, op1, op2) {
489                        self.last_error = Some(AsmError::InvalidInstruction);
490                        return;
491                    }
492
493                    if !check_gp_id(op0, op_data.a_hi_id)
494                        || !check_gp_id(op1, op_data.b_hi_id)
495                        || !check_gp_id(op2, op_data.c_hi_id)
496                    {
497                        self.last_error = Some(AsmError::InvalidOperand);
498                        return;
499                    }
500                    st.opcode.reset(op_data.opcode());
501                    st.opcode.add_imm(x, 31);
502                    st.opcode.add_reg(op2.id(), 16);
503                    st.opcode.add_reg(op1.id(), 5);
504                    st.opcode.add_reg(op0.id(), 0);
505                    emit_op!();
506                }
507            }
508
509            Encoding::BaseRRRR => {
510                let op_data = &BASE_RRRR[encoding_index];
511                if isign4 == enc_ops!(Reg, Reg, Reg, Reg) {
512                    let mut x = 0;
513                    if !check_gp_typex(op0, op_data.a_type, &mut x) {
514                        self.last_error = Some(AsmError::InvalidOperand);
515                        return;
516                    }
517                    if !check_gp_type(op1, op_data.b_type)
518                        || !check_gp_type(op2, op_data.c_type)
519                        || !check_gp_type(op3, op_data.d_type)
520                    {
521                        self.last_error = Some(AsmError::InvalidOperand);
522                        return;
523                    }
524
525                    if op_data.uniform != 0 && !check_signature!(op0, op1, op2, op3) {
526                        self.last_error = Some(AsmError::InvalidInstruction);
527                        return;
528                    }
529
530                    if !check_gp_id(op0, op_data.a_hi_id)
531                        || !check_gp_id(op1, op_data.b_hi_id)
532                        || !check_gp_id(op2, op_data.c_hi_id)
533                        || !check_gp_id(op3, op_data.d_hi_id)
534                    {
535                        self.last_error = Some(AsmError::InvalidOperand);
536                        return;
537                    }
538                    st.opcode.reset(op_data.opcode());
539                    st.opcode.add_imm(x, 31);
540                    st.opcode.add_reg(op2.id(), 16);
541                    st.opcode.add_reg(op3.id(), 10);
542                    st.opcode.add_reg(op1.id(), 5);
543                    st.opcode.add_reg(op0.id(), 0);
544                    emit_op!();
545                }
546            }
547
548            Encoding::BaseRRII => {
549                let op_data = &BASE_RRII[encoding_index];
550                if isign4 == enc_ops!(Reg, Reg, Imm, Imm) {
551                    let mut x = 0;
552                    if !check_gp_typex(op0, op_data.a_type, &mut x) {
553                        self.last_error = Some(AsmError::InvalidOperand);
554                        return;
555                    }
556                    if !check_gp_type(op1, op_data.b_type) {
557                        self.last_error = Some(AsmError::InvalidOperand);
558                        return;
559                    }
560
561                    if !check_gp_id(op0, op_data.a_hi_id) || !check_gp_id(op1, op_data.b_hi_id) {
562                        self.last_error = Some(AsmError::InvalidOperand);
563                        return;
564                    }
565
566                    let imm2 = op2.as_::<Imm>().value() as u64;
567                    let imm3 = op3.as_::<Imm>().value() as u64;
568
569                    if imm2 >= 1u64 << (op_data.a_imm_size + op_data.a_imm_discard_lsb)
570                        || imm3 >= 1u64 << (op_data.b_imm_size + op_data.b_imm_discard_lsb)
571                    {
572                        self.last_error = Some(AsmError::TooLarge);
573                        return;
574                    }
575
576                    let a_imm = imm2 as u32 >> op_data.a_imm_discard_lsb;
577                    let b_imm = imm3 as u32 >> op_data.b_imm_discard_lsb;
578
579                    if (a_imm << op_data.a_imm_discard_lsb) != imm2 as u32
580                        || (b_imm << op_data.b_imm_discard_lsb) != imm3 as u32
581                    {
582                        self.last_error = Some(AsmError::TooLarge);
583                        return;
584                    }
585
586                    st.opcode.reset(op_data.opcode());
587                    st.opcode.add_imm(a_imm, op_data.a_imm_offset);
588                    st.opcode.add_imm(b_imm, op_data.b_imm_offset);
589                    st.opcode.add_reg(op1.id(), 5);
590                    st.opcode.add_reg(op0.id(), 0);
591                    emit_op!();
592                }
593            }
594
595            Encoding::BaseMov => {
596                let x = (op0.as_::<Reg>().typ() as u32).wrapping_sub(RegType::Gp32 as u32);
597                if x > 1 {
598                    self.last_error = Some(AsmError::InvalidOperand);
599                    return;
600                }
601
602                if isign4 == enc_ops!(Reg, Reg) {
603                    if !op0.as_::<Reg>().is_gp() || !op1.as_::<Reg>().is_gp() {
604                        self.last_error = Some(AsmError::InvalidOperand);
605                        return;
606                    }
607
608                    if !check_signature!(op0, op1) {
609                        self.last_error = Some(AsmError::InvalidInstruction);
610                        return;
611                    }
612
613                    let has_sp = op0.as_::<Reg>().is_sp() || op1.as_::<Reg>().is_sp();
614
615                    if has_sp {
616                        if !check_gp_id2(op0, op1, 31) {
617                            self.last_error = Some(AsmError::InvalidOperand);
618                            return;
619                        }
620                        st.opcode.reset(0b00010001000000000000000000000000);
621                        st.opcode.add_imm(x, 31);
622                        st.opcode.add_reg(op1.id(), 5);
623                        st.opcode.add_reg(op0.id(), 0);
624                        emit_op!();
625                    } else {
626                        if !check_gp_id2(op0, op1, 63) {
627                            self.last_error = Some(AsmError::InvalidOperand);
628                            return;
629                        }
630                        st.opcode.reset(0b00101010000000000000001111100000);
631                        st.opcode.add_imm(x, 31);
632                        st.opcode.add_reg(op1.id(), 16);
633                        st.opcode.add_reg(op0.id(), 0);
634                        emit_op!();
635                    }
636                }
637
638                if isign4 == enc_ops!(Reg, Imm) {
639                    if !op0.as_::<Reg>().is_gp() {
640                        self.last_error = Some(AsmError::InvalidOperand);
641                        return;
642                    }
643
644                    let mut imm_value = op1.as_::<Imm>().value() as u64;
645                    if x == 0 {
646                        imm_value &= 0xFFFFFFFF;
647                    }
648
649                    // Prefer a single MOVN/MOVZ instruction over a logical instruction.
650                    st.multiple_op_count = encode_mov_sequence64(
651                        &mut st.multiple_op_data,
652                        imm_value,
653                        op0.id() & 31,
654                        x,
655                    );
656                    if st.multiple_op_count == 1 && !op0.as_::<Gp>().is_sp() {
657                        st.opcode.reset(st.multiple_op_data[0]);
658                        emit_op!();
659                    }
660
661                    if !op0.as_::<Gp>().is_zr() {
662                        if let Some(logical_imm) =
663                            encode_logical_imm(imm_value, if x != 0 { 64 } else { 32 })
664                        {
665                            st.opcode.reset(0b00110010000000000000001111100000);
666                            st.opcode.add_imm(x, 31);
667                            st.opcode.add_logical_imm(&logical_imm);
668                            st.opcode.add_reg(op0.id(), 0);
669                            emit_op!();
670                        }
671                    }
672
673                    check_features!();
674                    self.emit_handler(Handler::Multi, &mut st);
675                    return;
676                }
677            }
678
679            Encoding::BaseMovKNZ => {
680                let op_data = &BASE_MOV_KNZ[encoding_index];
681
682                let x = (op0.as_::<Reg>().typ() as u32).wrapping_sub(RegType::Gp32 as u32);
683                if x > 1 {
684                    self.last_error = Some(AsmError::InvalidInstruction);
685                    return;
686                }
687
688                if !check_gp_id(op0, 63) {
689                    self.last_error = Some(AsmError::InvalidOperand);
690                    return;
691                }
692
693                st.opcode.reset(op_data.opcode);
694                st.opcode.add_imm(x, 31);
695
696                if isign4 == enc_ops!(Reg, Imm) {
697                    let imm16 = op1.as_::<Imm>().value() as u64;
698                    if imm16 > 0xFFFF {
699                        self.last_error = Some(AsmError::TooLarge);
700                        return;
701                    }
702
703                    st.opcode.add_imm(imm16 as u32, 5);
704                    st.opcode.add_reg(op0.id(), 0);
705                    emit_op!();
706                }
707
708                if isign4 == enc_ops!(Reg, Imm, Imm) {
709                    let imm16 = op1.as_::<Imm>().value() as u64;
710                    let shift_type = op2.as_::<Imm>().predicate();
711                    let shift_value = op2.as_::<Imm>().value() as u64;
712
713                    if imm16 > 0xFFFF || shift_value > 48 || shift_type != ShiftOp::LSL as u32 {
714                        self.last_error = Some(AsmError::TooLarge);
715                        return;
716                    }
717
718                    let hw = (shift_value as u32) >> 4;
719
720                    if hw << 4 != shift_value as u32 {
721                        self.last_error = Some(AsmError::InvalidOperand);
722                        return;
723                    }
724
725                    st.opcode.add_imm(hw, 21);
726                    st.opcode.add_imm(imm16 as u32, 5);
727                    st.opcode.add_reg(op0.id(), 0);
728
729                    if x == 0 && hw > 1 {
730                        self.last_error = Some(AsmError::InvalidOperand);
731                        return;
732                    }
733
734                    emit_op!();
735                }
736            }
737
738            Encoding::BaseAdr => {
739                let op_data = &BASE_ADR[encoding_index];
740                if isign4 == enc_ops!(Reg, Label)
741                    || isign4 == enc_ops!(Reg, Sym)
742                    || isign4 == enc_ops!(Reg, Imm)
743                {
744                    if !op0.as_::<Reg>().is_gp() {
745                        self.last_error = Some(AsmError::InvalidOperand);
746                        return;
747                    }
748
749                    if !check_gp_id(op0, 63) {
750                        self.last_error = Some(AsmError::InvalidOperand);
751                        return;
752                    }
753
754                    st.opcode.reset(op_data.opcode());
755                    st.opcode.add_reg(op0.id(), 0);
756                    st.offset_format.reset_to_imm_type(
757                        match OffsetType::try_from(op_data.offset_type) {
758                            Ok(offset_type) => offset_type,
759                            Err(()) => {
760                                unreachable!("instdb offset type is always a valid OffsetType")
761                            }
762                        },
763                        4,
764                        5,
765                        21,
766                        0,
767                    );
768
769                    if inst_id == InstId::Adrp as u32 {
770                        st.offset_format.imm_discard_lsb = 12;
771                    }
772                    st.rm_rel = *op1;
773                    emit_rel!();
774                }
775            }
776
777            Encoding::BaseAddSub => {
778                let op_data = &BASE_ADD_SUB[encoding_index];
779
780                let mut x = 0;
781                if !check_gp_typex2(op0, op1, 3, &mut x) {
782                    self.last_error = Some(AsmError::InvalidOperand);
783                    return;
784                }
785
786                if isign4 == enc_ops!(Reg, Reg, Imm) || isign4 == enc_ops!(Reg, Reg, Imm, Imm) {
787                    st.opcode.reset((op_data.immediate_op as u32) << 24);
788
789                    // ADD | SUB (immediate) - ZR is not allowed.
790                    // ADDS|SUBS (immediate) - ZR allowed in Rd, SP allowed in Rn.
791                    let a_hi_id = if st.opcode.get() & 1 << 29 != 0 {
792                        63
793                    } else {
794                        31
795                    };
796                    let b_hi_id = 31;
797                    if !check_gp_id(op0, a_hi_id) || !check_gp_id(op1, b_hi_id) {
798                        self.last_error = Some(AsmError::InvalidOperand);
799                        return;
800                    }
801
802                    let mut imm = op2.as_::<Imm>().value() as u64;
803                    let mut shift = 0;
804
805                    if isign4 == enc_ops!(Reg, Reg, Imm, Imm) {
806                        if op3.as_::<Imm>().predicate() != ShiftOp::LSL as u32 {
807                            self.last_error = Some(AsmError::InvalidOperand);
808                            return;
809                        }
810
811                        if op3.as_::<Imm>().value() != 0 && op3.as_::<Imm>().value() != 12 {
812                            self.last_error = Some(AsmError::InvalidOperand);
813                            return;
814                        }
815
816                        shift = (op3.as_::<Imm>().value() != 0) as u32;
817                    }
818
819                    if imm > 0xfff {
820                        if shift != 0 || (imm & !(0xfff << 12)) != 0 {
821                            self.last_error = Some(AsmError::TooLarge);
822                            return;
823                        }
824
825                        shift = 1;
826                        imm >>= 12;
827                    }
828
829                    st.opcode.add_imm(x, 31);
830                    st.opcode.add_imm(shift, 12);
831                    st.opcode.add_imm(imm as u32, 10);
832                    st.opcode.add_reg(op1.id(), 5);
833                    st.opcode.add_reg(op0.id(), 0);
834                    emit_op!();
835                }
836
837                if isign4 == enc_ops!(Reg, Reg, Reg) || isign4 == enc_ops!(Reg, Reg, Reg, Imm) {
838                    let op_size = if x != 0 { 64 } else { 32 };
839                    let mut shift = 0;
840                    let mut shift_type = ShiftOp::LSL as u32;
841
842                    if isign4 == enc_ops!(Reg, Reg, Reg, Imm) {
843                        shift_type = op3.as_::<Imm>().predicate();
844                        shift = op3.as_::<Imm>().value() as u32;
845                    }
846
847                    if !check_gp_id(op2, 63) {
848                        self.last_error = Some(AsmError::InvalidOperand);
849                        return;
850                    }
851
852                    if shift_type <= ShiftOp::ASR as u32 {
853                        let has_sp = op0.as_::<Gp>().is_sp() || op1.as_::<Gp>().is_sp();
854
855                        if !has_sp {
856                            if !check_signature!(op1, op2) {
857                                self.last_error = Some(AsmError::InvalidInstruction);
858                                return;
859                            }
860
861                            if !check_gp_id3(op0, op1, op2, 63) {
862                                self.last_error = Some(AsmError::InvalidOperand);
863                                return;
864                            }
865
866                            if shift >= op_size {
867                                self.last_error = Some(AsmError::InvalidOperand);
868                                return;
869                            }
870
871                            st.opcode.reset((op_data.shifted_op as u32) << 21);
872                            st.opcode.add_imm(x, 31);
873                            st.opcode.add_imm(shift_type, 22);
874                            st.opcode.add_reg(op2.id(), 16);
875                            st.opcode.add_imm(shift, 10);
876                            st.opcode.add_reg(op1.id(), 5);
877                            st.opcode.add_reg(op0.id(), 0);
878                            emit_op!();
879                        }
880
881                        if shift_type != ShiftOp::LSL as u32 {
882                            self.last_error = Some(AsmError::InvalidOperand);
883                            return;
884                        }
885
886                        shift_type = if x != 0 {
887                            ShiftOp::UXTX as u32
888                        } else {
889                            ShiftOp::UXTW as u32
890                        };
891                    }
892
893                    st.opcode.reset((op_data.extended_op as u32) << 21);
894                    shift_type = shift_type.wrapping_sub(ShiftOp::UXTB as u32);
895
896                    if shift_type > 7 || shift > 4 {
897                        self.last_error = Some(AsmError::InvalidOperand);
898                        return;
899                    }
900
901                    if (st.opcode.get() & (1 << 29)) == 0 {
902                        if !check_gp_id2(op0, op1, 31) {
903                            self.last_error = Some(AsmError::InvalidOperand);
904                            return;
905                        }
906                    } else {
907                        if !check_gp_id(op0, 63) || !check_gp_id(op1, 31) {
908                            self.last_error = Some(AsmError::InvalidOperand);
909                            return;
910                        }
911                    }
912
913                    st.opcode.add_imm(x, 31);
914                    st.opcode.add_reg(op2.id(), 16);
915                    st.opcode.add_imm(shift_type, 13);
916                    st.opcode.add_imm(shift, 10);
917                    st.opcode.add_reg(op1.id(), 5);
918                    st.opcode.add_reg(op0.id(), 0);
919                    emit_op!();
920                }
921            }
922
923            Encoding::BaseLogical => {
924                let op_data = &BASE_LOGICAL[encoding_index];
925
926                let mut x = 0;
927                if !check_gp_typex2(op0, op1, 3, &mut x) {
928                    self.last_error = Some(AsmError::InvalidOperand);
929                    return;
930                }
931
932                if !check_signature!(op0, op1) {
933                    self.last_error = Some(AsmError::InvalidInstruction);
934                    return;
935                }
936
937                let op_size = if x != 0 { 64 } else { 32 };
938
939                if isign4 == enc_ops!(Reg, Reg, Imm) && op_data.immediate_op != 0 {
940                    st.opcode.reset((op_data.immediate_op as u32) << 23);
941
942                    let imm_mask = lsb_mask::<u64>(op_size);
943                    let mut imm_value = op2.as_::<Imm>().value() as u64;
944
945                    if op_data.negate_imm != 0 {
946                        imm_value ^= imm_mask;
947                    }
948
949                    let Some(logical_imm) = encode_logical_imm(imm_value, op_size) else {
950                        self.last_error = Some(AsmError::InvalidOperand);
951                        return;
952                    };
953
954                    let op_ands = 0x3 << 29;
955                    let is_ands = (st.opcode.get() & op_ands) == op_ands;
956
957                    if !check_gp_id(op0, if is_ands { 63 } else { 31 }) || !check_gp_id(op1, 63) {
958                        self.last_error = Some(AsmError::InvalidOperand);
959                        return;
960                    }
961
962                    st.opcode.add_imm(x, 31);
963                    st.opcode.add_logical_imm(&logical_imm);
964                    st.opcode.add_reg(op1.id(), 5);
965                    st.opcode.add_reg(op0.id(), 0);
966                    emit_op!();
967                }
968
969                if !check_signature!(op1, op2) {
970                    self.last_error = Some(AsmError::InvalidInstruction);
971                    return;
972                }
973
974                if isign4 == enc_ops!(Reg, Reg, Reg) {
975                    if !check_gp_id3(op0, op1, op2, 63) {
976                        self.last_error = Some(AsmError::InvalidOperand);
977                        return;
978                    }
979
980                    st.opcode.reset((op_data.shifted_op as u32) << 21);
981                    st.opcode.add_imm(x, 31);
982                    st.opcode.add_reg(op2.id(), 16);
983                    st.opcode.add_reg(op1.id(), 5);
984                    st.opcode.add_reg(op0.id(), 0);
985                    emit_op!();
986                }
987
988                if isign4 == enc_ops!(Reg, Reg, Reg, Imm) {
989                    if !check_gp_id3(op0, op1, op2, 63) {
990                        self.last_error = Some(AsmError::InvalidOperand);
991                        return;
992                    }
993
994                    let shift_type = op3.as_::<Imm>().predicate();
995                    let op_shift = op3.as_::<Imm>().value() as u32;
996
997                    if shift_type > 0x3 || op_shift >= op_size {
998                        self.last_error = Some(AsmError::InvalidOperand);
999                        return;
1000                    }
1001
1002                    st.opcode.reset((op_data.shifted_op as u32) << 21);
1003                    st.opcode.add_imm(x, 31);
1004                    st.opcode.add_imm(shift_type, 22);
1005                    st.opcode.add_reg(op2.id(), 16);
1006                    st.opcode.add_imm(op_shift, 10);
1007                    st.opcode.add_reg(op1.id(), 5);
1008                    st.opcode.add_reg(op0.id(), 0);
1009                    emit_op!();
1010                }
1011            }
1012
1013            Encoding::BaseCmpCmn => {
1014                let op_data = &BASE_CMP_CMN[encoding_index];
1015
1016                let mut x = 0;
1017                if !check_gp_typex(op0, 3, &mut x) {
1018                    self.last_error = Some(AsmError::InvalidOperand);
1019                    return;
1020                }
1021
1022                if isign4 == enc_ops!(Reg, Imm) {
1023                    if !check_gp_id(op0, 31) {
1024                        self.last_error = Some(AsmError::InvalidOperand);
1025                        return;
1026                    }
1027
1028                    let imm12 = op1.as_::<Imm>();
1029                    let mut imm_shift = 0;
1030                    let mut imm_value = imm12.value() as u64;
1031
1032                    if imm_value > 0xfff {
1033                        if (imm_value & !(0xfff << 12)) != 0 {
1034                            self.last_error = Some(AsmError::TooLarge);
1035                            return;
1036                        }
1037                        imm_shift = 1;
1038                        imm_value >>= 12;
1039                    }
1040
1041                    st.opcode.reset((op_data.immediate_op as u32) << 24);
1042                    st.opcode.add_imm(x, 31);
1043                    st.opcode.add_imm(imm_shift, 22);
1044                    st.opcode.add_imm(imm_value as u32, 10);
1045                    st.opcode.add_reg(op0.id(), 5);
1046                    st.opcode.add_reg(63, 0);
1047                    emit_op!();
1048                }
1049
1050                if isign4 == enc_ops!(Reg, Reg) || isign4 == enc_ops!(Reg, Reg, Imm) {
1051                    let op_size = if x != 0 { 64 } else { 32 };
1052                    let mut shift_type = 0;
1053                    let mut shift_value = 0;
1054
1055                    if isign4 == enc_ops!(Reg, Reg, Imm) {
1056                        shift_type = op2.as_::<Imm>().predicate();
1057                        shift_value = op2.as_::<Imm>().value() as u32;
1058                    }
1059
1060                    let has_sp = op0.as_::<Gp>().is_sp() || op1.as_::<Gp>().is_sp();
1061
1062                    if shift_type <= ShiftOp::ASR as u32 {
1063                        if !has_sp {
1064                            if !check_signature!(op0, op1) {
1065                                self.last_error = Some(AsmError::InvalidInstruction);
1066                                return;
1067                            }
1068
1069                            if shift_value >= op_size {
1070                                self.last_error = Some(AsmError::InvalidOperand);
1071                                return;
1072                            }
1073
1074                            st.opcode.reset((op_data.shifted_op as u32) << 21);
1075                            st.opcode.add_imm(x, 31);
1076                            st.opcode.add_imm(shift_type, 22);
1077                            st.opcode.add_reg(op1.id(), 16);
1078                            st.opcode.add_imm(shift_value, 10);
1079                            st.opcode.add_reg(op0.id(), 5);
1080                            st.opcode.add_reg(63, 0);
1081                            emit_op!();
1082                        }
1083
1084                        if shift_type != ShiftOp::LSL as u32 {
1085                            self.last_error = Some(AsmError::InvalidOperand);
1086                            return;
1087                        }
1088
1089                        shift_type = if x != 0 {
1090                            ShiftOp::UXTX as u32
1091                        } else {
1092                            ShiftOp::UXTW as u32
1093                        }
1094                    }
1095
1096                    shift_type = shift_type.wrapping_sub(ShiftOp::UXTB as u32);
1097
1098                    if shift_type > 7 || shift_value > 4 {
1099                        self.last_error = Some(AsmError::InvalidOperand);
1100                        return;
1101                    }
1102
1103                    st.opcode.reset((op_data.extended_op as u32) << 21);
1104                    st.opcode.add_imm(x, 31);
1105                    st.opcode.add_reg(op1.id(), 16);
1106                    st.opcode.add_imm(shift_type, 13);
1107                    st.opcode.add_imm(shift_value, 10);
1108                    st.opcode.add_reg(op0.id(), 5);
1109                    st.opcode.add_reg(63, 0);
1110                    emit_op!();
1111                }
1112            }
1113
1114            Encoding::BaseMvnNeg => {
1115                let op_data = &BASE_MVN_NEG[encoding_index];
1116
1117                let mut x = 0;
1118                if !check_gp_typex2(op0, op1, 3, &mut x) {
1119                    self.last_error = Some(AsmError::InvalidOperand);
1120                    return;
1121                }
1122
1123                st.opcode.reset(op_data.opcode);
1124                st.opcode.add_imm(x, 31);
1125                st.opcode.add_reg(op1.id(), 16);
1126                st.opcode.add_reg(op0.id(), 0);
1127
1128                if isign4 == enc_ops!(Reg, Reg) {
1129                    if !check_gp_id2(op0, op1, 63) {
1130                        self.last_error = Some(AsmError::InvalidOperand);
1131                        return;
1132                    }
1133
1134                    emit_op!();
1135                }
1136
1137                if isign4 == enc_ops!(Reg, Reg, Imm) {
1138                    if !check_gp_id2(op0, op1, 63) {
1139                        self.last_error = Some(AsmError::InvalidOperand);
1140                        return;
1141                    }
1142
1143                    let op_size = if x != 0 { 64 } else { 32 };
1144                    let shift_type = op2.as_::<Imm>().predicate();
1145                    let shift_value = op2.as_::<Imm>().value() as u32;
1146
1147                    if shift_type > ShiftOp::ROR as u32 || shift_value >= op_size {
1148                        self.last_error = Some(AsmError::InvalidOperand);
1149                        return;
1150                    }
1151
1152                    st.opcode.add_imm(shift_type, 22);
1153                    st.opcode.add_imm(shift_value, 10);
1154                    emit_op!();
1155                }
1156            }
1157
1158            Encoding::BaseTst => {
1159                let op_data = &BASE_TST[encoding_index];
1160
1161                let mut x = 0;
1162                if !check_gp_typex(op0, 3, &mut x) {
1163                    self.last_error = Some(AsmError::InvalidOperand);
1164                    return;
1165                }
1166
1167                if isign4 == enc_ops!(Reg, Imm) && op_data.immediate_op != 0 {
1168                    if !check_gp_id(op0, 63) {
1169                        self.last_error = Some(AsmError::InvalidOperand);
1170                        return;
1171                    }
1172                    let op_size = if x != 0 { 64 } else { 32 };
1173                    let imm_mask = lsb_mask::<u64>(op_size);
1174                    let imm_value = op1.as_::<Imm>().value() as u64;
1175
1176                    let Some(logical_imm) = encode_logical_imm(imm_value & imm_mask, op_size)
1177                    else {
1178                        self.last_error = Some(AsmError::InvalidOperand);
1179                        return;
1180                    };
1181
1182                    st.opcode.reset((op_data.immediate_op as u32) << 22);
1183                    st.opcode.add_logical_imm(&logical_imm);
1184                    st.opcode.add_imm(x, 31);
1185                    st.opcode.add_reg(op0.id(), 5);
1186                    st.opcode.add_reg(63, 0);
1187                    emit_op!();
1188                }
1189
1190                st.opcode.reset((op_data.shifted_op as u32) << 21);
1191                st.opcode.add_imm(x, 31);
1192                st.opcode.add_reg(op1.id(), 16);
1193                st.opcode.add_reg(op0.id(), 5);
1194                st.opcode.add_reg(63, 0);
1195
1196                if isign4 == enc_ops!(Reg, Reg) {
1197                    if !check_gp_id2(op0, op1, 63) {
1198                        self.last_error = Some(AsmError::InvalidOperand);
1199                        return;
1200                    }
1201
1202                    emit_op!();
1203                }
1204
1205                if isign4 == enc_ops!(Reg, Reg, Imm) {
1206                    if !check_gp_id2(op0, op1, 63) {
1207                        self.last_error = Some(AsmError::InvalidOperand);
1208                        return;
1209                    }
1210
1211                    let shift_type = op2.as_::<Imm>().predicate();
1212                    let shift_value = op2.as_::<Imm>().value() as u32;
1213
1214                    if shift_type > 0x3 || shift_value >= (if x != 0 { 64 } else { 32 }) {
1215                        self.last_error = Some(AsmError::InvalidOperand);
1216                        return;
1217                    }
1218
1219                    st.opcode.add_imm(shift_type, 22);
1220                    st.opcode.add_imm(shift_value, 10);
1221                    emit_op!();
1222                }
1223            }
1224
1225            Encoding::BaseBfc => {
1226                let op_data = &BASE_BFC[encoding_index];
1227                if isign4 == enc_ops!(Reg, Imm, Imm) {
1228                    let mut x = 0;
1229                    if !check_gp_typex(op0, 3, &mut x) {
1230                        self.last_error = Some(AsmError::InvalidOperand);
1231                        return;
1232                    }
1233
1234                    let lsb = op1.as_::<Imm>().value() as u64;
1235                    let width = op2.as_::<Imm>().value() as u64;
1236                    let op_size = if x != 0 { 64 } else { 32 };
1237
1238                    if lsb >= op_size || width == 0 || width > op_size {
1239                        self.last_error = Some(AsmError::InvalidOperand);
1240                        return;
1241                    }
1242
1243                    let lsb32 = 0u32.wrapping_sub(lsb as u32) & (op_size as u32 - 1);
1244                    let width32 = width as u32 - 1;
1245
1246                    st.opcode.reset(op_data.opcode);
1247                    st.opcode.add_imm(x, 31);
1248                    st.opcode.add_imm(x, 22);
1249                    st.opcode.add_imm(lsb32, 16);
1250                    st.opcode.add_imm(width32, 10);
1251                    st.opcode.add_reg(op0.id(), 0);
1252                    emit_op!();
1253                }
1254            }
1255
1256            Encoding::BaseBfi => {
1257                let op_data = &BASE_BFI[encoding_index];
1258                if isign4 == enc_ops!(Reg, Reg, Imm, Imm) {
1259                    let mut x = 0;
1260                    if !check_gp_typex(op0, 3, &mut x) {
1261                        self.last_error = Some(AsmError::InvalidOperand);
1262                        return;
1263                    }
1264
1265                    if !check_signature!(op0, op1) {
1266                        self.last_error = Some(AsmError::InvalidInstruction);
1267                        return;
1268                    }
1269
1270                    if !check_gp_id2(op0, op1, 63) {
1271                        self.last_error = Some(AsmError::InvalidOperand);
1272                        return;
1273                    }
1274
1275                    let lsb = op2.as_::<Imm>().value() as u64;
1276                    let width = op3.as_::<Imm>().value() as u64;
1277                    let op_size = if x != 0 { 64 } else { 32 };
1278
1279                    if lsb >= op_size as u64 || width == 0 || width > op_size as u64 {
1280                        self.last_error = Some(AsmError::InvalidOperand);
1281                        return;
1282                    }
1283
1284                    let imm_l = 0u32.wrapping_sub(lsb as u32) & (op_size as u32 - 1);
1285                    let imm_w = width as u32 - 1;
1286
1287                    st.opcode.reset(op_data.opcode);
1288                    st.opcode.add_imm(x, 31);
1289                    st.opcode.add_imm(x, 22);
1290                    st.opcode.add_imm(imm_l, 16);
1291                    st.opcode.add_imm(imm_w, 10);
1292                    st.opcode.add_reg(op1.id(), 5);
1293                    st.opcode.add_reg(op0.id(), 0);
1294                    emit_op!();
1295                }
1296            }
1297
1298            Encoding::BaseBfm => {
1299                let op_data = &BASE_BFM[encoding_index];
1300                if isign4 == enc_ops!(Reg, Reg, Imm, Imm) {
1301                    let mut x = 0;
1302                    if !check_gp_typex(op0, 3, &mut x) {
1303                        self.last_error = Some(AsmError::InvalidInstruction);
1304                        return;
1305                    }
1306
1307                    if !check_signature!(op0, op1) {
1308                        self.last_error = Some(AsmError::InvalidInstruction);
1309                        return;
1310                    }
1311
1312                    if !check_gp_id2(op0, op1, 63) {
1313                        self.last_error = Some(AsmError::InvalidOperand);
1314                        return;
1315                    }
1316
1317                    let imm_r = op2.as_::<Imm>().value() as u64;
1318                    let imm_s = op3.as_::<Imm>().value() as u64;
1319                    let op_size = if x != 0 { 64 } else { 32 };
1320
1321                    if (imm_r | imm_s) >= op_size as u64 {
1322                        self.last_error = Some(AsmError::InvalidOperand);
1323                        return;
1324                    }
1325
1326                    st.opcode.reset(op_data.opcode);
1327                    st.opcode.add_imm(x, 31);
1328                    st.opcode.add_imm(x, 22);
1329                    st.opcode.add_imm(imm_r as u32, 16);
1330                    st.opcode.add_imm(imm_s as u32, 10);
1331                    st.opcode.add_reg(op1.id(), 5);
1332                    st.opcode.add_reg(op0.id(), 0);
1333                    emit_op!();
1334                }
1335            }
1336
1337            Encoding::BaseBfx => {
1338                let op_data = &BASE_BFX[encoding_index];
1339                if isign4 == enc_ops!(Reg, Reg, Imm, Imm) {
1340                    let mut x = 0;
1341                    if !check_gp_typex(op0, 3, &mut x) {
1342                        self.last_error = Some(AsmError::InvalidInstruction);
1343                        return;
1344                    }
1345
1346                    if !check_signature!(op0, op1) {
1347                        self.last_error = Some(AsmError::InvalidInstruction);
1348                        return;
1349                    }
1350
1351                    if !check_gp_id2(op0, op1, 63) {
1352                        self.last_error = Some(AsmError::InvalidOperand);
1353                        return;
1354                    }
1355
1356                    let lsb = op2.as_::<Imm>().value() as u64;
1357                    let width = op3.as_::<Imm>().value() as u64;
1358                    let op_size = if x != 0 { 64 } else { 32 };
1359
1360                    if lsb >= op_size as u64 || width == 0 || width > op_size as u64 {
1361                        self.last_error = Some(AsmError::InvalidOperand);
1362                        return;
1363                    }
1364
1365                    let lsb32 = lsb as u32;
1366                    let width32 = lsb32 + width as u32 - 1;
1367
1368                    if width32 >= op_size as u32 {
1369                        self.last_error = Some(AsmError::InvalidOperand);
1370                        return;
1371                    }
1372
1373                    st.opcode.reset(op_data.opcode);
1374                    st.opcode.add_imm(x, 31);
1375                    st.opcode.add_imm(x, 22);
1376                    st.opcode.add_imm(lsb32, 16);
1377                    st.opcode.add_imm(width32, 10);
1378                    st.opcode.add_reg(op1.id(), 5);
1379                    st.opcode.add_reg(op0.id(), 0);
1380                    emit_op!();
1381                }
1382            }
1383
1384            Encoding::BaseExtend => {
1385                let op_data = &BASE_EXTEND[encoding_index];
1386
1387                if isign4 == enc_ops!(Reg, Reg) {
1388                    let mut x = 0;
1389                    if !check_gp_typex(op0, op_data.reg_type, &mut x) {
1390                        self.last_error = Some(AsmError::InvalidOperand);
1391                        return;
1392                    }
1393
1394                    if !op1.as_::<Reg>().is_gp32() {
1395                        self.last_error = Some(AsmError::InvalidOperand);
1396                        return;
1397                    }
1398
1399                    if !check_gp_id2(op0, op1, 63) {
1400                        self.last_error = Some(AsmError::InvalidOperand);
1401                        return;
1402                    }
1403
1404                    st.opcode.reset(op_data.opcode());
1405                    st.opcode.add_imm(x, 31);
1406                    st.opcode.add_imm(x, 22);
1407                    st.opcode.add_reg(op1.id(), 5);
1408                    st.opcode.add_reg(op0.id(), 0);
1409                    emit_op!();
1410                }
1411            }
1412
1413            Encoding::BaseExtract => {
1414                let op_data = &BASE_EXTRACT[encoding_index];
1415
1416                if isign4 == enc_ops!(Reg, Reg, Reg, Imm) {
1417                    let mut x = 0;
1418                    if !check_gp_typex(op0, 3, &mut x) {
1419                        self.last_error = Some(AsmError::InvalidInstruction);
1420                        return;
1421                    }
1422
1423                    if !check_signature!(op0, op1, op2) {
1424                        self.last_error = Some(AsmError::InvalidInstruction);
1425                        return;
1426                    }
1427
1428                    if !check_gp_id3(op0, op1, op2, 63) {
1429                        self.last_error = Some(AsmError::InvalidOperand);
1430                        return;
1431                    }
1432
1433                    let lsb = op3.as_::<Imm>().value() as u64;
1434                    let op_size = if x != 0 { 64 } else { 32 };
1435
1436                    if lsb >= op_size as u64 {
1437                        self.last_error = Some(AsmError::InvalidOperand);
1438                        return;
1439                    }
1440
1441                    st.opcode.reset(op_data.opcode);
1442                    st.opcode.add_imm(x, 31);
1443                    st.opcode.add_imm(x, 22);
1444                    st.opcode.add_reg(op2.id(), 16);
1445                    st.opcode.add_imm(lsb as u32, 10);
1446                    st.opcode.add_reg(op1.id(), 5);
1447                    st.opcode.add_reg(op0.id(), 0);
1448                    emit_op!();
1449                }
1450            }
1451
1452            Encoding::BaseRev => {
1453                if isign4 == enc_ops!(Reg, Reg) {
1454                    let mut x = 0;
1455                    if !check_gp_typex(op0, 3, &mut x) {
1456                        self.last_error = Some(AsmError::InvalidInstruction);
1457                        return;
1458                    }
1459
1460                    if !check_signature!(op0, op1) {
1461                        self.last_error = Some(AsmError::InvalidInstruction);
1462                        return;
1463                    }
1464
1465                    if !check_gp_id2(op0, op1, 63) {
1466                        self.last_error = Some(AsmError::InvalidOperand);
1467                        return;
1468                    }
1469
1470                    st.opcode.reset(0b01011010110000000000100000000000);
1471                    st.opcode.add_imm(x, 31);
1472                    st.opcode.add_imm(x, 10);
1473                    st.opcode.add_reg(op1.id(), 5);
1474                    st.opcode.add_reg(op0.id(), 0);
1475                    emit_op!();
1476                }
1477            }
1478
1479            Encoding::BaseShift => {
1480                let op_data = &BASE_SHIFT[encoding_index];
1481
1482                let mut x = 0;
1483                if !check_gp_typex(op0, 3, &mut x) {
1484                    self.last_error = Some(AsmError::InvalidInstruction);
1485                    return;
1486                }
1487
1488                if isign4 == enc_ops!(Reg, Reg, Reg) {
1489                    if !check_signature!(op0, op1, op2) {
1490                        self.last_error = Some(AsmError::InvalidInstruction);
1491                        return;
1492                    }
1493
1494                    if !check_gp_id3(op0, op1, op2, 63) {
1495                        self.last_error = Some(AsmError::InvalidOperand);
1496                        return;
1497                    }
1498
1499                    st.opcode.reset(op_data.register_op());
1500                    st.opcode.add_imm(x, 31);
1501                    st.opcode.add_reg(op2.id(), 16);
1502                    st.opcode.add_reg(op1.id(), 5);
1503                    st.opcode.add_reg(op0.id(), 0);
1504                    emit_op!();
1505                }
1506
1507                if isign4 == enc_ops!(Reg, Reg, Imm) && op_data.immediate_op != 0 {
1508                    if !check_signature!(op0, op1) {
1509                        self.last_error = Some(AsmError::InvalidInstruction);
1510                        return;
1511                    }
1512
1513                    if !check_gp_id2(op0, op1, 63) {
1514                        self.last_error = Some(AsmError::InvalidOperand);
1515                        return;
1516                    }
1517
1518                    let imm_r = op2.as_::<Imm>().value() as u64;
1519                    let op_size = if x != 0 { 64 } else { 32 };
1520
1521                    if imm_r >= op_size as u64 {
1522                        self.last_error = Some(AsmError::InvalidOperand);
1523                        return;
1524                    }
1525
1526                    st.opcode.reset(op_data.immediate_op());
1527                    st.opcode.add_imm(x, 31);
1528                    st.opcode.add_imm(x, 22);
1529                    st.opcode.add_reg(op1.id(), 5);
1530                    st.opcode.add_reg(op0.id(), 0);
1531
1532                    if st.opcode.get() & (1 << 10) != 0 {
1533                        st.opcode.add_imm(x, 15);
1534                        st.opcode.add_imm(imm_r as u32, 16);
1535                        emit_op!();
1536                    }
1537
1538                    if op_data.ror == 0 {
1539                        let ubfm_imm_r = (0u32).wrapping_sub(imm_r as u32) & (op_size as u32 - 1);
1540                        let ubfm_imm_s = op_size as u32 - 1 - imm_r as u32;
1541
1542                        st.opcode.add_imm(ubfm_imm_r, 16);
1543                        st.opcode.add_imm(ubfm_imm_s, 10);
1544                        emit_op!();
1545                    } else {
1546                        st.opcode.add_imm(imm_r as u32, 10);
1547                        st.opcode.add_reg(op1.id(), 16);
1548                        emit_op!();
1549                    }
1550                }
1551            }
1552
1553            Encoding::BaseCCmp => {
1554                let op_data = &BASE_C_CMP[encoding_index];
1555
1556                if isign4 == enc_ops!(Reg, Reg, Imm, Imm) || isign4 == enc_ops!(Reg, Imm, Imm, Imm)
1557                {
1558                    let mut x = 0;
1559                    if !check_gp_typex(op0, 3, &mut x) {
1560                        self.last_error = Some(AsmError::InvalidOperand);
1561                        return;
1562                    }
1563
1564                    if !check_gp_id(op0, 31) {
1565                        self.last_error = Some(AsmError::InvalidOperand);
1566                        return;
1567                    }
1568
1569                    let nzcv = op2.as_::<Imm>().value() as u64;
1570                    let cond = op3.as_::<Imm>().value() as u64;
1571
1572                    if (nzcv | cond) > 0xF {
1573                        self.last_error = Some(AsmError::TooLarge);
1574                        return;
1575                    }
1576
1577                    st.opcode.reset(op_data.opcode);
1578                    st.opcode.add_imm(x, 31);
1579                    st.opcode
1580                        .add_imm(cond_code_to_opcode_field(cond as u32), 12);
1581                    st.opcode.add_imm(nzcv as u32, 0);
1582
1583                    if isign4 == enc_ops!(Reg, Reg, Imm, Imm) {
1584                        if !check_signature!(op0, op1) {
1585                            self.last_error = Some(AsmError::InvalidInstruction);
1586                            return;
1587                        }
1588
1589                        if !check_gp_id(op1, 31) {
1590                            self.last_error = Some(AsmError::InvalidOperand);
1591                            return;
1592                        }
1593
1594                        st.opcode.add_reg(op1.id(), 16);
1595                        st.opcode.add_reg(op0.id(), 5);
1596                        emit_op!();
1597                    } else {
1598                        let imm5 = op1.as_::<Imm>().value() as u64;
1599                        if imm5 > 0x1F {
1600                            self.last_error = Some(AsmError::TooLarge);
1601                            return;
1602                        }
1603
1604                        st.opcode.add_imm(1, 11);
1605                        st.opcode.add_imm(imm5 as u32, 16);
1606                        st.opcode.add_reg(op0.id(), 5);
1607                        emit_op!();
1608                    }
1609                }
1610            }
1611
1612            Encoding::BaseCInc => {
1613                let op_data = &BASE_C_INC[encoding_index];
1614
1615                if isign4 == enc_ops!(Reg, Reg, Imm) {
1616                    let mut x = 0;
1617                    if !check_gp_typex2(op0, op1, 3, &mut x) {
1618                        self.last_error = Some(AsmError::InvalidInstruction);
1619                        return;
1620                    }
1621
1622                    if !check_gp_id2(op0, op1, 31) {
1623                        self.last_error = Some(AsmError::InvalidOperand);
1624                        return;
1625                    }
1626
1627                    let cond = op2.as_::<Imm>().value() as u64;
1628                    if cond.wrapping_sub(2) > 0xE {
1629                        self.last_error = Some(AsmError::TooLarge);
1630                        return;
1631                    }
1632
1633                    st.opcode.reset(op_data.opcode);
1634                    st.opcode.add_imm(x, 31);
1635                    st.opcode.add_reg(op1.id(), 16);
1636                    st.opcode
1637                        .add_imm(cond_code_to_opcode_field((cond as u32) ^ 1), 12);
1638                    st.opcode.add_reg(op1.id(), 5);
1639                    st.opcode.add_reg(op0.id(), 0);
1640                    emit_op!();
1641                }
1642            }
1643
1644            Encoding::BaseCSel => {
1645                let op_data = &BASE_C_SEL[encoding_index];
1646
1647                if isign4 == enc_ops!(Reg, Reg, Reg, Imm) {
1648                    let mut x = 0;
1649                    if !check_gp_typex(op0, 3, &mut x) {
1650                        self.last_error = Some(AsmError::InvalidInstruction);
1651                        return;
1652                    }
1653
1654                    if !check_signature!(op0, op1, op2) {
1655                        self.last_error = Some(AsmError::InvalidInstruction);
1656                        return;
1657                    }
1658
1659                    // `Rm` (op2) may be `XZR`/`WZR` (id 63, e.g. a `CSEL`
1660                    // zeroing idiom); it encodes as 31 like `SP`.
1661                    if !check_gp_id2(op0, op1, 31) || !check_gp_id(op2, 63) {
1662                        self.last_error = Some(AsmError::InvalidOperand);
1663                        return;
1664                    }
1665
1666                    let cond = op3.as_::<Imm>().value() as u64;
1667                    if cond > 0xF {
1668                        self.last_error = Some(AsmError::TooLarge);
1669                        return;
1670                    }
1671
1672                    st.opcode.reset(op_data.opcode);
1673                    st.opcode.add_imm(x, 31);
1674                    st.opcode.add_reg(op2.id(), 16);
1675                    st.opcode
1676                        .add_imm(cond_code_to_opcode_field(cond as u32), 12);
1677                    st.opcode.add_reg(op1.id(), 5);
1678                    st.opcode.add_reg(op0.id(), 0);
1679                    emit_op!();
1680                }
1681            }
1682
1683            Encoding::BaseCSet => {
1684                let op_data = &BASE_C_SET[encoding_index];
1685
1686                if isign4 == enc_ops!(Reg, Imm) {
1687                    let mut x = 0;
1688                    if !check_gp_typex(op0, 3, &mut x) {
1689                        self.last_error = Some(AsmError::InvalidInstruction);
1690                        return;
1691                    }
1692
1693                    if !check_gp_id(op0, 31) {
1694                        self.last_error = Some(AsmError::InvalidOperand);
1695                        return;
1696                    }
1697
1698                    let cond = op1.as_::<Imm>().value() as u64;
1699                    if cond.wrapping_sub(2) >= 0xE {
1700                        self.last_error = Some(AsmError::TooLarge);
1701                        return;
1702                    }
1703
1704                    st.opcode.reset(op_data.opcode);
1705                    st.opcode.add_imm(x, 31);
1706                    st.opcode
1707                        .add_imm(cond_code_to_opcode_field((cond as u32) ^ 1), 12);
1708                    st.opcode.add_reg(op0.id(), 0);
1709                    emit_op!();
1710                }
1711            }
1712
1713            Encoding::BaseMinMax => {
1714                let op_data = &BASE_MIN_MAX[encoding_index];
1715
1716                if isign4 == enc_ops!(Reg, Reg, Reg) {
1717                    let mut x = 0;
1718                    if !check_gp_typex(op0, 3, &mut x) {
1719                        self.last_error = Some(AsmError::InvalidInstruction);
1720                        return;
1721                    }
1722
1723                    if !check_signature!(op0, op1, op2) {
1724                        self.last_error = Some(AsmError::InvalidInstruction);
1725                        return;
1726                    }
1727
1728                    st.opcode.reset(op_data.register_op);
1729                    st.opcode.add_imm(x, 31);
1730                    st.opcode.add_reg(op2.id(), 16);
1731                    st.opcode.add_reg(op1.id(), 5);
1732                    st.opcode.add_reg(op0.id(), 0);
1733                    emit_op!();
1734                }
1735
1736                if isign4 == enc_ops!(Reg, Reg, Imm) {
1737                    let mut x = 0;
1738                    if !check_gp_typex(op0, 3, &mut x) {
1739                        self.last_error = Some(AsmError::InvalidInstruction);
1740                        return;
1741                    }
1742
1743                    if !check_signature!(op0, op1) {
1744                        self.last_error = Some(AsmError::InvalidInstruction);
1745                        return;
1746                    }
1747
1748                    let imm = op2.as_::<Imm>().value() as u64;
1749
1750                    if (op_data.immediate_op & (1u32 << 18)) != 0 {
1751                        if imm > 0xFF {
1752                            self.last_error = Some(AsmError::TooLarge);
1753                            return;
1754                        }
1755                    } else {
1756                        if (imm as i64) < -128 || (imm as i64) > 127 {
1757                            self.last_error = Some(AsmError::TooLarge);
1758                            return;
1759                        }
1760                    }
1761
1762                    st.opcode.reset(op_data.immediate_op);
1763                    st.opcode.add_imm(x, 31);
1764                    st.opcode.add_imm((imm & 0xFF) as u32, 10);
1765                    st.opcode.add_reg(op1.id(), 5);
1766                    st.opcode.add_reg(op0.id(), 0);
1767                    emit_op!();
1768                }
1769            }
1770
1771            Encoding::BaseAtDcIcTlbi => {
1772                let op_data = &BASE_AT_DC_IC_TLBI[encoding_index];
1773
1774                if isign4 == enc_ops!(Imm) || isign4 == enc_ops!(Imm, Reg) {
1775                    if op_data.mandatory_reg != 0 && isign4 != enc_ops!(Imm, Reg) {
1776                        self.last_error = Some(AsmError::InvalidInstruction);
1777                        return;
1778                    }
1779
1780                    if op0.as_::<Imm>().value() as u64 > 0x7FFF {
1781                        self.last_error = Some(AsmError::TooLarge);
1782                        return;
1783                    }
1784
1785                    let imm = op0.as_::<Imm>().value() as u32;
1786                    if (imm & op_data.imm_verify_mask) != op_data.imm_verify_data {
1787                        self.last_error = Some(AsmError::InvalidOperand);
1788                        return;
1789                    }
1790
1791                    let mut rt = 31;
1792                    if op1.is_reg() {
1793                        if !op1.as_::<Reg>().is_gp64() {
1794                            self.last_error = Some(AsmError::InvalidInstruction);
1795                            return;
1796                        }
1797
1798                        if !check_gp_id(op1, 63) {
1799                            self.last_error = Some(AsmError::InvalidOperand);
1800                            return;
1801                        }
1802
1803                        rt = op1.id() & 31;
1804                    }
1805
1806                    st.opcode.reset(0b11010101000010000000000000000000);
1807                    st.opcode.add_imm(imm, 5);
1808                    st.opcode.add_reg(rt, 0);
1809                    emit_op!();
1810                }
1811            }
1812
1813            Encoding::BaseMrs => {
1814                if isign4 == enc_ops!(Reg, Imm) {
1815                    if !op0.as_::<Reg>().is_gp64() {
1816                        self.last_error = Some(AsmError::InvalidInstruction);
1817                        return;
1818                    }
1819
1820                    if !check_gp_id(op0, 63) {
1821                        self.last_error = Some(AsmError::InvalidOperand);
1822                        return;
1823                    }
1824
1825                    if op1.as_::<Imm>().value() as u64 > 0xFFFF {
1826                        self.last_error = Some(AsmError::TooLarge);
1827                        return;
1828                    }
1829
1830                    let imm = op1.as_::<Imm>().value() as u32;
1831                    if (imm & (1 << 15)) == 0 {
1832                        self.last_error = Some(AsmError::InvalidOperand);
1833                        return;
1834                    }
1835
1836                    st.opcode.reset(0b11010101001100000000000000000000);
1837                    st.opcode.add_imm(imm, 5);
1838                    st.opcode.add_reg(op0.id(), 0);
1839                    emit_op!();
1840                }
1841            }
1842
1843            Encoding::BaseMsr => {
1844                if isign4 == enc_ops!(Imm, Reg) {
1845                    if !op1.as_::<Reg>().is_gp64() {
1846                        self.last_error = Some(AsmError::InvalidInstruction);
1847                        return;
1848                    }
1849
1850                    if op0.as_::<Imm>().value() as u64 > 0xFFFF {
1851                        self.last_error = Some(AsmError::TooLarge);
1852                        return;
1853                    }
1854
1855                    let imm = op0.as_::<Imm>().value() as u32;
1856                    if (imm & (1 << 15)) == 0 {
1857                        self.last_error = Some(AsmError::InvalidOperand);
1858                        return;
1859                    }
1860
1861                    if !check_gp_id(op1, 63) {
1862                        self.last_error = Some(AsmError::InvalidOperand);
1863                        return;
1864                    }
1865
1866                    st.opcode.reset(0b11010101000100000000000000000000);
1867                    st.opcode.add_imm(imm, 5);
1868                    st.opcode.add_reg(op1.id(), 0);
1869                    emit_op!();
1870                }
1871
1872                if isign4 == enc_ops!(Imm, Imm) {
1873                    if op0.as_::<Imm>().value() as u64 > 0x1F {
1874                        self.last_error = Some(AsmError::TooLarge);
1875                        return;
1876                    }
1877
1878                    if op1.as_::<Imm>().value() as u64 > 0xF {
1879                        self.last_error = Some(AsmError::TooLarge);
1880                        return;
1881                    }
1882
1883                    let op = op0.as_::<Imm>().value() as u32;
1884                    let crm = op1.as_::<Imm>().value() as u32;
1885
1886                    let op1_val = op >> 3;
1887                    let op2_val = op & 0x7;
1888
1889                    st.opcode.reset(0b11010101000000000100000000011111);
1890                    st.opcode.add_imm(op1_val, 16);
1891                    st.opcode.add_imm(crm, 8);
1892                    st.opcode.add_imm(op2_val, 5);
1893                    emit_op!();
1894                }
1895            }
1896
1897            Encoding::BaseSys => {
1898                if isign4 == enc_ops!(Imm, Imm, Imm, Imm) {
1899                    if op0.as_::<Imm>().value() as u64 > 0x7
1900                        || op1.as_::<Imm>().value() as u64 > 0xF
1901                        || op2.as_::<Imm>().value() as u64 > 0xF
1902                        || op3.as_::<Imm>().value() as u64 > 0x7
1903                    {
1904                        self.last_error = Some(AsmError::TooLarge);
1905                        return;
1906                    }
1907
1908                    let op1_val = op0.as_::<Imm>().value() as u32;
1909                    let crn = op1.as_::<Imm>().value() as u32;
1910                    let crm = op2.as_::<Imm>().value() as u32;
1911                    let op2_val = op3.as_::<Imm>().value() as u32;
1912                    let mut rt = 31;
1913
1914                    let op4 = *ops.get(4).unwrap_or(&NOREG);
1915                    if op4.is_reg() {
1916                        if !op4.as_::<Reg>().is_gp64() {
1917                            self.last_error = Some(AsmError::InvalidInstruction);
1918                            return;
1919                        }
1920
1921                        if !check_gp_id(op4, 63) {
1922                            self.last_error = Some(AsmError::InvalidOperand);
1923                            return;
1924                        }
1925
1926                        rt = op4.id() & 31;
1927                    } else if !op4.is_none() {
1928                        self.last_error = Some(AsmError::InvalidInstruction);
1929                        return;
1930                    }
1931
1932                    st.opcode.reset(0b11010101000010000000000000000000);
1933                    st.opcode.add_imm(op1_val, 16);
1934                    st.opcode.add_imm(crn, 12);
1935                    st.opcode.add_imm(crm, 8);
1936                    st.opcode.add_imm(op2_val, 5);
1937                    st.opcode.add_reg(rt, 0);
1938                    emit_op!();
1939                }
1940            }
1941
1942            Encoding::BaseBranchReg => {
1943                let op_data = &BASE_BRANCH_REG[encoding_index];
1944                if isign4 == enc_ops!(Reg) {
1945                    if !op0.as_::<Reg>().is_gp64() {
1946                        self.last_error = Some(AsmError::InvalidInstruction);
1947                        return;
1948                    }
1949
1950                    if !check_gp_id(op0, 63) {
1951                        self.last_error = Some(AsmError::InvalidOperand);
1952                        return;
1953                    }
1954
1955                    st.opcode.reset(op_data.opcode);
1956                    st.opcode.add_reg(op0.id(), 5);
1957                    emit_op!();
1958                }
1959            }
1960
1961            Encoding::BaseBranchRel => {
1962                let op_data = &BASE_BRANCH_REL[encoding_index];
1963                if isign4 == enc_ops!(Label) || isign4 == enc_ops!(Imm) {
1964                    st.opcode.reset(op_data.opcode);
1965                    st.rm_rel = *op0;
1966
1967                    if inst_cc as u32 != 0 || (st.opcode.0 & (1 << 30)) != 0 {
1968                        if st.opcode.has_x() {
1969                            self.last_error = Some(AsmError::InvalidInstruction);
1970                            return;
1971                        }
1972
1973                        st.opcode.0 |= 1 << 30;
1974                        st.opcode
1975                            .add_imm(cond_code_to_opcode_field(inst_cc as u32), 0);
1976                        st.offset_format
1977                            .reset_to_imm_type(OffsetType::SignedOffset, 4, 5, 19, 2);
1978                        st.rm_rel = *op0;
1979                        emit_rel!();
1980                    }
1981
1982                    st.offset_format
1983                        .reset_to_imm_type(OffsetType::SignedOffset, 4, 0, 26, 2);
1984                    st.rm_rel = *op0;
1985                    emit_rel!();
1986                }
1987            }
1988
1989            Encoding::BaseBranchCmp => {
1990                let op_data = &BASE_BRANCH_CMP[encoding_index];
1991                if isign4 == enc_ops!(Reg, Label) || isign4 == enc_ops!(Reg, Imm) {
1992                    let mut x = 0;
1993                    if !check_gp_typex(op0, 3, &mut x) {
1994                        self.last_error = Some(AsmError::InvalidInstruction);
1995                        return;
1996                    }
1997
1998                    if !check_gp_id(op0, 31) {
1999                        self.last_error = Some(AsmError::InvalidOperand);
2000                        return;
2001                    }
2002
2003                    st.opcode.reset(op_data.opcode);
2004                    st.opcode.add_imm(x, 31);
2005                    st.opcode.add_reg(op0.id(), 0);
2006                    st.offset_format
2007                        .reset_to_imm_type(OffsetType::SignedOffset, 4, 5, 19, 2);
2008
2009                    st.rm_rel = *op1;
2010                    emit_rel!();
2011                }
2012            }
2013
2014            Encoding::BaseBranchTst => {
2015                let op_data = &BASE_BRANCH_TST[encoding_index];
2016                if isign4 == enc_ops!(Reg, Imm, Label) || isign4 == enc_ops!(Reg, Imm, Imm) {
2017                    let mut x = 0;
2018                    if !check_gp_typex(op0, 3, &mut x) {
2019                        self.last_error = Some(AsmError::InvalidInstruction);
2020                        return;
2021                    }
2022
2023                    if !check_gp_id(op0, 31) {
2024                        self.last_error = Some(AsmError::InvalidOperand);
2025                        return;
2026                    }
2027
2028                    let mut imm = op1.as_::<Imm>().value() as u64;
2029
2030                    st.opcode.reset(op_data.opcode);
2031                    if imm >= 32 {
2032                        if x == 0 {
2033                            self.last_error = Some(AsmError::InvalidOperand);
2034                            return;
2035                        }
2036                        st.opcode.add_imm(x, 31);
2037                        imm &= 0x1F;
2038                    }
2039
2040                    st.opcode.add_reg(op0.id(), 0);
2041                    st.opcode.add_imm(imm as u32, 19);
2042                    st.offset_format
2043                        .reset_to_imm_type(OffsetType::SignedOffset, 4, 5, 14, 2);
2044
2045                    st.rm_rel = *op2;
2046                    emit_rel!();
2047                }
2048            }
2049
2050            Encoding::BasePrfm => {
2051                let op_data = &BASE_PRFM[encoding_index];
2052                if isign4 == enc_ops!(Imm, Mem) {
2053                    let m = op1.as_::<Mem>();
2054                    st.rm_rel = *op1;
2055
2056                    let imm_shift = 3u32;
2057
2058                    if op0.as_::<Imm>().value() as u64 > 0x1F {
2059                        self.last_error = Some(AsmError::TooLarge);
2060                        return;
2061                    }
2062
2063                    let offset = m.offset();
2064                    let prfop = op0.as_::<Imm>().value() as u32;
2065
2066                    if m.has_base_reg() {
2067                        if m.has_index() {
2068                            let opt = SHIFT_OP_TO_LD_ST_OP_MAP[m.shift_op() as usize];
2069                            if opt == 0xFF {
2070                                self.last_error = Some(AsmError::InvalidOperand);
2071                                return;
2072                            }
2073
2074                            let shift = m.shift();
2075                            let s = if shift != 0 { 1 } else { 0 };
2076
2077                            if s != 0 && shift != imm_shift {
2078                                self.last_error = Some(AsmError::InvalidOperand);
2079                                return;
2080                            }
2081
2082                            st.opcode.reset((op_data.register_op as u32) << 21);
2083                            st.opcode.add_imm(opt as u32, 13);
2084                            st.opcode.add_imm(s, 12);
2085                            st.opcode.0 |= 1 << 11;
2086                            st.opcode.add_imm(prfop, 0);
2087                            st.opcode.add_reg(m.base_id(), 5);
2088                            st.opcode.add_reg(m.index_id(), 16);
2089                            emit_op!();
2090                        }
2091
2092                        let offset32 = offset as i32;
2093                        let imm12 = (offset32 as u32) >> imm_shift;
2094
2095                        if imm12 < (1 << 12) && ((imm12 << imm_shift) as i32) == offset32 {
2096                            st.opcode.reset((op_data.s_offset_op as u32) << 22);
2097                            st.opcode.add_imm(imm12, 10);
2098                            st.opcode.add_imm(prfop, 0);
2099                            st.opcode.add_reg(m.base_id(), 5);
2100                            emit_op!();
2101                        }
2102
2103                        if offset32 >= -256 && offset32 < 256 {
2104                            st.opcode.reset((op_data.u_offset_op as u32) << 21);
2105                            st.opcode.add_imm((offset32 as u32) & 0x1FF, 12);
2106                            st.opcode.add_imm(prfop, 0);
2107                            st.opcode.add_reg(m.base_id(), 5);
2108                            emit_op!();
2109                        }
2110
2111                        self.last_error = Some(AsmError::InvalidOperand);
2112                        return;
2113                    } else {
2114                        st.opcode.reset((op_data.literal_op as u32) << 24);
2115                        st.opcode.add_imm(prfop, 0);
2116                        st.offset_format
2117                            .reset_to_imm_type(OffsetType::SignedOffset, 4, 5, 19, 2);
2118                        st.rm_rel = *op1;
2119                        emit_rel!();
2120                    }
2121                }
2122            }
2123
2124            Encoding::BaseLdSt => {
2125                let op_data = &BASE_LD_ST[encoding_index];
2126                if isign4 == enc_ops!(Reg, Mem) {
2127                    let m = op1.as_::<Mem>();
2128                    st.rm_rel = *op1;
2129
2130                    let mut x = 0;
2131                    if !check_gp_typex(op0, op_data.reg_type, &mut x) {
2132                        self.last_error = Some(AsmError::InvalidOperand);
2133                        return;
2134                    }
2135
2136                    if !check_gp_id(op0, 31) {
2137                        self.last_error = Some(AsmError::InvalidOperand);
2138                        return;
2139                    }
2140
2141                    let x_shift_mask = if op_data.u_offset_shift == 2 { 1 } else { 0 };
2142                    let imm_shift = (op_data.u_offset_shift as u32) + (x & x_shift_mask);
2143
2144                    let offset = m.offset();
2145
2146                    if m.has_base_reg() {
2147                        if m.has_index() {
2148                            if m.is_pre_or_post() {
2149                                self.last_error = Some(AsmError::InvalidOperand);
2150                                return;
2151                            }
2152                            let opt = SHIFT_OP_TO_LD_ST_OP_MAP[m.shift_op() as usize];
2153                            if opt == 0xFF {
2154                                self.last_error = Some(AsmError::InvalidOperand);
2155                                return;
2156                            }
2157
2158                            let shift = m.shift();
2159                            let s = if shift != 0 { 1 } else { 0 };
2160
2161                            if s != 0 && shift != imm_shift {
2162                                self.last_error = Some(AsmError::InvalidOperand);
2163                                return;
2164                            }
2165
2166                            st.opcode.reset((op_data.register_op as u32) << 21);
2167                            st.opcode.xor_imm(x, op_data.x_offset as u32);
2168                            st.opcode.add_imm(opt as u32, 13);
2169                            st.opcode.add_imm(s, 12);
2170                            st.opcode.0 |= 1 << 11;
2171                            st.opcode.add_reg(op0.id(), 0);
2172                            st.opcode.add_reg(m.base_id(), 5);
2173                            st.opcode.add_reg(m.index_id(), 16);
2174                            emit_op!();
2175                        }
2176
2177                        let offset32 = offset as i32;
2178                        let imm12 = (offset32 as u32) >> imm_shift;
2179
2180                        // Unsigned-offset form has no writeback: never use
2181                        // it for pre/post-indexed operands.
2182                        if m.is_fixed_offset()
2183                            && imm12 < (1 << 12)
2184                            && ((imm12 << imm_shift) as i32) == offset32
2185                        {
2186                            st.opcode.reset((op_data.u_offset_op as u32) << 22);
2187                            st.opcode.xor_imm(x, op_data.x_offset as u32);
2188                            st.opcode.add_imm(imm12, 10);
2189                            st.opcode.add_reg(op0.id(), 0);
2190                            st.opcode.add_reg(m.base_id(), 5);
2191                            emit_op!();
2192                        }
2193
2194                        if offset32 >= -256 && offset32 < 256 {
2195                            // Pre/post-indexed forms share the base opcode
2196                            // with bit 24 clear and carry the mode in bits
2197                            // [11:10] (`11` pre, `01` post); the plain
2198                            // path below keeps its historical encoding.
2199                            let indexed = match m.offset_mode() {
2200                                OffsetMode::PreIndex => Some(0b11),
2201                                OffsetMode::PostIndex => Some(0b01),
2202                                _ => None,
2203                            };
2204                            if let Some(mode) = indexed {
2205                                st.opcode
2206                                    .reset(((op_data.u_offset_op as u32) << 22) & !(1 << 24));
2207                                st.opcode.xor_imm(x, op_data.x_offset as u32);
2208                                st.opcode.add_imm((offset32 as u32) & 0x1FF, 12);
2209                                st.opcode.add_imm(mode, 10);
2210                                st.opcode.add_reg(op0.id(), 0);
2211                                st.opcode.add_reg(m.base_id(), 5);
2212                                emit_op!();
2213                            } else {
2214                                st.opcode.reset((op_data.u_offset_op as u32) << 22);
2215                                st.opcode.xor_imm(x, op_data.x_offset as u32);
2216                                st.opcode.add_imm((offset32 as u32) & 0x1FF, 12);
2217                                st.opcode.add_reg(op0.id(), 0);
2218                                st.opcode.add_reg(m.base_id(), 5);
2219                                emit_op!();
2220                            }
2221                        }
2222
2223                        self.last_error = Some(AsmError::InvalidOperand);
2224                        return;
2225                    } else {
2226                        if op_data.literal_op == 0 {
2227                            self.last_error = Some(AsmError::InvalidInstruction);
2228                            return;
2229                        }
2230
2231                        st.opcode.reset((op_data.literal_op as u32) << 24);
2232                        st.opcode.xor_imm(x, op_data.x_offset);
2233                        st.opcode.add_reg(op0.id(), 0);
2234                        st.offset_format
2235                            .reset_to_imm_type(OffsetType::Ldr, 4, 5, 19, 2);
2236                        emit_rel!();
2237                    }
2238                }
2239            }
2240
2241            Encoding::BaseLdpStp => {
2242                let op_data = &BASE_LDP_STP[encoding_index];
2243                if isign4 == enc_ops!(Reg, Reg, Mem) {
2244                    let m = op2.as_::<Mem>();
2245                    st.rm_rel = *op2;
2246
2247                    let mut x = 0;
2248                    if !check_gp_typex2(op0, op1, op_data.reg_type, &mut x) {
2249                        self.last_error = Some(AsmError::InvalidOperand);
2250                        return;
2251                    }
2252
2253                    if !check_gp_id2(op0, op1, 31) {
2254                        self.last_error = Some(AsmError::InvalidOperand);
2255                        return;
2256                    }
2257
2258                    let offset_shift = op_data.offset_shift as u32 + x;
2259                    let offset32 = (m.offset_lo32() as i32) >> offset_shift;
2260
2261                    if (offset32 as u32) << offset_shift != m.offset_lo32() as u32 {
2262                        self.last_error = Some(AsmError::InvalidOperand);
2263                        return;
2264                    }
2265
2266                    const I7_MAX: i32 = (1 << 6) - 1;
2267                    const I7_MIN: i32 = -(1 << 6);
2268
2269                    if offset32 < I7_MIN || offset32 > I7_MAX {
2270                        self.last_error = Some(AsmError::InvalidOperand);
2271                        return;
2272                    }
2273
2274                    if m.is_pre_or_post() && offset32 != 0 {
2275                        if op_data.pre_post_op == 0 {
2276                            self.last_error = Some(AsmError::InvalidInstruction);
2277                            return;
2278                        }
2279
2280                        st.opcode.reset((op_data.pre_post_op as u32) << 22);
2281                        st.opcode.add_imm(m.is_pre_index() as u32, 24);
2282                    } else {
2283                        st.opcode.reset((op_data.offset_op as u32) << 22);
2284                    }
2285                    st.opcode.add_imm(x, op_data.x_offset as u32);
2286                    st.opcode.add_imm((offset32 as u32) & 0x7F, 15);
2287                    st.opcode.add_reg(op1.id(), 10);
2288                    st.opcode.add_reg(op0.id(), 0);
2289                    st.opcode.add_reg(m.base_id(), 5);
2290                    emit_op!();
2291                }
2292            }
2293
2294            Encoding::BaseStx => {
2295                let op_data = &BASE_STX[encoding_index];
2296                if isign4 == enc_ops!(Reg, Reg, Mem) {
2297                    let m = op2.as_::<Mem>();
2298                    let mut x = 0;
2299                    if !op0.as_::<Reg>().is_gp32() || !check_gp_typex(op1, op_data.reg_type, &mut x)
2300                    {
2301                        self.last_error = Some(AsmError::InvalidOperand);
2302                        return;
2303                    }
2304                    if !check_gp_id2(op0, op1, 31) {
2305                        self.last_error = Some(AsmError::InvalidOperand);
2306                        return;
2307                    }
2308                    st.opcode.reset(op_data.opcode());
2309                    st.opcode.add_imm(x, op_data.x_offset as _);
2310                    st.opcode.add_reg(op0.id(), 16);
2311                    st.opcode.add_reg(op1.id(), 0);
2312                    st.rm_rel = *op2;
2313                    st.opcode.add_reg(m.base_id(), 5);
2314                    emit_op!();
2315                }
2316            }
2317
2318            Encoding::BaseLdxp => {
2319                let op_data = &BASE_LDXP[encoding_index];
2320                if isign4 == enc_ops!(Reg, Reg, Mem) {
2321                    let m = op2.as_::<Mem>();
2322                    let mut x = 0;
2323                    if !check_gp_typex(op0, op_data.reg_type, &mut x) || !check_signature!(op0, op1)
2324                    {
2325                        self.last_error = Some(AsmError::InvalidOperand);
2326                        return;
2327                    }
2328                    if !check_gp_id2(op0, op1, 31) {
2329                        self.last_error = Some(AsmError::InvalidOperand);
2330                        return;
2331                    }
2332                    st.opcode.reset(op_data.opcode());
2333                    st.opcode.add_imm(x, op_data.x_offset as _);
2334                    st.opcode.add_reg(op1.id(), 10);
2335                    st.opcode.add_reg(op0.id(), 0);
2336                    st.rm_rel = *op2;
2337                    st.opcode.add_reg(m.base_id(), 5);
2338                    emit_op!();
2339                }
2340            }
2341
2342            Encoding::BaseStxp => {
2343                let op_data = &BASE_STXP[encoding_index];
2344                if isign4 == enc_ops!(Reg, Reg, Reg, Mem) {
2345                    let m = op3.as_::<Mem>();
2346                    let mut x = 0;
2347                    if !op0.as_::<Reg>().is_gp32()
2348                        || !check_gp_typex(op1, op_data.reg_type, &mut x)
2349                        || !check_signature!(op1, op2)
2350                    {
2351                        self.last_error = Some(AsmError::InvalidOperand);
2352                        return;
2353                    }
2354                    if !check_gp_id3(op0, op1, op2, 31) {
2355                        self.last_error = Some(AsmError::InvalidOperand);
2356                        return;
2357                    }
2358                    st.opcode.reset(op_data.opcode());
2359                    st.opcode.add_imm(x, op_data.x_offset as _);
2360                    st.opcode.add_reg(op0.id(), 16);
2361                    st.opcode.add_reg(op2.id(), 10);
2362                    st.opcode.add_reg(op1.id(), 0);
2363                    st.rm_rel = *op3;
2364                    st.opcode.add_reg(m.base_id(), 5);
2365                    emit_op!();
2366                }
2367            }
2368
2369            Encoding::BaseRMNoImm => {
2370                let op_data = &BASE_RM_NO_IMM[encoding_index];
2371                if isign4 == enc_ops!(Reg, Mem) {
2372                    let m = op1.as_::<Mem>();
2373                    let mut x = 0;
2374                    if !check_gp_typex(op0, op_data.reg_type, &mut x) {
2375                        self.last_error = Some(AsmError::InvalidOperand);
2376                        return;
2377                    }
2378                    if !check_gp_id(op0, op_data.reg_hi_id) {
2379                        self.last_error = Some(AsmError::InvalidOperand);
2380                        return;
2381                    }
2382                    st.opcode.reset(op_data.opcode());
2383                    st.opcode.add_imm(x, op_data.x_offset as _);
2384                    st.opcode.add_reg(op0.id(), 0);
2385                    st.rm_rel = *op1;
2386
2387                    emit_mem_base_no_imm_rn5!();
2388                }
2389            }
2390
2391            Encoding::BaseRMSImm9 => {
2392                let op_data = &BASE_RM_SIMM9[encoding_index];
2393                if isign4 == enc_ops!(Reg, Mem) {
2394                    let m = op1.as_::<Mem>();
2395                    let mut x = 0;
2396                    if !check_gp_typex(op0, op_data.reg_type, &mut x) {
2397                        self.last_error = Some(AsmError::InvalidOperand);
2398                        return;
2399                    }
2400                    if !check_gp_id(op0, op_data.reg_hi_id) {
2401                        self.last_error = Some(AsmError::InvalidOperand);
2402                        return;
2403                    }
2404                    if m.has_base_reg() && !m.has_index() {
2405                        let offset32 = m.offset() as i32 >> op_data.imm_shift;
2406                        if (offset32 << op_data.imm_shift) != m.offset() as i32 {
2407                            self.last_error = Some(AsmError::InvalidOperand);
2408                            return;
2409                        }
2410                        if offset32 < -256 || offset32 > 255 {
2411                            self.last_error = Some(AsmError::InvalidOperand);
2412                            return;
2413                        }
2414                        if m.is_fixed_offset() {
2415                            st.opcode.reset(op_data.offset_op());
2416                        } else {
2417                            st.opcode.reset(op_data.pre_post_op());
2418                            st.opcode.xor_imm(m.is_pre_index() as u32, 11);
2419                        }
2420                        st.opcode.xor_imm(x, op_data.x_offset as u32);
2421                        st.opcode.add_imm((offset32 as u32) & 0x1FF, 12);
2422                        st.opcode.add_reg(op0.id(), 0);
2423                        st.opcode.add_reg(m.base_id(), 5);
2424                        emit_op!();
2425                    }
2426                    self.last_error = Some(AsmError::InvalidOperand);
2427                    return;
2428                }
2429            }
2430
2431            Encoding::BaseRMSImm10 => {
2432                let op_data = &BASE_RM_SIMM10[encoding_index];
2433                if isign4 == enc_ops!(Reg, Mem) {
2434                    let m = op1.as_::<Mem>();
2435                    let mut x = 0;
2436                    if !check_gp_typex(op0, op_data.reg_type, &mut x) {
2437                        self.last_error = Some(AsmError::InvalidOperand);
2438                        return;
2439                    }
2440                    if !check_gp_id(op0, op_data.reg_hi_id) {
2441                        self.last_error = Some(AsmError::InvalidOperand);
2442                        return;
2443                    }
2444                    if m.has_base_reg() && !m.has_index() {
2445                        let offset32 = m.offset() as i32 >> op_data.imm_shift;
2446                        if (offset32 << op_data.imm_shift) != m.offset() as i32 {
2447                            self.last_error = Some(AsmError::InvalidOperand);
2448                            return;
2449                        }
2450                        if offset32 < -512 || offset32 > 511 {
2451                            self.last_error = Some(AsmError::InvalidOperand);
2452                            return;
2453                        }
2454                        let offset32 = (offset32 as u32) & 0x3FF;
2455                        st.opcode.reset(op_data.opcode());
2456                        st.opcode.xor_imm(m.is_pre_index() as u32, 11);
2457                        st.opcode.xor_imm(x, op_data.x_offset as u32);
2458                        st.opcode.add_imm(offset32 >> 9, 22);
2459                        st.opcode.add_imm(offset32, 12);
2460                        st.opcode.add_reg(op0.id(), 0);
2461                        st.opcode.add_reg(m.base_id(), 5);
2462                        emit_op!();
2463                    }
2464                    self.last_error = Some(AsmError::InvalidOperand);
2465                    return;
2466                }
2467            }
2468
2469            Encoding::BaseAtomicOp => {
2470                let op_data = &BASE_ATOMIC_OP[encoding_index];
2471                if isign4 == enc_ops!(Reg, Reg, Mem) {
2472                    let m = op2.as_::<Mem>();
2473                    let mut x = 0;
2474                    if !check_gp_typex(op0, op_data.reg_type, &mut x) || !check_signature!(op0, op1)
2475                    {
2476                        self.last_error = Some(AsmError::InvalidOperand);
2477                        return;
2478                    }
2479                    if !check_gp_id2(op0, op1, 31) {
2480                        self.last_error = Some(AsmError::InvalidOperand);
2481                        return;
2482                    }
2483                    st.opcode.reset(op_data.opcode());
2484                    st.opcode.add_imm(x, op_data.x_offset as _);
2485                    st.opcode.add_reg(op0.id(), 16);
2486                    st.opcode.add_reg(op1.id(), 0);
2487                    st.rm_rel = *op2;
2488                    st.opcode.add_reg(m.base_id(), 5);
2489                    emit_op!();
2490                }
2491            }
2492
2493            Encoding::BaseAtomicSt => {
2494                let op_data = &BASE_ATOMIC_ST[encoding_index];
2495                if isign4 == enc_ops!(Reg, Mem) {
2496                    let m = op1.as_::<Mem>();
2497                    let mut x = 0;
2498                    if !check_gp_typex(op0, op_data.reg_type, &mut x) {
2499                        self.last_error = Some(AsmError::InvalidOperand);
2500                        return;
2501                    }
2502                    if !check_gp_id(op0, 31) {
2503                        self.last_error = Some(AsmError::InvalidOperand);
2504                        return;
2505                    }
2506                    st.opcode.reset(op_data.opcode());
2507                    st.opcode.add_imm(x, op_data.x_offset as _);
2508                    st.opcode.add_reg(op0.id(), 16);
2509                    st.opcode.add_reg(31, 0);
2510                    st.rm_rel = *op1;
2511                    st.opcode.add_reg(m.base_id(), 5);
2512                    emit_op!();
2513                }
2514            }
2515
2516            Encoding::BaseAtomicCasp => {
2517                let op_data = &BASE_ATOMIC_CASP[encoding_index];
2518                if isign4 == enc_ops!(Reg, Reg, Reg, Reg) {
2519                    let op4 = *ops.get(4).unwrap_or(&NOREG);
2520                    if op4.is_mem() {
2521                        let m = op4.as_::<Mem>();
2522                        let mut x = 0;
2523                        if !check_gp_typex(op0, op_data.reg_type, &mut x) {
2524                            self.last_error = Some(AsmError::InvalidOperand);
2525                            return;
2526                        }
2527                        if !check_signature!(op0, op1, op2, op3) {
2528                            self.last_error = Some(AsmError::InvalidOperand);
2529                            return;
2530                        }
2531                        let id0 = op0.id();
2532                        let id2 = op2.id();
2533                        if (id0 & 1) != 0 || (id2 & 1) != 0 || id0 == id2 || id0 > 30 || id2 > 30 {
2534                            self.last_error = Some(AsmError::InvalidOperand);
2535                            return;
2536                        }
2537                        if (id0 + 1) != op1.id() || (id2 + 1) != op3.id() {
2538                            self.last_error = Some(AsmError::InvalidOperand);
2539                            return;
2540                        }
2541                        st.opcode.reset(op_data.opcode());
2542                        st.opcode.add_imm(x, op_data.x_offset as _);
2543                        st.opcode.add_reg(op0.id(), 16);
2544                        st.opcode.add_reg(op2.id(), 0);
2545                        st.rm_rel = *op4;
2546                        emit_mem_base_no_imm_rn5!();
2547                    }
2548                }
2549            }
2550
2551            Encoding::FSimdSV => {
2552                let op_data = &F_SIMD_SV[encoding_index];
2553
2554                if isign4 == enc_ops!(Reg, Reg) {
2555                    let q = op1.as_::<Reg>().typ() as u32;
2556                    let q = if q >= RegType::Vec64 as u32 {
2557                        q - RegType::Vec64 as u32
2558                    } else {
2559                        u32::MAX
2560                    };
2561                    if q > 1 {
2562                        self.last_error = Some(AsmError::InvalidInstruction);
2563                        return;
2564                    }
2565
2566                    if op0.as_::<Vec>().has_element_type() {
2567                        self.last_error = Some(AsmError::InvalidInstruction);
2568                        return;
2569                    }
2570
2571                    let sz = op0.as_::<Reg>().typ() as u32;
2572                    let sz = if sz >= RegType::Vec16 as u32 {
2573                        sz - RegType::Vec16 as u32
2574                    } else {
2575                        u32::MAX
2576                    };
2577                    let element_sz = op1.as_::<Vec>().element_type() as u32;
2578                    let element_sz = if element_sz >= VecElementType::H as u32 {
2579                        element_sz - VecElementType::H as u32
2580                    } else {
2581                        u32::MAX
2582                    };
2583
2584                    if (sz | element_sz) > 1 || sz != element_sz {
2585                        self.last_error = Some(AsmError::InvalidInstruction);
2586                        return;
2587                    }
2588
2589                    if sz != 0 && q == 0 {
2590                        self.last_error = Some(AsmError::InvalidInstruction);
2591                        return;
2592                    }
2593
2594                    st.opcode.reset((op_data.opcode as u32) << 10);
2595                    if sz == 0 {
2596                        st.opcode.0 ^= 1 << 29;
2597                    }
2598                    st.opcode.add_imm(q, 30);
2599                    st.opcode.add_reg(op0.id(), 0);
2600                    st.opcode.add_reg(op1.id(), 5);
2601                    emit_op!();
2602                }
2603            }
2604
2605            Encoding::FSimdVV => {
2606                let op_data = &F_SIMD_VV[encoding_index];
2607
2608                if isign4 == enc_ops!(Reg, Reg) {
2609                    if !match_signature2(op0, op1, inst_flags as u32) {
2610                        self.last_error = Some(AsmError::InvalidInstruction);
2611                        return;
2612                    }
2613
2614                    if let Some(fp_opcode) = pick_fp_opcode(
2615                        op0.as_::<Vec>(),
2616                        op_data.scalar_op(),
2617                        op_data.scalar_hf(),
2618                        op_data.vector_op(),
2619                        op_data.vector_hf(),
2620                        &mut 0,
2621                    ) {
2622                        st.opcode.reset(fp_opcode.0);
2623                        emit_rd0_rn5!();
2624                    }
2625
2626                    self.last_error = Some(AsmError::InvalidInstruction);
2627                    return;
2628                }
2629            }
2630
2631            Encoding::FSimdVVV => {
2632                let op_data = &F_SIMD_VVV[encoding_index];
2633
2634                if isign4 == enc_ops!(Reg, Reg, Reg) {
2635                    if !match_signature3(op0, op1, op2, inst_flags as u32) {
2636                        self.last_error = Some(AsmError::InvalidInstruction);
2637                        return;
2638                    }
2639
2640                    if let Some(fp_opcode) = pick_fp_opcode(
2641                        op0.as_::<Vec>(),
2642                        op_data.scalar_op(),
2643                        op_data.scalar_hf(),
2644                        op_data.vector_op(),
2645                        op_data.vector_hf(),
2646                        &mut 0,
2647                    ) {
2648                        st.opcode.reset(fp_opcode.0);
2649                        emit_rd0_rn5_rm16!();
2650                    }
2651
2652                    self.last_error = Some(AsmError::InvalidInstruction);
2653                    return;
2654                }
2655            }
2656
2657            Encoding::FSimdVVVe => {
2658                let op_data = &F_SIMD_VVVE[encoding_index];
2659
2660                if isign4 == enc_ops!(Reg, Reg, Reg) {
2661                    if !op2.as_::<Vec>().has_element_index() {
2662                        if !match_signature3(op0, op1, op2, inst_flags as u32) {
2663                            self.last_error = Some(AsmError::InvalidInstruction);
2664                            return;
2665                        }
2666
2667                        if let Some(fp_opcode) = pick_fp_opcode(
2668                            op0.as_::<Vec>(),
2669                            op_data.scalar_op(),
2670                            op_data.scalar_hf(),
2671                            op_data.vector_op(),
2672                            op_data.vector_hf(),
2673                            &mut 0,
2674                        ) {
2675                            st.opcode.reset(fp_opcode.0);
2676
2677                            emit_rd0_rn5_rm16!();
2678                        }
2679
2680                        self.last_error = Some(AsmError::InvalidInstruction);
2681                        return;
2682                    } else {
2683                        if !match_signature2(op0, op1, inst_flags as u32) {
2684                            self.last_error = Some(AsmError::InvalidInstruction);
2685                            return;
2686                        }
2687
2688                        let q = op1.as_::<Reg>().is_vec128() as u32;
2689                        let mut sz = 0;
2690                        if let Some((fp_opcode)) = pick_fp_opcode(
2691                            op0.as_::<Vec>(),
2692                            op_data.element_scalar_op(),
2693                            5,
2694                            op_data.element_vector_op(),
2695                            5,
2696                            &mut sz,
2697                        ) {
2698                            if sz == 0 && op2.as_::<Reg>().id() > 15 {
2699                                self.last_error = Some(AsmError::InvalidOperand);
2700                                return;
2701                            }
2702
2703                            let element_index = op2.as_::<Vec>().element_index();
2704                            if element_index > (7u32 >> sz) {
2705                                self.last_error = Some(AsmError::InvalidOperand);
2706                                return;
2707                            }
2708
2709                            let hlm = element_index << sz;
2710                            st.opcode.reset(fp_opcode.0);
2711                            st.opcode.add_imm(q, 30);
2712                            st.opcode.add_imm(hlm & 3, 20);
2713                            st.opcode.add_imm(hlm >> 2, 11);
2714                            emit_rd0_rn5_rm16!();
2715                        }
2716
2717                        self.last_error = Some(AsmError::InvalidInstruction);
2718                        return;
2719                    }
2720                }
2721            }
2722
2723            Encoding::FSimdVVVV => {
2724                let op_data = &F_SIMD_VVVV[encoding_index];
2725
2726                if isign4 == enc_ops!(Reg, Reg, Reg, Reg) {
2727                    if !match_signature4(op0, op1, op2, op3, inst_flags as u32) {
2728                        self.last_error = Some(AsmError::InvalidInstruction);
2729                        return;
2730                    }
2731
2732                    if let Some(fp_opcode) = pick_fp_opcode(
2733                        op0.as_::<Vec>(),
2734                        op_data.scalar_op(),
2735                        op_data.scalar_hf(),
2736                        op_data.vector_op(),
2737                        op_data.vector_hf(),
2738                        &mut 0,
2739                    ) {
2740                        st.opcode.reset(fp_opcode.0);
2741                        emit_rd0_rn5_rm16_ra10!();
2742                    }
2743
2744                    self.last_error = Some(AsmError::InvalidInstruction);
2745                    return;
2746                }
2747            }
2748
2749            Encoding::SimdFcadd => {
2750                let op_data = &SIMD_FCADD[encoding_index];
2751
2752                if isign4 == enc_ops!(Reg, Reg, Reg, Imm) {
2753                    if !check_signature!(op0, op1, op2) || op0.as_::<Vec>().has_element_index() {
2754                        self.last_error = Some(AsmError::InvalidInstruction);
2755                        return;
2756                    }
2757
2758                    let q = (op0.as_::<Reg>().is_vec128() as u32).wrapping_sub(1);
2759                    if q > 1 {
2760                        self.last_error = Some(AsmError::InvalidInstruction);
2761                        return;
2762                    }
2763
2764                    let mut sz = op0.as_::<Vec>().element_type() as u32;
2765                    sz = sz.wrapping_sub(1);
2766                    if sz == 0 || sz > 3 {
2767                        self.last_error = Some(AsmError::InvalidInstruction);
2768                        return;
2769                    }
2770
2771                    let mut rot = 0u32;
2772                    let imm_val = op3.as_::<Imm>().value();
2773                    if imm_val == 270 {
2774                        rot = 1;
2775                    } else if imm_val != 90 {
2776                        self.last_error = Some(AsmError::InvalidOperand);
2777                        return;
2778                    }
2779
2780                    st.opcode.reset(op_data.opcode());
2781                    st.opcode.add_imm(q, 30);
2782                    st.opcode.add_imm(sz, 22);
2783                    st.opcode.add_imm(rot, 12);
2784                    emit_rd0_rn5_rm16!();
2785                }
2786            }
2787
2788            Encoding::SimdFccmpFccmpe => {
2789                let op_data = &SIMD_FCCMP_FCCMPE[encoding_index];
2790
2791                if isign4 == enc_ops!(Reg, Reg, Imm, Imm) {
2792                    let sz = (op0.as_::<Reg>().typ() as u32).wrapping_sub(RegType::Vec16 as u32);
2793                    if sz > 2 {
2794                        self.last_error = Some(AsmError::InvalidInstruction);
2795                        return;
2796                    }
2797
2798                    if !check_signature!(op0, op1) || op0.as_::<Vec>().has_element_type() {
2799                        self.last_error = Some(AsmError::InvalidInstruction);
2800                        return;
2801                    }
2802
2803                    let nzcv = op2.as_::<Imm>().value() as u64;
2804                    let cond = op3.as_::<Imm>().value() as u64;
2805
2806                    if (nzcv | cond) > 0xF {
2807                        self.last_error = Some(AsmError::InvalidOperand);
2808                        return;
2809                    }
2810
2811                    let type_field = sz.wrapping_sub(1) & 0x3;
2812
2813                    st.opcode.reset(op_data.opcode());
2814                    st.opcode.add_imm(type_field, 22);
2815                    st.opcode
2816                        .add_imm(cond_code_to_opcode_field(cond as u32), 12);
2817                    st.opcode.add_imm(nzcv as u32, 0);
2818                    emit_rn5_rm16!();
2819                }
2820            }
2821
2822            Encoding::SimdFcm => {
2823                let op_data = &SIMD_FCM[encoding_index];
2824
2825                if isign4 == enc_ops!(Reg, Reg, Reg) && op_data.has_register_op() {
2826                    if !match_signature3(op0, op1, op2, inst_flags as u32) {
2827                        self.last_error = Some(AsmError::InvalidInstruction);
2828                        return;
2829                    }
2830
2831                    if let Some(fp_opcode) = pick_fp_opcode(
2832                        op0.as_::<Vec>(),
2833                        op_data.register_scalar_op(),
2834                        op_data.register_scalar_hf(),
2835                        op_data.register_vector_op(),
2836                        op_data.register_vector_hf(),
2837                        &mut 0,
2838                    ) {
2839                        st.opcode.reset(fp_opcode.0);
2840                        emit_rd0_rn5_rm16!();
2841                    }
2842
2843                    self.last_error = Some(AsmError::InvalidInstruction);
2844                    return;
2845                }
2846
2847                if isign4 == enc_ops!(Reg, Reg, Imm) && op_data.has_zero_op() {
2848                    if !check_signature!(op0, op1) {
2849                        self.last_error = Some(AsmError::InvalidInstruction);
2850                        return;
2851                    }
2852
2853                    if op2.as_::<Imm>().value() != 0 {
2854                        self.last_error = Some(AsmError::InvalidOperand);
2855                        return;
2856                    }
2857
2858                    if let Some(fp_opcode) = pick_fp_opcode(
2859                        op0.as_::<Vec>(),
2860                        op_data.zero_scalar_op(),
2861                        5,
2862                        op_data.zero_vector_op(),
2863                        5,
2864                        &mut 0,
2865                    ) {
2866                        st.opcode.reset(fp_opcode.0);
2867                        emit_rd0_rn5!();
2868                    }
2869
2870                    self.last_error = Some(AsmError::InvalidInstruction);
2871                    return;
2872                }
2873            }
2874
2875            Encoding::SimdFcmla => {
2876                let op_data = &SIMD_FCMLA[encoding_index];
2877
2878                if isign4 == enc_ops!(Reg, Reg, Reg, Imm) {
2879                    if !check_signature!(op0, op1) {
2880                        self.last_error = Some(AsmError::InvalidInstruction);
2881                        return;
2882                    }
2883
2884                    let q = (op0.as_::<Reg>().is_vec128() as u32).wrapping_sub(1);
2885                    if q > 1 {
2886                        self.last_error = Some(AsmError::InvalidInstruction);
2887                        return;
2888                    }
2889
2890                    let mut sz = op0.as_::<Vec>().element_type() as u32;
2891                    sz = sz.wrapping_sub(1);
2892                    if sz == 0 || sz > 3 {
2893                        self.last_error = Some(AsmError::InvalidInstruction);
2894                        return;
2895                    }
2896
2897                    let mut rot = 0u32;
2898                    match op3.as_::<Imm>().value() {
2899                        0 => rot = 0,
2900                        90 => rot = 1,
2901                        180 => rot = 2,
2902                        270 => rot = 3,
2903                        _ => {
2904                            self.last_error = Some(AsmError::InvalidOperand);
2905                            return;
2906                        }
2907                    }
2908
2909                    if !op2.as_::<Vec>().has_element_index() {
2910                        if !check_signature!(op1, op2) {
2911                            self.last_error = Some(AsmError::InvalidInstruction);
2912                            return;
2913                        }
2914
2915                        st.opcode.reset(op_data.regular_op());
2916                        st.opcode.add_imm(q, 30);
2917                        st.opcode.add_imm(sz, 22);
2918                        st.opcode.add_imm(rot, 11);
2919                        emit_rd0_rn5_rm16!();
2920                    } else {
2921                        if op0.as_::<Vec>().element_type() != op2.as_::<Vec>().element_type() {
2922                            self.last_error = Some(AsmError::InvalidOperand);
2923                            return;
2924                        }
2925
2926                        if !((sz == 1) || (q == 1 && sz == 2)) {
2927                            self.last_error = Some(AsmError::InvalidOperand);
2928                            return;
2929                        }
2930
2931                        let element_index = op2.as_::<Vec>().element_index();
2932                        let hl_field_shift = if sz == 1 { 0u32 } else { 1u32 };
2933                        let max_element_index = if q == 1 && sz == 1 { 3u32 } else { 1u32 };
2934
2935                        if element_index > max_element_index {
2936                            self.last_error = Some(AsmError::InvalidOperand);
2937                            return;
2938                        }
2939
2940                        let hl = element_index << hl_field_shift;
2941
2942                        st.opcode.reset(op_data.element_op());
2943                        st.opcode.add_imm(q, 30);
2944                        st.opcode.add_imm(sz, 22);
2945                        st.opcode.add_imm(hl & 1u32, 21);
2946                        st.opcode.add_imm(hl >> 1, 11);
2947                        st.opcode.add_imm(rot, 13);
2948                        emit_rd0_rn5_rm16!();
2949                    }
2950                }
2951            }
2952
2953            Encoding::SimdFcmpFcmpe => {
2954                let op_data = &SIMD_FCMP_FCMPE[encoding_index];
2955
2956                let sz = (op0.as_::<Reg>().typ() as u32).wrapping_sub(RegType::Vec16 as u32);
2957                let type_field = sz.wrapping_sub(1) & 0x3u32;
2958
2959                if sz > 2 {
2960                    self.last_error = Some(AsmError::InvalidInstruction);
2961                    return;
2962                }
2963
2964                if op0.as_::<Vec>().has_element_type() {
2965                    self.last_error = Some(AsmError::InvalidInstruction);
2966                    return;
2967                }
2968
2969                st.opcode.reset(op_data.opcode());
2970                st.opcode.add_imm(type_field, 22);
2971
2972                if isign4 == enc_ops!(Reg, Reg) {
2973                    if !check_signature!(op0, op1) {
2974                        self.last_error = Some(AsmError::InvalidInstruction);
2975                        return;
2976                    }
2977
2978                    st.opcode.add_reg(op0.id(), 5);
2979                    st.opcode.add_reg(op1.id(), 16);
2980                    emit_op!();
2981                } else if isign4 == enc_ops!(Reg, Imm) {
2982                    if op1.as_::<Imm>().value() != 0 {
2983                        self.last_error = Some(AsmError::InvalidOperand);
2984                        return;
2985                    }
2986
2987                    st.opcode.0 |= 0x8;
2988                    emit_rd0_rn5!();
2989                }
2990            }
2991
2992            Encoding::SimdFcsel => {
2993                if isign4 == enc_ops!(Reg, Reg, Reg, Imm) {
2994                    if !check_signature!(op0, op1, op2) {
2995                        self.last_error = Some(AsmError::InvalidInstruction);
2996                        return;
2997                    }
2998
2999                    let sz = (op0.as_::<Reg>().typ() as u32).wrapping_sub(RegType::Vec16 as u32);
3000                    let type_field = sz.wrapping_sub(1) & 0x3u32;
3001
3002                    if sz > 2 || op0.as_::<Vec>().has_element_type() {
3003                        self.last_error = Some(AsmError::InvalidInstruction);
3004                        return;
3005                    }
3006
3007                    let cond = op3.as_::<Imm>().value() as u32;
3008                    if cond > 0xFu32 {
3009                        self.last_error = Some(AsmError::InvalidImmediate);
3010                        return;
3011                    }
3012
3013                    st.opcode.reset(0b00011110001000000000110000000000u32);
3014                    st.opcode.add_imm(type_field, 22);
3015                    st.opcode.add_imm(cond, 12);
3016                    emit_rd0_rn5_rm16!();
3017                }
3018            }
3019
3020            Encoding::SimdFcvt => {
3021                if isign4 == enc_ops!(Reg, Reg) {
3022                    let dst_sz =
3023                        (op0.as_::<Reg>().reg_type() as u32).wrapping_sub(RegType::Vec16 as u32);
3024                    let src_sz =
3025                        (op1.as_::<Reg>().reg_type() as u32).wrapping_sub(RegType::Vec16 as u32);
3026
3027                    if (dst_sz | src_sz) > 3 {
3028                        self.last_error = Some(AsmError::InvalidInstruction);
3029                        return;
3030                    }
3031
3032                    if op0.as_::<Vec>().has_element_type() || op1.as_::<Vec>().has_element_type() {
3033                        self.last_error = Some(AsmError::InvalidInstruction);
3034                        return;
3035                    }
3036
3037                    // Table that provides 'type' and 'opc' according to the dst/src combination.
3038                    let table: [u8; 16] = [
3039                        0xFFu8, // H <- H (Invalid).
3040                        0x03u8, // H <- S (type=00 opc=11).
3041                        0x13u8, // H <- D (type=01 opc=11).
3042                        0xFFu8, // H <- Q (Invalid).
3043                        0x30u8, // S <- H (type=11 opc=00).
3044                        0xFFu8, // S <- S (Invalid).
3045                        0x10u8, // S <- D (type=01 opc=00).
3046                        0xFFu8, // S <- Q (Invalid).
3047                        0x31u8, // D <- H (type=11 opc=01).
3048                        0x01u8, // D <- S (type=00 opc=01).
3049                        0xFFu8, // D <- D (Invalid).
3050                        0xFFu8, // D <- Q (Invalid).
3051                        0xFFu8, // Q <- H (Invalid).
3052                        0xFFu8, // Q <- S (Invalid).
3053                        0xFFu8, // Q <- D (Invalid).
3054                        0xFFu8, // Q <- Q (Invalid).
3055                    ];
3056
3057                    let type_opc = table[((dst_sz << 2) | src_sz) as usize];
3058                    if type_opc == 0xFFu8 {
3059                        self.last_error = Some(AsmError::InvalidInstruction);
3060                        return;
3061                    }
3062
3063                    st.opcode.reset(0b0001111000100010010000 << 10);
3064                    st.opcode.add_imm((type_opc as u32) >> 4, 22);
3065                    st.opcode.add_imm((type_opc as u32) & 15, 15);
3066                    emit_rd0_rn5!();
3067                }
3068            }
3069
3070            Encoding::SimdFcvtLN => {
3071                let op_data = &SIMD_FCVT_LN[encoding_index];
3072
3073                if isign4 == enc_ops!(Reg, Reg) {
3074                    // Scalar form - only FCVTXN.
3075                    if op0.as_::<Vec>().is_vec32() && op1.as_::<Vec>().is_vec64() {
3076                        if op_data.has_scalar() == 0 {
3077                            self.last_error = Some(AsmError::InvalidInstruction);
3078                            return;
3079                        }
3080
3081                        if op0.as_::<Vec>().has_element_type()
3082                            || op1.as_::<Vec>().has_element_type()
3083                        {
3084                            self.last_error = Some(AsmError::InvalidInstruction);
3085                            return;
3086                        }
3087
3088                        st.opcode.reset(op_data.scalar_op());
3089                        st.opcode.0 |= 0x400000; // sz bit must be 1
3090                        emit_rd0_rn5!();
3091                        return;
3092                    }
3093
3094                    st.opcode.reset(op_data.vector_op());
3095
3096                    let is_long = (inst_flags & InstFlag::Long as u16) != 0;
3097                    let (rl, rn) = if is_long {
3098                        (op0.as_::<Vec>(), op1.as_::<Vec>())
3099                    } else {
3100                        (op1.as_::<Vec>(), op0.as_::<Vec>())
3101                    };
3102
3103                    let q = (rn.reg_type() as u32).wrapping_sub(RegType::Vec64 as u32);
3104                    if (st.opcode.has_q() as u32) != q {
3105                        self.last_error = Some(AsmError::InvalidInstruction);
3106                        return;
3107                    }
3108
3109                    if rl.is_vec_s4()
3110                        && rn.element_type() == VecElementType::H
3111                        && op_data.is_cvtxn() == 0
3112                    {
3113                        emit_rd0_rn5!();
3114                        return;
3115                    }
3116
3117                    if rl.is_vec_d2() && rn.element_type() == VecElementType::S {
3118                        st.opcode.0 |= 0x400000;
3119                        emit_rd0_rn5!();
3120                        return;
3121                    }
3122
3123                    self.last_error = Some(AsmError::InvalidInstruction);
3124                    return;
3125                }
3126            }
3127
3128            Encoding::SimdFcvtSV => {
3129                let op_data = &SIMD_FCVT_SV[encoding_index];
3130
3131                // So we can support both IntToFloat and FloatToInt conversions.
3132                let is_float_to_int = op_data.is_float_to_int();
3133                let (op_gp, op_vec) = if is_float_to_int != 0 {
3134                    (&op0, &op1)
3135                } else {
3136                    (&op1, &op0)
3137                };
3138
3139                if isign4 == enc_ops!(Reg, Reg) {
3140                    if op_gp.as_::<Reg>().is_gp() && op_vec.as_::<Reg>().is_vec() {
3141                        let x = op_gp.as_::<Reg>().is_gp64() as u32;
3142                        let type_field = (op_vec.as_::<Reg>().reg_type() as u32)
3143                            .wrapping_sub(RegType::Vec16 as u32);
3144
3145                        if type_field > 2u32 {
3146                            self.last_error = Some(AsmError::InvalidInstruction);
3147                            return;
3148                        }
3149
3150                        let type_val = (type_field - 1u32) & 0x3;
3151                        st.opcode.reset(op_data.general_op());
3152                        st.opcode.add_imm(type_val, 22);
3153                        st.opcode.add_imm(x, 31);
3154                        emit_rd0_rn5!();
3155                    } else if op0.as_::<Reg>().is_vec() && op1.as_::<Reg>().is_vec() {
3156                        if !check_signature!(op0, op1) {
3157                            self.last_error = Some(AsmError::InvalidInstruction);
3158                            return;
3159                        }
3160
3161                        if let Some(fp_opcode) = pick_fp_opcode(
3162                            op0.as_::<Vec>(),
3163                            op_data.scalar_int_op(),
3164                            5,
3165                            op_data.vector_int_op(),
3166                            5,
3167                            &mut 0,
3168                        ) {
3169                            st.opcode.reset(fp_opcode.0);
3170                            emit_rd0_rn5!();
3171                        } else {
3172                            self.last_error = Some(AsmError::InvalidInstruction);
3173                            return;
3174                        }
3175                    }
3176                } else if isign4 == enc_ops!(Reg, Reg, Imm) && op_data.is_fixed_point() {
3177                    let scale_val = op2.as_::<Imm>().value() as u32;
3178                    if scale_val >= 64 {
3179                        self.last_error = Some(AsmError::InvalidImmediate);
3180                        return;
3181                    }
3182
3183                    if scale_val == 0 {
3184                        self.last_error = Some(AsmError::InvalidOperand);
3185                        return;
3186                    }
3187
3188                    if op_gp.as_::<Reg>().is_gp() && op_vec.as_::<Reg>().is_vec() {
3189                        let x = op_gp.as_::<Reg>().is_gp64() as u32;
3190                        let type_field = (op_vec.as_::<Reg>().reg_type() as u32)
3191                            .wrapping_sub(RegType::Vec16 as u32);
3192
3193                        let scale_limit = 32u32 << x;
3194                        if scale_val > scale_limit {
3195                            self.last_error = Some(AsmError::InvalidOperand);
3196                            return;
3197                        }
3198
3199                        let type_val = (type_field - 1u32) & 0x3;
3200                        st.opcode.reset(op_data.general_op() ^ 0x200000);
3201                        st.opcode.add_imm(type_val, 22);
3202                        st.opcode.add_imm(x, 31);
3203                        st.opcode.add_imm(64u32 - scale_val, 10);
3204                        emit_rd0_rn5!();
3205                    } else if op0.as_::<Reg>().is_vec() && op1.as_::<Reg>().is_vec() {
3206                        if !check_signature!(op0, op1) {
3207                            self.last_error = Some(AsmError::InvalidInstruction);
3208                            return;
3209                        }
3210
3211                        let mut sz = 0u32;
3212                        if let Some(fp_opcode) = pick_fp_opcode(
3213                            op0.as_::<Vec>(),
3214                            op_data.scalar_fp_op(),
3215                            5,
3216                            op_data.vector_fp_op(),
3217                            5,
3218                            &mut sz,
3219                        ) {
3220                            let scale_limit = 16u32 << sz;
3221                            if scale_val > scale_limit {
3222                                self.last_error = Some(AsmError::InvalidOperand);
3223                                return;
3224                            }
3225
3226                            let imm = (!(scale_val) + 1) & ((1u32 << (sz + 4 + 1)) - 1);
3227                            st.opcode.reset(fp_opcode.0);
3228                            st.opcode.add_imm(imm, 16);
3229                            emit_rd0_rn5!();
3230                        } else {
3231                            self.last_error = Some(AsmError::InvalidInstruction);
3232                            return;
3233                        }
3234                    }
3235                }
3236            }
3237
3238            Encoding::SimdFmlal => {
3239                let op_data = &SIMD_FMLAL[encoding_index];
3240
3241                if isign4 == enc_ops!(Reg, Reg, Reg) {
3242                    let mut q =
3243                        (op0.as_::<Reg>().reg_type() as u32).wrapping_sub(RegType::Vec64 as u32);
3244                    let q_is_optional = op_data.optional_q() != 0;
3245
3246                    if q_is_optional {
3247                        if q > 1 {
3248                            self.last_error = Some(AsmError::InvalidInstruction);
3249                            return;
3250                        }
3251                    } else {
3252                        if q != 1 {
3253                            self.last_error = Some(AsmError::InvalidInstruction);
3254                            return;
3255                        }
3256
3257                        q = 0;
3258                    }
3259
3260                    if (op0.as_::<Reg>().reg_type() as u32)
3261                        != (op1.as_::<Reg>().reg_type() as u32) + if q_is_optional { 1 } else { 0 }
3262                        || (op0.as_::<Vec>().element_type() as u32) != op_data.ta as u32
3263                        || (op1.as_::<Vec>().element_type() as u32) != op_data.tb as u32
3264                    {
3265                        self.last_error = Some(AsmError::InvalidInstruction);
3266                        return;
3267                    }
3268
3269                    if !op2.as_::<Vec>().has_element_index() {
3270                        if !check_signature!(&op1, &op2) {
3271                            self.last_error = Some(AsmError::InvalidInstruction);
3272                            return;
3273                        }
3274
3275                        st.opcode.reset(op_data.vector_op());
3276                        st.opcode.add_imm(q, 30);
3277                        emit_rd0_rn5_rm16!();
3278                    } else {
3279                        if (op2.as_::<Vec>().element_type() as u32) != op_data.t_element as u32 {
3280                            self.last_error = Some(AsmError::InvalidInstruction);
3281                            return;
3282                        }
3283
3284                        if op2.as_::<Reg>().id() > 15 {
3285                            self.last_error = Some(AsmError::InvalidOperand);
3286                            return;
3287                        }
3288
3289                        let element_index = op2.as_::<Vec>().element_index();
3290                        if element_index > 7u32 {
3291                            self.last_error = Some(AsmError::InvalidOperand);
3292                            return;
3293                        }
3294
3295                        st.opcode.reset(op_data.element_op());
3296                        st.opcode.add_imm(q, 30);
3297                        st.opcode.add_imm(element_index & 3u32, 20);
3298                        st.opcode.add_imm(element_index >> 2, 11);
3299                        emit_rd0_rn5_rm16!();
3300                    }
3301                }
3302            }
3303
3304            Encoding::SimdFmov => {
3305                if isign4 == enc_ops!(Reg, Reg) {
3306                    // FMOV Gp <-> Vec st.opcode:
3307                    st.opcode.reset(0b00011110001001100000000000000000);
3308
3309                    if (op0.as_::<Reg>().is_gp() && op1.as_::<Reg>().is_vec()) {
3310                        // FMOV Wd, Hn      (sf=0 type=11 rmode=00 op=110)
3311                        // FMOV Xd, Hn      (sf=1 type=11 rmode=00 op=110)
3312                        // FMOV Wd, Sn      (sf=0 type=00 rmode=00 op=110)
3313                        // FMOV Xd, Dn      (sf=1 type=11 rmode=00 op=110)
3314                        // FMOV Xd, Vn.d[1] (sf=1 type=10 rmode=01 op=110)
3315                        let x = op0.as_::<Reg>().is_gp64();
3316                        let sz = (op1.as_::<Reg>().reg_type() as u32)
3317                            .wrapping_sub(RegType::Vec16 as u32);
3318
3319                        let mut typ = sz.wrapping_sub(1) & 0x3;
3320                        let mut r_mode_op = 0b00110;
3321
3322                        if (op1.as_::<Vec>().has_element_index()) {
3323                            // Special case.
3324                            if (!x
3325                                || !op1.as_::<Vec>().is_vec_d2()
3326                                || op1.as_::<Vec>().element_index() != 1)
3327                            {
3328                                self.last_error = Some(AsmError::InvalidInstruction);
3329                                return;
3330                            }
3331                            typ = 0b10;
3332                            r_mode_op = 0b01110;
3333                        } else {
3334                            // Must be scalar.
3335                            if (sz > 2) {
3336                                self.last_error = Some(AsmError::InvalidOperand);
3337                                return;
3338                            }
3339
3340                            if (op1.as_::<Vec>().has_element_type()) {
3341                                self.last_error = Some(AsmError::InvalidInstruction);
3342                                return;
3343                            }
3344
3345                            if (op1.as_::<Vec>().is_vec32() && x) {
3346                                self.last_error = Some(AsmError::InvalidInstruction);
3347                                return;
3348                            }
3349
3350                            if (op1.as_::<Vec>().is_vec64() && !x) {
3351                                self.last_error = Some(AsmError::InvalidInstruction);
3352                                return;
3353                            }
3354                        }
3355
3356                        st.opcode.add_imm(x as u32, 31);
3357                        st.opcode.add_imm(typ, 22);
3358                        st.opcode.add_imm(r_mode_op, 16);
3359
3360                        emit_rd0_rn5!();
3361                    }
3362
3363                    if (op0.as_::<Reg>().is_vec() && op1.as_::<Reg>().is_gp()) {
3364                        // FMOV Hd, Wn      (sf=0 type=11 rmode=00 op=111)
3365                        // FMOV Hd, Xn      (sf=1 type=11 rmode=00 op=111)
3366                        // FMOV Sd, Wn      (sf=0 type=00 rmode=00 op=111)
3367                        // FMOV Dd, Xn      (sf=1 type=11 rmode=00 op=111)
3368                        // FMOV Vd.d[1], Xn (sf=1 type=10 rmode=01 op=111)
3369                        let x = op1.as_::<Reg>().is_gp64();
3370                        let sz = (op0.as_::<Reg>().reg_type() as u32)
3371                            .wrapping_sub(RegType::Vec16 as u32);
3372
3373                        let mut typ = sz.wrapping_sub(1) & 0x3;
3374                        let mut r_mode_op = 0b00111;
3375
3376                        if (op0.as_::<Vec>().has_element_index()) {
3377                            // Special case.
3378                            if (!x
3379                                || !op0.as_::<Vec>().is_vec_d2()
3380                                || op0.as_::<Vec>().element_index() != 1)
3381                            {
3382                                self.last_error = Some(AsmError::InvalidInstruction);
3383                                return;
3384                            }
3385                            typ = 0b10;
3386                            r_mode_op = 0b01111;
3387                        } else {
3388                            // Must be scalar.
3389                            if (sz > 2) {
3390                                self.last_error = Some(AsmError::InvalidInstruction);
3391                                return;
3392                            }
3393
3394                            if (op0.as_::<Vec>().has_element_type()) {
3395                                self.last_error = Some(AsmError::InvalidInstruction);
3396                                return;
3397                            }
3398
3399                            if (op0.as_::<Vec>().is_vec32() && x) {
3400                                self.last_error = Some(AsmError::InvalidInstruction);
3401                                return;
3402                            }
3403
3404                            if (op0.as_::<Vec>().is_vec64() && !x) {
3405                                self.last_error = Some(AsmError::InvalidInstruction);
3406                                return;
3407                            }
3408                        }
3409
3410                        st.opcode.add_imm(x as u32, 31);
3411                        st.opcode.add_imm(typ, 22);
3412                        st.opcode.add_imm(r_mode_op, 16);
3413                        emit_rd0_rn5!();
3414                    }
3415
3416                    if check_signature!(op0, op1) {
3417                        let sz = (op0.as_::<Reg>().reg_type() as u32)
3418                            .wrapping_sub(RegType::Vec16 as u32);
3419                        if sz > 2 {
3420                            self.last_error = Some(AsmError::InvalidInstruction);
3421                            return;
3422                        }
3423
3424                        if op0.as_::<Vec>().has_element_type() {
3425                            self.last_error = Some(AsmError::InvalidInstruction);
3426                            return;
3427                        }
3428
3429                        let typ = sz.wrapping_sub(1) & 0x3;
3430                        st.opcode.reset(0b00011110001000000100000000000000);
3431                        st.opcode.add_imm(typ, 22);
3432                        emit_rd0_rn5!();
3433                    }
3434                }
3435
3436                if isign4 == enc_ops!(Reg, Imm) {
3437                    if op0.as_::<Reg>().is_vec() {
3438                        let fp_value = if op1.as_::<Imm>().is_double() {
3439                            op1.as_::<Imm>().value_f64()
3440                        } else if op1.as_::<Imm>().is_int32() {
3441                            op1.as_::<Imm>().value() as i32 as f64
3442                        } else {
3443                            self.last_error = Some(AsmError::InvalidOperand);
3444                            return;
3445                        };
3446
3447                        if !is_fp64_imm8(fp_value.to_bits()) {
3448                            self.last_error = Some(AsmError::InvalidOperand);
3449                            return;
3450                        }
3451
3452                        let imm8 = encode_fp64_to_imm8(fp_value.to_bits());
3453
3454                        if !op0.as_::<Vec>().has_element_type() {
3455                            let sz = (op0.as_::<Reg>().reg_type() as u32)
3456                                .wrapping_sub(RegType::Vec16 as u32);
3457                            let typ = sz.wrapping_sub(1) & 0x3;
3458                            if sz > 2 {
3459                                self.last_error = Some(AsmError::InvalidInstruction);
3460                                return;
3461                            }
3462
3463                            st.opcode.reset(0b00011110001000000001000000000000);
3464                            st.opcode.add_imm(typ, 22);
3465                            st.opcode.add_imm(imm8, 13);
3466                            emit_rd0!();
3467                        } else {
3468                            let q = (op0.as_::<Reg>().reg_type() as u32)
3469                                .wrapping_sub(RegType::Vec64 as u32);
3470                            let sz = (op0.as_::<Vec>().element_type() as u32)
3471                                .wrapping_sub(VecElementType::H as u32);
3472
3473                            if q > 1 || sz > 2 {
3474                                self.last_error = Some(AsmError::InvalidInstruction);
3475                                return;
3476                            }
3477
3478                            const SZ_BITS_TABLE: [u32; 3] = [1 << 11, 0, 1 << 29];
3479                            st.opcode.reset(0b00001111000000001111010000000000);
3480                            st.opcode ^= SZ_BITS_TABLE[sz as usize];
3481                            st.opcode.add_imm(q, 30);
3482                            st.opcode.add_imm(imm8 >> 5, 16);
3483                            st.opcode.add_imm(imm8 & 31, 5);
3484                            emit_rd0!();
3485                        }
3486                    }
3487                }
3488            }
3489
3490            Encoding::FSimdPair => {
3491                let op_data = &F_SIMD_PAIR[encoding_index];
3492
3493                if isign4 == enc_ops!(Reg, Reg) {
3494                    // This operation is only defined for:
3495                    //   hD, vS.2h (16-bit)
3496                    //   sD, vS.2s (32-bit)
3497                    //   dD, vS.2d (64-bit)
3498                    let sz =
3499                        (op0.as_::<Reg>().reg_type() as u32).wrapping_sub(RegType::Vec16 as u32);
3500                    if sz > 2 {
3501                        self.last_error = Some(AsmError::InvalidInstruction);
3502                        return;
3503                    }
3504
3505                    const SZ_SIGNATURES: [u32; 3] = [
3506                        A64VecS::SIGNATURE | (Vec::SIGNATURE_ELEMENT_H as u32),
3507                        A64VecD::SIGNATURE | (Vec::SIGNATURE_ELEMENT_S as u32),
3508                        A64VecQ::SIGNATURE | (Vec::SIGNATURE_ELEMENT_D as u32),
3509                    ];
3510
3511                    if op0.signature().bits() != SZ_SIGNATURES[sz as usize] {
3512                        self.last_error = Some(AsmError::InvalidInstruction);
3513                        return;
3514                    }
3515
3516                    const SZ_BITS_TABLE: [u32; 3] = [1 << 29, 0, 1 << 22];
3517
3518                    st.opcode.reset(op_data.scalar_op());
3519                    st.opcode ^= SZ_BITS_TABLE[sz as usize];
3520                    emit_rd0_rn5!();
3521                }
3522
3523                if isign4 == enc_ops!(Reg, Reg, Reg) {
3524                    if !check_signature!(op0, op1, op2) {
3525                        self.last_error = Some(AsmError::InvalidInstruction);
3526                        return;
3527                    }
3528
3529                    let q =
3530                        (op0.as_::<Reg>().reg_type() as u32).wrapping_sub(RegType::Vec64 as u32);
3531                    if q > 1 {
3532                        self.last_error = Some(AsmError::InvalidInstruction);
3533                        return;
3534                    }
3535
3536                    const SZ_BITS_TABLE: [u32; 3] =
3537                        [(1 << 22) | (1 << 21) | (1 << 15) | (1 << 14), 0, 1 << 22];
3538                    st.opcode.reset(op_data.scalar_op());
3539                    st.opcode ^= SZ_BITS_TABLE[q as usize];
3540                    st.opcode.add_imm(q, 30);
3541                    emit_rd0_rn5_rm16!();
3542                }
3543            }
3544
3545            Encoding::ISimdSV => {
3546                let op_data = &I_SIMD_SV[encoding_index];
3547
3548                if isign4 == enc_ops!(Reg, Reg) {
3549                    let l = (inst_flags & InstFlag::Long as u16) != 0;
3550                    if (op0.as_::<Vec>().reg_type() as u32).wrapping_sub(RegType::Vec8 as u32)
3551                        != (op1.as_::<Vec>().element_type() as u32)
3552                            .wrapping_sub(VecElementType::B as u32)
3553                            .wrapping_add(l as u32)
3554                    {
3555                        self.last_error = Some(AsmError::InvalidInstruction);
3556                        return;
3557                    }
3558                    let size_op = element_type_to_size_op(
3559                        op_data.vec_op_type,
3560                        op1.as_::<Reg>().reg_type(),
3561                        op1.as_::<Vec>().element_type(),
3562                    );
3563
3564                    if !size_op.is_valid() {
3565                        self.last_error = Some(AsmError::InvalidInstruction);
3566                        return;
3567                    }
3568
3569                    st.opcode.reset(op_data.opcode());
3570                    st.opcode.add_imm(size_op.q(), 30);
3571                    st.opcode.add_imm(size_op.size(), 22);
3572                    emit_rd0_rn5!();
3573                }
3574            }
3575
3576            Encoding::ISimdVV => {
3577                let op_data = &I_SIMD_VV[encoding_index];
3578
3579                if isign4 == enc_ops!(Reg, Reg) {
3580                    let sop = significant_simd_op(op0, op1, inst_flags as u32);
3581                    if !match_signature2(op0, op1, inst_flags as u32) {
3582                        self.last_error = Some(AsmError::InvalidInstruction);
3583                        return;
3584                    }
3585
3586                    let size_op = element_type_to_size_op(
3587                        op_data.vec_op_type,
3588                        sop.as_::<Reg>().reg_type(),
3589                        sop.as_::<Vec>().element_type(),
3590                    );
3591                    if !size_op.is_valid() {
3592                        self.last_error = Some(AsmError::InvalidInstruction);
3593                        return;
3594                    }
3595
3596                    st.opcode.reset(op_data.opcode());
3597                    st.opcode.add_imm(size_op.qs(), 30);
3598                    st.opcode.add_imm(size_op.scalar(), 28);
3599                    st.opcode.add_imm(size_op.size(), 22);
3600                    emit_rd0_rn5!();
3601                }
3602            }
3603
3604            Encoding::ISimdVVx => {
3605                let op_data = &I_SIMD_VVX[encoding_index];
3606                if isign4 == enc_ops!(Reg, Reg) {
3607                    if op0.signature().bits() != op_data.op0_signature
3608                        || op1.signature().bits() != op_data.op1_signature
3609                    {
3610                        self.last_error = Some(AsmError::InvalidInstruction);
3611                        return;
3612                    }
3613                    st.opcode.reset(op_data.opcode());
3614                    emit_rd0_rn5!();
3615                }
3616            }
3617
3618            Encoding::ISimdVVV => {
3619                let op_data = &I_SIMD_VVV[encoding_index];
3620
3621                if isign4 == enc_ops!(Reg, Reg, Reg) {
3622                    let sop = significant_simd_op(op0, op1, inst_flags as u32);
3623                    if !match_signature3(op0, op1, op2, inst_flags as u32) {
3624                        self.last_error = Some(AsmError::InvalidInstruction);
3625                        return;
3626                    }
3627
3628                    let size_op = element_type_to_size_op(
3629                        op_data.vec_op_type,
3630                        sop.as_::<Reg>().reg_type(),
3631                        sop.as_::<Vec>().element_type(),
3632                    );
3633                    if !size_op.is_valid() {
3634                        self.last_error = Some(AsmError::InvalidInstruction);
3635                        return;
3636                    }
3637
3638                    st.opcode.reset(op_data.opcode());
3639                    st.opcode.add_imm(size_op.qs(), 30);
3640                    st.opcode.add_imm(size_op.scalar(), 28);
3641                    st.opcode.add_imm(size_op.size(), 22);
3642                    emit_rd0_rn5_rm16!();
3643                }
3644            }
3645
3646            Encoding::ISimdVVVx => {
3647                let op_data = &I_SIMD_VVVX[encoding_index];
3648
3649                if isign4 == enc_ops!(Reg, Reg, Reg) {
3650                    if op0.signature().bits() != op_data.op0_signature
3651                        || op1.signature().bits() != op_data.op1_signature
3652                        || op2.signature().bits() != op_data.op2_signature
3653                    {
3654                        self.last_error = Some(AsmError::InvalidInstruction);
3655                        return;
3656                    }
3657
3658                    st.opcode.reset(op_data.opcode());
3659                    emit_rd0_rn5_rm16!();
3660                }
3661            }
3662
3663            Encoding::ISimdWWV => {
3664                let op_data = &I_SIMD_WWV[encoding_index];
3665                if isign4 == enc_ops!(Reg, Reg, Reg) {
3666                    let size_op = element_type_to_size_op(
3667                        op_data.vec_op_type,
3668                        op2.as_::<Reg>().reg_type(),
3669                        op2.as_::<Vec>().element_type(),
3670                    );
3671                    if !size_op.is_valid() {
3672                        self.last_error = Some(AsmError::InvalidInstruction);
3673                        return;
3674                    }
3675                    if !check_signature!(op0, op1)
3676                        || !op0.as_::<Reg>().is_vec128()
3677                        || (op0.as_::<Vec>().element_type() as u32)
3678                            != (op2.as_::<Vec>().element_type() as u32 + 1)
3679                    {
3680                        self.last_error = Some(AsmError::InvalidInstruction);
3681                        return;
3682                    }
3683                    st.opcode.reset(op_data.opcode());
3684                    st.opcode.add_imm(size_op.qs(), 30);
3685                    st.opcode.add_imm(size_op.scalar(), 28);
3686                    st.opcode.add_imm(size_op.size(), 22);
3687                    emit_rd0_rn5_rm16!();
3688                }
3689            }
3690
3691            Encoding::ISimdVVVe => {
3692                let op_data = &I_SIMD_VVVE[encoding_index];
3693                if isign4 == enc_ops!(Reg, Reg, Reg) {
3694                    let sop = significant_simd_op(op0, op1, inst_flags as u32);
3695                    if !match_signature2(op0, op1, inst_flags as u32) {
3696                        self.last_error = Some(AsmError::InvalidInstruction);
3697                        return;
3698                    }
3699                    if !op2.as_::<Vec>().has_element_index() {
3700                        let size_op = element_type_to_size_op(
3701                            op_data.regular_vec_type,
3702                            sop.as_::<Reg>().reg_type(),
3703                            sop.as_::<Vec>().element_type(),
3704                        );
3705                        if !size_op.is_valid() {
3706                            self.last_error = Some(AsmError::InvalidInstruction);
3707                            return;
3708                        }
3709                        if !check_signature!(op1, op2) {
3710                            self.last_error = Some(AsmError::InvalidInstruction);
3711                            return;
3712                        }
3713                        st.opcode.reset((op_data.regular_op as u32) << 10);
3714                        st.opcode.add_imm(size_op.qs(), 30);
3715                        st.opcode.add_imm(size_op.scalar(), 28);
3716                        st.opcode.add_imm(size_op.size(), 22);
3717                        emit_rd0_rn5_rm16!();
3718                    } else {
3719                        let size_op = element_type_to_size_op(
3720                            op_data.element_vec_type,
3721                            sop.as_::<Reg>().reg_type(),
3722                            sop.as_::<Vec>().element_type(),
3723                        );
3724                        if !size_op.is_valid() {
3725                            self.last_error = Some(AsmError::InvalidInstruction);
3726                            return;
3727                        }
3728                        let element_index = op2.as_::<Vec>().element_index();
3729                        let mut lmh = LMHImm {
3730                            lm: 0,
3731                            h: 0,
3732                            max_rm_id: 0,
3733                        };
3734                        if !encode_lmh(size_op.size(), element_index, &mut lmh) {
3735                            self.last_error = Some(AsmError::InvalidOperand);
3736                            return;
3737                        }
3738                        if op2.as_::<Reg>().id() > lmh.max_rm_id {
3739                            self.last_error = Some(AsmError::InvalidOperand);
3740                            return;
3741                        }
3742                        st.opcode.reset((op_data.element_op as u32) << 10);
3743                        st.opcode.add_imm(size_op.q(), 30);
3744                        st.opcode.add_imm(size_op.size(), 22);
3745                        st.opcode.add_imm(lmh.lm, 20);
3746                        st.opcode.add_imm(lmh.h, 11);
3747                        emit_rd0_rn5_rm16!();
3748                    }
3749                }
3750            }
3751
3752            Encoding::ISimdVVVI => {
3753                let op_data = &I_SIMD_VVVI[encoding_index];
3754                if isign4 == enc_ops!(Reg, Reg, Reg, Imm) {
3755                    let sop = significant_simd_op(op0, op1, inst_flags as u32);
3756                    if !match_signature3(op0, op1, op2, inst_flags as u32) {
3757                        self.last_error = Some(AsmError::InvalidInstruction);
3758                        return;
3759                    }
3760                    let size_op = element_type_to_size_op(
3761                        op_data.vec_op_type,
3762                        sop.as_::<Reg>().reg_type(),
3763                        sop.as_::<Vec>().element_type(),
3764                    );
3765                    if !size_op.is_valid() {
3766                        self.last_error = Some(AsmError::InvalidInstruction);
3767                        return;
3768                    }
3769                    let imm_value = op3.as_::<Imm>().value() as u64;
3770                    let mut imm_size = op_data.imm_size;
3771                    if op_data.imm64_has_one_bit_less != 0 && size_op.q() == 0 {
3772                        imm_size -= 1;
3773                    }
3774                    let imm_max = 1u64 << imm_size;
3775                    if imm_value >= imm_max {
3776                        self.last_error = Some(AsmError::InvalidImmediate);
3777                        return;
3778                    }
3779                    st.opcode.reset(op_data.opcode());
3780                    st.opcode.add_imm(size_op.qs(), 30);
3781                    st.opcode.add_imm(size_op.scalar(), 28);
3782                    st.opcode.add_imm(size_op.size(), 22);
3783                    st.opcode.add_imm(imm_value as u32, op_data.imm_shift);
3784                    emit_rd0_rn5_rm16!();
3785                }
3786            }
3787
3788            Encoding::ISimdVVVV => {
3789                let op_data = &I_SIMD_VVVV[encoding_index];
3790                if isign4 == enc_ops!(Reg, Reg, Reg, Reg) {
3791                    let sop = significant_simd_op(op0, op1, inst_flags as u32);
3792                    if !match_signature4(op0, op1, op2, op3, inst_flags as u32) {
3793                        self.last_error = Some(AsmError::InvalidInstruction);
3794                        return;
3795                    }
3796                    let size_op = element_type_to_size_op(
3797                        op_data.vec_op_type,
3798                        sop.as_::<Reg>().reg_type(),
3799                        sop.as_::<Vec>().element_type(),
3800                    );
3801                    if !size_op.is_valid() {
3802                        self.last_error = Some(AsmError::InvalidInstruction);
3803                        return;
3804                    }
3805                    st.opcode.reset((op_data.opcode as u32) << 10);
3806                    st.opcode.add_imm(size_op.qs(), 30);
3807                    st.opcode.add_imm(size_op.scalar(), 28);
3808                    st.opcode.add_imm(size_op.size(), 22);
3809                    emit_rd0_rn5_rm16_ra10!();
3810                }
3811            }
3812
3813            Encoding::ISimdVVVVx => {
3814                let op_data = &I_SIMD_VVVVX[encoding_index];
3815                if isign4 == enc_ops!(Reg, Reg, Reg, Reg) {
3816                    if op0.signature().bits() != op_data.op0_signature
3817                        || op1.signature().bits() != op_data.op1_signature
3818                        || op2.signature().bits() != op_data.op2_signature
3819                        || op3.signature().bits() != op_data.op3_signature
3820                    {
3821                        self.last_error = Some(AsmError::InvalidInstruction);
3822                        return;
3823                    }
3824                    st.opcode.reset((op_data.opcode as u32) << 10);
3825                    emit_rd0_rn5_rm16_ra10!();
3826                }
3827            }
3828
3829            Encoding::ISimdPair => {
3830                let op_data = &I_SIMD_PAIR[encoding_index];
3831                if isign4 == enc_ops!(Reg, Reg) && op_data.opcode2 != 0 {
3832                    if op0.as_::<Vec>().is_vec_d1() && op1.as_::<Vec>().is_vec_d2() {
3833                        st.opcode.reset((op_data.opcode2 as u32) << 10);
3834                        st.opcode.add_imm(0x3, 22);
3835                        emit_rd0_rn5!();
3836                    }
3837                }
3838                if isign4 == enc_ops!(Reg, Reg, Reg) {
3839                    if !match_signature3(op0, op1, op2, inst_flags as u32) {
3840                        self.last_error = Some(AsmError::InvalidInstruction);
3841                        return;
3842                    }
3843                    let size_op = element_type_to_size_op(
3844                        op_data.op_type3,
3845                        op0.as_::<Reg>().reg_type(),
3846                        op0.as_::<Vec>().element_type(),
3847                    );
3848                    if !size_op.is_valid() {
3849                        self.last_error = Some(AsmError::InvalidInstruction);
3850                        return;
3851                    }
3852                    st.opcode.reset((op_data.opcode3 as u32) << 10);
3853                    st.opcode.add_imm(size_op.qs(), 30);
3854                    st.opcode.add_imm(size_op.scalar(), 28);
3855                    st.opcode.add_imm(size_op.size(), 22);
3856                    emit_rd0_rn5_rm16!();
3857                }
3858            }
3859
3860            Encoding::SimdBicOrr => {
3861                let op_data = &SIMD_BIC_ORR[encoding_index];
3862                if isign4 == enc_ops!(Reg, Reg, Reg) {
3863                    if !match_signature3(op0, op1, op2, inst_flags as u32) {
3864                        self.last_error = Some(AsmError::InvalidInstruction);
3865                        return;
3866                    }
3867                    let size_op = element_type_to_size_op(
3868                        0, // kVO_V_B
3869                        op0.as_::<Reg>().reg_type(),
3870                        op0.as_::<Vec>().element_type(),
3871                    );
3872                    if !size_op.is_valid() {
3873                        self.last_error = Some(AsmError::InvalidInstruction);
3874                        return;
3875                    }
3876                    st.opcode.reset((op_data.register_op as u32) << 10);
3877                    st.opcode.add_imm(size_op.q(), 30);
3878                    emit_rd0_rn5_rm16!();
3879                }
3880                if isign4 == enc_ops!(Reg, Imm) || isign4 == enc_ops!(Reg, Imm, Imm) {
3881                    let size_op = element_type_to_size_op(
3882                        5, // kVO_V_HS
3883                        op0.as_::<Reg>().reg_type(),
3884                        op0.as_::<Vec>().element_type(),
3885                    );
3886                    if !size_op.is_valid() {
3887                        self.last_error = Some(AsmError::InvalidInstruction);
3888                        return;
3889                    }
3890                    if op1.as_::<Imm>().value() as u64 > 0xFFFFFFFF {
3891                        self.last_error = Some(AsmError::InvalidImmediate);
3892                        return;
3893                    }
3894                    let mut imm = op1.as_::<Imm>().value() as u32;
3895                    let mut shift = 0u32;
3896                    let max_shift = (8u32 << size_op.size()) - 8u32;
3897                    if isign4 == enc_ops!(Reg, Imm, Imm) {
3898                        if op2.as_::<Imm>().predicate() != ShiftOp::LSL as u32 {
3899                            self.last_error = Some(AsmError::InvalidImmediate);
3900                            return;
3901                        }
3902                        if imm > 0xFF || op2.as_::<Imm>().value() as u64 > max_shift as u64 {
3903                            self.last_error = Some(AsmError::InvalidImmediate);
3904                            return;
3905                        }
3906                        shift = op2.as_::<Imm>().value() as u32;
3907                        if (shift & 0x7) != 0 {
3908                            self.last_error = Some(AsmError::InvalidImmediate);
3909                            return;
3910                        }
3911                    } else if imm != 0 {
3912                        shift = imm.trailing_zeros() & !0x7;
3913                        imm >>= shift;
3914                        if imm > 0xFF || shift > max_shift {
3915                            self.last_error = Some(AsmError::InvalidImmediate);
3916                            return;
3917                        }
3918                    }
3919                    let mut cmode = 0x1 | ((shift / 8) << 1);
3920                    if size_op.size() == 1 {
3921                        cmode |= 1 << 3;
3922                    }
3923                    let abc = (imm >> 5) & 0x7;
3924                    let defgh = imm & 0x1F;
3925                    st.opcode.reset((op_data.immediate_op as u32) << 10);
3926                    st.opcode.add_imm(size_op.q(), 30);
3927                    st.opcode.add_imm(abc, 16);
3928                    st.opcode.add_imm(cmode, 12);
3929                    st.opcode.add_imm(defgh, 5);
3930                    emit_rd0!();
3931                }
3932            }
3933
3934            Encoding::SimdCmp => {
3935                let op_data = &SIMD_CMP[encoding_index];
3936
3937                if isign4 == enc_ops!(Reg, Reg, Reg) && op_data.register_op != 0 {
3938                    if !match_signature3(op0, op1, op2, inst_flags as u32) {
3939                        self.last_error = Some(AsmError::InvalidInstruction);
3940                        return;
3941                    }
3942
3943                    let size_op = element_type_to_size_op(
3944                        op_data.vec_op_type,
3945                        op0.as_::<Reg>().reg_type(),
3946                        op0.as_::<Vec>().element_type(),
3947                    );
3948                    if !size_op.is_valid() {
3949                        self.last_error = Some(AsmError::InvalidInstruction);
3950                        return;
3951                    }
3952
3953                    st.opcode.reset((op_data.register_op as u32) << 10);
3954                    st.opcode.add_imm(size_op.qs(), 30);
3955                    st.opcode.add_imm(size_op.scalar(), 28);
3956                    st.opcode.add_imm(size_op.size(), 22);
3957                    emit_rd0_rn5_rm16!();
3958                }
3959
3960                if isign4 == enc_ops!(Reg, Reg, Imm) && op_data.zero_op != 0 {
3961                    if !match_signature2(op0, op1, inst_flags as u32) {
3962                        self.last_error = Some(AsmError::InvalidInstruction);
3963                        return;
3964                    }
3965
3966                    if op2.as_::<Imm>().value() != 0 {
3967                        self.last_error = Some(AsmError::InvalidImmediate);
3968                        return;
3969                    }
3970
3971                    let size_op = element_type_to_size_op(
3972                        op_data.vec_op_type,
3973                        op0.as_::<Reg>().reg_type(),
3974                        op0.as_::<Vec>().element_type(),
3975                    );
3976                    if !size_op.is_valid() {
3977                        self.last_error = Some(AsmError::InvalidInstruction);
3978                        return;
3979                    }
3980
3981                    st.opcode.reset((op_data.zero_op as u32) << 10);
3982                    st.opcode.add_imm(size_op.qs(), 30);
3983                    st.opcode.add_imm(size_op.scalar(), 28);
3984                    st.opcode.add_imm(size_op.size(), 22);
3985                    emit_rd0_rn5!();
3986                }
3987            }
3988
3989            Encoding::SimdDot => {
3990                let op_data = &SIMD_DOT[encoding_index];
3991
3992                if isign4 == enc_ops!(Reg, Reg, Reg) {
3993                    let q =
3994                        (op0.as_::<Reg>().reg_type() as u32).wrapping_sub(RegType::Vec64 as u32);
3995                    let size = 2u32;
3996
3997                    if q > 1 {
3998                        self.last_error = Some(AsmError::InvalidInstruction);
3999                        return;
4000                    }
4001
4002                    if !op2.as_::<Vec>().has_element_index() {
4003                        if op_data.vector_op == 0 {
4004                            self.last_error = Some(AsmError::InvalidInstruction);
4005                            return;
4006                        }
4007
4008                        if op0.as_::<Reg>().reg_type() != op1.as_::<Reg>().reg_type()
4009                            || op1.as_::<Reg>().reg_type() != op2.as_::<Reg>().reg_type()
4010                        {
4011                            self.last_error = Some(AsmError::InvalidInstruction);
4012                            return;
4013                        }
4014
4015                        if op0.as_::<Vec>().element_type() as u32 != op_data.ta as u32
4016                            || op1.as_::<Vec>().element_type() as u32 != op_data.tb as u32
4017                            || op2.as_::<Vec>().element_type() as u32 != op_data.tb as u32
4018                        {
4019                            self.last_error = Some(AsmError::InvalidInstruction);
4020                            return;
4021                        }
4022
4023                        st.opcode.reset((op_data.vector_op as u32) << 10);
4024                        st.opcode.add_imm(q, 30);
4025                        emit_rd0_rn5_rm16!();
4026                    } else {
4027                        if op_data.element_op == 0 {
4028                            self.last_error = Some(AsmError::InvalidInstruction);
4029                            return;
4030                        }
4031
4032                        if op0.as_::<Reg>().reg_type() != op1.as_::<Reg>().reg_type()
4033                            || !op2.as_::<Reg>().is_vec128()
4034                        {
4035                            self.last_error = Some(AsmError::InvalidInstruction);
4036                            return;
4037                        }
4038
4039                        if op0.as_::<Vec>().element_type() as u32 != op_data.ta as u32
4040                            || op1.as_::<Vec>().element_type() as u32 != op_data.tb as u32
4041                            || op2.as_::<Vec>().element_type() as u32 != op_data.t_element as u32
4042                        {
4043                            self.last_error = Some(AsmError::InvalidInstruction);
4044                            return;
4045                        }
4046
4047                        let element_index = op2.as_::<Vec>().element_index();
4048                        let mut lmh = LMHImm {
4049                            lm: 0,
4050                            h: 0,
4051                            max_rm_id: 0,
4052                        };
4053                        if !encode_lmh(size, element_index, &mut lmh) {
4054                            self.last_error = Some(AsmError::InvalidOperand);
4055                            return;
4056                        }
4057
4058                        if op2.as_::<Reg>().id() > lmh.max_rm_id {
4059                            self.last_error = Some(AsmError::InvalidOperand);
4060                            return;
4061                        }
4062
4063                        st.opcode.reset((op_data.element_op as u32) << 10);
4064                        st.opcode.add_imm(q, 30);
4065                        st.opcode.add_imm(lmh.lm, 20);
4066                        st.opcode.add_imm(lmh.h, 11);
4067                        emit_rd0_rn5_rm16!();
4068                    }
4069                }
4070            }
4071
4072            Encoding::SimdDup => {
4073                simd_dup!();
4074            }
4075
4076            Encoding::SimdIns => {
4077                simd_insn!();
4078            }
4079
4080            Encoding::SimdMov => {
4081                if isign4 == enc_ops!(Reg, Reg) {
4082                    if op0.as_::<Reg>().is_vec() && op1.as_::<Reg>().is_vec() {
4083                        // INS v.x[index], v.x[index].
4084                        if op0.as_::<Vec>().has_element_index()
4085                            && op1.as_::<Vec>().has_element_index()
4086                        {
4087                            // SimdIns encoding.
4088
4089                            encoding = Encoding::SimdIns;
4090                            // Recurse to SimdIns.
4091                            simd_insn!();
4092                            return;
4093                        }
4094                        // DUP {b|h|s|d}, v.{b|h|s|d}[index].
4095                        if op1.as_::<Vec>().has_element_index() {
4096                            encoding = Encoding::SimdDup;
4097                            simd_dup!();
4098                            return;
4099                        }
4100                        if !check_signature!(op0, op1) {
4101                            self.last_error = Some(AsmError::InvalidInstruction);
4102                            return;
4103                        }
4104                        let q = (op0.as_::<Reg>().reg_type() as u32)
4105                            .wrapping_sub(RegType::Vec64 as u32);
4106                        if q > 1 {
4107                            self.last_error = Some(AsmError::InvalidInstruction);
4108                            return;
4109                        }
4110                        st.opcode.reset(0b0000111010100000000111 << 10);
4111                        st.opcode.add_imm(q, 30);
4112                        st.opcode.add_reg(op1.id(), 16);
4113                        emit_rd0_rn5!();
4114                        return;
4115                    }
4116                    if op0.as_::<Reg>().is_vec() && op1.as_::<Reg>().is_gp() {
4117                        // INS v.x[index], Rn.
4118                        if op0.as_::<Vec>().has_element_index() {
4119                            encoding = Encoding::SimdIns;
4120                            simd_insn!();
4121                            return;
4122                        }
4123                        self.last_error = Some(AsmError::InvalidInstruction);
4124                        return;
4125                    }
4126                    if op0.as_::<Reg>().is_gp() && op1.as_::<Reg>().is_vec() {
4127                        // UMOV Rd, V.{s|d}[index].
4128                        encoding_index = 1;
4129                        encoding = Encoding::SimdSmovUmov;
4130                        simd_umov!();
4131                        return;
4132                    }
4133                }
4134            }
4135
4136            Encoding::SimdMoviMvni => {
4137                let op_data = &SIMD_MOVI_MVNI[encoding_index];
4138                if isign4 == enc_ops!(Reg, Imm) || isign4 == enc_ops!(Reg, Imm, Imm) {
4139                    let mut size_op = element_type_to_size_op(
4140                        20,
4141                        op0.as_::<Reg>().reg_type(),
4142                        op0.as_::<Vec>().element_type(),
4143                    );
4144                    if !size_op.is_valid() {
4145                        self.last_error = Some(AsmError::InvalidInstruction);
4146                        return;
4147                    }
4148                    let mut imm64 = op1.as_::<Imm>().value() as u64;
4149                    let mut imm8 = 0u32;
4150                    let mut cmode = 0u32;
4151                    let inverted = op_data.inverted;
4152                    let mut op = 0u32;
4153                    let mut shift = 0u32;
4154                    let mut shift_op = ShiftOp::LSL as u32;
4155                    if size_op.size() == 3 {
4156                        if op2.is_imm() && op2.as_::<Imm>().value() != 0 {
4157                            self.last_error = Some(AsmError::InvalidImmediate);
4158                            return;
4159                        }
4160                        if is_byte_mask_imm(imm64) {
4161                            imm8 = encode_imm64_byte_mask_to_imm8(imm64);
4162                        } else {
4163                            if (imm64 >> 32) == (imm64 & 0xFFFFFFFF) {
4164                                imm64 &= 0xFFFFFFFF;
4165                                size_op.decrement_size();
4166                            } else {
4167                                self.last_error = Some(AsmError::InvalidImmediate);
4168                                return;
4169                            }
4170                        }
4171                    }
4172                    if size_op.size() < 3 {
4173                        if imm64 > 0xFFFFFFFF {
4174                            self.last_error = Some(AsmError::InvalidImmediate);
4175                            return;
4176                        }
4177                        imm8 = imm64 as u32;
4178                        if size_op.size() == 2 {
4179                            if (imm8 >> 16) == (imm8 & 0xFFFF) {
4180                                imm8 >>= 16;
4181                                size_op.decrement_size();
4182                            }
4183                        }
4184                        if size_op.size() == 1 {
4185                            if imm8 > 0xFFFF {
4186                                self.last_error = Some(AsmError::InvalidImmediate);
4187                                return;
4188                            }
4189                            if (imm8 >> 8) == (imm8 & 0xFF) {
4190                                imm8 >>= 8;
4191                                size_op.decrement_size();
4192                            }
4193                        }
4194                        let max_shift = (8u32 << size_op.size()) - 8u32;
4195                        if op2.is_imm() {
4196                            if imm8 > 0xFF || op2.as_::<Imm>().value() as u64 > max_shift as u64 {
4197                                self.last_error = Some(AsmError::InvalidImmediate);
4198                                return;
4199                            }
4200                            shift = op2.as_::<Imm>().value() as u32;
4201                            shift_op = op2.as_::<Imm>().predicate();
4202                        } else if imm8 != 0 {
4203                            shift = imm8.trailing_zeros() & !0x7;
4204                            imm8 >>= shift;
4205                            if imm8 > 0xFF || shift > max_shift {
4206                                self.last_error = Some(AsmError::InvalidImmediate);
4207                                return;
4208                            }
4209                        }
4210                        if (shift & 0x7) != 0 {
4211                            self.last_error = Some(AsmError::InvalidImmediate);
4212                            return;
4213                        }
4214                    }
4215                    shift /= 8;
4216                    match size_op.size() {
4217                        0 => {
4218                            if shift_op != ShiftOp::LSL as u32 {
4219                                self.last_error = Some(AsmError::InvalidImmediate);
4220                                return;
4221                            }
4222                            if inverted != 0 {
4223                                imm8 = !imm8 & 0xFF;
4224                            }
4225                            cmode = B!(3) | B!(2) | B!(1);
4226                        }
4227                        1 => {
4228                            if shift_op != ShiftOp::LSL as u32 {
4229                                self.last_error = Some(AsmError::InvalidImmediate);
4230                                return;
4231                            }
4232                            cmode = B!(3) | (shift << 1);
4233                            op = inverted;
4234                        }
4235                        2 => {
4236                            if shift_op == ShiftOp::LSL as u32 {
4237                                cmode = shift << 1;
4238                            } else if shift_op == ShiftOp::MSL as u32 {
4239                                if shift == 0 || shift > 2 {
4240                                    self.last_error = Some(AsmError::InvalidImmediate);
4241                                    return;
4242                                }
4243                                cmode = B!(3) | B!(2) | (shift - 1);
4244                            } else {
4245                                self.last_error = Some(AsmError::InvalidImmediate);
4246                                return;
4247                            }
4248                            op = inverted;
4249                        }
4250                        3 => {
4251                            if inverted != 0 {
4252                                imm8 = !imm8 & 0xFF;
4253                            }
4254                            op = 1;
4255                            cmode = B!(3) | B!(2) | B!(1);
4256                        }
4257                        _ => {}
4258                    }
4259                    let abc = (imm8 >> 5) & 0x7;
4260                    let defgh = imm8 & 0x1F;
4261                    st.opcode.reset((op_data.opcode as u32) << 10);
4262                    st.opcode.add_imm(size_op.q(), 30);
4263                    st.opcode.add_imm(op, 29);
4264                    st.opcode.add_imm(abc, 16);
4265                    st.opcode.add_imm(cmode, 12);
4266                    st.opcode.add_imm(defgh, 5);
4267                    emit_rd0!();
4268                    return;
4269                }
4270            }
4271
4272            Encoding::SimdShift => {
4273                let op_data = &SIMD_SHIFT[encoding_index];
4274                let sop = significant_simd_op(op0, op1, inst_flags as u32);
4275                let size_op = element_type_to_size_op(
4276                    op_data.vec_op_type,
4277                    sop.as_::<Reg>().reg_type(),
4278                    sop.as_::<Vec>().element_type(),
4279                );
4280                if !size_op.is_valid() {
4281                    self.last_error = Some(AsmError::InvalidInstruction);
4282                    return;
4283                }
4284                if isign4 == enc_ops!(Reg, Reg, Imm) && op_data.immediate_op != 0 {
4285                    if !match_signature2(op0, op1, inst_flags as u32) {
4286                        self.last_error = Some(AsmError::InvalidInstruction);
4287                        return;
4288                    }
4289                    if op2.as_::<Imm>().value() as u64 > 63 {
4290                        self.last_error = Some(AsmError::InvalidImmediate);
4291                        return;
4292                    }
4293                    let lsb_shift = size_op.size() + 3;
4294                    let lsb_mask = (1u32 << lsb_shift) - 1;
4295                    let mut imm = op2.as_::<Imm>().value() as u32;
4296                    if op_data.inverted_imm != 0 {
4297                        if imm == 0 || imm > (1u32 << lsb_shift) {
4298                            self.last_error = Some(AsmError::InvalidImmediate);
4299                            return;
4300                        }
4301                        imm = (!imm + 1) & lsb_mask;
4302                    }
4303                    if imm > lsb_mask {
4304                        self.last_error = Some(AsmError::InvalidImmediate);
4305                        return;
4306                    }
4307                    imm |= 1u32 << lsb_shift;
4308                    st.opcode.reset((op_data.immediate_op as u32) << 10);
4309                    st.opcode.add_imm(size_op.qs(), 30);
4310                    st.opcode.add_imm(size_op.scalar(), 28);
4311                    st.opcode.add_imm(imm, 16);
4312                    emit_rd0_rn5!();
4313                    return;
4314                }
4315                if isign4 == enc_ops!(Reg, Reg, Reg) && op_data.register_op != 0 {
4316                    if !match_signature3(op0, op1, op2, inst_flags as u32) {
4317                        self.last_error = Some(AsmError::InvalidInstruction);
4318                        return;
4319                    }
4320                    st.opcode.reset((op_data.register_op as u32) << 10);
4321                    st.opcode.add_imm(size_op.qs(), 30);
4322                    st.opcode.add_imm(size_op.scalar(), 28);
4323                    st.opcode.add_imm(size_op.size(), 22);
4324                    emit_rd0_rn5_rm16!();
4325                    return;
4326                }
4327            }
4328
4329            Encoding::SimdShiftES => {
4330                let op_data = &SIMD_SHIFT_ES[encoding_index];
4331                if isign4 == enc_ops!(Reg, Reg, Imm) {
4332                    let size_op = element_type_to_size_op(
4333                        op_data.vec_op_type,
4334                        op1.as_::<Reg>().reg_type(),
4335                        op1.as_::<Vec>().element_type(),
4336                    );
4337                    if !size_op.is_valid() {
4338                        self.last_error = Some(AsmError::InvalidInstruction);
4339                        return;
4340                    }
4341                    if !match_signature2(op0, op1, inst_flags as u32) {
4342                        self.last_error = Some(AsmError::InvalidInstruction);
4343                        return;
4344                    }
4345                    let shift = op2.as_::<Imm>().value() as u64;
4346                    let shift_op = op2.as_::<Imm>().predicate();
4347                    if shift != (8u64 << size_op.size()) || shift_op != ShiftOp::LSL as u32 {
4348                        self.last_error = Some(AsmError::InvalidImmediate);
4349                        return;
4350                    }
4351                    st.opcode.reset((op_data.opcode as u32) << 10);
4352                    st.opcode.add_imm(size_op.q(), 30);
4353                    st.opcode.add_imm(size_op.size(), 22);
4354                    emit_rd0_rn5!();
4355                    return;
4356                }
4357            }
4358
4359            Encoding::SimdSm3tt => {
4360                let op_data = &SIMD_SM3TT[encoding_index];
4361                if isign4 == enc_ops!(Reg, Reg, Reg) {
4362                    if op0.as_::<Vec>().is_vec_s4()
4363                        && op1.as_::<Vec>().is_vec_s4()
4364                        && op2.as_::<Vec>().is_vec_s4()
4365                        && op2.as_::<Vec>().has_element_index()
4366                    {
4367                        let imm2 = op2.as_::<Vec>().element_index();
4368                        if imm2 > 3 {
4369                            self.last_error = Some(AsmError::InvalidOperand);
4370                            return;
4371                        }
4372                        st.opcode.reset((op_data.opcode as u32) << 10);
4373                        st.opcode.add_imm(imm2, 12);
4374                        emit_rd0_rn5_rm16!();
4375                        return;
4376                    }
4377                }
4378            }
4379
4380            Encoding::SimdSmovUmov => {
4381                simd_umov!();
4382            }
4383
4384            Encoding::SimdSxtlUxtl => {
4385                let op_data = &SIMD_SXTL_UXTL[encoding_index];
4386                if isign4 == enc_ops!(Reg, Reg) {
4387                    let size_op = element_type_to_size_op(
4388                        op_data.vec_op_type,
4389                        op1.as_::<Reg>().reg_type(),
4390                        op1.as_::<Vec>().element_type(),
4391                    );
4392                    if !size_op.is_valid() {
4393                        self.last_error = Some(AsmError::InvalidInstruction);
4394                        return;
4395                    }
4396                    if !match_signature2(op0, op1, inst_flags as u32) {
4397                        self.last_error = Some(AsmError::InvalidInstruction);
4398                        return;
4399                    }
4400                    st.opcode.reset((op_data.opcode as u32) << 10);
4401                    st.opcode.add_imm(size_op.q(), 30);
4402                    st.opcode.add_imm(1u32, size_op.size() + 19);
4403                    emit_rd0_rn5!();
4404                    return;
4405                }
4406            }
4407
4408            Encoding::SimdTblTbx => {
4409                let op_data = &SIMD_TBL_TBX[encoding_index];
4410                if isign4 == enc_ops!(Reg, Reg, Reg) || isign4 == enc_ops!(Reg, Reg, Reg, Reg) {
4411                    st.opcode.reset((op_data.opcode as u32) << 10);
4412
4413                    let q =
4414                        (op0.as_::<Reg>().reg_type() as u32).wrapping_sub(RegType::Vec64 as u32);
4415                    if q > 1 || op0.as_::<Vec>().has_element_index() {
4416                        self.last_error = Some(AsmError::InvalidInstruction);
4417                        return;
4418                    }
4419                    if !op1.as_::<Vec>().is_vec_b16() || op1.as_::<Vec>().has_element_index() {
4420                        self.last_error = Some(AsmError::InvalidInstruction);
4421                        return;
4422                    }
4423                    let len =
4424                        (!op3.is_none() as u32) + (!op4.is_none() as u32) + (!op5.is_none() as u32);
4425                    st.opcode.add_imm(q, 30);
4426                    st.opcode.add_imm(len, 13);
4427
4428                    match len {
4429                        0 => {
4430                            if !check_signature!(op0, op2) {
4431                                self.last_error = Some(AsmError::InvalidInstruction);
4432                                return;
4433                            }
4434                            if op2.id() > 31 {
4435                                self.last_error = Some(AsmError::InvalidOperand);
4436                                return;
4437                            }
4438                            st.opcode.add_reg(op2.id(), 16);
4439                            emit_rd0_rn5!();
4440                            return;
4441                        }
4442                        1 => {
4443                            if !check_signature!(op0, op3) {
4444                                self.last_error = Some(AsmError::InvalidInstruction);
4445                                return;
4446                            }
4447                            if op3.id() > 31 {
4448                                self.last_error = Some(AsmError::InvalidOperand);
4449                                return;
4450                            }
4451                            st.opcode.add_reg(op3.id(), 16);
4452                            emit_rd0_rn5!();
4453                            return;
4454                        }
4455                        2 => {
4456                            if !check_signature!(op0, op4) {
4457                                self.last_error = Some(AsmError::InvalidInstruction);
4458                                return;
4459                            }
4460                            if op4.id() > 31 {
4461                                self.last_error = Some(AsmError::InvalidOperand);
4462                                return;
4463                            }
4464                            st.opcode.add_reg(op4.id(), 16);
4465                            emit_rd0_rn5!();
4466                            return;
4467                        }
4468                        3 => {
4469                            if !check_signature!(op0, op5) {
4470                                self.last_error = Some(AsmError::InvalidInstruction);
4471                                return;
4472                            }
4473                            if op5.id() > 31 {
4474                                self.last_error = Some(AsmError::InvalidOperand);
4475                                return;
4476                            }
4477                            st.opcode.add_reg(op5.id(), 16);
4478                            emit_rd0_rn5!();
4479                            return;
4480                        }
4481                        _ => {
4482                            self.last_error = Some(AsmError::InvalidInstruction);
4483                            return;
4484                        }
4485                    }
4486                }
4487            }
4488
4489            Encoding::SimdLdSt => {
4490                let op_data = &SIMD_LD_ST[encoding_index];
4491                if isign4 == enc_ops!(Reg, Mem) {
4492                    let m = op1.as_::<Mem>();
4493                    st.rm_rel = *op1;
4494
4495                    let xsz =
4496                        (op0.as_::<Reg>().reg_type() as u32).wrapping_sub(RegType::Vec8 as u32);
4497                    if xsz > 4 || op0.as_::<Vec>().has_element_index() {
4498                        self.last_error = Some(AsmError::InvalidOperand);
4499                        return;
4500                    }
4501
4502                    if !check_vec_id(op0) {
4503                        self.last_error = Some(AsmError::InvalidOperand);
4504                        return;
4505                    }
4506
4507                    // TODO: check_mem_base_index_rel(m)
4508                    let offset = m.offset();
4509                    if m.has_base_reg() {
4510                        if m.has_index() {
4511                            let opt = SHIFT_OP_TO_LD_ST_OP_MAP[m.shift_op() as usize];
4512                            if opt == 0xFF {
4513                                self.last_error = Some(AsmError::InvalidOperand);
4514                                return;
4515                            }
4516                            let shift = m.shift();
4517                            let s = if shift != 0 { 1 } else { 0 };
4518                            if s != 0 && shift != xsz {
4519                                self.last_error = Some(AsmError::InvalidOperand);
4520                                return;
4521                            }
4522                            st.opcode.reset((op_data.register_op as u32) << 21);
4523                            st.opcode.add_imm(xsz & 3, 30);
4524                            st.opcode.add_imm(xsz >> 2, 23);
4525                            st.opcode.add_imm(opt as u32, 13);
4526                            st.opcode.add_imm(s, 12);
4527                            st.opcode.0 |= 1 << 11;
4528                            st.opcode.add_reg(op0.id(), 0);
4529                            st.opcode.add_reg(m.base_id(), 5);
4530                            st.opcode.add_reg(m.index_id(), 16);
4531                            emit_op!();
4532                        }
4533
4534                        let offset32 = offset as i32;
4535                        if m.is_pre_or_post() {
4536                            if offset32 < -256 || offset32 > 255 {
4537                                self.last_error = Some(AsmError::InvalidOperand);
4538                                return;
4539                            }
4540                            st.opcode.reset((op_data.pre_post_op as u32) << 21);
4541                            st.opcode.add_imm(xsz & 3, 30);
4542                            st.opcode.add_imm(xsz >> 2, 23);
4543                            st.opcode.add_imm((offset32 as u32) & 0x1FF, 12);
4544                            st.opcode.add_imm(m.is_pre_index() as u32, 11);
4545                            st.opcode.0 |= 1 << 10;
4546                            st.opcode.add_reg(op0.id(), 0);
4547                            st.opcode.add_reg(m.base_id(), 5);
4548                            emit_op!();
4549                        } else {
4550                            let imm12 = (offset32 as u32) >> xsz;
4551                            if imm12 >= (1 << 12) || ((imm12 << xsz) as i32) != offset32 {
4552                                // Fallback to SimdLdurStur
4553                                let op_data_ldur = &SIMD_LDUR_STUR[encoding_index];
4554                                if m.has_base_reg() && !m.has_index() && !m.is_pre_or_post() {
4555                                    if offset32 < -256 || offset32 > 255 {
4556                                        self.last_error = Some(AsmError::InvalidOperand);
4557                                        return;
4558                                    }
4559                                    st.opcode.reset((op_data_ldur.opcode as u32) << 10);
4560                                    st.opcode.add_imm(xsz & 3, 30);
4561                                    st.opcode.add_imm(xsz >> 2, 23);
4562                                    st.opcode.add_imm((offset32 as u32) & 0x1FF, 12);
4563                                    st.opcode.add_reg(op0.id(), 0);
4564                                    st.opcode.add_reg(m.base_id(), 5);
4565                                    emit_op!();
4566                                }
4567                                self.last_error = Some(AsmError::InvalidOperand);
4568                                return;
4569                            }
4570                            st.opcode.reset((op_data.u_offset_op as u32) << 22);
4571                            st.opcode.add_imm(xsz & 3, 30);
4572                            st.opcode.add_imm(xsz >> 2, 23);
4573                            st.opcode.add_imm(imm12, 10);
4574                            st.opcode.add_reg(op0.id(), 0);
4575                            st.opcode.add_reg(m.base_id(), 5);
4576                            emit_op!();
4577                        }
4578                    } else {
4579                        if op_data.literal_op == 0 {
4580                            self.last_error = Some(AsmError::InvalidOperand);
4581                            return;
4582                        }
4583                        if xsz < 2 {
4584                            self.last_error = Some(AsmError::InvalidOperand);
4585                            return;
4586                        }
4587                        let opc = xsz - 2;
4588                        st.opcode.reset((op_data.literal_op as u32) << 24);
4589                        st.opcode.add_imm(opc, 30);
4590                        st.opcode.add_reg(op0.id(), 0);
4591                        st.offset_format
4592                            .reset_to_imm_type(OffsetType::SignedOffset, 4, 5, 19, 2);
4593                        st.rm_rel = *op1;
4594                        emit_rel!();
4595                    }
4596                }
4597            }
4598
4599            Encoding::SimdLdpStp => {
4600                let op_data = &SIMD_LDP_STP[encoding_index];
4601                if isign4 == enc_ops!(Reg, Reg, Mem) {
4602                    let m = op2.as_::<Mem>();
4603                    st.rm_rel = *op2;
4604
4605                    let opc =
4606                        (op0.as_::<Reg>().reg_type() as u32).wrapping_sub(RegType::Vec32 as u32);
4607                    if opc > 2
4608                        || op0.as_::<Vec>().has_element_type()
4609                        || op0.as_::<Vec>().has_element_index()
4610                    {
4611                        self.last_error = Some(AsmError::InvalidInstruction);
4612                        return;
4613                    }
4614                    if !check_signature!(op0, op1) {
4615                        self.last_error = Some(AsmError::InvalidInstruction);
4616                        return;
4617                    }
4618                    if !check_vec_id2(op0, op1) {
4619                        self.last_error = Some(AsmError::InvalidOperand);
4620                        return;
4621                    }
4622                    if m.base_type() != RegType::Gp64 || m.has_index() {
4623                        self.last_error = Some(AsmError::InvalidOperand);
4624                        return;
4625                    }
4626                    let offset_shift = 2 + opc;
4627                    let offset32 = m.offset() as i32 >> offset_shift;
4628                    if ((offset32 << offset_shift) as i32) != m.offset() as i32 {
4629                        self.last_error = Some(AsmError::InvalidOperand);
4630                        return;
4631                    }
4632                    if offset32 < -64 || offset32 > 63 {
4633                        self.last_error = Some(AsmError::InvalidOperand);
4634                        return;
4635                    }
4636                    if m.is_pre_or_post() && offset32 != 0 {
4637                        if op_data.pre_post_op == 0 {
4638                            self.last_error = Some(AsmError::InvalidOperand);
4639                            return;
4640                        }
4641                        st.opcode.reset((op_data.pre_post_op as u32) << 22);
4642                        st.opcode.add_imm(m.is_pre_index() as u32, 24);
4643                    } else {
4644                        st.opcode.reset((op_data.offset_op as u32) << 22);
4645                    }
4646                    st.opcode.add_imm(opc, 30);
4647                    st.opcode.add_imm((offset32 as u32) & 0x7F, 15);
4648                    st.opcode.add_reg(op1.id(), 10);
4649                    st.opcode.add_reg(op0.id(), 0);
4650                    st.opcode.add_reg(m.base_id(), 5);
4651                    emit_op!();
4652                }
4653            }
4654
4655            Encoding::SimdLdurStur => {
4656                let op_data = &SIMD_LDUR_STUR[encoding_index];
4657                if isign4 == enc_ops!(Reg, Mem) {
4658                    let m = op1.as_::<Mem>();
4659                    st.rm_rel = *op1;
4660
4661                    let sz =
4662                        (op0.as_::<Reg>().reg_type() as u32).wrapping_sub(RegType::Vec8 as u32);
4663                    if sz > 4
4664                        || op0.as_::<Vec>().has_element_type()
4665                        || op0.as_::<Vec>().has_element_index()
4666                    {
4667                        self.last_error = Some(AsmError::InvalidInstruction);
4668                        return;
4669                    }
4670                    if !check_vec_id(op0) {
4671                        self.last_error = Some(AsmError::InvalidOperand);
4672                        return;
4673                    }
4674                    if m.has_base_reg() && !m.has_index() && !m.is_pre_or_post() {
4675                        let offset32 = m.offset() as i32;
4676                        if offset32 < -256 || offset32 > 255 {
4677                            self.last_error = Some(AsmError::InvalidOperand);
4678                            return;
4679                        }
4680                        st.opcode.reset((op_data.opcode as u32) << 10);
4681                        st.opcode.add_imm(sz & 3, 30);
4682                        st.opcode.add_imm(sz >> 2, 23);
4683                        st.opcode.add_imm((offset32 as u32) & 0x1FF, 12);
4684                        st.opcode.add_reg(op0.id(), 0);
4685                        st.opcode.add_reg(m.base_id(), 5);
4686                        emit_op!();
4687                    }
4688                    self.last_error = Some(AsmError::InvalidOperand);
4689                    return;
4690                }
4691            }
4692
4693            Encoding::SimdLdNStN => {
4694                let op_data = &SIMD_LD_N_ST_N[encoding_index];
4695                let o4 = *ops.get(4).unwrap_or(&NOREG);
4696
4697                let mut n = 1;
4698
4699                if isign4 == enc_ops!(Reg, Mem) {
4700                    if op_data.n != 1 {
4701                        self.last_error = Some(AsmError::InvalidInstruction);
4702                        return;
4703                    }
4704                    st.rm_rel = *op1;
4705                } else if isign4 == enc_ops!(Reg, Reg, Mem) {
4706                    if op_data.n != 1 && op_data.n != 2 {
4707                        self.last_error = Some(AsmError::InvalidInstruction);
4708                        return;
4709                    }
4710                    if !check_signature!(op0, op1) || op0.id() + 1 != op1.id() {
4711                        self.last_error = Some(AsmError::InvalidInstruction);
4712                        return;
4713                    }
4714                    n = 2;
4715                    st.rm_rel = *op2;
4716                } else if isign4 == enc_ops!(Reg, Reg, Reg, Mem) && o4.is_none() {
4717                    if op_data.n != 1 && op_data.n != 3 {
4718                        self.last_error = Some(AsmError::InvalidInstruction);
4719                        return;
4720                    }
4721                    if !check_signature!(op0, op1, op2)
4722                        || op0.id() + 1 != op1.id()
4723                        || op1.id() + 1 != op2.id()
4724                    {
4725                        self.last_error = Some(AsmError::InvalidInstruction);
4726                        return;
4727                    }
4728                    n = 3;
4729                    st.rm_rel = *op3;
4730                } else if isign4 == enc_ops!(Reg, Reg, Reg, Reg) && o4.is_mem() {
4731                    if op_data.n != 1 && op_data.n != 4 {
4732                        self.last_error = Some(AsmError::InvalidInstruction);
4733                        return;
4734                    }
4735                    if !check_signature!(op0, op1, op2, op3)
4736                        || op0.id() + 1 != op1.id()
4737                        || op1.id() + 1 != op2.id()
4738                        || op2.id() + 1 != op3.id()
4739                    {
4740                        self.last_error = Some(AsmError::InvalidInstruction);
4741                        return;
4742                    }
4743                    n = 4;
4744                    st.rm_rel = *o4;
4745                } else {
4746                    self.last_error = Some(AsmError::InvalidInstruction);
4747                    return;
4748                }
4749
4750                let v = op0.as_::<Vec>();
4751                let m = st.rm_rel.as_::<Mem>();
4752
4753                let mut q = 0u32;
4754                let mut rm = 0u32;
4755                let mut rn = m.base_id();
4756                let sz = (v.element_type() as u32).wrapping_sub(VecElementType::B as u32);
4757                let mut opc_s_size = sz;
4758                let mut offset_possibility = 0u32;
4759
4760                if sz > 3 {
4761                    self.last_error = Some(AsmError::InvalidInstruction);
4762                    return;
4763                }
4764
4765                if m.base_type() != RegType::Gp64 {
4766                    self.last_error = Some(AsmError::InvalidOperand);
4767                    return;
4768                }
4769
4770                if rn > 30 && rn != Gp::ID_SP {
4771                    self.last_error = Some(AsmError::InvalidOperand);
4772                    return;
4773                }
4774
4775                rn &= 31;
4776
4777                if op_data.replicate != 0 {
4778                    if n != op_data.n {
4779                        self.last_error = Some(AsmError::InvalidInstruction);
4780                        return;
4781                    }
4782                    if v.has_element_index() {
4783                        self.last_error = Some(AsmError::InvalidInstruction);
4784                        return;
4785                    }
4786                    q = (v.reg_type() as u32).wrapping_sub(RegType::Vec64 as u32);
4787                    if q > 1 {
4788                        self.last_error = Some(AsmError::InvalidInstruction);
4789                        return;
4790                    }
4791                    st.opcode.reset((op_data.single_op as u32) << 10);
4792                    offset_possibility = (1u32 << sz) * n;
4793                } else if v.has_element_index() {
4794                    if n != op_data.n {
4795                        self.last_error = Some(AsmError::InvalidInstruction);
4796                        return;
4797                    }
4798                    const OPC_S_SIZE_BY_SZ_TABLE: [u32; 4] =
4799                        [0u32 << 3, 2u32 << 3, 4u32 << 3, (4u32 << 3) | 1u32];
4800                    st.opcode.reset((op_data.single_op as u32) << 10);
4801                    opc_s_size = OPC_S_SIZE_BY_SZ_TABLE[sz as usize];
4802                    offset_possibility = (1u32 << sz) * op_data.n;
4803                    let element_index = v.element_index();
4804                    let max_element_index = 15u32 >> sz;
4805                    if element_index > max_element_index {
4806                        self.last_error = Some(AsmError::InvalidOperand);
4807                        return;
4808                    }
4809                    let element_index_shifted = element_index << sz;
4810                    q = element_index_shifted >> 3;
4811                    opc_s_size |= element_index_shifted & 0x7;
4812                } else {
4813                    const OPC_S_SIZE_BY_N_TABLE: [u32; 5] =
4814                        [0u32, 0x7u32 << 2, 0xAu32 << 2, 0x6u32 << 2, 0x2u32 << 2];
4815                    q = (v.reg_type() as u32).wrapping_sub(RegType::Vec64 as u32);
4816                    if q > 1 {
4817                        self.last_error = Some(AsmError::InvalidInstruction);
4818                        return;
4819                    }
4820                    if op_data.n == 1 {
4821                        opc_s_size |= OPC_S_SIZE_BY_N_TABLE[n as usize];
4822                    }
4823                    st.opcode.reset((op_data.multiple_op as u32) << 10);
4824                    offset_possibility = (8u32 << q) * n;
4825                }
4826
4827                if m.has_index() {
4828                    if m.has_offset() || !m.is_post_index() {
4829                        self.last_error = Some(AsmError::InvalidOperand);
4830                        return;
4831                    }
4832                    rm = m.index_id();
4833                    if rm > 30 {
4834                        self.last_error = Some(AsmError::InvalidOperand);
4835                        return;
4836                    }
4837                    st.opcode.0 |= 1 << 23;
4838                } else {
4839                    if m.has_offset() {
4840                        if m.offset() != offset_possibility as i64 || !m.is_post_index() {
4841                            self.last_error = Some(AsmError::InvalidOperand);
4842                            return;
4843                        }
4844                        rm = 31;
4845                        st.opcode.0 |= 1 << 23;
4846                    }
4847                }
4848
4849                st.opcode.add_imm(q, 30);
4850                st.opcode.add_imm(rm, 16);
4851                st.opcode.add_imm(opc_s_size, 10);
4852                st.opcode.add_imm(rn, 5);
4853
4854                st.opcode.add_reg(op0.id(), 0);
4855                emit_op!();
4856            }
4857
4858            Encoding::None | Encoding::Count => (),
4859        }
4860
4861        self.last_error = Some(AsmError::UnsupportedInstruction {
4862            reason: "Unsupported instruction encoding or operand types",
4863        });
4864    }
4865}
4866
4867// @generated AArch64 target features begin
4868/// AArch64 architectural features present in the pinned AsmJit ISA metadata.
4869#[derive(Clone, Copy, Debug, PartialEq, Eq, PartialOrd, Ord)]
4870#[repr(u8)]
4871pub enum CpuFeature {
4872    Aes,
4873    Asimd,
4874    Bf16,
4875    Bti,
4876    Chk,
4877    Clrbhb,
4878    Crc32,
4879    Cssc,
4880    Dgh,
4881    Dotprod,
4882    Fcma,
4883    Fhm,
4884    Flagm,
4885    Flagm2,
4886    Fp16,
4887    Fp8,
4888    Frintts,
4889    I8Mm,
4890    Jscvt,
4891    Lor,
4892    Lse,
4893    Mte,
4894    Mte2,
4895    Pauth,
4896    Ras,
4897    Rdm,
4898    Sha1,
4899    Sha256,
4900    Sha3,
4901    Sha512,
4902    Sm3,
4903    Sm4,
4904}
4905
4906pub const CPU_FEATURE_COUNT: usize = 32;
4907pub const CPU_FEATURE_NAMES: [&str; CPU_FEATURE_COUNT] = [
4908    "AES", "ASIMD", "BF16", "BTI", "CHK", "CLRBHB", "CRC32", "CSSC", "DGH", "DOTPROD", "FCMA",
4909    "FHM", "FLAGM", "FLAGM2", "FP16", "FP8", "FRINTTS", "I8MM", "JSCVT", "LOR", "LSE", "MTE",
4910    "MTE2", "PAUTH", "RAS", "RDM", "SHA1", "SHA256", "SHA3", "SHA512", "SM3", "SM4",
4911];
4912
4913pub const ALL_CPU_FEATURES: [CpuFeature; CPU_FEATURE_COUNT] = [
4914    CpuFeature::Aes,
4915    CpuFeature::Asimd,
4916    CpuFeature::Bf16,
4917    CpuFeature::Bti,
4918    CpuFeature::Chk,
4919    CpuFeature::Clrbhb,
4920    CpuFeature::Crc32,
4921    CpuFeature::Cssc,
4922    CpuFeature::Dgh,
4923    CpuFeature::Dotprod,
4924    CpuFeature::Fcma,
4925    CpuFeature::Fhm,
4926    CpuFeature::Flagm,
4927    CpuFeature::Flagm2,
4928    CpuFeature::Fp16,
4929    CpuFeature::Fp8,
4930    CpuFeature::Frintts,
4931    CpuFeature::I8Mm,
4932    CpuFeature::Jscvt,
4933    CpuFeature::Lor,
4934    CpuFeature::Lse,
4935    CpuFeature::Mte,
4936    CpuFeature::Mte2,
4937    CpuFeature::Pauth,
4938    CpuFeature::Ras,
4939    CpuFeature::Rdm,
4940    CpuFeature::Sha1,
4941    CpuFeature::Sha256,
4942    CpuFeature::Sha3,
4943    CpuFeature::Sha512,
4944    CpuFeature::Sm3,
4945    CpuFeature::Sm4,
4946];
4947
4948impl CpuFeature {
4949    pub const fn name(self) -> &'static str {
4950        CPU_FEATURE_NAMES[self as usize]
4951    }
4952}
4953
4954const FEATURE_FORM_SIGNATURE_MASK: u32 = OperandSignature::OP_TYPE_MASK
4955    | OperandSignature::REG_TYPE_MASK
4956    | Vec::SIGNATURE_REG_ELEMENT_TYPE_MASK
4957    | Vec::SIGNATURE_REG_ELEMENT_FLAG_MASK;
4958
4959const fn feature_reg_signature(
4960    reg_type: RegType,
4961    element_type: VecElementType,
4962    element_access: bool,
4963) -> u32 {
4964    OperandType::Reg as u32
4965        | (reg_type as u32) << OperandSignature::REG_TYPE_SHIFT
4966        | (element_type as u32) << Vec::SIGNATURE_REG_ELEMENT_TYPE_SHIFT
4967        | (element_access as u32) << Vec::SIGNATURE_REG_ELEMENT_FLAG_SHIFT
4968}
4969
4970struct InstFeatureForm {
4971    opcode_mask: u32,
4972    opcode_value: u32,
4973    operand_signatures: [u32; 6],
4974    required: u64,
4975    context: &'static str,
4976}
4977
4978impl InstFeatureForm {
4979    fn matches(&self, opcode: u32, ops: &[&Operand]) -> bool {
4980        if opcode & self.opcode_mask != self.opcode_value {
4981            return false;
4982        }
4983        self.operand_signatures
4984            .iter()
4985            .enumerate()
4986            .all(|(index, expected)| {
4987                let actual = ops.get(index).map_or(0, |op| op.signature.bits());
4988                actual & FEATURE_FORM_SIGNATURE_MASK == *expected
4989            })
4990    }
4991}
4992
4993/// Conservative required-feature masks, indexed by `InstId as usize`.
4994pub static INST_FEATURE_MASKS: [u64; InstId::_Count as usize] = [
4995    0x0000000000000000, // None
4996    0x0000000000000080, // Abs
4997    0x0000000000000000, // Adc
4998    0x0000000000000000, // Adcs
4999    0x0000000000000000, // Add
5000    0x0000000000200000, // Addg
5001    0x0000000000000000, // Adds
5002    0x0000000000000000, // Adr
5003    0x0000000000000000, // Adrp
5004    0x0000000000000000, // And
5005    0x0000000000000000, // Ands
5006    0x0000000000000000, // Asr
5007    0x0000000000000000, // Asrv
5008    0x0000000000000000, // At
5009    0x0000000000800000, // Autda
5010    0x0000000000800000, // Autdza
5011    0x0000000000800000, // Autdb
5012    0x0000000000800000, // Autdzb
5013    0x0000000000800000, // Autia
5014    0x0000000000800000, // Autia1716
5015    0x0000000000800000, // Autiasp
5016    0x0000000000800000, // Autiaz
5017    0x0000000000800000, // Autib
5018    0x0000000000800000, // Autib1716
5019    0x0000000000800000, // Autibsp
5020    0x0000000000800000, // Autibz
5021    0x0000000000800000, // Autiza
5022    0x0000000000800000, // Autizb
5023    0x0000000000002000, // Axflag
5024    0x0000000000000000, // B
5025    0x0000000000000000, // Bc
5026    0x0000000000000000, // Bfc
5027    0x0000000000000000, // Bfi
5028    0x0000000000000000, // Bfm
5029    0x0000000000000000, // Bfxil
5030    0x0000000000000000, // Bic
5031    0x0000000000000000, // Bics
5032    0x0000000000000000, // Bl
5033    0x0000000000000000, // Blr
5034    0x0000000000000000, // Br
5035    0x0000000000000000, // Brk
5036    0x0000000000000008, // Bti
5037    0x0000000000100000, // Cas
5038    0x0000000000100000, // Casa
5039    0x0000000000100000, // Casab
5040    0x0000000000100000, // Casah
5041    0x0000000000100000, // Casal
5042    0x0000000000100000, // Casalb
5043    0x0000000000100000, // Casalh
5044    0x0000000000100000, // Casb
5045    0x0000000000100000, // Cash
5046    0x0000000000100000, // Casl
5047    0x0000000000100000, // Caslb
5048    0x0000000000100000, // Caslh
5049    0x0000000000100000, // Casp
5050    0x0000000000100000, // Caspa
5051    0x0000000000100000, // Caspal
5052    0x0000000000100000, // Caspl
5053    0x0000000000000000, // Cbnz
5054    0x0000000000000000, // Cbz
5055    0x0000000000000000, // Ccmn
5056    0x0000000000000000, // Ccmp
5057    0x0000000000001000, // Cfinv
5058    0x0000000000000010, // Chkfeat
5059    0x0000000000000000, // Cinc
5060    0x0000000000000000, // Cinv
5061    0x0000000000000020, // Clrbhb
5062    0x0000000000000000, // Clrex
5063    0x0000000000000000, // Cls
5064    0x0000000000000000, // Clz
5065    0x0000000000000000, // Cmn
5066    0x0000000000000000, // Cmp
5067    0x0000000000200000, // Cmpp
5068    0x0000000000000000, // Cneg
5069    0x0000000000000080, // Cnt
5070    0x0000000000000040, // Crc32b
5071    0x0000000000000040, // Crc32cb
5072    0x0000000000000040, // Crc32ch
5073    0x0000000000000040, // Crc32cw
5074    0x0000000000000040, // Crc32cx
5075    0x0000000000000040, // Crc32h
5076    0x0000000000000040, // Crc32w
5077    0x0000000000000040, // Crc32x
5078    0x0000000000000000, // Csdb
5079    0x0000000000000000, // Csel
5080    0x0000000000000000, // Cset
5081    0x0000000000000000, // Csetm
5082    0x0000000000000000, // Csinc
5083    0x0000000000000000, // Csinv
5084    0x0000000000000000, // Csneg
5085    0x0000000000000080, // Ctz
5086    0x0000000000000000, // Dc
5087    0x0000000000000000, // Dcps1
5088    0x0000000000000000, // Dcps2
5089    0x0000000000000000, // Dcps3
5090    0x0000000000000100, // Dgh
5091    0x0000000000000000, // Dmb
5092    0x0000000000000000, // Drps
5093    0x0000000000000000, // Dsb
5094    0x0000000000000000, // Eon
5095    0x0000000000000000, // Eor
5096    0x0000000001000000, // Esb
5097    0x0000000000000000, // Extr
5098    0x0000000000000000, // Eret
5099    0x0000000000200000, // Gmi
5100    0x0000000000000000, // Hint
5101    0x0000000000000000, // Hlt
5102    0x0000000000000000, // Hvc
5103    0x0000000000000000, // Ic
5104    0x0000000000000000, // Isb
5105    0x0000000000100000, // Ldadd
5106    0x0000000000100000, // Ldadda
5107    0x0000000000100000, // Ldaddab
5108    0x0000000000100000, // Ldaddah
5109    0x0000000000100000, // Ldaddal
5110    0x0000000000100000, // Ldaddalb
5111    0x0000000000100000, // Ldaddalh
5112    0x0000000000100000, // Ldaddb
5113    0x0000000000100000, // Ldaddh
5114    0x0000000000100000, // Ldaddl
5115    0x0000000000100000, // Ldaddlb
5116    0x0000000000100000, // Ldaddlh
5117    0x0000000000000000, // Ldar
5118    0x0000000000000000, // Ldarb
5119    0x0000000000000000, // Ldarh
5120    0x0000000000000000, // Ldaxp
5121    0x0000000000000000, // Ldaxr
5122    0x0000000000000000, // Ldaxrb
5123    0x0000000000000000, // Ldaxrh
5124    0x0000000000100000, // Ldclr
5125    0x0000000000100000, // Ldclra
5126    0x0000000000100000, // Ldclrab
5127    0x0000000000100000, // Ldclrah
5128    0x0000000000100000, // Ldclral
5129    0x0000000000100000, // Ldclralb
5130    0x0000000000100000, // Ldclralh
5131    0x0000000000100000, // Ldclrb
5132    0x0000000000100000, // Ldclrh
5133    0x0000000000100000, // Ldclrl
5134    0x0000000000100000, // Ldclrlb
5135    0x0000000000100000, // Ldclrlh
5136    0x0000000000100000, // Ldeor
5137    0x0000000000100000, // Ldeora
5138    0x0000000000100000, // Ldeorab
5139    0x0000000000100000, // Ldeorah
5140    0x0000000000100000, // Ldeoral
5141    0x0000000000100000, // Ldeoralb
5142    0x0000000000100000, // Ldeoralh
5143    0x0000000000100000, // Ldeorb
5144    0x0000000000100000, // Ldeorh
5145    0x0000000000100000, // Ldeorl
5146    0x0000000000100000, // Ldeorlb
5147    0x0000000000100000, // Ldeorlh
5148    0x0000000000200000, // Ldg
5149    0x0000000000400000, // Ldgm
5150    0x0000000000080000, // Ldlar
5151    0x0000000000080000, // Ldlarb
5152    0x0000000000080000, // Ldlarh
5153    0x0000000000000000, // Ldnp
5154    0x0000000000000000, // Ldp
5155    0x0000000000000000, // Ldpsw
5156    0x0000000000000000, // Ldr
5157    0x0000000000800000, // Ldraa
5158    0x0000000000800000, // Ldrab
5159    0x0000000000000000, // Ldrb
5160    0x0000000000000000, // Ldrh
5161    0x0000000000000000, // Ldrsb
5162    0x0000000000000000, // Ldrsh
5163    0x0000000000000000, // Ldrsw
5164    0x0000000000100000, // Ldset
5165    0x0000000000100000, // Ldseta
5166    0x0000000000100000, // Ldsetab
5167    0x0000000000100000, // Ldsetah
5168    0x0000000000100000, // Ldsetal
5169    0x0000000000100000, // Ldsetalb
5170    0x0000000000100000, // Ldsetalh
5171    0x0000000000100000, // Ldsetb
5172    0x0000000000100000, // Ldseth
5173    0x0000000000100000, // Ldsetl
5174    0x0000000000100000, // Ldsetlb
5175    0x0000000000100000, // Ldsetlh
5176    0x0000000000100000, // Ldsmax
5177    0x0000000000100000, // Ldsmaxa
5178    0x0000000000100000, // Ldsmaxab
5179    0x0000000000100000, // Ldsmaxah
5180    0x0000000000100000, // Ldsmaxal
5181    0x0000000000100000, // Ldsmaxalb
5182    0x0000000000100000, // Ldsmaxalh
5183    0x0000000000100000, // Ldsmaxb
5184    0x0000000000100000, // Ldsmaxh
5185    0x0000000000100000, // Ldsmaxl
5186    0x0000000000100000, // Ldsmaxlb
5187    0x0000000000100000, // Ldsmaxlh
5188    0x0000000000100000, // Ldsmin
5189    0x0000000000100000, // Ldsmina
5190    0x0000000000100000, // Ldsminab
5191    0x0000000000100000, // Ldsminah
5192    0x0000000000100000, // Ldsminal
5193    0x0000000000100000, // Ldsminalb
5194    0x0000000000100000, // Ldsminalh
5195    0x0000000000100000, // Ldsminb
5196    0x0000000000100000, // Ldsminh
5197    0x0000000000100000, // Ldsminl
5198    0x0000000000100000, // Ldsminlb
5199    0x0000000000100000, // Ldsminlh
5200    0x0000000000000000, // Ldtr
5201    0x0000000000000000, // Ldtrb
5202    0x0000000000000000, // Ldtrh
5203    0x0000000000000000, // Ldtrsb
5204    0x0000000000000000, // Ldtrsh
5205    0x0000000000000000, // Ldtrsw
5206    0x0000000000100000, // Ldumax
5207    0x0000000000100000, // Ldumaxa
5208    0x0000000000100000, // Ldumaxab
5209    0x0000000000100000, // Ldumaxah
5210    0x0000000000100000, // Ldumaxal
5211    0x0000000000100000, // Ldumaxalb
5212    0x0000000000100000, // Ldumaxalh
5213    0x0000000000100000, // Ldumaxb
5214    0x0000000000100000, // Ldumaxh
5215    0x0000000000100000, // Ldumaxl
5216    0x0000000000100000, // Ldumaxlb
5217    0x0000000000100000, // Ldumaxlh
5218    0x0000000000100000, // Ldumin
5219    0x0000000000100000, // Ldumina
5220    0x0000000000100000, // Lduminab
5221    0x0000000000100000, // Lduminah
5222    0x0000000000100000, // Lduminal
5223    0x0000000000100000, // Lduminalb
5224    0x0000000000100000, // Lduminalh
5225    0x0000000000100000, // Lduminb
5226    0x0000000000100000, // Lduminh
5227    0x0000000000100000, // Lduminl
5228    0x0000000000100000, // Lduminlb
5229    0x0000000000100000, // Lduminlh
5230    0x0000000000000000, // Ldur
5231    0x0000000000000000, // Ldurb
5232    0x0000000000000000, // Ldurh
5233    0x0000000000000000, // Ldursb
5234    0x0000000000000000, // Ldursh
5235    0x0000000000000000, // Ldursw
5236    0x0000000000000000, // Ldxp
5237    0x0000000000000000, // Ldxr
5238    0x0000000000000000, // Ldxrb
5239    0x0000000000000000, // Ldxrh
5240    0x0000000000000000, // Lsl
5241    0x0000000000000000, // Lslv
5242    0x0000000000000000, // Lsr
5243    0x0000000000000000, // Lsrv
5244    0x0000000000000000, // Madd
5245    0x0000000000000000, // Mneg
5246    0x0000000000000000, // Mov
5247    0x0000000000000000, // Movk
5248    0x0000000000000000, // Movn
5249    0x0000000000000000, // Movz
5250    0x0000000000000000, // Mrs
5251    0x0000000000000000, // Msr
5252    0x0000000000000000, // Msub
5253    0x0000000000000000, // Mul
5254    0x0000000000000000, // Mvn
5255    0x0000000000000000, // Neg
5256    0x0000000000000000, // Negs
5257    0x0000000000000000, // Ngc
5258    0x0000000000000000, // Ngcs
5259    0x0000000000000000, // Nop
5260    0x0000000000000000, // Orn
5261    0x0000000000000000, // Orr
5262    0x0000000000800000, // Pacda
5263    0x0000000000800000, // Pacdb
5264    0x0000000000800000, // Pacdza
5265    0x0000000000800000, // Pacdzb
5266    0x0000000000800000, // Pacga
5267    0x0000000000000000, // Prfm
5268    0x0000000000000000, // Pssbb
5269    0x0000000000000000, // Rbit
5270    0x0000000000000000, // Ret
5271    0x0000000000000000, // Rev
5272    0x0000000000000000, // Rev16
5273    0x0000000000000000, // Rev32
5274    0x0000000000000000, // Rev64
5275    0x0000000000000000, // Ror
5276    0x0000000000000000, // Rorv
5277    0x0000000000000000, // Sbc
5278    0x0000000000000000, // Sbcs
5279    0x0000000000000000, // Sbfiz
5280    0x0000000000000000, // Sbfm
5281    0x0000000000000000, // Sbfx
5282    0x0000000000000000, // Sdiv
5283    0x0000000000001000, // Setf8
5284    0x0000000000001000, // Setf16
5285    0x0000000000000000, // Sev
5286    0x0000000000000000, // Sevl
5287    0x0000000000000000, // Smaddl
5288    0x0000000000000080, // Smax
5289    0x0000000000000000, // Smc
5290    0x0000000000000080, // Smin
5291    0x0000000000000000, // Smnegl
5292    0x0000000000000000, // Smsubl
5293    0x0000000000000000, // Smulh
5294    0x0000000000000000, // Smull
5295    0x0000000000000000, // Ssbb
5296    0x0000000000200000, // St2g
5297    0x0000000000100000, // Stadd
5298    0x0000000000100000, // Staddl
5299    0x0000000000100000, // Staddb
5300    0x0000000000100000, // Staddlb
5301    0x0000000000100000, // Staddh
5302    0x0000000000100000, // Staddlh
5303    0x0000000000100000, // Stclr
5304    0x0000000000100000, // Stclrl
5305    0x0000000000100000, // Stclrb
5306    0x0000000000100000, // Stclrlb
5307    0x0000000000100000, // Stclrh
5308    0x0000000000100000, // Stclrlh
5309    0x0000000000100000, // Steor
5310    0x0000000000100000, // Steorl
5311    0x0000000000100000, // Steorb
5312    0x0000000000100000, // Steorlb
5313    0x0000000000100000, // Steorh
5314    0x0000000000100000, // Steorlh
5315    0x0000000000200000, // Stg
5316    0x0000000000400000, // Stgm
5317    0x0000000000200000, // Stgp
5318    0x0000000000080000, // Stllr
5319    0x0000000000080000, // Stllrb
5320    0x0000000000080000, // Stllrh
5321    0x0000000000000000, // Stlr
5322    0x0000000000000000, // Stlrb
5323    0x0000000000000000, // Stlrh
5324    0x0000000000000000, // Stlxp
5325    0x0000000000000000, // Stlxr
5326    0x0000000000000000, // Stlxrb
5327    0x0000000000000000, // Stlxrh
5328    0x0000000000000000, // Stnp
5329    0x0000000000000000, // Stp
5330    0x0000000000000000, // Str
5331    0x0000000000000000, // Strb
5332    0x0000000000000000, // Strh
5333    0x0000000000100000, // Stset
5334    0x0000000000100000, // Stsetl
5335    0x0000000000100000, // Stsetb
5336    0x0000000000100000, // Stsetlb
5337    0x0000000000100000, // Stseth
5338    0x0000000000100000, // Stsetlh
5339    0x0000000000100000, // Stsmax
5340    0x0000000000100000, // Stsmaxl
5341    0x0000000000100000, // Stsmaxb
5342    0x0000000000100000, // Stsmaxlb
5343    0x0000000000100000, // Stsmaxh
5344    0x0000000000100000, // Stsmaxlh
5345    0x0000000000100000, // Stsmin
5346    0x0000000000100000, // Stsminl
5347    0x0000000000100000, // Stsminb
5348    0x0000000000100000, // Stsminlb
5349    0x0000000000100000, // Stsminh
5350    0x0000000000100000, // Stsminlh
5351    0x0000000000000000, // Sttr
5352    0x0000000000000000, // Sttrb
5353    0x0000000000000000, // Sttrh
5354    0x0000000000100000, // Stumax
5355    0x0000000000100000, // Stumaxl
5356    0x0000000000100000, // Stumaxb
5357    0x0000000000100000, // Stumaxlb
5358    0x0000000000100000, // Stumaxh
5359    0x0000000000100000, // Stumaxlh
5360    0x0000000000100000, // Stumin
5361    0x0000000000100000, // Stuminl
5362    0x0000000000100000, // Stuminb
5363    0x0000000000100000, // Stuminlb
5364    0x0000000000100000, // Stuminh
5365    0x0000000000100000, // Stuminlh
5366    0x0000000000000000, // Stur
5367    0x0000000000000000, // Sturb
5368    0x0000000000000000, // Sturh
5369    0x0000000000000000, // Stxp
5370    0x0000000000000000, // Stxr
5371    0x0000000000000000, // Stxrb
5372    0x0000000000000000, // Stxrh
5373    0x0000000000200000, // Stz2g
5374    0x0000000000200000, // Stzg
5375    0x0000000000400000, // Stzgm
5376    0x0000000000000000, // Sub
5377    0x0000000000200000, // Subg
5378    0x0000000000200000, // Subp
5379    0x0000000000200000, // Subps
5380    0x0000000000000000, // Subs
5381    0x0000000000000000, // Svc
5382    0x0000000000100000, // Swp
5383    0x0000000000100000, // Swpa
5384    0x0000000000100000, // Swpab
5385    0x0000000000100000, // Swpah
5386    0x0000000000100000, // Swpal
5387    0x0000000000100000, // Swpalb
5388    0x0000000000100000, // Swpalh
5389    0x0000000000100000, // Swpb
5390    0x0000000000100000, // Swph
5391    0x0000000000100000, // Swpl
5392    0x0000000000100000, // Swplb
5393    0x0000000000100000, // Swplh
5394    0x0000000000000000, // Sxtb
5395    0x0000000000000000, // Sxth
5396    0x0000000000000000, // Sxtw
5397    0x0000000000000000, // Sys
5398    0x0000000000000000, // Tlbi
5399    0x0000000000000000, // Tst
5400    0x0000000000000000, // Tbnz
5401    0x0000000000000000, // Tbz
5402    0x0000000000000000, // Ubfiz
5403    0x0000000000000000, // Ubfm
5404    0x0000000000000000, // Ubfx
5405    0x0000000000000000, // Udf
5406    0x0000000000000000, // Udiv
5407    0x0000000000000000, // Umaddl
5408    0x0000000000000080, // Umax
5409    0x0000000000000080, // Umin
5410    0x0000000000000000, // Umnegl
5411    0x0000000000000000, // Umull
5412    0x0000000000000000, // Umulh
5413    0x0000000000000000, // Umsubl
5414    0x0000000000000000, // Uxtb
5415    0x0000000000000000, // Uxth
5416    0x0000000000000000, // Wfe
5417    0x0000000000000000, // Wfi
5418    0x0000000000002000, // Xaflag
5419    0x0000000000800000, // Xpacd
5420    0x0000000000800000, // Xpaci
5421    0x0000000000800000, // Xpaclri
5422    0x0000000000000000, // Yield
5423    0x0000000000000002, // Abs_v
5424    0x0000000000000002, // Add_v
5425    0x0000000000000002, // Addhn_v
5426    0x0000000000000002, // Addhn2_v
5427    0x0000000000000002, // Addp_v
5428    0x0000000000000002, // Addv_v
5429    0x0000000000000003, // Aesd_v
5430    0x0000000000000003, // Aese_v
5431    0x0000000000000003, // Aesimc_v
5432    0x0000000000000003, // Aesmc_v
5433    0x0000000000000002, // And_v
5434    0x0000000010000002, // Bcax_v
5435    0x0000000000000006, // Bfcvt_v
5436    0x0000000000000006, // Bfcvtn_v
5437    0x0000000000000006, // Bfcvtn2_v
5438    0x0000000000000006, // Bfdot_v
5439    0x0000000000000006, // Bfmlalb_v
5440    0x0000000000000006, // Bfmlalt_v
5441    0x0000000000000006, // Bfmmla_v
5442    0x0000000000000002, // Bic_v
5443    0x0000000000000002, // Bif_v
5444    0x0000000000000002, // Bit_v
5445    0x0000000000000002, // Bsl_v
5446    0x0000000000000002, // Cls_v
5447    0x0000000000000002, // Clz_v
5448    0x0000000000000002, // Cmeq_v
5449    0x0000000000000002, // Cmge_v
5450    0x0000000000000002, // Cmgt_v
5451    0x0000000000000002, // Cmhi_v
5452    0x0000000000000002, // Cmhs_v
5453    0x0000000000000002, // Cmle_v
5454    0x0000000000000002, // Cmlt_v
5455    0x0000000000000002, // Cmtst_v
5456    0x0000000000000002, // Cnt_v
5457    0x0000000000000002, // Dup_v
5458    0x0000000000000002, // Eor_v
5459    0x0000000010000002, // Eor3_v
5460    0x0000000000000002, // Ext_v
5461    0x0000000000004002, // Fabd_v
5462    0x0000000000004002, // Fabs_v
5463    0x0000000000004002, // Facge_v
5464    0x0000000000004002, // Facgt_v
5465    0x0000000000004002, // Fadd_v
5466    0x0000000000004002, // Faddp_v
5467    0x0000000000000402, // Fcadd_v
5468    0x0000000000004002, // Fccmp_v
5469    0x0000000000004002, // Fccmpe_v
5470    0x0000000000004002, // Fcmeq_v
5471    0x0000000000004002, // Fcmge_v
5472    0x0000000000004002, // Fcmgt_v
5473    0x0000000000000402, // Fcmla_v
5474    0x0000000000004002, // Fcmle_v
5475    0x0000000000004002, // Fcmlt_v
5476    0x0000000000004002, // Fcmp_v
5477    0x0000000000004002, // Fcmpe_v
5478    0x0000000000004002, // Fcsel_v
5479    0x0000000000000002, // Fcvt_v
5480    0x0000000000004002, // Fcvtas_v
5481    0x0000000000004002, // Fcvtau_v
5482    0x0000000000000002, // Fcvtl_v
5483    0x0000000000000002, // Fcvtl2_v
5484    0x0000000000004002, // Fcvtms_v
5485    0x0000000000004002, // Fcvtmu_v
5486    0x0000000000008002, // Fcvtn_v
5487    0x0000000000008002, // Fcvtn2_v
5488    0x0000000000004002, // Fcvtns_v
5489    0x0000000000004002, // Fcvtnu_v
5490    0x0000000000004002, // Fcvtps_v
5491    0x0000000000004002, // Fcvtpu_v
5492    0x0000000000000000, // Fcvtxn_v
5493    0x0000000000000000, // Fcvtxn2_v
5494    0x0000000000004002, // Fcvtzs_v
5495    0x0000000000004002, // Fcvtzu_v
5496    0x0000000000004002, // Fdiv_v
5497    0x0000000000040002, // Fjcvtzs_v
5498    0x0000000000004002, // Fmadd_v
5499    0x0000000000004002, // Fmax_v
5500    0x0000000000004002, // Fmaxnm_v
5501    0x0000000000004002, // Fmaxnmp_v
5502    0x0000000000004002, // Fmaxnmv_v
5503    0x0000000000004002, // Fmaxp_v
5504    0x0000000000004002, // Fmaxv_v
5505    0x0000000000004002, // Fmin_v
5506    0x0000000000004002, // Fminnm_v
5507    0x0000000000004002, // Fminnmp_v
5508    0x0000000000004002, // Fminnmv_v
5509    0x0000000000004002, // Fminp_v
5510    0x0000000000004002, // Fminv_v
5511    0x0000000000004002, // Fmla_v
5512    0x0000000000000802, // Fmlal_v
5513    0x0000000000000802, // Fmlal2_v
5514    0x0000000000004002, // Fmls_v
5515    0x0000000000000802, // Fmlsl_v
5516    0x0000000000000802, // Fmlsl2_v
5517    0x0000000000004002, // Fmov_v
5518    0x0000000000004002, // Fmsub_v
5519    0x0000000000004002, // Fmul_v
5520    0x0000000000004002, // Fmulx_v
5521    0x0000000000004002, // Fneg_v
5522    0x0000000000004002, // Fnmadd_v
5523    0x0000000000004002, // Fnmsub_v
5524    0x0000000000004002, // Fnmul_v
5525    0x0000000000004002, // Frecpe_v
5526    0x0000000000004002, // Frecps_v
5527    0x0000000000004002, // Frecpx_v
5528    0x0000000000010002, // Frint32x_v
5529    0x0000000000010002, // Frint32z_v
5530    0x0000000000010002, // Frint64x_v
5531    0x0000000000010002, // Frint64z_v
5532    0x0000000000004002, // Frinta_v
5533    0x0000000000004002, // Frinti_v
5534    0x0000000000004002, // Frintm_v
5535    0x0000000000004002, // Frintn_v
5536    0x0000000000004002, // Frintp_v
5537    0x0000000000004002, // Frintx_v
5538    0x0000000000004002, // Frintz_v
5539    0x0000000000004002, // Frsqrte_v
5540    0x0000000000004002, // Frsqrts_v
5541    0x0000000000004002, // Fsqrt_v
5542    0x0000000000004002, // Fsub_v
5543    0x0000000000000002, // Ins_v
5544    0x0000000000000002, // Ld1_v
5545    0x0000000000000002, // Ld1r_v
5546    0x0000000000000002, // Ld2_v
5547    0x0000000000000002, // Ld2r_v
5548    0x0000000000000002, // Ld3_v
5549    0x0000000000000002, // Ld3r_v
5550    0x0000000000000002, // Ld4_v
5551    0x0000000000000002, // Ld4r_v
5552    0x0000000000000002, // Ldnp_v
5553    0x0000000000000002, // Ldp_v
5554    0x0000000000000002, // Ldr_v
5555    0x0000000000000002, // Ldur_v
5556    0x0000000000000002, // Mla_v
5557    0x0000000000000002, // Mls_v
5558    0x0000000000000002, // Mov_v
5559    0x0000000000000002, // Movi_v
5560    0x0000000000000002, // Mul_v
5561    0x0000000000000002, // Mvn_v
5562    0x0000000000000002, // Mvni_v
5563    0x0000000000000002, // Neg_v
5564    0x0000000000000002, // Not_v
5565    0x0000000000000002, // Orn_v
5566    0x0000000000000002, // Orr_v
5567    0x0000000000000002, // Pmul_v
5568    0x0000000000000002, // Pmull_v
5569    0x0000000000000002, // Pmull2_v
5570    0x0000000000000002, // Raddhn_v
5571    0x0000000000000002, // Raddhn2_v
5572    0x0000000010000002, // Rax1_v
5573    0x0000000000000002, // Rbit_v
5574    0x0000000000000002, // Rev16_v
5575    0x0000000000000002, // Rev32_v
5576    0x0000000000000002, // Rev64_v
5577    0x0000000000000002, // Rshrn_v
5578    0x0000000000000002, // Rshrn2_v
5579    0x0000000000000002, // Rsubhn_v
5580    0x0000000000000002, // Rsubhn2_v
5581    0x0000000000000002, // Saba_v
5582    0x0000000000000002, // Sabal_v
5583    0x0000000000000002, // Sabal2_v
5584    0x0000000000000002, // Sabd_v
5585    0x0000000000000002, // Sabdl_v
5586    0x0000000000000002, // Sabdl2_v
5587    0x0000000000000002, // Sadalp_v
5588    0x0000000000000002, // Saddl_v
5589    0x0000000000000002, // Saddl2_v
5590    0x0000000000000002, // Saddlp_v
5591    0x0000000000000002, // Saddlv_v
5592    0x0000000000000002, // Saddw_v
5593    0x0000000000000002, // Saddw2_v
5594    0x0000000000004002, // Scvtf_v
5595    0x0000000000000202, // Sdot_v
5596    0x0000000004000002, // Sha1c_v
5597    0x0000000004000002, // Sha1h_v
5598    0x0000000004000002, // Sha1m_v
5599    0x0000000004000002, // Sha1p_v
5600    0x0000000004000002, // Sha1su0_v
5601    0x0000000004000002, // Sha1su1_v
5602    0x0000000008000002, // Sha256h_v
5603    0x0000000008000002, // Sha256h2_v
5604    0x0000000008000002, // Sha256su0_v
5605    0x0000000008000002, // Sha256su1_v
5606    0x0000000020000002, // Sha512h_v
5607    0x0000000020000002, // Sha512h2_v
5608    0x0000000020000002, // Sha512su0_v
5609    0x0000000020000002, // Sha512su1_v
5610    0x0000000000000002, // Shadd_v
5611    0x0000000000000002, // Shl_v
5612    0x0000000000000002, // Shll_v
5613    0x0000000000000002, // Shll2_v
5614    0x0000000000000002, // Shrn_v
5615    0x0000000000000002, // Shrn2_v
5616    0x0000000000000002, // Shsub_v
5617    0x0000000000000002, // Sli_v
5618    0x0000000040000002, // Sm3partw1_v
5619    0x0000000040000002, // Sm3partw2_v
5620    0x0000000040000002, // Sm3ss1_v
5621    0x0000000040000002, // Sm3tt1a_v
5622    0x0000000040000002, // Sm3tt1b_v
5623    0x0000000040000002, // Sm3tt2a_v
5624    0x0000000040000002, // Sm3tt2b_v
5625    0x0000000080000002, // Sm4e_v
5626    0x0000000080000002, // Sm4ekey_v
5627    0x0000000000000002, // Smax_v
5628    0x0000000000000002, // Smaxp_v
5629    0x0000000000000002, // Smaxv_v
5630    0x0000000000000002, // Smin_v
5631    0x0000000000000002, // Sminp_v
5632    0x0000000000000002, // Sminv_v
5633    0x0000000000000002, // Smlal_v
5634    0x0000000000000002, // Smlal2_v
5635    0x0000000000000002, // Smlsl_v
5636    0x0000000000000002, // Smlsl2_v
5637    0x0000000000020002, // Smmla_v
5638    0x0000000000000002, // Smov_v
5639    0x0000000000000002, // Smull_v
5640    0x0000000000000002, // Smull2_v
5641    0x0000000000000002, // Sqabs_v
5642    0x0000000000000002, // Sqadd_v
5643    0x0000000000000002, // Sqdmlal_v
5644    0x0000000000000002, // Sqdmlal2_v
5645    0x0000000000000002, // Sqdmlsl_v
5646    0x0000000000000002, // Sqdmlsl2_v
5647    0x0000000000000002, // Sqdmulh_v
5648    0x0000000000000002, // Sqdmull_v
5649    0x0000000000000002, // Sqdmull2_v
5650    0x0000000000000002, // Sqneg_v
5651    0x0000000002000002, // Sqrdmlah_v
5652    0x0000000002000002, // Sqrdmlsh_v
5653    0x0000000000000002, // Sqrdmulh_v
5654    0x0000000000000002, // Sqrshl_v
5655    0x0000000000000002, // Sqrshrn_v
5656    0x0000000000000002, // Sqrshrn2_v
5657    0x0000000000000002, // Sqrshrun_v
5658    0x0000000000000002, // Sqrshrun2_v
5659    0x0000000000000002, // Sqshl_v
5660    0x0000000000000002, // Sqshlu_v
5661    0x0000000000000002, // Sqshrn_v
5662    0x0000000000000002, // Sqshrn2_v
5663    0x0000000000000002, // Sqshrun_v
5664    0x0000000000000002, // Sqshrun2_v
5665    0x0000000000000002, // Sqsub_v
5666    0x0000000000000002, // Sqxtn_v
5667    0x0000000000000002, // Sqxtn2_v
5668    0x0000000000000002, // Sqxtun_v
5669    0x0000000000000002, // Sqxtun2_v
5670    0x0000000000000002, // Srhadd_v
5671    0x0000000000000002, // Sri_v
5672    0x0000000000000002, // Srshl_v
5673    0x0000000000000002, // Srshr_v
5674    0x0000000000000002, // Srsra_v
5675    0x0000000000000002, // Sshl_v
5676    0x0000000000000002, // Sshll_v
5677    0x0000000000000002, // Sshll2_v
5678    0x0000000000000002, // Sshr_v
5679    0x0000000000000002, // Ssra_v
5680    0x0000000000000002, // Ssubl_v
5681    0x0000000000000002, // Ssubl2_v
5682    0x0000000000000002, // Ssubw_v
5683    0x0000000000000002, // Ssubw2_v
5684    0x0000000000000002, // St1_v
5685    0x0000000000000002, // St2_v
5686    0x0000000000000002, // St3_v
5687    0x0000000000000002, // St4_v
5688    0x0000000000000002, // Stnp_v
5689    0x0000000000000002, // Stp_v
5690    0x0000000000000002, // Str_v
5691    0x0000000000000002, // Stur_v
5692    0x0000000000000002, // Sub_v
5693    0x0000000000000002, // Subhn_v
5694    0x0000000000000002, // Subhn2_v
5695    0x0000000000020002, // Sudot_v
5696    0x0000000000000002, // Suqadd_v
5697    0x0000000000000002, // Sxtl_v
5698    0x0000000000000002, // Sxtl2_v
5699    0x0000000000000002, // Tbl_v
5700    0x0000000000000002, // Tbx_v
5701    0x0000000000000002, // Trn1_v
5702    0x0000000000000002, // Trn2_v
5703    0x0000000000000002, // Uaba_v
5704    0x0000000000000002, // Uabal_v
5705    0x0000000000000002, // Uabal2_v
5706    0x0000000000000002, // Uabd_v
5707    0x0000000000000002, // Uabdl_v
5708    0x0000000000000002, // Uabdl2_v
5709    0x0000000000000002, // Uadalp_v
5710    0x0000000000000002, // Uaddl_v
5711    0x0000000000000002, // Uaddl2_v
5712    0x0000000000000002, // Uaddlp_v
5713    0x0000000000000002, // Uaddlv_v
5714    0x0000000000000002, // Uaddw_v
5715    0x0000000000000002, // Uaddw2_v
5716    0x0000000000004002, // Ucvtf_v
5717    0x0000000000000202, // Udot_v
5718    0x0000000000000002, // Uhadd_v
5719    0x0000000000000002, // Uhsub_v
5720    0x0000000000000002, // Umax_v
5721    0x0000000000000002, // Umaxp_v
5722    0x0000000000000002, // Umaxv_v
5723    0x0000000000000002, // Umin_v
5724    0x0000000000000002, // Uminp_v
5725    0x0000000000000002, // Uminv_v
5726    0x0000000000000002, // Umlal_v
5727    0x0000000000000002, // Umlal2_v
5728    0x0000000000000002, // Umlsl_v
5729    0x0000000000000002, // Umlsl2_v
5730    0x0000000000020002, // Ummla_v
5731    0x0000000000000002, // Umov_v
5732    0x0000000000000002, // Umull_v
5733    0x0000000000000002, // Umull2_v
5734    0x0000000000000002, // Uqadd_v
5735    0x0000000000000002, // Uqrshl_v
5736    0x0000000000000002, // Uqrshrn_v
5737    0x0000000000000002, // Uqrshrn2_v
5738    0x0000000000000002, // Uqshl_v
5739    0x0000000000000002, // Uqshrn_v
5740    0x0000000000000002, // Uqshrn2_v
5741    0x0000000000000002, // Uqsub_v
5742    0x0000000000000002, // Uqxtn_v
5743    0x0000000000000002, // Uqxtn2_v
5744    0x0000000000000002, // Urecpe_v
5745    0x0000000000000002, // Urhadd_v
5746    0x0000000000000002, // Urshl_v
5747    0x0000000000000002, // Urshr_v
5748    0x0000000000000002, // Ursqrte_v
5749    0x0000000000000002, // Ursra_v
5750    0x0000000000020002, // Usdot_v
5751    0x0000000000000002, // Ushl_v
5752    0x0000000000000002, // Ushll_v
5753    0x0000000000000002, // Ushll2_v
5754    0x0000000000000002, // Ushr_v
5755    0x0000000000020002, // Usmmla_v
5756    0x0000000000000002, // Usqadd_v
5757    0x0000000000000002, // Usra_v
5758    0x0000000000000002, // Usubl_v
5759    0x0000000000000002, // Usubl2_v
5760    0x0000000000000002, // Usubw_v
5761    0x0000000000000002, // Usubw2_v
5762    0x0000000000000002, // Uxtl_v
5763    0x0000000000000002, // Uxtl2_v
5764    0x0000000000000002, // Uzp1_v
5765    0x0000000000000002, // Uzp2_v
5766    0x0000000010000002, // Xar_v
5767    0x0000000000000002, // Xtn_v
5768    0x0000000000000002, // Xtn2_v
5769    0x0000000000000002, // Zip1_v
5770    0x0000000000000002, // Zip2_v
5771];
5772
5773/// Requirements common to every form, indexed by `InstId as usize`.
5774static INST_BASE_FEATURE_MASKS: [u64; InstId::_Count as usize] = [
5775    0x0000000000000000, // None
5776    0x0000000000000080, // Abs
5777    0x0000000000000000, // Adc
5778    0x0000000000000000, // Adcs
5779    0x0000000000000000, // Add
5780    0x0000000000200000, // Addg
5781    0x0000000000000000, // Adds
5782    0x0000000000000000, // Adr
5783    0x0000000000000000, // Adrp
5784    0x0000000000000000, // And
5785    0x0000000000000000, // Ands
5786    0x0000000000000000, // Asr
5787    0x0000000000000000, // Asrv
5788    0x0000000000000000, // At
5789    0x0000000000800000, // Autda
5790    0x0000000000800000, // Autdza
5791    0x0000000000800000, // Autdb
5792    0x0000000000800000, // Autdzb
5793    0x0000000000800000, // Autia
5794    0x0000000000800000, // Autia1716
5795    0x0000000000800000, // Autiasp
5796    0x0000000000800000, // Autiaz
5797    0x0000000000800000, // Autib
5798    0x0000000000800000, // Autib1716
5799    0x0000000000800000, // Autibsp
5800    0x0000000000800000, // Autibz
5801    0x0000000000800000, // Autiza
5802    0x0000000000800000, // Autizb
5803    0x0000000000002000, // Axflag
5804    0x0000000000000000, // B
5805    0x0000000000000000, // Bc
5806    0x0000000000000000, // Bfc
5807    0x0000000000000000, // Bfi
5808    0x0000000000000000, // Bfm
5809    0x0000000000000000, // Bfxil
5810    0x0000000000000000, // Bic
5811    0x0000000000000000, // Bics
5812    0x0000000000000000, // Bl
5813    0x0000000000000000, // Blr
5814    0x0000000000000000, // Br
5815    0x0000000000000000, // Brk
5816    0x0000000000000008, // Bti
5817    0x0000000000100000, // Cas
5818    0x0000000000100000, // Casa
5819    0x0000000000100000, // Casab
5820    0x0000000000100000, // Casah
5821    0x0000000000100000, // Casal
5822    0x0000000000100000, // Casalb
5823    0x0000000000100000, // Casalh
5824    0x0000000000100000, // Casb
5825    0x0000000000100000, // Cash
5826    0x0000000000100000, // Casl
5827    0x0000000000100000, // Caslb
5828    0x0000000000100000, // Caslh
5829    0x0000000000100000, // Casp
5830    0x0000000000100000, // Caspa
5831    0x0000000000100000, // Caspal
5832    0x0000000000100000, // Caspl
5833    0x0000000000000000, // Cbnz
5834    0x0000000000000000, // Cbz
5835    0x0000000000000000, // Ccmn
5836    0x0000000000000000, // Ccmp
5837    0x0000000000001000, // Cfinv
5838    0x0000000000000010, // Chkfeat
5839    0x0000000000000000, // Cinc
5840    0x0000000000000000, // Cinv
5841    0x0000000000000020, // Clrbhb
5842    0x0000000000000000, // Clrex
5843    0x0000000000000000, // Cls
5844    0x0000000000000000, // Clz
5845    0x0000000000000000, // Cmn
5846    0x0000000000000000, // Cmp
5847    0x0000000000200000, // Cmpp
5848    0x0000000000000000, // Cneg
5849    0x0000000000000080, // Cnt
5850    0x0000000000000040, // Crc32b
5851    0x0000000000000040, // Crc32cb
5852    0x0000000000000040, // Crc32ch
5853    0x0000000000000040, // Crc32cw
5854    0x0000000000000040, // Crc32cx
5855    0x0000000000000040, // Crc32h
5856    0x0000000000000040, // Crc32w
5857    0x0000000000000040, // Crc32x
5858    0x0000000000000000, // Csdb
5859    0x0000000000000000, // Csel
5860    0x0000000000000000, // Cset
5861    0x0000000000000000, // Csetm
5862    0x0000000000000000, // Csinc
5863    0x0000000000000000, // Csinv
5864    0x0000000000000000, // Csneg
5865    0x0000000000000080, // Ctz
5866    0x0000000000000000, // Dc
5867    0x0000000000000000, // Dcps1
5868    0x0000000000000000, // Dcps2
5869    0x0000000000000000, // Dcps3
5870    0x0000000000000100, // Dgh
5871    0x0000000000000000, // Dmb
5872    0x0000000000000000, // Drps
5873    0x0000000000000000, // Dsb
5874    0x0000000000000000, // Eon
5875    0x0000000000000000, // Eor
5876    0x0000000001000000, // Esb
5877    0x0000000000000000, // Extr
5878    0x0000000000000000, // Eret
5879    0x0000000000200000, // Gmi
5880    0x0000000000000000, // Hint
5881    0x0000000000000000, // Hlt
5882    0x0000000000000000, // Hvc
5883    0x0000000000000000, // Ic
5884    0x0000000000000000, // Isb
5885    0x0000000000100000, // Ldadd
5886    0x0000000000100000, // Ldadda
5887    0x0000000000100000, // Ldaddab
5888    0x0000000000100000, // Ldaddah
5889    0x0000000000100000, // Ldaddal
5890    0x0000000000100000, // Ldaddalb
5891    0x0000000000100000, // Ldaddalh
5892    0x0000000000100000, // Ldaddb
5893    0x0000000000100000, // Ldaddh
5894    0x0000000000100000, // Ldaddl
5895    0x0000000000100000, // Ldaddlb
5896    0x0000000000100000, // Ldaddlh
5897    0x0000000000000000, // Ldar
5898    0x0000000000000000, // Ldarb
5899    0x0000000000000000, // Ldarh
5900    0x0000000000000000, // Ldaxp
5901    0x0000000000000000, // Ldaxr
5902    0x0000000000000000, // Ldaxrb
5903    0x0000000000000000, // Ldaxrh
5904    0x0000000000100000, // Ldclr
5905    0x0000000000100000, // Ldclra
5906    0x0000000000100000, // Ldclrab
5907    0x0000000000100000, // Ldclrah
5908    0x0000000000100000, // Ldclral
5909    0x0000000000100000, // Ldclralb
5910    0x0000000000100000, // Ldclralh
5911    0x0000000000100000, // Ldclrb
5912    0x0000000000100000, // Ldclrh
5913    0x0000000000100000, // Ldclrl
5914    0x0000000000100000, // Ldclrlb
5915    0x0000000000100000, // Ldclrlh
5916    0x0000000000100000, // Ldeor
5917    0x0000000000100000, // Ldeora
5918    0x0000000000100000, // Ldeorab
5919    0x0000000000100000, // Ldeorah
5920    0x0000000000100000, // Ldeoral
5921    0x0000000000100000, // Ldeoralb
5922    0x0000000000100000, // Ldeoralh
5923    0x0000000000100000, // Ldeorb
5924    0x0000000000100000, // Ldeorh
5925    0x0000000000100000, // Ldeorl
5926    0x0000000000100000, // Ldeorlb
5927    0x0000000000100000, // Ldeorlh
5928    0x0000000000200000, // Ldg
5929    0x0000000000400000, // Ldgm
5930    0x0000000000080000, // Ldlar
5931    0x0000000000080000, // Ldlarb
5932    0x0000000000080000, // Ldlarh
5933    0x0000000000000000, // Ldnp
5934    0x0000000000000000, // Ldp
5935    0x0000000000000000, // Ldpsw
5936    0x0000000000000000, // Ldr
5937    0x0000000000800000, // Ldraa
5938    0x0000000000800000, // Ldrab
5939    0x0000000000000000, // Ldrb
5940    0x0000000000000000, // Ldrh
5941    0x0000000000000000, // Ldrsb
5942    0x0000000000000000, // Ldrsh
5943    0x0000000000000000, // Ldrsw
5944    0x0000000000100000, // Ldset
5945    0x0000000000100000, // Ldseta
5946    0x0000000000100000, // Ldsetab
5947    0x0000000000100000, // Ldsetah
5948    0x0000000000100000, // Ldsetal
5949    0x0000000000100000, // Ldsetalb
5950    0x0000000000100000, // Ldsetalh
5951    0x0000000000100000, // Ldsetb
5952    0x0000000000100000, // Ldseth
5953    0x0000000000100000, // Ldsetl
5954    0x0000000000100000, // Ldsetlb
5955    0x0000000000100000, // Ldsetlh
5956    0x0000000000100000, // Ldsmax
5957    0x0000000000100000, // Ldsmaxa
5958    0x0000000000100000, // Ldsmaxab
5959    0x0000000000100000, // Ldsmaxah
5960    0x0000000000100000, // Ldsmaxal
5961    0x0000000000100000, // Ldsmaxalb
5962    0x0000000000100000, // Ldsmaxalh
5963    0x0000000000100000, // Ldsmaxb
5964    0x0000000000100000, // Ldsmaxh
5965    0x0000000000100000, // Ldsmaxl
5966    0x0000000000100000, // Ldsmaxlb
5967    0x0000000000100000, // Ldsmaxlh
5968    0x0000000000100000, // Ldsmin
5969    0x0000000000100000, // Ldsmina
5970    0x0000000000100000, // Ldsminab
5971    0x0000000000100000, // Ldsminah
5972    0x0000000000100000, // Ldsminal
5973    0x0000000000100000, // Ldsminalb
5974    0x0000000000100000, // Ldsminalh
5975    0x0000000000100000, // Ldsminb
5976    0x0000000000100000, // Ldsminh
5977    0x0000000000100000, // Ldsminl
5978    0x0000000000100000, // Ldsminlb
5979    0x0000000000100000, // Ldsminlh
5980    0x0000000000000000, // Ldtr
5981    0x0000000000000000, // Ldtrb
5982    0x0000000000000000, // Ldtrh
5983    0x0000000000000000, // Ldtrsb
5984    0x0000000000000000, // Ldtrsh
5985    0x0000000000000000, // Ldtrsw
5986    0x0000000000100000, // Ldumax
5987    0x0000000000100000, // Ldumaxa
5988    0x0000000000100000, // Ldumaxab
5989    0x0000000000100000, // Ldumaxah
5990    0x0000000000100000, // Ldumaxal
5991    0x0000000000100000, // Ldumaxalb
5992    0x0000000000100000, // Ldumaxalh
5993    0x0000000000100000, // Ldumaxb
5994    0x0000000000100000, // Ldumaxh
5995    0x0000000000100000, // Ldumaxl
5996    0x0000000000100000, // Ldumaxlb
5997    0x0000000000100000, // Ldumaxlh
5998    0x0000000000100000, // Ldumin
5999    0x0000000000100000, // Ldumina
6000    0x0000000000100000, // Lduminab
6001    0x0000000000100000, // Lduminah
6002    0x0000000000100000, // Lduminal
6003    0x0000000000100000, // Lduminalb
6004    0x0000000000100000, // Lduminalh
6005    0x0000000000100000, // Lduminb
6006    0x0000000000100000, // Lduminh
6007    0x0000000000100000, // Lduminl
6008    0x0000000000100000, // Lduminlb
6009    0x0000000000100000, // Lduminlh
6010    0x0000000000000000, // Ldur
6011    0x0000000000000000, // Ldurb
6012    0x0000000000000000, // Ldurh
6013    0x0000000000000000, // Ldursb
6014    0x0000000000000000, // Ldursh
6015    0x0000000000000000, // Ldursw
6016    0x0000000000000000, // Ldxp
6017    0x0000000000000000, // Ldxr
6018    0x0000000000000000, // Ldxrb
6019    0x0000000000000000, // Ldxrh
6020    0x0000000000000000, // Lsl
6021    0x0000000000000000, // Lslv
6022    0x0000000000000000, // Lsr
6023    0x0000000000000000, // Lsrv
6024    0x0000000000000000, // Madd
6025    0x0000000000000000, // Mneg
6026    0x0000000000000000, // Mov
6027    0x0000000000000000, // Movk
6028    0x0000000000000000, // Movn
6029    0x0000000000000000, // Movz
6030    0x0000000000000000, // Mrs
6031    0x0000000000000000, // Msr
6032    0x0000000000000000, // Msub
6033    0x0000000000000000, // Mul
6034    0x0000000000000000, // Mvn
6035    0x0000000000000000, // Neg
6036    0x0000000000000000, // Negs
6037    0x0000000000000000, // Ngc
6038    0x0000000000000000, // Ngcs
6039    0x0000000000000000, // Nop
6040    0x0000000000000000, // Orn
6041    0x0000000000000000, // Orr
6042    0x0000000000800000, // Pacda
6043    0x0000000000800000, // Pacdb
6044    0x0000000000800000, // Pacdza
6045    0x0000000000800000, // Pacdzb
6046    0x0000000000800000, // Pacga
6047    0x0000000000000000, // Prfm
6048    0x0000000000000000, // Pssbb
6049    0x0000000000000000, // Rbit
6050    0x0000000000000000, // Ret
6051    0x0000000000000000, // Rev
6052    0x0000000000000000, // Rev16
6053    0x0000000000000000, // Rev32
6054    0x0000000000000000, // Rev64
6055    0x0000000000000000, // Ror
6056    0x0000000000000000, // Rorv
6057    0x0000000000000000, // Sbc
6058    0x0000000000000000, // Sbcs
6059    0x0000000000000000, // Sbfiz
6060    0x0000000000000000, // Sbfm
6061    0x0000000000000000, // Sbfx
6062    0x0000000000000000, // Sdiv
6063    0x0000000000001000, // Setf8
6064    0x0000000000001000, // Setf16
6065    0x0000000000000000, // Sev
6066    0x0000000000000000, // Sevl
6067    0x0000000000000000, // Smaddl
6068    0x0000000000000080, // Smax
6069    0x0000000000000000, // Smc
6070    0x0000000000000080, // Smin
6071    0x0000000000000000, // Smnegl
6072    0x0000000000000000, // Smsubl
6073    0x0000000000000000, // Smulh
6074    0x0000000000000000, // Smull
6075    0x0000000000000000, // Ssbb
6076    0x0000000000200000, // St2g
6077    0x0000000000100000, // Stadd
6078    0x0000000000100000, // Staddl
6079    0x0000000000100000, // Staddb
6080    0x0000000000100000, // Staddlb
6081    0x0000000000100000, // Staddh
6082    0x0000000000100000, // Staddlh
6083    0x0000000000100000, // Stclr
6084    0x0000000000100000, // Stclrl
6085    0x0000000000100000, // Stclrb
6086    0x0000000000100000, // Stclrlb
6087    0x0000000000100000, // Stclrh
6088    0x0000000000100000, // Stclrlh
6089    0x0000000000100000, // Steor
6090    0x0000000000100000, // Steorl
6091    0x0000000000100000, // Steorb
6092    0x0000000000100000, // Steorlb
6093    0x0000000000100000, // Steorh
6094    0x0000000000100000, // Steorlh
6095    0x0000000000200000, // Stg
6096    0x0000000000400000, // Stgm
6097    0x0000000000200000, // Stgp
6098    0x0000000000080000, // Stllr
6099    0x0000000000080000, // Stllrb
6100    0x0000000000080000, // Stllrh
6101    0x0000000000000000, // Stlr
6102    0x0000000000000000, // Stlrb
6103    0x0000000000000000, // Stlrh
6104    0x0000000000000000, // Stlxp
6105    0x0000000000000000, // Stlxr
6106    0x0000000000000000, // Stlxrb
6107    0x0000000000000000, // Stlxrh
6108    0x0000000000000000, // Stnp
6109    0x0000000000000000, // Stp
6110    0x0000000000000000, // Str
6111    0x0000000000000000, // Strb
6112    0x0000000000000000, // Strh
6113    0x0000000000100000, // Stset
6114    0x0000000000100000, // Stsetl
6115    0x0000000000100000, // Stsetb
6116    0x0000000000100000, // Stsetlb
6117    0x0000000000100000, // Stseth
6118    0x0000000000100000, // Stsetlh
6119    0x0000000000100000, // Stsmax
6120    0x0000000000100000, // Stsmaxl
6121    0x0000000000100000, // Stsmaxb
6122    0x0000000000100000, // Stsmaxlb
6123    0x0000000000100000, // Stsmaxh
6124    0x0000000000100000, // Stsmaxlh
6125    0x0000000000100000, // Stsmin
6126    0x0000000000100000, // Stsminl
6127    0x0000000000100000, // Stsminb
6128    0x0000000000100000, // Stsminlb
6129    0x0000000000100000, // Stsminh
6130    0x0000000000100000, // Stsminlh
6131    0x0000000000000000, // Sttr
6132    0x0000000000000000, // Sttrb
6133    0x0000000000000000, // Sttrh
6134    0x0000000000100000, // Stumax
6135    0x0000000000100000, // Stumaxl
6136    0x0000000000100000, // Stumaxb
6137    0x0000000000100000, // Stumaxlb
6138    0x0000000000100000, // Stumaxh
6139    0x0000000000100000, // Stumaxlh
6140    0x0000000000100000, // Stumin
6141    0x0000000000100000, // Stuminl
6142    0x0000000000100000, // Stuminb
6143    0x0000000000100000, // Stuminlb
6144    0x0000000000100000, // Stuminh
6145    0x0000000000100000, // Stuminlh
6146    0x0000000000000000, // Stur
6147    0x0000000000000000, // Sturb
6148    0x0000000000000000, // Sturh
6149    0x0000000000000000, // Stxp
6150    0x0000000000000000, // Stxr
6151    0x0000000000000000, // Stxrb
6152    0x0000000000000000, // Stxrh
6153    0x0000000000200000, // Stz2g
6154    0x0000000000200000, // Stzg
6155    0x0000000000400000, // Stzgm
6156    0x0000000000000000, // Sub
6157    0x0000000000200000, // Subg
6158    0x0000000000200000, // Subp
6159    0x0000000000200000, // Subps
6160    0x0000000000000000, // Subs
6161    0x0000000000000000, // Svc
6162    0x0000000000100000, // Swp
6163    0x0000000000100000, // Swpa
6164    0x0000000000100000, // Swpab
6165    0x0000000000100000, // Swpah
6166    0x0000000000100000, // Swpal
6167    0x0000000000100000, // Swpalb
6168    0x0000000000100000, // Swpalh
6169    0x0000000000100000, // Swpb
6170    0x0000000000100000, // Swph
6171    0x0000000000100000, // Swpl
6172    0x0000000000100000, // Swplb
6173    0x0000000000100000, // Swplh
6174    0x0000000000000000, // Sxtb
6175    0x0000000000000000, // Sxth
6176    0x0000000000000000, // Sxtw
6177    0x0000000000000000, // Sys
6178    0x0000000000000000, // Tlbi
6179    0x0000000000000000, // Tst
6180    0x0000000000000000, // Tbnz
6181    0x0000000000000000, // Tbz
6182    0x0000000000000000, // Ubfiz
6183    0x0000000000000000, // Ubfm
6184    0x0000000000000000, // Ubfx
6185    0x0000000000000000, // Udf
6186    0x0000000000000000, // Udiv
6187    0x0000000000000000, // Umaddl
6188    0x0000000000000080, // Umax
6189    0x0000000000000080, // Umin
6190    0x0000000000000000, // Umnegl
6191    0x0000000000000000, // Umull
6192    0x0000000000000000, // Umulh
6193    0x0000000000000000, // Umsubl
6194    0x0000000000000000, // Uxtb
6195    0x0000000000000000, // Uxth
6196    0x0000000000000000, // Wfe
6197    0x0000000000000000, // Wfi
6198    0x0000000000002000, // Xaflag
6199    0x0000000000800000, // Xpacd
6200    0x0000000000800000, // Xpaci
6201    0x0000000000800000, // Xpaclri
6202    0x0000000000000000, // Yield
6203    0x0000000000000002, // Abs_v
6204    0x0000000000000002, // Add_v
6205    0x0000000000000002, // Addhn_v
6206    0x0000000000000002, // Addhn2_v
6207    0x0000000000000002, // Addp_v
6208    0x0000000000000002, // Addv_v
6209    0x0000000000000003, // Aesd_v
6210    0x0000000000000003, // Aese_v
6211    0x0000000000000003, // Aesimc_v
6212    0x0000000000000003, // Aesmc_v
6213    0x0000000000000002, // And_v
6214    0x0000000010000002, // Bcax_v
6215    0x0000000000000006, // Bfcvt_v
6216    0x0000000000000006, // Bfcvtn_v
6217    0x0000000000000006, // Bfcvtn2_v
6218    0x0000000000000006, // Bfdot_v
6219    0x0000000000000006, // Bfmlalb_v
6220    0x0000000000000006, // Bfmlalt_v
6221    0x0000000000000006, // Bfmmla_v
6222    0x0000000000000002, // Bic_v
6223    0x0000000000000002, // Bif_v
6224    0x0000000000000002, // Bit_v
6225    0x0000000000000002, // Bsl_v
6226    0x0000000000000002, // Cls_v
6227    0x0000000000000002, // Clz_v
6228    0x0000000000000002, // Cmeq_v
6229    0x0000000000000002, // Cmge_v
6230    0x0000000000000002, // Cmgt_v
6231    0x0000000000000002, // Cmhi_v
6232    0x0000000000000002, // Cmhs_v
6233    0x0000000000000002, // Cmle_v
6234    0x0000000000000002, // Cmlt_v
6235    0x0000000000000002, // Cmtst_v
6236    0x0000000000000002, // Cnt_v
6237    0x0000000000000002, // Dup_v
6238    0x0000000000000002, // Eor_v
6239    0x0000000010000002, // Eor3_v
6240    0x0000000000000002, // Ext_v
6241    0x0000000000000002, // Fabd_v
6242    0x0000000000000002, // Fabs_v
6243    0x0000000000000002, // Facge_v
6244    0x0000000000000002, // Facgt_v
6245    0x0000000000000002, // Fadd_v
6246    0x0000000000000002, // Faddp_v
6247    0x0000000000000402, // Fcadd_v
6248    0x0000000000000002, // Fccmp_v
6249    0x0000000000000002, // Fccmpe_v
6250    0x0000000000000002, // Fcmeq_v
6251    0x0000000000000002, // Fcmge_v
6252    0x0000000000000002, // Fcmgt_v
6253    0x0000000000000402, // Fcmla_v
6254    0x0000000000000002, // Fcmle_v
6255    0x0000000000000002, // Fcmlt_v
6256    0x0000000000000002, // Fcmp_v
6257    0x0000000000000002, // Fcmpe_v
6258    0x0000000000000002, // Fcsel_v
6259    0x0000000000000002, // Fcvt_v
6260    0x0000000000000002, // Fcvtas_v
6261    0x0000000000000002, // Fcvtau_v
6262    0x0000000000000002, // Fcvtl_v
6263    0x0000000000000002, // Fcvtl2_v
6264    0x0000000000000002, // Fcvtms_v
6265    0x0000000000000002, // Fcvtmu_v
6266    0x0000000000000002, // Fcvtn_v
6267    0x0000000000000002, // Fcvtn2_v
6268    0x0000000000000002, // Fcvtns_v
6269    0x0000000000000002, // Fcvtnu_v
6270    0x0000000000000002, // Fcvtps_v
6271    0x0000000000000002, // Fcvtpu_v
6272    0x0000000000000000, // Fcvtxn_v
6273    0x0000000000000000, // Fcvtxn2_v
6274    0x0000000000000002, // Fcvtzs_v
6275    0x0000000000000002, // Fcvtzu_v
6276    0x0000000000000002, // Fdiv_v
6277    0x0000000000040002, // Fjcvtzs_v
6278    0x0000000000000002, // Fmadd_v
6279    0x0000000000000002, // Fmax_v
6280    0x0000000000000002, // Fmaxnm_v
6281    0x0000000000000002, // Fmaxnmp_v
6282    0x0000000000000002, // Fmaxnmv_v
6283    0x0000000000000002, // Fmaxp_v
6284    0x0000000000000002, // Fmaxv_v
6285    0x0000000000000002, // Fmin_v
6286    0x0000000000000002, // Fminnm_v
6287    0x0000000000000002, // Fminnmp_v
6288    0x0000000000000002, // Fminnmv_v
6289    0x0000000000000002, // Fminp_v
6290    0x0000000000000002, // Fminv_v
6291    0x0000000000000002, // Fmla_v
6292    0x0000000000000802, // Fmlal_v
6293    0x0000000000000802, // Fmlal2_v
6294    0x0000000000000002, // Fmls_v
6295    0x0000000000000802, // Fmlsl_v
6296    0x0000000000000802, // Fmlsl2_v
6297    0x0000000000000002, // Fmov_v
6298    0x0000000000000002, // Fmsub_v
6299    0x0000000000000002, // Fmul_v
6300    0x0000000000000002, // Fmulx_v
6301    0x0000000000000002, // Fneg_v
6302    0x0000000000000002, // Fnmadd_v
6303    0x0000000000000002, // Fnmsub_v
6304    0x0000000000000002, // Fnmul_v
6305    0x0000000000000002, // Frecpe_v
6306    0x0000000000000002, // Frecps_v
6307    0x0000000000000002, // Frecpx_v
6308    0x0000000000010002, // Frint32x_v
6309    0x0000000000010002, // Frint32z_v
6310    0x0000000000010002, // Frint64x_v
6311    0x0000000000010002, // Frint64z_v
6312    0x0000000000000002, // Frinta_v
6313    0x0000000000000002, // Frinti_v
6314    0x0000000000000002, // Frintm_v
6315    0x0000000000000002, // Frintn_v
6316    0x0000000000000002, // Frintp_v
6317    0x0000000000000002, // Frintx_v
6318    0x0000000000000002, // Frintz_v
6319    0x0000000000000002, // Frsqrte_v
6320    0x0000000000000002, // Frsqrts_v
6321    0x0000000000000002, // Fsqrt_v
6322    0x0000000000000002, // Fsub_v
6323    0x0000000000000002, // Ins_v
6324    0x0000000000000002, // Ld1_v
6325    0x0000000000000002, // Ld1r_v
6326    0x0000000000000002, // Ld2_v
6327    0x0000000000000002, // Ld2r_v
6328    0x0000000000000002, // Ld3_v
6329    0x0000000000000002, // Ld3r_v
6330    0x0000000000000002, // Ld4_v
6331    0x0000000000000002, // Ld4r_v
6332    0x0000000000000002, // Ldnp_v
6333    0x0000000000000002, // Ldp_v
6334    0x0000000000000002, // Ldr_v
6335    0x0000000000000002, // Ldur_v
6336    0x0000000000000002, // Mla_v
6337    0x0000000000000002, // Mls_v
6338    0x0000000000000002, // Mov_v
6339    0x0000000000000002, // Movi_v
6340    0x0000000000000002, // Mul_v
6341    0x0000000000000002, // Mvn_v
6342    0x0000000000000002, // Mvni_v
6343    0x0000000000000002, // Neg_v
6344    0x0000000000000002, // Not_v
6345    0x0000000000000002, // Orn_v
6346    0x0000000000000002, // Orr_v
6347    0x0000000000000002, // Pmul_v
6348    0x0000000000000002, // Pmull_v
6349    0x0000000000000002, // Pmull2_v
6350    0x0000000000000002, // Raddhn_v
6351    0x0000000000000002, // Raddhn2_v
6352    0x0000000010000002, // Rax1_v
6353    0x0000000000000002, // Rbit_v
6354    0x0000000000000002, // Rev16_v
6355    0x0000000000000002, // Rev32_v
6356    0x0000000000000002, // Rev64_v
6357    0x0000000000000002, // Rshrn_v
6358    0x0000000000000002, // Rshrn2_v
6359    0x0000000000000002, // Rsubhn_v
6360    0x0000000000000002, // Rsubhn2_v
6361    0x0000000000000002, // Saba_v
6362    0x0000000000000002, // Sabal_v
6363    0x0000000000000002, // Sabal2_v
6364    0x0000000000000002, // Sabd_v
6365    0x0000000000000002, // Sabdl_v
6366    0x0000000000000002, // Sabdl2_v
6367    0x0000000000000002, // Sadalp_v
6368    0x0000000000000002, // Saddl_v
6369    0x0000000000000002, // Saddl2_v
6370    0x0000000000000002, // Saddlp_v
6371    0x0000000000000002, // Saddlv_v
6372    0x0000000000000002, // Saddw_v
6373    0x0000000000000002, // Saddw2_v
6374    0x0000000000000002, // Scvtf_v
6375    0x0000000000000202, // Sdot_v
6376    0x0000000004000002, // Sha1c_v
6377    0x0000000004000002, // Sha1h_v
6378    0x0000000004000002, // Sha1m_v
6379    0x0000000004000002, // Sha1p_v
6380    0x0000000004000002, // Sha1su0_v
6381    0x0000000004000002, // Sha1su1_v
6382    0x0000000008000002, // Sha256h_v
6383    0x0000000008000002, // Sha256h2_v
6384    0x0000000008000002, // Sha256su0_v
6385    0x0000000008000002, // Sha256su1_v
6386    0x0000000020000002, // Sha512h_v
6387    0x0000000020000002, // Sha512h2_v
6388    0x0000000020000002, // Sha512su0_v
6389    0x0000000020000002, // Sha512su1_v
6390    0x0000000000000002, // Shadd_v
6391    0x0000000000000002, // Shl_v
6392    0x0000000000000002, // Shll_v
6393    0x0000000000000002, // Shll2_v
6394    0x0000000000000002, // Shrn_v
6395    0x0000000000000002, // Shrn2_v
6396    0x0000000000000002, // Shsub_v
6397    0x0000000000000002, // Sli_v
6398    0x0000000040000002, // Sm3partw1_v
6399    0x0000000040000002, // Sm3partw2_v
6400    0x0000000040000002, // Sm3ss1_v
6401    0x0000000040000002, // Sm3tt1a_v
6402    0x0000000040000002, // Sm3tt1b_v
6403    0x0000000040000002, // Sm3tt2a_v
6404    0x0000000040000002, // Sm3tt2b_v
6405    0x0000000080000002, // Sm4e_v
6406    0x0000000080000002, // Sm4ekey_v
6407    0x0000000000000002, // Smax_v
6408    0x0000000000000002, // Smaxp_v
6409    0x0000000000000002, // Smaxv_v
6410    0x0000000000000002, // Smin_v
6411    0x0000000000000002, // Sminp_v
6412    0x0000000000000002, // Sminv_v
6413    0x0000000000000002, // Smlal_v
6414    0x0000000000000002, // Smlal2_v
6415    0x0000000000000002, // Smlsl_v
6416    0x0000000000000002, // Smlsl2_v
6417    0x0000000000020002, // Smmla_v
6418    0x0000000000000002, // Smov_v
6419    0x0000000000000002, // Smull_v
6420    0x0000000000000002, // Smull2_v
6421    0x0000000000000002, // Sqabs_v
6422    0x0000000000000002, // Sqadd_v
6423    0x0000000000000002, // Sqdmlal_v
6424    0x0000000000000002, // Sqdmlal2_v
6425    0x0000000000000002, // Sqdmlsl_v
6426    0x0000000000000002, // Sqdmlsl2_v
6427    0x0000000000000002, // Sqdmulh_v
6428    0x0000000000000002, // Sqdmull_v
6429    0x0000000000000002, // Sqdmull2_v
6430    0x0000000000000002, // Sqneg_v
6431    0x0000000002000002, // Sqrdmlah_v
6432    0x0000000002000002, // Sqrdmlsh_v
6433    0x0000000000000002, // Sqrdmulh_v
6434    0x0000000000000002, // Sqrshl_v
6435    0x0000000000000002, // Sqrshrn_v
6436    0x0000000000000002, // Sqrshrn2_v
6437    0x0000000000000002, // Sqrshrun_v
6438    0x0000000000000002, // Sqrshrun2_v
6439    0x0000000000000002, // Sqshl_v
6440    0x0000000000000002, // Sqshlu_v
6441    0x0000000000000002, // Sqshrn_v
6442    0x0000000000000002, // Sqshrn2_v
6443    0x0000000000000002, // Sqshrun_v
6444    0x0000000000000002, // Sqshrun2_v
6445    0x0000000000000002, // Sqsub_v
6446    0x0000000000000002, // Sqxtn_v
6447    0x0000000000000002, // Sqxtn2_v
6448    0x0000000000000002, // Sqxtun_v
6449    0x0000000000000002, // Sqxtun2_v
6450    0x0000000000000002, // Srhadd_v
6451    0x0000000000000002, // Sri_v
6452    0x0000000000000002, // Srshl_v
6453    0x0000000000000002, // Srshr_v
6454    0x0000000000000002, // Srsra_v
6455    0x0000000000000002, // Sshl_v
6456    0x0000000000000002, // Sshll_v
6457    0x0000000000000002, // Sshll2_v
6458    0x0000000000000002, // Sshr_v
6459    0x0000000000000002, // Ssra_v
6460    0x0000000000000002, // Ssubl_v
6461    0x0000000000000002, // Ssubl2_v
6462    0x0000000000000002, // Ssubw_v
6463    0x0000000000000002, // Ssubw2_v
6464    0x0000000000000002, // St1_v
6465    0x0000000000000002, // St2_v
6466    0x0000000000000002, // St3_v
6467    0x0000000000000002, // St4_v
6468    0x0000000000000002, // Stnp_v
6469    0x0000000000000002, // Stp_v
6470    0x0000000000000002, // Str_v
6471    0x0000000000000002, // Stur_v
6472    0x0000000000000002, // Sub_v
6473    0x0000000000000002, // Subhn_v
6474    0x0000000000000002, // Subhn2_v
6475    0x0000000000020002, // Sudot_v
6476    0x0000000000000002, // Suqadd_v
6477    0x0000000000000002, // Sxtl_v
6478    0x0000000000000002, // Sxtl2_v
6479    0x0000000000000002, // Tbl_v
6480    0x0000000000000002, // Tbx_v
6481    0x0000000000000002, // Trn1_v
6482    0x0000000000000002, // Trn2_v
6483    0x0000000000000002, // Uaba_v
6484    0x0000000000000002, // Uabal_v
6485    0x0000000000000002, // Uabal2_v
6486    0x0000000000000002, // Uabd_v
6487    0x0000000000000002, // Uabdl_v
6488    0x0000000000000002, // Uabdl2_v
6489    0x0000000000000002, // Uadalp_v
6490    0x0000000000000002, // Uaddl_v
6491    0x0000000000000002, // Uaddl2_v
6492    0x0000000000000002, // Uaddlp_v
6493    0x0000000000000002, // Uaddlv_v
6494    0x0000000000000002, // Uaddw_v
6495    0x0000000000000002, // Uaddw2_v
6496    0x0000000000000002, // Ucvtf_v
6497    0x0000000000000202, // Udot_v
6498    0x0000000000000002, // Uhadd_v
6499    0x0000000000000002, // Uhsub_v
6500    0x0000000000000002, // Umax_v
6501    0x0000000000000002, // Umaxp_v
6502    0x0000000000000002, // Umaxv_v
6503    0x0000000000000002, // Umin_v
6504    0x0000000000000002, // Uminp_v
6505    0x0000000000000002, // Uminv_v
6506    0x0000000000000002, // Umlal_v
6507    0x0000000000000002, // Umlal2_v
6508    0x0000000000000002, // Umlsl_v
6509    0x0000000000000002, // Umlsl2_v
6510    0x0000000000020002, // Ummla_v
6511    0x0000000000000002, // Umov_v
6512    0x0000000000000002, // Umull_v
6513    0x0000000000000002, // Umull2_v
6514    0x0000000000000002, // Uqadd_v
6515    0x0000000000000002, // Uqrshl_v
6516    0x0000000000000002, // Uqrshrn_v
6517    0x0000000000000002, // Uqrshrn2_v
6518    0x0000000000000002, // Uqshl_v
6519    0x0000000000000002, // Uqshrn_v
6520    0x0000000000000002, // Uqshrn2_v
6521    0x0000000000000002, // Uqsub_v
6522    0x0000000000000002, // Uqxtn_v
6523    0x0000000000000002, // Uqxtn2_v
6524    0x0000000000000002, // Urecpe_v
6525    0x0000000000000002, // Urhadd_v
6526    0x0000000000000002, // Urshl_v
6527    0x0000000000000002, // Urshr_v
6528    0x0000000000000002, // Ursqrte_v
6529    0x0000000000000002, // Ursra_v
6530    0x0000000000020002, // Usdot_v
6531    0x0000000000000002, // Ushl_v
6532    0x0000000000000002, // Ushll_v
6533    0x0000000000000002, // Ushll2_v
6534    0x0000000000000002, // Ushr_v
6535    0x0000000000020002, // Usmmla_v
6536    0x0000000000000002, // Usqadd_v
6537    0x0000000000000002, // Usra_v
6538    0x0000000000000002, // Usubl_v
6539    0x0000000000000002, // Usubl2_v
6540    0x0000000000000002, // Usubw_v
6541    0x0000000000000002, // Usubw2_v
6542    0x0000000000000002, // Uxtl_v
6543    0x0000000000000002, // Uxtl2_v
6544    0x0000000000000002, // Uzp1_v
6545    0x0000000000000002, // Uzp2_v
6546    0x0000000010000002, // Xar_v
6547    0x0000000000000002, // Xtn_v
6548    0x0000000000000002, // Xtn2_v
6549    0x0000000000000002, // Zip1_v
6550    0x0000000000000002, // Zip2_v
6551];
6552
6553static INST_BASE_FEATURE_CONTEXT: [&str; InstId::_Count as usize] = [
6554    "",
6555    "abs requires: CSSC",
6556    "",
6557    "",
6558    "",
6559    "addg requires: MTE",
6560    "",
6561    "",
6562    "",
6563    "",
6564    "",
6565    "",
6566    "",
6567    "",
6568    "autda requires: PAUTH",
6569    "autdza requires: PAUTH",
6570    "autdb requires: PAUTH",
6571    "autdzb requires: PAUTH",
6572    "autia requires: PAUTH",
6573    "autia1716 requires: PAUTH",
6574    "autiasp requires: PAUTH",
6575    "autiaz requires: PAUTH",
6576    "autib requires: PAUTH",
6577    "autib1716 requires: PAUTH",
6578    "autibsp requires: PAUTH",
6579    "autibz requires: PAUTH",
6580    "autiza requires: PAUTH",
6581    "autizb requires: PAUTH",
6582    "axflag requires: FLAGM2",
6583    "",
6584    "",
6585    "",
6586    "",
6587    "",
6588    "",
6589    "",
6590    "",
6591    "",
6592    "",
6593    "",
6594    "",
6595    "bti requires: BTI",
6596    "cas requires: LSE",
6597    "casa requires: LSE",
6598    "casab requires: LSE",
6599    "casah requires: LSE",
6600    "casal requires: LSE",
6601    "casalb requires: LSE",
6602    "casalh requires: LSE",
6603    "casb requires: LSE",
6604    "cash requires: LSE",
6605    "casl requires: LSE",
6606    "caslb requires: LSE",
6607    "caslh requires: LSE",
6608    "casp requires: LSE",
6609    "caspa requires: LSE",
6610    "caspal requires: LSE",
6611    "caspl requires: LSE",
6612    "",
6613    "",
6614    "",
6615    "",
6616    "cfinv requires: FLAGM",
6617    "chkfeat requires: CHK",
6618    "",
6619    "",
6620    "clrbhb requires: CLRBHB",
6621    "",
6622    "",
6623    "",
6624    "",
6625    "",
6626    "cmpp requires: MTE",
6627    "",
6628    "cnt requires: CSSC",
6629    "crc32b requires: CRC32",
6630    "crc32cb requires: CRC32",
6631    "crc32ch requires: CRC32",
6632    "crc32cw requires: CRC32",
6633    "crc32cx requires: CRC32",
6634    "crc32h requires: CRC32",
6635    "crc32w requires: CRC32",
6636    "crc32x requires: CRC32",
6637    "",
6638    "",
6639    "",
6640    "",
6641    "",
6642    "",
6643    "",
6644    "ctz requires: CSSC",
6645    "",
6646    "",
6647    "",
6648    "",
6649    "dgh requires: DGH",
6650    "",
6651    "",
6652    "",
6653    "",
6654    "",
6655    "esb requires: RAS",
6656    "",
6657    "",
6658    "gmi requires: MTE",
6659    "",
6660    "",
6661    "",
6662    "",
6663    "",
6664    "ldadd requires: LSE",
6665    "ldadda requires: LSE",
6666    "ldaddab requires: LSE",
6667    "ldaddah requires: LSE",
6668    "ldaddal requires: LSE",
6669    "ldaddalb requires: LSE",
6670    "ldaddalh requires: LSE",
6671    "ldaddb requires: LSE",
6672    "ldaddh requires: LSE",
6673    "ldaddl requires: LSE",
6674    "ldaddlb requires: LSE",
6675    "ldaddlh requires: LSE",
6676    "",
6677    "",
6678    "",
6679    "",
6680    "",
6681    "",
6682    "",
6683    "ldclr requires: LSE",
6684    "ldclra requires: LSE",
6685    "ldclrab requires: LSE",
6686    "ldclrah requires: LSE",
6687    "ldclral requires: LSE",
6688    "ldclralb requires: LSE",
6689    "ldclralh requires: LSE",
6690    "ldclrb requires: LSE",
6691    "ldclrh requires: LSE",
6692    "ldclrl requires: LSE",
6693    "ldclrlb requires: LSE",
6694    "ldclrlh requires: LSE",
6695    "ldeor requires: LSE",
6696    "ldeora requires: LSE",
6697    "ldeorab requires: LSE",
6698    "ldeorah requires: LSE",
6699    "ldeoral requires: LSE",
6700    "ldeoralb requires: LSE",
6701    "ldeoralh requires: LSE",
6702    "ldeorb requires: LSE",
6703    "ldeorh requires: LSE",
6704    "ldeorl requires: LSE",
6705    "ldeorlb requires: LSE",
6706    "ldeorlh requires: LSE",
6707    "ldg requires: MTE",
6708    "ldgm requires: MTE2",
6709    "ldlar requires: LOR",
6710    "ldlarb requires: LOR",
6711    "ldlarh requires: LOR",
6712    "",
6713    "",
6714    "",
6715    "",
6716    "ldraa requires: PAUTH",
6717    "ldrab requires: PAUTH",
6718    "",
6719    "",
6720    "",
6721    "",
6722    "",
6723    "ldset requires: LSE",
6724    "ldseta requires: LSE",
6725    "ldsetab requires: LSE",
6726    "ldsetah requires: LSE",
6727    "ldsetal requires: LSE",
6728    "ldsetalb requires: LSE",
6729    "ldsetalh requires: LSE",
6730    "ldsetb requires: LSE",
6731    "ldseth requires: LSE",
6732    "ldsetl requires: LSE",
6733    "ldsetlb requires: LSE",
6734    "ldsetlh requires: LSE",
6735    "ldsmax requires: LSE",
6736    "ldsmaxa requires: LSE",
6737    "ldsmaxab requires: LSE",
6738    "ldsmaxah requires: LSE",
6739    "ldsmaxal requires: LSE",
6740    "ldsmaxalb requires: LSE",
6741    "ldsmaxalh requires: LSE",
6742    "ldsmaxb requires: LSE",
6743    "ldsmaxh requires: LSE",
6744    "ldsmaxl requires: LSE",
6745    "ldsmaxlb requires: LSE",
6746    "ldsmaxlh requires: LSE",
6747    "ldsmin requires: LSE",
6748    "ldsmina requires: LSE",
6749    "ldsminab requires: LSE",
6750    "ldsminah requires: LSE",
6751    "ldsminal requires: LSE",
6752    "ldsminalb requires: LSE",
6753    "ldsminalh requires: LSE",
6754    "ldsminb requires: LSE",
6755    "ldsminh requires: LSE",
6756    "ldsminl requires: LSE",
6757    "ldsminlb requires: LSE",
6758    "ldsminlh requires: LSE",
6759    "",
6760    "",
6761    "",
6762    "",
6763    "",
6764    "",
6765    "ldumax requires: LSE",
6766    "ldumaxa requires: LSE",
6767    "ldumaxab requires: LSE",
6768    "ldumaxah requires: LSE",
6769    "ldumaxal requires: LSE",
6770    "ldumaxalb requires: LSE",
6771    "ldumaxalh requires: LSE",
6772    "ldumaxb requires: LSE",
6773    "ldumaxh requires: LSE",
6774    "ldumaxl requires: LSE",
6775    "ldumaxlb requires: LSE",
6776    "ldumaxlh requires: LSE",
6777    "ldumin requires: LSE",
6778    "ldumina requires: LSE",
6779    "lduminab requires: LSE",
6780    "lduminah requires: LSE",
6781    "lduminal requires: LSE",
6782    "lduminalb requires: LSE",
6783    "lduminalh requires: LSE",
6784    "lduminb requires: LSE",
6785    "lduminh requires: LSE",
6786    "lduminl requires: LSE",
6787    "lduminlb requires: LSE",
6788    "lduminlh requires: LSE",
6789    "",
6790    "",
6791    "",
6792    "",
6793    "",
6794    "",
6795    "",
6796    "",
6797    "",
6798    "",
6799    "",
6800    "",
6801    "",
6802    "",
6803    "",
6804    "",
6805    "",
6806    "",
6807    "",
6808    "",
6809    "",
6810    "",
6811    "",
6812    "",
6813    "",
6814    "",
6815    "",
6816    "",
6817    "",
6818    "",
6819    "",
6820    "",
6821    "pacda requires: PAUTH",
6822    "pacdb requires: PAUTH",
6823    "pacdza requires: PAUTH",
6824    "pacdzb requires: PAUTH",
6825    "pacga requires: PAUTH",
6826    "",
6827    "",
6828    "",
6829    "",
6830    "",
6831    "",
6832    "",
6833    "",
6834    "",
6835    "",
6836    "",
6837    "",
6838    "",
6839    "",
6840    "",
6841    "",
6842    "setf8 requires: FLAGM",
6843    "setf16 requires: FLAGM",
6844    "",
6845    "",
6846    "",
6847    "smax requires: CSSC",
6848    "",
6849    "smin requires: CSSC",
6850    "",
6851    "",
6852    "",
6853    "",
6854    "",
6855    "st2g requires: MTE",
6856    "stadd requires: LSE",
6857    "staddl requires: LSE",
6858    "staddb requires: LSE",
6859    "staddlb requires: LSE",
6860    "staddh requires: LSE",
6861    "staddlh requires: LSE",
6862    "stclr requires: LSE",
6863    "stclrl requires: LSE",
6864    "stclrb requires: LSE",
6865    "stclrlb requires: LSE",
6866    "stclrh requires: LSE",
6867    "stclrlh requires: LSE",
6868    "steor requires: LSE",
6869    "steorl requires: LSE",
6870    "steorb requires: LSE",
6871    "steorlb requires: LSE",
6872    "steorh requires: LSE",
6873    "steorlh requires: LSE",
6874    "stg requires: MTE",
6875    "stgm requires: MTE2",
6876    "stgp requires: MTE",
6877    "stllr requires: LOR",
6878    "stllrb requires: LOR",
6879    "stllrh requires: LOR",
6880    "",
6881    "",
6882    "",
6883    "",
6884    "",
6885    "",
6886    "",
6887    "",
6888    "",
6889    "",
6890    "",
6891    "",
6892    "stset requires: LSE",
6893    "stsetl requires: LSE",
6894    "stsetb requires: LSE",
6895    "stsetlb requires: LSE",
6896    "stseth requires: LSE",
6897    "stsetlh requires: LSE",
6898    "stsmax requires: LSE",
6899    "stsmaxl requires: LSE",
6900    "stsmaxb requires: LSE",
6901    "stsmaxlb requires: LSE",
6902    "stsmaxh requires: LSE",
6903    "stsmaxlh requires: LSE",
6904    "stsmin requires: LSE",
6905    "stsminl requires: LSE",
6906    "stsminb requires: LSE",
6907    "stsminlb requires: LSE",
6908    "stsminh requires: LSE",
6909    "stsminlh requires: LSE",
6910    "",
6911    "",
6912    "",
6913    "stumax requires: LSE",
6914    "stumaxl requires: LSE",
6915    "stumaxb requires: LSE",
6916    "stumaxlb requires: LSE",
6917    "stumaxh requires: LSE",
6918    "stumaxlh requires: LSE",
6919    "stumin requires: LSE",
6920    "stuminl requires: LSE",
6921    "stuminb requires: LSE",
6922    "stuminlb requires: LSE",
6923    "stuminh requires: LSE",
6924    "stuminlh requires: LSE",
6925    "",
6926    "",
6927    "",
6928    "",
6929    "",
6930    "",
6931    "",
6932    "stz2g requires: MTE",
6933    "stzg requires: MTE",
6934    "stzgm requires: MTE2",
6935    "",
6936    "subg requires: MTE",
6937    "subp requires: MTE",
6938    "subps requires: MTE",
6939    "",
6940    "",
6941    "swp requires: LSE",
6942    "swpa requires: LSE",
6943    "swpab requires: LSE",
6944    "swpah requires: LSE",
6945    "swpal requires: LSE",
6946    "swpalb requires: LSE",
6947    "swpalh requires: LSE",
6948    "swpb requires: LSE",
6949    "swph requires: LSE",
6950    "swpl requires: LSE",
6951    "swplb requires: LSE",
6952    "swplh requires: LSE",
6953    "",
6954    "",
6955    "",
6956    "",
6957    "",
6958    "",
6959    "",
6960    "",
6961    "",
6962    "",
6963    "",
6964    "",
6965    "",
6966    "",
6967    "umax requires: CSSC",
6968    "umin requires: CSSC",
6969    "",
6970    "",
6971    "",
6972    "",
6973    "",
6974    "",
6975    "",
6976    "",
6977    "xaflag requires: FLAGM2",
6978    "xpacd requires: PAUTH",
6979    "xpaci requires: PAUTH",
6980    "xpaclri requires: PAUTH",
6981    "",
6982    "abs requires: ASIMD",
6983    "add requires: ASIMD",
6984    "addhn requires: ASIMD",
6985    "addhn2 requires: ASIMD",
6986    "addp requires: ASIMD",
6987    "addv requires: ASIMD",
6988    "aesd requires: AES, ASIMD",
6989    "aese requires: AES, ASIMD",
6990    "aesimc requires: AES, ASIMD",
6991    "aesmc requires: AES, ASIMD",
6992    "and requires: ASIMD",
6993    "bcax requires: ASIMD, SHA3",
6994    "bfcvt requires: ASIMD, BF16",
6995    "bfcvtn requires: ASIMD, BF16",
6996    "bfcvtn2 requires: ASIMD, BF16",
6997    "bfdot requires: ASIMD, BF16",
6998    "bfmlalb requires: ASIMD, BF16",
6999    "bfmlalt requires: ASIMD, BF16",
7000    "bfmmla requires: ASIMD, BF16",
7001    "bic requires: ASIMD",
7002    "bif requires: ASIMD",
7003    "bit requires: ASIMD",
7004    "bsl requires: ASIMD",
7005    "cls requires: ASIMD",
7006    "clz requires: ASIMD",
7007    "cmeq requires: ASIMD",
7008    "cmge requires: ASIMD",
7009    "cmgt requires: ASIMD",
7010    "cmhi requires: ASIMD",
7011    "cmhs requires: ASIMD",
7012    "cmle requires: ASIMD",
7013    "cmlt requires: ASIMD",
7014    "cmtst requires: ASIMD",
7015    "cnt requires: ASIMD",
7016    "dup requires: ASIMD",
7017    "eor requires: ASIMD",
7018    "eor3 requires: ASIMD, SHA3",
7019    "ext requires: ASIMD",
7020    "fabd requires: ASIMD",
7021    "fabs requires: ASIMD",
7022    "facge requires: ASIMD",
7023    "facgt requires: ASIMD",
7024    "fadd requires: ASIMD",
7025    "faddp requires: ASIMD",
7026    "fcadd requires: ASIMD, FCMA",
7027    "fccmp requires: ASIMD",
7028    "fccmpe requires: ASIMD",
7029    "fcmeq requires: ASIMD",
7030    "fcmge requires: ASIMD",
7031    "fcmgt requires: ASIMD",
7032    "fcmla requires: ASIMD, FCMA",
7033    "fcmle requires: ASIMD",
7034    "fcmlt requires: ASIMD",
7035    "fcmp requires: ASIMD",
7036    "fcmpe requires: ASIMD",
7037    "fcsel requires: ASIMD",
7038    "fcvt requires: ASIMD",
7039    "fcvtas requires: ASIMD",
7040    "fcvtau requires: ASIMD",
7041    "fcvtl requires: ASIMD",
7042    "fcvtl2 requires: ASIMD",
7043    "fcvtms requires: ASIMD",
7044    "fcvtmu requires: ASIMD",
7045    "fcvtn requires: ASIMD",
7046    "fcvtn2 requires: ASIMD",
7047    "fcvtns requires: ASIMD",
7048    "fcvtnu requires: ASIMD",
7049    "fcvtps requires: ASIMD",
7050    "fcvtpu requires: ASIMD",
7051    "",
7052    "",
7053    "fcvtzs requires: ASIMD",
7054    "fcvtzu requires: ASIMD",
7055    "fdiv requires: ASIMD",
7056    "fjcvtzs requires: ASIMD, JSCVT",
7057    "fmadd requires: ASIMD",
7058    "fmax requires: ASIMD",
7059    "fmaxnm requires: ASIMD",
7060    "fmaxnmp requires: ASIMD",
7061    "fmaxnmv requires: ASIMD",
7062    "fmaxp requires: ASIMD",
7063    "fmaxv requires: ASIMD",
7064    "fmin requires: ASIMD",
7065    "fminnm requires: ASIMD",
7066    "fminnmp requires: ASIMD",
7067    "fminnmv requires: ASIMD",
7068    "fminp requires: ASIMD",
7069    "fminv requires: ASIMD",
7070    "fmla requires: ASIMD",
7071    "fmlal requires: ASIMD, FHM",
7072    "fmlal2 requires: ASIMD, FHM",
7073    "fmls requires: ASIMD",
7074    "fmlsl requires: ASIMD, FHM",
7075    "fmlsl2 requires: ASIMD, FHM",
7076    "fmov requires: ASIMD",
7077    "fmsub requires: ASIMD",
7078    "fmul requires: ASIMD",
7079    "fmulx requires: ASIMD",
7080    "fneg requires: ASIMD",
7081    "fnmadd requires: ASIMD",
7082    "fnmsub requires: ASIMD",
7083    "fnmul requires: ASIMD",
7084    "frecpe requires: ASIMD",
7085    "frecps requires: ASIMD",
7086    "frecpx requires: ASIMD",
7087    "frint32x requires: ASIMD, FRINTTS",
7088    "frint32z requires: ASIMD, FRINTTS",
7089    "frint64x requires: ASIMD, FRINTTS",
7090    "frint64z requires: ASIMD, FRINTTS",
7091    "frinta requires: ASIMD",
7092    "frinti requires: ASIMD",
7093    "frintm requires: ASIMD",
7094    "frintn requires: ASIMD",
7095    "frintp requires: ASIMD",
7096    "frintx requires: ASIMD",
7097    "frintz requires: ASIMD",
7098    "frsqrte requires: ASIMD",
7099    "frsqrts requires: ASIMD",
7100    "fsqrt requires: ASIMD",
7101    "fsub requires: ASIMD",
7102    "ins requires: ASIMD",
7103    "ld1 requires: ASIMD",
7104    "ld1r requires: ASIMD",
7105    "ld2 requires: ASIMD",
7106    "ld2r requires: ASIMD",
7107    "ld3 requires: ASIMD",
7108    "ld3r requires: ASIMD",
7109    "ld4 requires: ASIMD",
7110    "ld4r requires: ASIMD",
7111    "ldnp requires: ASIMD",
7112    "ldp requires: ASIMD",
7113    "ldr requires: ASIMD",
7114    "ldur requires: ASIMD",
7115    "mla requires: ASIMD",
7116    "mls requires: ASIMD",
7117    "mov requires: ASIMD",
7118    "movi requires: ASIMD",
7119    "mul requires: ASIMD",
7120    "mvn requires: ASIMD",
7121    "mvni requires: ASIMD",
7122    "neg requires: ASIMD",
7123    "not requires: ASIMD",
7124    "orn requires: ASIMD",
7125    "orr requires: ASIMD",
7126    "pmul requires: ASIMD",
7127    "pmull requires: ASIMD",
7128    "pmull2 requires: ASIMD",
7129    "raddhn requires: ASIMD",
7130    "raddhn2 requires: ASIMD",
7131    "rax1 requires: ASIMD, SHA3",
7132    "rbit requires: ASIMD",
7133    "rev16 requires: ASIMD",
7134    "rev32 requires: ASIMD",
7135    "rev64 requires: ASIMD",
7136    "rshrn requires: ASIMD",
7137    "rshrn2 requires: ASIMD",
7138    "rsubhn requires: ASIMD",
7139    "rsubhn2 requires: ASIMD",
7140    "saba requires: ASIMD",
7141    "sabal requires: ASIMD",
7142    "sabal2 requires: ASIMD",
7143    "sabd requires: ASIMD",
7144    "sabdl requires: ASIMD",
7145    "sabdl2 requires: ASIMD",
7146    "sadalp requires: ASIMD",
7147    "saddl requires: ASIMD",
7148    "saddl2 requires: ASIMD",
7149    "saddlp requires: ASIMD",
7150    "saddlv requires: ASIMD",
7151    "saddw requires: ASIMD",
7152    "saddw2 requires: ASIMD",
7153    "scvtf requires: ASIMD",
7154    "sdot requires: ASIMD, DOTPROD",
7155    "sha1c requires: ASIMD, SHA1",
7156    "sha1h requires: ASIMD, SHA1",
7157    "sha1m requires: ASIMD, SHA1",
7158    "sha1p requires: ASIMD, SHA1",
7159    "sha1su0 requires: ASIMD, SHA1",
7160    "sha1su1 requires: ASIMD, SHA1",
7161    "sha256h requires: ASIMD, SHA256",
7162    "sha256h2 requires: ASIMD, SHA256",
7163    "sha256su0 requires: ASIMD, SHA256",
7164    "sha256su1 requires: ASIMD, SHA256",
7165    "sha512h requires: ASIMD, SHA512",
7166    "sha512h2 requires: ASIMD, SHA512",
7167    "sha512su0 requires: ASIMD, SHA512",
7168    "sha512su1 requires: ASIMD, SHA512",
7169    "shadd requires: ASIMD",
7170    "shl requires: ASIMD",
7171    "shll requires: ASIMD",
7172    "shll2 requires: ASIMD",
7173    "shrn requires: ASIMD",
7174    "shrn2 requires: ASIMD",
7175    "shsub requires: ASIMD",
7176    "sli requires: ASIMD",
7177    "sm3partw1 requires: ASIMD, SM3",
7178    "sm3partw2 requires: ASIMD, SM3",
7179    "sm3ss1 requires: ASIMD, SM3",
7180    "sm3tt1a requires: ASIMD, SM3",
7181    "sm3tt1b requires: ASIMD, SM3",
7182    "sm3tt2a requires: ASIMD, SM3",
7183    "sm3tt2b requires: ASIMD, SM3",
7184    "sm4e requires: ASIMD, SM4",
7185    "sm4ekey requires: ASIMD, SM4",
7186    "smax requires: ASIMD",
7187    "smaxp requires: ASIMD",
7188    "smaxv requires: ASIMD",
7189    "smin requires: ASIMD",
7190    "sminp requires: ASIMD",
7191    "sminv requires: ASIMD",
7192    "smlal requires: ASIMD",
7193    "smlal2 requires: ASIMD",
7194    "smlsl requires: ASIMD",
7195    "smlsl2 requires: ASIMD",
7196    "smmla requires: ASIMD, I8MM",
7197    "smov requires: ASIMD",
7198    "smull requires: ASIMD",
7199    "smull2 requires: ASIMD",
7200    "sqabs requires: ASIMD",
7201    "sqadd requires: ASIMD",
7202    "sqdmlal requires: ASIMD",
7203    "sqdmlal2 requires: ASIMD",
7204    "sqdmlsl requires: ASIMD",
7205    "sqdmlsl2 requires: ASIMD",
7206    "sqdmulh requires: ASIMD",
7207    "sqdmull requires: ASIMD",
7208    "sqdmull2 requires: ASIMD",
7209    "sqneg requires: ASIMD",
7210    "sqrdmlah requires: ASIMD, RDM",
7211    "sqrdmlsh requires: ASIMD, RDM",
7212    "sqrdmulh requires: ASIMD",
7213    "sqrshl requires: ASIMD",
7214    "sqrshrn requires: ASIMD",
7215    "sqrshrn2 requires: ASIMD",
7216    "sqrshrun requires: ASIMD",
7217    "sqrshrun2 requires: ASIMD",
7218    "sqshl requires: ASIMD",
7219    "sqshlu requires: ASIMD",
7220    "sqshrn requires: ASIMD",
7221    "sqshrn2 requires: ASIMD",
7222    "sqshrun requires: ASIMD",
7223    "sqshrun2 requires: ASIMD",
7224    "sqsub requires: ASIMD",
7225    "sqxtn requires: ASIMD",
7226    "sqxtn2 requires: ASIMD",
7227    "sqxtun requires: ASIMD",
7228    "sqxtun2 requires: ASIMD",
7229    "srhadd requires: ASIMD",
7230    "sri requires: ASIMD",
7231    "srshl requires: ASIMD",
7232    "srshr requires: ASIMD",
7233    "srsra requires: ASIMD",
7234    "sshl requires: ASIMD",
7235    "sshll requires: ASIMD",
7236    "sshll2 requires: ASIMD",
7237    "sshr requires: ASIMD",
7238    "ssra requires: ASIMD",
7239    "ssubl requires: ASIMD",
7240    "ssubl2 requires: ASIMD",
7241    "ssubw requires: ASIMD",
7242    "ssubw2 requires: ASIMD",
7243    "st1 requires: ASIMD",
7244    "st2 requires: ASIMD",
7245    "st3 requires: ASIMD",
7246    "st4 requires: ASIMD",
7247    "stnp requires: ASIMD",
7248    "stp requires: ASIMD",
7249    "str requires: ASIMD",
7250    "stur requires: ASIMD",
7251    "sub requires: ASIMD",
7252    "subhn requires: ASIMD",
7253    "subhn2 requires: ASIMD",
7254    "sudot requires: ASIMD, I8MM",
7255    "suqadd requires: ASIMD",
7256    "sxtl requires: ASIMD",
7257    "sxtl2 requires: ASIMD",
7258    "tbl requires: ASIMD",
7259    "tbx requires: ASIMD",
7260    "trn1 requires: ASIMD",
7261    "trn2 requires: ASIMD",
7262    "uaba requires: ASIMD",
7263    "uabal requires: ASIMD",
7264    "uabal2 requires: ASIMD",
7265    "uabd requires: ASIMD",
7266    "uabdl requires: ASIMD",
7267    "uabdl2 requires: ASIMD",
7268    "uadalp requires: ASIMD",
7269    "uaddl requires: ASIMD",
7270    "uaddl2 requires: ASIMD",
7271    "uaddlp requires: ASIMD",
7272    "uaddlv requires: ASIMD",
7273    "uaddw requires: ASIMD",
7274    "uaddw2 requires: ASIMD",
7275    "ucvtf requires: ASIMD",
7276    "udot requires: ASIMD, DOTPROD",
7277    "uhadd requires: ASIMD",
7278    "uhsub requires: ASIMD",
7279    "umax requires: ASIMD",
7280    "umaxp requires: ASIMD",
7281    "umaxv requires: ASIMD",
7282    "umin requires: ASIMD",
7283    "uminp requires: ASIMD",
7284    "uminv requires: ASIMD",
7285    "umlal requires: ASIMD",
7286    "umlal2 requires: ASIMD",
7287    "umlsl requires: ASIMD",
7288    "umlsl2 requires: ASIMD",
7289    "ummla requires: ASIMD, I8MM",
7290    "umov requires: ASIMD",
7291    "umull requires: ASIMD",
7292    "umull2 requires: ASIMD",
7293    "uqadd requires: ASIMD",
7294    "uqrshl requires: ASIMD",
7295    "uqrshrn requires: ASIMD",
7296    "uqrshrn2 requires: ASIMD",
7297    "uqshl requires: ASIMD",
7298    "uqshrn requires: ASIMD",
7299    "uqshrn2 requires: ASIMD",
7300    "uqsub requires: ASIMD",
7301    "uqxtn requires: ASIMD",
7302    "uqxtn2 requires: ASIMD",
7303    "urecpe requires: ASIMD",
7304    "urhadd requires: ASIMD",
7305    "urshl requires: ASIMD",
7306    "urshr requires: ASIMD",
7307    "ursqrte requires: ASIMD",
7308    "ursra requires: ASIMD",
7309    "usdot requires: ASIMD, I8MM",
7310    "ushl requires: ASIMD",
7311    "ushll requires: ASIMD",
7312    "ushll2 requires: ASIMD",
7313    "ushr requires: ASIMD",
7314    "usmmla requires: ASIMD, I8MM",
7315    "usqadd requires: ASIMD",
7316    "usra requires: ASIMD",
7317    "usubl requires: ASIMD",
7318    "usubl2 requires: ASIMD",
7319    "usubw requires: ASIMD",
7320    "usubw2 requires: ASIMD",
7321    "uxtl requires: ASIMD",
7322    "uxtl2 requires: ASIMD",
7323    "uzp1 requires: ASIMD",
7324    "uzp2 requires: ASIMD",
7325    "xar requires: ASIMD, SHA3",
7326    "xtn requires: ASIMD",
7327    "xtn2 requires: ASIMD",
7328    "zip1 requires: ASIMD",
7329    "zip2 requires: ASIMD",
7330];
7331
7332static INST_FEATURE_FORM_OFFSETS: [u16; InstId::_Count as usize + 1] = [
7333    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
7334    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
7335    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
7336    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
7337    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
7338    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
7339    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
7340    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
7341    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
7342    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
7343    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
7344    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
7345    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
7346    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
7347    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 6, 9, 12, 15, 18, 18, 19, 20, 26,
7348    32, 38, 38, 41, 44, 46, 48, 49, 49, 54, 59, 59, 59, 64, 69, 72, 73, 78, 83, 88, 93, 93, 93,
7349    103, 113, 116, 116, 117, 120, 123, 126, 128, 131, 133, 136, 139, 142, 144, 147, 149, 154, 154,
7350    154, 159, 159, 159, 167, 168, 174, 180, 183, 184, 185, 186, 189, 192, 193, 193, 193, 193, 193,
7351    196, 199, 202, 205, 208, 211, 214, 217, 220, 223, 226, 226, 226, 226, 226, 226, 226, 226, 226,
7352    226, 226, 226, 226, 226, 226, 226, 226, 226, 226, 226, 226, 226, 226, 226, 226, 226, 226, 226,
7353    226, 226, 226, 226, 226, 226, 226, 226, 226, 226, 226, 226, 226, 226, 226, 226, 226, 226, 226,
7354    226, 226, 226, 226, 226, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236,
7355    236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236,
7356    236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236,
7357    236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236,
7358    236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236,
7359    236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236,
7360    236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 246, 246, 246, 246, 246, 246,
7361    246, 246, 246, 246, 246, 246, 246, 246, 246, 246, 246, 246, 246, 246, 246, 246, 246, 246, 246,
7362    246, 246, 246, 246, 246, 246, 246, 246, 246, 246, 246, 246, 246, 246, 246, 246, 246, 246, 246,
7363    246, 246, 246, 246, 246, 246, 246, 246, 246, 246, 246,
7364];
7365
7366static INST_FEATURE_FORMS: [InstFeatureForm; 246] = [
7367    InstFeatureForm {
7368        opcode_mask: 0xffe0fc00,
7369        opcode_value: 0x7ec01400,
7370        operand_signatures: [
7371            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7372            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7373            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7374            0,
7375            0,
7376            0,
7377        ],
7378        required: 0x0000000000004002,
7379        context: "fabd Hd, Hn, Hm requires: ASIMD, FP16",
7380    },
7381    InstFeatureForm {
7382        opcode_mask: 0xffe0fc00,
7383        opcode_value: 0x2ec01400,
7384        operand_signatures: [
7385            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7386            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7387            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7388            0,
7389            0,
7390            0,
7391        ],
7392        required: 0x0000000000004002,
7393        context: "fabd Vd.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
7394    },
7395    InstFeatureForm {
7396        opcode_mask: 0xffe0fc00,
7397        opcode_value: 0x6ec01400,
7398        operand_signatures: [
7399            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7400            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7401            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7402            0,
7403            0,
7404            0,
7405        ],
7406        required: 0x0000000000004002,
7407        context: "fabd Vd.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
7408    },
7409    InstFeatureForm {
7410        opcode_mask: 0xfffffc00,
7411        opcode_value: 0x1ee0c000,
7412        operand_signatures: [
7413            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7414            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7415            0,
7416            0,
7417            0,
7418            0,
7419        ],
7420        required: 0x0000000000004002,
7421        context: "fabs Hd, Hn requires: ASIMD, FP16",
7422    },
7423    InstFeatureForm {
7424        opcode_mask: 0xfffffc00,
7425        opcode_value: 0x0ef8f800,
7426        operand_signatures: [
7427            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7428            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7429            0,
7430            0,
7431            0,
7432            0,
7433        ],
7434        required: 0x0000000000004002,
7435        context: "fabs Vd.4H, Vn.4H requires: ASIMD, FP16",
7436    },
7437    InstFeatureForm {
7438        opcode_mask: 0xfffffc00,
7439        opcode_value: 0x4ef8f800,
7440        operand_signatures: [
7441            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7442            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7443            0,
7444            0,
7445            0,
7446            0,
7447        ],
7448        required: 0x0000000000004002,
7449        context: "fabs Vd.8H, Vn.8H requires: ASIMD, FP16",
7450    },
7451    InstFeatureForm {
7452        opcode_mask: 0xffe0fc00,
7453        opcode_value: 0x7e402c00,
7454        operand_signatures: [
7455            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7456            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7457            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7458            0,
7459            0,
7460            0,
7461        ],
7462        required: 0x0000000000004002,
7463        context: "facge Hd, Hn, Hm requires: ASIMD, FP16",
7464    },
7465    InstFeatureForm {
7466        opcode_mask: 0xffe0fc00,
7467        opcode_value: 0x2e402c00,
7468        operand_signatures: [
7469            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7470            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7471            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7472            0,
7473            0,
7474            0,
7475        ],
7476        required: 0x0000000000004002,
7477        context: "facge Vd.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
7478    },
7479    InstFeatureForm {
7480        opcode_mask: 0xffe0fc00,
7481        opcode_value: 0x6e402c00,
7482        operand_signatures: [
7483            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7484            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7485            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7486            0,
7487            0,
7488            0,
7489        ],
7490        required: 0x0000000000004002,
7491        context: "facge Vd.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
7492    },
7493    InstFeatureForm {
7494        opcode_mask: 0xffe0fc00,
7495        opcode_value: 0x7ec02c00,
7496        operand_signatures: [
7497            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7498            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7499            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7500            0,
7501            0,
7502            0,
7503        ],
7504        required: 0x0000000000004002,
7505        context: "facgt Hd, Hn, Hm requires: ASIMD, FP16",
7506    },
7507    InstFeatureForm {
7508        opcode_mask: 0xffe0fc00,
7509        opcode_value: 0x2ec02c00,
7510        operand_signatures: [
7511            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7512            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7513            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7514            0,
7515            0,
7516            0,
7517        ],
7518        required: 0x0000000000004002,
7519        context: "facgt Vd.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
7520    },
7521    InstFeatureForm {
7522        opcode_mask: 0xffe0fc00,
7523        opcode_value: 0x6ec02c00,
7524        operand_signatures: [
7525            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7526            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7527            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7528            0,
7529            0,
7530            0,
7531        ],
7532        required: 0x0000000000004002,
7533        context: "facgt Vd.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
7534    },
7535    InstFeatureForm {
7536        opcode_mask: 0xffe0fc00,
7537        opcode_value: 0x1ee02800,
7538        operand_signatures: [
7539            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7540            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7541            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7542            0,
7543            0,
7544            0,
7545        ],
7546        required: 0x0000000000004002,
7547        context: "fadd Hd, Hn, Hm requires: ASIMD, FP16",
7548    },
7549    InstFeatureForm {
7550        opcode_mask: 0xffe0fc00,
7551        opcode_value: 0x0e401400,
7552        operand_signatures: [
7553            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7554            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7555            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7556            0,
7557            0,
7558            0,
7559        ],
7560        required: 0x0000000000004002,
7561        context: "fadd Vd.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
7562    },
7563    InstFeatureForm {
7564        opcode_mask: 0xffe0fc00,
7565        opcode_value: 0x4e401400,
7566        operand_signatures: [
7567            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7568            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7569            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7570            0,
7571            0,
7572            0,
7573        ],
7574        required: 0x0000000000004002,
7575        context: "fadd Vd.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
7576    },
7577    InstFeatureForm {
7578        opcode_mask: 0xfffffc00,
7579        opcode_value: 0x5e30d800,
7580        operand_signatures: [
7581            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7582            feature_reg_signature(RegType::Vec32, VecElementType::H, false),
7583            0,
7584            0,
7585            0,
7586            0,
7587        ],
7588        required: 0x0000000000004002,
7589        context: "faddp Hd, Vn.2H requires: ASIMD, FP16",
7590    },
7591    InstFeatureForm {
7592        opcode_mask: 0xffe0fc00,
7593        opcode_value: 0x2e401400,
7594        operand_signatures: [
7595            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7596            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7597            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7598            0,
7599            0,
7600            0,
7601        ],
7602        required: 0x0000000000004002,
7603        context: "faddp Vd.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
7604    },
7605    InstFeatureForm {
7606        opcode_mask: 0xffe0fc00,
7607        opcode_value: 0x6e401400,
7608        operand_signatures: [
7609            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7610            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7611            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7612            0,
7613            0,
7614            0,
7615        ],
7616        required: 0x0000000000004002,
7617        context: "faddp Vd.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
7618    },
7619    InstFeatureForm {
7620        opcode_mask: 0xffe00c10,
7621        opcode_value: 0x1ee00400,
7622        operand_signatures: [
7623            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7624            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7625            OperandType::Imm as u32,
7626            OperandType::Imm as u32,
7627            0,
7628            0,
7629        ],
7630        required: 0x0000000000004002,
7631        context: "fccmp Hn, Hm, #nzcv, #cond requires: ASIMD, FP16",
7632    },
7633    InstFeatureForm {
7634        opcode_mask: 0xffe00c10,
7635        opcode_value: 0x1ee00410,
7636        operand_signatures: [
7637            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7638            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7639            OperandType::Imm as u32,
7640            OperandType::Imm as u32,
7641            0,
7642            0,
7643        ],
7644        required: 0x0000000000004002,
7645        context: "fccmpe Hn, Hm, #nzcv, #cond requires: ASIMD, FP16",
7646    },
7647    InstFeatureForm {
7648        opcode_mask: 0xfffffc00,
7649        opcode_value: 0x5ef8d800,
7650        operand_signatures: [
7651            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7652            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7653            OperandType::Imm as u32,
7654            0,
7655            0,
7656            0,
7657        ],
7658        required: 0x0000000000004002,
7659        context: "fcmeq Hd, Hn, #0 requires: ASIMD, FP16",
7660    },
7661    InstFeatureForm {
7662        opcode_mask: 0xfffffc00,
7663        opcode_value: 0x0ef8d800,
7664        operand_signatures: [
7665            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7666            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7667            OperandType::Imm as u32,
7668            0,
7669            0,
7670            0,
7671        ],
7672        required: 0x0000000000004002,
7673        context: "fcmeq Vd.4H, Vn.4H, #0 requires: ASIMD, FP16",
7674    },
7675    InstFeatureForm {
7676        opcode_mask: 0xfffffc00,
7677        opcode_value: 0x4ef8d800,
7678        operand_signatures: [
7679            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7680            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7681            OperandType::Imm as u32,
7682            0,
7683            0,
7684            0,
7685        ],
7686        required: 0x0000000000004002,
7687        context: "fcmeq Vd.8H, Vn.8H, #0 requires: ASIMD, FP16",
7688    },
7689    InstFeatureForm {
7690        opcode_mask: 0xffe0fc00,
7691        opcode_value: 0x5e402400,
7692        operand_signatures: [
7693            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7694            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7695            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7696            0,
7697            0,
7698            0,
7699        ],
7700        required: 0x0000000000004002,
7701        context: "fcmeq Hd, Hn, Hm requires: ASIMD, FP16",
7702    },
7703    InstFeatureForm {
7704        opcode_mask: 0xffe0fc00,
7705        opcode_value: 0x0e402400,
7706        operand_signatures: [
7707            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7708            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7709            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7710            0,
7711            0,
7712            0,
7713        ],
7714        required: 0x0000000000004002,
7715        context: "fcmeq Vd.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
7716    },
7717    InstFeatureForm {
7718        opcode_mask: 0xffe0fc00,
7719        opcode_value: 0x4e402400,
7720        operand_signatures: [
7721            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7722            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7723            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7724            0,
7725            0,
7726            0,
7727        ],
7728        required: 0x0000000000004002,
7729        context: "fcmeq Vd.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
7730    },
7731    InstFeatureForm {
7732        opcode_mask: 0xfffffc00,
7733        opcode_value: 0x7ef8c800,
7734        operand_signatures: [
7735            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7736            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7737            OperandType::Imm as u32,
7738            0,
7739            0,
7740            0,
7741        ],
7742        required: 0x0000000000004002,
7743        context: "fcmge Hd, Hn, #0 requires: ASIMD, FP16",
7744    },
7745    InstFeatureForm {
7746        opcode_mask: 0xfffffc00,
7747        opcode_value: 0x2ef8c800,
7748        operand_signatures: [
7749            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7750            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7751            OperandType::Imm as u32,
7752            0,
7753            0,
7754            0,
7755        ],
7756        required: 0x0000000000004002,
7757        context: "fcmge Vd.4H, Vn.4H, #0 requires: ASIMD, FP16",
7758    },
7759    InstFeatureForm {
7760        opcode_mask: 0xfffffc00,
7761        opcode_value: 0x6ef8c800,
7762        operand_signatures: [
7763            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7764            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7765            OperandType::Imm as u32,
7766            0,
7767            0,
7768            0,
7769        ],
7770        required: 0x0000000000004002,
7771        context: "fcmge Vd.8H, Vn.8H, #0 requires: ASIMD, FP16",
7772    },
7773    InstFeatureForm {
7774        opcode_mask: 0xffe0fc00,
7775        opcode_value: 0x7e402400,
7776        operand_signatures: [
7777            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7778            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7779            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7780            0,
7781            0,
7782            0,
7783        ],
7784        required: 0x0000000000004002,
7785        context: "fcmge Hd, Hn, Hm requires: ASIMD, FP16",
7786    },
7787    InstFeatureForm {
7788        opcode_mask: 0xffe0fc00,
7789        opcode_value: 0x2e402400,
7790        operand_signatures: [
7791            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7792            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7793            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7794            0,
7795            0,
7796            0,
7797        ],
7798        required: 0x0000000000004002,
7799        context: "fcmge Vd.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
7800    },
7801    InstFeatureForm {
7802        opcode_mask: 0xffe0fc00,
7803        opcode_value: 0x6e402400,
7804        operand_signatures: [
7805            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7806            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7807            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7808            0,
7809            0,
7810            0,
7811        ],
7812        required: 0x0000000000004002,
7813        context: "fcmge Vd.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
7814    },
7815    InstFeatureForm {
7816        opcode_mask: 0xfffffc00,
7817        opcode_value: 0x5ef8c800,
7818        operand_signatures: [
7819            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7820            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7821            OperandType::Imm as u32,
7822            0,
7823            0,
7824            0,
7825        ],
7826        required: 0x0000000000004002,
7827        context: "fcmgt Hd, Hn, #0 requires: ASIMD, FP16",
7828    },
7829    InstFeatureForm {
7830        opcode_mask: 0xfffffc00,
7831        opcode_value: 0x0ef8c800,
7832        operand_signatures: [
7833            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7834            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7835            OperandType::Imm as u32,
7836            0,
7837            0,
7838            0,
7839        ],
7840        required: 0x0000000000004002,
7841        context: "fcmgt Vd.4H, Vn.4H, #0 requires: ASIMD, FP16",
7842    },
7843    InstFeatureForm {
7844        opcode_mask: 0xfffffc00,
7845        opcode_value: 0x4ef8c800,
7846        operand_signatures: [
7847            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7848            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7849            OperandType::Imm as u32,
7850            0,
7851            0,
7852            0,
7853        ],
7854        required: 0x0000000000004002,
7855        context: "fcmgt Vd.8H, Vn.8H, #0 requires: ASIMD, FP16",
7856    },
7857    InstFeatureForm {
7858        opcode_mask: 0xffe0fc00,
7859        opcode_value: 0x7ec02400,
7860        operand_signatures: [
7861            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7862            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7863            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7864            0,
7865            0,
7866            0,
7867        ],
7868        required: 0x0000000000004002,
7869        context: "fcmgt Hd, Hn, Hm requires: ASIMD, FP16",
7870    },
7871    InstFeatureForm {
7872        opcode_mask: 0xffe0fc00,
7873        opcode_value: 0x2ec02400,
7874        operand_signatures: [
7875            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7876            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7877            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7878            0,
7879            0,
7880            0,
7881        ],
7882        required: 0x0000000000004002,
7883        context: "fcmgt Vd.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
7884    },
7885    InstFeatureForm {
7886        opcode_mask: 0xffe0fc00,
7887        opcode_value: 0x6ec02400,
7888        operand_signatures: [
7889            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7890            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7891            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7892            0,
7893            0,
7894            0,
7895        ],
7896        required: 0x0000000000004002,
7897        context: "fcmgt Vd.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
7898    },
7899    InstFeatureForm {
7900        opcode_mask: 0xfffffc00,
7901        opcode_value: 0x7ef8d800,
7902        operand_signatures: [
7903            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7904            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7905            OperandType::Imm as u32,
7906            0,
7907            0,
7908            0,
7909        ],
7910        required: 0x0000000000004002,
7911        context: "fcmle Hd, Hn, #0 requires: ASIMD, FP16",
7912    },
7913    InstFeatureForm {
7914        opcode_mask: 0xfffffc00,
7915        opcode_value: 0x2ef8d800,
7916        operand_signatures: [
7917            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7918            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7919            OperandType::Imm as u32,
7920            0,
7921            0,
7922            0,
7923        ],
7924        required: 0x0000000000004002,
7925        context: "fcmle Vd.4H, Vn.4H, #0 requires: ASIMD, FP16",
7926    },
7927    InstFeatureForm {
7928        opcode_mask: 0xfffffc00,
7929        opcode_value: 0x6ef8d800,
7930        operand_signatures: [
7931            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7932            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7933            OperandType::Imm as u32,
7934            0,
7935            0,
7936            0,
7937        ],
7938        required: 0x0000000000004002,
7939        context: "fcmle Vd.8H, Vn.8H, #0 requires: ASIMD, FP16",
7940    },
7941    InstFeatureForm {
7942        opcode_mask: 0xfffffc00,
7943        opcode_value: 0x5ef8e800,
7944        operand_signatures: [
7945            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7946            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7947            OperandType::Imm as u32,
7948            0,
7949            0,
7950            0,
7951        ],
7952        required: 0x0000000000004002,
7953        context: "fcmlt Hd, Hn, #0 requires: ASIMD, FP16",
7954    },
7955    InstFeatureForm {
7956        opcode_mask: 0xfffffc00,
7957        opcode_value: 0x0ef8e800,
7958        operand_signatures: [
7959            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7960            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7961            OperandType::Imm as u32,
7962            0,
7963            0,
7964            0,
7965        ],
7966        required: 0x0000000000004002,
7967        context: "fcmlt Vd.4H, Vn.4H, #0 requires: ASIMD, FP16",
7968    },
7969    InstFeatureForm {
7970        opcode_mask: 0xfffffc00,
7971        opcode_value: 0x4ef8e800,
7972        operand_signatures: [
7973            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7974            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7975            OperandType::Imm as u32,
7976            0,
7977            0,
7978            0,
7979        ],
7980        required: 0x0000000000004002,
7981        context: "fcmlt Vd.8H, Vn.8H, #0 requires: ASIMD, FP16",
7982    },
7983    InstFeatureForm {
7984        opcode_mask: 0xfffffc1f,
7985        opcode_value: 0x1ee02008,
7986        operand_signatures: [
7987            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7988            OperandType::Imm as u32,
7989            0,
7990            0,
7991            0,
7992            0,
7993        ],
7994        required: 0x0000000000004002,
7995        context: "fcmp Hn, #0 requires: ASIMD, FP16",
7996    },
7997    InstFeatureForm {
7998        opcode_mask: 0xffe0fc1f,
7999        opcode_value: 0x1ee02000,
8000        operand_signatures: [
8001            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8002            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8003            0,
8004            0,
8005            0,
8006            0,
8007        ],
8008        required: 0x0000000000004002,
8009        context: "fcmp Hn, Hm requires: ASIMD, FP16",
8010    },
8011    InstFeatureForm {
8012        opcode_mask: 0xfffffc1f,
8013        opcode_value: 0x1ee02018,
8014        operand_signatures: [
8015            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8016            OperandType::Imm as u32,
8017            0,
8018            0,
8019            0,
8020            0,
8021        ],
8022        required: 0x0000000000004002,
8023        context: "fcmpe Hn, #0 requires: ASIMD, FP16",
8024    },
8025    InstFeatureForm {
8026        opcode_mask: 0xffe0fc1f,
8027        opcode_value: 0x1ee02010,
8028        operand_signatures: [
8029            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8030            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8031            0,
8032            0,
8033            0,
8034            0,
8035        ],
8036        required: 0x0000000000004002,
8037        context: "fcmpe Hn, Hm requires: ASIMD, FP16",
8038    },
8039    InstFeatureForm {
8040        opcode_mask: 0xffe00c00,
8041        opcode_value: 0x1ee00c00,
8042        operand_signatures: [
8043            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8044            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8045            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8046            OperandType::Imm as u32,
8047            0,
8048            0,
8049        ],
8050        required: 0x0000000000004002,
8051        context: "fcsel Hd, Hn, Hm, #cond requires: ASIMD, FP16",
8052    },
8053    InstFeatureForm {
8054        opcode_mask: 0xfffffc00,
8055        opcode_value: 0x1ee40000,
8056        operand_signatures: [
8057            feature_reg_signature(RegType::Gp32, VecElementType::None, false),
8058            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8059            0,
8060            0,
8061            0,
8062            0,
8063        ],
8064        required: 0x0000000000004002,
8065        context: "fcvtas Wd, Hn requires: ASIMD, FP16",
8066    },
8067    InstFeatureForm {
8068        opcode_mask: 0xfffffc00,
8069        opcode_value: 0x9ee40000,
8070        operand_signatures: [
8071            feature_reg_signature(RegType::Gp64, VecElementType::None, false),
8072            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8073            0,
8074            0,
8075            0,
8076            0,
8077        ],
8078        required: 0x0000000000004002,
8079        context: "fcvtas Xd, Hn requires: ASIMD, FP16",
8080    },
8081    InstFeatureForm {
8082        opcode_mask: 0xfffffc00,
8083        opcode_value: 0x5e79c800,
8084        operand_signatures: [
8085            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8086            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8087            0,
8088            0,
8089            0,
8090            0,
8091        ],
8092        required: 0x0000000000004002,
8093        context: "fcvtas Hd, Hn requires: ASIMD, FP16",
8094    },
8095    InstFeatureForm {
8096        opcode_mask: 0xfffffc00,
8097        opcode_value: 0x0e79c800,
8098        operand_signatures: [
8099            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8100            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8101            0,
8102            0,
8103            0,
8104            0,
8105        ],
8106        required: 0x0000000000004002,
8107        context: "fcvtas Vd.4H, Vn.4H requires: ASIMD, FP16",
8108    },
8109    InstFeatureForm {
8110        opcode_mask: 0xfffffc00,
8111        opcode_value: 0x4e79c800,
8112        operand_signatures: [
8113            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8114            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8115            0,
8116            0,
8117            0,
8118            0,
8119        ],
8120        required: 0x0000000000004002,
8121        context: "fcvtas Vd.8H, Vn.8H requires: ASIMD, FP16",
8122    },
8123    InstFeatureForm {
8124        opcode_mask: 0xfffffc00,
8125        opcode_value: 0x1ee50000,
8126        operand_signatures: [
8127            feature_reg_signature(RegType::Gp32, VecElementType::None, false),
8128            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8129            0,
8130            0,
8131            0,
8132            0,
8133        ],
8134        required: 0x0000000000004002,
8135        context: "fcvtau Wd, Hn requires: ASIMD, FP16",
8136    },
8137    InstFeatureForm {
8138        opcode_mask: 0xfffffc00,
8139        opcode_value: 0x9ee50000,
8140        operand_signatures: [
8141            feature_reg_signature(RegType::Gp64, VecElementType::None, false),
8142            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8143            0,
8144            0,
8145            0,
8146            0,
8147        ],
8148        required: 0x0000000000004002,
8149        context: "fcvtau Xd, Hn requires: ASIMD, FP16",
8150    },
8151    InstFeatureForm {
8152        opcode_mask: 0xfffffc00,
8153        opcode_value: 0x7e79c800,
8154        operand_signatures: [
8155            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8156            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8157            0,
8158            0,
8159            0,
8160            0,
8161        ],
8162        required: 0x0000000000004002,
8163        context: "fcvtau Hd, Hn requires: ASIMD, FP16",
8164    },
8165    InstFeatureForm {
8166        opcode_mask: 0xfffffc00,
8167        opcode_value: 0x2e79c800,
8168        operand_signatures: [
8169            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8170            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8171            0,
8172            0,
8173            0,
8174            0,
8175        ],
8176        required: 0x0000000000004002,
8177        context: "fcvtau Vd.4H, Vn.4H requires: ASIMD, FP16",
8178    },
8179    InstFeatureForm {
8180        opcode_mask: 0xfffffc00,
8181        opcode_value: 0x6e79c800,
8182        operand_signatures: [
8183            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8184            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8185            0,
8186            0,
8187            0,
8188            0,
8189        ],
8190        required: 0x0000000000004002,
8191        context: "fcvtau Vd.8H, Vn.8H requires: ASIMD, FP16",
8192    },
8193    InstFeatureForm {
8194        opcode_mask: 0xfffffc00,
8195        opcode_value: 0x1ef00000,
8196        operand_signatures: [
8197            feature_reg_signature(RegType::Gp32, VecElementType::None, false),
8198            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8199            0,
8200            0,
8201            0,
8202            0,
8203        ],
8204        required: 0x0000000000004002,
8205        context: "fcvtms Wd, Hn requires: ASIMD, FP16",
8206    },
8207    InstFeatureForm {
8208        opcode_mask: 0xfffffc00,
8209        opcode_value: 0x9ef00000,
8210        operand_signatures: [
8211            feature_reg_signature(RegType::Gp64, VecElementType::None, false),
8212            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8213            0,
8214            0,
8215            0,
8216            0,
8217        ],
8218        required: 0x0000000000004002,
8219        context: "fcvtms Xd, Hn requires: ASIMD, FP16",
8220    },
8221    InstFeatureForm {
8222        opcode_mask: 0xfffffc00,
8223        opcode_value: 0x5e79b800,
8224        operand_signatures: [
8225            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8226            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8227            0,
8228            0,
8229            0,
8230            0,
8231        ],
8232        required: 0x0000000000004002,
8233        context: "fcvtms Hd, Hn requires: ASIMD, FP16",
8234    },
8235    InstFeatureForm {
8236        opcode_mask: 0xfffffc00,
8237        opcode_value: 0x0e79b800,
8238        operand_signatures: [
8239            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8240            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8241            0,
8242            0,
8243            0,
8244            0,
8245        ],
8246        required: 0x0000000000004002,
8247        context: "fcvtms Vd.4H, Vn.4H requires: ASIMD, FP16",
8248    },
8249    InstFeatureForm {
8250        opcode_mask: 0xfffffc00,
8251        opcode_value: 0x4e79b800,
8252        operand_signatures: [
8253            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8254            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8255            0,
8256            0,
8257            0,
8258            0,
8259        ],
8260        required: 0x0000000000004002,
8261        context: "fcvtms Vd.8H, Vn.8H requires: ASIMD, FP16",
8262    },
8263    InstFeatureForm {
8264        opcode_mask: 0xfffffc00,
8265        opcode_value: 0x1ef10000,
8266        operand_signatures: [
8267            feature_reg_signature(RegType::Gp32, VecElementType::None, false),
8268            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8269            0,
8270            0,
8271            0,
8272            0,
8273        ],
8274        required: 0x0000000000004002,
8275        context: "fcvtmu Wd, Hn requires: ASIMD, FP16",
8276    },
8277    InstFeatureForm {
8278        opcode_mask: 0xfffffc00,
8279        opcode_value: 0x9ef10000,
8280        operand_signatures: [
8281            feature_reg_signature(RegType::Gp64, VecElementType::None, false),
8282            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8283            0,
8284            0,
8285            0,
8286            0,
8287        ],
8288        required: 0x0000000000004002,
8289        context: "fcvtmu Xd, Hn requires: ASIMD, FP16",
8290    },
8291    InstFeatureForm {
8292        opcode_mask: 0xfffffc00,
8293        opcode_value: 0x7e79b800,
8294        operand_signatures: [
8295            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8296            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8297            0,
8298            0,
8299            0,
8300            0,
8301        ],
8302        required: 0x0000000000004002,
8303        context: "fcvtmu Hd, Hn requires: ASIMD, FP16",
8304    },
8305    InstFeatureForm {
8306        opcode_mask: 0xfffffc00,
8307        opcode_value: 0x2e79b800,
8308        operand_signatures: [
8309            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8310            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8311            0,
8312            0,
8313            0,
8314            0,
8315        ],
8316        required: 0x0000000000004002,
8317        context: "fcvtmu Vd.4H, Vn.4H requires: ASIMD, FP16",
8318    },
8319    InstFeatureForm {
8320        opcode_mask: 0xfffffc00,
8321        opcode_value: 0x6e79b800,
8322        operand_signatures: [
8323            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8324            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8325            0,
8326            0,
8327            0,
8328            0,
8329        ],
8330        required: 0x0000000000004002,
8331        context: "fcvtmu Vd.8H, Vn.8H requires: ASIMD, FP16",
8332    },
8333    InstFeatureForm {
8334        opcode_mask: 0xffe0fc00,
8335        opcode_value: 0x0e40f400,
8336        operand_signatures: [
8337            feature_reg_signature(RegType::Vec64, VecElementType::B, false),
8338            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8339            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8340            0,
8341            0,
8342            0,
8343        ],
8344        required: 0x0000000000008002,
8345        context: "fcvtn Vd.8B, Vn.4H, Vm.4H requires: ASIMD, FP8",
8346    },
8347    InstFeatureForm {
8348        opcode_mask: 0xffe0fc00,
8349        opcode_value: 0x4e40f400,
8350        operand_signatures: [
8351            feature_reg_signature(RegType::Vec128, VecElementType::B, false),
8352            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8353            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8354            0,
8355            0,
8356            0,
8357        ],
8358        required: 0x0000000000008002,
8359        context: "fcvtn Vd.16B, Vn.8H, Vm.8H requires: ASIMD, FP8",
8360    },
8361    InstFeatureForm {
8362        opcode_mask: 0xffe0fc00,
8363        opcode_value: 0x0e00f400,
8364        operand_signatures: [
8365            feature_reg_signature(RegType::Vec64, VecElementType::B, false),
8366            feature_reg_signature(RegType::Vec128, VecElementType::S, false),
8367            feature_reg_signature(RegType::Vec128, VecElementType::S, false),
8368            0,
8369            0,
8370            0,
8371        ],
8372        required: 0x0000000000008002,
8373        context: "fcvtn Vd.8B, Vn.4S, Vm.4S requires: ASIMD, FP8",
8374    },
8375    InstFeatureForm {
8376        opcode_mask: 0xffe0fc00,
8377        opcode_value: 0x4e00f400,
8378        operand_signatures: [
8379            feature_reg_signature(RegType::Vec128, VecElementType::B, false),
8380            feature_reg_signature(RegType::Vec128, VecElementType::S, false),
8381            feature_reg_signature(RegType::Vec128, VecElementType::S, false),
8382            0,
8383            0,
8384            0,
8385        ],
8386        required: 0x0000000000008002,
8387        context: "fcvtn2 Vx.16B, Vn.4S, Vm.4S requires: ASIMD, FP8",
8388    },
8389    InstFeatureForm {
8390        opcode_mask: 0xfffffc00,
8391        opcode_value: 0x1ee00000,
8392        operand_signatures: [
8393            feature_reg_signature(RegType::Gp32, VecElementType::None, false),
8394            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8395            0,
8396            0,
8397            0,
8398            0,
8399        ],
8400        required: 0x0000000000004002,
8401        context: "fcvtns Wd, Hn requires: ASIMD, FP16",
8402    },
8403    InstFeatureForm {
8404        opcode_mask: 0xfffffc00,
8405        opcode_value: 0x9ee00000,
8406        operand_signatures: [
8407            feature_reg_signature(RegType::Gp64, VecElementType::None, false),
8408            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8409            0,
8410            0,
8411            0,
8412            0,
8413        ],
8414        required: 0x0000000000004002,
8415        context: "fcvtns Xd, Hn requires: ASIMD, FP16",
8416    },
8417    InstFeatureForm {
8418        opcode_mask: 0xfffffc00,
8419        opcode_value: 0x5e79a800,
8420        operand_signatures: [
8421            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8422            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8423            0,
8424            0,
8425            0,
8426            0,
8427        ],
8428        required: 0x0000000000004002,
8429        context: "fcvtns Hd, Hn requires: ASIMD, FP16",
8430    },
8431    InstFeatureForm {
8432        opcode_mask: 0xfffffc00,
8433        opcode_value: 0x0e79a800,
8434        operand_signatures: [
8435            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8436            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8437            0,
8438            0,
8439            0,
8440            0,
8441        ],
8442        required: 0x0000000000004002,
8443        context: "fcvtns Vd.4H, Vn.4H requires: ASIMD, FP16",
8444    },
8445    InstFeatureForm {
8446        opcode_mask: 0xfffffc00,
8447        opcode_value: 0x4e79a800,
8448        operand_signatures: [
8449            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8450            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
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8452            0,
8453            0,
8454            0,
8455        ],
8456        required: 0x0000000000004002,
8457        context: "fcvtns Vd.8H, Vn.8H requires: ASIMD, FP16",
8458    },
8459    InstFeatureForm {
8460        opcode_mask: 0xfffffc00,
8461        opcode_value: 0x1ee10000,
8462        operand_signatures: [
8463            feature_reg_signature(RegType::Gp32, VecElementType::None, false),
8464            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8465            0,
8466            0,
8467            0,
8468            0,
8469        ],
8470        required: 0x0000000000004002,
8471        context: "fcvtnu Wd, Hn requires: ASIMD, FP16",
8472    },
8473    InstFeatureForm {
8474        opcode_mask: 0xfffffc00,
8475        opcode_value: 0x9ee10000,
8476        operand_signatures: [
8477            feature_reg_signature(RegType::Gp64, VecElementType::None, false),
8478            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8479            0,
8480            0,
8481            0,
8482            0,
8483        ],
8484        required: 0x0000000000004002,
8485        context: "fcvtnu Xd, Hn requires: ASIMD, FP16",
8486    },
8487    InstFeatureForm {
8488        opcode_mask: 0xfffffc00,
8489        opcode_value: 0x7e79a800,
8490        operand_signatures: [
8491            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8492            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8493            0,
8494            0,
8495            0,
8496            0,
8497        ],
8498        required: 0x0000000000004002,
8499        context: "fcvtnu Hd, Hn requires: ASIMD, FP16",
8500    },
8501    InstFeatureForm {
8502        opcode_mask: 0xfffffc00,
8503        opcode_value: 0x2e79a800,
8504        operand_signatures: [
8505            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8506            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8507            0,
8508            0,
8509            0,
8510            0,
8511        ],
8512        required: 0x0000000000004002,
8513        context: "fcvtnu Vd.4H, Vn.4H requires: ASIMD, FP16",
8514    },
8515    InstFeatureForm {
8516        opcode_mask: 0xfffffc00,
8517        opcode_value: 0x6e79a800,
8518        operand_signatures: [
8519            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8520            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8521            0,
8522            0,
8523            0,
8524            0,
8525        ],
8526        required: 0x0000000000004002,
8527        context: "fcvtnu Vd.8H, Vn.8H requires: ASIMD, FP16",
8528    },
8529    InstFeatureForm {
8530        opcode_mask: 0xfffffc00,
8531        opcode_value: 0x1ee80000,
8532        operand_signatures: [
8533            feature_reg_signature(RegType::Gp32, VecElementType::None, false),
8534            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8535            0,
8536            0,
8537            0,
8538            0,
8539        ],
8540        required: 0x0000000000004002,
8541        context: "fcvtps Wd, Hn requires: ASIMD, FP16",
8542    },
8543    InstFeatureForm {
8544        opcode_mask: 0xfffffc00,
8545        opcode_value: 0x9ee80000,
8546        operand_signatures: [
8547            feature_reg_signature(RegType::Gp64, VecElementType::None, false),
8548            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8549            0,
8550            0,
8551            0,
8552            0,
8553        ],
8554        required: 0x0000000000004002,
8555        context: "fcvtps Xd, Hn requires: ASIMD, FP16",
8556    },
8557    InstFeatureForm {
8558        opcode_mask: 0xfffffc00,
8559        opcode_value: 0x5ef9a800,
8560        operand_signatures: [
8561            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8562            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8563            0,
8564            0,
8565            0,
8566            0,
8567        ],
8568        required: 0x0000000000004002,
8569        context: "fcvtps Hd, Hn requires: ASIMD, FP16",
8570    },
8571    InstFeatureForm {
8572        opcode_mask: 0xfffffc00,
8573        opcode_value: 0x0ef9a800,
8574        operand_signatures: [
8575            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8576            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8577            0,
8578            0,
8579            0,
8580            0,
8581        ],
8582        required: 0x0000000000004002,
8583        context: "fcvtps Vd.4H, Vn.4H requires: ASIMD, FP16",
8584    },
8585    InstFeatureForm {
8586        opcode_mask: 0xfffffc00,
8587        opcode_value: 0x4ef9a800,
8588        operand_signatures: [
8589            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8590            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8591            0,
8592            0,
8593            0,
8594            0,
8595        ],
8596        required: 0x0000000000004002,
8597        context: "fcvtps Vd.8H, Vn.8H requires: ASIMD, FP16",
8598    },
8599    InstFeatureForm {
8600        opcode_mask: 0xfffffc00,
8601        opcode_value: 0x1ee90000,
8602        operand_signatures: [
8603            feature_reg_signature(RegType::Gp32, VecElementType::None, false),
8604            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8605            0,
8606            0,
8607            0,
8608            0,
8609        ],
8610        required: 0x0000000000004002,
8611        context: "fcvtpu Wd, Hn requires: ASIMD, FP16",
8612    },
8613    InstFeatureForm {
8614        opcode_mask: 0xfffffc00,
8615        opcode_value: 0x9ee90000,
8616        operand_signatures: [
8617            feature_reg_signature(RegType::Gp64, VecElementType::None, false),
8618            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8619            0,
8620            0,
8621            0,
8622            0,
8623        ],
8624        required: 0x0000000000004002,
8625        context: "fcvtpu Xd, Hn requires: ASIMD, FP16",
8626    },
8627    InstFeatureForm {
8628        opcode_mask: 0xfffffc00,
8629        opcode_value: 0x7ef9a800,
8630        operand_signatures: [
8631            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8632            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8633            0,
8634            0,
8635            0,
8636            0,
8637        ],
8638        required: 0x0000000000004002,
8639        context: "fcvtpu Hd, Hn requires: ASIMD, FP16",
8640    },
8641    InstFeatureForm {
8642        opcode_mask: 0xfffffc00,
8643        opcode_value: 0x2ef9a800,
8644        operand_signatures: [
8645            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8646            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8647            0,
8648            0,
8649            0,
8650            0,
8651        ],
8652        required: 0x0000000000004002,
8653        context: "fcvtpu Vd.4H, Vn.4H requires: ASIMD, FP16",
8654    },
8655    InstFeatureForm {
8656        opcode_mask: 0xfffffc00,
8657        opcode_value: 0x6ef9a800,
8658        operand_signatures: [
8659            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8660            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8661            0,
8662            0,
8663            0,
8664            0,
8665        ],
8666        required: 0x0000000000004002,
8667        context: "fcvtpu Vd.8H, Vn.8H requires: ASIMD, FP16",
8668    },
8669    InstFeatureForm {
8670        opcode_mask: 0xfffffc00,
8671        opcode_value: 0x1ef80000,
8672        operand_signatures: [
8673            feature_reg_signature(RegType::Gp32, VecElementType::None, false),
8674            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8675            0,
8676            0,
8677            0,
8678            0,
8679        ],
8680        required: 0x0000000000004002,
8681        context: "fcvtzs Wd, Hn requires: ASIMD, FP16",
8682    },
8683    InstFeatureForm {
8684        opcode_mask: 0xfffffc00,
8685        opcode_value: 0x9ef80000,
8686        operand_signatures: [
8687            feature_reg_signature(RegType::Gp64, VecElementType::None, false),
8688            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8689            0,
8690            0,
8691            0,
8692            0,
8693        ],
8694        required: 0x0000000000004002,
8695        context: "fcvtzs Xd, Hn requires: ASIMD, FP16",
8696    },
8697    InstFeatureForm {
8698        opcode_mask: 0xfffffc00,
8699        opcode_value: 0x5ef9b800,
8700        operand_signatures: [
8701            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8702            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8703            0,
8704            0,
8705            0,
8706            0,
8707        ],
8708        required: 0x0000000000004002,
8709        context: "fcvtzs Hd, Hn requires: ASIMD, FP16",
8710    },
8711    InstFeatureForm {
8712        opcode_mask: 0xfffffc00,
8713        opcode_value: 0x0ef9b800,
8714        operand_signatures: [
8715            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8716            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8717            0,
8718            0,
8719            0,
8720            0,
8721        ],
8722        required: 0x0000000000004002,
8723        context: "fcvtzs Vd.4H, Vn.4H requires: ASIMD, FP16",
8724    },
8725    InstFeatureForm {
8726        opcode_mask: 0xfffffc00,
8727        opcode_value: 0x4ef9b800,
8728        operand_signatures: [
8729            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8730            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8731            0,
8732            0,
8733            0,
8734            0,
8735        ],
8736        required: 0x0000000000004002,
8737        context: "fcvtzs Vd.8H, Vn.8H requires: ASIMD, FP16",
8738    },
8739    InstFeatureForm {
8740        opcode_mask: 0xffff0000,
8741        opcode_value: 0x1ed80000,
8742        operand_signatures: [
8743            feature_reg_signature(RegType::Gp32, VecElementType::None, false),
8744            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8745            OperandType::Imm as u32,
8746            0,
8747            0,
8748            0,
8749        ],
8750        required: 0x0000000000004002,
8751        context: "fcvtzs Wd, Hn, #fbits requires: ASIMD, FP16",
8752    },
8753    InstFeatureForm {
8754        opcode_mask: 0xffff0000,
8755        opcode_value: 0x9ed80000,
8756        operand_signatures: [
8757            feature_reg_signature(RegType::Gp64, VecElementType::None, false),
8758            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8759            OperandType::Imm as u32,
8760            0,
8761            0,
8762            0,
8763        ],
8764        required: 0x0000000000004002,
8765        context: "fcvtzs Xd, Hn, #fbits requires: ASIMD, FP16",
8766    },
8767    InstFeatureForm {
8768        opcode_mask: 0xff80fc00,
8769        opcode_value: 0x5f00fc00,
8770        operand_signatures: [
8771            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8772            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8773            OperandType::Imm as u32,
8774            0,
8775            0,
8776            0,
8777        ],
8778        required: 0x0000000000004002,
8779        context: "fcvtzs Hd, Hn, #fbits requires: ASIMD, FP16",
8780    },
8781    InstFeatureForm {
8782        opcode_mask: 0xff80fc00,
8783        opcode_value: 0x0f00fc00,
8784        operand_signatures: [
8785            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8786            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8787            OperandType::Imm as u32,
8788            0,
8789            0,
8790            0,
8791        ],
8792        required: 0x0000000000004002,
8793        context: "fcvtzs Vd.4H, Vn.4H, #fbits requires: ASIMD, FP16",
8794    },
8795    InstFeatureForm {
8796        opcode_mask: 0xff80fc00,
8797        opcode_value: 0x4f00fc00,
8798        operand_signatures: [
8799            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8800            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8801            OperandType::Imm as u32,
8802            0,
8803            0,
8804            0,
8805        ],
8806        required: 0x0000000000004002,
8807        context: "fcvtzs Vd.8H, Vn.8H, #fbits requires: ASIMD, FP16",
8808    },
8809    InstFeatureForm {
8810        opcode_mask: 0xfffffc00,
8811        opcode_value: 0x1ef90000,
8812        operand_signatures: [
8813            feature_reg_signature(RegType::Gp32, VecElementType::None, false),
8814            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8815            0,
8816            0,
8817            0,
8818            0,
8819        ],
8820        required: 0x0000000000004002,
8821        context: "fcvtzu Wd, Hn requires: ASIMD, FP16",
8822    },
8823    InstFeatureForm {
8824        opcode_mask: 0xfffffc00,
8825        opcode_value: 0x9ef90000,
8826        operand_signatures: [
8827            feature_reg_signature(RegType::Gp64, VecElementType::None, false),
8828            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8829            0,
8830            0,
8831            0,
8832            0,
8833        ],
8834        required: 0x0000000000004002,
8835        context: "fcvtzu Xd, Hn requires: ASIMD, FP16",
8836    },
8837    InstFeatureForm {
8838        opcode_mask: 0xfffffc00,
8839        opcode_value: 0x7ef9b800,
8840        operand_signatures: [
8841            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8842            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8843            0,
8844            0,
8845            0,
8846            0,
8847        ],
8848        required: 0x0000000000004002,
8849        context: "fcvtzu Hd, Hn requires: ASIMD, FP16",
8850    },
8851    InstFeatureForm {
8852        opcode_mask: 0xfffffc00,
8853        opcode_value: 0x2ef9b800,
8854        operand_signatures: [
8855            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8856            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8857            0,
8858            0,
8859            0,
8860            0,
8861        ],
8862        required: 0x0000000000004002,
8863        context: "fcvtzu Vd.4H, Vn.4H requires: ASIMD, FP16",
8864    },
8865    InstFeatureForm {
8866        opcode_mask: 0xfffffc00,
8867        opcode_value: 0x6ef9b800,
8868        operand_signatures: [
8869            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8870            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8871            0,
8872            0,
8873            0,
8874            0,
8875        ],
8876        required: 0x0000000000004002,
8877        context: "fcvtzu Vd.8H, Vn.8H requires: ASIMD, FP16",
8878    },
8879    InstFeatureForm {
8880        opcode_mask: 0xffff0000,
8881        opcode_value: 0x1ed90000,
8882        operand_signatures: [
8883            feature_reg_signature(RegType::Gp32, VecElementType::None, false),
8884            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8885            OperandType::Imm as u32,
8886            0,
8887            0,
8888            0,
8889        ],
8890        required: 0x0000000000004002,
8891        context: "fcvtzu Wd, Hn, #fbits requires: ASIMD, FP16",
8892    },
8893    InstFeatureForm {
8894        opcode_mask: 0xffff0000,
8895        opcode_value: 0x9ed90000,
8896        operand_signatures: [
8897            feature_reg_signature(RegType::Gp64, VecElementType::None, false),
8898            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8899            OperandType::Imm as u32,
8900            0,
8901            0,
8902            0,
8903        ],
8904        required: 0x0000000000004002,
8905        context: "fcvtzu Xd, Hn, #fbits requires: ASIMD, FP16",
8906    },
8907    InstFeatureForm {
8908        opcode_mask: 0xff80fc00,
8909        opcode_value: 0x7f00fc00,
8910        operand_signatures: [
8911            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8912            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8913            OperandType::Imm as u32,
8914            0,
8915            0,
8916            0,
8917        ],
8918        required: 0x0000000000004002,
8919        context: "fcvtzu Hd, Hn, #fbits requires: ASIMD, FP16",
8920    },
8921    InstFeatureForm {
8922        opcode_mask: 0xff80fc00,
8923        opcode_value: 0x2f00fc00,
8924        operand_signatures: [
8925            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8926            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8927            OperandType::Imm as u32,
8928            0,
8929            0,
8930            0,
8931        ],
8932        required: 0x0000000000004002,
8933        context: "fcvtzu Vd.4H, Vn.4H, #fbits requires: ASIMD, FP16",
8934    },
8935    InstFeatureForm {
8936        opcode_mask: 0xff80fc00,
8937        opcode_value: 0x6f00fc00,
8938        operand_signatures: [
8939            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8940            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8941            OperandType::Imm as u32,
8942            0,
8943            0,
8944            0,
8945        ],
8946        required: 0x0000000000004002,
8947        context: "fcvtzu Vd.8H, Vn.8H, #fbits requires: ASIMD, FP16",
8948    },
8949    InstFeatureForm {
8950        opcode_mask: 0xffe0fc00,
8951        opcode_value: 0x1ee01800,
8952        operand_signatures: [
8953            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8954            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8955            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8956            0,
8957            0,
8958            0,
8959        ],
8960        required: 0x0000000000004002,
8961        context: "fdiv Hd, Hn, Hm requires: ASIMD, FP16",
8962    },
8963    InstFeatureForm {
8964        opcode_mask: 0xffe0fc00,
8965        opcode_value: 0x2e403c00,
8966        operand_signatures: [
8967            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8968            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8969            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8970            0,
8971            0,
8972            0,
8973        ],
8974        required: 0x0000000000004002,
8975        context: "fdiv Vd.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
8976    },
8977    InstFeatureForm {
8978        opcode_mask: 0xffe0fc00,
8979        opcode_value: 0x6e403c00,
8980        operand_signatures: [
8981            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8982            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8983            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8984            0,
8985            0,
8986            0,
8987        ],
8988        required: 0x0000000000004002,
8989        context: "fdiv Vd.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
8990    },
8991    InstFeatureForm {
8992        opcode_mask: 0xffe08000,
8993        opcode_value: 0x1fc00000,
8994        operand_signatures: [
8995            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8996            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8997            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8998            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8999            0,
9000            0,
9001        ],
9002        required: 0x0000000000004002,
9003        context: "fmadd Hd, Hn, Hm, Ha requires: ASIMD, FP16",
9004    },
9005    InstFeatureForm {
9006        opcode_mask: 0xffe0fc00,
9007        opcode_value: 0x1ee04800,
9008        operand_signatures: [
9009            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9010            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9011            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9012            0,
9013            0,
9014            0,
9015        ],
9016        required: 0x0000000000004002,
9017        context: "fmax Hd, Hn, Hm requires: ASIMD, FP16",
9018    },
9019    InstFeatureForm {
9020        opcode_mask: 0xffe0fc00,
9021        opcode_value: 0x0e403400,
9022        operand_signatures: [
9023            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9024            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9025            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9026            0,
9027            0,
9028            0,
9029        ],
9030        required: 0x0000000000004002,
9031        context: "fmax Vd.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
9032    },
9033    InstFeatureForm {
9034        opcode_mask: 0xffe0fc00,
9035        opcode_value: 0x4e403400,
9036        operand_signatures: [
9037            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9038            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9039            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9040            0,
9041            0,
9042            0,
9043        ],
9044        required: 0x0000000000004002,
9045        context: "fmax Vd.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
9046    },
9047    InstFeatureForm {
9048        opcode_mask: 0xffe0fc00,
9049        opcode_value: 0x1ee06800,
9050        operand_signatures: [
9051            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9052            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9053            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9054            0,
9055            0,
9056            0,
9057        ],
9058        required: 0x0000000000004002,
9059        context: "fmaxnm Hd, Hn, Hm requires: ASIMD, FP16",
9060    },
9061    InstFeatureForm {
9062        opcode_mask: 0xffe0fc00,
9063        opcode_value: 0x0e400400,
9064        operand_signatures: [
9065            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9066            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9067            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9068            0,
9069            0,
9070            0,
9071        ],
9072        required: 0x0000000000004002,
9073        context: "fmaxnm Vd.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
9074    },
9075    InstFeatureForm {
9076        opcode_mask: 0xffe0fc00,
9077        opcode_value: 0x4e400400,
9078        operand_signatures: [
9079            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9080            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9081            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9082            0,
9083            0,
9084            0,
9085        ],
9086        required: 0x0000000000004002,
9087        context: "fmaxnm Vd.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
9088    },
9089    InstFeatureForm {
9090        opcode_mask: 0xfffffc00,
9091        opcode_value: 0x5e30c800,
9092        operand_signatures: [
9093            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9094            feature_reg_signature(RegType::Vec32, VecElementType::H, false),
9095            0,
9096            0,
9097            0,
9098            0,
9099        ],
9100        required: 0x0000000000004002,
9101        context: "fmaxnmp Hd, Vn.2H requires: ASIMD, FP16",
9102    },
9103    InstFeatureForm {
9104        opcode_mask: 0xffe0fc00,
9105        opcode_value: 0x2e400400,
9106        operand_signatures: [
9107            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9108            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9109            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9110            0,
9111            0,
9112            0,
9113        ],
9114        required: 0x0000000000004002,
9115        context: "fmaxnmp Vd.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
9116    },
9117    InstFeatureForm {
9118        opcode_mask: 0xffe0fc00,
9119        opcode_value: 0x6e400400,
9120        operand_signatures: [
9121            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9122            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9123            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9124            0,
9125            0,
9126            0,
9127        ],
9128        required: 0x0000000000004002,
9129        context: "fmaxnmp Vd.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
9130    },
9131    InstFeatureForm {
9132        opcode_mask: 0xfffffc00,
9133        opcode_value: 0x0e30c800,
9134        operand_signatures: [
9135            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9136            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9137            0,
9138            0,
9139            0,
9140            0,
9141        ],
9142        required: 0x0000000000004002,
9143        context: "fmaxnmv Hd, Vn.4H requires: ASIMD, FP16",
9144    },
9145    InstFeatureForm {
9146        opcode_mask: 0xfffffc00,
9147        opcode_value: 0x4e30c800,
9148        operand_signatures: [
9149            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9150            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9151            0,
9152            0,
9153            0,
9154            0,
9155        ],
9156        required: 0x0000000000004002,
9157        context: "fmaxnmv Hd, Vn.8H requires: ASIMD, FP16",
9158    },
9159    InstFeatureForm {
9160        opcode_mask: 0xfffffc00,
9161        opcode_value: 0x5e30f800,
9162        operand_signatures: [
9163            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9164            feature_reg_signature(RegType::Vec32, VecElementType::H, false),
9165            0,
9166            0,
9167            0,
9168            0,
9169        ],
9170        required: 0x0000000000004002,
9171        context: "fmaxp Hd, Vn.2H requires: ASIMD, FP16",
9172    },
9173    InstFeatureForm {
9174        opcode_mask: 0xffe0fc00,
9175        opcode_value: 0x2e403400,
9176        operand_signatures: [
9177            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9178            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9179            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9180            0,
9181            0,
9182            0,
9183        ],
9184        required: 0x0000000000004002,
9185        context: "fmaxp Vd.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
9186    },
9187    InstFeatureForm {
9188        opcode_mask: 0xffe0fc00,
9189        opcode_value: 0x6e403400,
9190        operand_signatures: [
9191            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9192            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9193            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9194            0,
9195            0,
9196            0,
9197        ],
9198        required: 0x0000000000004002,
9199        context: "fmaxp Vd.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
9200    },
9201    InstFeatureForm {
9202        opcode_mask: 0xfffffc00,
9203        opcode_value: 0x0e30f800,
9204        operand_signatures: [
9205            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9206            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9207            0,
9208            0,
9209            0,
9210            0,
9211        ],
9212        required: 0x0000000000004002,
9213        context: "fmaxv Hd, Vn.4H requires: ASIMD, FP16",
9214    },
9215    InstFeatureForm {
9216        opcode_mask: 0xfffffc00,
9217        opcode_value: 0x4e30f800,
9218        operand_signatures: [
9219            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9220            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9221            0,
9222            0,
9223            0,
9224            0,
9225        ],
9226        required: 0x0000000000004002,
9227        context: "fmaxv Hd, Vn.8H requires: ASIMD, FP16",
9228    },
9229    InstFeatureForm {
9230        opcode_mask: 0xffe0fc00,
9231        opcode_value: 0x1ee05800,
9232        operand_signatures: [
9233            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9234            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9235            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9236            0,
9237            0,
9238            0,
9239        ],
9240        required: 0x0000000000004002,
9241        context: "fmin Hd, Hn, Hm requires: ASIMD, FP16",
9242    },
9243    InstFeatureForm {
9244        opcode_mask: 0xffe0fc00,
9245        opcode_value: 0x0ec03400,
9246        operand_signatures: [
9247            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9248            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9249            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9250            0,
9251            0,
9252            0,
9253        ],
9254        required: 0x0000000000004002,
9255        context: "fmin Vd.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
9256    },
9257    InstFeatureForm {
9258        opcode_mask: 0xffe0fc00,
9259        opcode_value: 0x4ec03400,
9260        operand_signatures: [
9261            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9262            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9263            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9264            0,
9265            0,
9266            0,
9267        ],
9268        required: 0x0000000000004002,
9269        context: "fmin Vd.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
9270    },
9271    InstFeatureForm {
9272        opcode_mask: 0xffe0fc00,
9273        opcode_value: 0x1ee07800,
9274        operand_signatures: [
9275            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9276            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9277            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9278            0,
9279            0,
9280            0,
9281        ],
9282        required: 0x0000000000004002,
9283        context: "fminnm Hd, Hn, Hm requires: ASIMD, FP16",
9284    },
9285    InstFeatureForm {
9286        opcode_mask: 0xffe0fc00,
9287        opcode_value: 0x0ec00400,
9288        operand_signatures: [
9289            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9290            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9291            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9292            0,
9293            0,
9294            0,
9295        ],
9296        required: 0x0000000000004002,
9297        context: "fminnm Vd.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
9298    },
9299    InstFeatureForm {
9300        opcode_mask: 0xffe0fc00,
9301        opcode_value: 0x4ec00400,
9302        operand_signatures: [
9303            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9304            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9305            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9306            0,
9307            0,
9308            0,
9309        ],
9310        required: 0x0000000000004002,
9311        context: "fminnm Vd.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
9312    },
9313    InstFeatureForm {
9314        opcode_mask: 0xfffffc00,
9315        opcode_value: 0x5eb0c800,
9316        operand_signatures: [
9317            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9318            feature_reg_signature(RegType::Vec32, VecElementType::H, false),
9319            0,
9320            0,
9321            0,
9322            0,
9323        ],
9324        required: 0x0000000000004002,
9325        context: "fminnmp Hd, Vn.2H requires: ASIMD, FP16",
9326    },
9327    InstFeatureForm {
9328        opcode_mask: 0xffe0fc00,
9329        opcode_value: 0x2ec00400,
9330        operand_signatures: [
9331            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9332            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9333            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9334            0,
9335            0,
9336            0,
9337        ],
9338        required: 0x0000000000004002,
9339        context: "fminnmp Vd.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
9340    },
9341    InstFeatureForm {
9342        opcode_mask: 0xffe0fc00,
9343        opcode_value: 0x6ec00400,
9344        operand_signatures: [
9345            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9346            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9347            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9348            0,
9349            0,
9350            0,
9351        ],
9352        required: 0x0000000000004002,
9353        context: "fminnmp Vd.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
9354    },
9355    InstFeatureForm {
9356        opcode_mask: 0xfffffc00,
9357        opcode_value: 0x0eb0c800,
9358        operand_signatures: [
9359            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9360            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9361            0,
9362            0,
9363            0,
9364            0,
9365        ],
9366        required: 0x0000000000004002,
9367        context: "fminnmv Hd, Vn.4H requires: ASIMD, FP16",
9368    },
9369    InstFeatureForm {
9370        opcode_mask: 0xfffffc00,
9371        opcode_value: 0x4eb0c800,
9372        operand_signatures: [
9373            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9374            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9375            0,
9376            0,
9377            0,
9378            0,
9379        ],
9380        required: 0x0000000000004002,
9381        context: "fminnmv Hd, Vn.8H requires: ASIMD, FP16",
9382    },
9383    InstFeatureForm {
9384        opcode_mask: 0xfffffc00,
9385        opcode_value: 0x5eb0f800,
9386        operand_signatures: [
9387            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9388            feature_reg_signature(RegType::Vec32, VecElementType::H, false),
9389            0,
9390            0,
9391            0,
9392            0,
9393        ],
9394        required: 0x0000000000004002,
9395        context: "fminp Hd, Vn.2H requires: ASIMD, FP16",
9396    },
9397    InstFeatureForm {
9398        opcode_mask: 0xffe0fc00,
9399        opcode_value: 0x2ec03400,
9400        operand_signatures: [
9401            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9402            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9403            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9404            0,
9405            0,
9406            0,
9407        ],
9408        required: 0x0000000000004002,
9409        context: "fminp Vd.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
9410    },
9411    InstFeatureForm {
9412        opcode_mask: 0xffe0fc00,
9413        opcode_value: 0x6ec03400,
9414        operand_signatures: [
9415            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9416            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9417            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9418            0,
9419            0,
9420            0,
9421        ],
9422        required: 0x0000000000004002,
9423        context: "fminp Vd.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
9424    },
9425    InstFeatureForm {
9426        opcode_mask: 0xfffffc00,
9427        opcode_value: 0x0eb0f800,
9428        operand_signatures: [
9429            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9430            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9431            0,
9432            0,
9433            0,
9434            0,
9435        ],
9436        required: 0x0000000000004002,
9437        context: "fminv Hd, Vn.4H requires: ASIMD, FP16",
9438    },
9439    InstFeatureForm {
9440        opcode_mask: 0xfffffc00,
9441        opcode_value: 0x4eb0f800,
9442        operand_signatures: [
9443            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9444            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9445            0,
9446            0,
9447            0,
9448            0,
9449        ],
9450        required: 0x0000000000004002,
9451        context: "fminv Hd, Vn.8H requires: ASIMD, FP16",
9452    },
9453    InstFeatureForm {
9454        opcode_mask: 0xffe0fc00,
9455        opcode_value: 0x0e400c00,
9456        operand_signatures: [
9457            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9458            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9459            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9460            0,
9461            0,
9462            0,
9463        ],
9464        required: 0x0000000000004002,
9465        context: "fmla Vx.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
9466    },
9467    InstFeatureForm {
9468        opcode_mask: 0xffe0fc00,
9469        opcode_value: 0x4e400c00,
9470        operand_signatures: [
9471            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9472            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9473            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9474            0,
9475            0,
9476            0,
9477        ],
9478        required: 0x0000000000004002,
9479        context: "fmla Vx.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
9480    },
9481    InstFeatureForm {
9482        opcode_mask: 0xffc0f400,
9483        opcode_value: 0x5f001000,
9484        operand_signatures: [
9485            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9486            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9487            feature_reg_signature(RegType::Vec128, VecElementType::H, true),
9488            0,
9489            0,
9490            0,
9491        ],
9492        required: 0x0000000000004002,
9493        context: "fmla Hx, Hn, Vm.H[#idx] requires: ASIMD, FP16",
9494    },
9495    InstFeatureForm {
9496        opcode_mask: 0xffc0f400,
9497        opcode_value: 0x0f001000,
9498        operand_signatures: [
9499            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9500            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9501            feature_reg_signature(RegType::Vec128, VecElementType::H, true),
9502            0,
9503            0,
9504            0,
9505        ],
9506        required: 0x0000000000004002,
9507        context: "fmla Vx.4H, Vn.4H, Vm.H[#idx] requires: ASIMD, FP16",
9508    },
9509    InstFeatureForm {
9510        opcode_mask: 0xffc0f400,
9511        opcode_value: 0x4f001000,
9512        operand_signatures: [
9513            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9514            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9515            feature_reg_signature(RegType::Vec128, VecElementType::H, true),
9516            0,
9517            0,
9518            0,
9519        ],
9520        required: 0x0000000000004002,
9521        context: "fmla Vx.8H, Vn.8H, Vm.H[#idx] requires: ASIMD, FP16",
9522    },
9523    InstFeatureForm {
9524        opcode_mask: 0xffe0fc00,
9525        opcode_value: 0x0ec00c00,
9526        operand_signatures: [
9527            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9528            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9529            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9530            0,
9531            0,
9532            0,
9533        ],
9534        required: 0x0000000000004002,
9535        context: "fmls Vx.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
9536    },
9537    InstFeatureForm {
9538        opcode_mask: 0xffe0fc00,
9539        opcode_value: 0x4ec00c00,
9540        operand_signatures: [
9541            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9542            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9543            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9544            0,
9545            0,
9546            0,
9547        ],
9548        required: 0x0000000000004002,
9549        context: "fmls Vx.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
9550    },
9551    InstFeatureForm {
9552        opcode_mask: 0xffc0f400,
9553        opcode_value: 0x5f005000,
9554        operand_signatures: [
9555            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9556            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9557            feature_reg_signature(RegType::Vec128, VecElementType::H, true),
9558            0,
9559            0,
9560            0,
9561        ],
9562        required: 0x0000000000004002,
9563        context: "fmls Hx, Hn, Vm.H[#idx] requires: ASIMD, FP16",
9564    },
9565    InstFeatureForm {
9566        opcode_mask: 0xffc0f400,
9567        opcode_value: 0x0f005000,
9568        operand_signatures: [
9569            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9570            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9571            feature_reg_signature(RegType::Vec128, VecElementType::H, true),
9572            0,
9573            0,
9574            0,
9575        ],
9576        required: 0x0000000000004002,
9577        context: "fmls Vx.4H, Vn.4H, Vm.H[#idx] requires: ASIMD, FP16",
9578    },
9579    InstFeatureForm {
9580        opcode_mask: 0xffc0f400,
9581        opcode_value: 0x4f005000,
9582        operand_signatures: [
9583            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9584            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9585            feature_reg_signature(RegType::Vec128, VecElementType::H, true),
9586            0,
9587            0,
9588            0,
9589        ],
9590        required: 0x0000000000004002,
9591        context: "fmls Vx.8H, Vn.8H, Vm.H[#idx] requires: ASIMD, FP16",
9592    },
9593    InstFeatureForm {
9594        opcode_mask: 0xfffffc00,
9595        opcode_value: 0x1ee60000,
9596        operand_signatures: [
9597            feature_reg_signature(RegType::Gp32, VecElementType::None, false),
9598            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9599            0,
9600            0,
9601            0,
9602            0,
9603        ],
9604        required: 0x0000000000004002,
9605        context: "fmov Wd, Hn requires: ASIMD, FP16",
9606    },
9607    InstFeatureForm {
9608        opcode_mask: 0xfffffc00,
9609        opcode_value: 0x9ee60000,
9610        operand_signatures: [
9611            feature_reg_signature(RegType::Gp64, VecElementType::None, false),
9612            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9613            0,
9614            0,
9615            0,
9616            0,
9617        ],
9618        required: 0x0000000000004002,
9619        context: "fmov Xd, Hn requires: ASIMD, FP16",
9620    },
9621    InstFeatureForm {
9622        opcode_mask: 0xfffffc00,
9623        opcode_value: 0x1ee70000,
9624        operand_signatures: [
9625            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9626            feature_reg_signature(RegType::Gp32, VecElementType::None, false),
9627            0,
9628            0,
9629            0,
9630            0,
9631        ],
9632        required: 0x0000000000004002,
9633        context: "fmov Hd, Wn requires: ASIMD, FP16",
9634    },
9635    InstFeatureForm {
9636        opcode_mask: 0xfffffc00,
9637        opcode_value: 0x9ee70000,
9638        operand_signatures: [
9639            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9640            feature_reg_signature(RegType::Gp64, VecElementType::None, false),
9641            0,
9642            0,
9643            0,
9644            0,
9645        ],
9646        required: 0x0000000000004002,
9647        context: "fmov Hd, Xn requires: ASIMD, FP16",
9648    },
9649    InstFeatureForm {
9650        opcode_mask: 0xfffffc00,
9651        opcode_value: 0x1ee04000,
9652        operand_signatures: [
9653            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9654            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9655            0,
9656            0,
9657            0,
9658            0,
9659        ],
9660        required: 0x0000000000004002,
9661        context: "fmov Hd, Hn requires: ASIMD, FP16",
9662    },
9663    InstFeatureForm {
9664        opcode_mask: 0xffe01fe0,
9665        opcode_value: 0x1ee01000,
9666        operand_signatures: [
9667            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9668            OperandType::Imm as u32,
9669            0,
9670            0,
9671            0,
9672            0,
9673        ],
9674        required: 0x0000000000004002,
9675        context: "fmov Hd, #fimm requires: ASIMD, FP16",
9676    },
9677    InstFeatureForm {
9678        opcode_mask: 0xfff8fc00,
9679        opcode_value: 0x0f00fc00,
9680        operand_signatures: [
9681            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9682            OperandType::Imm as u32,
9683            0,
9684            0,
9685            0,
9686            0,
9687        ],
9688        required: 0x0000000000004002,
9689        context: "fmov Vd.4H, #fimm requires: ASIMD, FP16",
9690    },
9691    InstFeatureForm {
9692        opcode_mask: 0xfff8fc00,
9693        opcode_value: 0x4f00fc00,
9694        operand_signatures: [
9695            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9696            OperandType::Imm as u32,
9697            0,
9698            0,
9699            0,
9700            0,
9701        ],
9702        required: 0x0000000000004002,
9703        context: "fmov Vd.8H, #fimm requires: ASIMD, FP16",
9704    },
9705    InstFeatureForm {
9706        opcode_mask: 0xffe08000,
9707        opcode_value: 0x1fc08000,
9708        operand_signatures: [
9709            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9710            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9711            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9712            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9713            0,
9714            0,
9715        ],
9716        required: 0x0000000000004002,
9717        context: "fmsub Hd, Hn, Hm, Ha requires: ASIMD, FP16",
9718    },
9719    InstFeatureForm {
9720        opcode_mask: 0xffe0fc00,
9721        opcode_value: 0x1ee00800,
9722        operand_signatures: [
9723            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9724            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9725            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9726            0,
9727            0,
9728            0,
9729        ],
9730        required: 0x0000000000004002,
9731        context: "fmul Hd, Hn, Hm requires: ASIMD, FP16",
9732    },
9733    InstFeatureForm {
9734        opcode_mask: 0xffe0fc00,
9735        opcode_value: 0x2e401c00,
9736        operand_signatures: [
9737            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9738            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9739            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9740            0,
9741            0,
9742            0,
9743        ],
9744        required: 0x0000000000004002,
9745        context: "fmul Vd.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
9746    },
9747    InstFeatureForm {
9748        opcode_mask: 0xffe0fc00,
9749        opcode_value: 0x6e401c00,
9750        operand_signatures: [
9751            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9752            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9753            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9754            0,
9755            0,
9756            0,
9757        ],
9758        required: 0x0000000000004002,
9759        context: "fmul Vd.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
9760    },
9761    InstFeatureForm {
9762        opcode_mask: 0xffc0f400,
9763        opcode_value: 0x5f009000,
9764        operand_signatures: [
9765            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9766            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9767            feature_reg_signature(RegType::Vec128, VecElementType::H, true),
9768            0,
9769            0,
9770            0,
9771        ],
9772        required: 0x0000000000004002,
9773        context: "fmul Hd, Hn, Vm.H[#idx] requires: ASIMD, FP16",
9774    },
9775    InstFeatureForm {
9776        opcode_mask: 0xffc0f400,
9777        opcode_value: 0x0f009000,
9778        operand_signatures: [
9779            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9780            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9781            feature_reg_signature(RegType::Vec128, VecElementType::H, true),
9782            0,
9783            0,
9784            0,
9785        ],
9786        required: 0x0000000000004002,
9787        context: "fmul Vd.4H, Vn.4H, Vm.H[#idx] requires: ASIMD, FP16",
9788    },
9789    InstFeatureForm {
9790        opcode_mask: 0xffc0f400,
9791        opcode_value: 0x4f009000,
9792        operand_signatures: [
9793            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9794            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9795            feature_reg_signature(RegType::Vec128, VecElementType::H, true),
9796            0,
9797            0,
9798            0,
9799        ],
9800        required: 0x0000000000004002,
9801        context: "fmul Vd.8H, Vn.8H, Vm.H[#idx] requires: ASIMD, FP16",
9802    },
9803    InstFeatureForm {
9804        opcode_mask: 0xffe0fc00,
9805        opcode_value: 0x5e401c00,
9806        operand_signatures: [
9807            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9808            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9809            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9810            0,
9811            0,
9812            0,
9813        ],
9814        required: 0x0000000000004002,
9815        context: "fmulx Hd, Hn, Hm requires: ASIMD, FP16",
9816    },
9817    InstFeatureForm {
9818        opcode_mask: 0xffe0fc00,
9819        opcode_value: 0x0e401c00,
9820        operand_signatures: [
9821            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9822            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9823            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9824            0,
9825            0,
9826            0,
9827        ],
9828        required: 0x0000000000004002,
9829        context: "fmulx Vd.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
9830    },
9831    InstFeatureForm {
9832        opcode_mask: 0xffe0fc00,
9833        opcode_value: 0x4e401c00,
9834        operand_signatures: [
9835            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9836            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9837            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9838            0,
9839            0,
9840            0,
9841        ],
9842        required: 0x0000000000004002,
9843        context: "fmulx Vd.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
9844    },
9845    InstFeatureForm {
9846        opcode_mask: 0xffc0f400,
9847        opcode_value: 0x7f009000,
9848        operand_signatures: [
9849            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9850            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9851            feature_reg_signature(RegType::Vec128, VecElementType::H, true),
9852            0,
9853            0,
9854            0,
9855        ],
9856        required: 0x0000000000004002,
9857        context: "fmulx Hd, Hn, Vm.H[#idx] requires: ASIMD, FP16",
9858    },
9859    InstFeatureForm {
9860        opcode_mask: 0xffc0f400,
9861        opcode_value: 0x2f009000,
9862        operand_signatures: [
9863            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9864            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9865            feature_reg_signature(RegType::Vec128, VecElementType::H, true),
9866            0,
9867            0,
9868            0,
9869        ],
9870        required: 0x0000000000004002,
9871        context: "fmulx Vd.4H, Vn.4H, Vm.H[#idx] requires: ASIMD, FP16",
9872    },
9873    InstFeatureForm {
9874        opcode_mask: 0xffc0f400,
9875        opcode_value: 0x6f009000,
9876        operand_signatures: [
9877            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9878            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9879            feature_reg_signature(RegType::Vec128, VecElementType::H, true),
9880            0,
9881            0,
9882            0,
9883        ],
9884        required: 0x0000000000004002,
9885        context: "fmulx Vd.8H, Vn.8H, Vm.H[#idx] requires: ASIMD, FP16",
9886    },
9887    InstFeatureForm {
9888        opcode_mask: 0xfffffc00,
9889        opcode_value: 0x1ee14000,
9890        operand_signatures: [
9891            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9892            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9893            0,
9894            0,
9895            0,
9896            0,
9897        ],
9898        required: 0x0000000000004002,
9899        context: "fneg Hd, Hn requires: ASIMD, FP16",
9900    },
9901    InstFeatureForm {
9902        opcode_mask: 0xfffffc00,
9903        opcode_value: 0x2ef8f800,
9904        operand_signatures: [
9905            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9906            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9907            0,
9908            0,
9909            0,
9910            0,
9911        ],
9912        required: 0x0000000000004002,
9913        context: "fneg Vd.4H, Vn.4H requires: ASIMD, FP16",
9914    },
9915    InstFeatureForm {
9916        opcode_mask: 0xfffffc00,
9917        opcode_value: 0x6ef8f800,
9918        operand_signatures: [
9919            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9920            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9921            0,
9922            0,
9923            0,
9924            0,
9925        ],
9926        required: 0x0000000000004002,
9927        context: "fneg Vd.8H, Vn.8H requires: ASIMD, FP16",
9928    },
9929    InstFeatureForm {
9930        opcode_mask: 0xffe08000,
9931        opcode_value: 0x1fe00000,
9932        operand_signatures: [
9933            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9934            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9935            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9936            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9937            0,
9938            0,
9939        ],
9940        required: 0x0000000000004002,
9941        context: "fnmadd Hd, Hn, Hm, Ha requires: ASIMD, FP16",
9942    },
9943    InstFeatureForm {
9944        opcode_mask: 0xffe08000,
9945        opcode_value: 0x1fe08000,
9946        operand_signatures: [
9947            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9948            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9949            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9950            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9951            0,
9952            0,
9953        ],
9954        required: 0x0000000000004002,
9955        context: "fnmsub Hd, Hn, Hm, Ha requires: ASIMD, FP16",
9956    },
9957    InstFeatureForm {
9958        opcode_mask: 0xffe0fc00,
9959        opcode_value: 0x1ee08800,
9960        operand_signatures: [
9961            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9962            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9963            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9964            0,
9965            0,
9966            0,
9967        ],
9968        required: 0x0000000000004002,
9969        context: "fnmul Hd, Hn, Hm requires: ASIMD, FP16",
9970    },
9971    InstFeatureForm {
9972        opcode_mask: 0xfffffc00,
9973        opcode_value: 0x5ef9d800,
9974        operand_signatures: [
9975            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9976            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9977            0,
9978            0,
9979            0,
9980            0,
9981        ],
9982        required: 0x0000000000004002,
9983        context: "frecpe Hd, Hn requires: ASIMD, FP16",
9984    },
9985    InstFeatureForm {
9986        opcode_mask: 0xfffffc00,
9987        opcode_value: 0x0ef9d800,
9988        operand_signatures: [
9989            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9990            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9991            0,
9992            0,
9993            0,
9994            0,
9995        ],
9996        required: 0x0000000000004002,
9997        context: "frecpe Vd.4H, Vn.4H requires: ASIMD, FP16",
9998    },
9999    InstFeatureForm {
10000        opcode_mask: 0xfffffc00,
10001        opcode_value: 0x4ef9d800,
10002        operand_signatures: [
10003            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10004            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10005            0,
10006            0,
10007            0,
10008            0,
10009        ],
10010        required: 0x0000000000004002,
10011        context: "frecpe Vd.8H, Vn.8H requires: ASIMD, FP16",
10012    },
10013    InstFeatureForm {
10014        opcode_mask: 0xffe0fc00,
10015        opcode_value: 0x5e403c00,
10016        operand_signatures: [
10017            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10018            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10019            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10020            0,
10021            0,
10022            0,
10023        ],
10024        required: 0x0000000000004002,
10025        context: "frecps Hd, Hn, Hm requires: ASIMD, FP16",
10026    },
10027    InstFeatureForm {
10028        opcode_mask: 0xffe0fc00,
10029        opcode_value: 0x0e403c00,
10030        operand_signatures: [
10031            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10032            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10033            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10034            0,
10035            0,
10036            0,
10037        ],
10038        required: 0x0000000000004002,
10039        context: "frecps Vd.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
10040    },
10041    InstFeatureForm {
10042        opcode_mask: 0xffe0fc00,
10043        opcode_value: 0x4e403c00,
10044        operand_signatures: [
10045            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10046            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10047            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10048            0,
10049            0,
10050            0,
10051        ],
10052        required: 0x0000000000004002,
10053        context: "frecps Vd.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
10054    },
10055    InstFeatureForm {
10056        opcode_mask: 0xfffffc00,
10057        opcode_value: 0x5ef9f800,
10058        operand_signatures: [
10059            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10060            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10061            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10062            0,
10063            0,
10064            0,
10065        ],
10066        required: 0x0000000000004002,
10067        context: "frecpx Hd, Hn, Hm requires: ASIMD, FP16",
10068    },
10069    InstFeatureForm {
10070        opcode_mask: 0xfffffc00,
10071        opcode_value: 0x1ee64000,
10072        operand_signatures: [
10073            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10074            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10075            0,
10076            0,
10077            0,
10078            0,
10079        ],
10080        required: 0x0000000000004002,
10081        context: "frinta Hd, Hn requires: ASIMD, FP16",
10082    },
10083    InstFeatureForm {
10084        opcode_mask: 0xfffffc00,
10085        opcode_value: 0x2e798800,
10086        operand_signatures: [
10087            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10088            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10089            0,
10090            0,
10091            0,
10092            0,
10093        ],
10094        required: 0x0000000000004002,
10095        context: "frinta Vd.4H, Vn.4H requires: ASIMD, FP16",
10096    },
10097    InstFeatureForm {
10098        opcode_mask: 0xfffffc00,
10099        opcode_value: 0x6e798800,
10100        operand_signatures: [
10101            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10102            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10103            0,
10104            0,
10105            0,
10106            0,
10107        ],
10108        required: 0x0000000000004002,
10109        context: "frinta Vd.8H, Vn.8H requires: ASIMD, FP16",
10110    },
10111    InstFeatureForm {
10112        opcode_mask: 0xfffffc00,
10113        opcode_value: 0x1ee7c000,
10114        operand_signatures: [
10115            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10116            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10117            0,
10118            0,
10119            0,
10120            0,
10121        ],
10122        required: 0x0000000000004002,
10123        context: "frinti Hd, Hn requires: ASIMD, FP16",
10124    },
10125    InstFeatureForm {
10126        opcode_mask: 0xfffffc00,
10127        opcode_value: 0x2ef99800,
10128        operand_signatures: [
10129            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10130            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10131            0,
10132            0,
10133            0,
10134            0,
10135        ],
10136        required: 0x0000000000004002,
10137        context: "frinti Vd.4H, Vn.4H requires: ASIMD, FP16",
10138    },
10139    InstFeatureForm {
10140        opcode_mask: 0xfffffc00,
10141        opcode_value: 0x6ef99800,
10142        operand_signatures: [
10143            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10144            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10145            0,
10146            0,
10147            0,
10148            0,
10149        ],
10150        required: 0x0000000000004002,
10151        context: "frinti Vd.8H, Vn.8H requires: ASIMD, FP16",
10152    },
10153    InstFeatureForm {
10154        opcode_mask: 0xfffffc00,
10155        opcode_value: 0x1ee54000,
10156        operand_signatures: [
10157            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10158            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10159            0,
10160            0,
10161            0,
10162            0,
10163        ],
10164        required: 0x0000000000004002,
10165        context: "frintm Hd, Hn requires: ASIMD, FP16",
10166    },
10167    InstFeatureForm {
10168        opcode_mask: 0xfffffc00,
10169        opcode_value: 0x0e799800,
10170        operand_signatures: [
10171            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10172            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10173            0,
10174            0,
10175            0,
10176            0,
10177        ],
10178        required: 0x0000000000004002,
10179        context: "frintm Vd.4H, Vn.4H requires: ASIMD, FP16",
10180    },
10181    InstFeatureForm {
10182        opcode_mask: 0xfffffc00,
10183        opcode_value: 0x4e799800,
10184        operand_signatures: [
10185            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10186            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10187            0,
10188            0,
10189            0,
10190            0,
10191        ],
10192        required: 0x0000000000004002,
10193        context: "frintm Vd.8H, Vn.8H requires: ASIMD, FP16",
10194    },
10195    InstFeatureForm {
10196        opcode_mask: 0xfffffc00,
10197        opcode_value: 0x1ee44000,
10198        operand_signatures: [
10199            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10200            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10201            0,
10202            0,
10203            0,
10204            0,
10205        ],
10206        required: 0x0000000000004002,
10207        context: "frintn Hd, Hn requires: ASIMD, FP16",
10208    },
10209    InstFeatureForm {
10210        opcode_mask: 0xfffffc00,
10211        opcode_value: 0x0e798800,
10212        operand_signatures: [
10213            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10214            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10215            0,
10216            0,
10217            0,
10218            0,
10219        ],
10220        required: 0x0000000000004002,
10221        context: "frintn Vd.4H, Vn.4H requires: ASIMD, FP16",
10222    },
10223    InstFeatureForm {
10224        opcode_mask: 0xfffffc00,
10225        opcode_value: 0x4e798800,
10226        operand_signatures: [
10227            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10228            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10229            0,
10230            0,
10231            0,
10232            0,
10233        ],
10234        required: 0x0000000000004002,
10235        context: "frintn Vd.8H, Vn.8H requires: ASIMD, FP16",
10236    },
10237    InstFeatureForm {
10238        opcode_mask: 0xfffffc00,
10239        opcode_value: 0x1ee4c000,
10240        operand_signatures: [
10241            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10242            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10243            0,
10244            0,
10245            0,
10246            0,
10247        ],
10248        required: 0x0000000000004002,
10249        context: "frintp Hd, Hn requires: ASIMD, FP16",
10250    },
10251    InstFeatureForm {
10252        opcode_mask: 0xfffffc00,
10253        opcode_value: 0x0ef98800,
10254        operand_signatures: [
10255            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10256            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10257            0,
10258            0,
10259            0,
10260            0,
10261        ],
10262        required: 0x0000000000004002,
10263        context: "frintp Vd.4H, Vn.4H requires: ASIMD, FP16",
10264    },
10265    InstFeatureForm {
10266        opcode_mask: 0xfffffc00,
10267        opcode_value: 0x4ef98800,
10268        operand_signatures: [
10269            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10270            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10271            0,
10272            0,
10273            0,
10274            0,
10275        ],
10276        required: 0x0000000000004002,
10277        context: "frintp Vd.8H, Vn.8H requires: ASIMD, FP16",
10278    },
10279    InstFeatureForm {
10280        opcode_mask: 0xfffffc00,
10281        opcode_value: 0x1ee74000,
10282        operand_signatures: [
10283            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10284            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10285            0,
10286            0,
10287            0,
10288            0,
10289        ],
10290        required: 0x0000000000004002,
10291        context: "frintx Hd, Hn requires: ASIMD, FP16",
10292    },
10293    InstFeatureForm {
10294        opcode_mask: 0xfffffc00,
10295        opcode_value: 0x2e799800,
10296        operand_signatures: [
10297            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10298            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10299            0,
10300            0,
10301            0,
10302            0,
10303        ],
10304        required: 0x0000000000004002,
10305        context: "frintx Vd.4H, Vn.4H requires: ASIMD, FP16",
10306    },
10307    InstFeatureForm {
10308        opcode_mask: 0xfffffc00,
10309        opcode_value: 0x6e799800,
10310        operand_signatures: [
10311            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10312            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10313            0,
10314            0,
10315            0,
10316            0,
10317        ],
10318        required: 0x0000000000004002,
10319        context: "frintx Vd.8H, Vn.8H requires: ASIMD, FP16",
10320    },
10321    InstFeatureForm {
10322        opcode_mask: 0xfffffc00,
10323        opcode_value: 0x1ee5c000,
10324        operand_signatures: [
10325            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10326            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10327            0,
10328            0,
10329            0,
10330            0,
10331        ],
10332        required: 0x0000000000004002,
10333        context: "frintz Hd, Hn requires: ASIMD, FP16",
10334    },
10335    InstFeatureForm {
10336        opcode_mask: 0xfffffc00,
10337        opcode_value: 0x0ef99800,
10338        operand_signatures: [
10339            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10340            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10341            0,
10342            0,
10343            0,
10344            0,
10345        ],
10346        required: 0x0000000000004002,
10347        context: "frintz Vd.4H, Vn.4H requires: ASIMD, FP16",
10348    },
10349    InstFeatureForm {
10350        opcode_mask: 0xfffffc00,
10351        opcode_value: 0x4ef99800,
10352        operand_signatures: [
10353            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10354            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10355            0,
10356            0,
10357            0,
10358            0,
10359        ],
10360        required: 0x0000000000004002,
10361        context: "frintz Vd.8H, Vn.8H requires: ASIMD, FP16",
10362    },
10363    InstFeatureForm {
10364        opcode_mask: 0xfffffc00,
10365        opcode_value: 0x7ef9d800,
10366        operand_signatures: [
10367            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10368            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10369            0,
10370            0,
10371            0,
10372            0,
10373        ],
10374        required: 0x0000000000004002,
10375        context: "frsqrte Hd, Hn requires: ASIMD, FP16",
10376    },
10377    InstFeatureForm {
10378        opcode_mask: 0xfffffc00,
10379        opcode_value: 0x2ef9d800,
10380        operand_signatures: [
10381            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10382            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10383            0,
10384            0,
10385            0,
10386            0,
10387        ],
10388        required: 0x0000000000004002,
10389        context: "frsqrte Vd.4H, Vn.4H requires: ASIMD, FP16",
10390    },
10391    InstFeatureForm {
10392        opcode_mask: 0xfffffc00,
10393        opcode_value: 0x6ef9d800,
10394        operand_signatures: [
10395            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10396            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10397            0,
10398            0,
10399            0,
10400            0,
10401        ],
10402        required: 0x0000000000004002,
10403        context: "frsqrte Vd.8H, Vn.8H requires: ASIMD, FP16",
10404    },
10405    InstFeatureForm {
10406        opcode_mask: 0xffe0fc00,
10407        opcode_value: 0x5ec03c00,
10408        operand_signatures: [
10409            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10410            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10411            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10412            0,
10413            0,
10414            0,
10415        ],
10416        required: 0x0000000000004002,
10417        context: "frsqrts Hd, Hn, Hm requires: ASIMD, FP16",
10418    },
10419    InstFeatureForm {
10420        opcode_mask: 0xffe0fc00,
10421        opcode_value: 0x0ec03c00,
10422        operand_signatures: [
10423            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10424            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10425            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10426            0,
10427            0,
10428            0,
10429        ],
10430        required: 0x0000000000004002,
10431        context: "frsqrts Vd.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
10432    },
10433    InstFeatureForm {
10434        opcode_mask: 0xffe0fc00,
10435        opcode_value: 0x4ec03c00,
10436        operand_signatures: [
10437            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10438            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10439            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10440            0,
10441            0,
10442            0,
10443        ],
10444        required: 0x0000000000004002,
10445        context: "frsqrts Vd.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
10446    },
10447    InstFeatureForm {
10448        opcode_mask: 0xfffffc00,
10449        opcode_value: 0x1ee1c000,
10450        operand_signatures: [
10451            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10452            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10453            0,
10454            0,
10455            0,
10456            0,
10457        ],
10458        required: 0x0000000000004002,
10459        context: "fsqrt Hd, Hn requires: ASIMD, FP16",
10460    },
10461    InstFeatureForm {
10462        opcode_mask: 0xfffffc00,
10463        opcode_value: 0x2ef9f800,
10464        operand_signatures: [
10465            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10466            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10467            0,
10468            0,
10469            0,
10470            0,
10471        ],
10472        required: 0x0000000000004002,
10473        context: "fsqrt Vd.4H, Vn.4H requires: ASIMD, FP16",
10474    },
10475    InstFeatureForm {
10476        opcode_mask: 0xfffffc00,
10477        opcode_value: 0x6ef9f800,
10478        operand_signatures: [
10479            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10480            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10481            0,
10482            0,
10483            0,
10484            0,
10485        ],
10486        required: 0x0000000000004002,
10487        context: "fsqrt Vd.8H, Vn.8H requires: ASIMD, FP16",
10488    },
10489    InstFeatureForm {
10490        opcode_mask: 0xffe0fc00,
10491        opcode_value: 0x1ee03800,
10492        operand_signatures: [
10493            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10494            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10495            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10496            0,
10497            0,
10498            0,
10499        ],
10500        required: 0x0000000000004002,
10501        context: "fsub Hd, Hn, Hm requires: ASIMD, FP16",
10502    },
10503    InstFeatureForm {
10504        opcode_mask: 0xffe0fc00,
10505        opcode_value: 0x0ec01400,
10506        operand_signatures: [
10507            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10508            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10509            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10510            0,
10511            0,
10512            0,
10513        ],
10514        required: 0x0000000000004002,
10515        context: "fsub Vd.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
10516    },
10517    InstFeatureForm {
10518        opcode_mask: 0xffe0fc00,
10519        opcode_value: 0x4ec01400,
10520        operand_signatures: [
10521            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10522            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10523            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10524            0,
10525            0,
10526            0,
10527        ],
10528        required: 0x0000000000004002,
10529        context: "fsub Vd.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
10530    },
10531    InstFeatureForm {
10532        opcode_mask: 0xfffffc00,
10533        opcode_value: 0x1ee20000,
10534        operand_signatures: [
10535            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10536            feature_reg_signature(RegType::Gp32, VecElementType::None, false),
10537            0,
10538            0,
10539            0,
10540            0,
10541        ],
10542        required: 0x0000000000004002,
10543        context: "scvtf Hd, Wn requires: ASIMD, FP16",
10544    },
10545    InstFeatureForm {
10546        opcode_mask: 0xfffffc00,
10547        opcode_value: 0x9ee20000,
10548        operand_signatures: [
10549            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10550            feature_reg_signature(RegType::Gp64, VecElementType::None, false),
10551            0,
10552            0,
10553            0,
10554            0,
10555        ],
10556        required: 0x0000000000004002,
10557        context: "scvtf Hd, Xn requires: ASIMD, FP16",
10558    },
10559    InstFeatureForm {
10560        opcode_mask: 0xfffffc00,
10561        opcode_value: 0x5e79d800,
10562        operand_signatures: [
10563            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10564            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10565            0,
10566            0,
10567            0,
10568            0,
10569        ],
10570        required: 0x0000000000004002,
10571        context: "scvtf Hd, Hn requires: ASIMD, FP16",
10572    },
10573    InstFeatureForm {
10574        opcode_mask: 0xfffffc00,
10575        opcode_value: 0x0e79d800,
10576        operand_signatures: [
10577            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10578            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10579            0,
10580            0,
10581            0,
10582            0,
10583        ],
10584        required: 0x0000000000004002,
10585        context: "scvtf Vd.4H, Vn.4H requires: ASIMD, FP16",
10586    },
10587    InstFeatureForm {
10588        opcode_mask: 0xfffffc00,
10589        opcode_value: 0x4e79d800,
10590        operand_signatures: [
10591            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10592            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10593            0,
10594            0,
10595            0,
10596            0,
10597        ],
10598        required: 0x0000000000004002,
10599        context: "scvtf Vd.8H, Vn.8H requires: ASIMD, FP16",
10600    },
10601    InstFeatureForm {
10602        opcode_mask: 0xffff0000,
10603        opcode_value: 0x1ec20000,
10604        operand_signatures: [
10605            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10606            feature_reg_signature(RegType::Gp32, VecElementType::None, false),
10607            OperandType::Imm as u32,
10608            0,
10609            0,
10610            0,
10611        ],
10612        required: 0x0000000000004002,
10613        context: "scvtf Hd, Wn, #fbits requires: ASIMD, FP16",
10614    },
10615    InstFeatureForm {
10616        opcode_mask: 0xffff0000,
10617        opcode_value: 0x9ec20000,
10618        operand_signatures: [
10619            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10620            feature_reg_signature(RegType::Gp64, VecElementType::None, false),
10621            OperandType::Imm as u32,
10622            0,
10623            0,
10624            0,
10625        ],
10626        required: 0x0000000000004002,
10627        context: "scvtf Hd, Xn, #fbits requires: ASIMD, FP16",
10628    },
10629    InstFeatureForm {
10630        opcode_mask: 0xff80fc00,
10631        opcode_value: 0x5f00e400,
10632        operand_signatures: [
10633            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10634            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10635            OperandType::Imm as u32,
10636            0,
10637            0,
10638            0,
10639        ],
10640        required: 0x0000000000004002,
10641        context: "scvtf Hd, Hn, #bits requires: ASIMD, FP16",
10642    },
10643    InstFeatureForm {
10644        opcode_mask: 0xff80fc00,
10645        opcode_value: 0x0f00e400,
10646        operand_signatures: [
10647            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10648            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10649            OperandType::Imm as u32,
10650            0,
10651            0,
10652            0,
10653        ],
10654        required: 0x0000000000004002,
10655        context: "scvtf Vd.4H, Vn.4H, #fbits requires: ASIMD, FP16",
10656    },
10657    InstFeatureForm {
10658        opcode_mask: 0xff80fc00,
10659        opcode_value: 0x4f00e400,
10660        operand_signatures: [
10661            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10662            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10663            OperandType::Imm as u32,
10664            0,
10665            0,
10666            0,
10667        ],
10668        required: 0x0000000000004002,
10669        context: "scvtf Vd.8H, Vn.8H, #fbits requires: ASIMD, FP16",
10670    },
10671    InstFeatureForm {
10672        opcode_mask: 0xfffffc00,
10673        opcode_value: 0x1ee30000,
10674        operand_signatures: [
10675            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10676            feature_reg_signature(RegType::Gp32, VecElementType::None, false),
10677            0,
10678            0,
10679            0,
10680            0,
10681        ],
10682        required: 0x0000000000004002,
10683        context: "ucvtf Hd, Wn requires: ASIMD, FP16",
10684    },
10685    InstFeatureForm {
10686        opcode_mask: 0xfffffc00,
10687        opcode_value: 0x9ee30000,
10688        operand_signatures: [
10689            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10690            feature_reg_signature(RegType::Gp64, VecElementType::None, false),
10691            0,
10692            0,
10693            0,
10694            0,
10695        ],
10696        required: 0x0000000000004002,
10697        context: "ucvtf Hd, Xn requires: ASIMD, FP16",
10698    },
10699    InstFeatureForm {
10700        opcode_mask: 0xfffffc00,
10701        opcode_value: 0x7e79d800,
10702        operand_signatures: [
10703            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10704            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10705            0,
10706            0,
10707            0,
10708            0,
10709        ],
10710        required: 0x0000000000004002,
10711        context: "ucvtf Hd, Hn requires: ASIMD, FP16",
10712    },
10713    InstFeatureForm {
10714        opcode_mask: 0xfffffc00,
10715        opcode_value: 0x2e79d800,
10716        operand_signatures: [
10717            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10718            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10719            0,
10720            0,
10721            0,
10722            0,
10723        ],
10724        required: 0x0000000000004002,
10725        context: "ucvtf Vd.4H, Vn.4H requires: ASIMD, FP16",
10726    },
10727    InstFeatureForm {
10728        opcode_mask: 0xfffffc00,
10729        opcode_value: 0x6e79d800,
10730        operand_signatures: [
10731            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10732            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10733            0,
10734            0,
10735            0,
10736            0,
10737        ],
10738        required: 0x0000000000004002,
10739        context: "ucvtf Vd.8H, Vn.8H requires: ASIMD, FP16",
10740    },
10741    InstFeatureForm {
10742        opcode_mask: 0xffff0000,
10743        opcode_value: 0x1ec30000,
10744        operand_signatures: [
10745            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10746            feature_reg_signature(RegType::Gp32, VecElementType::None, false),
10747            OperandType::Imm as u32,
10748            0,
10749            0,
10750            0,
10751        ],
10752        required: 0x0000000000004002,
10753        context: "ucvtf Hd, Wn, #fbits requires: ASIMD, FP16",
10754    },
10755    InstFeatureForm {
10756        opcode_mask: 0xffff0000,
10757        opcode_value: 0x9ec30000,
10758        operand_signatures: [
10759            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10760            feature_reg_signature(RegType::Gp64, VecElementType::None, false),
10761            OperandType::Imm as u32,
10762            0,
10763            0,
10764            0,
10765        ],
10766        required: 0x0000000000004002,
10767        context: "ucvtf Hd, Xn, #fbits requires: ASIMD, FP16",
10768    },
10769    InstFeatureForm {
10770        opcode_mask: 0xff80fc00,
10771        opcode_value: 0x7f00e400,
10772        operand_signatures: [
10773            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10774            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10775            OperandType::Imm as u32,
10776            0,
10777            0,
10778            0,
10779        ],
10780        required: 0x0000000000004002,
10781        context: "ucvtf Hd, Hn, #bits requires: ASIMD, FP16",
10782    },
10783    InstFeatureForm {
10784        opcode_mask: 0xff80fc00,
10785        opcode_value: 0x2f00e400,
10786        operand_signatures: [
10787            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10788            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10789            OperandType::Imm as u32,
10790            0,
10791            0,
10792            0,
10793        ],
10794        required: 0x0000000000004002,
10795        context: "ucvtf Vd.4H, Vn.4H, #fbits requires: ASIMD, FP16",
10796    },
10797    InstFeatureForm {
10798        opcode_mask: 0xff80fc00,
10799        opcode_value: 0x6f00e400,
10800        operand_signatures: [
10801            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10802            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10803            OperandType::Imm as u32,
10804            0,
10805            0,
10806            0,
10807        ],
10808        required: 0x0000000000004002,
10809        context: "ucvtf Vd.8H, Vn.8H, #fbits requires: ASIMD, FP16",
10810    },
10811];
10812
10813fn required_features_for_form(
10814    inst_id: usize,
10815    opcode: u32,
10816    ops: &[&Operand],
10817) -> (u64, &'static str) {
10818    let start = INST_FEATURE_FORM_OFFSETS[inst_id] as usize;
10819    let end = INST_FEATURE_FORM_OFFSETS[inst_id + 1] as usize;
10820    for form in &INST_FEATURE_FORMS[start..end] {
10821        if form.matches(opcode, ops) {
10822            return (form.required, form.context);
10823        }
10824    }
10825    (
10826        INST_BASE_FEATURE_MASKS[inst_id],
10827        INST_BASE_FEATURE_CONTEXT[inst_id],
10828    )
10829}
10830
10831/// One instruction carrying each represented feature.
10832pub static CPU_FEATURE_REPRESENTATIVE: [InstId; CPU_FEATURE_COUNT] = [
10833    InstId::Aesd_v,
10834    InstId::Abs_v,
10835    InstId::Bfcvt_v,
10836    InstId::Bti,
10837    InstId::Chkfeat,
10838    InstId::Clrbhb,
10839    InstId::Crc32b,
10840    InstId::Abs,
10841    InstId::Dgh,
10842    InstId::Sdot_v,
10843    InstId::Fcadd_v,
10844    InstId::Fmlal_v,
10845    InstId::Cfinv,
10846    InstId::Axflag,
10847    InstId::Fabd_v,
10848    InstId::Fcvtn_v,
10849    InstId::Frint32x_v,
10850    InstId::Smmla_v,
10851    InstId::Fjcvtzs_v,
10852    InstId::Ldlar,
10853    InstId::Cas,
10854    InstId::Addg,
10855    InstId::Ldgm,
10856    InstId::Autda,
10857    InstId::Esb,
10858    InstId::Sqrdmlah_v,
10859    InstId::Sha1c_v,
10860    InstId::Sha256h_v,
10861    InstId::Bcax_v,
10862    InstId::Sha512h_v,
10863    InstId::Sm3partw1_v,
10864    InstId::Sm4e_v,
10865];
10866// @generated AArch64 target features end