asmkit/riscv/

emitter.rs

//! Typed RISC-V emitter traits generated by `meta/riscv.py`.
//!
//! Invalid operand categories fail at compile time:
//!
//! ```compile_fail
//! use asmkit::riscv::{Assembler, FaddSEmitter, Gp};
//! fn require<T: FaddSEmitter<Gp, Gp, Gp, Gp>>() {}
//! require::<Assembler<'static>>();
//! ```
//!
//! ```compile_fail
//! use asmkit::riscv::{Assembler, VaddVvEmitter, Vp};
//! fn require<T: VaddVvEmitter<Vp, Vp, Vp, Vp>>() {}
//! require::<Assembler<'static>>();
//! ```
//!
//! ```compile_fail
//! use asmkit::Sym;
//! use asmkit::riscv::{Assembler, Gp, JalEmitter};
//! fn require<T: JalEmitter<Gp, Sym>>() {}
//! require::<Assembler<'static>>();
//! ```
//!
//! ```
//! use asmkit::Imm;
//! use asmkit::riscv::{Assembler, FcvtmodWDEmitter, FmvWXEmitter, FmvXWEmitter, Fp, Gp, VfaddVfEmitter, Vp};
//! fn require<T: FcvtmodWDEmitter<Gp, Fp> + FmvWXEmitter<Fp, Gp> + FmvXWEmitter<Gp, Fp> + VfaddVfEmitter<Vp, Vp, Fp, Imm>>() {}
//! require::<Assembler<'static>>();
//! ```
//!
//! ```compile_fail
//! use asmkit::Imm;
//! use asmkit::riscv::{Assembler, Gp, VfaddVfEmitter, Vp};
//! fn require<T: VfaddVfEmitter<Vp, Vp, Gp, Imm>>() {}
//! require::<Assembler<'static>>();
//! ```
//!
//! ```compile_fail
//! use asmkit::Label;
//! use asmkit::riscv::{Assembler, Gp, JalrEmitter, LbEmitter};
//! fn require<T: JalrEmitter<Gp, Gp, Label> + LbEmitter<Gp, Gp, Label>>() {}
//! require::<Assembler<'static>>();
//! ```
use super::{assembler::*, opcodes::*, operands::*};
use crate::core::operand::*;

/* Automatically generated by parse_opcodes (meta/riscv.py). Do not edit by hand.
 * Derived from riscv-opcodes (BSD-3-Clause) and riscv-unified-db
 * (BSD-3-Clause-Clear); see meta/README.md for the input pins. */

/// Integer add
///
/// Add the value in rs1 to rs2, and store the result in rd.
/// Any overflow is thrown away.
///
/// # Forms
/// Assembly: `add xd, xs1, xs2`
/// Rust: `add(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait AddEmitter<T0, T1, T2> {
    fn add(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// Add unsigned word
///
/// This instruction performs an XLEN-wide addition between rs2 and the
/// zero-extended least-significant word of rs1.
///
/// # Forms
/// Assembly: `add.uw xd, xs1, xs2`
/// Rust: `add_uw(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait AddUwEmitter<T0, T1, T2> {
    fn add_uw(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// Add immediate
///
/// Add an immediate to the value in rs1, and store the result in rd
///
/// # Forms
/// Assembly: `addi xd, xs1, imm`
/// Rust: `addi(rd, rs1, imm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `imm` — Immediate encoding value.
pub trait AddiEmitter<T0, T1, T2> {
    fn addi(&mut self, rd: T0, rs1: T1, imm: T2);
}

/// Add immediate word
///
/// Add an immediate to the 32-bit value in rs1, and store the sign extended result in rd
///
/// # Forms
/// Assembly: `addiw xd, xs1, imm`
/// Rust: `addiw(rd, rs1, imm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `imm` — Immediate encoding value.
pub trait AddiwEmitter<T0, T1, T2> {
    fn addiw(&mut self, rd: T0, rs1: T1, imm: T2);
}

/// Add word
///
/// Add the 32-bit values in rs1 to rs2, and store the sign-extended result in rd.
/// Any overflow is thrown away.
///
/// # Forms
/// Assembly: `addw xd, xs1, xs2`
/// Rust: `addw(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait AddwEmitter<T0, T1, T2> {
    fn addw(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `aes32dsi` instruction.
///
/// # Forms
/// Assembly: `aes32dsi xd, xs1, xs2, bs`
/// Rust: `aes32dsi(rd, rs1, rs2, bs)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
/// - `bs` — Immediate encoding value.
pub trait Aes32DsiEmitter<T0, T1, T2, T3> {
    fn aes32dsi(&mut self, rd: T0, rs1: T1, rs2: T2, bs: T3);
}

/// RISC-V `aes32dsmi` instruction.
///
/// # Forms
/// Assembly: `aes32dsmi xd, xs1, xs2, bs`
/// Rust: `aes32dsmi(rd, rs1, rs2, bs)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
/// - `bs` — Immediate encoding value.
pub trait Aes32DsmiEmitter<T0, T1, T2, T3> {
    fn aes32dsmi(&mut self, rd: T0, rs1: T1, rs2: T2, bs: T3);
}

/// RISC-V `aes32esi` instruction.
///
/// # Forms
/// Assembly: `aes32esi xd, xs1, xs2, bs`
/// Rust: `aes32esi(rd, rs1, rs2, bs)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
/// - `bs` — Immediate encoding value.
pub trait Aes32EsiEmitter<T0, T1, T2, T3> {
    fn aes32esi(&mut self, rd: T0, rs1: T1, rs2: T2, bs: T3);
}

/// RISC-V `aes32esmi` instruction.
///
/// # Forms
/// Assembly: `aes32esmi xd, xs1, xs2, bs`
/// Rust: `aes32esmi(rd, rs1, rs2, bs)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
/// - `bs` — Immediate encoding value.
pub trait Aes32EsmiEmitter<T0, T1, T2, T3> {
    fn aes32esmi(&mut self, rd: T0, rs1: T1, rs2: T2, bs: T3);
}

/// RISC-V `aes64ds` instruction.
///
/// # Forms
/// Assembly: `aes64ds xd, xs1, xs2`
/// Rust: `aes64ds(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait Aes64DsEmitter<T0, T1, T2> {
    fn aes64ds(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `aes64dsm` instruction.
///
/// # Forms
/// Assembly: `aes64dsm xd, xs1, xs2`
/// Rust: `aes64dsm(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait Aes64DsmEmitter<T0, T1, T2> {
    fn aes64dsm(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `aes64es` instruction.
///
/// # Forms
/// Assembly: `aes64es xd, xs1, xs2`
/// Rust: `aes64es(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait Aes64EsEmitter<T0, T1, T2> {
    fn aes64es(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `aes64esm` instruction.
///
/// # Forms
/// Assembly: `aes64esm xd, xs1, xs2`
/// Rust: `aes64esm(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait Aes64EsmEmitter<T0, T1, T2> {
    fn aes64esm(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `aes64im` instruction.
///
/// # Forms
/// Assembly: `aes64im xd, xs1`
/// Rust: `aes64im(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait Aes64ImEmitter<T0, T1> {
    fn aes64im(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `aes64ks1i` instruction.
///
/// # Forms
/// Assembly: `aes64ks1i xd, xs1, rnum`
/// Rust: `aes64ks1i(rd, rs1, rnum)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rnum` — Immediate encoding value.
pub trait Aes64Ks1IEmitter<T0, T1, T2> {
    fn aes64ks1i(&mut self, rd: T0, rs1: T1, rnum: T2);
}

/// RISC-V `aes64ks2` instruction.
///
/// # Forms
/// Assembly: `aes64ks2 xd, xs1, xs2`
/// Rust: `aes64ks2(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait Aes64Ks2Emitter<T0, T1, T2> {
    fn aes64ks2(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `amoadd.b` instruction.
///
/// # Forms
/// Assembly: `amoadd.b xd, xs1, xs2, aq, rl`
/// Rust: `amoadd_b(rd, rs1, rs2, aq, rl)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Memory base register.
/// - `rs2` — Source register.
/// - `aq` — Acquire-order bit.
/// - `rl` — Release-order bit; retained for the existing emitter API.
pub trait AmoaddBEmitter<T0, T1, T2, T3, T4> {
    fn amoadd_b(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4);
}

/// Atomic fetch-and-add doubleword
///
/// Atomically:
///
///   * Load the doubleword at address _rs1_
///   * Write the loaded value into _rd_
///   * Add the value of register _rs2_ to the loaded value
///   * Write the sum to the address in _rs1_
///
/// # Forms
/// Assembly: `amoadd.d xd, xs2, (xs1)`
/// Rust: `amoadd_d(rd, rs1, rs2, aq, rl)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Memory base register.
/// - `rs2` — Source register.
/// - `aq` — Acquire-order bit.
/// - `rl` — Release-order bit; retained for the existing emitter API.
pub trait AmoaddDEmitter<T0, T1, T2, T3, T4> {
    fn amoadd_d(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4);
}

/// RISC-V `amoadd.h` instruction.
///
/// # Forms
/// Assembly: `amoadd.h xd, xs1, xs2, aq, rl`
/// Rust: `amoadd_h(rd, rs1, rs2, aq, rl)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Memory base register.
/// - `rs2` — Source register.
/// - `aq` — Acquire-order bit.
/// - `rl` — Release-order bit; retained for the existing emitter API.
pub trait AmoaddHEmitter<T0, T1, T2, T3, T4> {
    fn amoadd_h(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4);
}

/// Atomic fetch-and-add word
///
/// Atomically:
///
///   * Load the word at address _rs1_
///   * Write the sign-extended value into _rd_
///   * Add the least-significant word of register _rs2_ to the loaded value
///   * Write the sum to the address in _rs1_
///
/// # Forms
/// Assembly: `amoadd.w xd, xs2, (xrs1)`
/// Rust: `amoadd_w(rd, rs1, rs2, aq, rl)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Memory base register.
/// - `rs2` — Source register.
/// - `aq` — Acquire-order bit.
/// - `rl` — Release-order bit; retained for the existing emitter API.
pub trait AmoaddWEmitter<T0, T1, T2, T3, T4> {
    fn amoadd_w(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4);
}

/// RISC-V `amoand.b` instruction.
///
/// # Forms
/// Assembly: `amoand.b xd, xs1, xs2, aq, rl`
/// Rust: `amoand_b(rd, rs1, rs2, aq, rl)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Memory base register.
/// - `rs2` — Source register.
/// - `aq` — Acquire-order bit.
/// - `rl` — Release-order bit; retained for the existing emitter API.
pub trait AmoandBEmitter<T0, T1, T2, T3, T4> {
    fn amoand_b(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4);
}

/// Atomic fetch-and-and doubleword
///
/// Atomically:
///
///   * Load the doubleword at address _rs1_
///   * Write the loaded value into _rd_
///   * AND the value of register _rs2_ to the loaded value
///   * Write the result to the address in _rs1_
///
/// # Forms
/// Assembly: `amoand.d xd, xs2, (xrs1)`
/// Rust: `amoand_d(rd, rs1, rs2, aq, rl)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Memory base register.
/// - `rs2` — Source register.
/// - `aq` — Acquire-order bit.
/// - `rl` — Release-order bit; retained for the existing emitter API.
pub trait AmoandDEmitter<T0, T1, T2, T3, T4> {
    fn amoand_d(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4);
}

/// RISC-V `amoand.h` instruction.
///
/// # Forms
/// Assembly: `amoand.h xd, xs1, xs2, aq, rl`
/// Rust: `amoand_h(rd, rs1, rs2, aq, rl)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Memory base register.
/// - `rs2` — Source register.
/// - `aq` — Acquire-order bit.
/// - `rl` — Release-order bit; retained for the existing emitter API.
pub trait AmoandHEmitter<T0, T1, T2, T3, T4> {
    fn amoand_h(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4);
}

/// Atomic fetch-and-and word
///
/// Atomically:
///
///   * Load the word at address _rs1_
///   * Write the sign-extended value into _rd_
///   * AND the least-significant word of register _rs2_ to the loaded value
///   * Write the result to the address in _rs1_
///
/// # Forms
/// Assembly: `amoand.w xd, xs2, (xrs1)`
/// Rust: `amoand_w(rd, rs1, rs2, aq, rl)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Memory base register.
/// - `rs2` — Source register.
/// - `aq` — Acquire-order bit.
/// - `rl` — Release-order bit; retained for the existing emitter API.
pub trait AmoandWEmitter<T0, T1, T2, T3, T4> {
    fn amoand_w(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4);
}

/// RISC-V `amocas.b` instruction.
///
/// # Forms
/// Assembly: `amocas.b xd, xs1, xs2, aq, rl`
/// Rust: `amocas_b(rd, rs1, rs2, aq, rl)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Memory base register.
/// - `rs2` — Source register.
/// - `aq` — Acquire-order bit.
/// - `rl` — Release-order bit; retained for the existing emitter API.
pub trait AmocasBEmitter<T0, T1, T2, T3, T4> {
    fn amocas_b(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4);
}

/// RISC-V `amocas.d` instruction.
///
/// # Forms
/// Assembly: `amocas.d xd, xs1, xs2, aq, rl`
/// Rust: `amocas_d(rd, rs1, rs2, aq, rl)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Memory base register.
/// - `rs2` — Source register.
/// - `aq` — Acquire-order bit.
/// - `rl` — Release-order bit; retained for the existing emitter API.
pub trait AmocasDEmitter<T0, T1, T2, T3, T4> {
    fn amocas_d(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4);
}

/// RISC-V `amocas.h` instruction.
///
/// # Forms
/// Assembly: `amocas.h xd, xs1, xs2, aq, rl`
/// Rust: `amocas_h(rd, rs1, rs2, aq, rl)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Memory base register.
/// - `rs2` — Source register.
/// - `aq` — Acquire-order bit.
/// - `rl` — Release-order bit; retained for the existing emitter API.
pub trait AmocasHEmitter<T0, T1, T2, T3, T4> {
    fn amocas_h(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4);
}

/// RISC-V `amocas.q` instruction.
///
/// # Forms
/// Assembly: `amocas.q xd, xs1, xs2, aq, rl`
/// Rust: `amocas_q(rd, rs1, rs2, aq, rl)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Memory base register.
/// - `rs2` — Source register.
/// - `aq` — Acquire-order bit.
/// - `rl` — Release-order bit; retained for the existing emitter API.
pub trait AmocasQEmitter<T0, T1, T2, T3, T4> {
    fn amocas_q(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4);
}

/// RISC-V `amocas.w` instruction.
///
/// # Forms
/// Assembly: `amocas.w xd, xs1, xs2, aq, rl`
/// Rust: `amocas_w(rd, rs1, rs2, aq, rl)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Memory base register.
/// - `rs2` — Source register.
/// - `aq` — Acquire-order bit.
/// - `rl` — Release-order bit; retained for the existing emitter API.
pub trait AmocasWEmitter<T0, T1, T2, T3, T4> {
    fn amocas_w(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4);
}

/// RISC-V `amomax.b` instruction.
///
/// # Forms
/// Assembly: `amomax.b xd, xs1, xs2, aq, rl`
/// Rust: `amomax_b(rd, rs1, rs2, aq, rl)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Memory base register.
/// - `rs2` — Source register.
/// - `aq` — Acquire-order bit.
/// - `rl` — Release-order bit; retained for the existing emitter API.
pub trait AmomaxBEmitter<T0, T1, T2, T3, T4> {
    fn amomax_b(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4);
}

/// Atomic MAX doubleword
///
/// Atomically:
///
///   * Load the doubleword at address _rs1_
///   * Write the loaded value into _rd_
///   * Signed compare the value of register _rs2_ to the loaded value, and select the maximum value
///   * Write the maximum to the address in _rs1_
///
/// # Forms
/// Assembly: `amomax.d xd, xs2, (xrs1)`
/// Rust: `amomax_d(rd, rs1, rs2, aq, rl)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Memory base register.
/// - `rs2` — Source register.
/// - `aq` — Acquire-order bit.
/// - `rl` — Release-order bit; retained for the existing emitter API.
pub trait AmomaxDEmitter<T0, T1, T2, T3, T4> {
    fn amomax_d(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4);
}

/// RISC-V `amomax.h` instruction.
///
/// # Forms
/// Assembly: `amomax.h xd, xs1, xs2, aq, rl`
/// Rust: `amomax_h(rd, rs1, rs2, aq, rl)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Memory base register.
/// - `rs2` — Source register.
/// - `aq` — Acquire-order bit.
/// - `rl` — Release-order bit; retained for the existing emitter API.
pub trait AmomaxHEmitter<T0, T1, T2, T3, T4> {
    fn amomax_h(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4);
}

/// Atomic MAX word
///
/// Atomically:
///
///   * Load the word at address _rs1_
///   * Write the sign-extended value into _rd_
///   * Signed compare the least-significant word of register _rs2_ to the loaded value, and select the maximum value
///   * Write the maximum to the address in _rs1_
///
/// # Forms
/// Assembly: `amomax.w xd, xs2, (xrs1)`
/// Rust: `amomax_w(rd, rs1, rs2, aq, rl)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Memory base register.
/// - `rs2` — Source register.
/// - `aq` — Acquire-order bit.
/// - `rl` — Release-order bit; retained for the existing emitter API.
pub trait AmomaxWEmitter<T0, T1, T2, T3, T4> {
    fn amomax_w(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4);
}

/// RISC-V `amomaxu.b` instruction.
///
/// # Forms
/// Assembly: `amomaxu.b xd, xs1, xs2, aq, rl`
/// Rust: `amomaxu_b(rd, rs1, rs2, aq, rl)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Memory base register.
/// - `rs2` — Source register.
/// - `aq` — Acquire-order bit.
/// - `rl` — Release-order bit; retained for the existing emitter API.
pub trait AmomaxuBEmitter<T0, T1, T2, T3, T4> {
    fn amomaxu_b(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4);
}

/// Atomic MAX unsigned doubleword
///
/// Atomically:
///
///   * Load the doubleword at address _rs1_
///   * Write the loaded value into _rd_
///   * Unsigned compare the value of register _rs2_ to the loaded value, and select the maximum value
///   * Write the maximum to the address in _rs1_
///
/// # Forms
/// Assembly: `amomaxu.d xd, xs2, (xrs1)`
/// Rust: `amomaxu_d(rd, rs1, rs2, aq, rl)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Memory base register.
/// - `rs2` — Source register.
/// - `aq` — Acquire-order bit.
/// - `rl` — Release-order bit; retained for the existing emitter API.
pub trait AmomaxuDEmitter<T0, T1, T2, T3, T4> {
    fn amomaxu_d(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4);
}

/// RISC-V `amomaxu.h` instruction.
///
/// # Forms
/// Assembly: `amomaxu.h xd, xs1, xs2, aq, rl`
/// Rust: `amomaxu_h(rd, rs1, rs2, aq, rl)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Memory base register.
/// - `rs2` — Source register.
/// - `aq` — Acquire-order bit.
/// - `rl` — Release-order bit; retained for the existing emitter API.
pub trait AmomaxuHEmitter<T0, T1, T2, T3, T4> {
    fn amomaxu_h(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4);
}

/// Atomic MAX unsigned word
///
/// Atomically:
///
///   * Load the word at address _rs1_
///   * Write the sign-extended value into _rd_
///   * Unsigned compare the least-significant word of register _rs2_ to the loaded value, and select the maximum value
///   * Write the maximum to the address in _rs1_
///
/// # Forms
/// Assembly: `amomaxu.w xd, xs2, (xrs1)`
/// Rust: `amomaxu_w(rd, rs1, rs2, aq, rl)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Memory base register.
/// - `rs2` — Source register.
/// - `aq` — Acquire-order bit.
/// - `rl` — Release-order bit; retained for the existing emitter API.
pub trait AmomaxuWEmitter<T0, T1, T2, T3, T4> {
    fn amomaxu_w(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4);
}

/// RISC-V `amomin.b` instruction.
///
/// # Forms
/// Assembly: `amomin.b xd, xs1, xs2, aq, rl`
/// Rust: `amomin_b(rd, rs1, rs2, aq, rl)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Memory base register.
/// - `rs2` — Source register.
/// - `aq` — Acquire-order bit.
/// - `rl` — Release-order bit; retained for the existing emitter API.
pub trait AmominBEmitter<T0, T1, T2, T3, T4> {
    fn amomin_b(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4);
}

/// Atomic MIN doubleword
///
/// Atomically:
///
///   * Load the doubleword at address _rs1_
///   * Write the loaded value into _rd_
///   * Signed compare the value of register _rs2_ to the loaded value, and select the minimum value
///   * Write the minimum to the address in _rs1_
///
/// # Forms
/// Assembly: `amomin.d xd, xs2, (xrs1)`
/// Rust: `amomin_d(rd, rs1, rs2, aq, rl)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Memory base register.
/// - `rs2` — Source register.
/// - `aq` — Acquire-order bit.
/// - `rl` — Release-order bit; retained for the existing emitter API.
pub trait AmominDEmitter<T0, T1, T2, T3, T4> {
    fn amomin_d(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4);
}

/// RISC-V `amomin.h` instruction.
///
/// # Forms
/// Assembly: `amomin.h xd, xs1, xs2, aq, rl`
/// Rust: `amomin_h(rd, rs1, rs2, aq, rl)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Memory base register.
/// - `rs2` — Source register.
/// - `aq` — Acquire-order bit.
/// - `rl` — Release-order bit; retained for the existing emitter API.
pub trait AmominHEmitter<T0, T1, T2, T3, T4> {
    fn amomin_h(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4);
}

/// Atomic MIN word
///
/// Atomically:
///
///   * Load the word at address _rs1_
///   * Write the sign-extended value into _rd_
///   * Signed compare the least-significant word of register _rs2_ to the loaded value, and select the minimum value
///   * Write the result to the address in _rs1_
///
/// # Forms
/// Assembly: `amomin.w xd, xs2, (xrs1)`
/// Rust: `amomin_w(rd, rs1, rs2, aq, rl)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Memory base register.
/// - `rs2` — Source register.
/// - `aq` — Acquire-order bit.
/// - `rl` — Release-order bit; retained for the existing emitter API.
pub trait AmominWEmitter<T0, T1, T2, T3, T4> {
    fn amomin_w(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4);
}

/// RISC-V `amominu.b` instruction.
///
/// # Forms
/// Assembly: `amominu.b xd, xs1, xs2, aq, rl`
/// Rust: `amominu_b(rd, rs1, rs2, aq, rl)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Memory base register.
/// - `rs2` — Source register.
/// - `aq` — Acquire-order bit.
/// - `rl` — Release-order bit; retained for the existing emitter API.
pub trait AmominuBEmitter<T0, T1, T2, T3, T4> {
    fn amominu_b(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4);
}

/// Atomic MIN unsigned doubleword
///
/// Atomically:
///
///   * Load the doubleword at address _rs1_
///   * Write the loaded value into _rd_
///   * Unsigned compare the value of register _rs2_ to the loaded value, and select the minimum value
///   * Write the minimum to the address in _rs1_
///
/// # Forms
/// Assembly: `amominu.d xd, xs2, (xrs1)`
/// Rust: `amominu_d(rd, rs1, rs2, aq, rl)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Memory base register.
/// - `rs2` — Source register.
/// - `aq` — Acquire-order bit.
/// - `rl` — Release-order bit; retained for the existing emitter API.
pub trait AmominuDEmitter<T0, T1, T2, T3, T4> {
    fn amominu_d(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4);
}

/// RISC-V `amominu.h` instruction.
///
/// # Forms
/// Assembly: `amominu.h xd, xs1, xs2, aq, rl`
/// Rust: `amominu_h(rd, rs1, rs2, aq, rl)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Memory base register.
/// - `rs2` — Source register.
/// - `aq` — Acquire-order bit.
/// - `rl` — Release-order bit; retained for the existing emitter API.
pub trait AmominuHEmitter<T0, T1, T2, T3, T4> {
    fn amominu_h(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4);
}

/// Atomic MIN unsigned word
///
/// Atomically:
///
///   * Load the word at address _rs1_
///   * Write the sign-extended value into _rd_
///   * Unsigned compare the least-significant word of register _rs2_ to the loaded word, and select the minimum value
///   * Write the result to the address in _rs1_
///
/// # Forms
/// Assembly: `amominu.w xd, xs2, (xrs1)`
/// Rust: `amominu_w(rd, rs1, rs2, aq, rl)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Memory base register.
/// - `rs2` — Source register.
/// - `aq` — Acquire-order bit.
/// - `rl` — Release-order bit; retained for the existing emitter API.
pub trait AmominuWEmitter<T0, T1, T2, T3, T4> {
    fn amominu_w(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4);
}

/// RISC-V `amoor.b` instruction.
///
/// # Forms
/// Assembly: `amoor.b xd, xs1, xs2, aq, rl`
/// Rust: `amoor_b(rd, rs1, rs2, aq, rl)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Memory base register.
/// - `rs2` — Source register.
/// - `aq` — Acquire-order bit.
/// - `rl` — Release-order bit; retained for the existing emitter API.
pub trait AmoorBEmitter<T0, T1, T2, T3, T4> {
    fn amoor_b(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4);
}

/// Atomic fetch-and-or doubleword
///
/// Atomically:
///
///   * Load the doubleword at address _rs1_
///   * Write the loaded value into _rd_
///   * OR the value of register _rs2_ to the loaded value
///   * Write the result to the address in _rs1_
///
/// # Forms
/// Assembly: `amoor.d xd, xs2, (xrs1)`
/// Rust: `amoor_d(rd, rs1, rs2, aq, rl)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Memory base register.
/// - `rs2` — Source register.
/// - `aq` — Acquire-order bit.
/// - `rl` — Release-order bit; retained for the existing emitter API.
pub trait AmoorDEmitter<T0, T1, T2, T3, T4> {
    fn amoor_d(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4);
}

/// RISC-V `amoor.h` instruction.
///
/// # Forms
/// Assembly: `amoor.h xd, xs1, xs2, aq, rl`
/// Rust: `amoor_h(rd, rs1, rs2, aq, rl)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Memory base register.
/// - `rs2` — Source register.
/// - `aq` — Acquire-order bit.
/// - `rl` — Release-order bit; retained for the existing emitter API.
pub trait AmoorHEmitter<T0, T1, T2, T3, T4> {
    fn amoor_h(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4);
}

/// Atomic fetch-and-or word
///
/// Atomically:
///
///   * Load the word at address _rs1_
///   * Write the sign-extended value into _rd_
///   * OR the least-significant word of register _rs2_ to the loaded value
///   * Write the result to the address in _rs1_
///
/// # Forms
/// Assembly: `amoor.w xd, xs2, (xrs1)`
/// Rust: `amoor_w(rd, rs1, rs2, aq, rl)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Memory base register.
/// - `rs2` — Source register.
/// - `aq` — Acquire-order bit.
/// - `rl` — Release-order bit; retained for the existing emitter API.
pub trait AmoorWEmitter<T0, T1, T2, T3, T4> {
    fn amoor_w(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4);
}

/// RISC-V `amoswap.b` instruction.
///
/// # Forms
/// Assembly: `amoswap.b xd, xs1, xs2, aq, rl`
/// Rust: `amoswap_b(rd, rs1, rs2, aq, rl)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Memory base register.
/// - `rs2` — Source register.
/// - `aq` — Acquire-order bit.
/// - `rl` — Release-order bit; retained for the existing emitter API.
pub trait AmoswapBEmitter<T0, T1, T2, T3, T4> {
    fn amoswap_b(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4);
}

/// Atomic SWAP doubleword
///
/// Atomically:
///
///   * Load the doubleword at address _rs1_
///   * Write the value into _rd_
///   * Store the value of register _rs2_ to the address in _rs1_
///
/// # Forms
/// Assembly: `amoswap.d xd, xs2, (xrs1)`
/// Rust: `amoswap_d(rd, rs1, rs2, aq, rl)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Memory base register.
/// - `rs2` — Source register.
/// - `aq` — Acquire-order bit.
/// - `rl` — Release-order bit; retained for the existing emitter API.
pub trait AmoswapDEmitter<T0, T1, T2, T3, T4> {
    fn amoswap_d(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4);
}

/// RISC-V `amoswap.h` instruction.
///
/// # Forms
/// Assembly: `amoswap.h xd, xs1, xs2, aq, rl`
/// Rust: `amoswap_h(rd, rs1, rs2, aq, rl)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Memory base register.
/// - `rs2` — Source register.
/// - `aq` — Acquire-order bit.
/// - `rl` — Release-order bit; retained for the existing emitter API.
pub trait AmoswapHEmitter<T0, T1, T2, T3, T4> {
    fn amoswap_h(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4);
}

/// Atomic SWAP word
///
/// Atomically:
///
///   * Load the word at address _rs1_
///   * Write the sign-extended value into _rd_
///   * Store the least-significant word of register _rs2_ to the address in _rs1_
///
/// # Forms
/// Assembly: `amoswap.w xd, xs2, (xrs1)`
/// Rust: `amoswap_w(rd, rs1, rs2, aq, rl)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Memory base register.
/// - `rs2` — Source register.
/// - `aq` — Acquire-order bit.
/// - `rl` — Release-order bit; retained for the existing emitter API.
pub trait AmoswapWEmitter<T0, T1, T2, T3, T4> {
    fn amoswap_w(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4);
}

/// RISC-V `amoxor.b` instruction.
///
/// # Forms
/// Assembly: `amoxor.b xd, xs1, xs2, aq, rl`
/// Rust: `amoxor_b(rd, rs1, rs2, aq, rl)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Memory base register.
/// - `rs2` — Source register.
/// - `aq` — Acquire-order bit.
/// - `rl` — Release-order bit; retained for the existing emitter API.
pub trait AmoxorBEmitter<T0, T1, T2, T3, T4> {
    fn amoxor_b(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4);
}

/// Atomic fetch-and-xor doubleword
///
/// Atomically:
///
///   * Load the doubleword at address _rs1_
///   * Write the loaded value into _rd_
///   * XOR the value of register _rs2_ to the loaded value
///   * Write the result to the address in _rs1_
///
/// # Forms
/// Assembly: `amoxor.d xd, xs2, (xrs1)`
/// Rust: `amoxor_d(rd, rs1, rs2, aq, rl)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Memory base register.
/// - `rs2` — Source register.
/// - `aq` — Acquire-order bit.
/// - `rl` — Release-order bit; retained for the existing emitter API.
pub trait AmoxorDEmitter<T0, T1, T2, T3, T4> {
    fn amoxor_d(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4);
}

/// RISC-V `amoxor.h` instruction.
///
/// # Forms
/// Assembly: `amoxor.h xd, xs1, xs2, aq, rl`
/// Rust: `amoxor_h(rd, rs1, rs2, aq, rl)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Memory base register.
/// - `rs2` — Source register.
/// - `aq` — Acquire-order bit.
/// - `rl` — Release-order bit; retained for the existing emitter API.
pub trait AmoxorHEmitter<T0, T1, T2, T3, T4> {
    fn amoxor_h(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4);
}

/// Atomic fetch-and-xor word
///
/// Atomically:
///
///   * Load the word at address _rs1_
///   * Write the sign-extended value into _rd_
///   * XOR the least-significant word of register _rs2_ to the loaded value
///   * Write the result to the address in _rs1_
///
/// # Forms
/// Assembly: `amoxor.w xd, xs2, (xrs1)`
/// Rust: `amoxor_w(rd, rs1, rs2, aq, rl)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Memory base register.
/// - `rs2` — Source register.
/// - `aq` — Acquire-order bit.
/// - `rl` — Release-order bit; retained for the existing emitter API.
pub trait AmoxorWEmitter<T0, T1, T2, T3, T4> {
    fn amoxor_w(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4);
}

/// And
///
/// And rs1 with rs2, and store the result in rd
///
/// # Forms
/// Assembly: `and xd, xs1, xs2`
/// Rust: `and(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait AndEmitter<T0, T1, T2> {
    fn and(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// And immediate
///
/// And an immediate to the value in rs1, and store the result in rd
///
/// # Forms
/// Assembly: `andi xd, xs1, imm`
/// Rust: `andi(rd, rs1, imm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `imm` — Immediate encoding value.
pub trait AndiEmitter<T0, T1, T2> {
    fn andi(&mut self, rd: T0, rs1: T1, imm: T2);
}

/// AND with inverted operand
///
/// This instruction performs the bitwise logical AND operation between `rs1` and the
/// bitwise inversion of `rs2`.
///
/// # Forms
/// Assembly: `andn xd, xs1, xs2`
/// Rust: `andn(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait AndnEmitter<T0, T1, T2> {
    fn andn(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// Add upper immediate to pc
///
/// Add an immediate to the current PC.
///
/// # Forms
/// Assembly: `auipc xd, imm`
/// Rust: `auipc(rd, imm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `imm` — Immediate encoding value.
pub trait AuipcEmitter<T0, T1> {
    fn auipc(&mut self, rd: T0, imm: T1);
}

/// Single-Bit clear (Register)
///
/// This instruction returns rs1 with a single bit cleared at the index specified in rs2.
/// The index is read from the lower log2(XLEN) bits of rs2.
///
/// # Forms
/// Assembly: `bclr xd, xs1, xs2`
/// Rust: `bclr(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait BclrEmitter<T0, T1, T2> {
    fn bclr(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// Single-Bit clear (Immediate)
///
/// This instruction returns rs1 with a single bit cleared at the index specified in shamt. The
/// index is read from the lower log2(XLEN) bits of shamt. For RV32, the encodings corresponding
/// to shamt\[5\]=1 are reserved.
///
/// # Forms
/// Assembly: `bclri xd, xs1, shamt`
/// Rust: `bclri(rd, rs1, shamtd)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `shamtd` — Immediate encoding value.
pub trait BclriEmitter<T0, T1, T2> {
    fn bclri(&mut self, rd: T0, rs1: T1, shamtd: T2);
}

/// Single-Bit clear (Immediate)
///
/// This instruction returns rs1 with a single bit cleared at the index specified in shamt. The
/// index is read from the lower log2(XLEN) bits of shamt. For RV32, the encodings corresponding
/// to shamt\[5\]=1 are reserved.
///
/// # Forms
/// Assembly: `bclri.rv32 xd, xs1, shamt`
/// Rust: `bclri_rv32(rd, rs1, shamtw)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `shamtw` — Immediate encoding value.
pub trait BclriRv32Emitter<T0, T1, T2> {
    fn bclri_rv32(&mut self, rd: T0, rs1: T1, shamtw: T2);
}

/// Branch if equal
///
/// Branch to PC + imm if
/// the value in register rs1 is equal to the value in register rs2.
///
/// Raise a `MisalignedAddress` exception if PC + imm is misaligned.
///
/// # Forms
/// Assembly: `beq xs1, xs2, imm`
/// Rust: `beq(rs1, rs2, imm)`
///
/// # Arguments
/// - `rs1` — Source register.
/// - `rs2` — Source register.
/// - `imm` — Immediate encoding value.
pub trait BeqEmitter<T0, T1, T2> {
    fn beq(&mut self, rs1: T0, rs2: T1, imm: T2);
}

/// RISC-V `beqz` instruction.
///
/// # Forms
/// Assembly: `beqz rs1 bimm12lohi`
/// Rust: `beqz(rs1, imm)`
///
/// # Arguments
/// - `rs1` — Source register.
/// - `imm` — Immediate encoding value.
pub trait BeqzEmitter<T0, T1> {
    fn beqz(&mut self, rs1: T0, imm: T1);
}

/// Single-Bit extract (Register)
///
/// This instruction returns a single bit extracted from rs1 at the index specified in rs2.
/// The index is read from the lower log2(XLEN) bits of rs2.
///
/// # Forms
/// Assembly: `bext xd, xs1, xs2`
/// Rust: `bext(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait BextEmitter<T0, T1, T2> {
    fn bext(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// Single-Bit extract (Immediate)
///
/// This instruction returns a single bit extracted from rs1 at the index specified in rs2.
/// The index is read from the lower log2(XLEN) bits of shamt. For RV32, the encodings
/// corresponding to shamt\[5\]=1 are reserved.
///
/// # Forms
/// Assembly: `bexti xd, xs1, shamt`
/// Rust: `bexti(rd, rs1, shamtd)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `shamtd` — Immediate encoding value.
pub trait BextiEmitter<T0, T1, T2> {
    fn bexti(&mut self, rd: T0, rs1: T1, shamtd: T2);
}

/// Single-Bit extract (Immediate)
///
/// This instruction returns a single bit extracted from rs1 at the index specified in rs2.
/// The index is read from the lower log2(XLEN) bits of shamt. For RV32, the encodings
/// corresponding to shamt\[5\]=1 are reserved.
///
/// # Forms
/// Assembly: `bexti.rv32 xd, xs1, shamt`
/// Rust: `bexti_rv32(rd, rs1, shamtw)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `shamtw` — Immediate encoding value.
pub trait BextiRv32Emitter<T0, T1, T2> {
    fn bexti_rv32(&mut self, rd: T0, rs1: T1, shamtw: T2);
}

/// Branch if greater than or equal
///
/// Branch to PC + imm if
/// the signed value in register rs1 is greater than or equal to the signed value in register rs2.
///
/// Raise a `MisalignedAddress` exception if PC + imm is misaligned.
///
/// # Forms
/// Assembly: `bge xs1, xs2, imm`
/// Rust: `bge(rs1, rs2, imm)`
///
/// # Arguments
/// - `rs1` — Source register.
/// - `rs2` — Source register.
/// - `imm` — Immediate encoding value.
pub trait BgeEmitter<T0, T1, T2> {
    fn bge(&mut self, rs1: T0, rs2: T1, imm: T2);
}

/// Branch if greater than or equal unsigned
///
/// Branch to PC + imm if
/// the unsigned value in register rs1 is greater than or equal to the unsigned value in register rs2.
///
/// Raise a `MisalignedAddress` exception if PC + imm is misaligned.
///
/// # Forms
/// Assembly: `bgeu xs1, xs2, imm`
/// Rust: `bgeu(rs1, rs2, imm)`
///
/// # Arguments
/// - `rs1` — Source register.
/// - `rs2` — Source register.
/// - `imm` — Immediate encoding value.
pub trait BgeuEmitter<T0, T1, T2> {
    fn bgeu(&mut self, rs1: T0, rs2: T1, imm: T2);
}

/// RISC-V `bgez` instruction.
///
/// # Forms
/// Assembly: `bgez rs1 bimm12lohi`
/// Rust: `bgez(rs1, imm)`
///
/// # Arguments
/// - `rs1` — Source register.
/// - `imm` — Immediate encoding value.
pub trait BgezEmitter<T0, T1> {
    fn bgez(&mut self, rs1: T0, imm: T1);
}

/// RISC-V `bgt` instruction.
///
/// # Forms
/// Assembly: `bgt rs1 rs2 bimm12lohi`
/// Rust: `bgt(rs1, rs2, imm)`
///
/// # Arguments
/// - `rs1` — Source register.
/// - `rs2` — Source register.
/// - `imm` — Immediate encoding value.
pub trait BgtEmitter<T0, T1, T2> {
    fn bgt(&mut self, rs1: T0, rs2: T1, imm: T2);
}

/// RISC-V `bgtu` instruction.
///
/// # Forms
/// Assembly: `bgtu rs1 rs2 bimm12lohi`
/// Rust: `bgtu(rs1, rs2, imm)`
///
/// # Arguments
/// - `rs1` — Source register.
/// - `rs2` — Source register.
/// - `imm` — Immediate encoding value.
pub trait BgtuEmitter<T0, T1, T2> {
    fn bgtu(&mut self, rs1: T0, rs2: T1, imm: T2);
}

/// RISC-V `bgtz` instruction.
///
/// # Forms
/// Assembly: `bgtz rs2 bimm12lohi`
/// Rust: `bgtz(rs2, imm)`
///
/// # Arguments
/// - `rs2` — Source register.
/// - `imm` — Immediate encoding value.
pub trait BgtzEmitter<T0, T1> {
    fn bgtz(&mut self, rs2: T0, imm: T1);
}

/// Single-Bit invert (Register)
///
/// This instruction returns rs1 with a single bit inverted at the index specified in rs2.
/// The index is read from the lower log2(XLEN) bits of rs2.
///
/// # Forms
/// Assembly: `binv xd, xs1, xs2`
/// Rust: `binv(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait BinvEmitter<T0, T1, T2> {
    fn binv(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// Single-Bit invert (Immediate)
///
/// This instruction returns rs1 with a single bit inverted at the index specified in shamt.
/// The index is read from the lower log2(XLEN) bits of shamt.
/// For RV32, the encodings corresponding to shamt\[5\]=1 are reserved.
///
/// # Forms
/// Assembly: `binvi xd, xs1, shamt`
/// Rust: `binvi(rd, rs1, shamtd)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `shamtd` — Immediate encoding value.
pub trait BinviEmitter<T0, T1, T2> {
    fn binvi(&mut self, rd: T0, rs1: T1, shamtd: T2);
}

/// Single-Bit invert (Immediate)
///
/// This instruction returns rs1 with a single bit inverted at the index specified in shamt.
/// The index is read from the lower log2(XLEN) bits of shamt.
/// For RV32, the encodings corresponding to shamt\[5\]=1 are reserved.
///
/// # Forms
/// Assembly: `binvi.rv32 xd, xs1, shamt`
/// Rust: `binvi_rv32(rd, rs1, shamtw)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `shamtw` — Immediate encoding value.
pub trait BinviRv32Emitter<T0, T1, T2> {
    fn binvi_rv32(&mut self, rd: T0, rs1: T1, shamtw: T2);
}

/// RISC-V `ble` instruction.
///
/// # Forms
/// Assembly: `ble rs1 rs2 bimm12lohi`
/// Rust: `ble(rs1, rs2, imm)`
///
/// # Arguments
/// - `rs1` — Source register.
/// - `rs2` — Source register.
/// - `imm` — Immediate encoding value.
pub trait BleEmitter<T0, T1, T2> {
    fn ble(&mut self, rs1: T0, rs2: T1, imm: T2);
}

/// RISC-V `bleu` instruction.
///
/// # Forms
/// Assembly: `bleu rs1 rs2 bimm12lohi`
/// Rust: `bleu(rs1, rs2, imm)`
///
/// # Arguments
/// - `rs1` — Source register.
/// - `rs2` — Source register.
/// - `imm` — Immediate encoding value.
pub trait BleuEmitter<T0, T1, T2> {
    fn bleu(&mut self, rs1: T0, rs2: T1, imm: T2);
}

/// RISC-V `blez` instruction.
///
/// # Forms
/// Assembly: `blez rs2 bimm12lohi`
/// Rust: `blez(rs2, imm)`
///
/// # Arguments
/// - `rs2` — Source register.
/// - `imm` — Immediate encoding value.
pub trait BlezEmitter<T0, T1> {
    fn blez(&mut self, rs2: T0, imm: T1);
}

/// Branch if less than
///
/// Branch to PC + imm if
/// the signed value in register rs1 is less than the signed value in register rs2.
///
/// Raise a `MisalignedAddress` exception if PC + imm is misaligned.
///
/// # Forms
/// Assembly: `blt xs1, xs2, imm`
/// Rust: `blt(rs1, rs2, imm)`
///
/// # Arguments
/// - `rs1` — Source register.
/// - `rs2` — Source register.
/// - `imm` — Immediate encoding value.
pub trait BltEmitter<T0, T1, T2> {
    fn blt(&mut self, rs1: T0, rs2: T1, imm: T2);
}

/// Branch if less than unsigned
///
/// Branch to PC + imm if
/// the unsigned value in register rs1 is less than the unsigned value in register rs2.
///
/// Raise a `MisalignedAddress` exception if PC + imm is misaligned.
///
/// # Forms
/// Assembly: `bltu xs1, xs2, imm`
/// Rust: `bltu(rs1, rs2, imm)`
///
/// # Arguments
/// - `rs1` — Source register.
/// - `rs2` — Source register.
/// - `imm` — Immediate encoding value.
pub trait BltuEmitter<T0, T1, T2> {
    fn bltu(&mut self, rs1: T0, rs2: T1, imm: T2);
}

/// RISC-V `bltz` instruction.
///
/// # Forms
/// Assembly: `bltz rs1 bimm12lohi`
/// Rust: `bltz(rs1, imm)`
///
/// # Arguments
/// - `rs1` — Source register.
/// - `imm` — Immediate encoding value.
pub trait BltzEmitter<T0, T1> {
    fn bltz(&mut self, rs1: T0, imm: T1);
}

/// Branch if not equal
///
/// Branch to PC + imm if
/// the value in register rs1 is not equal to the value in register rs2.
///
/// Raise a `MisalignedAddress` exception if PC + imm is misaligned.
///
/// # Forms
/// Assembly: `bne xs1, xs2, imm`
/// Rust: `bne(rs1, rs2, imm)`
///
/// # Arguments
/// - `rs1` — Source register.
/// - `rs2` — Source register.
/// - `imm` — Immediate encoding value.
pub trait BneEmitter<T0, T1, T2> {
    fn bne(&mut self, rs1: T0, rs2: T1, imm: T2);
}

/// RISC-V `bnez` instruction.
///
/// # Forms
/// Assembly: `bnez rs1 bimm12lohi`
/// Rust: `bnez(rs1, imm)`
///
/// # Arguments
/// - `rs1` — Source register.
/// - `imm` — Immediate encoding value.
pub trait BnezEmitter<T0, T1> {
    fn bnez(&mut self, rs1: T0, imm: T1);
}

/// Reverse bits in bytes
///
/// This instruction reverses the order of the bits in every byte of a register.
///
/// # Forms
/// Assembly: `brev8 xd, xs1`
/// Rust: `brev8(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait Brev8Emitter<T0, T1> {
    fn brev8(&mut self, rd: T0, rs1: T1);
}

/// Single-Bit set (Register)
///
/// This instruction returns rs1 with a single bit set at the index specified in rs2.
/// The index is read from the lower log2(XLEN) bits of rs2.
///
/// # Forms
/// Assembly: `bset xd, xs1, xs2`
/// Rust: `bset(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait BsetEmitter<T0, T1, T2> {
    fn bset(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// Single-Bit set (Immediate)
///
/// This instruction returns rs1 with a single bit set at the index specified in shamt.
/// The index is read from the lower log2(XLEN) bits of shamt.
/// For RV32, the encodings corresponding to shamt\[5\]=1 are reserved.
///
/// # Forms
/// Assembly: `bseti xd, xs1, shamt`
/// Rust: `bseti(rd, rs1, shamtd)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `shamtd` — Immediate encoding value.
pub trait BsetiEmitter<T0, T1, T2> {
    fn bseti(&mut self, rd: T0, rs1: T1, shamtd: T2);
}

/// Single-Bit set (Immediate)
///
/// This instruction returns rs1 with a single bit set at the index specified in shamt.
/// The index is read from the lower log2(XLEN) bits of shamt.
/// For RV32, the encodings corresponding to shamt\[5\]=1 are reserved.
///
/// # Forms
/// Assembly: `bseti.rv32 xd, xs1, shamt`
/// Rust: `bseti_rv32(rd, rs1, shamtw)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `shamtw` — Immediate encoding value.
pub trait BsetiRv32Emitter<T0, T1, T2> {
    fn bseti_rv32(&mut self, rd: T0, rs1: T1, shamtw: T2);
}

/// Add
///
/// Add the value in rs2 to rd, and store the result in rd.
/// C.ADD expands into `add rd, rd, rs2`.
///
/// # Forms
/// Assembly: `c.add xd, rs2`
/// Rust: `c_add(rd, rs2)`
///
/// # Arguments
/// - `rd` — Destination/source register.
/// - `rs2` — Instruction operand.
pub trait CAddEmitter<T0, T1> {
    fn c_add(&mut self, rd: T0, rs2: T1);
}

/// Add a sign-extended non-zero immediate
///
/// C.ADDI adds the non-zero sign-extended 6-bit immediate to the value in register rd then writes the result to rd.
/// C.ADDI expands into `addi rd, rd, imm`.
/// C.ADDI is only valid when rd &ne; x0 and imm &ne; 0.
/// The code points with rd=x0 encode the C.NOP instruction; the remaining code points with imm=0 encode HINTs.
///
/// # Forms
/// Assembly: `c.addi xd, imm`
/// Rust: `c_addi(rd, imm)`
///
/// # Arguments
/// - `rd` — Destination/source register.
/// - `imm` — Immediate encoding value.
pub trait CAddiEmitter<T0, T1> {
    fn c_addi(&mut self, rd: T0, imm: T1);
}

/// Add a sign-extended non-zero immediate
///
/// C.ADDI16SP adds the non-zero sign-extended 6-bit immediate to the value in the stack pointer (sp=x2), where the immediate is scaled to represent multiples of 16 in the range (-512,496).
/// C.ADDI16SP is used to adjust the stack pointer in procedure prologues and epilogues.
/// It expands into `addi x2, x2, nzimm\[9:4\]`.
/// C.ADDI16SP is only valid when nzimm &ne; 0; the code point with nzimm=0 is reserved.
///
/// # Forms
/// Assembly: `c.addi16sp imm`
/// Rust: `c_addi16sp(imm)`
///
/// # Arguments
/// - `imm` — Immediate encoding value.
pub trait CAddi16spEmitter<T0> {
    fn c_addi16sp(&mut self, imm: T0);
}

/// Add a zero-extended non-zero immediate, scaled by 4, to the stack pointer
///
/// Adds a zero-extended non-zero immediate, scaled by 4, to the stack pointer, x2, and writes the result to rd'.
/// This instruction is used to generate pointers to stack-allocated variables.
/// It expands to `addi rd', x2, nzuimm\[9:2\]`.
/// C.ADDI4SPN is only valid when nzuimm &ne; 0; the code points with nzuimm=0 are reserved.
///
/// # Forms
/// Assembly: `c.addi4spn xd, imm`
/// Rust: `c_addi4spn(rd, imm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `imm` — Immediate encoding value.
pub trait CAddi4spnEmitter<T0, T1> {
    fn c_addi4spn(&mut self, rd: T0, imm: T1);
}

/// Add a sign-extended non-zero immediate
///
/// C.ADDIW is an RV64C/RV128C-only instruction that performs the same computation as C.ADDI but produces a 32-bit result, then sign-extends result to 64 bits.
/// C.ADDIW expands into `addiw rd, rd, imm`.
/// The immediate can be zero for C.ADDIW, where this corresponds to `sext.w rd`.
/// C.ADDIW is only valid when rd &ne; x0; the code points with rd=x0 are reserved.
///
/// # Forms
/// Assembly: `c.addiw xd, imm`
/// Rust: `c_addiw(rd, imm)`
///
/// # Arguments
/// - `rd` — Destination/source register.
/// - `imm` — Immediate encoding value.
pub trait CAddiwEmitter<T0, T1> {
    fn c_addiw(&mut self, rd: T0, imm: T1);
}

/// Add word
///
/// Add the 32-bit values in rs2 from rd, and store the result in rd.
/// The rd and rs2 register indexes should be used as rd+8 and rs2+8 (registers x8-x15).
/// C.ADDW expands into `addw rd, rd, rs2`.
///
/// # Forms
/// Assembly: `c.addw xd, rs2`
/// Rust: `c_addw(rd, rs2)`
///
/// # Arguments
/// - `rd` — Destination/source register.
/// - `rs2` — Source register.
pub trait CAddwEmitter<T0, T1> {
    fn c_addw(&mut self, rd: T0, rs2: T1);
}

/// And
///
/// And rd with rs2, and store the result in rd
/// The rd and rs2 register indexes should be used as rd+8 and rs2+8 (registers x8-x15).
/// C.AND expands into `and rd, rd, rs2`.
///
/// # Forms
/// Assembly: `c.and xd, rs2`
/// Rust: `c_and(rd, rs2)`
///
/// # Arguments
/// - `rd` — Destination/source register.
/// - `rs2` — Source register.
pub trait CAndEmitter<T0, T1> {
    fn c_and(&mut self, rd: T0, rs2: T1);
}

/// And immediate
///
/// And an immediate to the value in rd, and store the result in rd.
/// The rd register index should be used as rd+8 (registers x8-x15).
/// C.ANDI expands into `andi rd, rd, imm`.
///
/// # Forms
/// Assembly: `c.andi xd, imm`
/// Rust: `c_andi(rd, imm)`
///
/// # Arguments
/// - `rd` — Destination/source register.
/// - `imm` — Immediate encoding value.
pub trait CAndiEmitter<T0, T1> {
    fn c_andi(&mut self, rd: T0, imm: T1);
}

/// Branch if Equal Zero
///
/// C.BEQZ performs conditional control transfers. The offset is sign-extended and added to the pc to form the branch target address. It can therefore target a &pm;256 B range. C.BEQZ takes the branch if the value in register rs1' is zero.
/// It expands to `beq` `rs1, x0, offset`.
///
/// # Forms
/// Assembly: `c.beqz xs1, imm`
/// Rust: `c_beqz(rs1, bimm9lohi)`
///
/// # Arguments
/// - `rs1` — Source register.
/// - `bimm9lohi` — Immediate encoding value.
pub trait CBeqzEmitter<T0, T1> {
    fn c_beqz(&mut self, rs1: T0, bimm9lohi: T1);
}

/// Branch if NOT Equal Zero
///
/// C.BEQZ performs conditional control transfers. The offset is sign-extended and added to the pc to form the branch target address. It can therefore target a &pm;256 B range. C.BEQZ takes the branch if the value in register rs1' is NOT zero.
/// It expands to `beq` `rs1, x0, offset`.
///
/// # Forms
/// Assembly: `c.bnez xs1, imm`
/// Rust: `c_bnez(rs1, bimm9lohi)`
///
/// # Arguments
/// - `rs1` — Source register.
/// - `bimm9lohi` — Immediate encoding value.
pub trait CBnezEmitter<T0, T1> {
    fn c_bnez(&mut self, rs1: T0, bimm9lohi: T1);
}

/// Breakpoint exception.
///
/// The C.EBREAK instruction is used by debuggers to cause control to be transferred back to
/// a debugging environment. Unless overridden by an external debug environment,
/// C.EBREAK raises a breakpoint exception and performs no other operation.
///
/// \[NOTE\]
/// As described in the `C` Standard Extension for Compressed Instructions, the `c.ebreak`
/// instruction performs the same operation as the EBREAK instruction.
///
/// EBREAK causes the receiving privilege mode's epc register to be set to the address of
/// the EBREAK instruction itself, not the address of the following instruction.
/// As EBREAK causes a synchronous exception, it is not considered to retire,
/// and should not increment the `minstret` CSR.
///
/// # Forms
/// Assembly: `c.ebreak " "`
/// Rust: `c_ebreak()`
///
/// # Arguments
pub trait CEbreakEmitter {
    fn c_ebreak(&mut self);
}

/// Load double-precision
///
/// Loads a double precision floating-point value from memory into register rd.
/// It computes an effective address by adding the zero-extended offset, scaled by 8,
/// to the base address in register rs1.
/// It expands to `fld` `rd, offset(rs1)`.
///
/// # Forms
/// Assembly: `c.fld xd, imm(xs1)`
/// Rust: `c_fld(rd, rs1, imm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Memory base register.
/// - `imm` — Immediate encoding value.
pub trait CFldEmitter<T0, T1, T2> {
    fn c_fld(&mut self, rd: T0, rs1: T1, imm: T2);
}

/// Load doubleword into floating-point register from stack
///
/// Loads a double-precision floating-point value from memory into floating-point register rd.
/// It computes its effective address by adding the zero-extended offset, scaled by 8,
/// to the stack pointer, x2.
/// It expands to `fld` `rd, offset(x2)`.
///
/// # Forms
/// Assembly: `c.fldsp fd, imm(sp)`
/// Rust: `c_fldsp(rd, imm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `imm` — Immediate encoding value.
pub trait CFldspEmitter<T0, T1> {
    fn c_fldsp(&mut self, rd: T0, imm: T1);
}

/// Load single-precision
///
/// Loads a single precision floating-point value from memory into register rd.
/// It computes an effective address by adding the zero-extended offset, scaled by 4,
/// to the base address in register rs1.
/// It expands to `flw` `rd, offset(rs1)`.
///
/// # Forms
/// Assembly: `c.flw xd, imm(xs1)`
/// Rust: `c_flw(rd, rs1, imm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Memory base register.
/// - `imm` — Immediate encoding value.
pub trait CFlwEmitter<T0, T1, T2> {
    fn c_flw(&mut self, rd: T0, rs1: T1, imm: T2);
}

/// Load word into floating-point register from stack
///
/// Loads a single-precision floating-point value from memory into floating-point register rd.
/// It computes its effective address by adding the zero-extended offset, scaled by 4,
/// to the stack pointer, x2.
/// It expands to `flw` `rd, offset(x2)`.
///
/// # Forms
/// Assembly: `c.flwsp fd, imm(sp)`
/// Rust: `c_flwsp(rd, imm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `imm` — Immediate encoding value.
pub trait CFlwspEmitter<T0, T1> {
    fn c_flwsp(&mut self, rd: T0, imm: T1);
}

/// Store double-precision
///
/// Stores a double precision floating-point value in register rs2 to memory.
/// It computes an effective address by adding the zero-extended offset, scaled by 8,
/// to the base address in register rs1.
/// It expands to `fsd` `rs2, offset(rs1)`.
///
/// # Forms
/// Assembly: `c.fsd xs2, imm(xs1)`
/// Rust: `c_fsd(rs1, rs2, imm)`
///
/// # Arguments
/// - `rs1` — Memory base register.
/// - `rs2` — Source register.
/// - `imm` — Immediate encoding value.
pub trait CFsdEmitter<T0, T1, T2> {
    fn c_fsd(&mut self, rs1: T0, rs2: T1, imm: T2);
}

/// Store double-precision value to stack
///
/// Stores a double-precision floating-point value in floating-point register rs2 to memory.
/// It computes an effective address by adding the zero-extended offset, scaled by 8,
/// to the stack pointer, x2.
/// It expands to `fsd` `rs2, offset(x2)`.
///
/// # Forms
/// Assembly: `c.fsdsp fs2, imm(sp)`
/// Rust: `c_fsdsp(rs2, imm)`
///
/// # Arguments
/// - `rs2` — Instruction operand.
/// - `imm` — Immediate encoding value.
pub trait CFsdspEmitter<T0, T1> {
    fn c_fsdsp(&mut self, rs2: T0, imm: T1);
}

/// Store single-precision
///
/// Stores a single precision floating-point value in register rs2 to memory.
/// It computes an effective address by adding the zero-extended offset, scaled by 4,
/// to the base address in register rs1.
/// It expands to `fsw` `rs2, offset(rs1)`.
///
/// # Forms
/// Assembly: `c.fsw xs2, imm(xs1)`
/// Rust: `c_fsw(rs1, rs2, imm)`
///
/// # Arguments
/// - `rs1` — Memory base register.
/// - `rs2` — Source register.
/// - `imm` — Immediate encoding value.
pub trait CFswEmitter<T0, T1, T2> {
    fn c_fsw(&mut self, rs1: T0, rs2: T1, imm: T2);
}

/// Store single-precision value to stack
///
/// Stores a single-precision floating-point value in floating-point register rs2 to memory.
/// It computes an effective address by adding the zero-extended offset, scaled by 4,
/// to the stack pointer, x2.
/// It expands to `fsw` `rs2, offset(x2)`.
///
/// # Forms
/// Assembly: `c.fswsp fs2, imm(sp)`
/// Rust: `c_fswsp(rs2, imm)`
///
/// # Arguments
/// - `rs2` — Instruction operand.
/// - `imm` — Immediate encoding value.
pub trait CFswspEmitter<T0, T1> {
    fn c_fswsp(&mut self, rs2: T0, imm: T1);
}

/// Jump
///
/// C.J performs an unconditional control transfer. The offset is sign-extended and added to the pc to form the jump target address. C.J can therefore target a &pm;2 KiB range.
/// It expands to `jal` `x0, offset`.
///
/// # Forms
/// Assembly: `c.j imm`
/// Rust: `c_j(imm)`
///
/// # Arguments
/// - `imm` — Immediate encoding value.
pub trait CJEmitter<T0> {
    fn c_j(&mut self, imm: T0);
}

/// Jump and Link
///
/// C.JAL is an RV32C-only instruction that performs the same operation as C.J, but additionally writes the address of the instruction following the jump (pc+2) to the link register, x1.
/// It expands to `jal` `x1, offset`.
///
/// # Forms
/// Assembly: `c.jal imm`
/// Rust: `c_jal(imm)`
///
/// # Arguments
/// - `imm` — Immediate encoding value.
pub trait CJalEmitter<T0> {
    fn c_jal(&mut self, imm: T0);
}

/// Jump and Link Register.
///
/// C.JALR (jump and link register) performs the same operation as C.JR, but additionally writes the address of the instruction following the jump (pc+2) to the link register, x1.
/// C.JALR expands to jalr x1, 0(rs1).
///
/// # Forms
/// Assembly: `c.jalr xs1`
/// Rust: `c_jalr(rs1)`
///
/// # Arguments
/// - `rs1` — Instruction operand.
pub trait CJalrEmitter<T0> {
    fn c_jalr(&mut self, rs1: T0);
}

/// Jump Register
///
/// C.JR (jump register) performs an unconditional control transfer to the address in register rs1.
/// C.JR expands to jalr x0, 0(rs1).
///
/// # Forms
/// Assembly: `c.jr xs1`
/// Rust: `c_jr(rs1)`
///
/// # Arguments
/// - `rs1` — Source register.
pub trait CJrEmitter<T0> {
    fn c_jr(&mut self, rs1: T0);
}

/// Load unsigned byte, 16-bit encoding
///
/// Loads a 8-bit value from memory into register rd.
/// It computes an effective address by adding the zero-extended offset, to the base address in register rs1.
/// It expands to `lbu` `rd, offset(rs1)`.
///
/// # Forms
/// Assembly: `c.lbu xd, imm(xs1)`
/// Rust: `c_lbu(rd, rs1, imm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `imm` — Immediate encoding value.
pub trait CLbuEmitter<T0, T1, T2> {
    fn c_lbu(&mut self, rd: T0, rs1: T1, imm: T2);
}

/// Load double
///
/// Loads a 64-bit value from memory into register rd.
/// It computes an effective address by adding the zero-extended offset, scaled by 8,
/// to the base address in register rs1.
/// It expands to `ld` `rd, offset(rs1)`.
///
/// # Forms
/// Assembly: `c.ld xd, imm(xs1)`
/// Rust: `c_ld(rd, rs1, imm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Memory base register.
/// - `imm` — Immediate encoding value.
pub trait CLdEmitter<T0, T1, T2> {
    fn c_ld(&mut self, rd: T0, rs1: T1, imm: T2);
}

/// Load doubleword from stack pointer
///
/// C.LDSP is an RV64C/RV128C-only instruction that loads a 64-bit value from memory
/// into register rd.
/// It computes its effective address by adding the zero-extended offset, scaled by 8,
/// to the stack pointer, x2.
/// It expands to `ld` `rd, offset(x2)`.
/// C.LDSP is only valid when rd &ne; x0 the code points with rd=x0 are reserved.
///
/// # Forms
/// Assembly: `c.ldsp xd, imm(sp)`
/// Rust: `c_ldsp(rd, imm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `imm` — Immediate encoding value.
pub trait CLdspEmitter<T0, T1> {
    fn c_ldsp(&mut self, rd: T0, imm: T1);
}

/// Load signed halfword, 16-bit encoding
///
/// Loads a 16-bit value from memory into register rd.
/// It computes an effective address by adding the zero-extended offset, to the base address in register rs1.
/// It expands to `lh` `rd, offset(rs1)`.
///
/// # Forms
/// Assembly: `c.lh xd, imm(xs1)`
/// Rust: `c_lh(rd, rs1, imm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `imm` — Immediate encoding value.
pub trait CLhEmitter<T0, T1, T2> {
    fn c_lh(&mut self, rd: T0, rs1: T1, imm: T2);
}

/// Load unsigned halfword, 16-bit encoding
///
/// Loads a 16-bit value from memory into register rd.
/// It computes an effective address by adding the zero-extended offset, to the base address in register rs1.
/// It expands to `lhu` `rd, offset(rs1)`.
///
/// # Forms
/// Assembly: `c.lhu xd, imm(xs1)`
/// Rust: `c_lhu(rd, rs1, imm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `imm` — Immediate encoding value.
pub trait CLhuEmitter<T0, T1, T2> {
    fn c_lhu(&mut self, rd: T0, rs1: T1, imm: T2);
}

/// Load the sign-extended 6-bit immediate
///
/// C.LI loads the sign-extended 6-bit immediate, imm, into register rd.
/// C.LI expands into `addi rd, x0, imm`.
/// C.LI is only valid when rd &ne; x0; the code points with rd=x0 encode HINTs.
///
/// # Forms
/// Assembly: `c.li xd, imm`
/// Rust: `c_li(rd, imm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `imm` — Immediate encoding value.
pub trait CLiEmitter<T0, T1> {
    fn c_li(&mut self, rd: T0, imm: T1);
}

/// Load the non-zero 6-bit immediate field into bits 17-12 of the destination register
///
/// C.LUI loads the non-zero 6-bit immediate field into bits 17-12 of the destination register, clears the bottom 12 bits, and sign-extends bit 17 into all higher bits of the destination.
/// C.LUI expands into `lui rd, imm`.
/// C.LUI is only valid when rd&ne;x0 and rd&ne;x2, and when the immediate is not equal to zero.
/// The code points with imm=0 are reserved; the remaining code points with rd=x0 are HINTs; and the remaining code points with rd=x2 correspond to the C.ADDI16SP instruction
///
/// # Forms
/// Assembly: `c.lui xd, imm`
/// Rust: `c_lui(rd, imm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `imm` — Immediate encoding value.
pub trait CLuiEmitter<T0, T1> {
    fn c_lui(&mut self, rd: T0, imm: T1);
}

/// Load word
///
/// Loads a 32-bit value from memory into register rd.
/// It computes an effective address by adding the zero-extended offset, scaled by 4,
/// to the base address in register rs1.
/// It expands to `lw` `rd, offset(rs1)`.
///
/// # Forms
/// Assembly: `c.lw xd, imm(xs1)`
/// Rust: `c_lw(rd, rs1, imm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Memory base register.
/// - `imm` — Immediate encoding value.
pub trait CLwEmitter<T0, T1, T2> {
    fn c_lw(&mut self, rd: T0, rs1: T1, imm: T2);
}

/// Load word from stack pointer
///
/// Loads a 32-bit value from memory into register rd.
/// It computes an effective address by adding the zero-extended offset, scaled by 4,
/// to the stack pointer, x2.
/// It expands to `lw` `rd, offset(x2)`.
/// C.LWSP is only valid when rd &ne; x0. The code points with rd=x0 are reserved.
///
/// # Forms
/// Assembly: `c.lwsp xd, imm(sp)`
/// Rust: `c_lwsp(rd, imm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `imm` — Immediate encoding value.
pub trait CLwspEmitter<T0, T1> {
    fn c_lwsp(&mut self, rd: T0, imm: T1);
}

/// RISC-V `c.mop.1` instruction.
///
/// # Forms
/// Assembly: `c.mop.1`
/// Rust: `c_mop_1()`
///
/// # Arguments
pub trait CMop1Emitter {
    fn c_mop_1(&mut self);
}

/// RISC-V `c.mop.11` instruction.
///
/// # Forms
/// Assembly: `c.mop.11`
/// Rust: `c_mop_11()`
///
/// # Arguments
pub trait CMop11Emitter {
    fn c_mop_11(&mut self);
}

/// RISC-V `c.mop.13` instruction.
///
/// # Forms
/// Assembly: `c.mop.13`
/// Rust: `c_mop_13()`
///
/// # Arguments
pub trait CMop13Emitter {
    fn c_mop_13(&mut self);
}

/// RISC-V `c.mop.15` instruction.
///
/// # Forms
/// Assembly: `c.mop.15`
/// Rust: `c_mop_15()`
///
/// # Arguments
pub trait CMop15Emitter {
    fn c_mop_15(&mut self);
}

/// RISC-V `c.mop.3` instruction.
///
/// # Forms
/// Assembly: `c.mop.3`
/// Rust: `c_mop_3()`
///
/// # Arguments
pub trait CMop3Emitter {
    fn c_mop_3(&mut self);
}

/// RISC-V `c.mop.5` instruction.
///
/// # Forms
/// Assembly: `c.mop.5`
/// Rust: `c_mop_5()`
///
/// # Arguments
pub trait CMop5Emitter {
    fn c_mop_5(&mut self);
}

/// RISC-V `c.mop.7` instruction.
///
/// # Forms
/// Assembly: `c.mop.7`
/// Rust: `c_mop_7()`
///
/// # Arguments
pub trait CMop7Emitter {
    fn c_mop_7(&mut self);
}

/// RISC-V `c.mop.9` instruction.
///
/// # Forms
/// Assembly: `c.mop.9`
/// Rust: `c_mop_9()`
///
/// # Arguments
pub trait CMop9Emitter {
    fn c_mop_9(&mut self);
}

/// RISC-V `c.mop.n` instruction.
///
/// # Forms
/// Assembly: `c.mop.n c_mop_t`
/// Rust: `c_mop_n(mop_t)`
///
/// # Arguments
/// - `mop_t` — Instruction operand.
pub trait CMopNEmitter<T0> {
    fn c_mop_n(&mut self, mop_t: T0);
}

/// Multiply, 16-bit encoding
///
/// This instruction multiplies XLEN bits of the source operands from rsd' and rs2' and writes the lowest XLEN bits of the result to rsd'.
///
/// # Forms
/// Assembly: `c.mul xd, xs2`
/// Rust: `c_mul(rd, rs2)`
///
/// # Arguments
/// - `rd` — Destination/source register.
/// - `rs2` — Source register.
pub trait CMulEmitter<T0, T1> {
    fn c_mul(&mut self, rd: T0, rs2: T1);
}

/// Move Register
///
/// C.MV (move register) performs copy of the data in register rs2 to register rd
/// C.MV expands to addi rd, x0, rs2.
///
/// # Forms
/// Assembly: `c.mv xd, xs2`
/// Rust: `c_mv(rd, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs2` — Instruction operand.
pub trait CMvEmitter<T0, T1> {
    fn c_mv(&mut self, rd: T0, rs2: T1);
}

/// Non-operation
///
/// C.NOP expands into `addi x0, x0, imm`.
///
/// # Forms
/// Assembly: `c.nop imm`
/// Rust: `c_nop(imm)`
///
/// # Arguments
/// - `imm` — Immediate encoding value.
pub trait CNopEmitter<T0> {
    fn c_nop(&mut self, imm: T0);
}

/// Bitwise not, 16-bit encoding
///
/// This instruction takes a single source/destination operand.
/// This instruction takes the one's complement of rd'/rs1' and writes the result to the same register.
///
/// # Forms
/// Assembly: `c.not xd`
/// Rust: `c_not(rd)`
///
/// # Arguments
/// - `rd` — Destination/source register.
pub trait CNotEmitter<T0> {
    fn c_not(&mut self, rd: T0);
}

/// RISC-V `c.ntl.all` instruction.
///
/// # Forms
/// Assembly: `c.ntl.all`
/// Rust: `c_ntl_all()`
///
/// # Arguments
pub trait CNtlAllEmitter {
    fn c_ntl_all(&mut self);
}

/// RISC-V `c.ntl.p1` instruction.
///
/// # Forms
/// Assembly: `c.ntl.p1`
/// Rust: `c_ntl_p1()`
///
/// # Arguments
pub trait CNtlP1Emitter {
    fn c_ntl_p1(&mut self);
}

/// RISC-V `c.ntl.pall` instruction.
///
/// # Forms
/// Assembly: `c.ntl.pall`
/// Rust: `c_ntl_pall()`
///
/// # Arguments
pub trait CNtlPallEmitter {
    fn c_ntl_pall(&mut self);
}

/// RISC-V `c.ntl.s1` instruction.
///
/// # Forms
/// Assembly: `c.ntl.s1`
/// Rust: `c_ntl_s1()`
///
/// # Arguments
pub trait CNtlS1Emitter {
    fn c_ntl_s1(&mut self);
}

/// Or
///
/// Or rd with rs2, and store the result in rd
/// The rd and rs2 register indexes should be used as rd+8 and rs2+8 (registers x8-x15).
/// C.OR expands into `or rd, rd, rs2`.
///
/// # Forms
/// Assembly: `c.or xd, rs2`
/// Rust: `c_or(rd, rs2)`
///
/// # Arguments
/// - `rd` — Destination/source register.
/// - `rs2` — Source register.
pub trait COrEmitter<T0, T1> {
    fn c_or(&mut self, rd: T0, rs2: T1);
}

/// Store unsigned byte, 16-bit encoding
///
/// Stores a 8-bit value from register rs2 into memory.
/// It computes an effective address by adding the zero-extended offset, to the base address in register rs1.
/// It expands to `sb` `rs2, offset(rs1)`.
///
/// # Forms
/// Assembly: `c.sb xs2, imm(xs1)`
/// Rust: `c_sb(rs1, rs2, imm)`
///
/// # Arguments
/// - `rs1` — Source register.
/// - `rs2` — Source register.
/// - `imm` — Immediate encoding value.
pub trait CSbEmitter<T0, T1, T2> {
    fn c_sb(&mut self, rs1: T0, rs2: T1, imm: T2);
}

/// Store double
///
/// Stores a 64-bit value in register rs2 to memory.
/// It computes an effective address by adding the zero-extended offset, scaled by 8,
/// to the base address in register rs1.
/// It expands to `sd` `rs2, offset(rs1)`.
///
/// # Forms
/// Assembly: `c.sd xs2, imm(xs1)`
/// Rust: `c_sd(rs1, rs2, imm)`
///
/// # Arguments
/// - `rs1` — Memory base register.
/// - `rs2` — Source register.
/// - `imm` — Immediate encoding value.
pub trait CSdEmitter<T0, T1, T2> {
    fn c_sd(&mut self, rs1: T0, rs2: T1, imm: T2);
}

/// Store doubleword to stack
///
/// Stores a 64-bit value in register rs2 to memory.
/// It computes an effective address by adding the zero-extended offset, scaled by 8,
/// to the stack pointer, x2.
/// It expands to `sd` `rs2, offset(x2)`.
///
/// # Forms
/// Assembly: `c.sdsp xs2, imm(sp)`
/// Rust: `c_sdsp(rs2, imm)`
///
/// # Arguments
/// - `rs2` — Instruction operand.
/// - `imm` — Immediate encoding value.
pub trait CSdspEmitter<T0, T1> {
    fn c_sdsp(&mut self, rs2: T0, imm: T1);
}

/// Sign-extend byte, 16-bit encoding
///
/// This instruction takes a single source/destination operand.
/// This instruction sign-extends the least-significant byte of the source to XLEN by copying
/// the most-significant bit in the byte (i.e., bit 7) to all of the more-significant bits.
///
/// # Forms
/// Assembly: `c.sext.b xd`
/// Rust: `c_sext_b(rd)`
///
/// # Arguments
/// - `rd` — Destination/source register.
pub trait CSextBEmitter<T0> {
    fn c_sext_b(&mut self, rd: T0);
}

/// Sign-extend halfword, 16-bit encoding
///
/// This instruction takes a single source/destination operand.
/// This instruction sign-extends the least-significant halfword of the source to XLEN by copying
/// the most-significant bit in the halfword (i.e., bit 15) to all of the more-significant bits.
///
/// # Forms
/// Assembly: `c.sext.h xd`
/// Rust: `c_sext_h(rd)`
///
/// # Arguments
/// - `rd` — Destination/source register.
pub trait CSextHEmitter<T0> {
    fn c_sext_h(&mut self, rd: T0);
}

/// Store unsigned halfword, 16-bit encoding
///
/// Stores a 16-bit value from register rs2 into memory.
/// It computes an effective address by adding the zero-extended offset, to the base address in register rs1.
/// It expands to `sh` `rs2, offset(rs1)`.
///
/// # Forms
/// Assembly: `c.sh xs2, imm(xs1)`
/// Rust: `c_sh(rs1, rs2, imm)`
///
/// # Arguments
/// - `rs1` — Source register.
/// - `rs2` — Source register.
/// - `imm` — Immediate encoding value.
pub trait CShEmitter<T0, T1, T2> {
    fn c_sh(&mut self, rs1: T0, rs2: T1, imm: T2);
}

/// Shift left logical immediate
///
/// Shift the value in rd left by shamt, and store the result back in rd.
/// C.SLLI expands into `slli rd, rd, shamt`.
///
/// # Forms
/// Assembly: `c.slli xd, shamt`
/// Rust: `c_slli(rd, imm)`
///
/// # Arguments
/// - `rd` — Destination/source register.
/// - `imm` — Immediate encoding value.
pub trait CSlliEmitter<T0, T1> {
    fn c_slli(&mut self, rd: T0, imm: T1);
}

/// Shift left logical immediate
///
/// Shift the value in rd left by shamt, and store the result back in rd.
/// C.SLLI expands into `slli rd, rd, shamt`.
///
/// # Forms
/// Assembly: `c.slli.rv32 xd, shamt`
/// Rust: `c_slli_rv32(rd, imm)`
///
/// # Arguments
/// - `rd` — Destination/source register.
/// - `imm` — Immediate encoding value.
pub trait CSlliRv32Emitter<T0, T1> {
    fn c_slli_rv32(&mut self, rd: T0, imm: T1);
}

/// Shift right arithmetical immediate
///
/// Arithmetic shift (the original sign bit is copied into the vacated upper bits) the value in rd right by shamt, and store the result in rd.
/// The rd register index should be used as rd+8 (registers x8-x15).
/// C.SRAI expands into `srai rd, rd, shamt`.
///
/// # Forms
/// Assembly: `c.srai xd, shamt`
/// Rust: `c_srai(rd, imm)`
///
/// # Arguments
/// - `rd` — Destination/source register.
/// - `imm` — Immediate encoding value.
pub trait CSraiEmitter<T0, T1> {
    fn c_srai(&mut self, rd: T0, imm: T1);
}

/// Shift right arithmetical immediate
///
/// Arithmetic shift (the original sign bit is copied into the vacated upper bits) the value in rd right by shamt, and store the result in rd.
/// The rd register index should be used as rd+8 (registers x8-x15).
/// C.SRAI expands into `srai rd, rd, shamt`.
///
/// # Forms
/// Assembly: `c.srai.rv32 xd, shamt`
/// Rust: `c_srai_rv32(rd, imm)`
///
/// # Arguments
/// - `rd` — Destination/source register.
/// - `imm` — Immediate encoding value.
pub trait CSraiRv32Emitter<T0, T1> {
    fn c_srai_rv32(&mut self, rd: T0, imm: T1);
}

/// Shift right logical immediate
///
/// Shift the value in rd right by shamt, and store the result back in rd.
/// The rd register index should be used as rd+8 (registers x8-x15).
/// C.SRLI expands into `srli rd, rd, shamt`.
///
/// # Forms
/// Assembly: `c.srli xd, shamt`
/// Rust: `c_srli(rd, imm)`
///
/// # Arguments
/// - `rd` — Destination/source register.
/// - `imm` — Immediate encoding value.
pub trait CSrliEmitter<T0, T1> {
    fn c_srli(&mut self, rd: T0, imm: T1);
}

/// Shift right logical immediate
///
/// Shift the value in rd right by shamt, and store the result back in rd.
/// The rd register index should be used as rd+8 (registers x8-x15).
/// C.SRLI expands into `srli rd, rd, shamt`.
///
/// # Forms
/// Assembly: `c.srli.rv32 xd, shamt`
/// Rust: `c_srli_rv32(rd, imm)`
///
/// # Arguments
/// - `rd` — Destination/source register.
/// - `imm` — Immediate encoding value.
pub trait CSrliRv32Emitter<T0, T1> {
    fn c_srli_rv32(&mut self, rd: T0, imm: T1);
}

/// RISC-V `c.sspopchk.x5` instruction.
///
/// # Forms
/// Assembly: `c.sspopchk.x5`
/// Rust: `c_sspopchk_x5()`
///
/// # Arguments
pub trait CSspopchkX5Emitter {
    fn c_sspopchk_x5(&mut self);
}

/// RISC-V `c.sspush.x1` instruction.
///
/// # Forms
/// Assembly: `c.sspush.x1`
/// Rust: `c_sspush_x1()`
///
/// # Arguments
pub trait CSspushX1Emitter {
    fn c_sspush_x1(&mut self);
}

/// Subtract
///
/// Subtract the value in rs2 from rd, and store the result in rd.
/// The rd and rs2 register indexes should be used as rd+8 and rs2+8 (registers x8-x15).
/// C.SUB expands into `sub rd, rd, rs2`.
///
/// # Forms
/// Assembly: `c.sub xd, rs2`
/// Rust: `c_sub(rd, rs2)`
///
/// # Arguments
/// - `rd` — Destination/source register.
/// - `rs2` — Source register.
pub trait CSubEmitter<T0, T1> {
    fn c_sub(&mut self, rd: T0, rs2: T1);
}

/// Subtract word
///
/// Subtract the 32-bit values in rs2 from rd, and store the result in rd.
/// The rd and rs2 register indexes should be used as rd+8 and rs2+8 (registers x8-x15).
/// C.SUBW expands into `subw rd, rd, rs2`.
///
/// # Forms
/// Assembly: `c.subw xd, rs2`
/// Rust: `c_subw(rd, rs2)`
///
/// # Arguments
/// - `rd` — Destination/source register.
/// - `rs2` — Source register.
pub trait CSubwEmitter<T0, T1> {
    fn c_subw(&mut self, rd: T0, rs2: T1);
}

/// Store word
///
/// Stores a 32-bit value in register rs2 to memory.
/// It computes an effective address by adding the zero-extended offset, scaled by 4,
/// to the base address in register rs1.
/// It expands to `sw` `rs2, offset(rs1)`.
///
/// # Forms
/// Assembly: `c.sw xs2, imm(xs1)`
/// Rust: `c_sw(rs1, rs2, imm)`
///
/// # Arguments
/// - `rs1` — Memory base register.
/// - `rs2` — Source register.
/// - `imm` — Immediate encoding value.
pub trait CSwEmitter<T0, T1, T2> {
    fn c_sw(&mut self, rs1: T0, rs2: T1, imm: T2);
}

/// Store word to stack
///
/// Stores a 32-bit value in register rs2 to memory.
/// It computes an effective address by adding the zero-extended offset, scaled by 4,
/// to the stack pointer, x2.
/// It expands to `sw` `rs2, offset(x2)`.
///
/// # Forms
/// Assembly: `c.swsp xs2, imm(sp)`
/// Rust: `c_swsp(rs2, imm)`
///
/// # Arguments
/// - `rs2` — Instruction operand.
/// - `imm` — Immediate encoding value.
pub trait CSwspEmitter<T0, T1> {
    fn c_swsp(&mut self, rs2: T0, imm: T1);
}

/// Exclusive Or
///
/// Exclusive or rd with rs2, and store the result in rd
/// The rd and rs2 register indexes should be used as rd+8 and rs2+8 (registers x8-x15).
/// C.XOR expands into `xor rd, rd, rs2`.
///
/// # Forms
/// Assembly: `c.xor xd, rs2`
/// Rust: `c_xor(rd, rs2)`
///
/// # Arguments
/// - `rd` — Destination/source register.
/// - `rs2` — Source register.
pub trait CXorEmitter<T0, T1> {
    fn c_xor(&mut self, rd: T0, rs2: T1);
}

/// Zero-extend byte, 16-bit encoding
///
/// This instruction takes a single source/destination operand.
/// This instruction zero-extends the least-significant byte of the source to XLEN by inserting
/// 0's into all of the bits more significant than 7.
///
/// # Forms
/// Assembly: `c.zext.b xd`
/// Rust: `c_zext_b(rd)`
///
/// # Arguments
/// - `rd` — Destination/source register.
pub trait CZextBEmitter<T0> {
    fn c_zext_b(&mut self, rd: T0);
}

/// Zero-extend halfword, 16-bit encoding
///
/// This instruction takes a single source/destination operand.
/// This instruction zero-extends the least-significant halfword of the source to XLEN by inserting
/// 0's into all of the bits more significant than 15.
///
/// # Forms
/// Assembly: `c.zext.h xd`
/// Rust: `c_zext_h(rd)`
///
/// # Arguments
/// - `rd` — Destination/source register.
pub trait CZextHEmitter<T0> {
    fn c_zext_h(&mut self, rd: T0);
}

/// Zero-extend word, 16-bit encoding
///
/// This instruction takes a single source/destination operand.
/// It zero-extends the least-significant word of the operand to XLEN bits by inserting zeros into all of the bits more significant than 31.
///
/// # Forms
/// Assembly: `c.zext.w xd`
/// Rust: `c_zext_w(rd)`
///
/// # Arguments
/// - `rd` — Destination/source register.
pub trait CZextWEmitter<T0> {
    fn c_zext_w(&mut self, rd: T0);
}

/// Cache Block Clean
///
/// Cleans an entire cache block globally throughout the system.
///
/// Exactly what happens is coherence protocol-dependent, but in general it is expected that after this
/// operation():
///
///   * The cache block will be in the clean (not dirty) state in any coherent cache holding a valid copy of the line.
///   * The data will be cleaned to a point such that an incoherent load can observe the cleaned data.
///
/// `cbo.clean` is ordered by `FENCE` instructions but not `FENCE.I` or `SFENCE.VMA`.
///
/// &lt;%- if CACHE_BLOCK_SIZE.bit_length &gt; \[PMP_GRANULARITY, PMA_GRANULARITY\].min -%&gt;
/// Both PMP and PMA access control must be the same for all bytes in the block; otherwise, `cbo.clean` has UNSPECIFIED behavior.
/// &lt;%- end -%&gt;
///
/// Clean operations are treated as stores for page and access permissions. If permission checks fail,
/// one of the following exceptions will occur:
///
///   &lt;%- if ext?(:H) -%&gt;
///   * `Store/AMO Guest-Page Fault` if virtual memory translation fails during G-stage translation.
///   &lt;%- end -%&gt;
///   * `Store/AMO Page Fault` if virtual memory translation fails &lt;% if ext?(:H) %&gt;when V=0 or during VS-stage translation&lt;% end %&gt;
///   * `Store/AMO Access Fault` if a PMP or PMA access check fails
///
/// &lt;%- if CACHE_BLOCK_SIZE.bit_length &lt;= \[PMP_GRANULARITY, PMA_GRANULARITY\].min -%&gt;
/// Because cache blocks are naturally aligned and always fit in a single PMP or PMA regions, the PMP
/// and PMA access checks only need to check a single address in the line.
/// &lt;%- end -%&gt;
///
/// CBO operations never raise a misaligned address fault.
///
/// # Forms
/// Assembly: `cbo.clean "TODO"`
/// Rust: `cbo_clean(rs1)`
///
/// # Arguments
/// - `rs1` — Source register.
pub trait CboCleanEmitter<T0> {
    fn cbo_clean(&mut self, rs1: T0);
}

/// Cache Block Flush
///
/// Flushes an entire cache block by cleaning it and then invalidating it in all caches.
///
/// `cbo.flush` is ordered by `FENCE` instructions but not `FENCE.I` or `SFENCE.VMA`.
///
/// &lt;%- if CACHE_BLOCK_SIZE.bit_length &gt; \[PMP_GRANULARITY, PMA_GRANULARITY\].min -%&gt;
/// Both PMP and PMA access control must be the same for all bytes in the block; otherwise, `cbo.flush` has UNSPECIFIED behavior.
/// &lt;%- end -%&gt;
///
/// Flush operations are treated as stores for page and access permissions. If permission checks fail,
/// one of the following exceptions will occur:
///
///   &lt;%- if ext?(:H) -%&gt;
///   * `Store/AMO Guest-Page Fault` if virtual memory translation fails during G-stage translation.
///   &lt;%- end -%&gt;
///   * `Store/AMO Page Fault` if virtual memory translation fails &lt;% if ext?(:H) %&gt;when V=0 or during VS-stage translation&lt;% end %&gt;
///   * `Store/AMO Access Fault` if a PMP or PMA access check fails.
///
/// &lt;%- if CACHE_BLOCK_SIZE.bit_length &lt;= \[PMP_GRANULARITY, PMA_GRANULARITY\].min -%&gt;
/// Because cache blocks are naturally aligned and always fit in a single PMP or PMA regions, the PMP
/// and PMA access checks only need to check a single address in the line.
/// &lt;%- end -%&gt;
///
/// CBO operations never raise a misaligned address fault.
///
/// # Forms
/// Assembly: `cbo.flush "TODO"`
/// Rust: `cbo_flush(rs1)`
///
/// # Arguments
/// - `rs1` — Source register.
pub trait CboFlushEmitter<T0> {
    fn cbo_flush(&mut self, rs1: T0);
}

/// Cache Block Invalidate
///
/// Either invalidates or flushes (clean + invalidate) a cache block, depending on the current mode and value of
/// `menvcfg.CBIE`, `senvcfg.CBIE`, and/or `henvcfg.CBIE`.
///
/// The instruction is an invalidate (without a clean) when:
///
///   * In M-mode
///   * In (H)S-mode and `menvcfg.CBIE` == 11
///   * In U-mode and `menvcfg.CBIE` == 11 and `senvcfg.CBIE` == 11
///   * In VS-mode and `menvcfg.CBIE` == 11 and `henvcfg.CBIE` == 11
///   * In VU-mode and `menvcfg.CBIE` == 11 and `henvcfg.CBIE` == 11 and `senvcfg.CBIE` == 11
///
/// Otherwise, if the instruction does not trap (see Access section), the operation is a flush.
/// The table below summarizes the options.
///
/// \[%autowidth,cols="1,1,1,1,1,1,1,1",separator="!"\]
/// !===
/// .2+h!\[.rotate\]#`menvcfg.CBIE`# .2+h! \[.rotate\]#`senvcfg.CBIE`# .2+h! \[.rotate\]#`henvcfg.CBIE`#
/// 5+^.&gt;h! `cbe.inval` Operation
/// .^h! M-mode .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode
///
/// ! 00 ! - ! - ! Invalidate ! `Illegal Instruction` ! `Illegal Instruction` ! `Virtual Instruction` ! `Virtual Instruction`
/// ! 01 ! 00 ! 00 ! Invalidate ! Flush  ! `Illegal Instruction` ! `Virtual Instruction` ! `Virtual Instruction`
/// ! 01 ! 00 ! 01 ! Invalidate ! Flush  ! `Illegal Instruction` ! Flush ! `Virtual Instruction`
/// ! 01 ! 00 ! 11 ! Invalidate ! Flush  ! `Illegal Instruction` ! Flush ! `Virtual Instruction`
/// ! 01 ! 01 ! 00 ! Invalidate ! Flush  ! Flush ! `Virtual Instruction` ! `Virtual Instruction`
/// ! 01 ! 01 ! 01 ! Invalidate ! Flush  ! Flush ! Flush ! Flush
/// ! 01 ! 01 ! 11 ! Invalidate ! Flush  ! Flush ! Flush ! Flush
/// ! 01 ! 11 ! 00 ! Invalidate ! Flush  ! Flush ! `Virtual Instruction` ! `Virtual Instruction`
/// ! 01 ! 11 ! 01 ! Invalidate ! Flush  ! Flush ! Flush ! Flush
/// ! 01 ! 11 ! 11 ! Invalidate ! Flush  ! Flush ! Flush ! Flush
/// ! 11 ! 00 ! 00  ! Invalidate ! Invalidate  ! `Illegal Instruction` ! `Virtual Instruction` ! `Virtual Instruction`
/// ! 11 ! 00 ! 01  ! Invalidate ! Invalidate  ! `Illegal Instruction` ! Flush ! `Virtual Instruction`
/// ! 11 ! 00 ! 11  ! Invalidate ! Invalidate  ! `Illegal Instruction` ! Invalidate ! `Virtual Instruction`
/// ! 11 ! 01 ! 00 ! Invalidate ! Invalidate  ! Flush ! `Virtual Instruction` ! `Virtual Instruction`
/// ! 11 ! 01 ! 01 ! Invalidate ! Invalidate  ! Flush ! Flush ! Flush
/// ! 11 ! 01 ! 11 ! Invalidate ! Invalidate  ! Flush ! Invalidate ! Flush
/// ! 11 ! 11 ! 00 ! Invalidate ! Invalidate  ! Invalidate ! `Virtual Instruction` ! `Virtual Instruction`
/// ! 11 ! 11 ! 01 ! Invalidate ! Invalidate  ! Invalidate ! Flush ! Flush
/// ! 11 ! 11 ! 11 ! Invalidate ! Invalidate  ! Invalidate ! Invalidate ! Invalidate
/// !===
///
/// `cbo.inval` is ordered by `FENCE` instructions but not `FENCE.I` or `SFENCE.VMA`.
///
/// &lt;%- if CACHE_BLOCK_SIZE.bit_length &gt; \[PMP_GRANULARITY, PMA_GRANULARITY\].min -%&gt;
/// Both PMP and PMA access control must be the same for all bytes in the block; otherwise, `cbo.zero` has UNSPECIFIED behavior.
/// &lt;%- end -%&gt;
///
/// Invalidate operations are treated as stores for page and access permissions. If permission checks fail,
/// one of the following exceptions will occur:
///
///   &lt;%- if ext?(:H) -%&gt;
///   * `Store/AMO Guest-Page Fault` if virtual memory translation fails during G-stage translation.
///   &lt;%- end -%&gt;
///   * `Store/AMO Page Fault` if virtual memory translation fails &lt;% if ext?(:H) %&gt;when V=0 or during VS-stage translation&lt;% end %&gt;
///   * `Store/AMO Access Fault` if a PMP or PMA access check fails.
///
/// &lt;%- if CACHE_BLOCK_SIZE.bit_length &lt;= \[PMP_GRANULARITY, PMA_GRANULARITY\].min -%&gt;
/// Because cache blocks are naturally aligned and always fit in a single PMP or PMA regions, the PMP
/// and PMA access checks only need to check a single address in the line.
/// &lt;%- end -%&gt;
///
/// CBO operations never raise a misaligned address fault.
///
/// # Forms
/// Assembly: `cbo.inval "TODO"`
/// Rust: `cbo_inval(rs1)`
///
/// # Arguments
/// - `rs1` — Source register.
pub trait CboInvalEmitter<T0> {
    fn cbo_inval(&mut self, rs1: T0);
}

/// Cache Block Zero
///
/// Zeros an entire cache block
///
/// The block zeroing does not need to be atomic.
///
/// `cbo.zero` is ordered by `FENCE` instructions but not `FENCE.I` or `SFENCE.VMA`.
///
/// &lt;%- if CACHE_BLOCK_SIZE.bit_length &gt; \[PMP_GRANULARITY, PMA_GRANULARITY\].min -%&gt;
/// Both PMP and PMA access control must be the same for all bytes in the block; otherwise, `cbo.zero` has UNSPECIFIED behavior.
/// &lt;%- end -%&gt;
///
/// Clean operations are treated as stores for page and access permissions. If permission checks fail,
/// one of the following exceptions will occur:
///
///   &lt;%- if ext?(:H) -%&gt;
///   * `Store/AMO Guest-Page Fault` if virtual memory translation fails during G-stage translation.
///   &lt;%- end -%&gt;
///   * `Store/AMO Page Fault` if virtual memory translation fails &lt;% if ext?(:H) %&gt;when V=0 or during VS-stage translation&lt;% end %&gt;
///   * `Store/AMO Access Fault` if a PMP or PMA access check fails.
///
/// &lt;%- if CACHE_BLOCK_SIZE.bit_length &lt;= \[PMP_GRANULARITY, PMA_GRANULARITY\].min -%&gt;
/// Because cache blocks are naturally aligned and always fit in a single PMP or PMA regions, the PMP
/// and PMA access checks only need to check a single address in the line.
/// &lt;%- end -%&gt;
///
/// CBO operations never raise a misaligned address fault.
///
/// # Forms
/// Assembly: `cbo.zero "TODO"`
/// Rust: `cbo_zero(rs1)`
///
/// # Arguments
/// - `rs1` — Source register.
pub trait CboZeroEmitter<T0> {
    fn cbo_zero(&mut self, rs1: T0);
}

/// Carry-less multiply (low-part)
///
/// `clmul` produces the lower half of the 2*XLEN carry-less product
///
/// # Forms
/// Assembly: `clmul xd, xs1, xs2`
/// Rust: `clmul(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait ClmulEmitter<T0, T1, T2> {
    fn clmul(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// Carry-less multiply (high-part)
///
/// `clmulh` produces the upper half of the 2*XLEN carry-less product
///
/// # Forms
/// Assembly: `clmulh xd, xs1, xs2`
/// Rust: `clmulh(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait ClmulhEmitter<T0, T1, T2> {
    fn clmulh(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// Carry-less multiply (reversed)
///
/// `clmulr` produces bits 2*XLEN-2:XLEN-1 of the 2*XLEN carry-less product
///
/// # Forms
/// Assembly: `clmulr xd, xs1, xs2`
/// Rust: `clmulr(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait ClmulrEmitter<T0, T1, T2> {
    fn clmulr(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// Count leading zero bits
///
/// This instruction counts the number of 0's before the first 1,
/// starting at the most-significant bit (i.e., XLEN-1) and progressing to bit 0.
/// Accordingly, if the input is 0, the output is XLEN, and if the most-significant
/// bit of the input is a 1, the output is 0.
///
/// # Forms
/// Assembly: `clz xd, xs1`
/// Rust: `clz(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait ClzEmitter<T0, T1> {
    fn clz(&mut self, rd: T0, rs1: T1);
}

/// Count leading zero bits in word
///
/// This instruction counts the number of 0's before the first 1 starting at bit 31 and progressing to bit 0.
/// Accordingly, if the least-significant word is 0, the output is 32, and if the most-significant
/// bit of the word (_i.e._, bit 31) is a 1, the output is 0.
///
/// # Forms
/// Assembly: `clzw xd, xs1`
/// Rust: `clzw(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait ClzwEmitter<T0, T1> {
    fn clzw(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `cm.jalt` instruction.
///
/// # Forms
/// Assembly: `cm.jalt c_index`
/// Rust: `cm_jalt(index)`
///
/// # Arguments
/// - `index` — Instruction operand.
pub trait CmJaltEmitter<T0> {
    fn cm_jalt(&mut self, index: T0);
}

/// Count set bits
///
/// This instructions counts the number of 1's (i.e., set bits) in the source register.
///
/// .Software Hint
/// \[NOTE\]
/// ----
/// This operations is known as population count, popcount, sideways sum,
/// bit summation, or Hamming weight.
///
/// The GCC builtin function `__builtin_popcount (unsigned int x)` is
/// implemented by cpop on RV32 and by cpopw on RV64. The GCC builtin
/// function `__builtin_popcountl (unsigned long x)` for LP64 is
/// implemented by cpop on RV64.
/// ----
///
/// # Forms
/// Assembly: `cpop xd, xs1`
/// Rust: `cpop(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait CpopEmitter<T0, T1> {
    fn cpop(&mut self, rd: T0, rs1: T1);
}

/// Count set bits in word
///
/// This instructions counts the number of 1's (i.e., set bits) in the least-significant word of the source register.
///
/// .Software Hint
/// \[NOTE\]
/// ----
/// This operations is known as population count, popcount, sideways sum,
/// bit summation, or Hamming weight.
///
/// The GCC builtin function `__builtin_popcount (unsigned int x)` is
/// implemented by cpop on RV32 and by cpopw on RV64. The GCC builtin
/// function `__builtin_popcountl (unsigned long x)` for LP64 is
/// implemented by cpop on RV64.
/// ----
///
/// # Forms
/// Assembly: `cpopw xd, xs1`
/// Rust: `cpopw(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait CpopwEmitter<T0, T1> {
    fn cpopw(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `csrc` instruction.
///
/// # Forms
/// Assembly: `csrc rs1 csr`
/// Rust: `csrc(rs1, csr)`
///
/// # Arguments
/// - `rs1` — Source register.
/// - `csr` — Control and status register number.
pub trait CsrcEmitter<T0, T1> {
    fn csrc(&mut self, rs1: T0, csr: T1);
}

/// RISC-V `csrci` instruction.
///
/// # Forms
/// Assembly: `csrci csr zimm5`
/// Rust: `csrci(csr, zimm5)`
///
/// # Arguments
/// - `csr` — Control and status register number.
/// - `zimm5` — Immediate encoding value.
pub trait CsrciEmitter<T0, T1> {
    fn csrci(&mut self, csr: T0, zimm5: T1);
}

/// RISC-V `csrr` instruction.
///
/// # Forms
/// Assembly: `csrr rd csr`
/// Rust: `csrr(rd, csr)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `csr` — Control and status register number.
pub trait CsrrEmitter<T0, T1> {
    fn csrr(&mut self, rd: T0, csr: T1);
}

/// RISC-V `csrrc` instruction.
///
/// # Forms
/// Assembly: `csrrc xd, xs1, csr`
/// Rust: `csrrc(rd, rs1, csr)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `csr` — Control and status register number.
pub trait CsrrcEmitter<T0, T1, T2> {
    fn csrrc(&mut self, rd: T0, rs1: T1, csr: T2);
}

/// RISC-V `csrrci` instruction.
///
/// # Forms
/// Assembly: `csrrci xd, csr, imm`
/// Rust: `csrrci(rd, csr, zimm5)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `csr` — Control and status register number.
/// - `zimm5` — Immediate encoding value.
pub trait CsrrciEmitter<T0, T1, T2> {
    fn csrrci(&mut self, rd: T0, csr: T1, zimm5: T2);
}

/// Atomic Read and Set Bits in CSR
///
/// Atomically read and set bits in a CSR.
///
/// Reads the value of the CSR, zero-extends the value to `XLEN` bits,
/// and writes it to integer register `rd`. The initial value in integer
/// register `rs1` is treated as a bit mask that specifies bit positions
/// to be set in the CSR. Any bit that is high in `rs1` will cause the
/// corresponding bit to be set in the CSR, if that CSR bit is writable.
/// Other bits in the CSR are not explicitly written.
///
/// # Forms
/// Assembly: `csrrs xd, xs1, csr`
/// Rust: `csrrs(rd, rs1, csr)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `csr` — Control and status register number.
pub trait CsrrsEmitter<T0, T1, T2> {
    fn csrrs(&mut self, rd: T0, rs1: T1, csr: T2);
}

/// RISC-V `csrrsi` instruction.
///
/// # Forms
/// Assembly: `csrrsi xd, csr, imm`
/// Rust: `csrrsi(rd, csr, zimm5)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `csr` — Control and status register number.
/// - `zimm5` — Immediate encoding value.
pub trait CsrrsiEmitter<T0, T1, T2> {
    fn csrrsi(&mut self, rd: T0, csr: T1, zimm5: T2);
}

/// Atomic Read/Write CSR
///
/// Atomically swap values in the CSRs and integer registers.
///
/// Read the old value of the CSR, zero-extends the value to `XLEN` bits,
/// and then write it to integer register rd.
/// The initial value in rs1 is written to the CSR.
/// If `rd=x0`, then the instruction shall not read the CSR and shall not
/// cause any of the side effects that might occur on a CSR read.
///
/// # Forms
/// Assembly: `csrrw xd, xs1, csr`
/// Rust: `csrrw(rd, rs1, csr)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `csr` — Control and status register number.
pub trait CsrrwEmitter<T0, T1, T2> {
    fn csrrw(&mut self, rd: T0, rs1: T1, csr: T2);
}

/// Atomic Read/Write CSR Immediate
///
/// Atomically write CSR using a 5-bit immediate, and load the previous value into 'rd'.
///
/// Read the old value of the CSR, zero-extends the value to `XLEN` bits,
/// and then write it to integer register rd.
/// The 5-bit uimm field is zero-extended and written to the CSR.
/// If `rd=x0`, then the instruction shall not read the CSR and shall not
/// cause any of the side effects that might occur on a CSR read.
///
/// # Forms
/// Assembly: `csrrwi xd, zimm, csr`
/// Rust: `csrrwi(rd, csr, zimm5)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `csr` — Control and status register number.
/// - `zimm5` — Immediate encoding value.
pub trait CsrrwiEmitter<T0, T1, T2> {
    fn csrrwi(&mut self, rd: T0, csr: T1, zimm5: T2);
}

/// RISC-V `csrs` instruction.
///
/// # Forms
/// Assembly: `csrs rs1 csr`
/// Rust: `csrs(rs1, csr)`
///
/// # Arguments
/// - `rs1` — Source register.
/// - `csr` — Control and status register number.
pub trait CsrsEmitter<T0, T1> {
    fn csrs(&mut self, rs1: T0, csr: T1);
}

/// RISC-V `csrsi` instruction.
///
/// # Forms
/// Assembly: `csrsi csr zimm5`
/// Rust: `csrsi(csr, zimm5)`
///
/// # Arguments
/// - `csr` — Control and status register number.
/// - `zimm5` — Immediate encoding value.
pub trait CsrsiEmitter<T0, T1> {
    fn csrsi(&mut self, csr: T0, zimm5: T1);
}

/// RISC-V `csrw` instruction.
///
/// # Forms
/// Assembly: `csrw rs1 csr`
/// Rust: `csrw(rs1, csr)`
///
/// # Arguments
/// - `rs1` — Source register.
/// - `csr` — Control and status register number.
pub trait CsrwEmitter<T0, T1> {
    fn csrw(&mut self, rs1: T0, csr: T1);
}

/// RISC-V `csrwi` instruction.
///
/// # Forms
/// Assembly: `csrwi csr zimm5`
/// Rust: `csrwi(csr, zimm5)`
///
/// # Arguments
/// - `csr` — Control and status register number.
/// - `zimm5` — Immediate encoding value.
pub trait CsrwiEmitter<T0, T1> {
    fn csrwi(&mut self, csr: T0, zimm5: T1);
}

/// Count trailing zero bits
///
/// This instruction counts the number of 0's before the first 1,
/// starting at the least-significant bit (i.e., 0) and progressing
/// to the most-significant bit (i.e., XLEN-1). Accordingly, if the
/// input is 0, the output is XLEN, and if the least-significant bit
/// of the input is a 1, the output is 0.
///
/// # Forms
/// Assembly: `ctz xd, xs1`
/// Rust: `ctz(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait CtzEmitter<T0, T1> {
    fn ctz(&mut self, rd: T0, rs1: T1);
}

/// Count trailing zero bits in word
///
/// This instruction counts the number of 0's before the first 1,
/// starting at the least-significant bit (i.e., 0) and progressing
/// to the most-significant bit of the least-significant word (i.e., 31). Accordingly, if the
/// least-significant word is 0, the output is 32, and if the least-significant bit
/// of the input is a 1, the output is 0.
///
/// # Forms
/// Assembly: `ctzw xd, xs1`
/// Rust: `ctzw(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait CtzwEmitter<T0, T1> {
    fn ctzw(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `czero.eqz` instruction.
///
/// # Forms
/// Assembly: `czero.eqz xd, xs1, xs2`
/// Rust: `czero_eqz(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait CzeroEqzEmitter<T0, T1, T2> {
    fn czero_eqz(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `czero.nez` instruction.
///
/// # Forms
/// Assembly: `czero.nez xd, xs1, xs2`
/// Rust: `czero_nez(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait CzeroNezEmitter<T0, T1, T2> {
    fn czero_nez(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// Signed division
///
/// Divide rs1 by rs2, and store the result in rd. The remainder is discarded.
///
/// Division by zero will put -1 into rd.
///
/// Division resulting in signed overflow (when most negative number is divided by -1)
/// will put the most negative number into rd;
///
/// # Forms
/// Assembly: `div xd, xs1, xs2`
/// Rust: `div(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait DivEmitter<T0, T1, T2> {
    fn div(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// Unsigned division
///
/// Divide unsigned values in rs1 by rs2, and store the result in rd.
///
/// The remainder is discarded.
///
/// If the value in rs2 is zero, rd gets the largest unsigned value.
///
/// # Forms
/// Assembly: `divu xd, xs1, xs2`
/// Rust: `divu(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait DivuEmitter<T0, T1, T2> {
    fn divu(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// Unsigned 32-bit division
///
/// Divide the unsigned 32-bit values in rs1 and rs2, and store the sign-extended result in rd.
///
/// The remainder is discarded.
///
/// If the value in rs2 is zero, rd is written with all 1s.
///
/// # Forms
/// Assembly: `divuw xd, xs1, xs2`
/// Rust: `divuw(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait DivuwEmitter<T0, T1, T2> {
    fn divuw(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// Signed 32-bit division
///
/// Divide the lower 32-bits of register rs1 by the lower 32-bits of register rs2,
/// and store the sign-extended result in rd.
///
/// The remainder is discarded.
///
/// Division by zero will put -1 into rd.
///
/// Division resulting in signed overflow (when most negative number is divided by -1)
/// will put the most negative number into rd;
///
/// # Forms
/// Assembly: `divw xd, xs1, xs2`
/// Rust: `divw(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait DivwEmitter<T0, T1, T2> {
    fn divw(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `dret` instruction.
///
/// # Forms
/// Assembly: `dret dret`
/// Rust: `dret()`
///
/// # Arguments
pub trait DretEmitter {
    fn dret(&mut self);
}

/// Breakpoint exception
///
/// The EBREAK instruction is used by debuggers to cause control to be transferred back to
/// a debugging environment. Unless overridden by an external debug environment,
/// EBREAK raises a breakpoint exception and performs no other operation.
///
/// \[NOTE\]
/// As described in the `C` Standard Extension for Compressed Instructions, the `c.ebreak`
/// instruction performs the same operation as the EBREAK instruction.
///
/// EBREAK causes the receiving privilege mode's epc register to be set to the address of
/// the EBREAK instruction itself, not the address of the following instruction.
/// As EBREAK causes a synchronous exception, it is not considered to retire,
/// and should not increment the `minstret` CSR.
///
/// # Forms
/// Assembly: `ebreak ""`
/// Rust: `ebreak()`
///
/// # Arguments
pub trait EbreakEmitter {
    fn ebreak(&mut self);
}

/// Environment call
///
/// The ECALL instruction is used to make a request to the supporting execution environment.
/// When executed in U-mode, S-mode, or M-mode, it generates an environment-call-from-U-mode
/// exception, environment-call-from-S-mode exception, or environment-call-from-M-mode
/// exception, respectively, and performs no other operation.
///
/// \[NOTE\]
/// ECALL generates a different exception for each originating privilege mode so that
/// environment call exceptions can be selectively delegated.
/// A typical use case for Unix-like operating systems is to delegate to S-mode
/// the environment-call-from-U-mode exception but not the others.
///
/// ECALL causes the receiving privilege mode's epc register to be set to the address of
/// the ECALL instruction itself, not the address of the following instruction.
/// As ECALL causes a synchronous exception, it is not considered to retire,
/// and should not increment the `minstret` CSR.
///
/// # Forms
/// Assembly: `ecall ""`
/// Rust: `ecall()`
///
/// # Arguments
pub trait EcallEmitter {
    fn ecall(&mut self);
}

/// RISC-V `fabs.d` instruction.
///
/// # Forms
/// Assembly: `fabs.d rd rs1 rs2_eq_rs1`
/// Rust: `fabs_d(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait FabsDEmitter<T0, T1, T2> {
    fn fabs_d(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `fabs.h` instruction.
///
/// # Forms
/// Assembly: `fabs.h rd rs1 rs2_eq_rs1`
/// Rust: `fabs_h(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait FabsHEmitter<T0, T1, T2> {
    fn fabs_h(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `fabs.q` instruction.
///
/// # Forms
/// Assembly: `fabs.q rd rs1 rs2_eq_rs1`
/// Rust: `fabs_q(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait FabsQEmitter<T0, T1, T2> {
    fn fabs_q(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `fabs.s` instruction.
///
/// # Forms
/// Assembly: `fabs.s rd rs1 rs2_eq_rs1`
/// Rust: `fabs_s(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait FabsSEmitter<T0, T1, T2> {
    fn fabs_s(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `fadd.d` instruction.
///
/// # Forms
/// Assembly: `fadd.d xd, xs1, xs2, rm`
/// Rust: `fadd_d(rd, rs1, rs2, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
/// - `rm` — Rounding mode.
pub trait FaddDEmitter<T0, T1, T2, T3> {
    fn fadd_d(&mut self, rd: T0, rs1: T1, rs2: T2, rm: T3);
}

/// RISC-V `fadd.h` instruction.
///
/// # Forms
/// Assembly: `fadd.h xd, xs1, xs2, rm`
/// Rust: `fadd_h(rd, rs1, rs2, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
/// - `rm` — Rounding mode.
pub trait FaddHEmitter<T0, T1, T2, T3> {
    fn fadd_h(&mut self, rd: T0, rs1: T1, rs2: T2, rm: T3);
}

/// RISC-V `fadd.q` instruction.
///
/// # Forms
/// Assembly: `fadd.q qd, qs1, qs2, rm`
/// Rust: `fadd_q(rd, rs1, rs2, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
/// - `rm` — Rounding mode.
pub trait FaddQEmitter<T0, T1, T2, T3> {
    fn fadd_q(&mut self, rd: T0, rs1: T1, rs2: T2, rm: T3);
}

/// Single-precision floating-point addition
///
/// Do the single-precision floating-point addition of fs1 and fs2 and store the result in fd.
/// rm is the dynamic Rounding Mode.
///
/// # Forms
/// Assembly: `fadd.s fd, fs1, fs2, rm`
/// Rust: `fadd_s(rd, rs1, rs2, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
/// - `rm` — Rounding mode.
pub trait FaddSEmitter<T0, T1, T2, T3> {
    fn fadd_s(&mut self, rd: T0, rs1: T1, rs2: T2, rm: T3);
}

/// RISC-V `fclass.d` instruction.
///
/// # Forms
/// Assembly: `fclass.d xd, xs1`
/// Rust: `fclass_d(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait FclassDEmitter<T0, T1> {
    fn fclass_d(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `fclass.h` instruction.
///
/// # Forms
/// Assembly: `fclass.h xd, xs1`
/// Rust: `fclass_h(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait FclassHEmitter<T0, T1> {
    fn fclass_h(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `fclass.q` instruction.
///
/// # Forms
/// Assembly: `fclass.q xd, qs1`
/// Rust: `fclass_q(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait FclassQEmitter<T0, T1> {
    fn fclass_q(&mut self, rd: T0, rs1: T1);
}

/// Single-precision floating-point classify.
///
/// The `fclass.s` instruction examines the value in floating-point register
/// _fs1_ and writes to integer register _rd_ a 10-bit mask that indicates
/// the class of the floating-point number.
/// The format of the mask is described in the table below.
/// The corresponding bit in _rd_ will be set if the property is true and
/// clear otherwise.
/// All other bits in _rd_ are cleared.
/// Note that exactly one bit in rd will be set.
/// `fclass.s` does not set the floating-point exception flags.
///
/// .Format of result of `fclass` instruction.
/// \[%autowidth,float="center",align="center",cols="^,&lt;",options="header",\]
/// |===
/// |_rd_ bit |Meaning
/// |0 |_rs1_ is latexmath:\[$-\infty$\].
/// |1 |_rs1_ is a negative normal number.
/// |2 |_rs1_ is a negative subnormal number.
/// |3 |_rs1_ is latexmath:\[$-0$\].
/// |4 |_rs1_ is latexmath:\[$+0$\].
/// |5 |_rs1_ is a positive subnormal number.
/// |6 |_rs1_ is a positive normal number.
/// |7 |_rs1_ is latexmath:\[$+\infty$\].
/// |8 |_rs1_ is a signaling NaN.
/// |9 |_rs1_ is a quiet NaN.
/// |===
///
/// # Forms
/// Assembly: `fclass.s xd, fs1`
/// Rust: `fclass_s(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait FclassSEmitter<T0, T1> {
    fn fclass_s(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `fcvt.bf16.s` instruction.
///
/// # Forms
/// Assembly: `fcvt.bf16.s xd, xs1, rm`
/// Rust: `fcvt_bf16_s(rd, rs1, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rm` — Rounding mode.
pub trait FcvtBf16SEmitter<T0, T1, T2> {
    fn fcvt_bf16_s(&mut self, rd: T0, rs1: T1, rm: T2);
}

/// RISC-V `fcvt.d.h` instruction.
///
/// # Forms
/// Assembly: `fcvt.d.h xd, xs1, rm`
/// Rust: `fcvt_d_h(rd, rs1, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rm` — Rounding mode.
pub trait FcvtDHEmitter<T0, T1, T2> {
    fn fcvt_d_h(&mut self, rd: T0, rs1: T1, rm: T2);
}

/// RISC-V `fcvt.d.l` instruction.
///
/// # Forms
/// Assembly: `fcvt.d.l xd, xs1, rm`
/// Rust: `fcvt_d_l(rd, rs1, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rm` — Rounding mode.
pub trait FcvtDLEmitter<T0, T1, T2> {
    fn fcvt_d_l(&mut self, rd: T0, rs1: T1, rm: T2);
}

/// RISC-V `fcvt.d.lu` instruction.
///
/// # Forms
/// Assembly: `fcvt.d.lu xd, xs1, rm`
/// Rust: `fcvt_d_lu(rd, rs1, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rm` — Rounding mode.
pub trait FcvtDLuEmitter<T0, T1, T2> {
    fn fcvt_d_lu(&mut self, rd: T0, rs1: T1, rm: T2);
}

/// RISC-V `fcvt.d.q` instruction.
///
/// # Forms
/// Assembly: `fcvt.d.q xd, qs1, rm`
/// Rust: `fcvt_d_q(rd, rs1, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rm` — Rounding mode.
pub trait FcvtDQEmitter<T0, T1, T2> {
    fn fcvt_d_q(&mut self, rd: T0, rs1: T1, rm: T2);
}

/// RISC-V `fcvt.d.s` instruction.
///
/// # Forms
/// Assembly: `fcvt.d.s xd, xs1, rm`
/// Rust: `fcvt_d_s(rd, rs1, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rm` — Rounding mode.
pub trait FcvtDSEmitter<T0, T1, T2> {
    fn fcvt_d_s(&mut self, rd: T0, rs1: T1, rm: T2);
}

/// RISC-V `fcvt.d.w` instruction.
///
/// # Forms
/// Assembly: `fcvt.d.w xd, xs1, rm`
/// Rust: `fcvt_d_w(rd, rs1, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rm` — Rounding mode.
pub trait FcvtDWEmitter<T0, T1, T2> {
    fn fcvt_d_w(&mut self, rd: T0, rs1: T1, rm: T2);
}

/// RISC-V `fcvt.d.wu` instruction.
///
/// # Forms
/// Assembly: `fcvt.d.wu xd, xs1, rm`
/// Rust: `fcvt_d_wu(rd, rs1, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rm` — Rounding mode.
pub trait FcvtDWuEmitter<T0, T1, T2> {
    fn fcvt_d_wu(&mut self, rd: T0, rs1: T1, rm: T2);
}

/// RISC-V `fcvt.h.d` instruction.
///
/// # Forms
/// Assembly: `fcvt.h.d xd, xs1, rm`
/// Rust: `fcvt_h_d(rd, rs1, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rm` — Rounding mode.
pub trait FcvtHDEmitter<T0, T1, T2> {
    fn fcvt_h_d(&mut self, rd: T0, rs1: T1, rm: T2);
}

/// RISC-V `fcvt.h.l` instruction.
///
/// # Forms
/// Assembly: `fcvt.h.l xd, xs1, rm`
/// Rust: `fcvt_h_l(rd, rs1, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rm` — Rounding mode.
pub trait FcvtHLEmitter<T0, T1, T2> {
    fn fcvt_h_l(&mut self, rd: T0, rs1: T1, rm: T2);
}

/// RISC-V `fcvt.h.lu` instruction.
///
/// # Forms
/// Assembly: `fcvt.h.lu xd, xs1, rm`
/// Rust: `fcvt_h_lu(rd, rs1, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rm` — Rounding mode.
pub trait FcvtHLuEmitter<T0, T1, T2> {
    fn fcvt_h_lu(&mut self, rd: T0, rs1: T1, rm: T2);
}

/// RISC-V `fcvt.h.q` instruction.
///
/// # Forms
/// Assembly: `fcvt.h.q xd, qs1, rm`
/// Rust: `fcvt_h_q(rd, rs1, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rm` — Rounding mode.
pub trait FcvtHQEmitter<T0, T1, T2> {
    fn fcvt_h_q(&mut self, rd: T0, rs1: T1, rm: T2);
}

/// Convert half-precision float to a single-precision float
///
/// Converts a half-precision number in floating-point register _fs1_ into a single-precision floating-point number in
/// floating-point register _fd_.
///
/// `fcvt.h.s` rounds according to the _rm_ field.
///
/// All floating-point conversion instructions set the Inexact exception flag if the rounded
/// result differs from the operand value and the Invalid exception flag is not set.
///
/// # Forms
/// Assembly: `fcvt.h.s fd, xs1`
/// Rust: `fcvt_h_s(rd, rs1, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rm` — Rounding mode.
pub trait FcvtHSEmitter<T0, T1, T2> {
    fn fcvt_h_s(&mut self, rd: T0, rs1: T1, rm: T2);
}

/// RISC-V `fcvt.h.w` instruction.
///
/// # Forms
/// Assembly: `fcvt.h.w xd, xs1, rm`
/// Rust: `fcvt_h_w(rd, rs1, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rm` — Rounding mode.
pub trait FcvtHWEmitter<T0, T1, T2> {
    fn fcvt_h_w(&mut self, rd: T0, rs1: T1, rm: T2);
}

/// RISC-V `fcvt.h.wu` instruction.
///
/// # Forms
/// Assembly: `fcvt.h.wu xd, xs1, rm`
/// Rust: `fcvt_h_wu(rd, rs1, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rm` — Rounding mode.
pub trait FcvtHWuEmitter<T0, T1, T2> {
    fn fcvt_h_wu(&mut self, rd: T0, rs1: T1, rm: T2);
}

/// RISC-V `fcvt.l.d` instruction.
///
/// # Forms
/// Assembly: `fcvt.l.d xd, xs1, rm`
/// Rust: `fcvt_l_d(rd, rs1, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rm` — Rounding mode.
pub trait FcvtLDEmitter<T0, T1, T2> {
    fn fcvt_l_d(&mut self, rd: T0, rs1: T1, rm: T2);
}

/// RISC-V `fcvt.l.h` instruction.
///
/// # Forms
/// Assembly: `fcvt.l.h xd, xs1, rm`
/// Rust: `fcvt_l_h(rd, rs1, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rm` — Rounding mode.
pub trait FcvtLHEmitter<T0, T1, T2> {
    fn fcvt_l_h(&mut self, rd: T0, rs1: T1, rm: T2);
}

/// RISC-V `fcvt.l.q` instruction.
///
/// # Forms
/// Assembly: `fcvt.l.q xd, qs1, rm`
/// Rust: `fcvt_l_q(rd, rs1, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rm` — Rounding mode.
pub trait FcvtLQEmitter<T0, T1, T2> {
    fn fcvt_l_q(&mut self, rd: T0, rs1: T1, rm: T2);
}

/// RISC-V `fcvt.l.s` instruction.
///
/// # Forms
/// Assembly: `fcvt.l.s xd, fs1, rm`
/// Rust: `fcvt_l_s(rd, rs1, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rm` — Rounding mode.
pub trait FcvtLSEmitter<T0, T1, T2> {
    fn fcvt_l_s(&mut self, rd: T0, rs1: T1, rm: T2);
}

/// RISC-V `fcvt.lu.d` instruction.
///
/// # Forms
/// Assembly: `fcvt.lu.d xd, xs1, rm`
/// Rust: `fcvt_lu_d(rd, rs1, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rm` — Rounding mode.
pub trait FcvtLuDEmitter<T0, T1, T2> {
    fn fcvt_lu_d(&mut self, rd: T0, rs1: T1, rm: T2);
}

/// RISC-V `fcvt.lu.h` instruction.
///
/// # Forms
/// Assembly: `fcvt.lu.h xd, xs1, rm`
/// Rust: `fcvt_lu_h(rd, rs1, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rm` — Rounding mode.
pub trait FcvtLuHEmitter<T0, T1, T2> {
    fn fcvt_lu_h(&mut self, rd: T0, rs1: T1, rm: T2);
}

/// RISC-V `fcvt.lu.q` instruction.
///
/// # Forms
/// Assembly: `fcvt.lu.q qd, hs1, rm`
/// Rust: `fcvt_lu_q(rd, rs1, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rm` — Rounding mode.
pub trait FcvtLuQEmitter<T0, T1, T2> {
    fn fcvt_lu_q(&mut self, rd: T0, rs1: T1, rm: T2);
}

/// RISC-V `fcvt.lu.s` instruction.
///
/// # Forms
/// Assembly: `fcvt.lu.s xd, fs1, rm`
/// Rust: `fcvt_lu_s(rd, rs1, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rm` — Rounding mode.
pub trait FcvtLuSEmitter<T0, T1, T2> {
    fn fcvt_lu_s(&mut self, rd: T0, rs1: T1, rm: T2);
}

/// RISC-V `fcvt.q.d` instruction.
///
/// # Forms
/// Assembly: `fcvt.q.d dd, fs1, rm`
/// Rust: `fcvt_q_d(rd, rs1, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rm` — Rounding mode.
pub trait FcvtQDEmitter<T0, T1, T2> {
    fn fcvt_q_d(&mut self, rd: T0, rs1: T1, rm: T2);
}

/// RISC-V `fcvt.q.h` instruction.
///
/// # Forms
/// Assembly: `fcvt.q.h hd, qs1, rm`
/// Rust: `fcvt_q_h(rd, rs1, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rm` — Rounding mode.
pub trait FcvtQHEmitter<T0, T1, T2> {
    fn fcvt_q_h(&mut self, rd: T0, rs1: T1, rm: T2);
}

/// RISC-V `fcvt.q.l` instruction.
///
/// # Forms
/// Assembly: `fcvt.q.l qd, xs1, rm`
/// Rust: `fcvt_q_l(rd, rs1, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rm` — Rounding mode.
pub trait FcvtQLEmitter<T0, T1, T2> {
    fn fcvt_q_l(&mut self, rd: T0, rs1: T1, rm: T2);
}

/// RISC-V `fcvt.q.lu` instruction.
///
/// # Forms
/// Assembly: `fcvt.q.lu qd, xs1, rm`
/// Rust: `fcvt_q_lu(rd, rs1, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rm` — Rounding mode.
pub trait FcvtQLuEmitter<T0, T1, T2> {
    fn fcvt_q_lu(&mut self, rd: T0, rs1: T1, rm: T2);
}

/// RISC-V `fcvt.q.s` instruction.
///
/// # Forms
/// Assembly: `fcvt.q.s qd, fs1, rm`
/// Rust: `fcvt_q_s(rd, rs1, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rm` — Rounding mode.
pub trait FcvtQSEmitter<T0, T1, T2> {
    fn fcvt_q_s(&mut self, rd: T0, rs1: T1, rm: T2);
}

/// RISC-V `fcvt.q.w` instruction.
///
/// # Forms
/// Assembly: `fcvt.q.w fd, xs1, rm`
/// Rust: `fcvt_q_w(rd, rs1, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rm` — Rounding mode.
pub trait FcvtQWEmitter<T0, T1, T2> {
    fn fcvt_q_w(&mut self, rd: T0, rs1: T1, rm: T2);
}

/// RISC-V `fcvt.q.wu` instruction.
///
/// # Forms
/// Assembly: `fcvt.q.wu qd, xs1, rm`
/// Rust: `fcvt_q_wu(rd, rs1, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rm` — Rounding mode.
pub trait FcvtQWuEmitter<T0, T1, T2> {
    fn fcvt_q_wu(&mut self, rd: T0, rs1: T1, rm: T2);
}

/// RISC-V `fcvt.s.bf16` instruction.
///
/// # Forms
/// Assembly: `fcvt.s.bf16 xd, xs1, rm`
/// Rust: `fcvt_s_bf16(rd, rs1, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rm` — Rounding mode.
pub trait FcvtSBf16Emitter<T0, T1, T2> {
    fn fcvt_s_bf16(&mut self, rd: T0, rs1: T1, rm: T2);
}

/// RISC-V `fcvt.s.d` instruction.
///
/// # Forms
/// Assembly: `fcvt.s.d xd, xs1, rm`
/// Rust: `fcvt_s_d(rd, rs1, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rm` — Rounding mode.
pub trait FcvtSDEmitter<T0, T1, T2> {
    fn fcvt_s_d(&mut self, rd: T0, rs1: T1, rm: T2);
}

/// Convert single-precision float to a half-precision float
///
/// Converts a single-precision number in floating-point register _fs1_ into a half-precision floating-point number in
/// floating-point register _fd_.
///
/// `fcvt.s.h` will never round, and so the 'rm' field is effectively ignored.
///
/// # Forms
/// Assembly: `fcvt.s.h fd, xs1`
/// Rust: `fcvt_s_h(rd, rs1, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rm` — Rounding mode.
pub trait FcvtSHEmitter<T0, T1, T2> {
    fn fcvt_s_h(&mut self, rd: T0, rs1: T1, rm: T2);
}

/// RISC-V `fcvt.s.l` instruction.
///
/// # Forms
/// Assembly: `fcvt.s.l fd, xs1, rm`
/// Rust: `fcvt_s_l(rd, rs1, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rm` — Rounding mode.
pub trait FcvtSLEmitter<T0, T1, T2> {
    fn fcvt_s_l(&mut self, rd: T0, rs1: T1, rm: T2);
}

/// RISC-V `fcvt.s.lu` instruction.
///
/// # Forms
/// Assembly: `fcvt.s.lu fd, xs1, rm`
/// Rust: `fcvt_s_lu(rd, rs1, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rm` — Rounding mode.
pub trait FcvtSLuEmitter<T0, T1, T2> {
    fn fcvt_s_lu(&mut self, rd: T0, rs1: T1, rm: T2);
}

/// RISC-V `fcvt.s.q` instruction.
///
/// # Forms
/// Assembly: `fcvt.s.q fd, qs1, rm`
/// Rust: `fcvt_s_q(rd, rs1, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rm` — Rounding mode.
pub trait FcvtSQEmitter<T0, T1, T2> {
    fn fcvt_s_q(&mut self, rd: T0, rs1: T1, rm: T2);
}

/// Convert signed 32-bit integer to single-precision float
///
/// Converts a 32-bit signed integer in integer register _rs1_ into a floating-point number in
/// floating-point register _fd_.
///
/// All floating-point to integer and integer to floating-point conversion instructions round
/// according to the _rm_ field.
/// A floating-point register can be initialized to floating-point positive zero using
/// `fcvt.s.w rd, x0`, which will never set any exception flags.
///
/// All floating-point conversion instructions set the Inexact exception flag if the rounded
/// result differs from the operand value and the Invalid exception flag is not set.
///
/// # Forms
/// Assembly: `fcvt.s.w fd, xs1`
/// Rust: `fcvt_s_w(rd, rs1, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rm` — Rounding mode.
pub trait FcvtSWEmitter<T0, T1, T2> {
    fn fcvt_s_w(&mut self, rd: T0, rs1: T1, rm: T2);
}

/// RISC-V `fcvt.s.wu` instruction.
///
/// # Forms
/// Assembly: `fcvt.s.wu fd, xs1, rm`
/// Rust: `fcvt_s_wu(rd, rs1, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rm` — Rounding mode.
pub trait FcvtSWuEmitter<T0, T1, T2> {
    fn fcvt_s_wu(&mut self, rd: T0, rs1: T1, rm: T2);
}

/// RISC-V `fcvt.w.d` instruction.
///
/// # Forms
/// Assembly: `fcvt.w.d xd, xs1, rm`
/// Rust: `fcvt_w_d(rd, rs1, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rm` — Rounding mode.
pub trait FcvtWDEmitter<T0, T1, T2> {
    fn fcvt_w_d(&mut self, rd: T0, rs1: T1, rm: T2);
}

/// RISC-V `fcvt.w.h` instruction.
///
/// # Forms
/// Assembly: `fcvt.w.h xd, xs1, rm`
/// Rust: `fcvt_w_h(rd, rs1, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rm` — Rounding mode.
pub trait FcvtWHEmitter<T0, T1, T2> {
    fn fcvt_w_h(&mut self, rd: T0, rs1: T1, rm: T2);
}

/// RISC-V `fcvt.w.q` instruction.
///
/// # Forms
/// Assembly: `fcvt.w.q xd, qs1, rm`
/// Rust: `fcvt_w_q(rd, rs1, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rm` — Rounding mode.
pub trait FcvtWQEmitter<T0, T1, T2> {
    fn fcvt_w_q(&mut self, rd: T0, rs1: T1, rm: T2);
}

/// Convert single-precision float to integer word to signed 32-bit integer.
///
/// Converts a floating-point number in floating-point register _fs1_ to a signed 32-bit integer indicates
/// integer register _rd_.
///
/// For XLEN &gt;32, `fcvt.w.s` sign-extends the 32-bit result to the destination register width.
///
/// If the rounded result is not representable as a 32-bit signed integer, it is clipped to the
/// nearest value and the invalid flag is set.
///
/// The range of valid inputs and behavior for invalid inputs are:
///
/// \[separator="!"\]
/// !===
/// ! ! Value
///
/// h! Minimum valid input (after rounding) ! `-2^31`
/// h! Maximum valid input (after rounding) ! `2^31 - 1`
/// h! Output for out-of-range negative input ! `-2^31`
/// h! Output for `-&infin;` ! `-2^31`
/// h! Output for out-of-range positive input ! `2^31 - 1`
/// h! Output for `+&infin;` for `NaN` ! `2^31 - 1`
/// !===
///
/// All floating-point to integer and integer to floating-point conversion instructions round
/// according to the _rm_ field.
/// A floating-point register can be initialized to floating-point positive zero using
/// `fcvt.s.w rd, x0`, which will never set any exception flags.
///
/// All floating-point conversion instructions set the Inexact exception flag if the rounded
/// result differs from the operand value and the Invalid exception flag is not set.
///
/// # Forms
/// Assembly: `fcvt.w.s xd, fs1`
/// Rust: `fcvt_w_s(rd, rs1, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rm` — Rounding mode.
pub trait FcvtWSEmitter<T0, T1, T2> {
    fn fcvt_w_s(&mut self, rd: T0, rs1: T1, rm: T2);
}

/// RISC-V `fcvt.wu.d` instruction.
///
/// # Forms
/// Assembly: `fcvt.wu.d xd, xs1, rm`
/// Rust: `fcvt_wu_d(rd, rs1, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rm` — Rounding mode.
pub trait FcvtWuDEmitter<T0, T1, T2> {
    fn fcvt_wu_d(&mut self, rd: T0, rs1: T1, rm: T2);
}

/// RISC-V `fcvt.wu.h` instruction.
///
/// # Forms
/// Assembly: `fcvt.wu.h xd, xs1, rm`
/// Rust: `fcvt_wu_h(rd, rs1, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rm` — Rounding mode.
pub trait FcvtWuHEmitter<T0, T1, T2> {
    fn fcvt_wu_h(&mut self, rd: T0, rs1: T1, rm: T2);
}

/// RISC-V `fcvt.wu.q` instruction.
///
/// # Forms
/// Assembly: `fcvt.wu.q xd, xs1, rm`
/// Rust: `fcvt_wu_q(rd, rs1, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rm` — Rounding mode.
pub trait FcvtWuQEmitter<T0, T1, T2> {
    fn fcvt_wu_q(&mut self, rd: T0, rs1: T1, rm: T2);
}

/// RISC-V `fcvt.wu.s` instruction.
///
/// # Forms
/// Assembly: `fcvt.wu.s xd, fs1, rm`
/// Rust: `fcvt_wu_s(rd, rs1, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rm` — Rounding mode.
pub trait FcvtWuSEmitter<T0, T1, T2> {
    fn fcvt_wu_s(&mut self, rd: T0, rs1: T1, rm: T2);
}

/// RISC-V `fcvtmod.w.d` instruction.
///
/// # Forms
/// Assembly: `fcvtmod.w.d xd, xs1`
/// Rust: `fcvtmod_w_d(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait FcvtmodWDEmitter<T0, T1> {
    fn fcvtmod_w_d(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `fdiv.d` instruction.
///
/// # Forms
/// Assembly: `fdiv.d xd, xs1, xs2, rm`
/// Rust: `fdiv_d(rd, rs1, rs2, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
/// - `rm` — Rounding mode.
pub trait FdivDEmitter<T0, T1, T2, T3> {
    fn fdiv_d(&mut self, rd: T0, rs1: T1, rs2: T2, rm: T3);
}

/// RISC-V `fdiv.h` instruction.
///
/// # Forms
/// Assembly: `fdiv.h xd, xs1, xs2, rm`
/// Rust: `fdiv_h(rd, rs1, rs2, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
/// - `rm` — Rounding mode.
pub trait FdivHEmitter<T0, T1, T2, T3> {
    fn fdiv_h(&mut self, rd: T0, rs1: T1, rs2: T2, rm: T3);
}

/// RISC-V `fdiv.q` instruction.
///
/// # Forms
/// Assembly: `fdiv.q qd, qs1, qs2, rm`
/// Rust: `fdiv_q(rd, rs1, rs2, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
/// - `rm` — Rounding mode.
pub trait FdivQEmitter<T0, T1, T2, T3> {
    fn fdiv_q(&mut self, rd: T0, rs1: T1, rs2: T2, rm: T3);
}

/// RISC-V `fdiv.s` instruction.
///
/// # Forms
/// Assembly: `fdiv.s fd, fs1, fs2, rm`
/// Rust: `fdiv_s(rd, rs1, rs2, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
/// - `rm` — Rounding mode.
pub trait FdivSEmitter<T0, T1, T2, T3> {
    fn fdiv_s(&mut self, rd: T0, rs1: T1, rs2: T2, rm: T3);
}

/// Memory ordering fence
///
/// Orders memory operations.
///
/// The `fence` instruction is used to order device I/O and memory accesses as
/// viewed by other RISC-V harts and external devices or coprocessors. Any
/// combination of device input (I), device output (O), memory reads \(R),
/// and memory writes (W) may be ordered with respect to any combination of
/// the same. Informally, no other RISC-V hart or external device can
/// observe any operation in the _successor_ set following a `fence` before
/// any operation in the _predecessor_ set preceding the `fence`.
///
/// The predecessor and successor fields have the same format to specify operation types:
///
/// \[%autowidth\]
/// |===
/// 4+| `pred` 4+| `succ`
///
/// | 27 | 26 |25 | 24 | 23 | 22 | 21| 20
/// | PI | PO |PR | PW | SI | SO |SR | SW
/// |===
///
/// \[%autowidth,align="center",cols="^1,^1,&lt;3",options="header"\]
/// .Fence mode encoding
/// |===
/// |_fm_ field |Mnemonic |Meaning
/// |0000 |_none_ |Normal Fence
/// |1000 |TSO |With `FENCE RW,RW`: exclude write-to-read ordering; otherwise: _Reserved for future use._
/// 2+|_other_ |_Reserved for future use._
/// |===
///
/// When the mode field _fm_ is `0001` and both the predecessor and successor sets are 'RW',
/// then the instruction acts as a special-case `fence.tso`. `fence.tso` orders all load operations
/// in its predecessor set before all memory operations in its successor set, and all store operations
/// in its predecessor set before all store operations in its successor set. This leaves non-AMO store
/// operations in the 'fence.tso's predecessor set unordered with non-AMO loads in its successor set.
///
/// When mode field _fm_ is not `0001`, or when mode field _fm_ is `0001` but the _pred_ and
/// _succ_ fields are not both 'RW' (0x3), then the fence acts as a baseline fence (_e.g._, _fm_ is
/// effectively `0000`). This is unaffected by the FIOM bits, described below (implicit promotion does
/// not change how `fence.tso` is decoded).
///
/// The `rs1` and `rd` fields are unused and ignored.
///
/// In modes other than M-mode, `fence` is further affected by `menvcfg.FIOM`,
/// `senvcfg.FIOM`&lt;% if ext?(:H) %&gt;, and/or `henvcfg.FIOM`&lt;% end %&gt;
/// as follows:
///
/// .Effective PR/PW/SR/SW in (H)S-mode
/// \[%autowidth,cols=",,,",options="header",separator="!"\]
/// !===
/// ! \[.rotate\]#`menvcfg.FIOM`# ! `pred.PI` +
/// `pred.PO` +
/// `succ.SI` +
/// `succ.SO`
/// ! -&gt; +
/// -&gt; +
/// -&gt; +
/// -&gt;
/// ! effective `PR` +
/// effective `PW` +
/// effective `SR` +
/// effective `SW`
///
/// ! 0 ! - ! ! from encoding
/// ! 1 ! 0 ! ! from encoding
/// ! 1 ! 1 ! ! 1
/// !===
///
/// .Effective PR/PW/SR/SW in U-mode
/// \[%autowidth,options="header",separator="!",cols=",,,,"\]
/// !===
/// ! \[.rotate\]#`menvcfg.FIOM`# ! \[.rotate\]#`senvcfg.FIOM`# !  `pred.PI` +
/// `pred.PO` +
/// `succ.SI` +
/// `succ.SO`
/// ! -&gt; +
/// -&gt; +
/// -&gt; +
/// -&gt;
/// ! effective `PR` +
/// effective `PW` +
/// effective `SR` +
/// effective `SW`
///
/// ! 0 ! 0 ! - ! ! from encoding
/// ! 0 ! 1 ! 0 ! ! from encoding
/// ! 0 ! 1 ! 1 ! ! 1
/// ! 1 ! - ! 0 ! ! from encoding
/// ! 1 ! - ! 1 ! ! 1
/// !===
///
/// &lt;%- if ext?(:H) -%&gt;
/// .Effective PR/PW/SR/SW in VS-mode and VU-mode
/// \[%autowidth,options="header",separator="!",cols=",,,,"\]
/// !===
/// ! \[.rotate\]#`menvcfg.FIOM`# ! \[.rotate\]#`henvcfg.FIOM`# !  `pred.PI` +
/// `pred.PO` +
/// `succ.SI` +
/// `succ.SO`
/// ! -&gt; +
/// -&gt; +
/// -&gt; +
/// -&gt;
/// ! effective `PR` +
/// effective `PW` +
/// effective `SR` +
/// effective `SW`
///
/// ! 0 ! 0 ! - ! ! from encoding
/// ! 0 ! 1 ! 0 ! ! from encoding
/// ! 0 ! 1 ! 1 ! ! 1
/// ! 1 ! - ! 0 ! ! from encoding
/// ! 1 ! - ! 1 ! ! 1
/// !===
/// &lt;%- end -%&gt;
///
/// # Forms
/// Assembly: `fence "TODO"`
/// Rust: `fence(fm, pred, succ, rs1, rd)`
///
/// # Arguments
/// - `fm` — Immediate encoding value.
/// - `pred` — Immediate encoding value.
/// - `succ` — Immediate encoding value.
/// - `rs1` — Source register.
/// - `rd` — Destination/source register.
pub trait FenceEmitter<T0, T1, T2, T3, T4> {
    fn fence(&mut self, fm: T0, pred: T1, succ: T2, rs1: T3, rd: T4);
}

/// Instruction fence
///
/// The FENCE.I instruction is used to synchronize the instruction and data
/// streams. RISC-V does not guarantee that stores to instruction memory
/// will be made visible to instruction fetches on a RISC-V hart until that
/// hart executes a FENCE.I instruction. A FENCE.I instruction ensures that
/// a subsequent instruction fetch on a RISC-V hart will see any previous
/// data stores already visible to the same RISC-V hart. FENCE.I does _not_
/// ensure that other RISC-V harts' instruction fetches will observe the
/// local hart's stores in a multiprocessor system. To make a store to
/// instruction memory visible to all RISC-V harts, the writing hart also
/// has to execute a data FENCE before requesting that all remote RISC-V
/// harts execute a FENCE.I.
///
/// The unused fields in the FENCE.I instruction, _imm\[11:0\]_, _rs1_, and
/// _rd_, are reserved for finer-grain fences in future extensions. For
/// forward compatibility, base implementations shall ignore these fields,
/// and standard software shall zero these fields.
/// (((FENCE.I, finer-grained)))
/// (((FENCE.I, forward compatibility)))
///
/// \[NOTE\]
/// ====
/// Because FENCE.I only orders stores with a hart's own instruction
/// fetches, application code should only rely upon FENCE.I if the
/// application thread will not be migrated to a different hart. The EEI can
/// provide mechanisms for efficient multiprocessor instruction-stream
/// synchronization.
/// ====
///
/// # Forms
/// Assembly: `fence.i ""`
/// Rust: `fence_i()`
///
/// # Arguments
pub trait FenceIEmitter {
    fn fence_i(&mut self);
}

/// RISC-V `fence.tso` instruction.
///
/// # Forms
/// Assembly: `fence.tso`
/// Rust: `fence_tso()`
///
/// # Arguments
pub trait FenceTsoEmitter {
    fn fence_tso(&mut self);
}

/// RISC-V `feq.d` instruction.
///
/// # Forms
/// Assembly: `feq.d xd, xs1, xs2`
/// Rust: `feq_d(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait FeqDEmitter<T0, T1, T2> {
    fn feq_d(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `feq.h` instruction.
///
/// # Forms
/// Assembly: `feq.h xd, xs1, xs2`
/// Rust: `feq_h(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait FeqHEmitter<T0, T1, T2> {
    fn feq_h(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `feq.q` instruction.
///
/// # Forms
/// Assembly: `feq.q xd, qs1, qs2`
/// Rust: `feq_q(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait FeqQEmitter<T0, T1, T2> {
    fn feq_q(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// Single-precision floating-point equal
///
/// Writes 1 to _rd_ if _fs1_ and _fs2_ are equal, and 0 otherwise.
///
/// If either operand is NaN, the result is 0 (not equal). If either operand is a signaling NaN, the invalid flag is set.
///
/// Positive zero is considered equal to negative zero.
///
/// # Forms
/// Assembly: `feq.s xd, fs1, fs2`
/// Rust: `feq_s(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait FeqSEmitter<T0, T1, T2> {
    fn feq_s(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `fld` instruction.
///
/// # Forms
/// Assembly: `fld xd, xs1, imm`
/// Rust: `fld(rd, rs1, imm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Memory base register.
/// - `imm` — Immediate encoding value.
pub trait FldEmitter<T0, T1, T2> {
    fn fld(&mut self, rd: T0, rs1: T1, imm: T2);
}

/// RISC-V `fle.d` instruction.
///
/// # Forms
/// Assembly: `fle.d xd, xs1, xs2`
/// Rust: `fle_d(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait FleDEmitter<T0, T1, T2> {
    fn fle_d(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `fle.h` instruction.
///
/// # Forms
/// Assembly: `fle.h xd, xs1, xs2`
/// Rust: `fle_h(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait FleHEmitter<T0, T1, T2> {
    fn fle_h(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `fle.q` instruction.
///
/// # Forms
/// Assembly: `fle.q xd, qs1, qs2`
/// Rust: `fle_q(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait FleQEmitter<T0, T1, T2> {
    fn fle_q(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// Single-precision floating-point less than or equal
///
/// Writes 1 to _rd_ if _fs1_ is less than or equal to _fs2_, and 0 otherwise.
///
/// If either operand is NaN, the result is 0 (not equal).
/// If either operand is a NaN (signaling or quiet), the invalid flag is set.
///
/// Positive zero and negative zero are considered equal.
///
/// # Forms
/// Assembly: `fle.s xd, fs1, fs2`
/// Rust: `fle_s(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait FleSEmitter<T0, T1, T2> {
    fn fle_s(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `fleq.d` instruction.
///
/// # Forms
/// Assembly: `fleq.d xd, xs1, xs2`
/// Rust: `fleq_d(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait FleqDEmitter<T0, T1, T2> {
    fn fleq_d(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `fleq.h` instruction.
///
/// # Forms
/// Assembly: `fleq.h xd, xs1, xs2`
/// Rust: `fleq_h(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait FleqHEmitter<T0, T1, T2> {
    fn fleq_h(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `fleq.q` instruction.
///
/// # Forms
/// Assembly: `fleq.q xd, qs1, qs2`
/// Rust: `fleq_q(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait FleqQEmitter<T0, T1, T2> {
    fn fleq_q(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `fleq.s` instruction.
///
/// # Forms
/// Assembly: `fleq.s xd, fs1, fs2`
/// Rust: `fleq_s(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait FleqSEmitter<T0, T1, T2> {
    fn fleq_s(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// Half-precision floating-point load
///
/// The `flh` instruction loads a single-precision floating-point value from memory at address _rs1_ + _imm_ into floating-point register _rd_.
///
/// `flh` does not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved.
///
/// `flh` is only guaranteed to execute atomically if the effective address is naturally aligned.
///
/// # Forms
/// Assembly: `flh fd, imm(xs1)`
/// Rust: `flh(rd, rs1, imm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Memory base register.
/// - `imm` — Immediate encoding value.
pub trait FlhEmitter<T0, T1, T2> {
    fn flh(&mut self, rd: T0, rs1: T1, imm: T2);
}

/// RISC-V `fli.d` instruction.
///
/// # Forms
/// Assembly: `fli.d xd, xs1`
/// Rust: `fli_d(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait FliDEmitter<T0, T1> {
    fn fli_d(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `fli.h` instruction.
///
/// # Forms
/// Assembly: `fli.h xd, xs1`
/// Rust: `fli_h(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait FliHEmitter<T0, T1> {
    fn fli_h(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `fli.q` instruction.
///
/// # Forms
/// Assembly: `fli.q fd, qs1`
/// Rust: `fli_q(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait FliQEmitter<T0, T1> {
    fn fli_q(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `fli.s` instruction.
///
/// # Forms
/// Assembly: `fli.s fd, fs1`
/// Rust: `fli_s(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait FliSEmitter<T0, T1> {
    fn fli_s(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `flq` instruction.
///
/// # Forms
/// Assembly: `flq qd, xs1, imm`
/// Rust: `flq(rd, rs1, imm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Memory base register.
/// - `imm` — Immediate encoding value.
pub trait FlqEmitter<T0, T1, T2> {
    fn flq(&mut self, rd: T0, rs1: T1, imm: T2);
}

/// RISC-V `flt.d` instruction.
///
/// # Forms
/// Assembly: `flt.d xd, xs1, xs2`
/// Rust: `flt_d(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait FltDEmitter<T0, T1, T2> {
    fn flt_d(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `flt.h` instruction.
///
/// # Forms
/// Assembly: `flt.h xd, xs1, xs2`
/// Rust: `flt_h(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait FltHEmitter<T0, T1, T2> {
    fn flt_h(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `flt.q` instruction.
///
/// # Forms
/// Assembly: `flt.q xd, qs1, qs2`
/// Rust: `flt_q(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait FltQEmitter<T0, T1, T2> {
    fn flt_q(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// Single-precision floating-point less than
///
/// Writes 1 to _rd_ if _fs1_ is less than _fs2_, and 0 otherwise.
///
/// If either operand is NaN, the result is 0 (not equal).
/// If either operand is a NaN (signaling or quiet), the invalid flag is set.
///
/// # Forms
/// Assembly: `flt.s xd, fs1, fs2`
/// Rust: `flt_s(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait FltSEmitter<T0, T1, T2> {
    fn flt_s(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `fltq.d` instruction.
///
/// # Forms
/// Assembly: `fltq.d xd, xs1, xs2`
/// Rust: `fltq_d(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait FltqDEmitter<T0, T1, T2> {
    fn fltq_d(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `fltq.h` instruction.
///
/// # Forms
/// Assembly: `fltq.h xd, xs1, xs2`
/// Rust: `fltq_h(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait FltqHEmitter<T0, T1, T2> {
    fn fltq_h(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `fltq.q` instruction.
///
/// # Forms
/// Assembly: `fltq.q qd, qs1, qs2`
/// Rust: `fltq_q(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait FltqQEmitter<T0, T1, T2> {
    fn fltq_q(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `fltq.s` instruction.
///
/// # Forms
/// Assembly: `fltq.s xd, fs1, fs2`
/// Rust: `fltq_s(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait FltqSEmitter<T0, T1, T2> {
    fn fltq_s(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// Single-precision floating-point load
///
/// The `flw` instruction loads a single-precision floating-point value from memory at address _rs1_ + _imm_ into floating-point register _fd_.
///
/// `flw` does not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved.
///
/// # Forms
/// Assembly: `flw fd, xs1, imm`
/// Rust: `flw(rd, rs1, imm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Memory base register.
/// - `imm` — Immediate encoding value.
pub trait FlwEmitter<T0, T1, T2> {
    fn flw(&mut self, rd: T0, rs1: T1, imm: T2);
}

/// RISC-V `fmadd.d` instruction.
///
/// # Forms
/// Assembly: `fmadd.d xd, xs1, xs2, xs3, rm`
/// Rust: `fmadd_d(rd, rs1, rs2, rs3, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
/// - `rs3` — Source register.
/// - `rm` — Rounding mode.
pub trait FmaddDEmitter<T0, T1, T2, T3, T4> {
    fn fmadd_d(&mut self, rd: T0, rs1: T1, rs2: T2, rs3: T3, rm: T4);
}

/// RISC-V `fmadd.h` instruction.
///
/// # Forms
/// Assembly: `fmadd.h xd, xs1, xs2, xs3, rm`
/// Rust: `fmadd_h(rd, rs1, rs2, rs3, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
/// - `rs3` — Source register.
/// - `rm` — Rounding mode.
pub trait FmaddHEmitter<T0, T1, T2, T3, T4> {
    fn fmadd_h(&mut self, rd: T0, rs1: T1, rs2: T2, rs3: T3, rm: T4);
}

/// RISC-V `fmadd.q` instruction.
///
/// # Forms
/// Assembly: `fmadd.q qd, qs1, qs2, qs3, rm`
/// Rust: `fmadd_q(rd, rs1, rs2, rs3, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
/// - `rs3` — Source register.
/// - `rm` — Rounding mode.
pub trait FmaddQEmitter<T0, T1, T2, T3, T4> {
    fn fmadd_q(&mut self, rd: T0, rs1: T1, rs2: T2, rs3: T3, rm: T4);
}

/// RISC-V `fmadd.s` instruction.
///
/// # Forms
/// Assembly: `fmadd.s fd, fs1, fs2, fs3, rm`
/// Rust: `fmadd_s(rd, rs1, rs2, rs3, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
/// - `rs3` — Source register.
/// - `rm` — Rounding mode.
pub trait FmaddSEmitter<T0, T1, T2, T3, T4> {
    fn fmadd_s(&mut self, rd: T0, rs1: T1, rs2: T2, rs3: T3, rm: T4);
}

/// RISC-V `fmax.d` instruction.
///
/// # Forms
/// Assembly: `fmax.d xd, xs1, xs2`
/// Rust: `fmax_d(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait FmaxDEmitter<T0, T1, T2> {
    fn fmax_d(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `fmax.h` instruction.
///
/// # Forms
/// Assembly: `fmax.h xd, xs1, xs2`
/// Rust: `fmax_h(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait FmaxHEmitter<T0, T1, T2> {
    fn fmax_h(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `fmax.q` instruction.
///
/// # Forms
/// Assembly: `fmax.q qd, qs1, qs2`
/// Rust: `fmax_q(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait FmaxQEmitter<T0, T1, T2> {
    fn fmax_q(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `fmax.s` instruction.
///
/// # Forms
/// Assembly: `fmax.s fd, fs1, fs2`
/// Rust: `fmax_s(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait FmaxSEmitter<T0, T1, T2> {
    fn fmax_s(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `fmaxm.d` instruction.
///
/// # Forms
/// Assembly: `fmaxm.d xd, xs1, xs2`
/// Rust: `fmaxm_d(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait FmaxmDEmitter<T0, T1, T2> {
    fn fmaxm_d(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `fmaxm.h` instruction.
///
/// # Forms
/// Assembly: `fmaxm.h xd, xs1, xs2`
/// Rust: `fmaxm_h(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait FmaxmHEmitter<T0, T1, T2> {
    fn fmaxm_h(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `fmaxm.q` instruction.
///
/// # Forms
/// Assembly: `fmaxm.q qd, qs1, qs2`
/// Rust: `fmaxm_q(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait FmaxmQEmitter<T0, T1, T2> {
    fn fmaxm_q(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `fmaxm.s` instruction.
///
/// # Forms
/// Assembly: `fmaxm.s xd, xs1, xs2`
/// Rust: `fmaxm_s(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait FmaxmSEmitter<T0, T1, T2> {
    fn fmaxm_s(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `fmin.d` instruction.
///
/// # Forms
/// Assembly: `fmin.d xd, xs1, xs2`
/// Rust: `fmin_d(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait FminDEmitter<T0, T1, T2> {
    fn fmin_d(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `fmin.h` instruction.
///
/// # Forms
/// Assembly: `fmin.h xd, xs1, xs2`
/// Rust: `fmin_h(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait FminHEmitter<T0, T1, T2> {
    fn fmin_h(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `fmin.q` instruction.
///
/// # Forms
/// Assembly: `fmin.q xd, xs1, xs2`
/// Rust: `fmin_q(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait FminQEmitter<T0, T1, T2> {
    fn fmin_q(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `fmin.s` instruction.
///
/// # Forms
/// Assembly: `fmin.s xd, xs1, xs2`
/// Rust: `fmin_s(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait FminSEmitter<T0, T1, T2> {
    fn fmin_s(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `fminm.d` instruction.
///
/// # Forms
/// Assembly: `fminm.d xd, xs1, xs2`
/// Rust: `fminm_d(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait FminmDEmitter<T0, T1, T2> {
    fn fminm_d(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `fminm.h` instruction.
///
/// # Forms
/// Assembly: `fminm.h xd, xs1, xs2`
/// Rust: `fminm_h(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait FminmHEmitter<T0, T1, T2> {
    fn fminm_h(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `fminm.q` instruction.
///
/// # Forms
/// Assembly: `fminm.q qd, qs1, qs2`
/// Rust: `fminm_q(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait FminmQEmitter<T0, T1, T2> {
    fn fminm_q(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `fminm.s` instruction.
///
/// # Forms
/// Assembly: `fminm.s fd, fs1, fs2`
/// Rust: `fminm_s(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait FminmSEmitter<T0, T1, T2> {
    fn fminm_s(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `fmsub.d` instruction.
///
/// # Forms
/// Assembly: `fmsub.d xd, xs1, xs2, xs3, rm`
/// Rust: `fmsub_d(rd, rs1, rs2, rs3, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
/// - `rs3` — Source register.
/// - `rm` — Rounding mode.
pub trait FmsubDEmitter<T0, T1, T2, T3, T4> {
    fn fmsub_d(&mut self, rd: T0, rs1: T1, rs2: T2, rs3: T3, rm: T4);
}

/// RISC-V `fmsub.h` instruction.
///
/// # Forms
/// Assembly: `fmsub.h xd, xs1, xs2, xs3, rm`
/// Rust: `fmsub_h(rd, rs1, rs2, rs3, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
/// - `rs3` — Source register.
/// - `rm` — Rounding mode.
pub trait FmsubHEmitter<T0, T1, T2, T3, T4> {
    fn fmsub_h(&mut self, rd: T0, rs1: T1, rs2: T2, rs3: T3, rm: T4);
}

/// RISC-V `fmsub.q` instruction.
///
/// # Forms
/// Assembly: `fmsub.q qd, qs1, qs2, qs3, rm`
/// Rust: `fmsub_q(rd, rs1, rs2, rs3, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
/// - `rs3` — Source register.
/// - `rm` — Rounding mode.
pub trait FmsubQEmitter<T0, T1, T2, T3, T4> {
    fn fmsub_q(&mut self, rd: T0, rs1: T1, rs2: T2, rs3: T3, rm: T4);
}

/// RISC-V `fmsub.s` instruction.
///
/// # Forms
/// Assembly: `fmsub.s fd, fs1, fs2, fs3, rm`
/// Rust: `fmsub_s(rd, rs1, rs2, rs3, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
/// - `rs3` — Source register.
/// - `rm` — Rounding mode.
pub trait FmsubSEmitter<T0, T1, T2, T3, T4> {
    fn fmsub_s(&mut self, rd: T0, rs1: T1, rs2: T2, rs3: T3, rm: T4);
}

/// RISC-V `fmul.d` instruction.
///
/// # Forms
/// Assembly: `fmul.d xd, xs1, xs2, rm`
/// Rust: `fmul_d(rd, rs1, rs2, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
/// - `rm` — Rounding mode.
pub trait FmulDEmitter<T0, T1, T2, T3> {
    fn fmul_d(&mut self, rd: T0, rs1: T1, rs2: T2, rm: T3);
}

/// RISC-V `fmul.h` instruction.
///
/// # Forms
/// Assembly: `fmul.h xd, xs1, xs2, rm`
/// Rust: `fmul_h(rd, rs1, rs2, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
/// - `rm` — Rounding mode.
pub trait FmulHEmitter<T0, T1, T2, T3> {
    fn fmul_h(&mut self, rd: T0, rs1: T1, rs2: T2, rm: T3);
}

/// RISC-V `fmul.q` instruction.
///
/// # Forms
/// Assembly: `fmul.q qd, qs1, qs2, rm`
/// Rust: `fmul_q(rd, rs1, rs2, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
/// - `rm` — Rounding mode.
pub trait FmulQEmitter<T0, T1, T2, T3> {
    fn fmul_q(&mut self, rd: T0, rs1: T1, rs2: T2, rm: T3);
}

/// RISC-V `fmul.s` instruction.
///
/// # Forms
/// Assembly: `fmul.s fd, fs1, fs2, rm`
/// Rust: `fmul_s(rd, rs1, rs2, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
/// - `rm` — Rounding mode.
pub trait FmulSEmitter<T0, T1, T2, T3> {
    fn fmul_s(&mut self, rd: T0, rs1: T1, rs2: T2, rm: T3);
}

/// RISC-V `fmv.d` instruction.
///
/// # Forms
/// Assembly: `fmv.d rd rs1 rs2_eq_rs1`
/// Rust: `fmv_d(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait FmvDEmitter<T0, T1, T2> {
    fn fmv_d(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `fmv.d.x` instruction.
///
/// # Forms
/// Assembly: `fmv.d.x xd, xs1`
/// Rust: `fmv_d_x(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait FmvDXEmitter<T0, T1> {
    fn fmv_d_x(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `fmv.h` instruction.
///
/// # Forms
/// Assembly: `fmv.h rd rs1 rs2_eq_rs1`
/// Rust: `fmv_h(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait FmvHEmitter<T0, T1, T2> {
    fn fmv_h(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// Half-precision floating-point move from integer
///
/// Moves the half-precision value encoded in IEEE 754-2008 standard encoding
/// from the lower 16 bits of integer register `rs1` to the floating-point
/// register `fd`. The bits are not modified in the transfer, and in particular,
/// the payloads of non-canonical NaNs are preserved.
///
/// # Forms
/// Assembly: `fmv.h.x fd, xs1`
/// Rust: `fmv_h_x(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait FmvHXEmitter<T0, T1> {
    fn fmv_h_x(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `fmv.q` instruction.
///
/// # Forms
/// Assembly: `fmv.q rd rs1 rs2_eq_rs1`
/// Rust: `fmv_q(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait FmvQEmitter<T0, T1, T2> {
    fn fmv_q(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `fmv.s` instruction.
///
/// # Forms
/// Assembly: `fmv.s rd rs1 rs2_eq_rs1`
/// Rust: `fmv_s(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait FmvSEmitter<T0, T1, T2> {
    fn fmv_s(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `fmv.s.x` instruction.
///
/// # Forms
/// Assembly: `fmv.s.x rd rs1`
/// Rust: `fmv_s_x(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait FmvSXEmitter<T0, T1> {
    fn fmv_s_x(&mut self, rd: T0, rs1: T1);
}

/// Single-precision floating-point move from integer
///
/// Moves the single-precision value encoded in IEEE 754-2008 standard encoding
/// from the lower 32 bits of integer register `rs1` to the floating-point
/// register `fd`. The bits are not modified in the transfer, and in particular,
/// the payloads of non-canonical NaNs are preserved.
///
/// # Forms
/// Assembly: `fmv.w.x fd, xs1`
/// Rust: `fmv_w_x(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait FmvWXEmitter<T0, T1> {
    fn fmv_w_x(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `fmv.x.d` instruction.
///
/// # Forms
/// Assembly: `fmv.x.d xd, xs1`
/// Rust: `fmv_x_d(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait FmvXDEmitter<T0, T1> {
    fn fmv_x_d(&mut self, rd: T0, rs1: T1);
}

/// Move half-precision value from floating-point to integer register
///
/// Moves the half-precision value in floating-point register rs1 represented in IEEE 754-2008
/// encoding to the lower 16 bits of integer register rd.
///
/// The bits are not modified in the transfer, and in particular, the payloads of non-canonical
/// NaNs are preserved.
///
/// The highest XLEN-16 bits of the destination register are filled with copies of the
/// floating-point number's sign bit.
///
/// # Forms
/// Assembly: `fmv.x.h rd, fs1`
/// Rust: `fmv_x_h(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait FmvXHEmitter<T0, T1> {
    fn fmv_x_h(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `fmv.x.s` instruction.
///
/// # Forms
/// Assembly: `fmv.x.s rd rs1`
/// Rust: `fmv_x_s(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait FmvXSEmitter<T0, T1> {
    fn fmv_x_s(&mut self, rd: T0, rs1: T1);
}

/// Move single-precision value from floating-point to integer register
///
/// Moves the single-precision value in floating-point register rs1 represented in IEEE 754-2008
/// encoding to the lower 32 bits of integer register rd.
/// The bits are not modified in the transfer, and in particular, the payloads of non-canonical
/// NaNs are preserved.
/// For RV64, the higher 32 bits of the destination register are filled with copies of the
/// floating-point number's sign bit.
///
/// # Forms
/// Assembly: `fmv.x.w xd, fs1`
/// Rust: `fmv_x_w(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait FmvXWEmitter<T0, T1> {
    fn fmv_x_w(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `fmvh.x.d` instruction.
///
/// # Forms
/// Assembly: `fmvh.x.d xd, xs1`
/// Rust: `fmvh_x_d(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait FmvhXDEmitter<T0, T1> {
    fn fmvh_x_d(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `fmvh.x.q` instruction.
///
/// # Forms
/// Assembly: `fmvh.x.q xd, qs1`
/// Rust: `fmvh_x_q(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait FmvhXQEmitter<T0, T1> {
    fn fmvh_x_q(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `fmvp.d.x` instruction.
///
/// # Forms
/// Assembly: `fmvp.d.x xd, xs1, xs2`
/// Rust: `fmvp_d_x(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait FmvpDXEmitter<T0, T1, T2> {
    fn fmvp_d_x(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `fmvp.q.x` instruction.
///
/// # Forms
/// Assembly: `fmvp.q.x qd, xs1, xs2`
/// Rust: `fmvp_q_x(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait FmvpQXEmitter<T0, T1, T2> {
    fn fmvp_q_x(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `fneg.d` instruction.
///
/// # Forms
/// Assembly: `fneg.d rd rs1 rs2_eq_rs1`
/// Rust: `fneg_d(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait FnegDEmitter<T0, T1, T2> {
    fn fneg_d(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `fneg.h` instruction.
///
/// # Forms
/// Assembly: `fneg.h rd rs1 rs2_eq_rs1`
/// Rust: `fneg_h(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait FnegHEmitter<T0, T1, T2> {
    fn fneg_h(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `fneg.q` instruction.
///
/// # Forms
/// Assembly: `fneg.q rd rs1 rs2_eq_rs1`
/// Rust: `fneg_q(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait FnegQEmitter<T0, T1, T2> {
    fn fneg_q(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `fneg.s` instruction.
///
/// # Forms
/// Assembly: `fneg.s rd rs1 rs2_eq_rs1`
/// Rust: `fneg_s(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait FnegSEmitter<T0, T1, T2> {
    fn fneg_s(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `fnmadd.d` instruction.
///
/// # Forms
/// Assembly: `fnmadd.d xd, xs1, xs2, xs3, rm`
/// Rust: `fnmadd_d(rd, rs1, rs2, rs3, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
/// - `rs3` — Source register.
/// - `rm` — Rounding mode.
pub trait FnmaddDEmitter<T0, T1, T2, T3, T4> {
    fn fnmadd_d(&mut self, rd: T0, rs1: T1, rs2: T2, rs3: T3, rm: T4);
}

/// RISC-V `fnmadd.h` instruction.
///
/// # Forms
/// Assembly: `fnmadd.h xd, xs1, xs2, xs3, rm`
/// Rust: `fnmadd_h(rd, rs1, rs2, rs3, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
/// - `rs3` — Source register.
/// - `rm` — Rounding mode.
pub trait FnmaddHEmitter<T0, T1, T2, T3, T4> {
    fn fnmadd_h(&mut self, rd: T0, rs1: T1, rs2: T2, rs3: T3, rm: T4);
}

/// RISC-V `fnmadd.q` instruction.
///
/// # Forms
/// Assembly: `fnmadd.q qd, qs1, qs2, qs3, rm`
/// Rust: `fnmadd_q(rd, rs1, rs2, rs3, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
/// - `rs3` — Source register.
/// - `rm` — Rounding mode.
pub trait FnmaddQEmitter<T0, T1, T2, T3, T4> {
    fn fnmadd_q(&mut self, rd: T0, rs1: T1, rs2: T2, rs3: T3, rm: T4);
}

/// RISC-V `fnmadd.s` instruction.
///
/// # Forms
/// Assembly: `fnmadd.s fd, fs1, fs2, fs3, rm`
/// Rust: `fnmadd_s(rd, rs1, rs2, rs3, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
/// - `rs3` — Source register.
/// - `rm` — Rounding mode.
pub trait FnmaddSEmitter<T0, T1, T2, T3, T4> {
    fn fnmadd_s(&mut self, rd: T0, rs1: T1, rs2: T2, rs3: T3, rm: T4);
}

/// RISC-V `fnmsub.d` instruction.
///
/// # Forms
/// Assembly: `fnmsub.d xd, xs1, xs2, xs3, rm`
/// Rust: `fnmsub_d(rd, rs1, rs2, rs3, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
/// - `rs3` — Source register.
/// - `rm` — Rounding mode.
pub trait FnmsubDEmitter<T0, T1, T2, T3, T4> {
    fn fnmsub_d(&mut self, rd: T0, rs1: T1, rs2: T2, rs3: T3, rm: T4);
}

/// RISC-V `fnmsub.h` instruction.
///
/// # Forms
/// Assembly: `fnmsub.h xd, xs1, xs2, xs3, rm`
/// Rust: `fnmsub_h(rd, rs1, rs2, rs3, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
/// - `rs3` — Source register.
/// - `rm` — Rounding mode.
pub trait FnmsubHEmitter<T0, T1, T2, T3, T4> {
    fn fnmsub_h(&mut self, rd: T0, rs1: T1, rs2: T2, rs3: T3, rm: T4);
}

/// RISC-V `fnmsub.q` instruction.
///
/// # Forms
/// Assembly: `fnmsub.q qd, qs1, qs2, qs3, rm`
/// Rust: `fnmsub_q(rd, rs1, rs2, rs3, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
/// - `rs3` — Source register.
/// - `rm` — Rounding mode.
pub trait FnmsubQEmitter<T0, T1, T2, T3, T4> {
    fn fnmsub_q(&mut self, rd: T0, rs1: T1, rs2: T2, rs3: T3, rm: T4);
}

/// RISC-V `fnmsub.s` instruction.
///
/// # Forms
/// Assembly: `fnmsub.s xd, xs1, xs2, xs3, rm`
/// Rust: `fnmsub_s(rd, rs1, rs2, rs3, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
/// - `rs3` — Source register.
/// - `rm` — Rounding mode.
pub trait FnmsubSEmitter<T0, T1, T2, T3, T4> {
    fn fnmsub_s(&mut self, rd: T0, rs1: T1, rs2: T2, rs3: T3, rm: T4);
}

/// RISC-V `frcsr` instruction.
///
/// # Forms
/// Assembly: `frcsr rd`
/// Rust: `frcsr(rd)`
///
/// # Arguments
/// - `rd` — Destination register.
pub trait FrcsrEmitter<T0> {
    fn frcsr(&mut self, rd: T0);
}

/// RISC-V `frflags` instruction.
///
/// # Forms
/// Assembly: `frflags rd`
/// Rust: `frflags(rd)`
///
/// # Arguments
/// - `rd` — Destination register.
pub trait FrflagsEmitter<T0> {
    fn frflags(&mut self, rd: T0);
}

/// RISC-V `fround.d` instruction.
///
/// # Forms
/// Assembly: `fround.d xd, xs1, rm`
/// Rust: `fround_d(rd, rs1, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rm` — Rounding mode.
pub trait FroundDEmitter<T0, T1, T2> {
    fn fround_d(&mut self, rd: T0, rs1: T1, rm: T2);
}

/// RISC-V `fround.h` instruction.
///
/// # Forms
/// Assembly: `fround.h xd, xs1, rm`
/// Rust: `fround_h(rd, rs1, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rm` — Rounding mode.
pub trait FroundHEmitter<T0, T1, T2> {
    fn fround_h(&mut self, rd: T0, rs1: T1, rm: T2);
}

/// RISC-V `fround.q` instruction.
///
/// # Forms
/// Assembly: `fround.q qd, qs1, rm`
/// Rust: `fround_q(rd, rs1, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rm` — Rounding mode.
pub trait FroundQEmitter<T0, T1, T2> {
    fn fround_q(&mut self, rd: T0, rs1: T1, rm: T2);
}

/// RISC-V `fround.s` instruction.
///
/// # Forms
/// Assembly: `fround.s fd, xs1, rm`
/// Rust: `fround_s(rd, rs1, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rm` — Rounding mode.
pub trait FroundSEmitter<T0, T1, T2> {
    fn fround_s(&mut self, rd: T0, rs1: T1, rm: T2);
}

/// RISC-V `froundnx.d` instruction.
///
/// # Forms
/// Assembly: `froundnx.d xd, xs1, rm`
/// Rust: `froundnx_d(rd, rs1, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rm` — Rounding mode.
pub trait FroundnxDEmitter<T0, T1, T2> {
    fn froundnx_d(&mut self, rd: T0, rs1: T1, rm: T2);
}

/// RISC-V `froundnx.h` instruction.
///
/// # Forms
/// Assembly: `froundnx.h xd, xs1, rm`
/// Rust: `froundnx_h(rd, rs1, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rm` — Rounding mode.
pub trait FroundnxHEmitter<T0, T1, T2> {
    fn froundnx_h(&mut self, rd: T0, rs1: T1, rm: T2);
}

/// RISC-V `froundnx.q` instruction.
///
/// # Forms
/// Assembly: `froundnx.q qd, qs1, rm`
/// Rust: `froundnx_q(rd, rs1, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rm` — Rounding mode.
pub trait FroundnxQEmitter<T0, T1, T2> {
    fn froundnx_q(&mut self, rd: T0, rs1: T1, rm: T2);
}

/// RISC-V `froundnx.s` instruction.
///
/// # Forms
/// Assembly: `froundnx.s fd, rs1, rm`
/// Rust: `froundnx_s(rd, rs1, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rm` — Rounding mode.
pub trait FroundnxSEmitter<T0, T1, T2> {
    fn froundnx_s(&mut self, rd: T0, rs1: T1, rm: T2);
}

/// RISC-V `frrm` instruction.
///
/// # Forms
/// Assembly: `frrm rd`
/// Rust: `frrm(rd)`
///
/// # Arguments
/// - `rd` — Destination register.
pub trait FrrmEmitter<T0> {
    fn frrm(&mut self, rd: T0);
}

/// RISC-V `fscsr` instruction.
///
/// # Forms
/// Assembly: `fscsr rd rs1`
/// Rust: `fscsr(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait FscsrEmitter<T0, T1> {
    fn fscsr(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `fsd` instruction.
///
/// # Forms
/// Assembly: `fsd xs1, xs2, imm`
/// Rust: `fsd(rs1, rs2, imm)`
///
/// # Arguments
/// - `rs1` — Memory base register.
/// - `rs2` — Source register.
/// - `imm` — Immediate encoding value.
pub trait FsdEmitter<T0, T1, T2> {
    fn fsd(&mut self, rs1: T0, rs2: T1, imm: T2);
}

/// RISC-V `fsflags` instruction.
///
/// # Forms
/// Assembly: `fsflags rd rs1`
/// Rust: `fsflags(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait FsflagsEmitter<T0, T1> {
    fn fsflags(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `fsflagsi` instruction.
///
/// # Forms
/// Assembly: `fsflagsi rd zimm5`
/// Rust: `fsflagsi(rd, zimm5)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `zimm5` — Immediate encoding value.
pub trait FsflagsiEmitter<T0, T1> {
    fn fsflagsi(&mut self, rd: T0, zimm5: T1);
}

/// RISC-V `fsgnj.d` instruction.
///
/// # Forms
/// Assembly: `fsgnj.d xd, xs1, xs2`
/// Rust: `fsgnj_d(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait FsgnjDEmitter<T0, T1, T2> {
    fn fsgnj_d(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `fsgnj.h` instruction.
///
/// # Forms
/// Assembly: `fsgnj.h xd, xs1, xs2`
/// Rust: `fsgnj_h(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait FsgnjHEmitter<T0, T1, T2> {
    fn fsgnj_h(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `fsgnj.q` instruction.
///
/// # Forms
/// Assembly: `fsgnj.q qd, qs1, qs2`
/// Rust: `fsgnj_q(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait FsgnjQEmitter<T0, T1, T2> {
    fn fsgnj_q(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// Single-precision sign inject
///
/// Writes _fd_ with sign bit of _fs2_ and the exponent and mantissa of _fs1_.
///
/// Sign-injection instructions do not set floating-point exception flags, nor do they canonicalize NaNs.
///
/// # Forms
/// Assembly: `fsgnj.s fd, fs1, fs2`
/// Rust: `fsgnj_s(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait FsgnjSEmitter<T0, T1, T2> {
    fn fsgnj_s(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `fsgnjn.d` instruction.
///
/// # Forms
/// Assembly: `fsgnjn.d xd, xs1, xs2`
/// Rust: `fsgnjn_d(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait FsgnjnDEmitter<T0, T1, T2> {
    fn fsgnjn_d(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `fsgnjn.h` instruction.
///
/// # Forms
/// Assembly: `fsgnjn.h xd, xs1, xs2`
/// Rust: `fsgnjn_h(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait FsgnjnHEmitter<T0, T1, T2> {
    fn fsgnjn_h(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `fsgnjn.q` instruction.
///
/// # Forms
/// Assembly: `fsgnjn.q qd, qs1, qs2`
/// Rust: `fsgnjn_q(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait FsgnjnQEmitter<T0, T1, T2> {
    fn fsgnjn_q(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// Single-precision sign inject negate
///
/// Writes _fd_ with the opposite of the sign bit of _fs2_ and the exponent and mantissa of _fs1_.
///
/// Sign-injection instructions do not set floating-point exception flags, nor do they canonicalize NaNs.
///
/// # Forms
/// Assembly: `fsgnjn.s fd, fs1, fs2`
/// Rust: `fsgnjn_s(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait FsgnjnSEmitter<T0, T1, T2> {
    fn fsgnjn_s(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `fsgnjx.d` instruction.
///
/// # Forms
/// Assembly: `fsgnjx.d xd, xs1, xs2`
/// Rust: `fsgnjx_d(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait FsgnjxDEmitter<T0, T1, T2> {
    fn fsgnjx_d(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `fsgnjx.h` instruction.
///
/// # Forms
/// Assembly: `fsgnjx.h xd, xs1, xs2`
/// Rust: `fsgnjx_h(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait FsgnjxHEmitter<T0, T1, T2> {
    fn fsgnjx_h(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `fsgnjx.q` instruction.
///
/// # Forms
/// Assembly: `fsgnjx.q qd, qs1, qs2`
/// Rust: `fsgnjx_q(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait FsgnjxQEmitter<T0, T1, T2> {
    fn fsgnjx_q(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// Single-precision sign inject exclusive or
///
/// Writes _fd_ with the xor of the sign bits of _fs2_ and _fs1_ and the exponent and mantissa of _fs1_.
///
/// Sign-injection instructions do not set floating-point exception flags, nor do they canonicalize NaNs.
///
/// # Forms
/// Assembly: `fsgnjx.s fd, fs1, fs2`
/// Rust: `fsgnjx_s(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait FsgnjxSEmitter<T0, T1, T2> {
    fn fsgnjx_s(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// Half-precision floating-point store
///
/// The `fsh` instruction stores a half-precision floating-point value
/// from register _rd_ to memory at address _rs1_ + _imm_.
///
/// `fsh` does not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved.
///
/// `fsh` ignores all but the lower 16 bits in _rs2_.
///
/// `fsh` is only guaranteed to execute atomically if the effective address is naturally aligned.
///
/// # Forms
/// Assembly: `fsh fs2, imm(xs1)`
/// Rust: `fsh(rs1, rs2, imm)`
///
/// # Arguments
/// - `rs1` — Memory base register.
/// - `rs2` — Source register.
/// - `imm` — Immediate encoding value.
pub trait FshEmitter<T0, T1, T2> {
    fn fsh(&mut self, rs1: T0, rs2: T1, imm: T2);
}

/// RISC-V `fsq` instruction.
///
/// # Forms
/// Assembly: `fsq xs1, qs2, imm`
/// Rust: `fsq(rs1, rs2, imm)`
///
/// # Arguments
/// - `rs1` — Memory base register.
/// - `rs2` — Source register.
/// - `imm` — Immediate encoding value.
pub trait FsqEmitter<T0, T1, T2> {
    fn fsq(&mut self, rs1: T0, rs2: T1, imm: T2);
}

/// RISC-V `fsqrt.d` instruction.
///
/// # Forms
/// Assembly: `fsqrt.d xd, xs1, rm`
/// Rust: `fsqrt_d(rd, rs1, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rm` — Rounding mode.
pub trait FsqrtDEmitter<T0, T1, T2> {
    fn fsqrt_d(&mut self, rd: T0, rs1: T1, rm: T2);
}

/// RISC-V `fsqrt.h` instruction.
///
/// # Forms
/// Assembly: `fsqrt.h xd, xs1, rm`
/// Rust: `fsqrt_h(rd, rs1, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rm` — Rounding mode.
pub trait FsqrtHEmitter<T0, T1, T2> {
    fn fsqrt_h(&mut self, rd: T0, rs1: T1, rm: T2);
}

/// RISC-V `fsqrt.q` instruction.
///
/// # Forms
/// Assembly: `fsqrt.q qd, qs1, rm`
/// Rust: `fsqrt_q(rd, rs1, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rm` — Rounding mode.
pub trait FsqrtQEmitter<T0, T1, T2> {
    fn fsqrt_q(&mut self, rd: T0, rs1: T1, rm: T2);
}

/// RISC-V `fsqrt.s` instruction.
///
/// # Forms
/// Assembly: `fsqrt.s fd, fs1, rm`
/// Rust: `fsqrt_s(rd, rs1, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rm` — Rounding mode.
pub trait FsqrtSEmitter<T0, T1, T2> {
    fn fsqrt_s(&mut self, rd: T0, rs1: T1, rm: T2);
}

/// RISC-V `fsrm` instruction.
///
/// # Forms
/// Assembly: `fsrm rd rs1`
/// Rust: `fsrm(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait FsrmEmitter<T0, T1> {
    fn fsrm(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `fsrmi` instruction.
///
/// # Forms
/// Assembly: `fsrmi rd zimm5`
/// Rust: `fsrmi(rd, zimm5)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `zimm5` — Immediate encoding value.
pub trait FsrmiEmitter<T0, T1> {
    fn fsrmi(&mut self, rd: T0, zimm5: T1);
}

/// RISC-V `fsub.d` instruction.
///
/// # Forms
/// Assembly: `fsub.d xd, xs1, xs2, rm`
/// Rust: `fsub_d(rd, rs1, rs2, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
/// - `rm` — Rounding mode.
pub trait FsubDEmitter<T0, T1, T2, T3> {
    fn fsub_d(&mut self, rd: T0, rs1: T1, rs2: T2, rm: T3);
}

/// RISC-V `fsub.h` instruction.
///
/// # Forms
/// Assembly: `fsub.h xd, xs1, xs2, rm`
/// Rust: `fsub_h(rd, rs1, rs2, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
/// - `rm` — Rounding mode.
pub trait FsubHEmitter<T0, T1, T2, T3> {
    fn fsub_h(&mut self, rd: T0, rs1: T1, rs2: T2, rm: T3);
}

/// RISC-V `fsub.q` instruction.
///
/// # Forms
/// Assembly: `fsub.q qd, qs1, qs2, rm`
/// Rust: `fsub_q(rd, rs1, rs2, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
/// - `rm` — Rounding mode.
pub trait FsubQEmitter<T0, T1, T2, T3> {
    fn fsub_q(&mut self, rd: T0, rs1: T1, rs2: T2, rm: T3);
}

/// Single-precision floating-point subtraction
///
/// Do the single-precision floating-point subtraction of fs2 from fs1 and store the result in fd.
/// rm is the dynamic Rounding Mode.
///
/// # Forms
/// Assembly: `fsub.s fd, fs1, fs2, rm`
/// Rust: `fsub_s(rd, rs1, rs2, rm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
/// - `rm` — Rounding mode.
pub trait FsubSEmitter<T0, T1, T2, T3> {
    fn fsub_s(&mut self, rd: T0, rs1: T1, rs2: T2, rm: T3);
}

/// Single-precision floating-point store
///
/// The `fsw` instruction stores a single-precision floating-point value in _fs2_ to memory at address _rs1_ + _imm_.
///
/// `fsw` does not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved.
///
/// # Forms
/// Assembly: `fsw fs2, xs1, imm`
/// Rust: `fsw(rs1, rs2, imm)`
///
/// # Arguments
/// - `rs1` — Memory base register.
/// - `rs2` — Source register.
/// - `imm` — Immediate encoding value.
pub trait FswEmitter<T0, T1, T2> {
    fn fsw(&mut self, rs1: T0, rs2: T1, imm: T2);
}

/// RISC-V `hfence.gvma` instruction.
///
/// # Forms
/// Assembly: `hfence.gvma xs1, xs2`
/// Rust: `hfence_gvma(rs1, rs2)`
///
/// # Arguments
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait HfenceGvmaEmitter<T0, T1> {
    fn hfence_gvma(&mut self, rs1: T0, rs2: T1);
}

/// RISC-V `hfence.vvma` instruction.
///
/// # Forms
/// Assembly: `hfence.vvma xs1, xs2`
/// Rust: `hfence_vvma(rs1, rs2)`
///
/// # Arguments
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait HfenceVvmaEmitter<T0, T1> {
    fn hfence_vvma(&mut self, rs1: T0, rs2: T1);
}

/// Invalidate cached address translations
///
/// `hinval.gvma` has the same semantics as `sinval.vma` except that it combines with
/// `sfence.w.inval` and `sfence.inval.ir` to replace `hfence.gvma` and uses VMID instead of ASID.
///
/// # Forms
/// Assembly: `hinval.gvma xs1, xs2`
/// Rust: `hinval_gvma(rs1, rs2)`
///
/// # Arguments
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait HinvalGvmaEmitter<T0, T1> {
    fn hinval_gvma(&mut self, rs1: T0, rs2: T1);
}

/// Invalidate cached address translations
///
/// `hinval.vvma` has the same semantics as `sinval.vma` except that it combines with
/// `sfence.w.inval` and `sfence.inval.ir` to replace `hfence.vvma`.
///
/// # Forms
/// Assembly: `hinval.vvma xs1, xs2`
/// Rust: `hinval_vvma(rs1, rs2)`
///
/// # Arguments
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait HinvalVvmaEmitter<T0, T1> {
    fn hinval_vvma(&mut self, rs1: T0, rs2: T1);
}

/// RISC-V `hlv.b` instruction.
///
/// # Forms
/// Assembly: `hlv.b xd, xs1`
/// Rust: `hlv_b(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait HlvBEmitter<T0, T1> {
    fn hlv_b(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `hlv.bu` instruction.
///
/// # Forms
/// Assembly: `hlv.bu xd, xs1`
/// Rust: `hlv_bu(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait HlvBuEmitter<T0, T1> {
    fn hlv_bu(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `hlv.d` instruction.
///
/// # Forms
/// Assembly: `hlv.d xd, xs1`
/// Rust: `hlv_d(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait HlvDEmitter<T0, T1> {
    fn hlv_d(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `hlv.h` instruction.
///
/// # Forms
/// Assembly: `hlv.h xd, xs1`
/// Rust: `hlv_h(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait HlvHEmitter<T0, T1> {
    fn hlv_h(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `hlv.hu` instruction.
///
/// # Forms
/// Assembly: `hlv.hu xd, xs1`
/// Rust: `hlv_hu(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait HlvHuEmitter<T0, T1> {
    fn hlv_hu(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `hlv.w` instruction.
///
/// # Forms
/// Assembly: `hlv.w xd, xs1`
/// Rust: `hlv_w(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait HlvWEmitter<T0, T1> {
    fn hlv_w(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `hlv.wu` instruction.
///
/// # Forms
/// Assembly: `hlv.wu xd, xs1`
/// Rust: `hlv_wu(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait HlvWuEmitter<T0, T1> {
    fn hlv_wu(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `hlvx.hu` instruction.
///
/// # Forms
/// Assembly: `hlvx.hu xd, xs1`
/// Rust: `hlvx_hu(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait HlvxHuEmitter<T0, T1> {
    fn hlvx_hu(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `hlvx.wu` instruction.
///
/// # Forms
/// Assembly: `hlvx.wu xd, xs1`
/// Rust: `hlvx_wu(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait HlvxWuEmitter<T0, T1> {
    fn hlvx_wu(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `hsv.b` instruction.
///
/// # Forms
/// Assembly: `hsv.b xs1, xs2`
/// Rust: `hsv_b(rs1, rs2)`
///
/// # Arguments
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait HsvBEmitter<T0, T1> {
    fn hsv_b(&mut self, rs1: T0, rs2: T1);
}

/// RISC-V `hsv.d` instruction.
///
/// # Forms
/// Assembly: `hsv.d xs1, xs2`
/// Rust: `hsv_d(rs1, rs2)`
///
/// # Arguments
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait HsvDEmitter<T0, T1> {
    fn hsv_d(&mut self, rs1: T0, rs2: T1);
}

/// RISC-V `hsv.h` instruction.
///
/// # Forms
/// Assembly: `hsv.h xs1, xs2`
/// Rust: `hsv_h(rs1, rs2)`
///
/// # Arguments
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait HsvHEmitter<T0, T1> {
    fn hsv_h(&mut self, rs1: T0, rs2: T1);
}

/// RISC-V `hsv.w` instruction.
///
/// # Forms
/// Assembly: `hsv.w xs1, xs2`
/// Rust: `hsv_w(rs1, rs2)`
///
/// # Arguments
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait HsvWEmitter<T0, T1> {
    fn hsv_w(&mut self, rs1: T0, rs2: T1);
}

/// RISC-V `j` instruction.
///
/// # Forms
/// Assembly: `j jimm20`
/// Rust: `j(imm)`
///
/// # Arguments
/// - `imm` — Immediate encoding value.
pub trait JEmitter<T0> {
    fn j(&mut self, imm: T0);
}

/// Jump and link
///
/// Jump to a PC-relative offset and store the return
/// address in rd.
///
/// # Forms
/// Assembly: `jal xd, imm`
/// Rust: `jal(rd, imm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `imm` — Immediate encoding value.
pub trait JalEmitter<T0, T1> {
    fn jal(&mut self, rd: T0, imm: T1);
}

/// RISC-V `jal.pseudo` instruction.
///
/// # Forms
/// Assembly: `jal.pseudo jimm20`
/// Rust: `jal_pseudo(imm)`
///
/// # Arguments
/// - `imm` — Immediate encoding value.
pub trait JalPseudoEmitter<T0> {
    fn jal_pseudo(&mut self, imm: T0);
}

/// Jump and link register
///
/// Jump to an address formed by adding rs1
/// to a signed offset then clearing the least
/// significant bit, and store the return address
/// in rd.
///
/// # Forms
/// Assembly: `jalr xd, imm(rs1)`
/// Rust: `jalr(rd, rs1, imm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `imm` — Immediate encoding value.
pub trait JalrEmitter<T0, T1, T2> {
    fn jalr(&mut self, rd: T0, rs1: T1, imm: T2);
}

/// RISC-V `jalr.pseudo` instruction.
///
/// # Forms
/// Assembly: `jalr.pseudo rs1`
/// Rust: `jalr_pseudo(rs1)`
///
/// # Arguments
/// - `rs1` — Source register.
pub trait JalrPseudoEmitter<T0> {
    fn jalr_pseudo(&mut self, rs1: T0);
}

/// RISC-V `jr` instruction.
///
/// # Forms
/// Assembly: `jr rs1`
/// Rust: `jr(rs1)`
///
/// # Arguments
/// - `rs1` — Source register.
pub trait JrEmitter<T0> {
    fn jr(&mut self, rs1: T0);
}

/// Load byte
///
/// Load 8 bits of data into register `rd` from an
/// address formed by adding `rs1` to a signed offset.
/// Sign extend the result.
///
/// # Forms
/// Assembly: `lb xd, imm(rs1)`
/// Rust: `lb(rd, rs1, imm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Memory base register.
/// - `imm` — Immediate encoding value.
pub trait LbEmitter<T0, T1, T2> {
    fn lb(&mut self, rd: T0, rs1: T1, imm: T2);
}

/// Load byte unsigned
///
/// Load 8 bits of data into register `rd` from an
/// address formed by adding `rs1` to a signed offset.
/// Zero extend the result.
///
/// # Forms
/// Assembly: `lbu xd, imm(rs1)`
/// Rust: `lbu(rd, rs1, imm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Memory base register.
/// - `imm` — Immediate encoding value.
pub trait LbuEmitter<T0, T1, T2> {
    fn lbu(&mut self, rd: T0, rs1: T1, imm: T2);
}

/// Load doubleword
///
/// Load 64 bits of data into register `rd` from an
/// address formed by adding `rs1` to a signed offset.
///
/// # Forms
/// Assembly: `ld xd, imm(rs1)`
/// Rust: `ld(rd, rs1, imm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Memory base register.
/// - `imm` — Immediate encoding value.
pub trait LdEmitter<T0, T1, T2> {
    fn ld(&mut self, rd: T0, rs1: T1, imm: T2);
}

/// Load halfword
///
/// Load 16 bits of data into register `rd` from an
/// address formed by adding `rs1` to a signed offset.
/// Sign extend the result.
///
/// # Forms
/// Assembly: `lh xd, imm(rs1)`
/// Rust: `lh(rd, rs1, imm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Memory base register.
/// - `imm` — Immediate encoding value.
pub trait LhEmitter<T0, T1, T2> {
    fn lh(&mut self, rd: T0, rs1: T1, imm: T2);
}

/// Load halfword unsigned
///
/// Load 16 bits of data into register `rd` from an
/// address formed by adding `rs1` to a signed offset.
/// Zero extend the result.
///
/// # Forms
/// Assembly: `lhu xd, imm(rs1)`
/// Rust: `lhu(rd, rs1, imm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Memory base register.
/// - `imm` — Immediate encoding value.
pub trait LhuEmitter<T0, T1, T2> {
    fn lhu(&mut self, rd: T0, rs1: T1, imm: T2);
}

/// RISC-V `lpad` instruction.
///
/// # Forms
/// Assembly: `lpad imm`
/// Rust: `lpad(imm)`
///
/// # Arguments
/// - `imm` — Immediate encoding value.
pub trait LpadEmitter<T0> {
    fn lpad(&mut self, imm: T0);
}

/// Load reserved doubleword
///
/// Loads a word from the address in rs1, places the value in rd,
/// and registers a _reservation set_  -- a set of bytes that subsumes the bytes in the
/// addressed word.
///
/// The address in rs1 must be 8-byte aligned.
///
/// If the address is not naturally aligned, a `LoadAddressMisaligned` exception or an
/// `LoadAccessFault` exception will be generated. The access-fault exception can be generated
/// for a memory access that would otherwise be able to complete except for the misalignment,
/// if the misaligned access should not be emulated.
///
/// An implementation can register an arbitrarily large reservation set on each LR, provided the
/// reservation set includes all bytes of the addressed data word or doubleword.
/// An SC can only pair with the most recent LR in program order.
/// An SC may succeed only if no store from another hart to the reservation set can be
/// observed to have occurred between the LR and the SC, and if there is no other SC between the
/// LR and itself in program order.
/// An SC may succeed only if no write from a device other than a hart to the bytes accessed by
/// the LR instruction can be observed to have occurred between the LR and SC. Note this LR
/// might have had a different effective address and data size, but reserved the SC's
/// address as part of the reservation set.
///
/// \[NOTE\]
/// ----
/// Following this model, in systems with memory translation, an SC is allowed to succeed if the
/// earlier LR reserved the same location using an alias with a different virtual address, but is
/// also allowed to fail if the virtual address is different.
///
/// To accommodate legacy devices and buses, writes from devices other than RISC-V harts are only
/// required to invalidate reservations when they overlap the bytes accessed by the LR.
/// These writes are not required to invalidate the reservation when they access other bytes in
/// the reservation set.
/// ----
///
/// Software should not set the _rl_ bit on an LR instruction unless the _aq_ bit is also set.
/// LR.rl and SC.aq instructions are not guaranteed to provide any stronger ordering than those
/// with both bits clear, but may result in lower performance.
///
/// # Forms
/// Assembly: `lr.d xd, xs1`
/// Rust: `lr_d(rd, rs1, aq, rl)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Memory base register.
/// - `aq` — Acquire-order bit.
/// - `rl` — Release-order bit; retained for the existing emitter API.
pub trait LrDEmitter<T0, T1, T2, T3> {
    fn lr_d(&mut self, rd: T0, rs1: T1, aq: T2, rl: T3);
}

/// Load reserved word
///
/// Loads a word from the address in rs1, places the sign-extended value in rd,
/// and registers a _reservation set_  -- a set of bytes that subsumes the bytes in the
/// addressed word.
///
/// &lt;%- if XLEN == 64 -%&gt;
/// The 32-bit load result is sign-extended to 64-bits.
/// &lt;%- end -%&gt;
///
/// The address in rs1 must be naturally aligned to the size of the operand
/// (_i.e._, eight-byte aligned for doublewords and four-byte aligned for words).
///
/// If the address is not naturally aligned, a `LoadAddressMisaligned` exception or an
/// `LoadAccessFault` exception will be generated. The access-fault exception can be generated
/// for a memory access that would otherwise be able to complete except for the misalignment,
/// if the misaligned access should not be emulated.
///
/// An implementation can register an arbitrarily large reservation set on each LR, provided the
/// reservation set includes all bytes of the addressed data word or doubleword.
/// An SC can only pair with the most recent LR in program order.
/// An SC may succeed only if no store from another hart to the reservation set can be
/// observed to have occurred between the LR and the SC, and if there is no other SC between the
/// LR and itself in program order.
/// An SC may succeed only if no write from a device other than a hart to the bytes accessed by
/// the LR instruction can be observed to have occurred between the LR and SC. Note this LR
/// might have had a different effective address and data size, but reserved the SC's
/// address as part of the reservation set.
///
/// \[NOTE\]
/// ----
/// Following this model, in systems with memory translation, an SC is allowed to succeed if the
/// earlier LR reserved the same location using an alias with a different virtual address, but is
/// also allowed to fail if the virtual address is different.
///
/// To accommodate legacy devices and buses, writes from devices other than RISC-V harts are only
/// required to invalidate reservations when they overlap the bytes accessed by the LR.
/// These writes are not required to invalidate the reservation when they access other bytes in
/// the reservation set.
/// ----
///
/// Software should not set the _rl_ bit on an LR instruction unless the _aq_ bit is also set.
/// LR.rl and SC.aq instructions are not guaranteed to provide any stronger ordering than those
/// with both bits clear, but may result in lower performance.
///
/// # Forms
/// Assembly: `lr.w xd, xs1`
/// Rust: `lr_w(rd, rs1, aq, rl)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Memory base register.
/// - `aq` — Acquire-order bit.
/// - `rl` — Release-order bit; retained for the existing emitter API.
pub trait LrWEmitter<T0, T1, T2, T3> {
    fn lr_w(&mut self, rd: T0, rs1: T1, aq: T2, rl: T3);
}

/// Load upper immediate
///
/// Load the zero-extended imm into rd.
///
/// # Forms
/// Assembly: `lui xd, imm`
/// Rust: `lui(rd, imm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `imm` — Immediate encoding value.
pub trait LuiEmitter<T0, T1> {
    fn lui(&mut self, rd: T0, imm: T1);
}

/// Load word
///
/// Load 32 bits of data into register `rd` from an
/// address formed by adding `rs1` to a signed offset.
/// Sign extend the result.
///
/// # Forms
/// Assembly: `lw xd, imm(rs1)`
/// Rust: `lw(rd, rs1, imm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Memory base register.
/// - `imm` — Immediate encoding value.
pub trait LwEmitter<T0, T1, T2> {
    fn lw(&mut self, rd: T0, rs1: T1, imm: T2);
}

/// Load word unsigned
///
/// Load 64 bits of data into register `rd` from an
/// address formed by adding `rs1` to a signed offset.
/// Zero extend the result.
///
/// # Forms
/// Assembly: `lwu xd, imm(rs1)`
/// Rust: `lwu(rd, rs1, imm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Memory base register.
/// - `imm` — Immediate encoding value.
pub trait LwuEmitter<T0, T1, T2> {
    fn lwu(&mut self, rd: T0, rs1: T1, imm: T2);
}

/// Maximum
///
/// This instruction returns the larger of two signed integers.
///
/// .Software Hint
/// \[NOTE\]
/// Calculating the absolute value of a signed integer can be performed using the
/// following sequence: `neg rD,rS` followed by `max rD,rS,rD. When using this
/// common sequence, it is suggested that they are scheduled with no intervening
/// instructions so that implementations that are so optimized can fuse them
/// together.
///
/// # Forms
/// Assembly: `max xd, xs1, xs2`
/// Rust: `max(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait MaxEmitter<T0, T1, T2> {
    fn max(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// Unsigned maximum
///
/// This instruction returns the larger of two unsigned integers.
///
/// # Forms
/// Assembly: `maxu xd, xs1, xs2`
/// Rust: `maxu(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait MaxuEmitter<T0, T1, T2> {
    fn maxu(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// Minimum
///
/// This instruction returns the smaller of two signed integers.
///
/// # Forms
/// Assembly: `min xd, xs1, xs2`
/// Rust: `min(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait MinEmitter<T0, T1, T2> {
    fn min(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// Unsigned minimum
///
/// This instruction returns the smaller of two unsigned integers.
///
/// # Forms
/// Assembly: `minu xd, xs1, xs2`
/// Rust: `minu(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait MinuEmitter<T0, T1, T2> {
    fn minu(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `mnret` instruction.
///
/// # Forms
/// Assembly: `mnret mnret`
/// Rust: `mnret()`
///
/// # Arguments
pub trait MnretEmitter {
    fn mnret(&mut self);
}

/// RISC-V `mop.r.0` instruction.
///
/// # Forms
/// Assembly: `mop.r.0 rd rs1`
/// Rust: `mop_r_0(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait MopR0Emitter<T0, T1> {
    fn mop_r_0(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `mop.r.1` instruction.
///
/// # Forms
/// Assembly: `mop.r.1 rd rs1`
/// Rust: `mop_r_1(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait MopR1Emitter<T0, T1> {
    fn mop_r_1(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `mop.r.10` instruction.
///
/// # Forms
/// Assembly: `mop.r.10 rd rs1`
/// Rust: `mop_r_10(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait MopR10Emitter<T0, T1> {
    fn mop_r_10(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `mop.r.11` instruction.
///
/// # Forms
/// Assembly: `mop.r.11 rd rs1`
/// Rust: `mop_r_11(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait MopR11Emitter<T0, T1> {
    fn mop_r_11(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `mop.r.12` instruction.
///
/// # Forms
/// Assembly: `mop.r.12 rd rs1`
/// Rust: `mop_r_12(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait MopR12Emitter<T0, T1> {
    fn mop_r_12(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `mop.r.13` instruction.
///
/// # Forms
/// Assembly: `mop.r.13 rd rs1`
/// Rust: `mop_r_13(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait MopR13Emitter<T0, T1> {
    fn mop_r_13(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `mop.r.14` instruction.
///
/// # Forms
/// Assembly: `mop.r.14 rd rs1`
/// Rust: `mop_r_14(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait MopR14Emitter<T0, T1> {
    fn mop_r_14(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `mop.r.15` instruction.
///
/// # Forms
/// Assembly: `mop.r.15 rd rs1`
/// Rust: `mop_r_15(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait MopR15Emitter<T0, T1> {
    fn mop_r_15(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `mop.r.16` instruction.
///
/// # Forms
/// Assembly: `mop.r.16 rd rs1`
/// Rust: `mop_r_16(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait MopR16Emitter<T0, T1> {
    fn mop_r_16(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `mop.r.17` instruction.
///
/// # Forms
/// Assembly: `mop.r.17 rd rs1`
/// Rust: `mop_r_17(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait MopR17Emitter<T0, T1> {
    fn mop_r_17(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `mop.r.18` instruction.
///
/// # Forms
/// Assembly: `mop.r.18 rd rs1`
/// Rust: `mop_r_18(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait MopR18Emitter<T0, T1> {
    fn mop_r_18(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `mop.r.19` instruction.
///
/// # Forms
/// Assembly: `mop.r.19 rd rs1`
/// Rust: `mop_r_19(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait MopR19Emitter<T0, T1> {
    fn mop_r_19(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `mop.r.2` instruction.
///
/// # Forms
/// Assembly: `mop.r.2 rd rs1`
/// Rust: `mop_r_2(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait MopR2Emitter<T0, T1> {
    fn mop_r_2(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `mop.r.20` instruction.
///
/// # Forms
/// Assembly: `mop.r.20 rd rs1`
/// Rust: `mop_r_20(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait MopR20Emitter<T0, T1> {
    fn mop_r_20(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `mop.r.21` instruction.
///
/// # Forms
/// Assembly: `mop.r.21 rd rs1`
/// Rust: `mop_r_21(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait MopR21Emitter<T0, T1> {
    fn mop_r_21(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `mop.r.22` instruction.
///
/// # Forms
/// Assembly: `mop.r.22 rd rs1`
/// Rust: `mop_r_22(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait MopR22Emitter<T0, T1> {
    fn mop_r_22(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `mop.r.23` instruction.
///
/// # Forms
/// Assembly: `mop.r.23 rd rs1`
/// Rust: `mop_r_23(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait MopR23Emitter<T0, T1> {
    fn mop_r_23(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `mop.r.24` instruction.
///
/// # Forms
/// Assembly: `mop.r.24 rd rs1`
/// Rust: `mop_r_24(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait MopR24Emitter<T0, T1> {
    fn mop_r_24(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `mop.r.25` instruction.
///
/// # Forms
/// Assembly: `mop.r.25 rd rs1`
/// Rust: `mop_r_25(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait MopR25Emitter<T0, T1> {
    fn mop_r_25(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `mop.r.26` instruction.
///
/// # Forms
/// Assembly: `mop.r.26 rd rs1`
/// Rust: `mop_r_26(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait MopR26Emitter<T0, T1> {
    fn mop_r_26(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `mop.r.27` instruction.
///
/// # Forms
/// Assembly: `mop.r.27 rd rs1`
/// Rust: `mop_r_27(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait MopR27Emitter<T0, T1> {
    fn mop_r_27(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `mop.r.28` instruction.
///
/// # Forms
/// Assembly: `mop.r.28 rd rs1`
/// Rust: `mop_r_28(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait MopR28Emitter<T0, T1> {
    fn mop_r_28(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `mop.r.29` instruction.
///
/// # Forms
/// Assembly: `mop.r.29 rd rs1`
/// Rust: `mop_r_29(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait MopR29Emitter<T0, T1> {
    fn mop_r_29(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `mop.r.3` instruction.
///
/// # Forms
/// Assembly: `mop.r.3 rd rs1`
/// Rust: `mop_r_3(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait MopR3Emitter<T0, T1> {
    fn mop_r_3(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `mop.r.30` instruction.
///
/// # Forms
/// Assembly: `mop.r.30 rd rs1`
/// Rust: `mop_r_30(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait MopR30Emitter<T0, T1> {
    fn mop_r_30(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `mop.r.31` instruction.
///
/// # Forms
/// Assembly: `mop.r.31 rd rs1`
/// Rust: `mop_r_31(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait MopR31Emitter<T0, T1> {
    fn mop_r_31(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `mop.r.4` instruction.
///
/// # Forms
/// Assembly: `mop.r.4 rd rs1`
/// Rust: `mop_r_4(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait MopR4Emitter<T0, T1> {
    fn mop_r_4(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `mop.r.5` instruction.
///
/// # Forms
/// Assembly: `mop.r.5 rd rs1`
/// Rust: `mop_r_5(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait MopR5Emitter<T0, T1> {
    fn mop_r_5(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `mop.r.6` instruction.
///
/// # Forms
/// Assembly: `mop.r.6 rd rs1`
/// Rust: `mop_r_6(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait MopR6Emitter<T0, T1> {
    fn mop_r_6(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `mop.r.7` instruction.
///
/// # Forms
/// Assembly: `mop.r.7 rd rs1`
/// Rust: `mop_r_7(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait MopR7Emitter<T0, T1> {
    fn mop_r_7(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `mop.r.8` instruction.
///
/// # Forms
/// Assembly: `mop.r.8 rd rs1`
/// Rust: `mop_r_8(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait MopR8Emitter<T0, T1> {
    fn mop_r_8(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `mop.r.9` instruction.
///
/// # Forms
/// Assembly: `mop.r.9 rd rs1`
/// Rust: `mop_r_9(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait MopR9Emitter<T0, T1> {
    fn mop_r_9(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `mop.rr.0` instruction.
///
/// # Forms
/// Assembly: `mop.rr.0 rd rs1 rs2`
/// Rust: `mop_rr_0(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait MopRr0Emitter<T0, T1, T2> {
    fn mop_rr_0(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `mop.rr.1` instruction.
///
/// # Forms
/// Assembly: `mop.rr.1 rd rs1 rs2`
/// Rust: `mop_rr_1(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait MopRr1Emitter<T0, T1, T2> {
    fn mop_rr_1(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `mop.rr.2` instruction.
///
/// # Forms
/// Assembly: `mop.rr.2 rd rs1 rs2`
/// Rust: `mop_rr_2(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait MopRr2Emitter<T0, T1, T2> {
    fn mop_rr_2(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `mop.rr.3` instruction.
///
/// # Forms
/// Assembly: `mop.rr.3 rd rs1 rs2`
/// Rust: `mop_rr_3(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait MopRr3Emitter<T0, T1, T2> {
    fn mop_rr_3(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `mop.rr.4` instruction.
///
/// # Forms
/// Assembly: `mop.rr.4 rd rs1 rs2`
/// Rust: `mop_rr_4(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait MopRr4Emitter<T0, T1, T2> {
    fn mop_rr_4(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `mop.rr.5` instruction.
///
/// # Forms
/// Assembly: `mop.rr.5 rd rs1 rs2`
/// Rust: `mop_rr_5(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait MopRr5Emitter<T0, T1, T2> {
    fn mop_rr_5(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `mop.rr.6` instruction.
///
/// # Forms
/// Assembly: `mop.rr.6 rd rs1 rs2`
/// Rust: `mop_rr_6(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait MopRr6Emitter<T0, T1, T2> {
    fn mop_rr_6(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `mop.rr.7` instruction.
///
/// # Forms
/// Assembly: `mop.rr.7 rd rs1 rs2`
/// Rust: `mop_rr_7(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait MopRr7Emitter<T0, T1, T2> {
    fn mop_rr_7(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// Machine Exception Return
///
/// Returns from an exception in M-mode.
///
/// # Forms
/// Assembly: `mret ""`
/// Rust: `mret()`
///
/// # Arguments
pub trait MretEmitter {
    fn mret(&mut self);
}

/// Signed multiply
///
/// MUL performs an XLEN-bitxXLEN-bit multiplication of `rs1` by `rs2` and places the lower
/// XLEN bits in the destination register.
/// Any overflow is thrown away.
///
/// \[NOTE\]
/// If both the high and low bits of the same product are required, then the recommended code
/// sequence is:
/// MULH\[\[S\]U\] rdh, rs1, rs2; MUL rdl, rs1, rs2
/// (source register specifiers must be in same order and rdh cannot be the same as rs1 or rs2).
/// Microarchitectures can then fuse these into a single multiply operation instead of
/// performing two separate multiplies.
///
/// # Forms
/// Assembly: `mul xd, xs1, xs2`
/// Rust: `mul(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait MulEmitter<T0, T1, T2> {
    fn mul(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// Signed multiply high
///
/// Multiply the signed values in rs1 to rs2, and store the upper half of the result in rd.
/// The lower half is thrown away.
///
/// If both the upper and lower halves are needed, it suggested to use the sequence:
///
/// ---
///   mulh rdh, rs1, rs2
///   mul  rdl, rs1, rs2
/// ---
///
/// Microarchitectures may look for that sequence and fuse the operations.
///
/// # Forms
/// Assembly: `mulh xd, xs1, xs2`
/// Rust: `mulh(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait MulhEmitter<T0, T1, T2> {
    fn mulh(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// Signed/unsigned multiply high
///
/// Multiply the signed value in rs1 by the unsigned value in rs2, and store the upper half of the result in rd.
/// The lower half is thrown away.
///
/// If both the upper and lower halves are needed, it suggested to use the sequence:
///
/// ---
///   mulhsu rdh, rs1, rs2
///   mul    rdl, rs1, rs2
/// ---
///
/// Microarchitectures may look for that sequence and fuse the operations.
///
/// # Forms
/// Assembly: `mulhsu xd, xs1, xs2`
/// Rust: `mulhsu(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait MulhsuEmitter<T0, T1, T2> {
    fn mulhsu(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// Unsigned multiply high
///
/// Multiply the unsigned values in rs1 to rs2, and store the upper half of the result in rd.
/// The lower half is thrown away.
///
/// If both the upper and lower halves are needed, it suggested to use the sequence:
///
/// ---
///   mulhu rdh, rs1, rs2
///   mul   rdl, rs1, rs2
/// ---
///
/// Microarchitectures may look for that sequence and fuse the operations.
///
/// # Forms
/// Assembly: `mulhu xd, xs1, xs2`
/// Rust: `mulhu(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait MulhuEmitter<T0, T1, T2> {
    fn mulhu(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// Signed 32-bit multiply
///
/// Multiplies the lower 32 bits of the source registers, placing the sign-extension of the
/// lower 32 bits of the result into the destination register.
///
/// Any overflow is thrown away.
///
/// \[NOTE\]
/// In RV64, MUL can be used to obtain the upper 32 bits of the 64-bit product,
/// but signed arguments must be proper 32-bit signed values, whereas unsigned arguments
/// must have their upper 32 bits clear. If the arguments are not known to be sign- or zero-extended,
/// an alternative is to shift both arguments left by 32 bits, then use MULH\[\[S\]U\].
///
/// # Forms
/// Assembly: `mulw xd, xs1, xs2`
/// Rust: `mulw(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait MulwEmitter<T0, T1, T2> {
    fn mulw(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `mv` instruction.
///
/// # Forms
/// Assembly: `mv rd rs1`
/// Rust: `mv(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait MvEmitter<T0, T1> {
    fn mv(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `neg` instruction.
///
/// # Forms
/// Assembly: `neg rd rs1`
/// Rust: `neg(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait NegEmitter<T0, T1> {
    fn neg(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `nop` instruction.
///
/// # Forms
/// Assembly: `nop`
/// Rust: `nop()`
///
/// # Arguments
pub trait NopEmitter {
    fn nop(&mut self);
}

/// RISC-V `ntl.all` instruction.
///
/// # Forms
/// Assembly: `ntl.all`
/// Rust: `ntl_all()`
///
/// # Arguments
pub trait NtlAllEmitter {
    fn ntl_all(&mut self);
}

/// RISC-V `ntl.p1` instruction.
///
/// # Forms
/// Assembly: `ntl.p1`
/// Rust: `ntl_p1()`
///
/// # Arguments
pub trait NtlP1Emitter {
    fn ntl_p1(&mut self);
}

/// RISC-V `ntl.pall` instruction.
///
/// # Forms
/// Assembly: `ntl.pall`
/// Rust: `ntl_pall()`
///
/// # Arguments
pub trait NtlPallEmitter {
    fn ntl_pall(&mut self);
}

/// RISC-V `ntl.s1` instruction.
///
/// # Forms
/// Assembly: `ntl.s1`
/// Rust: `ntl_s1()`
///
/// # Arguments
pub trait NtlS1Emitter {
    fn ntl_s1(&mut self);
}

/// Or
///
/// Or rs1 with rs2, and store the result in rd
///
/// # Forms
/// Assembly: `or xd, xs1, xs2`
/// Rust: `or(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait OrEmitter<T0, T1, T2> {
    fn or(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// Bitware OR-combine, byte granule
///
/// Combines the bits within each byte using bitwise logical OR. This sets the bits
/// of each byte in the result rd to all zeros if no bit within the respective byte
/// of rs is set, or to all ones if any bit within the respective byte of rs is set.
///
/// # Forms
/// Assembly: `orc.b xd, xs1, xs2`
/// Rust: `orc_b(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait OrcBEmitter<T0, T1> {
    fn orc_b(&mut self, rd: T0, rs1: T1);
}

/// Or immediate
///
/// Or an immediate to the value in rs1, and store the result in rd
///
/// # Forms
/// Assembly: `ori xd, xs1, imm`
/// Rust: `ori(rd, rs1, imm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `imm` — Immediate encoding value.
pub trait OriEmitter<T0, T1, T2> {
    fn ori(&mut self, rd: T0, rs1: T1, imm: T2);
}

/// OR with inverted operand
///
/// This instruction performs the bitwise logical OR operation between rs1 and the bitwise inversion of rs2.
///
/// # Forms
/// Assembly: `orn xd, xs1, xs2`
/// Rust: `orn(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait OrnEmitter<T0, T1, T2> {
    fn orn(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `pack` instruction.
///
/// # Forms
/// Assembly: `pack xd, xs1, xs2`
/// Rust: `pack(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait PackEmitter<T0, T1, T2> {
    fn pack(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `packh` instruction.
///
/// # Forms
/// Assembly: `packh xd, xs1, xs2`
/// Rust: `packh(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait PackhEmitter<T0, T1, T2> {
    fn packh(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `packw` instruction.
///
/// # Forms
/// Assembly: `packw xd, xs1, xs2`
/// Rust: `packw(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait PackwEmitter<T0, T1, T2> {
    fn packw(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `pause` instruction.
///
/// # Forms
/// Assembly: `pause`
/// Rust: `pause()`
///
/// # Arguments
pub trait PauseEmitter {
    fn pause(&mut self);
}

/// RISC-V `prefetch.i` instruction.
///
/// # Forms
/// Assembly: `prefetch.i rs1 imm12lohi`
/// Rust: `prefetch_i(rs1, imm)`
///
/// # Arguments
/// - `rs1` — Source register.
/// - `imm` — Immediate encoding value.
pub trait PrefetchIEmitter<T0, T1> {
    fn prefetch_i(&mut self, rs1: T0, imm: T1);
}

/// RISC-V `prefetch.r` instruction.
///
/// # Forms
/// Assembly: `prefetch.r rs1 imm12lohi`
/// Rust: `prefetch_r(rs1, imm)`
///
/// # Arguments
/// - `rs1` — Source register.
/// - `imm` — Immediate encoding value.
pub trait PrefetchREmitter<T0, T1> {
    fn prefetch_r(&mut self, rs1: T0, imm: T1);
}

/// RISC-V `prefetch.w` instruction.
///
/// # Forms
/// Assembly: `prefetch.w rs1 imm12lohi`
/// Rust: `prefetch_w(rs1, imm)`
///
/// # Arguments
/// - `rs1` — Source register.
/// - `imm` — Immediate encoding value.
pub trait PrefetchWEmitter<T0, T1> {
    fn prefetch_w(&mut self, rs1: T0, imm: T1);
}

/// RISC-V `rdcycle` instruction.
///
/// # Forms
/// Assembly: `rdcycle rd`
/// Rust: `rdcycle(rd)`
///
/// # Arguments
/// - `rd` — Destination register.
pub trait RdcycleEmitter<T0> {
    fn rdcycle(&mut self, rd: T0);
}

/// RISC-V `rdcycleh` instruction.
///
/// # Forms
/// Assembly: `rdcycleh rd`
/// Rust: `rdcycleh(rd)`
///
/// # Arguments
/// - `rd` — Destination register.
pub trait RdcyclehEmitter<T0> {
    fn rdcycleh(&mut self, rd: T0);
}

/// RISC-V `rdinstret` instruction.
///
/// # Forms
/// Assembly: `rdinstret rd`
/// Rust: `rdinstret(rd)`
///
/// # Arguments
/// - `rd` — Destination register.
pub trait RdinstretEmitter<T0> {
    fn rdinstret(&mut self, rd: T0);
}

/// RISC-V `rdinstreth` instruction.
///
/// # Forms
/// Assembly: `rdinstreth rd`
/// Rust: `rdinstreth(rd)`
///
/// # Arguments
/// - `rd` — Destination register.
pub trait RdinstrethEmitter<T0> {
    fn rdinstreth(&mut self, rd: T0);
}

/// RISC-V `rdtime` instruction.
///
/// # Forms
/// Assembly: `rdtime rd`
/// Rust: `rdtime(rd)`
///
/// # Arguments
/// - `rd` — Destination register.
pub trait RdtimeEmitter<T0> {
    fn rdtime(&mut self, rd: T0);
}

/// RISC-V `rdtimeh` instruction.
///
/// # Forms
/// Assembly: `rdtimeh rd`
/// Rust: `rdtimeh(rd)`
///
/// # Arguments
/// - `rd` — Destination register.
pub trait RdtimehEmitter<T0> {
    fn rdtimeh(&mut self, rd: T0);
}

/// Signed remainder
///
/// Calculate the remainder of signed division of rs1 by rs2, and store the result in rd.
///
/// If the value in register rs2 is zero, write the value in rs1 into rd;
///
/// If the result of the division overflows, write zero into rd;
///
/// # Forms
/// Assembly: `rem xd, xs1, xs2`
/// Rust: `rem(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait RemEmitter<T0, T1, T2> {
    fn rem(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// Unsigned remainder
///
/// Calculate the remainder of unsigned division of rs1 by rs2, and store the result in rd.
///
/// # Forms
/// Assembly: `remu xd, xs1, xs2`
/// Rust: `remu(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait RemuEmitter<T0, T1, T2> {
    fn remu(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// Unsigned 32-bit remainder
///
/// Calculate the remainder of unsigned division of the 32-bit values in rs1 by rs2,
/// and store the sign-extended result in rd.
///
/// If the value in rs2 is zero, rd gets the sign-extended value in rs1.
///
/// # Forms
/// Assembly: `remuw xd, xs1, xs2`
/// Rust: `remuw(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait RemuwEmitter<T0, T1, T2> {
    fn remuw(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// Signed 32-bit remainder
///
/// Calculate the remainder of signed division of the 32-bit values rs1 by rs2,
/// and store the sign-extended result in rd.
///
/// If the value in register rs2 is zero, write the sign-extended 32-bit value in rs1 into rd;
///
/// If the result of the division overflows, write zero into rd;
///
/// # Forms
/// Assembly: `remw xd, xs1, xs2`
/// Rust: `remw(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait RemwEmitter<T0, T1, T2> {
    fn remw(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `ret` instruction.
///
/// # Forms
/// Assembly: `ret`
/// Rust: `ret()`
///
/// # Arguments
pub trait RetEmitter {
    fn ret(&mut self);
}

/// Byte-reverse register (RV64 encoding)
///
/// This instruction reverses the order of the bytes in rs1.
///
/// \[NOTE\]
/// The rev8 mnemonic corresponds to different instruction encodings in RV32 and RV64.
///
/// \[NOTE\]
/// The byte-reverse operation is only available for the full register width. To emulate word-sized
/// and halfword-sized byte-reversal, perform a `rev8 rd,rs` followed by a `srai rd,rd,K`, where K
/// is XLEN-32 and XLEN-16, respectively.
///
/// # Forms
/// Assembly: `rev8 xd, xs1`
/// Rust: `rev8(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait Rev8Emitter<T0, T1> {
    fn rev8(&mut self, rd: T0, rs1: T1);
}

/// Byte-reverse register (RV64 encoding)
///
/// This instruction reverses the order of the bytes in rs1.
///
/// \[NOTE\]
/// The rev8 mnemonic corresponds to different instruction encodings in RV32 and RV64.
///
/// \[NOTE\]
/// The byte-reverse operation is only available for the full register width. To emulate word-sized
/// and halfword-sized byte-reversal, perform a `rev8 rd,rs` followed by a `srai rd,rd,K`, where K
/// is XLEN-32 and XLEN-16, respectively.
///
/// # Forms
/// Assembly: `rev8.rv32 xd, xs1`
/// Rust: `rev8_rv32(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait Rev8Rv32Emitter<T0, T1> {
    fn rev8_rv32(&mut self, rd: T0, rs1: T1);
}

/// Rotate left (Register)
///
/// This instruction performs a rotate left of rs1 by the amount in least-significant `log2(XLEN)` bits of rs2.
///
/// # Forms
/// Assembly: `rol xd, xs1, xs2`
/// Rust: `rol(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait RolEmitter<T0, T1, T2> {
    fn rol(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// Rotate left word (Register)
///
/// This instruction performs a rotate left of the least-significant word of rs1 by the amount in least-significant 5 bits of rs2.
/// The resulting word value is sign-extended by copying bit 31 to all of the more-significant bits.
///
/// # Forms
/// Assembly: `rolw xd, xs1, xs2`
/// Rust: `rolw(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait RolwEmitter<T0, T1, T2> {
    fn rolw(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// Rotate right (Register)
///
/// This instruction performs a rotate right of rs1 by the amount in least-significant `log2(XLEN)` bits of rs2.
///
/// # Forms
/// Assembly: `ror xd, xs1, xs2`
/// Rust: `ror(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait RorEmitter<T0, T1, T2> {
    fn ror(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// Rotate right (Immediate)
///
/// This instruction performs a rotate right of rs1 by the amount in the least-significant log2(XLEN) bits of shamt.
/// For RV32, the encodings corresponding to shamt\[5\]=1 are reserved.
///
/// # Forms
/// Assembly: `rori xd, xs1, shamt`
/// Rust: `rori(rd, rs1, shamtd)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `shamtd` — Immediate encoding value.
pub trait RoriEmitter<T0, T1, T2> {
    fn rori(&mut self, rd: T0, rs1: T1, shamtd: T2);
}

/// Rotate right (Immediate)
///
/// This instruction performs a rotate right of rs1 by the amount in the least-significant log2(XLEN) bits of shamt.
/// For RV32, the encodings corresponding to shamt\[5\]=1 are reserved.
///
/// # Forms
/// Assembly: `rori.rv32 xd, xs1, shamt`
/// Rust: `rori_rv32(rd, rs1, shamtw)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `shamtw` — Immediate encoding value.
pub trait RoriRv32Emitter<T0, T1, T2> {
    fn rori_rv32(&mut self, rd: T0, rs1: T1, shamtw: T2);
}

/// Rotate right word (Immediate)
///
/// This instruction performs a rotate right on the least-significant word of rs1 by the amount in
/// the least-significant log2(XLEN) bits of shamt. The resulting word value is sign-extended by
/// copying bit 31 to all of the more-significant bits.
///
/// # Forms
/// Assembly: `roriw xd, xs1, shamt`
/// Rust: `roriw(rd, rs1, shamtw)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `shamtw` — Immediate encoding value.
pub trait RoriwEmitter<T0, T1, T2> {
    fn roriw(&mut self, rd: T0, rs1: T1, shamtw: T2);
}

/// Rotate right word (Register)
///
/// This instruction performs a rotate right on the least-significant word of rs1 by the amount in
/// least-significant 5 bits of rs2. The resultant word is sign-extended by copying bit 31 to all
/// of the more-significant bits.
///
/// # Forms
/// Assembly: `rorw xd, xs1, xs2`
/// Rust: `rorw(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait RorwEmitter<T0, T1, T2> {
    fn rorw(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// Store byte
///
/// Store 8 bits of data from register `rs2` to an
/// address formed by adding `rs1` to a signed offset.
///
/// # Forms
/// Assembly: `sb xs2, imm(xs1)`
/// Rust: `sb(rs1, rs2, imm)`
///
/// # Arguments
/// - `rs1` — Memory base register.
/// - `rs2` — Source register.
/// - `imm` — Immediate encoding value.
pub trait SbEmitter<T0, T1, T2> {
    fn sb(&mut self, rs1: T0, rs2: T1, imm: T2);
}

/// RISC-V `sbreak` instruction.
///
/// # Forms
/// Assembly: `sbreak`
/// Rust: `sbreak()`
///
/// # Arguments
pub trait SbreakEmitter {
    fn sbreak(&mut self);
}

/// Store conditional doubleword
///
/// `sc.d` conditionally writes a doubleword in _rs2_ to the address in _rs1_:
/// the `sc.d` succeeds only if the reservation is still valid and the
/// reservation set contains the bytes being written. If the `sc.d` succeeds,
/// the instruction writes the doubleword in _rs2_ to memory, and it writes zero to _rd_.
/// If the `sc.d` fails, the instruction does not write to memory, and it writes a
/// nonzero value to _rd_. For the purposes of memory protection, a failed `sc.d`
/// may be treated like a store. Regardless of success or failure, executing an
/// `sc.d` instruction invalidates any reservation held by this hart.
///
/// The failure code with value 1 encodes an unspecified failure.
/// Other failure codes are reserved at this time.
/// Portable software should only assume the failure code will be non-zero.
///
/// The address held in _rs1_ must be naturally aligned to the size of the operand
/// (_i.e._, eight-byte aligned).
/// If the address is not naturally aligned, an address-misaligned exception or an
/// access-fault exception will be generated.
/// The access-fault exception can be generated for a memory access that would otherwise
/// be able to complete except for the misalignment,
/// if the misaligned access should not be emulated.
///
/// \[NOTE\]
/// --
/// Emulating misaligned LR/SC sequences is impractical in most systems.
///
/// Misaligned LR/SC sequences also raise the possibility of accessing multiple
/// reservation sets at once, which present definitions do not provide for.
/// --
///
/// An implementation can register an arbitrarily large reservation set on each LR,
/// provided the reservation set includes all bytes of the addressed data word or
/// doubleword.
/// An SC can only pair with the most recent LR in program order.
/// An SC may succeed only if no store from another hart to the reservation set
/// can be observed to have occurred between the LR and the SC,
/// and if there is no other SC between the LR and itself in program order.
/// An SC may succeed only if no write from a device other than a hart to the bytes
/// accessed by the LR instruction can be observed to have occurred between the LR
/// and SC.
/// Note this LR might have had a different effective address and data size,
/// but reserved the SC's address as part of the reservation set.
///
/// \[NOTE\]
/// ----
/// Following this model, in systems with memory translation, an SC is allowed to succeed if the
/// earlier LR reserved the same location using an alias with a different virtual address, but is
/// also allowed to fail if the virtual address is different.
///
/// To accommodate legacy devices and buses, writes from devices other than RISC-V harts are only
/// required to invalidate reservations when they overlap the bytes accessed by the LR.
/// These writes are not required to invalidate the reservation when they access other bytes in
/// the reservation set.
/// ----
///
/// The SC must fail if the address is not within the reservation set of the most
/// recent LR in program order.
/// The SC must fail if a store to the reservation set from another hart can be
/// observed to occur between the LR and SC.
/// The SC must fail if a write from some other device to the bytes accessed by the
/// LR can be observed to occur between the LR and SC.
/// (If such a device writes the reservation set but does not write the bytes accessed
/// by the LR, the SC may or may not fail.)
/// An SC must fail if there is another SC (to any address) between the LR and the SC
/// in program order.
/// The precise statement of the atomicity requirements for successful LR/SC sequences
/// is defined by the Atomicity Axiom of the memory model.
///
/// \[NOTE\]
/// --
/// The platform should provide a means to determine the size and shape of the reservation set.
///
/// A platform specification may constrain the size and shape of the reservation set.
///
/// A store-conditional instruction to a scratch word of memory should be used to forcibly invalidate any existing load reservation:
///
///   * during a preemptive context switch, and
///   * if necessary when changing virtual to physical address mappings, such as when migrating pages that might contain an active reservation.
///
/// The invalidation of a hart's reservation when it executes an LR or SC imply that a hart can only hold one reservation at a time, and that an SC can only pair with the most recent LR, and LR with the next following SC, in program order. This is a restriction to the Atomicity Axiom in Section 18.1 that ensures software runs correctly on expected common implementations that operate in this manner.
/// --
///
/// An SC instruction can never be observed by another RISC-V hart before the LR instruction that established the reservation.
///
/// \[NOTE\]
/// --
/// The LR/SC sequence can be given acquire semantics by setting the aq bit on the LR instruction. The LR/SC sequence can be given release semantics by by setting the rl bit on the SC instruction. Assuming suitable mappings for other atomic operations, setting the aq bit on the LR instruction, and setting the rl bit on the SC instruction makes the LR/SC sequence sequentially consistent in the C++ memory_order_seq_cst sense. Such a sequence does not act as a fence for ordering ordinary load and store instructions before and after the sequence. Specific instruction mappings for other C++ atomic operations, or stronger notions of "sequential consistency", may require both bits to be set on either or both of the LR or SC instruction.
///
/// If neither bit is set on either LR or SC, the LR/SC sequence can be observed to occur before or after surrounding memory operations from the same RISC-V hart. This can be appropriate when the LR/SC sequence is used to implement a parallel reduction operation.
/// --
///
/// Software should not set the _rl_ bit on an LR instruction unless the _aq_ bit is also set.
/// LR.rl and SC.aq instructions are not guaranteed to provide any stronger ordering than those
/// with both bits clear, but may result in lower performance.
///
/// # Forms
/// Assembly: `sc.d xd, xs2, xs1`
/// Rust: `sc_d(rd, rs1, rs2, aq, rl)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Memory base register.
/// - `rs2` — Source register.
/// - `aq` — Acquire-order bit.
/// - `rl` — Release-order bit; retained for the existing emitter API.
pub trait ScDEmitter<T0, T1, T2, T3, T4> {
    fn sc_d(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4);
}

/// Store conditional word
///
/// `sc.w` conditionally writes a word in _rs2_ to the address in _rs1_:
/// the `sc.w` succeeds only if the reservation is still valid and the
/// reservation set contains the bytes being written. If the `sc.w` succeeds,
/// the instruction writes the word in _rs2_ to memory, and it writes zero to _rd_.
/// If the `sc.w` fails, the instruction does not write to memory, and it writes a
/// nonzero value to _rd_. For the purposes of memory protection, a failed `sc.w`
/// may be treated like a store. Regardless of success or failure, executing an
/// `sc.w` instruction invalidates any reservation held by this hart.
///
/// &lt;%- if XLEN == 64 -%&gt;
/// \[NOTE\]
/// If a value other than 0 or 1 is defined as a result for `sc.w`, the value will before
/// sign-extended into _rd_.
/// &lt;%- end -%&gt;
///
/// The failure code with value 1 encodes an unspecified failure.
/// Other failure codes are reserved at this time.
/// Portable software should only assume the failure code will be non-zero.
///
/// The address held in _rs1_ must be naturally aligned to the size of the operand
/// (_i.e._, eight-byte aligned for doublewords and four-byte aligned for words).
/// If the address is not naturally aligned, an address-misaligned exception or an
/// access-fault exception will be generated.
/// The access-fault exception can be generated for a memory access that would otherwise
/// be able to complete except for the misalignment,
/// if the misaligned access should not be emulated.
///
/// \[NOTE\]
/// --
/// Emulating misaligned LR/SC sequences is impractical in most systems.
///
/// Misaligned LR/SC sequences also raise the possibility of accessing multiple
/// reservation sets at once, which present definitions do not provide for.
/// --
///
/// An implementation can register an arbitrarily large reservation set on each LR,
/// provided the reservation set includes all bytes of the addressed data word or
/// doubleword.
/// An SC can only pair with the most recent LR in program order.
/// An SC may succeed only if no store from another hart to the reservation set
/// can be observed to have occurred between the LR and the SC,
/// and if there is no other SC between the LR and itself in program order.
/// An SC may succeed only if no write from a device other than a hart to the bytes
/// accessed by the LR instruction can be observed to have occurred between the LR
/// and SC.
/// Note this LR might have had a different effective address and data size,
/// but reserved the SC's address as part of the reservation set.
///
/// \[NOTE\]
/// ----
/// Following this model, in systems with memory translation, an SC is allowed to succeed if the
/// earlier LR reserved the same location using an alias with a different virtual address, but is
/// also allowed to fail if the virtual address is different.
///
/// To accommodate legacy devices and buses, writes from devices other than RISC-V harts are only
/// required to invalidate reservations when they overlap the bytes accessed by the LR.
/// These writes are not required to invalidate the reservation when they access other bytes in
/// the reservation set.
/// ----
///
/// The SC must fail if the address is not within the reservation set of the most
/// recent LR in program order.
/// The SC must fail if a store to the reservation set from another hart can be
/// observed to occur between the LR and SC.
/// The SC must fail if a write from some other device to the bytes accessed by the
/// LR can be observed to occur between the LR and SC.
/// (If such a device writes the reservation set but does not write the bytes accessed
/// by the LR, the SC may or may not fail.)
/// An SC must fail if there is another SC (to any address) between the LR and the SC
/// in program order.
/// The precise statement of the atomicity requirements for successful LR/SC sequences
/// is defined by the Atomicity Axiom of the memory model.
///
/// \[NOTE\]
/// --
/// The platform should provide a means to determine the size and shape of the reservation set.
///
/// A platform specification may constrain the size and shape of the reservation set.
///
/// A store-conditional instruction to a scratch word of memory should be used to forcibly invalidate any existing load reservation:
///
///   * during a preemptive context switch, and
///   * if necessary when changing virtual to physical address mappings, such as when migrating pages that might contain an active reservation.
///
/// The invalidation of a hart's reservation when it executes an LR or SC imply that a hart can only hold one reservation at a time, and that an SC can only pair with the most recent LR, and LR with the next following SC, in program order. This is a restriction to the Atomicity Axiom in Section 18.1 that ensures software runs correctly on expected common implementations that operate in this manner.
/// --
///
/// An SC instruction can never be observed by another RISC-V hart before the LR instruction that established the reservation.
///
/// \[NOTE\]
/// --
/// The LR/SC sequence can be given acquire semantics by setting the aq bit on the LR instruction. The LR/SC sequence can be given release semantics by by setting the rl bit on the SC instruction. Assuming suitable mappings for other atomic operations, setting the aq bit on the LR instruction, and setting the rl bit on the SC instruction makes the LR/SC sequence sequentially consistent in the C++ memory_order_seq_cst sense. Such a sequence does not act as a fence for ordering ordinary load and store instructions before and after the sequence. Specific instruction mappings for other C++ atomic operations, or stronger notions of "sequential consistency", may require both bits to be set on either or both of the LR or SC instruction.
///
/// If neither bit is set on either LR or SC, the LR/SC sequence can be observed to occur before or after surrounding memory operations from the same RISC-V hart. This can be appropriate when the LR/SC sequence is used to implement a parallel reduction operation.
/// --
///
/// Software should not set the _rl_ bit on an LR instruction unless the _aq_ bit is also set.
/// LR.rl and SC.aq instructions are not guaranteed to provide any stronger ordering than those
/// with both bits clear, but may result in lower performance.
///
/// # Forms
/// Assembly: `sc.w xd, xs2, xs1`
/// Rust: `sc_w(rd, rs1, rs2, aq, rl)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Memory base register.
/// - `rs2` — Source register.
/// - `aq` — Acquire-order bit.
/// - `rl` — Release-order bit; retained for the existing emitter API.
pub trait ScWEmitter<T0, T1, T2, T3, T4> {
    fn sc_w(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4);
}

/// RISC-V `scall` instruction.
///
/// # Forms
/// Assembly: `scall`
/// Rust: `scall()`
///
/// # Arguments
pub trait ScallEmitter {
    fn scall(&mut self);
}

/// RISC-V `sctrclr` instruction.
///
/// # Forms
/// Assembly: `sctrclr sctrclr`
/// Rust: `sctrclr()`
///
/// # Arguments
pub trait SctrclrEmitter {
    fn sctrclr(&mut self);
}

/// Store doubleword
///
/// Store 64 bits of data from register `rs2` to an
/// address formed by adding `rs1` to a signed offset.
///
/// # Forms
/// Assembly: `sd xs2, imm(xs1)`
/// Rust: `sd(rs1, rs2, imm)`
///
/// # Arguments
/// - `rs1` — Memory base register.
/// - `rs2` — Source register.
/// - `imm` — Immediate encoding value.
pub trait SdEmitter<T0, T1, T2> {
    fn sd(&mut self, rs1: T0, rs2: T1, imm: T2);
}

/// RISC-V `seqz` instruction.
///
/// # Forms
/// Assembly: `seqz rd rs1`
/// Rust: `seqz(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait SeqzEmitter<T0, T1> {
    fn seqz(&mut self, rd: T0, rs1: T1);
}

/// Sign-extend byte
///
/// This instruction sign-extends the least-significant byte in the source to XLEN by copying the
/// most-significant bit in the byte (i.e., bit 7) to all of the more-significant bits.
///
/// # Forms
/// Assembly: `sext.b xd, xs1`
/// Rust: `sext_b(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait SextBEmitter<T0, T1> {
    fn sext_b(&mut self, rd: T0, rs1: T1);
}

/// Sign-extend halfword
///
/// This instruction sign-extends the least-significant halfword in the source to XLEN by copying the
/// most-significant bit in the halfword (i.e., bit 15) to all of the more-significant bits.
///
/// # Forms
/// Assembly: `sext.h xd, xs1`
/// Rust: `sext_h(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait SextHEmitter<T0, T1> {
    fn sext_h(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `sext.w` instruction.
///
/// # Forms
/// Assembly: `sext.w rd rs1`
/// Rust: `sext_w(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait SextWEmitter<T0, T1> {
    fn sext_w(&mut self, rd: T0, rs1: T1);
}

/// Order implicit page table reads after invalidation
///
/// The `sfence.inval.ir` instruction guarantees that any previous `sinval.vma`
/// instructions executed by the current hart are ordered before subsequent implicit references by
/// that hart to the memory-management data structures.
///
/// # Forms
/// Assembly: `sfence.inval.ir ""`
/// Rust: `sfence_inval_ir()`
///
/// # Arguments
pub trait SfenceInvalIrEmitter {
    fn sfence_inval_ir(&mut self);
}

/// Supervisor memory-management fence
///
/// The supervisor memory-management fence instruction `SFENCE.VMA` is used to
/// synchronize updates to in-memory memory-management data structures with
/// current execution. Instruction execution causes implicit reads and
/// writes to these data structures; however, these implicit references are
/// ordinarily not ordered with respect to explicit loads and stores.
/// Executing an SFENCE.VMA instruction guarantees that any previous stores
/// already visible to the current RISC-V hart are ordered before certain
/// implicit references by subsequent instructions in that hart to the
/// memory-management data structures. The specific set of operations
/// ordered by SFENCE.VMA is determined by _rs1_ and _rs2_, as described
/// below. SFENCE.VMA is also used to invalidate entries in the
/// address-translation cache associated with a hart (see &lt;&lt;sv32algorithm&gt;&gt;). Further details on the behavior of this instruction are described in &lt;&lt;virt-control&gt;&gt; and &lt;&lt;pmp-vmem&gt;&gt;.
///
/// \[NOTE\]
/// ====
/// The SFENCE.VMA is used to flush any local hardware caches related to
/// address translation. It is specified as a fence rather than a TLB flush
/// to provide cleaner semantics with respect to which instructions are
/// affected by the flush operation and to support a wider variety of
/// dynamic caching structures and memory-management schemes. SFENCE.VMA is
/// also used by higher privilege levels to synchronize page table writes
/// and the address translation hardware.
/// ====
///
/// SFENCE.VMA orders only the local hart's implicit references to the
/// memory-management data structures.
///
/// \[NOTE\]
/// ====
/// Consequently, other harts must be notified separately when the
/// memory-management data structures have been modified. One approach is to
/// use 1) a local data fence to ensure local writes are visible globally,
/// then 2) an interprocessor interrupt to the other thread, then 3) a local
/// SFENCE.VMA in the interrupt handler of the remote thread, and finally 4)
/// signal back to originating thread that operation is complete. This is,
/// of course, the RISC-V analog to a TLB shootdown.
/// ====
///
/// For the common case that the translation data structures have only been
/// modified for a single address mapping (i.e., one page or superpage),
/// _rs1_ can specify a virtual address within that mapping to effect a
/// translation fence for that mapping only. Furthermore, for the common
/// case that the translation data structures have only been modified for a
/// single address-space identifier, _rs2_ can specify the address space.
/// The behavior of SFENCE.VMA depends on _rs1_ and _rs2_ as follows:
///
/// * If __rs1__=`x0` and __rs2__=`x0`, the fence orders all reads and writes
/// made to any level of the page tables, for all address spaces. The fence
/// also invalidates all address-translation cache entries, for all address
/// spaces.
/// * If __rs1__=`x0` and __rs2__&#8800;``x0``, the fence orders all
/// reads and writes made to any level of the page tables, but only for the
/// address space identified by integer register _rs2_. Accesses to _global_
/// mappings (see &lt;&lt;translation&gt;&gt;) are not ordered. The
/// fence also invalidates all address-translation cache entries matching
/// the address space identified by integer register _rs2_, except for
/// entries containing global mappings.
/// * If __rs1__&#8800;``x0`` and __rs2__=`x0`, the fence orders only
/// reads and writes made to leaf page table entries corresponding to the
/// virtual address in __rs1__, for all address spaces. The fence also
/// invalidates all address-translation cache entries that contain leaf page
/// table entries corresponding to the virtual address in _rs1_, for all
/// address spaces.
/// * If __rs1__&#8800;``x0`` and __rs2__&#8800;``x0``, the
/// fence orders only reads and writes made to leaf page table entries
/// corresponding to the virtual address in _rs1_, for the address space
/// identified by integer register _rs2_. Accesses to global mappings are
/// not ordered. The fence also invalidates all address-translation cache
/// entries that contain leaf page table entries corresponding to the
/// virtual address in _rs1_ and that match the address space identified by
/// integer register _rs2_, except for entries containing global mappings.
///
/// If the value held in _rs1_ is not a valid virtual address, then the
/// SFENCE.VMA instruction has no effect. No exception is raised in this
/// case.
///
/// When __rs2__&#8800;``x0``, bits SXLEN-1:ASIDMAX of the value held
/// in _rs2_ are reserved for future standard use. Until their use is
/// defined by a standard extension, they should be zeroed by software and
/// ignored by current implementations. Furthermore, if
/// ASIDLEN&lt;ASIDMAX, the implementation shall ignore bits
/// ASIDMAX-1:ASIDLEN of the value held in _rs2_.
///
/// \[NOTE\]
/// ====
/// It is always legal to over-fence, e.g., by fencing only based on a
/// subset of the bits in _rs1_ and/or _rs2_, and/or by simply treating all
/// SFENCE.VMA instructions as having _rs1_=`x0` and/or _rs2_=`x0`. For
/// example, simpler implementations can ignore the virtual address in _rs1_
/// and the ASID value in _rs2_ and always perform a global fence. The
/// choice not to raise an exception when an invalid virtual address is held
/// in _rs1_ facilitates this type of simplification.
/// ====
///
/// An implicit read of the memory-management data structures may return any
/// translation for an address that was valid at any time since the most
/// recent SFENCE.VMA that subsumes that address. The ordering implied by
/// SFENCE.VMA does not place implicit reads and writes to the
/// memory-management data structures into the global memory order in a way
/// that interacts cleanly with the standard RVWMO ordering rules. In
/// particular, even though an SFENCE.VMA orders prior explicit accesses
/// before subsequent implicit accesses, and those implicit accesses are
/// ordered before their associated explicit accesses, SFENCE.VMA does not
/// necessarily place prior explicit accesses before subsequent explicit
/// accesses in the global memory order. These implicit loads also need not
/// otherwise obey normal program order semantics with respect to prior
/// loads or stores to the same address.
///
/// \[NOTE\]
/// ====
/// A consequence of this specification is that an implementation may use
/// any translation for an address that was valid at any time since the most
/// recent SFENCE.VMA that subsumes that address. In particular, if a leaf
/// PTE is modified but a subsuming SFENCE.VMA is not executed, either the
/// old translation or the new translation will be used, but the choice is
/// unpredictable. The behavior is otherwise well-defined.
///
/// In a conventional TLB design, it is possible for multiple entries to
/// match a single address if, for example, a page is upgraded to a
/// superpage without first clearing the original non-leaf PTE's valid bit
/// and executing an SFENCE.VMA with __rs1__=`x0`. In this case, a similar
/// remark applies: it is unpredictable whether the old non-leaf PTE or the
/// new leaf PTE is used, but the behavior is otherwise well defined.
///
/// Another consequence of this specification is that it is generally unsafe
/// to update a PTE using a set of stores of a width less than the width of
/// the PTE, as it is legal for the implementation to read the PTE at any
/// time, including when only some of the partial stores have taken effect.
///
/// ***
///
/// This specification permits the caching of PTEs whose V (Valid) bit is
/// clear. Operating systems must be written to cope with this possibility,
/// but implementers are reminded that eagerly caching invalid PTEs will
/// reduce performance by causing additional page faults.
/// ====
///
/// Implementations must only perform implicit reads of the translation data
/// structures pointed to by the current contents of the `satp` register or
/// a subsequent valid (V=1) translation data structure entry, and must only
/// raise exceptions for implicit accesses that are generated as a result of
/// instruction execution, not those that are performed speculatively.
///
/// Changes to the `sstatus` fields SUM and MXR take effect immediately,
/// without the need to execute an SFENCE.VMA instruction. Changing
/// `satp`.MODE from Bare to other modes and vice versa also takes effect
/// immediately, without the need to execute an SFENCE.VMA instruction.
/// Likewise, changes to `satp`.ASID take effect immediately.
///
/// \[TIP\]
/// ====
/// The following common situations typically require executing an
/// SFENCE.VMA instruction:
///
/// * When software recycles an ASID (i.e., reassociates it with a different
/// page table), it should _first_ change `satp` to point to the new page
/// table using the recycled ASID, _then_ execute SFENCE.VMA with __rs1__=`x0`
/// and _rs2_ set to the recycled ASID. Alternatively, software can execute
/// the same SFENCE.VMA instruction while a different ASID is loaded into
/// `satp`, provided the next time `satp` is loaded with the recycled ASID,
/// it is simultaneously loaded with the new page table.
/// * If the implementation does not provide ASIDs, or software chooses to
/// always use ASID 0, then after every `satp` write, software should
/// execute SFENCE.VMA with __rs1__=`x0`. In the common case that no global
/// translations have been modified, _rs2_ should be set to a register other
/// than `x0` but which contains the value zero, so that global translations
/// are not flushed.
/// * If software modifies a non-leaf PTE, it should execute SFENCE.VMA with
/// __rs1__=`x0`. If any PTE along the traversal path had its G bit set, _rs2_
/// must be `x0`; otherwise, _rs2_ should be set to the ASID for which the
/// translation is being modified.
/// * If software modifies a leaf PTE, it should execute SFENCE.VMA with
/// _rs1_ set to a virtual address within the page. If any PTE along the
/// traversal path had its G bit set, _rs2_ must be `x0`; otherwise, _rs2_
/// should be set to the ASID for which the translation is being modified.
/// * For the special cases of increasing the permissions on a leaf PTE and
/// changing an invalid PTE to a valid leaf, software may choose to execute
/// the SFENCE.VMA lazily. After modifying the PTE but before executing
/// SFENCE.VMA, either the new or old permissions will be used. In the
/// latter case, a page-fault exception might occur, at which point software
/// should execute SFENCE.VMA in accordance with the previous bullet point.
/// ====
///
/// If a hart employs an address-translation cache, that cache must appear
/// to be private to that hart. In particular, the meaning of an ASID is
/// local to a hart; software may choose to use the same ASID to refer to
/// different address spaces on different harts.
///
/// \[NOTE\]
/// ====
/// A future extension could redefine ASIDs to be global across the SEE,
/// enabling such options as shared translation caches and hardware support
/// for broadcast TLB shootdown. However, as OSes have evolved to
/// significantly reduce the scope of TLB shootdowns using novel
/// ASID-management techniques, we expect the local-ASID scheme to remain
/// attractive for its simplicity and possibly better scalability.
/// ====
///
/// For implementations that make `satp`.MODE read-only zero (always Bare),
/// attempts to execute an SFENCE.VMA instruction might raise an
/// illegal-instruction exception.
///
/// # Forms
/// Assembly: `sfence.vma xs1, xs2`
/// Rust: `sfence_vma(rs1, rs2)`
///
/// # Arguments
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait SfenceVmaEmitter<T0, T1> {
    fn sfence_vma(&mut self, rs1: T0, rs2: T1);
}

/// Order writes before sfence
///
/// The `sfence.w.inval` instruction guarantees that any previous stores already visible to the
/// current RISC-V hart are ordered before subsequent `sinval.vma` instructions executed by the
/// same hart.
///
/// # Forms
/// Assembly: `sfence.w.inval ""`
/// Rust: `sfence_w_inval()`
///
/// # Arguments
pub trait SfenceWInvalEmitter {
    fn sfence_w_inval(&mut self);
}

/// RISC-V `sgtz` instruction.
///
/// # Forms
/// Assembly: `sgtz rd rs2`
/// Rust: `sgtz(rd, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs2` — Source register.
pub trait SgtzEmitter<T0, T1> {
    fn sgtz(&mut self, rd: T0, rs2: T1);
}

/// Store halfword
///
/// Store 16 bits of data from register `rs2` to an
/// address formed by adding `rs1` to a signed offset.
///
/// # Forms
/// Assembly: `sh xs2, imm(xs1)`
/// Rust: `sh(rs1, rs2, imm)`
///
/// # Arguments
/// - `rs1` — Memory base register.
/// - `rs2` — Source register.
/// - `imm` — Immediate encoding value.
pub trait ShEmitter<T0, T1, T2> {
    fn sh(&mut self, rs1: T0, rs2: T1, imm: T2);
}

/// Shift left by 1 and add
///
/// This instruction shifts `rs1` to the left by 1 bit and adds it to `rs2`.
///
/// # Forms
/// Assembly: `sh1add xd, xs1, xs2`
/// Rust: `sh1add(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait Sh1AddEmitter<T0, T1, T2> {
    fn sh1add(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// Shift unsigned word left by 1 and add
///
/// This instruction performs an XLEN-wide addition of two addends. The first addend is rs2.
/// The second addend is the unsigned value formed by extracting the least-significant word of rs1
/// and shifting it left by 1 place.
///
/// # Forms
/// Assembly: `sh1add.uw xd, xs1, xs2`
/// Rust: `sh1add_uw(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait Sh1AddUwEmitter<T0, T1, T2> {
    fn sh1add_uw(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// Shift left by 2 and add
///
/// This instruction shifts `rs1` to the left by 2 places and adds it to `rs2`.
///
/// # Forms
/// Assembly: `sh2add xd, xs1, xs2`
/// Rust: `sh2add(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait Sh2AddEmitter<T0, T1, T2> {
    fn sh2add(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// Shift unsigned word left by 2 and add
///
/// This instruction performs an XLEN-wide addition of two addends. The first addend is rs2.
/// The second addend is the unsigned value formed by extracting the least-significant word of rs1
/// and shifting it left by 2 places.
///
/// # Forms
/// Assembly: `sh2add.uw xd, xs1, xs2`
/// Rust: `sh2add_uw(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait Sh2AddUwEmitter<T0, T1, T2> {
    fn sh2add_uw(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// Shift left by 3 and add
///
/// This instruction shifts `rs1` to the left by 3 places and adds it to `rs2`.
///
/// # Forms
/// Assembly: `sh3add xd, xs1, xs2`
/// Rust: `sh3add(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait Sh3AddEmitter<T0, T1, T2> {
    fn sh3add(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// Shift unsigned word left by 3 and add
///
/// This instruction performs an XLEN-wide addition of two addends. The first addend is rs2.
/// The second addend is the unsigned value formed by extracting the least-significant word of rs1
/// and shifting it left by 3 places.
///
/// # Forms
/// Assembly: `sh3add.uw xd, xs1, xs2`
/// Rust: `sh3add_uw(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait Sh3AddUwEmitter<T0, T1, T2> {
    fn sh3add_uw(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `sha256sig0` instruction.
///
/// # Forms
/// Assembly: `sha256sig0 xd, xs1`
/// Rust: `sha256sig0(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait Sha256Sig0Emitter<T0, T1> {
    fn sha256sig0(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `sha256sig1` instruction.
///
/// # Forms
/// Assembly: `sha256sig1 xd, xs1`
/// Rust: `sha256sig1(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait Sha256Sig1Emitter<T0, T1> {
    fn sha256sig1(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `sha256sum0` instruction.
///
/// # Forms
/// Assembly: `sha256sum0 xd, xs1`
/// Rust: `sha256sum0(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait Sha256Sum0Emitter<T0, T1> {
    fn sha256sum0(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `sha256sum1` instruction.
///
/// # Forms
/// Assembly: `sha256sum1 xd, xs1`
/// Rust: `sha256sum1(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait Sha256Sum1Emitter<T0, T1> {
    fn sha256sum1(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `sha512sig0` instruction.
///
/// # Forms
/// Assembly: `sha512sig0 xd, xs1`
/// Rust: `sha512sig0(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait Sha512Sig0Emitter<T0, T1> {
    fn sha512sig0(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `sha512sig0h` instruction.
///
/// # Forms
/// Assembly: `sha512sig0h xd, xs1, xs2`
/// Rust: `sha512sig0h(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait Sha512Sig0HEmitter<T0, T1, T2> {
    fn sha512sig0h(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `sha512sig0l` instruction.
///
/// # Forms
/// Assembly: `sha512sig0l xd, xs1, xs2`
/// Rust: `sha512sig0l(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait Sha512Sig0LEmitter<T0, T1, T2> {
    fn sha512sig0l(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `sha512sig1` instruction.
///
/// # Forms
/// Assembly: `sha512sig1 xd, xs1`
/// Rust: `sha512sig1(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait Sha512Sig1Emitter<T0, T1> {
    fn sha512sig1(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `sha512sig1h` instruction.
///
/// # Forms
/// Assembly: `sha512sig1h xd, xs1, xs2`
/// Rust: `sha512sig1h(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait Sha512Sig1HEmitter<T0, T1, T2> {
    fn sha512sig1h(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `sha512sig1l` instruction.
///
/// # Forms
/// Assembly: `sha512sig1l xd, xs1, xs2`
/// Rust: `sha512sig1l(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait Sha512Sig1LEmitter<T0, T1, T2> {
    fn sha512sig1l(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `sha512sum0` instruction.
///
/// # Forms
/// Assembly: `sha512sum0 xd, xs1`
/// Rust: `sha512sum0(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait Sha512Sum0Emitter<T0, T1> {
    fn sha512sum0(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `sha512sum0r` instruction.
///
/// # Forms
/// Assembly: `sha512sum0r xd, xs1, xs2`
/// Rust: `sha512sum0r(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait Sha512Sum0REmitter<T0, T1, T2> {
    fn sha512sum0r(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `sha512sum1` instruction.
///
/// # Forms
/// Assembly: `sha512sum1 xd, xs1`
/// Rust: `sha512sum1(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait Sha512Sum1Emitter<T0, T1> {
    fn sha512sum1(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `sha512sum1r` instruction.
///
/// # Forms
/// Assembly: `sha512sum1r xd, xs1, xs2`
/// Rust: `sha512sum1r(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait Sha512Sum1REmitter<T0, T1, T2> {
    fn sha512sum1r(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// Invalidate cached address translations
///
/// # Forms
/// Assembly: `sinval.vma xs1, xs2`
/// Rust: `sinval_vma(rs1, rs2)`
///
/// # Arguments
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait SinvalVmaEmitter<T0, T1> {
    fn sinval_vma(&mut self, rs1: T0, rs2: T1);
}

/// Shift left logical
///
/// Shift the value in `rs1` left by the value in the lower 6 bits of `rs2`, and store the result in `rd`.
///
/// # Forms
/// Assembly: `sll xd, xs1, xs2`
/// Rust: `sll(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait SllEmitter<T0, T1, T2> {
    fn sll(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// Shift left logical immediate
///
/// Shift the value in rs1 left by shamt, and store the result in rd
///
/// # Forms
/// Assembly: `slli xd, xs1, shamt`
/// Rust: `slli(rd, rs1, shamtd)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `shamtd` — Immediate encoding value.
pub trait SlliEmitter<T0, T1, T2> {
    fn slli(&mut self, rd: T0, rs1: T1, shamtd: T2);
}

/// Shift left logical immediate
///
/// Shift the value in rs1 left by shamt, and store the result in rd
///
/// # Forms
/// Assembly: `slli.rv32 xd, xs1, shamt`
/// Rust: `slli_rv32(rd, rs1, shamtw)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `shamtw` — Immediate encoding value.
pub trait SlliRv32Emitter<T0, T1, T2> {
    fn slli_rv32(&mut self, rd: T0, rs1: T1, shamtw: T2);
}

/// Shift left unsigned word (Immediate)
///
/// This instruction takes the least-significant word of rs1, zero-extends it, and shifts it
/// left by the immediate.
///
/// \[NOTE\]
/// This instruction is the same as `slli` with `zext.w` performed on rs1 before shifting.
///
/// # Forms
/// Assembly: `slli.uw xd, xs1, shamt`
/// Rust: `slli_uw(rd, rs1, shamtd)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `shamtd` — Immediate encoding value.
pub trait SlliUwEmitter<T0, T1, T2> {
    fn slli_uw(&mut self, rd: T0, rs1: T1, shamtd: T2);
}

/// Shift left logical immediate word
///
/// Shift the 32-bit value in rs1 left by shamt, and store the sign-extended result in rd
///
/// # Forms
/// Assembly: `slliw xd, xs1, shamt`
/// Rust: `slliw(rd, rs1, shamtw)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `shamtw` — Immediate encoding value.
pub trait SlliwEmitter<T0, T1, T2> {
    fn slliw(&mut self, rd: T0, rs1: T1, shamtw: T2);
}

/// Shift left logical word
///
/// Shift the 32-bit value in `rs1` left by the value in the lower 5 bits of `rs2`, and store the sign-extended result in `rd`.
///
/// # Forms
/// Assembly: `sllw xd, xs1, xs2`
/// Rust: `sllw(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait SllwEmitter<T0, T1, T2> {
    fn sllw(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// Set on less than
///
/// Places the value 1 in register `rd` if register `rs1` is less than the value in register `rs2`, where
/// both sources are treated as signed numbers, else 0 is written to `rd`.
///
/// # Forms
/// Assembly: `slt xd, xs1, rs2`
/// Rust: `slt(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait SltEmitter<T0, T1, T2> {
    fn slt(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// Set on less than immediate
///
/// Places the value 1 in register `rd` if register `rs1` is less than the sign-extended immediate
/// when both are treated as signed numbers, else 0 is written to `rd`.
///
/// # Forms
/// Assembly: `slti xd, xs1, imm`
/// Rust: `slti(rd, rs1, imm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `imm` — Immediate encoding value.
pub trait SltiEmitter<T0, T1, T2> {
    fn slti(&mut self, rd: T0, rs1: T1, imm: T2);
}

/// Set on less than immediate unsigned
///
/// Places the value 1 in register `rd` if register `rs1` is less than the sign-extended immediate
/// when both are treated as unsigned numbers (_i.e._, the immediate is first sign-extended to
/// XLEN bits then treated as an unsigned number), else 0 is written to `rd`.
///
/// NOTE: `sltiu rd, rs1, 1` sets `rd` to 1 if `rs1` equals zero, otherwise sets `rd` to 0
/// (assembler pseudoinstruction `SEQZ rd, rs`).
///
/// # Forms
/// Assembly: `sltiu xd, xs1, imm`
/// Rust: `sltiu(rd, rs1, imm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `imm` — Immediate encoding value.
pub trait SltiuEmitter<T0, T1, T2> {
    fn sltiu(&mut self, rd: T0, rs1: T1, imm: T2);
}

/// Set on less than unsigned
///
/// Places the value 1 in register `rd` if register `rs1` is less than the value in register `rs2`, where
/// both sources are treated as unsigned numbers, else 0 is written to `rd`.
///
/// # Forms
/// Assembly: `sltu xd, xs1, xs2`
/// Rust: `sltu(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait SltuEmitter<T0, T1, T2> {
    fn sltu(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `sltz` instruction.
///
/// # Forms
/// Assembly: `sltz rd rs1`
/// Rust: `sltz(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait SltzEmitter<T0, T1> {
    fn sltz(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `sm3p0` instruction.
///
/// # Forms
/// Assembly: `sm3p0 xd, xs1`
/// Rust: `sm3p0(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait Sm3P0Emitter<T0, T1> {
    fn sm3p0(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `sm3p1` instruction.
///
/// # Forms
/// Assembly: `sm3p1 xd, xs1`
/// Rust: `sm3p1(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait Sm3P1Emitter<T0, T1> {
    fn sm3p1(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `sm4ed` instruction.
///
/// # Forms
/// Assembly: `sm4ed xd, xs1, xs2, bs`
/// Rust: `sm4ed(rd, rs1, rs2, bs)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
/// - `bs` — Immediate encoding value.
pub trait Sm4EdEmitter<T0, T1, T2, T3> {
    fn sm4ed(&mut self, rd: T0, rs1: T1, rs2: T2, bs: T3);
}

/// RISC-V `sm4ks` instruction.
///
/// # Forms
/// Assembly: `sm4ks xd, xs1, xs2, bs`
/// Rust: `sm4ks(rd, rs1, rs2, bs)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
/// - `bs` — Immediate encoding value.
pub trait Sm4KsEmitter<T0, T1, T2, T3> {
    fn sm4ks(&mut self, rd: T0, rs1: T1, rs2: T2, bs: T3);
}

/// RISC-V `snez` instruction.
///
/// # Forms
/// Assembly: `snez rd rs2`
/// Rust: `snez(rd, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs2` — Source register.
pub trait SnezEmitter<T0, T1> {
    fn snez(&mut self, rd: T0, rs2: T1);
}

/// Shift right arithmetic
///
/// Arithmetic shift the value in `rs1` right by the value in the lower 5 bits of `rs2`, and store the result in `rd`.
///
/// # Forms
/// Assembly: `sra xd, xs1, xs2`
/// Rust: `sra(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait SraEmitter<T0, T1, T2> {
    fn sra(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// Shift right arithmetic immediate
///
/// Arithmetic shift (the original sign bit is copied into the vacated upper bits) the
/// value in rs1 right by shamt, and store the result in rd.
///
/// # Forms
/// Assembly: `srai xd, xs1, shamt`
/// Rust: `srai(rd, rs1, shamtd)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `shamtd` — Immediate encoding value.
pub trait SraiEmitter<T0, T1, T2> {
    fn srai(&mut self, rd: T0, rs1: T1, shamtd: T2);
}

/// Shift right arithmetic immediate
///
/// Arithmetic shift (the original sign bit is copied into the vacated upper bits) the
/// value in rs1 right by shamt, and store the result in rd.
///
/// # Forms
/// Assembly: `srai.rv32 xd, xs1, shamt`
/// Rust: `srai_rv32(rd, rs1, shamtw)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `shamtw` — Immediate encoding value.
pub trait SraiRv32Emitter<T0, T1, T2> {
    fn srai_rv32(&mut self, rd: T0, rs1: T1, shamtw: T2);
}

/// Shift right arithmetic immediate word
///
/// Arithmetic shift (the original sign bit is copied into the vacated upper bits) the
/// 32-bit value in rs1 right by shamt, and store the sign-extended result in rd.
///
/// # Forms
/// Assembly: `sraiw xd, xs1, shamt`
/// Rust: `sraiw(rd, rs1, shamtw)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `shamtw` — Immediate encoding value.
pub trait SraiwEmitter<T0, T1, T2> {
    fn sraiw(&mut self, rd: T0, rs1: T1, shamtw: T2);
}

/// Shift right arithmetic word
///
/// Arithmetic shift the 32-bit value in `rs1` right by the value in the lower 5 bits of `rs2`, and store the sign-extended result in `rd`.
///
/// # Forms
/// Assembly: `sraw xd, xs1, xs2`
/// Rust: `sraw(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait SrawEmitter<T0, T1, T2> {
    fn sraw(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// Supervisor Exception Return
///
/// Returns from an exception.
///
/// When `sret` is allowed to execute, its behavior depends on whether or not the current privilege
/// mode is virtualized.
///
/// *When the current privilege mode is (H)S-mode or M-mode*
///
/// `sret` sets  `hstatus.HPV` = 0, `mstatus.SPP` = 0,
/// `mstatus.SIE` = `mstatus.SPIE`, and `mstatus.SPIE` = 1,
/// changes the privilege mode according to the table below,
/// and then jumps to the address in `sepc`.
///
/// .Next privilege mode following an `sret` in (H)S-mode or M-mode
/// \[%autowidth\]
/// |===
/// | \[.rotate\]#`mstatus.SPP`# | \[.rotate\]#`hstatus.SPV`# .&gt;| Mode after `sret`
///
/// | 0 | 0 | U-mode
/// | 0 | 1 | VU-mode
/// | 1 | 0 | (H)S-mode
/// | 1 | 1 | VS-mode
/// |===
///
/// *When the current privilege mode is VS-mode*
///
/// `sret` sets
/// `vsstatus.SPP` = 0, `vsstatus.SIE` = `vstatus.SPIE`, and `vsstatus.SPIE` = 1,
/// changes the privilege mode according to the table below,
/// and then jumps to the address in `vsepc`.
///
/// .Next privilege mode following an `sret` in (H)S-mode or M-mode
/// \[%autowidth\]
/// |===
/// | \[.rotate\]#`vsstatus.SPP`# .&gt;| Mode after `sret`
///
/// | 0 | VU-mode
/// | 1 | VS-mode
/// |===
///
/// # Forms
/// Assembly: `sret ""`
/// Rust: `sret()`
///
/// # Arguments
pub trait SretEmitter {
    fn sret(&mut self);
}

/// Shift right logical
///
/// Logical shift the value in `rs1` right by the value in the lower bits of `rs2`, and store the result in `rd`.
///
/// # Forms
/// Assembly: `srl xd, xs1, xs2`
/// Rust: `srl(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait SrlEmitter<T0, T1, T2> {
    fn srl(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// Shift right logical immediate
///
/// Shift the value in rs1 right by shamt, and store the result in rd
///
/// # Forms
/// Assembly: `srli xd, xs1, shamt`
/// Rust: `srli(rd, rs1, shamtd)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `shamtd` — Immediate encoding value.
pub trait SrliEmitter<T0, T1, T2> {
    fn srli(&mut self, rd: T0, rs1: T1, shamtd: T2);
}

/// Shift right logical immediate
///
/// Shift the value in rs1 right by shamt, and store the result in rd
///
/// # Forms
/// Assembly: `srli.rv32 xd, xs1, shamt`
/// Rust: `srli_rv32(rd, rs1, shamtw)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `shamtw` — Immediate encoding value.
pub trait SrliRv32Emitter<T0, T1, T2> {
    fn srli_rv32(&mut self, rd: T0, rs1: T1, shamtw: T2);
}

/// Shift right logical immediate word
///
/// Shift the 32-bit value in rs1 right by shamt, and store the sign-extended result in rd
///
/// # Forms
/// Assembly: `srliw xd, xs1, shamt`
/// Rust: `srliw(rd, rs1, shamtw)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `shamtw` — Immediate encoding value.
pub trait SrliwEmitter<T0, T1, T2> {
    fn srliw(&mut self, rd: T0, rs1: T1, shamtw: T2);
}

/// Shift right logical word
///
/// Logical shift the 32-bit value in `rs1` right by the value in the lower 5 bits of `rs2`, and store the sign-extended result in `rd`.
///
/// # Forms
/// Assembly: `srlw xd, xs1, xs2`
/// Rust: `srlw(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait SrlwEmitter<T0, T1, T2> {
    fn srlw(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `ssamoswap.d` instruction.
///
/// # Forms
/// Assembly: `ssamoswap.d xd, xs1, xs2, aq, rl`
/// Rust: `ssamoswap_d(rd, rs1, rs2, aq, rl)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Memory base register.
/// - `rs2` — Source register.
/// - `aq` — Acquire-order bit.
/// - `rl` — Release-order bit; retained for the existing emitter API.
pub trait SsamoswapDEmitter<T0, T1, T2, T3, T4> {
    fn ssamoswap_d(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4);
}

/// RISC-V `ssamoswap.w` instruction.
///
/// # Forms
/// Assembly: `ssamoswap.w xd, xs1, xs2, aq, rl`
/// Rust: `ssamoswap_w(rd, rs1, rs2, aq, rl)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Memory base register.
/// - `rs2` — Source register.
/// - `aq` — Acquire-order bit.
/// - `rl` — Release-order bit; retained for the existing emitter API.
pub trait SsamoswapWEmitter<T0, T1, T2, T3, T4> {
    fn ssamoswap_w(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4);
}

/// RISC-V `sspopchk.x1` instruction.
///
/// # Forms
/// Assembly: `sspopchk.x1 sspopchk_x1`
/// Rust: `sspopchk_x1()`
///
/// # Arguments
pub trait SspopchkX1Emitter {
    fn sspopchk_x1(&mut self);
}

/// RISC-V `sspopchk.x5` instruction.
///
/// # Forms
/// Assembly: `sspopchk.x5 sspopchk_x5`
/// Rust: `sspopchk_x5()`
///
/// # Arguments
pub trait SspopchkX5Emitter {
    fn sspopchk_x5(&mut self);
}

/// RISC-V `sspush.x1` instruction.
///
/// # Forms
/// Assembly: `sspush.x1 sspush_x1`
/// Rust: `sspush_x1()`
///
/// # Arguments
pub trait SspushX1Emitter {
    fn sspush_x1(&mut self);
}

/// RISC-V `sspush.x5` instruction.
///
/// # Forms
/// Assembly: `sspush.x5 sspush_x5`
/// Rust: `sspush_x5()`
///
/// # Arguments
pub trait SspushX5Emitter {
    fn sspush_x5(&mut self);
}

/// RISC-V `ssrdp` instruction.
///
/// # Forms
/// Assembly: `ssrdp xd`
/// Rust: `ssrdp(rd)`
///
/// # Arguments
/// - `rd` — Destination register.
pub trait SsrdpEmitter<T0> {
    fn ssrdp(&mut self, rd: T0);
}

/// Subtract
///
/// Subtract the value in rs2 from rs1, and store the result in rd
///
/// # Forms
/// Assembly: `sub xd, xs1, xs2`
/// Rust: `sub(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait SubEmitter<T0, T1, T2> {
    fn sub(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// Subtract word
///
/// Subtract the 32-bit values in rs2 from rs1, and store the sign-extended result in rd
///
/// # Forms
/// Assembly: `subw xd, xs1, xs2`
/// Rust: `subw(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait SubwEmitter<T0, T1, T2> {
    fn subw(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// Store word
///
/// Store 32 bits of data from register `rs2` to an
/// address formed by adding `rs1` to a signed offset.
///
/// # Forms
/// Assembly: `sw xs2, imm(xs1)`
/// Rust: `sw(rs1, rs2, imm)`
///
/// # Arguments
/// - `rs1` — Memory base register.
/// - `rs2` — Source register.
/// - `imm` — Immediate encoding value.
pub trait SwEmitter<T0, T1, T2> {
    fn sw(&mut self, rs1: T0, rs2: T1, imm: T2);
}

/// Bit deinterleave
///
/// This instruction gathers bits from the high and low halves of the source word into odd/even bit
/// positions in the destination word. It is the inverse of the zip instruction. This instruction is
/// available only on RV32.
///
/// # Forms
/// Assembly: `unzip xd, xs1`
/// Rust: `unzip(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait UnzipEmitter<T0, T1> {
    fn unzip(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `vaadd.vv` instruction.
///
/// # Forms
/// Assembly: `vaadd.vv vm, vs2, vs1, vd`
/// Rust: `vaadd_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VaaddVvEmitter<T0, T1, T2, T3> {
    fn vaadd_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vaadd.vx` instruction.
///
/// # Forms
/// Assembly: `vaadd.vx vm, vs2, xs1, vd`
/// Rust: `vaadd_vx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VaaddVxEmitter<T0, T1, T2, T3> {
    fn vaadd_vx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vaaddu.vv` instruction.
///
/// # Forms
/// Assembly: `vaaddu.vv vm, vs2, vs1, vd`
/// Rust: `vaaddu_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VaadduVvEmitter<T0, T1, T2, T3> {
    fn vaaddu_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vaaddu.vx` instruction.
///
/// # Forms
/// Assembly: `vaaddu.vx vm, vs2, xs1, vd`
/// Rust: `vaaddu_vx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VaadduVxEmitter<T0, T1, T2, T3> {
    fn vaaddu_vx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vadc.vim` instruction.
///
/// # Forms
/// Assembly: `vadc.vim vs2, vd, imm`
/// Rust: `vadc_vim(vd, vs2, simm5)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `simm5` — Immediate encoding value.
pub trait VadcVimEmitter<T0, T1, T2> {
    fn vadc_vim(&mut self, vd: T0, vs2: T1, simm5: T2);
}

/// RISC-V `vadc.vvm` instruction.
///
/// # Forms
/// Assembly: `vadc.vvm vs2, vs1, vd`
/// Rust: `vadc_vvm(vd, vs1, vs2)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
pub trait VadcVvmEmitter<T0, T1, T2> {
    fn vadc_vvm(&mut self, vd: T0, vs1: T1, vs2: T2);
}

/// RISC-V `vadc.vxm` instruction.
///
/// # Forms
/// Assembly: `vadc.vxm vs2, xs1, vd`
/// Rust: `vadc_vxm(vd, rs1, vs2)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `rs1` — Source register.
/// - `vs2` — Vector register operand.
pub trait VadcVxmEmitter<T0, T1, T2> {
    fn vadc_vxm(&mut self, vd: T0, rs1: T1, vs2: T2);
}

/// RISC-V `vadd.vi` instruction.
///
/// # Forms
/// Assembly: `vadd.vi vm, vs2, vd, imm`
/// Rust: `vadd_vi(vd, vs2, simm5, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `simm5` — Immediate encoding value.
/// - `vm` — Vector mask control.
pub trait VaddViEmitter<T0, T1, T2, T3> {
    fn vadd_vi(&mut self, vd: T0, vs2: T1, simm5: T2, vm: T3);
}

/// RISC-V `vadd.vv` instruction.
///
/// # Forms
/// Assembly: `vadd.vv vm, vs2, vs1, vd`
/// Rust: `vadd_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VaddVvEmitter<T0, T1, T2, T3> {
    fn vadd_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vadd.vx` instruction.
///
/// # Forms
/// Assembly: `vadd.vx vm, vs2, xs1, vd`
/// Rust: `vadd_vx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VaddVxEmitter<T0, T1, T2, T3> {
    fn vadd_vx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vaesdf.vs` instruction.
///
/// # Forms
/// Assembly: `vaesdf.vs vs2, vd`
/// Rust: `vaesdf_vs(vd, vs2)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
pub trait VaesdfVsEmitter<T0, T1> {
    fn vaesdf_vs(&mut self, vd: T0, vs2: T1);
}

/// RISC-V `vaesdf.vv` instruction.
///
/// # Forms
/// Assembly: `vaesdf.vv vs2, vd`
/// Rust: `vaesdf_vv(vd, vs2)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
pub trait VaesdfVvEmitter<T0, T1> {
    fn vaesdf_vv(&mut self, vd: T0, vs2: T1);
}

/// RISC-V `vaesdm.vs` instruction.
///
/// # Forms
/// Assembly: `vaesdm.vs vs2, vd`
/// Rust: `vaesdm_vs(vd, vs2)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
pub trait VaesdmVsEmitter<T0, T1> {
    fn vaesdm_vs(&mut self, vd: T0, vs2: T1);
}

/// RISC-V `vaesdm.vv` instruction.
///
/// # Forms
/// Assembly: `vaesdm.vv vs2, vd`
/// Rust: `vaesdm_vv(vd, vs2)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
pub trait VaesdmVvEmitter<T0, T1> {
    fn vaesdm_vv(&mut self, vd: T0, vs2: T1);
}

/// RISC-V `vaesef.vs` instruction.
///
/// # Forms
/// Assembly: `vaesef.vs vs2, vd`
/// Rust: `vaesef_vs(vd, vs2)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
pub trait VaesefVsEmitter<T0, T1> {
    fn vaesef_vs(&mut self, vd: T0, vs2: T1);
}

/// RISC-V `vaesef.vv` instruction.
///
/// # Forms
/// Assembly: `vaesef.vv vs2, vd`
/// Rust: `vaesef_vv(vd, vs2)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
pub trait VaesefVvEmitter<T0, T1> {
    fn vaesef_vv(&mut self, vd: T0, vs2: T1);
}

/// RISC-V `vaesem.vs` instruction.
///
/// # Forms
/// Assembly: `vaesem.vs vs2, vd`
/// Rust: `vaesem_vs(vd, vs2)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
pub trait VaesemVsEmitter<T0, T1> {
    fn vaesem_vs(&mut self, vd: T0, vs2: T1);
}

/// RISC-V `vaesem.vv` instruction.
///
/// # Forms
/// Assembly: `vaesem.vv vs2, vd`
/// Rust: `vaesem_vv(vd, vs2)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
pub trait VaesemVvEmitter<T0, T1> {
    fn vaesem_vv(&mut self, vd: T0, vs2: T1);
}

/// RISC-V `vaeskf1.vi` instruction.
///
/// # Forms
/// Assembly: `vaeskf1.vi vs2, vd, imm`
/// Rust: `vaeskf1_vi(vd, vs2, zimm5)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `zimm5` — Immediate encoding value.
pub trait Vaeskf1ViEmitter<T0, T1, T2> {
    fn vaeskf1_vi(&mut self, vd: T0, vs2: T1, zimm5: T2);
}

/// RISC-V `vaeskf2.vi` instruction.
///
/// # Forms
/// Assembly: `vaeskf2.vi vs2, vd, imm`
/// Rust: `vaeskf2_vi(vd, vs2, zimm5)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `zimm5` — Immediate encoding value.
pub trait Vaeskf2ViEmitter<T0, T1, T2> {
    fn vaeskf2_vi(&mut self, vd: T0, vs2: T1, zimm5: T2);
}

/// Vector AES round zero
///
/// # Forms
/// Assembly: `vaesz.vs vs2, vd`
/// Rust: `vaesz_vs(vd, vs2)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
pub trait VaeszVsEmitter<T0, T1> {
    fn vaesz_vs(&mut self, vd: T0, vs2: T1);
}

/// RISC-V `vand.vi` instruction.
///
/// # Forms
/// Assembly: `vand.vi vm, vs2, vd, imm`
/// Rust: `vand_vi(vd, vs2, simm5, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `simm5` — Immediate encoding value.
/// - `vm` — Vector mask control.
pub trait VandViEmitter<T0, T1, T2, T3> {
    fn vand_vi(&mut self, vd: T0, vs2: T1, simm5: T2, vm: T3);
}

/// RISC-V `vand.vv` instruction.
///
/// # Forms
/// Assembly: `vand.vv vm, vs2, vs1, vd`
/// Rust: `vand_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VandVvEmitter<T0, T1, T2, T3> {
    fn vand_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vand.vx` instruction.
///
/// # Forms
/// Assembly: `vand.vx vm, vs2, xs1, vd`
/// Rust: `vand_vx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VandVxEmitter<T0, T1, T2, T3> {
    fn vand_vx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vandn.vv` instruction.
///
/// # Forms
/// Assembly: `vandn.vv vm, vs2, vs1, vd`
/// Rust: `vandn_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VandnVvEmitter<T0, T1, T2, T3> {
    fn vandn_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vandn.vx` instruction.
///
/// # Forms
/// Assembly: `vandn.vx vm, vs2, xs1, vd`
/// Rust: `vandn_vx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VandnVxEmitter<T0, T1, T2, T3> {
    fn vandn_vx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vasub.vv` instruction.
///
/// # Forms
/// Assembly: `vasub.vv vm, vs2, vs1, vd`
/// Rust: `vasub_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VasubVvEmitter<T0, T1, T2, T3> {
    fn vasub_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vasub.vx` instruction.
///
/// # Forms
/// Assembly: `vasub.vx vm, vs2, xs1, vd`
/// Rust: `vasub_vx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VasubVxEmitter<T0, T1, T2, T3> {
    fn vasub_vx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vasubu.vv` instruction.
///
/// # Forms
/// Assembly: `vasubu.vv vm, vs2, vs1, vd`
/// Rust: `vasubu_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VasubuVvEmitter<T0, T1, T2, T3> {
    fn vasubu_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vasubu.vx` instruction.
///
/// # Forms
/// Assembly: `vasubu.vx vm, vs2, xs1, vd`
/// Rust: `vasubu_vx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VasubuVxEmitter<T0, T1, T2, T3> {
    fn vasubu_vx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vbrev8.v` instruction.
///
/// # Forms
/// Assembly: `vbrev8.v vm, vs2, vd`
/// Rust: `vbrev8_v(vd, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait Vbrev8VEmitter<T0, T1, T2> {
    fn vbrev8_v(&mut self, vd: T0, vs2: T1, vm: T2);
}

/// RISC-V `vbrev.v` instruction.
///
/// # Forms
/// Assembly: `vbrev.v vm, vs2, vd`
/// Rust: `vbrev_v(vd, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VbrevVEmitter<T0, T1, T2> {
    fn vbrev_v(&mut self, vd: T0, vs2: T1, vm: T2);
}

/// RISC-V `vclmul.vv` instruction.
///
/// # Forms
/// Assembly: `vclmul.vv vm, vs2, vs1, vd`
/// Rust: `vclmul_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VclmulVvEmitter<T0, T1, T2, T3> {
    fn vclmul_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vclmul.vx` instruction.
///
/// # Forms
/// Assembly: `vclmul.vx vm, vs2, xs1, vd`
/// Rust: `vclmul_vx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VclmulVxEmitter<T0, T1, T2, T3> {
    fn vclmul_vx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vclmulh.vv` instruction.
///
/// # Forms
/// Assembly: `vclmulh.vv vm, vs2, vs1, vd`
/// Rust: `vclmulh_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VclmulhVvEmitter<T0, T1, T2, T3> {
    fn vclmulh_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vclmulh.vx` instruction.
///
/// # Forms
/// Assembly: `vclmulh.vx vm, vs2, xs1, vd`
/// Rust: `vclmulh_vx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VclmulhVxEmitter<T0, T1, T2, T3> {
    fn vclmulh_vx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vclz.v` instruction.
///
/// # Forms
/// Assembly: `vclz.v vm, vs2, vd`
/// Rust: `vclz_v(vd, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VclzVEmitter<T0, T1, T2> {
    fn vclz_v(&mut self, vd: T0, vs2: T1, vm: T2);
}

/// RISC-V `vcompress.vm` instruction.
///
/// # Forms
/// Assembly: `vcompress.vm vs2, vs1, vd`
/// Rust: `vcompress_vm(vd, vs1, vs2)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
pub trait VcompressVmEmitter<T0, T1, T2> {
    fn vcompress_vm(&mut self, vd: T0, vs1: T1, vs2: T2);
}

/// RISC-V `vcpop.m` instruction.
///
/// # Forms
/// Assembly: `vcpop.m vm, vs2, xd`
/// Rust: `vcpop_m(rd, vs2, vm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VcpopMEmitter<T0, T1, T2> {
    fn vcpop_m(&mut self, rd: T0, vs2: T1, vm: T2);
}

/// RISC-V `vcpop.v` instruction.
///
/// # Forms
/// Assembly: `vcpop.v vm, vs2, vd`
/// Rust: `vcpop_v(vd, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VcpopVEmitter<T0, T1, T2> {
    fn vcpop_v(&mut self, vd: T0, vs2: T1, vm: T2);
}

/// RISC-V `vctz.v` instruction.
///
/// # Forms
/// Assembly: `vctz.v vm, vs2, vd`
/// Rust: `vctz_v(vd, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VctzVEmitter<T0, T1, T2> {
    fn vctz_v(&mut self, vd: T0, vs2: T1, vm: T2);
}

/// RISC-V `vdiv.vv` instruction.
///
/// # Forms
/// Assembly: `vdiv.vv vm, vs2, vs1, vd`
/// Rust: `vdiv_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VdivVvEmitter<T0, T1, T2, T3> {
    fn vdiv_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vdiv.vx` instruction.
///
/// # Forms
/// Assembly: `vdiv.vx vm, vs2, xs1, vd`
/// Rust: `vdiv_vx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VdivVxEmitter<T0, T1, T2, T3> {
    fn vdiv_vx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vdivu.vv` instruction.
///
/// # Forms
/// Assembly: `vdivu.vv vm, vs2, vs1, vd`
/// Rust: `vdivu_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VdivuVvEmitter<T0, T1, T2, T3> {
    fn vdivu_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vdivu.vx` instruction.
///
/// # Forms
/// Assembly: `vdivu.vx vm, vs2, xs1, vd`
/// Rust: `vdivu_vx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VdivuVxEmitter<T0, T1, T2, T3> {
    fn vdivu_vx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vfadd.vf` instruction.
///
/// # Forms
/// Assembly: `vfadd.vf vm, vs2, xs1, vd`
/// Rust: `vfadd_vf(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VfaddVfEmitter<T0, T1, T2, T3> {
    fn vfadd_vf(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vfadd.vv` instruction.
///
/// # Forms
/// Assembly: `vfadd.vv vm, vs2, vs1, vd`
/// Rust: `vfadd_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VfaddVvEmitter<T0, T1, T2, T3> {
    fn vfadd_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vfclass.v` instruction.
///
/// # Forms
/// Assembly: `vfclass.v vm, vs2, vd`
/// Rust: `vfclass_v(vd, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VfclassVEmitter<T0, T1, T2> {
    fn vfclass_v(&mut self, vd: T0, vs2: T1, vm: T2);
}

/// RISC-V `vfcvt.f.x.v` instruction.
///
/// # Forms
/// Assembly: `vfcvt.f.x.v vm, vs2, vd`
/// Rust: `vfcvt_f_x_v(vd, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VfcvtFXVEmitter<T0, T1, T2> {
    fn vfcvt_f_x_v(&mut self, vd: T0, vs2: T1, vm: T2);
}

/// RISC-V `vfcvt.f.xu.v` instruction.
///
/// # Forms
/// Assembly: `vfcvt.f.xu.v vm, vs2, vd`
/// Rust: `vfcvt_f_xu_v(vd, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VfcvtFXuVEmitter<T0, T1, T2> {
    fn vfcvt_f_xu_v(&mut self, vd: T0, vs2: T1, vm: T2);
}

/// RISC-V `vfcvt.rtz.x.f.v` instruction.
///
/// # Forms
/// Assembly: `vfcvt.rtz.x.f.v vm, vs2, vd`
/// Rust: `vfcvt_rtz_x_f_v(vd, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VfcvtRtzXFVEmitter<T0, T1, T2> {
    fn vfcvt_rtz_x_f_v(&mut self, vd: T0, vs2: T1, vm: T2);
}

/// RISC-V `vfcvt.rtz.xu.f.v` instruction.
///
/// # Forms
/// Assembly: `vfcvt.rtz.xu.f.v vm, vs2, vd`
/// Rust: `vfcvt_rtz_xu_f_v(vd, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VfcvtRtzXuFVEmitter<T0, T1, T2> {
    fn vfcvt_rtz_xu_f_v(&mut self, vd: T0, vs2: T1, vm: T2);
}

/// RISC-V `vfcvt.x.f.v` instruction.
///
/// # Forms
/// Assembly: `vfcvt.x.f.v vm, vs2, vd`
/// Rust: `vfcvt_x_f_v(vd, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VfcvtXFVEmitter<T0, T1, T2> {
    fn vfcvt_x_f_v(&mut self, vd: T0, vs2: T1, vm: T2);
}

/// RISC-V `vfcvt.xu.f.v` instruction.
///
/// # Forms
/// Assembly: `vfcvt.xu.f.v vm, vs2, vd`
/// Rust: `vfcvt_xu_f_v(vd, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VfcvtXuFVEmitter<T0, T1, T2> {
    fn vfcvt_xu_f_v(&mut self, vd: T0, vs2: T1, vm: T2);
}

/// RISC-V `vfdiv.vf` instruction.
///
/// # Forms
/// Assembly: `vfdiv.vf vm, vs2, xs1, vd`
/// Rust: `vfdiv_vf(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VfdivVfEmitter<T0, T1, T2, T3> {
    fn vfdiv_vf(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vfdiv.vv` instruction.
///
/// # Forms
/// Assembly: `vfdiv.vv vm, vs2, vs1, vd`
/// Rust: `vfdiv_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VfdivVvEmitter<T0, T1, T2, T3> {
    fn vfdiv_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vfirst.m` instruction.
///
/// # Forms
/// Assembly: `vfirst.m vm, vs2, xd`
/// Rust: `vfirst_m(rd, vs2, vm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VfirstMEmitter<T0, T1, T2> {
    fn vfirst_m(&mut self, rd: T0, vs2: T1, vm: T2);
}

/// RISC-V `vfmacc.vf` instruction.
///
/// # Forms
/// Assembly: `vfmacc.vf vm, vs2, xs1, vd`
/// Rust: `vfmacc_vf(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VfmaccVfEmitter<T0, T1, T2, T3> {
    fn vfmacc_vf(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vfmacc.vv` instruction.
///
/// # Forms
/// Assembly: `vfmacc.vv vm, vs2, vs1, vd`
/// Rust: `vfmacc_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VfmaccVvEmitter<T0, T1, T2, T3> {
    fn vfmacc_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vfmadd.vf` instruction.
///
/// # Forms
/// Assembly: `vfmadd.vf vm, vs2, xs1, vd`
/// Rust: `vfmadd_vf(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VfmaddVfEmitter<T0, T1, T2, T3> {
    fn vfmadd_vf(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vfmadd.vv` instruction.
///
/// # Forms
/// Assembly: `vfmadd.vv vm, vs2, vs1, vd`
/// Rust: `vfmadd_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VfmaddVvEmitter<T0, T1, T2, T3> {
    fn vfmadd_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vfmax.vf` instruction.
///
/// # Forms
/// Assembly: `vfmax.vf vm, vs2, xs1, vd`
/// Rust: `vfmax_vf(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VfmaxVfEmitter<T0, T1, T2, T3> {
    fn vfmax_vf(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vfmax.vv` instruction.
///
/// # Forms
/// Assembly: `vfmax.vv vm, vs2, vs1, vd`
/// Rust: `vfmax_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VfmaxVvEmitter<T0, T1, T2, T3> {
    fn vfmax_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vfmerge.vfm` instruction.
///
/// # Forms
/// Assembly: `vfmerge.vfm vs2, xs1, vd`
/// Rust: `vfmerge_vfm(vd, rs1, vs2)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `rs1` — Source register.
/// - `vs2` — Vector register operand.
pub trait VfmergeVfmEmitter<T0, T1, T2> {
    fn vfmerge_vfm(&mut self, vd: T0, rs1: T1, vs2: T2);
}

/// RISC-V `vfmin.vf` instruction.
///
/// # Forms
/// Assembly: `vfmin.vf vm, vs2, xs1, vd`
/// Rust: `vfmin_vf(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VfminVfEmitter<T0, T1, T2, T3> {
    fn vfmin_vf(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vfmin.vv` instruction.
///
/// # Forms
/// Assembly: `vfmin.vv vm, vs2, vs1, vd`
/// Rust: `vfmin_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VfminVvEmitter<T0, T1, T2, T3> {
    fn vfmin_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vfmsac.vf` instruction.
///
/// # Forms
/// Assembly: `vfmsac.vf vm, vs2, xs1, vd`
/// Rust: `vfmsac_vf(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VfmsacVfEmitter<T0, T1, T2, T3> {
    fn vfmsac_vf(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vfmsac.vv` instruction.
///
/// # Forms
/// Assembly: `vfmsac.vv vm, vs2, vs1, vd`
/// Rust: `vfmsac_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VfmsacVvEmitter<T0, T1, T2, T3> {
    fn vfmsac_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vfmsub.vf` instruction.
///
/// # Forms
/// Assembly: `vfmsub.vf vm, vs2, xs1, vd`
/// Rust: `vfmsub_vf(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VfmsubVfEmitter<T0, T1, T2, T3> {
    fn vfmsub_vf(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vfmsub.vv` instruction.
///
/// # Forms
/// Assembly: `vfmsub.vv vm, vs2, vs1, vd`
/// Rust: `vfmsub_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VfmsubVvEmitter<T0, T1, T2, T3> {
    fn vfmsub_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vfmul.vf` instruction.
///
/// # Forms
/// Assembly: `vfmul.vf vm, vs2, xs1, vd`
/// Rust: `vfmul_vf(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VfmulVfEmitter<T0, T1, T2, T3> {
    fn vfmul_vf(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vfmul.vv` instruction.
///
/// # Forms
/// Assembly: `vfmul.vv vm, vs2, vs1, vd`
/// Rust: `vfmul_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VfmulVvEmitter<T0, T1, T2, T3> {
    fn vfmul_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vfmv.f.s` instruction.
///
/// # Forms
/// Assembly: `vfmv.f.s vs2, xd`
/// Rust: `vfmv_f_s(rd, vs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `vs2` — Vector register operand.
pub trait VfmvFSEmitter<T0, T1> {
    fn vfmv_f_s(&mut self, rd: T0, vs2: T1);
}

/// RISC-V `vfmv.s.f` instruction.
///
/// # Forms
/// Assembly: `vfmv.s.f xs1, vd`
/// Rust: `vfmv_s_f(vd, rs1)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `rs1` — Source register.
pub trait VfmvSFEmitter<T0, T1> {
    fn vfmv_s_f(&mut self, vd: T0, rs1: T1);
}

/// RISC-V `vfmv.v.f` instruction.
///
/// # Forms
/// Assembly: `vfmv.v.f xs1, vd`
/// Rust: `vfmv_v_f(vd, rs1)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `rs1` — Source register.
pub trait VfmvVFEmitter<T0, T1> {
    fn vfmv_v_f(&mut self, vd: T0, rs1: T1);
}

/// RISC-V `vfncvt.f.f.w` instruction.
///
/// # Forms
/// Assembly: `vfncvt.f.f.w vm, vs2, vd`
/// Rust: `vfncvt_f_f_w(vd, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VfncvtFFWEmitter<T0, T1, T2> {
    fn vfncvt_f_f_w(&mut self, vd: T0, vs2: T1, vm: T2);
}

/// RISC-V `vfncvt.f.x.w` instruction.
///
/// # Forms
/// Assembly: `vfncvt.f.x.w vm, vs2, vd`
/// Rust: `vfncvt_f_x_w(vd, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VfncvtFXWEmitter<T0, T1, T2> {
    fn vfncvt_f_x_w(&mut self, vd: T0, vs2: T1, vm: T2);
}

/// RISC-V `vfncvt.f.xu.w` instruction.
///
/// # Forms
/// Assembly: `vfncvt.f.xu.w vm, vs2, vd`
/// Rust: `vfncvt_f_xu_w(vd, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VfncvtFXuWEmitter<T0, T1, T2> {
    fn vfncvt_f_xu_w(&mut self, vd: T0, vs2: T1, vm: T2);
}

/// RISC-V `vfncvt.rod.f.f.w` instruction.
///
/// # Forms
/// Assembly: `vfncvt.rod.f.f.w vm, vs2, vd`
/// Rust: `vfncvt_rod_f_f_w(vd, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VfncvtRodFFWEmitter<T0, T1, T2> {
    fn vfncvt_rod_f_f_w(&mut self, vd: T0, vs2: T1, vm: T2);
}

/// RISC-V `vfncvt.rtz.x.f.w` instruction.
///
/// # Forms
/// Assembly: `vfncvt.rtz.x.f.w vm, vs2, vd`
/// Rust: `vfncvt_rtz_x_f_w(vd, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VfncvtRtzXFWEmitter<T0, T1, T2> {
    fn vfncvt_rtz_x_f_w(&mut self, vd: T0, vs2: T1, vm: T2);
}

/// RISC-V `vfncvt.rtz.xu.f.w` instruction.
///
/// # Forms
/// Assembly: `vfncvt.rtz.xu.f.w vm, vs2, vd`
/// Rust: `vfncvt_rtz_xu_f_w(vd, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VfncvtRtzXuFWEmitter<T0, T1, T2> {
    fn vfncvt_rtz_xu_f_w(&mut self, vd: T0, vs2: T1, vm: T2);
}

/// RISC-V `vfncvt.x.f.w` instruction.
///
/// # Forms
/// Assembly: `vfncvt.x.f.w vm, vs2, vd`
/// Rust: `vfncvt_x_f_w(vd, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VfncvtXFWEmitter<T0, T1, T2> {
    fn vfncvt_x_f_w(&mut self, vd: T0, vs2: T1, vm: T2);
}

/// RISC-V `vfncvt.xu.f.w` instruction.
///
/// # Forms
/// Assembly: `vfncvt.xu.f.w vm, vs2, vd`
/// Rust: `vfncvt_xu_f_w(vd, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VfncvtXuFWEmitter<T0, T1, T2> {
    fn vfncvt_xu_f_w(&mut self, vd: T0, vs2: T1, vm: T2);
}

/// RISC-V `vfncvtbf16.f.f.w` instruction.
///
/// # Forms
/// Assembly: `vfncvtbf16.f.f.w vm, vs2, vd`
/// Rust: `vfncvtbf16_f_f_w(vd, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait Vfncvtbf16FFWEmitter<T0, T1, T2> {
    fn vfncvtbf16_f_f_w(&mut self, vd: T0, vs2: T1, vm: T2);
}

/// RISC-V `vfnmacc.vf` instruction.
///
/// # Forms
/// Assembly: `vfnmacc.vf vm, vs2, xs1, vd`
/// Rust: `vfnmacc_vf(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VfnmaccVfEmitter<T0, T1, T2, T3> {
    fn vfnmacc_vf(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vfnmacc.vv` instruction.
///
/// # Forms
/// Assembly: `vfnmacc.vv vm, vs2, vs1, vd`
/// Rust: `vfnmacc_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VfnmaccVvEmitter<T0, T1, T2, T3> {
    fn vfnmacc_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vfnmadd.vf` instruction.
///
/// # Forms
/// Assembly: `vfnmadd.vf vm, vs2, xs1, vd`
/// Rust: `vfnmadd_vf(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VfnmaddVfEmitter<T0, T1, T2, T3> {
    fn vfnmadd_vf(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vfnmadd.vv` instruction.
///
/// # Forms
/// Assembly: `vfnmadd.vv vm, vs2, vs1, vd`
/// Rust: `vfnmadd_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VfnmaddVvEmitter<T0, T1, T2, T3> {
    fn vfnmadd_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vfnmsac.vf` instruction.
///
/// # Forms
/// Assembly: `vfnmsac.vf vm, vs2, xs1, vd`
/// Rust: `vfnmsac_vf(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VfnmsacVfEmitter<T0, T1, T2, T3> {
    fn vfnmsac_vf(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vfnmsac.vv` instruction.
///
/// # Forms
/// Assembly: `vfnmsac.vv vm, vs2, vs1, vd`
/// Rust: `vfnmsac_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VfnmsacVvEmitter<T0, T1, T2, T3> {
    fn vfnmsac_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vfnmsub.vf` instruction.
///
/// # Forms
/// Assembly: `vfnmsub.vf vm, vs2, xs1, vd`
/// Rust: `vfnmsub_vf(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VfnmsubVfEmitter<T0, T1, T2, T3> {
    fn vfnmsub_vf(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vfnmsub.vv` instruction.
///
/// # Forms
/// Assembly: `vfnmsub.vv vm, vs2, vs1, vd`
/// Rust: `vfnmsub_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VfnmsubVvEmitter<T0, T1, T2, T3> {
    fn vfnmsub_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vfrdiv.vf` instruction.
///
/// # Forms
/// Assembly: `vfrdiv.vf vm, vs2, xs1, vd`
/// Rust: `vfrdiv_vf(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VfrdivVfEmitter<T0, T1, T2, T3> {
    fn vfrdiv_vf(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vfrec7.v` instruction.
///
/// # Forms
/// Assembly: `vfrec7.v vm, vs2, vd`
/// Rust: `vfrec7_v(vd, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait Vfrec7VEmitter<T0, T1, T2> {
    fn vfrec7_v(&mut self, vd: T0, vs2: T1, vm: T2);
}

/// RISC-V `vfredmax.vs` instruction.
///
/// # Forms
/// Assembly: `vfredmax.vs vm, vs2, vs1, vd`
/// Rust: `vfredmax_vs(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VfredmaxVsEmitter<T0, T1, T2, T3> {
    fn vfredmax_vs(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vfredmin.vs` instruction.
///
/// # Forms
/// Assembly: `vfredmin.vs vm, vs2, vs1, vd`
/// Rust: `vfredmin_vs(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VfredminVsEmitter<T0, T1, T2, T3> {
    fn vfredmin_vs(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vfredosum.vs` instruction.
///
/// # Forms
/// Assembly: `vfredosum.vs vm, vs2, vs1, vd`
/// Rust: `vfredosum_vs(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VfredosumVsEmitter<T0, T1, T2, T3> {
    fn vfredosum_vs(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vfredsum.vs` instruction.
///
/// # Forms
/// Assembly: `vfredsum.vs vd vs1 vs2 vm`
/// Rust: `vfredsum_vs(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VfredsumVsEmitter<T0, T1, T2, T3> {
    fn vfredsum_vs(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vfredusum.vs` instruction.
///
/// # Forms
/// Assembly: `vfredusum.vs vm, vs2, vs1, vd`
/// Rust: `vfredusum_vs(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VfredusumVsEmitter<T0, T1, T2, T3> {
    fn vfredusum_vs(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vfrsqrt7.v` instruction.
///
/// # Forms
/// Assembly: `vfrsqrt7.v vm, vs2, vd`
/// Rust: `vfrsqrt7_v(vd, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait Vfrsqrt7VEmitter<T0, T1, T2> {
    fn vfrsqrt7_v(&mut self, vd: T0, vs2: T1, vm: T2);
}

/// RISC-V `vfrsub.vf` instruction.
///
/// # Forms
/// Assembly: `vfrsub.vf vm, vs2, xs1, vd`
/// Rust: `vfrsub_vf(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VfrsubVfEmitter<T0, T1, T2, T3> {
    fn vfrsub_vf(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vfsgnj.vf` instruction.
///
/// # Forms
/// Assembly: `vfsgnj.vf vm, vs2, xs1, vd`
/// Rust: `vfsgnj_vf(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VfsgnjVfEmitter<T0, T1, T2, T3> {
    fn vfsgnj_vf(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vfsgnj.vv` instruction.
///
/// # Forms
/// Assembly: `vfsgnj.vv vm, vs2, vs1, vd`
/// Rust: `vfsgnj_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VfsgnjVvEmitter<T0, T1, T2, T3> {
    fn vfsgnj_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vfsgnjn.vf` instruction.
///
/// # Forms
/// Assembly: `vfsgnjn.vf vm, vs2, xs1, vd`
/// Rust: `vfsgnjn_vf(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VfsgnjnVfEmitter<T0, T1, T2, T3> {
    fn vfsgnjn_vf(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vfsgnjn.vv` instruction.
///
/// # Forms
/// Assembly: `vfsgnjn.vv vm, vs2, vs1, vd`
/// Rust: `vfsgnjn_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VfsgnjnVvEmitter<T0, T1, T2, T3> {
    fn vfsgnjn_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vfsgnjx.vf` instruction.
///
/// # Forms
/// Assembly: `vfsgnjx.vf vm, vs2, xs1, vd`
/// Rust: `vfsgnjx_vf(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VfsgnjxVfEmitter<T0, T1, T2, T3> {
    fn vfsgnjx_vf(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vfsgnjx.vv` instruction.
///
/// # Forms
/// Assembly: `vfsgnjx.vv vm, vs2, vs1, vd`
/// Rust: `vfsgnjx_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VfsgnjxVvEmitter<T0, T1, T2, T3> {
    fn vfsgnjx_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vfslide1down.vf` instruction.
///
/// # Forms
/// Assembly: `vfslide1down.vf vm, vs2, xs1, vd`
/// Rust: `vfslide1down_vf(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait Vfslide1DownVfEmitter<T0, T1, T2, T3> {
    fn vfslide1down_vf(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vfslide1up.vf` instruction.
///
/// # Forms
/// Assembly: `vfslide1up.vf vm, vs2, xs1, vd`
/// Rust: `vfslide1up_vf(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait Vfslide1UpVfEmitter<T0, T1, T2, T3> {
    fn vfslide1up_vf(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vfsqrt.v` instruction.
///
/// # Forms
/// Assembly: `vfsqrt.v vm, vs2, vd`
/// Rust: `vfsqrt_v(vd, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VfsqrtVEmitter<T0, T1, T2> {
    fn vfsqrt_v(&mut self, vd: T0, vs2: T1, vm: T2);
}

/// RISC-V `vfsub.vf` instruction.
///
/// # Forms
/// Assembly: `vfsub.vf vm, vs2, xs1, vd`
/// Rust: `vfsub_vf(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VfsubVfEmitter<T0, T1, T2, T3> {
    fn vfsub_vf(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vfsub.vv` instruction.
///
/// # Forms
/// Assembly: `vfsub.vv vm, vs2, vs1, vd`
/// Rust: `vfsub_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VfsubVvEmitter<T0, T1, T2, T3> {
    fn vfsub_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vfwadd.vf` instruction.
///
/// # Forms
/// Assembly: `vfwadd.vf vm, vs2, xs1, vd`
/// Rust: `vfwadd_vf(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VfwaddVfEmitter<T0, T1, T2, T3> {
    fn vfwadd_vf(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vfwadd.vv` instruction.
///
/// # Forms
/// Assembly: `vfwadd.vv vm, vs2, vs1, vd`
/// Rust: `vfwadd_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VfwaddVvEmitter<T0, T1, T2, T3> {
    fn vfwadd_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vfwadd.wf` instruction.
///
/// # Forms
/// Assembly: `vfwadd.wf vm, vs2, xs1, vd`
/// Rust: `vfwadd_wf(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VfwaddWfEmitter<T0, T1, T2, T3> {
    fn vfwadd_wf(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vfwadd.wv` instruction.
///
/// # Forms
/// Assembly: `vfwadd.wv vm, vs2, vs1, vd`
/// Rust: `vfwadd_wv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VfwaddWvEmitter<T0, T1, T2, T3> {
    fn vfwadd_wv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vfwcvt.f.f.v` instruction.
///
/// # Forms
/// Assembly: `vfwcvt.f.f.v vm, vs2, vd`
/// Rust: `vfwcvt_f_f_v(vd, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VfwcvtFFVEmitter<T0, T1, T2> {
    fn vfwcvt_f_f_v(&mut self, vd: T0, vs2: T1, vm: T2);
}

/// RISC-V `vfwcvt.f.x.v` instruction.
///
/// # Forms
/// Assembly: `vfwcvt.f.x.v vm, vs2, vd`
/// Rust: `vfwcvt_f_x_v(vd, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VfwcvtFXVEmitter<T0, T1, T2> {
    fn vfwcvt_f_x_v(&mut self, vd: T0, vs2: T1, vm: T2);
}

/// RISC-V `vfwcvt.f.xu.v` instruction.
///
/// # Forms
/// Assembly: `vfwcvt.f.xu.v vm, vs2, vd`
/// Rust: `vfwcvt_f_xu_v(vd, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VfwcvtFXuVEmitter<T0, T1, T2> {
    fn vfwcvt_f_xu_v(&mut self, vd: T0, vs2: T1, vm: T2);
}

/// RISC-V `vfwcvt.rtz.x.f.v` instruction.
///
/// # Forms
/// Assembly: `vfwcvt.rtz.x.f.v vm, vs2, vd`
/// Rust: `vfwcvt_rtz_x_f_v(vd, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VfwcvtRtzXFVEmitter<T0, T1, T2> {
    fn vfwcvt_rtz_x_f_v(&mut self, vd: T0, vs2: T1, vm: T2);
}

/// RISC-V `vfwcvt.rtz.xu.f.v` instruction.
///
/// # Forms
/// Assembly: `vfwcvt.rtz.xu.f.v vm, vs2, vd`
/// Rust: `vfwcvt_rtz_xu_f_v(vd, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VfwcvtRtzXuFVEmitter<T0, T1, T2> {
    fn vfwcvt_rtz_xu_f_v(&mut self, vd: T0, vs2: T1, vm: T2);
}

/// RISC-V `vfwcvt.x.f.v` instruction.
///
/// # Forms
/// Assembly: `vfwcvt.x.f.v vm, vs2, vd`
/// Rust: `vfwcvt_x_f_v(vd, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VfwcvtXFVEmitter<T0, T1, T2> {
    fn vfwcvt_x_f_v(&mut self, vd: T0, vs2: T1, vm: T2);
}

/// RISC-V `vfwcvt.xu.f.v` instruction.
///
/// # Forms
/// Assembly: `vfwcvt.xu.f.v vm, vs2, vd`
/// Rust: `vfwcvt_xu_f_v(vd, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VfwcvtXuFVEmitter<T0, T1, T2> {
    fn vfwcvt_xu_f_v(&mut self, vd: T0, vs2: T1, vm: T2);
}

/// RISC-V `vfwcvtbf16.f.f.v` instruction.
///
/// # Forms
/// Assembly: `vfwcvtbf16.f.f.v vm, vs2, vd`
/// Rust: `vfwcvtbf16_f_f_v(vd, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait Vfwcvtbf16FFVEmitter<T0, T1, T2> {
    fn vfwcvtbf16_f_f_v(&mut self, vd: T0, vs2: T1, vm: T2);
}

/// RISC-V `vfwmacc.vf` instruction.
///
/// # Forms
/// Assembly: `vfwmacc.vf vm, vs2, xs1, vd`
/// Rust: `vfwmacc_vf(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VfwmaccVfEmitter<T0, T1, T2, T3> {
    fn vfwmacc_vf(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vfwmacc.vv` instruction.
///
/// # Forms
/// Assembly: `vfwmacc.vv vm, vs2, vs1, vd`
/// Rust: `vfwmacc_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VfwmaccVvEmitter<T0, T1, T2, T3> {
    fn vfwmacc_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vfwmaccbf16.vf` instruction.
///
/// # Forms
/// Assembly: `vfwmaccbf16.vf vm, vs2, xs1, vd`
/// Rust: `vfwmaccbf16_vf(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait Vfwmaccbf16VfEmitter<T0, T1, T2, T3> {
    fn vfwmaccbf16_vf(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vfwmaccbf16.vv` instruction.
///
/// # Forms
/// Assembly: `vfwmaccbf16.vv vm, vs2, vs1, vd`
/// Rust: `vfwmaccbf16_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait Vfwmaccbf16VvEmitter<T0, T1, T2, T3> {
    fn vfwmaccbf16_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vfwmsac.vf` instruction.
///
/// # Forms
/// Assembly: `vfwmsac.vf vm, vs2, xs1, vd`
/// Rust: `vfwmsac_vf(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VfwmsacVfEmitter<T0, T1, T2, T3> {
    fn vfwmsac_vf(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vfwmsac.vv` instruction.
///
/// # Forms
/// Assembly: `vfwmsac.vv vm, vs2, vs1, vd`
/// Rust: `vfwmsac_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VfwmsacVvEmitter<T0, T1, T2, T3> {
    fn vfwmsac_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vfwmul.vf` instruction.
///
/// # Forms
/// Assembly: `vfwmul.vf vm, vs2, xs1, vd`
/// Rust: `vfwmul_vf(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VfwmulVfEmitter<T0, T1, T2, T3> {
    fn vfwmul_vf(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vfwmul.vv` instruction.
///
/// # Forms
/// Assembly: `vfwmul.vv vm, vs2, vs1, vd`
/// Rust: `vfwmul_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VfwmulVvEmitter<T0, T1, T2, T3> {
    fn vfwmul_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vfwnmacc.vf` instruction.
///
/// # Forms
/// Assembly: `vfwnmacc.vf vm, vs2, xs1, vd`
/// Rust: `vfwnmacc_vf(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VfwnmaccVfEmitter<T0, T1, T2, T3> {
    fn vfwnmacc_vf(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vfwnmacc.vv` instruction.
///
/// # Forms
/// Assembly: `vfwnmacc.vv vm, vs2, vs1, vd`
/// Rust: `vfwnmacc_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VfwnmaccVvEmitter<T0, T1, T2, T3> {
    fn vfwnmacc_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vfwnmsac.vf` instruction.
///
/// # Forms
/// Assembly: `vfwnmsac.vf vm, vs2, xs1, vd`
/// Rust: `vfwnmsac_vf(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VfwnmsacVfEmitter<T0, T1, T2, T3> {
    fn vfwnmsac_vf(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vfwnmsac.vv` instruction.
///
/// # Forms
/// Assembly: `vfwnmsac.vv vm, vs2, vs1, vd`
/// Rust: `vfwnmsac_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VfwnmsacVvEmitter<T0, T1, T2, T3> {
    fn vfwnmsac_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vfwredosum.vs` instruction.
///
/// # Forms
/// Assembly: `vfwredosum.vs vm, vs2, vs1, vd`
/// Rust: `vfwredosum_vs(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VfwredosumVsEmitter<T0, T1, T2, T3> {
    fn vfwredosum_vs(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vfwredsum.vs` instruction.
///
/// # Forms
/// Assembly: `vfwredsum.vs vd vs1 vs2 vm`
/// Rust: `vfwredsum_vs(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VfwredsumVsEmitter<T0, T1, T2, T3> {
    fn vfwredsum_vs(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vfwredusum.vs` instruction.
///
/// # Forms
/// Assembly: `vfwredusum.vs vm, vs2, vs1, vd`
/// Rust: `vfwredusum_vs(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VfwredusumVsEmitter<T0, T1, T2, T3> {
    fn vfwredusum_vs(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vfwsub.vf` instruction.
///
/// # Forms
/// Assembly: `vfwsub.vf vm, vs2, xs1, vd`
/// Rust: `vfwsub_vf(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VfwsubVfEmitter<T0, T1, T2, T3> {
    fn vfwsub_vf(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vfwsub.vv` instruction.
///
/// # Forms
/// Assembly: `vfwsub.vv vm, vs2, vs1, vd`
/// Rust: `vfwsub_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VfwsubVvEmitter<T0, T1, T2, T3> {
    fn vfwsub_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vfwsub.wf` instruction.
///
/// # Forms
/// Assembly: `vfwsub.wf vm, vs2, xs1, vd`
/// Rust: `vfwsub_wf(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VfwsubWfEmitter<T0, T1, T2, T3> {
    fn vfwsub_wf(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vfwsub.wv` instruction.
///
/// # Forms
/// Assembly: `vfwsub.wv vm, vs2, vs1, vd`
/// Rust: `vfwsub_wv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VfwsubWvEmitter<T0, T1, T2, T3> {
    fn vfwsub_wv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vghsh.vv` instruction.
///
/// # Forms
/// Assembly: `vghsh.vv vs2, vs1, vd`
/// Rust: `vghsh_vv(vd, vs1, vs2)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
pub trait VghshVvEmitter<T0, T1, T2> {
    fn vghsh_vv(&mut self, vd: T0, vs1: T1, vs2: T2);
}

/// RISC-V `vgmul.vv` instruction.
///
/// # Forms
/// Assembly: `vgmul.vv vs2, vd`
/// Rust: `vgmul_vv(vd, vs2)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
pub trait VgmulVvEmitter<T0, T1> {
    fn vgmul_vv(&mut self, vd: T0, vs2: T1);
}

/// RISC-V `vid.v` instruction.
///
/// # Forms
/// Assembly: `vid.v vm, vd`
/// Rust: `vid_v(vd, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VidVEmitter<T0, T1> {
    fn vid_v(&mut self, vd: T0, vm: T1);
}

/// RISC-V `viota.m` instruction.
///
/// # Forms
/// Assembly: `viota.m vm, vs2, vd`
/// Rust: `viota_m(vd, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait ViotaMEmitter<T0, T1, T2> {
    fn viota_m(&mut self, vd: T0, vs2: T1, vm: T2);
}

/// RISC-V `vl1r.v` instruction.
///
/// # Forms
/// Assembly: `vl1r.v vd rs1`
/// Rust: `vl1r_v(vd, rs1)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `rs1` — Memory base register.
pub trait Vl1RVEmitter<T0, T1> {
    fn vl1r_v(&mut self, vd: T0, rs1: T1);
}

/// RISC-V `vl1re16.v` instruction.
///
/// # Forms
/// Assembly: `vl1re16.v xs1, vd`
/// Rust: `vl1re16_v(vd, rs1)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `rs1` — Memory base register.
pub trait Vl1Re16VEmitter<T0, T1> {
    fn vl1re16_v(&mut self, vd: T0, rs1: T1);
}

/// RISC-V `vl1re32.v` instruction.
///
/// # Forms
/// Assembly: `vl1re32.v xs1, vd`
/// Rust: `vl1re32_v(vd, rs1)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `rs1` — Memory base register.
pub trait Vl1Re32VEmitter<T0, T1> {
    fn vl1re32_v(&mut self, vd: T0, rs1: T1);
}

/// RISC-V `vl1re64.v` instruction.
///
/// # Forms
/// Assembly: `vl1re64.v xs1, vd`
/// Rust: `vl1re64_v(vd, rs1)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `rs1` — Memory base register.
pub trait Vl1Re64VEmitter<T0, T1> {
    fn vl1re64_v(&mut self, vd: T0, rs1: T1);
}

/// RISC-V `vl1re8.v` instruction.
///
/// # Forms
/// Assembly: `vl1re8.v xs1, vd`
/// Rust: `vl1re8_v(vd, rs1)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `rs1` — Memory base register.
pub trait Vl1Re8VEmitter<T0, T1> {
    fn vl1re8_v(&mut self, vd: T0, rs1: T1);
}

/// RISC-V `vl2r.v` instruction.
///
/// # Forms
/// Assembly: `vl2r.v vd rs1`
/// Rust: `vl2r_v(vd, rs1)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `rs1` — Memory base register.
pub trait Vl2RVEmitter<T0, T1> {
    fn vl2r_v(&mut self, vd: T0, rs1: T1);
}

/// RISC-V `vl2re16.v` instruction.
///
/// # Forms
/// Assembly: `vl2re16.v xs1, vd`
/// Rust: `vl2re16_v(vd, rs1)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `rs1` — Memory base register.
pub trait Vl2Re16VEmitter<T0, T1> {
    fn vl2re16_v(&mut self, vd: T0, rs1: T1);
}

/// RISC-V `vl2re32.v` instruction.
///
/// # Forms
/// Assembly: `vl2re32.v xs1, vd`
/// Rust: `vl2re32_v(vd, rs1)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `rs1` — Memory base register.
pub trait Vl2Re32VEmitter<T0, T1> {
    fn vl2re32_v(&mut self, vd: T0, rs1: T1);
}

/// RISC-V `vl2re64.v` instruction.
///
/// # Forms
/// Assembly: `vl2re64.v xs1, vd`
/// Rust: `vl2re64_v(vd, rs1)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `rs1` — Memory base register.
pub trait Vl2Re64VEmitter<T0, T1> {
    fn vl2re64_v(&mut self, vd: T0, rs1: T1);
}

/// RISC-V `vl2re8.v` instruction.
///
/// # Forms
/// Assembly: `vl2re8.v xs1, vd`
/// Rust: `vl2re8_v(vd, rs1)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `rs1` — Memory base register.
pub trait Vl2Re8VEmitter<T0, T1> {
    fn vl2re8_v(&mut self, vd: T0, rs1: T1);
}

/// RISC-V `vl4r.v` instruction.
///
/// # Forms
/// Assembly: `vl4r.v vd rs1`
/// Rust: `vl4r_v(vd, rs1)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `rs1` — Memory base register.
pub trait Vl4RVEmitter<T0, T1> {
    fn vl4r_v(&mut self, vd: T0, rs1: T1);
}

/// RISC-V `vl4re16.v` instruction.
///
/// # Forms
/// Assembly: `vl4re16.v xs1, vd`
/// Rust: `vl4re16_v(vd, rs1)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `rs1` — Memory base register.
pub trait Vl4Re16VEmitter<T0, T1> {
    fn vl4re16_v(&mut self, vd: T0, rs1: T1);
}

/// RISC-V `vl4re32.v` instruction.
///
/// # Forms
/// Assembly: `vl4re32.v xs1, vd`
/// Rust: `vl4re32_v(vd, rs1)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `rs1` — Memory base register.
pub trait Vl4Re32VEmitter<T0, T1> {
    fn vl4re32_v(&mut self, vd: T0, rs1: T1);
}

/// RISC-V `vl4re64.v` instruction.
///
/// # Forms
/// Assembly: `vl4re64.v xs1, vd`
/// Rust: `vl4re64_v(vd, rs1)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `rs1` — Memory base register.
pub trait Vl4Re64VEmitter<T0, T1> {
    fn vl4re64_v(&mut self, vd: T0, rs1: T1);
}

/// RISC-V `vl4re8.v` instruction.
///
/// # Forms
/// Assembly: `vl4re8.v xs1, vd`
/// Rust: `vl4re8_v(vd, rs1)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `rs1` — Memory base register.
pub trait Vl4Re8VEmitter<T0, T1> {
    fn vl4re8_v(&mut self, vd: T0, rs1: T1);
}

/// RISC-V `vl8r.v` instruction.
///
/// # Forms
/// Assembly: `vl8r.v vd rs1`
/// Rust: `vl8r_v(vd, rs1)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `rs1` — Memory base register.
pub trait Vl8RVEmitter<T0, T1> {
    fn vl8r_v(&mut self, vd: T0, rs1: T1);
}

/// RISC-V `vl8re16.v` instruction.
///
/// # Forms
/// Assembly: `vl8re16.v xs1, vd`
/// Rust: `vl8re16_v(vd, rs1)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `rs1` — Memory base register.
pub trait Vl8Re16VEmitter<T0, T1> {
    fn vl8re16_v(&mut self, vd: T0, rs1: T1);
}

/// RISC-V `vl8re32.v` instruction.
///
/// # Forms
/// Assembly: `vl8re32.v xs1, vd`
/// Rust: `vl8re32_v(vd, rs1)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `rs1` — Memory base register.
pub trait Vl8Re32VEmitter<T0, T1> {
    fn vl8re32_v(&mut self, vd: T0, rs1: T1);
}

/// RISC-V `vl8re64.v` instruction.
///
/// # Forms
/// Assembly: `vl8re64.v xs1, vd`
/// Rust: `vl8re64_v(vd, rs1)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `rs1` — Memory base register.
pub trait Vl8Re64VEmitter<T0, T1> {
    fn vl8re64_v(&mut self, vd: T0, rs1: T1);
}

/// RISC-V `vl8re8.v` instruction.
///
/// # Forms
/// Assembly: `vl8re8.v xs1, vd`
/// Rust: `vl8re8_v(vd, rs1)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `rs1` — Memory base register.
pub trait Vl8Re8VEmitter<T0, T1> {
    fn vl8re8_v(&mut self, vd: T0, rs1: T1);
}

/// RISC-V `vle16.v` instruction.
///
/// # Forms
/// Assembly: `vle16.v vm, xs1, vd`
/// Rust: `vle16_v(vd, rs1, vm, nf)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `rs1` — Memory base register.
/// - `vm` — Vector mask control.
/// - `nf` — Vector segment field count.
pub trait Vle16VEmitter<T0, T1, T2, T3> {
    fn vle16_v(&mut self, vd: T0, rs1: T1, vm: T2, nf: T3);
}

/// RISC-V `vle16ff.v` instruction.
///
/// # Forms
/// Assembly: `vle16ff.v vm, xs1, vd`
/// Rust: `vle16ff_v(vd, rs1, vm, nf)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `rs1` — Memory base register.
/// - `vm` — Vector mask control.
/// - `nf` — Vector segment field count.
pub trait Vle16FfVEmitter<T0, T1, T2, T3> {
    fn vle16ff_v(&mut self, vd: T0, rs1: T1, vm: T2, nf: T3);
}

/// RISC-V `vle1.v` instruction.
///
/// # Forms
/// Assembly: `vle1.v vd rs1`
/// Rust: `vle1_v(vd, rs1)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `rs1` — Memory base register.
pub trait Vle1VEmitter<T0, T1> {
    fn vle1_v(&mut self, vd: T0, rs1: T1);
}

/// RISC-V `vle32.v` instruction.
///
/// # Forms
/// Assembly: `vle32.v vm, xs1, vd`
/// Rust: `vle32_v(vd, rs1, vm, nf)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `rs1` — Memory base register.
/// - `vm` — Vector mask control.
/// - `nf` — Vector segment field count.
pub trait Vle32VEmitter<T0, T1, T2, T3> {
    fn vle32_v(&mut self, vd: T0, rs1: T1, vm: T2, nf: T3);
}

/// RISC-V `vle32ff.v` instruction.
///
/// # Forms
/// Assembly: `vle32ff.v vm, xs1, vd`
/// Rust: `vle32ff_v(vd, rs1, vm, nf)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `rs1` — Memory base register.
/// - `vm` — Vector mask control.
/// - `nf` — Vector segment field count.
pub trait Vle32FfVEmitter<T0, T1, T2, T3> {
    fn vle32ff_v(&mut self, vd: T0, rs1: T1, vm: T2, nf: T3);
}

/// RISC-V `vle64.v` instruction.
///
/// # Forms
/// Assembly: `vle64.v vm, xs1, vd`
/// Rust: `vle64_v(vd, rs1, vm, nf)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `rs1` — Memory base register.
/// - `vm` — Vector mask control.
/// - `nf` — Vector segment field count.
pub trait Vle64VEmitter<T0, T1, T2, T3> {
    fn vle64_v(&mut self, vd: T0, rs1: T1, vm: T2, nf: T3);
}

/// RISC-V `vle64ff.v` instruction.
///
/// # Forms
/// Assembly: `vle64ff.v vm, xs1, vd`
/// Rust: `vle64ff_v(vd, rs1, vm, nf)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `rs1` — Memory base register.
/// - `vm` — Vector mask control.
/// - `nf` — Vector segment field count.
pub trait Vle64FfVEmitter<T0, T1, T2, T3> {
    fn vle64ff_v(&mut self, vd: T0, rs1: T1, vm: T2, nf: T3);
}

/// RISC-V `vle8.v` instruction.
///
/// # Forms
/// Assembly: `vle8.v vm, xs1, vd`
/// Rust: `vle8_v(vd, rs1, vm, nf)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `rs1` — Memory base register.
/// - `vm` — Vector mask control.
/// - `nf` — Vector segment field count.
pub trait Vle8VEmitter<T0, T1, T2, T3> {
    fn vle8_v(&mut self, vd: T0, rs1: T1, vm: T2, nf: T3);
}

/// RISC-V `vle8ff.v` instruction.
///
/// # Forms
/// Assembly: `vle8ff.v vm, xs1, vd`
/// Rust: `vle8ff_v(vd, rs1, vm, nf)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `rs1` — Memory base register.
/// - `vm` — Vector mask control.
/// - `nf` — Vector segment field count.
pub trait Vle8FfVEmitter<T0, T1, T2, T3> {
    fn vle8ff_v(&mut self, vd: T0, rs1: T1, vm: T2, nf: T3);
}

/// RISC-V `vlm.v` instruction.
///
/// # Forms
/// Assembly: `vlm.v xs1, vd`
/// Rust: `vlm_v(vd, rs1)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `rs1` — Memory base register.
pub trait VlmVEmitter<T0, T1> {
    fn vlm_v(&mut self, vd: T0, rs1: T1);
}

/// RISC-V `vloxei16.v` instruction.
///
/// # Forms
/// Assembly: `vloxei16.v vm, vs2, xs1, vd`
/// Rust: `vloxei16_v(vd, rs1, vs2, vm, nf)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `rs1` — Memory base register.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
/// - `nf` — Vector segment field count.
pub trait Vloxei16VEmitter<T0, T1, T2, T3, T4> {
    fn vloxei16_v(&mut self, vd: T0, rs1: T1, vs2: T2, vm: T3, nf: T4);
}

/// RISC-V `vloxei32.v` instruction.
///
/// # Forms
/// Assembly: `vloxei32.v vm, vs2, xs1, vd`
/// Rust: `vloxei32_v(vd, rs1, vs2, vm, nf)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `rs1` — Memory base register.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
/// - `nf` — Vector segment field count.
pub trait Vloxei32VEmitter<T0, T1, T2, T3, T4> {
    fn vloxei32_v(&mut self, vd: T0, rs1: T1, vs2: T2, vm: T3, nf: T4);
}

/// RISC-V `vloxei64.v` instruction.
///
/// # Forms
/// Assembly: `vloxei64.v vm, vs2, xs1, vd`
/// Rust: `vloxei64_v(vd, rs1, vs2, vm, nf)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `rs1` — Memory base register.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
/// - `nf` — Vector segment field count.
pub trait Vloxei64VEmitter<T0, T1, T2, T3, T4> {
    fn vloxei64_v(&mut self, vd: T0, rs1: T1, vs2: T2, vm: T3, nf: T4);
}

/// RISC-V `vloxei8.v` instruction.
///
/// # Forms
/// Assembly: `vloxei8.v vm, vs2, xs1, vd`
/// Rust: `vloxei8_v(vd, rs1, vs2, vm, nf)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `rs1` — Memory base register.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
/// - `nf` — Vector segment field count.
pub trait Vloxei8VEmitter<T0, T1, T2, T3, T4> {
    fn vloxei8_v(&mut self, vd: T0, rs1: T1, vs2: T2, vm: T3, nf: T4);
}

/// RISC-V `vlse16.v` instruction.
///
/// # Forms
/// Assembly: `vlse16.v vm, xs2, xs1, vd`
/// Rust: `vlse16_v(vd, rs1, rs2, vm, nf)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `rs1` — Memory base register.
/// - `rs2` — Source register.
/// - `vm` — Vector mask control.
/// - `nf` — Vector segment field count.
pub trait Vlse16VEmitter<T0, T1, T2, T3, T4> {
    fn vlse16_v(&mut self, vd: T0, rs1: T1, rs2: T2, vm: T3, nf: T4);
}

/// RISC-V `vlse32.v` instruction.
///
/// # Forms
/// Assembly: `vlse32.v vm, xs2, xs1, vd`
/// Rust: `vlse32_v(vd, rs1, rs2, vm, nf)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `rs1` — Memory base register.
/// - `rs2` — Source register.
/// - `vm` — Vector mask control.
/// - `nf` — Vector segment field count.
pub trait Vlse32VEmitter<T0, T1, T2, T3, T4> {
    fn vlse32_v(&mut self, vd: T0, rs1: T1, rs2: T2, vm: T3, nf: T4);
}

/// RISC-V `vlse64.v` instruction.
///
/// # Forms
/// Assembly: `vlse64.v vm, xs2, xs1, vd`
/// Rust: `vlse64_v(vd, rs1, rs2, vm, nf)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `rs1` — Memory base register.
/// - `rs2` — Source register.
/// - `vm` — Vector mask control.
/// - `nf` — Vector segment field count.
pub trait Vlse64VEmitter<T0, T1, T2, T3, T4> {
    fn vlse64_v(&mut self, vd: T0, rs1: T1, rs2: T2, vm: T3, nf: T4);
}

/// RISC-V `vlse8.v` instruction.
///
/// # Forms
/// Assembly: `vlse8.v vm, xs2, xs1, vd`
/// Rust: `vlse8_v(vd, rs1, rs2, vm, nf)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `rs1` — Memory base register.
/// - `rs2` — Source register.
/// - `vm` — Vector mask control.
/// - `nf` — Vector segment field count.
pub trait Vlse8VEmitter<T0, T1, T2, T3, T4> {
    fn vlse8_v(&mut self, vd: T0, rs1: T1, rs2: T2, vm: T3, nf: T4);
}

/// RISC-V `vluxei16.v` instruction.
///
/// # Forms
/// Assembly: `vluxei16.v vm, vs2, xs1, vd`
/// Rust: `vluxei16_v(vd, rs1, vs2, vm, nf)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `rs1` — Memory base register.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
/// - `nf` — Vector segment field count.
pub trait Vluxei16VEmitter<T0, T1, T2, T3, T4> {
    fn vluxei16_v(&mut self, vd: T0, rs1: T1, vs2: T2, vm: T3, nf: T4);
}

/// RISC-V `vluxei32.v` instruction.
///
/// # Forms
/// Assembly: `vluxei32.v vm, vs2, xs1, vd`
/// Rust: `vluxei32_v(vd, rs1, vs2, vm, nf)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `rs1` — Memory base register.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
/// - `nf` — Vector segment field count.
pub trait Vluxei32VEmitter<T0, T1, T2, T3, T4> {
    fn vluxei32_v(&mut self, vd: T0, rs1: T1, vs2: T2, vm: T3, nf: T4);
}

/// RISC-V `vluxei64.v` instruction.
///
/// # Forms
/// Assembly: `vluxei64.v vm, vs2, xs1, vd`
/// Rust: `vluxei64_v(vd, rs1, vs2, vm, nf)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `rs1` — Memory base register.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
/// - `nf` — Vector segment field count.
pub trait Vluxei64VEmitter<T0, T1, T2, T3, T4> {
    fn vluxei64_v(&mut self, vd: T0, rs1: T1, vs2: T2, vm: T3, nf: T4);
}

/// RISC-V `vluxei8.v` instruction.
///
/// # Forms
/// Assembly: `vluxei8.v vm, vs2, xs1, vd`
/// Rust: `vluxei8_v(vd, rs1, vs2, vm, nf)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `rs1` — Memory base register.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
/// - `nf` — Vector segment field count.
pub trait Vluxei8VEmitter<T0, T1, T2, T3, T4> {
    fn vluxei8_v(&mut self, vd: T0, rs1: T1, vs2: T2, vm: T3, nf: T4);
}

/// RISC-V `vmacc.vv` instruction.
///
/// # Forms
/// Assembly: `vmacc.vv vm, vs2, vs1, vd`
/// Rust: `vmacc_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VmaccVvEmitter<T0, T1, T2, T3> {
    fn vmacc_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vmacc.vx` instruction.
///
/// # Forms
/// Assembly: `vmacc.vx vm, vs2, xs1, vd`
/// Rust: `vmacc_vx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VmaccVxEmitter<T0, T1, T2, T3> {
    fn vmacc_vx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vmadc.vi` instruction.
///
/// # Forms
/// Assembly: `vmadc.vi vs2, vd, imm`
/// Rust: `vmadc_vi(vd, vs2, simm5)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `simm5` — Immediate encoding value.
pub trait VmadcViEmitter<T0, T1, T2> {
    fn vmadc_vi(&mut self, vd: T0, vs2: T1, simm5: T2);
}

/// RISC-V `vmadc.vim` instruction.
///
/// # Forms
/// Assembly: `vmadc.vim vs2, vd, imm`
/// Rust: `vmadc_vim(vd, vs2, simm5)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `simm5` — Immediate encoding value.
pub trait VmadcVimEmitter<T0, T1, T2> {
    fn vmadc_vim(&mut self, vd: T0, vs2: T1, simm5: T2);
}

/// RISC-V `vmadc.vv` instruction.
///
/// # Forms
/// Assembly: `vmadc.vv vs2, vs1, vd`
/// Rust: `vmadc_vv(vd, vs1, vs2)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
pub trait VmadcVvEmitter<T0, T1, T2> {
    fn vmadc_vv(&mut self, vd: T0, vs1: T1, vs2: T2);
}

/// RISC-V `vmadc.vvm` instruction.
///
/// # Forms
/// Assembly: `vmadc.vvm vs2, vs1, vd`
/// Rust: `vmadc_vvm(vd, vs1, vs2)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
pub trait VmadcVvmEmitter<T0, T1, T2> {
    fn vmadc_vvm(&mut self, vd: T0, vs1: T1, vs2: T2);
}

/// RISC-V `vmadc.vx` instruction.
///
/// # Forms
/// Assembly: `vmadc.vx vs2, xs1, vd`
/// Rust: `vmadc_vx(vd, rs1, vs2)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `rs1` — Source register.
/// - `vs2` — Vector register operand.
pub trait VmadcVxEmitter<T0, T1, T2> {
    fn vmadc_vx(&mut self, vd: T0, rs1: T1, vs2: T2);
}

/// RISC-V `vmadc.vxm` instruction.
///
/// # Forms
/// Assembly: `vmadc.vxm vs2, xs1, vd`
/// Rust: `vmadc_vxm(vd, rs1, vs2)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `rs1` — Source register.
/// - `vs2` — Vector register operand.
pub trait VmadcVxmEmitter<T0, T1, T2> {
    fn vmadc_vxm(&mut self, vd: T0, rs1: T1, vs2: T2);
}

/// RISC-V `vmadd.vv` instruction.
///
/// # Forms
/// Assembly: `vmadd.vv vm, vs2, vs1, vd`
/// Rust: `vmadd_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VmaddVvEmitter<T0, T1, T2, T3> {
    fn vmadd_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vmadd.vx` instruction.
///
/// # Forms
/// Assembly: `vmadd.vx vm, vs2, xs1, vd`
/// Rust: `vmadd_vx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VmaddVxEmitter<T0, T1, T2, T3> {
    fn vmadd_vx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vmand.mm` instruction.
///
/// # Forms
/// Assembly: `vmand.mm vs2, vs1, vd`
/// Rust: `vmand_mm(vd, vs1, vs2)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
pub trait VmandMmEmitter<T0, T1, T2> {
    fn vmand_mm(&mut self, vd: T0, vs1: T1, vs2: T2);
}

/// RISC-V `vmandn.mm` instruction.
///
/// # Forms
/// Assembly: `vmandn.mm vs2, vs1, vd`
/// Rust: `vmandn_mm(vd, vs1, vs2)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
pub trait VmandnMmEmitter<T0, T1, T2> {
    fn vmandn_mm(&mut self, vd: T0, vs1: T1, vs2: T2);
}

/// RISC-V `vmandnot.mm` instruction.
///
/// # Forms
/// Assembly: `vmandnot.mm vd vs1 vs2 vm`
/// Rust: `vmandnot_mm(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VmandnotMmEmitter<T0, T1, T2, T3> {
    fn vmandnot_mm(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vmax.vv` instruction.
///
/// # Forms
/// Assembly: `vmax.vv vm, vs2, vs1, vd`
/// Rust: `vmax_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VmaxVvEmitter<T0, T1, T2, T3> {
    fn vmax_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vmax.vx` instruction.
///
/// # Forms
/// Assembly: `vmax.vx vm, vs2, xs1, vd`
/// Rust: `vmax_vx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VmaxVxEmitter<T0, T1, T2, T3> {
    fn vmax_vx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vmaxu.vv` instruction.
///
/// # Forms
/// Assembly: `vmaxu.vv vm, vs2, vs1, vd`
/// Rust: `vmaxu_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VmaxuVvEmitter<T0, T1, T2, T3> {
    fn vmaxu_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vmaxu.vx` instruction.
///
/// # Forms
/// Assembly: `vmaxu.vx vm, vs2, xs1, vd`
/// Rust: `vmaxu_vx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VmaxuVxEmitter<T0, T1, T2, T3> {
    fn vmaxu_vx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vmerge.vim` instruction.
///
/// # Forms
/// Assembly: `vmerge.vim vs2, vd, imm`
/// Rust: `vmerge_vim(vd, vs2, simm5)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `simm5` — Immediate encoding value.
pub trait VmergeVimEmitter<T0, T1, T2> {
    fn vmerge_vim(&mut self, vd: T0, vs2: T1, simm5: T2);
}

/// RISC-V `vmerge.vvm` instruction.
///
/// # Forms
/// Assembly: `vmerge.vvm vs2, vs1, vd`
/// Rust: `vmerge_vvm(vd, vs1, vs2)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
pub trait VmergeVvmEmitter<T0, T1, T2> {
    fn vmerge_vvm(&mut self, vd: T0, vs1: T1, vs2: T2);
}

/// RISC-V `vmerge.vxm` instruction.
///
/// # Forms
/// Assembly: `vmerge.vxm vs2, xs1, vd`
/// Rust: `vmerge_vxm(vd, rs1, vs2)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `rs1` — Source register.
/// - `vs2` — Vector register operand.
pub trait VmergeVxmEmitter<T0, T1, T2> {
    fn vmerge_vxm(&mut self, vd: T0, rs1: T1, vs2: T2);
}

/// RISC-V `vmfeq.vf` instruction.
///
/// # Forms
/// Assembly: `vmfeq.vf vm, vs2, xs1, vd`
/// Rust: `vmfeq_vf(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VmfeqVfEmitter<T0, T1, T2, T3> {
    fn vmfeq_vf(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vmfeq.vv` instruction.
///
/// # Forms
/// Assembly: `vmfeq.vv vm, vs2, vs1, vd`
/// Rust: `vmfeq_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VmfeqVvEmitter<T0, T1, T2, T3> {
    fn vmfeq_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vmfge.vf` instruction.
///
/// # Forms
/// Assembly: `vmfge.vf vm, vs2, xs1, vd`
/// Rust: `vmfge_vf(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VmfgeVfEmitter<T0, T1, T2, T3> {
    fn vmfge_vf(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vmfgt.vf` instruction.
///
/// # Forms
/// Assembly: `vmfgt.vf vm, vs2, xs1, vd`
/// Rust: `vmfgt_vf(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VmfgtVfEmitter<T0, T1, T2, T3> {
    fn vmfgt_vf(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vmfle.vf` instruction.
///
/// # Forms
/// Assembly: `vmfle.vf vm, vs2, xs1, vd`
/// Rust: `vmfle_vf(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VmfleVfEmitter<T0, T1, T2, T3> {
    fn vmfle_vf(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vmfle.vv` instruction.
///
/// # Forms
/// Assembly: `vmfle.vv vm, vs2, vs1, vd`
/// Rust: `vmfle_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VmfleVvEmitter<T0, T1, T2, T3> {
    fn vmfle_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vmflt.vf` instruction.
///
/// # Forms
/// Assembly: `vmflt.vf vm, vs2, xs1, vd`
/// Rust: `vmflt_vf(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VmfltVfEmitter<T0, T1, T2, T3> {
    fn vmflt_vf(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vmflt.vv` instruction.
///
/// # Forms
/// Assembly: `vmflt.vv vm, vs2, vs1, vd`
/// Rust: `vmflt_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VmfltVvEmitter<T0, T1, T2, T3> {
    fn vmflt_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vmfne.vf` instruction.
///
/// # Forms
/// Assembly: `vmfne.vf vm, vs2, xs1, vd`
/// Rust: `vmfne_vf(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VmfneVfEmitter<T0, T1, T2, T3> {
    fn vmfne_vf(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vmfne.vv` instruction.
///
/// # Forms
/// Assembly: `vmfne.vv vm, vs2, vs1, vd`
/// Rust: `vmfne_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VmfneVvEmitter<T0, T1, T2, T3> {
    fn vmfne_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vmin.vv` instruction.
///
/// # Forms
/// Assembly: `vmin.vv vm, vs2, vs1, vd`
/// Rust: `vmin_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VminVvEmitter<T0, T1, T2, T3> {
    fn vmin_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vmin.vx` instruction.
///
/// # Forms
/// Assembly: `vmin.vx vm, vs2, xs1, vd`
/// Rust: `vmin_vx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VminVxEmitter<T0, T1, T2, T3> {
    fn vmin_vx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vminu.vv` instruction.
///
/// # Forms
/// Assembly: `vminu.vv vm, vs2, vs1, vd`
/// Rust: `vminu_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VminuVvEmitter<T0, T1, T2, T3> {
    fn vminu_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vminu.vx` instruction.
///
/// # Forms
/// Assembly: `vminu.vx vm, vs2, xs1, vd`
/// Rust: `vminu_vx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VminuVxEmitter<T0, T1, T2, T3> {
    fn vminu_vx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vmnand.mm` instruction.
///
/// # Forms
/// Assembly: `vmnand.mm vs2, vs1, vd`
/// Rust: `vmnand_mm(vd, vs1, vs2)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
pub trait VmnandMmEmitter<T0, T1, T2> {
    fn vmnand_mm(&mut self, vd: T0, vs1: T1, vs2: T2);
}

/// RISC-V `vmnor.mm` instruction.
///
/// # Forms
/// Assembly: `vmnor.mm vs2, vs1, vd`
/// Rust: `vmnor_mm(vd, vs1, vs2)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
pub trait VmnorMmEmitter<T0, T1, T2> {
    fn vmnor_mm(&mut self, vd: T0, vs1: T1, vs2: T2);
}

/// RISC-V `vmor.mm` instruction.
///
/// # Forms
/// Assembly: `vmor.mm vs2, vs1, vd`
/// Rust: `vmor_mm(vd, vs1, vs2)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
pub trait VmorMmEmitter<T0, T1, T2> {
    fn vmor_mm(&mut self, vd: T0, vs1: T1, vs2: T2);
}

/// RISC-V `vmorn.mm` instruction.
///
/// # Forms
/// Assembly: `vmorn.mm vs2, vs1, vd`
/// Rust: `vmorn_mm(vd, vs1, vs2)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
pub trait VmornMmEmitter<T0, T1, T2> {
    fn vmorn_mm(&mut self, vd: T0, vs1: T1, vs2: T2);
}

/// RISC-V `vmornot.mm` instruction.
///
/// # Forms
/// Assembly: `vmornot.mm vd vs1 vs2 vm`
/// Rust: `vmornot_mm(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VmornotMmEmitter<T0, T1, T2, T3> {
    fn vmornot_mm(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vmsbc.vv` instruction.
///
/// # Forms
/// Assembly: `vmsbc.vv vs2, vs1, vd`
/// Rust: `vmsbc_vv(vd, vs1, vs2)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
pub trait VmsbcVvEmitter<T0, T1, T2> {
    fn vmsbc_vv(&mut self, vd: T0, vs1: T1, vs2: T2);
}

/// RISC-V `vmsbc.vvm` instruction.
///
/// # Forms
/// Assembly: `vmsbc.vvm vs2, vs1, vd`
/// Rust: `vmsbc_vvm(vd, vs1, vs2)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
pub trait VmsbcVvmEmitter<T0, T1, T2> {
    fn vmsbc_vvm(&mut self, vd: T0, vs1: T1, vs2: T2);
}

/// RISC-V `vmsbc.vx` instruction.
///
/// # Forms
/// Assembly: `vmsbc.vx vs2, xs1, vd`
/// Rust: `vmsbc_vx(vd, rs1, vs2)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `rs1` — Source register.
/// - `vs2` — Vector register operand.
pub trait VmsbcVxEmitter<T0, T1, T2> {
    fn vmsbc_vx(&mut self, vd: T0, rs1: T1, vs2: T2);
}

/// RISC-V `vmsbc.vxm` instruction.
///
/// # Forms
/// Assembly: `vmsbc.vxm vs2, xs1, vd`
/// Rust: `vmsbc_vxm(vd, rs1, vs2)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `rs1` — Source register.
/// - `vs2` — Vector register operand.
pub trait VmsbcVxmEmitter<T0, T1, T2> {
    fn vmsbc_vxm(&mut self, vd: T0, rs1: T1, vs2: T2);
}

/// RISC-V `vmsbf.m` instruction.
///
/// # Forms
/// Assembly: `vmsbf.m vm, vs2, vd`
/// Rust: `vmsbf_m(vd, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VmsbfMEmitter<T0, T1, T2> {
    fn vmsbf_m(&mut self, vd: T0, vs2: T1, vm: T2);
}

/// RISC-V `vmseq.vi` instruction.
///
/// # Forms
/// Assembly: `vmseq.vi vm, vs2, vd, imm`
/// Rust: `vmseq_vi(vd, vs2, simm5, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `simm5` — Immediate encoding value.
/// - `vm` — Vector mask control.
pub trait VmseqViEmitter<T0, T1, T2, T3> {
    fn vmseq_vi(&mut self, vd: T0, vs2: T1, simm5: T2, vm: T3);
}

/// RISC-V `vmseq.vv` instruction.
///
/// # Forms
/// Assembly: `vmseq.vv vm, vs2, vs1, vd`
/// Rust: `vmseq_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VmseqVvEmitter<T0, T1, T2, T3> {
    fn vmseq_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vmseq.vx` instruction.
///
/// # Forms
/// Assembly: `vmseq.vx vm, vs2, xs1, vd`
/// Rust: `vmseq_vx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VmseqVxEmitter<T0, T1, T2, T3> {
    fn vmseq_vx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vmsgt.vi` instruction.
///
/// # Forms
/// Assembly: `vmsgt.vi vm, vs2, vd, imm`
/// Rust: `vmsgt_vi(vd, vs2, simm5, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `simm5` — Immediate encoding value.
/// - `vm` — Vector mask control.
pub trait VmsgtViEmitter<T0, T1, T2, T3> {
    fn vmsgt_vi(&mut self, vd: T0, vs2: T1, simm5: T2, vm: T3);
}

/// RISC-V `vmsgt.vx` instruction.
///
/// # Forms
/// Assembly: `vmsgt.vx vm, vs2, xs1, vd`
/// Rust: `vmsgt_vx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VmsgtVxEmitter<T0, T1, T2, T3> {
    fn vmsgt_vx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vmsgtu.vi` instruction.
///
/// # Forms
/// Assembly: `vmsgtu.vi vm, vs2, vd, imm`
/// Rust: `vmsgtu_vi(vd, vs2, simm5, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `simm5` — Immediate encoding value.
/// - `vm` — Vector mask control.
pub trait VmsgtuViEmitter<T0, T1, T2, T3> {
    fn vmsgtu_vi(&mut self, vd: T0, vs2: T1, simm5: T2, vm: T3);
}

/// RISC-V `vmsgtu.vx` instruction.
///
/// # Forms
/// Assembly: `vmsgtu.vx vm, vs2, xs1, vd`
/// Rust: `vmsgtu_vx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VmsgtuVxEmitter<T0, T1, T2, T3> {
    fn vmsgtu_vx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vmsif.m` instruction.
///
/// # Forms
/// Assembly: `vmsif.m vm, vs2, vd`
/// Rust: `vmsif_m(vd, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VmsifMEmitter<T0, T1, T2> {
    fn vmsif_m(&mut self, vd: T0, vs2: T1, vm: T2);
}

/// RISC-V `vmsle.vi` instruction.
///
/// # Forms
/// Assembly: `vmsle.vi vm, vs2, vd, imm`
/// Rust: `vmsle_vi(vd, vs2, simm5, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `simm5` — Immediate encoding value.
/// - `vm` — Vector mask control.
pub trait VmsleViEmitter<T0, T1, T2, T3> {
    fn vmsle_vi(&mut self, vd: T0, vs2: T1, simm5: T2, vm: T3);
}

/// RISC-V `vmsle.vv` instruction.
///
/// # Forms
/// Assembly: `vmsle.vv vm, vs2, vs1, vd`
/// Rust: `vmsle_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VmsleVvEmitter<T0, T1, T2, T3> {
    fn vmsle_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vmsle.vx` instruction.
///
/// # Forms
/// Assembly: `vmsle.vx vm, vs2, xs1, vd`
/// Rust: `vmsle_vx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VmsleVxEmitter<T0, T1, T2, T3> {
    fn vmsle_vx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vmsleu.vi` instruction.
///
/// # Forms
/// Assembly: `vmsleu.vi vm, vs2, vd, imm`
/// Rust: `vmsleu_vi(vd, vs2, simm5, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `simm5` — Immediate encoding value.
/// - `vm` — Vector mask control.
pub trait VmsleuViEmitter<T0, T1, T2, T3> {
    fn vmsleu_vi(&mut self, vd: T0, vs2: T1, simm5: T2, vm: T3);
}

/// RISC-V `vmsleu.vv` instruction.
///
/// # Forms
/// Assembly: `vmsleu.vv vm, vs2, vs1, vd`
/// Rust: `vmsleu_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VmsleuVvEmitter<T0, T1, T2, T3> {
    fn vmsleu_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vmsleu.vx` instruction.
///
/// # Forms
/// Assembly: `vmsleu.vx vm, vs2, xs1, vd`
/// Rust: `vmsleu_vx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VmsleuVxEmitter<T0, T1, T2, T3> {
    fn vmsleu_vx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vmslt.vv` instruction.
///
/// # Forms
/// Assembly: `vmslt.vv vm, vs2, vs1, vd`
/// Rust: `vmslt_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VmsltVvEmitter<T0, T1, T2, T3> {
    fn vmslt_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vmslt.vx` instruction.
///
/// # Forms
/// Assembly: `vmslt.vx vm, vs2, xs1, vd`
/// Rust: `vmslt_vx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VmsltVxEmitter<T0, T1, T2, T3> {
    fn vmslt_vx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vmsltu.vv` instruction.
///
/// # Forms
/// Assembly: `vmsltu.vv vm, vs2, vs1, vd`
/// Rust: `vmsltu_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VmsltuVvEmitter<T0, T1, T2, T3> {
    fn vmsltu_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vmsltu.vx` instruction.
///
/// # Forms
/// Assembly: `vmsltu.vx vm, vs2, xs1, vd`
/// Rust: `vmsltu_vx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VmsltuVxEmitter<T0, T1, T2, T3> {
    fn vmsltu_vx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vmsne.vi` instruction.
///
/// # Forms
/// Assembly: `vmsne.vi vm, vs2, vd, imm`
/// Rust: `vmsne_vi(vd, vs2, simm5, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `simm5` — Immediate encoding value.
/// - `vm` — Vector mask control.
pub trait VmsneViEmitter<T0, T1, T2, T3> {
    fn vmsne_vi(&mut self, vd: T0, vs2: T1, simm5: T2, vm: T3);
}

/// RISC-V `vmsne.vv` instruction.
///
/// # Forms
/// Assembly: `vmsne.vv vm, vs2, vs1, vd`
/// Rust: `vmsne_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VmsneVvEmitter<T0, T1, T2, T3> {
    fn vmsne_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vmsne.vx` instruction.
///
/// # Forms
/// Assembly: `vmsne.vx vm, vs2, xs1, vd`
/// Rust: `vmsne_vx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VmsneVxEmitter<T0, T1, T2, T3> {
    fn vmsne_vx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vmsof.m` instruction.
///
/// # Forms
/// Assembly: `vmsof.m vm, vs2, vd`
/// Rust: `vmsof_m(vd, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VmsofMEmitter<T0, T1, T2> {
    fn vmsof_m(&mut self, vd: T0, vs2: T1, vm: T2);
}

/// RISC-V `vmul.vv` instruction.
///
/// # Forms
/// Assembly: `vmul.vv vm, vs2, vs1, vd`
/// Rust: `vmul_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VmulVvEmitter<T0, T1, T2, T3> {
    fn vmul_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vmul.vx` instruction.
///
/// # Forms
/// Assembly: `vmul.vx vm, vs2, xs1, vd`
/// Rust: `vmul_vx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VmulVxEmitter<T0, T1, T2, T3> {
    fn vmul_vx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vmulh.vv` instruction.
///
/// # Forms
/// Assembly: `vmulh.vv vm, vs2, vs1, vd`
/// Rust: `vmulh_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VmulhVvEmitter<T0, T1, T2, T3> {
    fn vmulh_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vmulh.vx` instruction.
///
/// # Forms
/// Assembly: `vmulh.vx vm, vs2, xs1, vd`
/// Rust: `vmulh_vx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VmulhVxEmitter<T0, T1, T2, T3> {
    fn vmulh_vx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vmulhsu.vv` instruction.
///
/// # Forms
/// Assembly: `vmulhsu.vv vm, vs2, vs1, vd`
/// Rust: `vmulhsu_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VmulhsuVvEmitter<T0, T1, T2, T3> {
    fn vmulhsu_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vmulhsu.vx` instruction.
///
/// # Forms
/// Assembly: `vmulhsu.vx vm, vs2, xs1, vd`
/// Rust: `vmulhsu_vx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VmulhsuVxEmitter<T0, T1, T2, T3> {
    fn vmulhsu_vx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vmulhu.vv` instruction.
///
/// # Forms
/// Assembly: `vmulhu.vv vm, vs2, vs1, vd`
/// Rust: `vmulhu_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VmulhuVvEmitter<T0, T1, T2, T3> {
    fn vmulhu_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vmulhu.vx` instruction.
///
/// # Forms
/// Assembly: `vmulhu.vx vm, vs2, xs1, vd`
/// Rust: `vmulhu_vx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VmulhuVxEmitter<T0, T1, T2, T3> {
    fn vmulhu_vx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vmv1r.v` instruction.
///
/// # Forms
/// Assembly: `vmv1r.v vs2, vd`
/// Rust: `vmv1r_v(vd, vs2)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
pub trait Vmv1RVEmitter<T0, T1> {
    fn vmv1r_v(&mut self, vd: T0, vs2: T1);
}

/// RISC-V `vmv2r.v` instruction.
///
/// # Forms
/// Assembly: `vmv2r.v vs2, vd`
/// Rust: `vmv2r_v(vd, vs2)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
pub trait Vmv2RVEmitter<T0, T1> {
    fn vmv2r_v(&mut self, vd: T0, vs2: T1);
}

/// RISC-V `vmv4r.v` instruction.
///
/// # Forms
/// Assembly: `vmv4r.v vs2, vd`
/// Rust: `vmv4r_v(vd, vs2)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
pub trait Vmv4RVEmitter<T0, T1> {
    fn vmv4r_v(&mut self, vd: T0, vs2: T1);
}

/// RISC-V `vmv8r.v` instruction.
///
/// # Forms
/// Assembly: `vmv8r.v vs2, vd`
/// Rust: `vmv8r_v(vd, vs2)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
pub trait Vmv8RVEmitter<T0, T1> {
    fn vmv8r_v(&mut self, vd: T0, vs2: T1);
}

/// RISC-V `vmv.s.x` instruction.
///
/// # Forms
/// Assembly: `vmv.s.x xs1, vd`
/// Rust: `vmv_s_x(vd, rs1)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `rs1` — Source register.
pub trait VmvSXEmitter<T0, T1> {
    fn vmv_s_x(&mut self, vd: T0, rs1: T1);
}

/// RISC-V `vmv.v.i` instruction.
///
/// # Forms
/// Assembly: `vmv.v.i vd, imm`
/// Rust: `vmv_v_i(vd, simm5)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `simm5` — Immediate encoding value.
pub trait VmvVIEmitter<T0, T1> {
    fn vmv_v_i(&mut self, vd: T0, simm5: T1);
}

/// RISC-V `vmv.v.v` instruction.
///
/// # Forms
/// Assembly: `vmv.v.v vs1, vd`
/// Rust: `vmv_v_v(vd, vs1)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
pub trait VmvVVEmitter<T0, T1> {
    fn vmv_v_v(&mut self, vd: T0, vs1: T1);
}

/// RISC-V `vmv.v.x` instruction.
///
/// # Forms
/// Assembly: `vmv.v.x xs1, vd`
/// Rust: `vmv_v_x(vd, rs1)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `rs1` — Source register.
pub trait VmvVXEmitter<T0, T1> {
    fn vmv_v_x(&mut self, vd: T0, rs1: T1);
}

/// RISC-V `vmv.x.s` instruction.
///
/// # Forms
/// Assembly: `vmv.x.s vs2, xd`
/// Rust: `vmv_x_s(rd, vs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `vs2` — Vector register operand.
pub trait VmvXSEmitter<T0, T1> {
    fn vmv_x_s(&mut self, rd: T0, vs2: T1);
}

/// RISC-V `vmxnor.mm` instruction.
///
/// # Forms
/// Assembly: `vmxnor.mm vs2, vs1, vd`
/// Rust: `vmxnor_mm(vd, vs1, vs2)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
pub trait VmxnorMmEmitter<T0, T1, T2> {
    fn vmxnor_mm(&mut self, vd: T0, vs1: T1, vs2: T2);
}

/// RISC-V `vmxor.mm` instruction.
///
/// # Forms
/// Assembly: `vmxor.mm vs2, vs1, vd`
/// Rust: `vmxor_mm(vd, vs1, vs2)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
pub trait VmxorMmEmitter<T0, T1, T2> {
    fn vmxor_mm(&mut self, vd: T0, vs1: T1, vs2: T2);
}

/// RISC-V `vnclip.wi` instruction.
///
/// # Forms
/// Assembly: `vnclip.wi vm, vs2, vd, imm`
/// Rust: `vnclip_wi(vd, vs2, zimm5, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `zimm5` — Immediate encoding value.
/// - `vm` — Vector mask control.
pub trait VnclipWiEmitter<T0, T1, T2, T3> {
    fn vnclip_wi(&mut self, vd: T0, vs2: T1, zimm5: T2, vm: T3);
}

/// RISC-V `vnclip.wv` instruction.
///
/// # Forms
/// Assembly: `vnclip.wv vm, vs2, vs1, vd`
/// Rust: `vnclip_wv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VnclipWvEmitter<T0, T1, T2, T3> {
    fn vnclip_wv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vnclip.wx` instruction.
///
/// # Forms
/// Assembly: `vnclip.wx vm, vs2, xs1, vd`
/// Rust: `vnclip_wx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VnclipWxEmitter<T0, T1, T2, T3> {
    fn vnclip_wx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vnclipu.wi` instruction.
///
/// # Forms
/// Assembly: `vnclipu.wi vm, vs2, vd, imm`
/// Rust: `vnclipu_wi(vd, vs2, zimm5, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `zimm5` — Immediate encoding value.
/// - `vm` — Vector mask control.
pub trait VnclipuWiEmitter<T0, T1, T2, T3> {
    fn vnclipu_wi(&mut self, vd: T0, vs2: T1, zimm5: T2, vm: T3);
}

/// RISC-V `vnclipu.wv` instruction.
///
/// # Forms
/// Assembly: `vnclipu.wv vm, vs2, vs1, vd`
/// Rust: `vnclipu_wv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VnclipuWvEmitter<T0, T1, T2, T3> {
    fn vnclipu_wv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vnclipu.wx` instruction.
///
/// # Forms
/// Assembly: `vnclipu.wx vm, vs2, xs1, vd`
/// Rust: `vnclipu_wx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VnclipuWxEmitter<T0, T1, T2, T3> {
    fn vnclipu_wx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vnmsac.vv` instruction.
///
/// # Forms
/// Assembly: `vnmsac.vv vm, vs2, vs1, vd`
/// Rust: `vnmsac_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VnmsacVvEmitter<T0, T1, T2, T3> {
    fn vnmsac_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vnmsac.vx` instruction.
///
/// # Forms
/// Assembly: `vnmsac.vx vm, vs2, xs1, vd`
/// Rust: `vnmsac_vx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VnmsacVxEmitter<T0, T1, T2, T3> {
    fn vnmsac_vx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vnmsub.vv` instruction.
///
/// # Forms
/// Assembly: `vnmsub.vv vm, vs2, vs1, vd`
/// Rust: `vnmsub_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VnmsubVvEmitter<T0, T1, T2, T3> {
    fn vnmsub_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vnmsub.vx` instruction.
///
/// # Forms
/// Assembly: `vnmsub.vx vm, vs2, xs1, vd`
/// Rust: `vnmsub_vx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VnmsubVxEmitter<T0, T1, T2, T3> {
    fn vnmsub_vx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vnsra.wi` instruction.
///
/// # Forms
/// Assembly: `vnsra.wi vm, vs2, vd, imm`
/// Rust: `vnsra_wi(vd, vs2, zimm5, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `zimm5` — Immediate encoding value.
/// - `vm` — Vector mask control.
pub trait VnsraWiEmitter<T0, T1, T2, T3> {
    fn vnsra_wi(&mut self, vd: T0, vs2: T1, zimm5: T2, vm: T3);
}

/// RISC-V `vnsra.wv` instruction.
///
/// # Forms
/// Assembly: `vnsra.wv vm, vs2, vs1, vd`
/// Rust: `vnsra_wv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VnsraWvEmitter<T0, T1, T2, T3> {
    fn vnsra_wv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vnsra.wx` instruction.
///
/// # Forms
/// Assembly: `vnsra.wx vm, vs2, xs1, vd`
/// Rust: `vnsra_wx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VnsraWxEmitter<T0, T1, T2, T3> {
    fn vnsra_wx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vnsrl.wi` instruction.
///
/// # Forms
/// Assembly: `vnsrl.wi vm, vs2, vd, imm`
/// Rust: `vnsrl_wi(vd, vs2, zimm5, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `zimm5` — Immediate encoding value.
/// - `vm` — Vector mask control.
pub trait VnsrlWiEmitter<T0, T1, T2, T3> {
    fn vnsrl_wi(&mut self, vd: T0, vs2: T1, zimm5: T2, vm: T3);
}

/// RISC-V `vnsrl.wv` instruction.
///
/// # Forms
/// Assembly: `vnsrl.wv vm, vs2, vs1, vd`
/// Rust: `vnsrl_wv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VnsrlWvEmitter<T0, T1, T2, T3> {
    fn vnsrl_wv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vnsrl.wx` instruction.
///
/// # Forms
/// Assembly: `vnsrl.wx vm, vs2, xs1, vd`
/// Rust: `vnsrl_wx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VnsrlWxEmitter<T0, T1, T2, T3> {
    fn vnsrl_wx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vor.vi` instruction.
///
/// # Forms
/// Assembly: `vor.vi vm, vs2, vd, imm`
/// Rust: `vor_vi(vd, vs2, simm5, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `simm5` — Immediate encoding value.
/// - `vm` — Vector mask control.
pub trait VorViEmitter<T0, T1, T2, T3> {
    fn vor_vi(&mut self, vd: T0, vs2: T1, simm5: T2, vm: T3);
}

/// RISC-V `vor.vv` instruction.
///
/// # Forms
/// Assembly: `vor.vv vm, vs2, vs1, vd`
/// Rust: `vor_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VorVvEmitter<T0, T1, T2, T3> {
    fn vor_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vor.vx` instruction.
///
/// # Forms
/// Assembly: `vor.vx vm, vs2, xs1, vd`
/// Rust: `vor_vx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VorVxEmitter<T0, T1, T2, T3> {
    fn vor_vx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vpopc.m` instruction.
///
/// # Forms
/// Assembly: `vpopc.m rd vs2 vm`
/// Rust: `vpopc_m(rd, vs2, vm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VpopcMEmitter<T0, T1, T2> {
    fn vpopc_m(&mut self, rd: T0, vs2: T1, vm: T2);
}

/// RISC-V `vredand.vs` instruction.
///
/// # Forms
/// Assembly: `vredand.vs vm, vs2, vs1, vd`
/// Rust: `vredand_vs(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VredandVsEmitter<T0, T1, T2, T3> {
    fn vredand_vs(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vredmax.vs` instruction.
///
/// # Forms
/// Assembly: `vredmax.vs vm, vs2, vs1, vd`
/// Rust: `vredmax_vs(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VredmaxVsEmitter<T0, T1, T2, T3> {
    fn vredmax_vs(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vredmaxu.vs` instruction.
///
/// # Forms
/// Assembly: `vredmaxu.vs vm, vs2, vs1, vd`
/// Rust: `vredmaxu_vs(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VredmaxuVsEmitter<T0, T1, T2, T3> {
    fn vredmaxu_vs(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vredmin.vs` instruction.
///
/// # Forms
/// Assembly: `vredmin.vs vm, vs2, vs1, vd`
/// Rust: `vredmin_vs(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VredminVsEmitter<T0, T1, T2, T3> {
    fn vredmin_vs(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vredminu.vs` instruction.
///
/// # Forms
/// Assembly: `vredminu.vs vm, vs2, vs1, vd`
/// Rust: `vredminu_vs(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VredminuVsEmitter<T0, T1, T2, T3> {
    fn vredminu_vs(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vredor.vs` instruction.
///
/// # Forms
/// Assembly: `vredor.vs vm, vs2, vs1, vd`
/// Rust: `vredor_vs(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VredorVsEmitter<T0, T1, T2, T3> {
    fn vredor_vs(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vredsum.vs` instruction.
///
/// # Forms
/// Assembly: `vredsum.vs vm, vs2, vs1, vd`
/// Rust: `vredsum_vs(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VredsumVsEmitter<T0, T1, T2, T3> {
    fn vredsum_vs(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vredxor.vs` instruction.
///
/// # Forms
/// Assembly: `vredxor.vs vm, vs2, vs1, vd`
/// Rust: `vredxor_vs(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VredxorVsEmitter<T0, T1, T2, T3> {
    fn vredxor_vs(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vrem.vv` instruction.
///
/// # Forms
/// Assembly: `vrem.vv vm, vs2, vs1, vd`
/// Rust: `vrem_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VremVvEmitter<T0, T1, T2, T3> {
    fn vrem_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vrem.vx` instruction.
///
/// # Forms
/// Assembly: `vrem.vx vm, vs2, xs1, vd`
/// Rust: `vrem_vx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VremVxEmitter<T0, T1, T2, T3> {
    fn vrem_vx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vremu.vv` instruction.
///
/// # Forms
/// Assembly: `vremu.vv vm, vs2, vs1, vd`
/// Rust: `vremu_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VremuVvEmitter<T0, T1, T2, T3> {
    fn vremu_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vremu.vx` instruction.
///
/// # Forms
/// Assembly: `vremu.vx vm, vs2, xs1, vd`
/// Rust: `vremu_vx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VremuVxEmitter<T0, T1, T2, T3> {
    fn vremu_vx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vrev8.v` instruction.
///
/// # Forms
/// Assembly: `vrev8.v vm, vs2, vd`
/// Rust: `vrev8_v(vd, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait Vrev8VEmitter<T0, T1, T2> {
    fn vrev8_v(&mut self, vd: T0, vs2: T1, vm: T2);
}

/// RISC-V `vrgather.vi` instruction.
///
/// # Forms
/// Assembly: `vrgather.vi vm, vs2, vd, imm`
/// Rust: `vrgather_vi(vd, vs2, zimm5, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `zimm5` — Immediate encoding value.
/// - `vm` — Vector mask control.
pub trait VrgatherViEmitter<T0, T1, T2, T3> {
    fn vrgather_vi(&mut self, vd: T0, vs2: T1, zimm5: T2, vm: T3);
}

/// RISC-V `vrgather.vv` instruction.
///
/// # Forms
/// Assembly: `vrgather.vv vm, vs2, vs1, vd`
/// Rust: `vrgather_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VrgatherVvEmitter<T0, T1, T2, T3> {
    fn vrgather_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vrgather.vx` instruction.
///
/// # Forms
/// Assembly: `vrgather.vx vm, vs2, xs1, vd`
/// Rust: `vrgather_vx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VrgatherVxEmitter<T0, T1, T2, T3> {
    fn vrgather_vx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vrgatherei16.vv` instruction.
///
/// # Forms
/// Assembly: `vrgatherei16.vv vm, vs2, vs1, vd`
/// Rust: `vrgatherei16_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait Vrgatherei16VvEmitter<T0, T1, T2, T3> {
    fn vrgatherei16_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vrol.vv` instruction.
///
/// # Forms
/// Assembly: `vrol.vv vm, vs2, vs1, vd`
/// Rust: `vrol_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VrolVvEmitter<T0, T1, T2, T3> {
    fn vrol_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vrol.vx` instruction.
///
/// # Forms
/// Assembly: `vrol.vx vm, vs2, xs1, vd`
/// Rust: `vrol_vx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VrolVxEmitter<T0, T1, T2, T3> {
    fn vrol_vx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vror.vi` instruction.
///
/// # Forms
/// Assembly: `vror.vi vm, vs2, vd, imm`
/// Rust: `vror_vi(vd, vs2, zimm6lohi, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `zimm6lohi` — Immediate encoding value.
/// - `vm` — Vector mask control.
pub trait VrorViEmitter<T0, T1, T2, T3> {
    fn vror_vi(&mut self, vd: T0, vs2: T1, zimm6lohi: T2, vm: T3);
}

/// RISC-V `vror.vv` instruction.
///
/// # Forms
/// Assembly: `vror.vv vm, vs2, vs1, vd`
/// Rust: `vror_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VrorVvEmitter<T0, T1, T2, T3> {
    fn vror_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vror.vx` instruction.
///
/// # Forms
/// Assembly: `vror.vx vm, vs2, xs1, vd`
/// Rust: `vror_vx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VrorVxEmitter<T0, T1, T2, T3> {
    fn vror_vx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vrsub.vi` instruction.
///
/// # Forms
/// Assembly: `vrsub.vi vm, vs2, vd, imm`
/// Rust: `vrsub_vi(vd, vs2, simm5, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `simm5` — Immediate encoding value.
/// - `vm` — Vector mask control.
pub trait VrsubViEmitter<T0, T1, T2, T3> {
    fn vrsub_vi(&mut self, vd: T0, vs2: T1, simm5: T2, vm: T3);
}

/// RISC-V `vrsub.vx` instruction.
///
/// # Forms
/// Assembly: `vrsub.vx vm, vs2, xs1, vd`
/// Rust: `vrsub_vx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VrsubVxEmitter<T0, T1, T2, T3> {
    fn vrsub_vx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vs1r.v` instruction.
///
/// # Forms
/// Assembly: `vs1r.v xs1, vs3`
/// Rust: `vs1r_v(vs3, rs1)`
///
/// # Arguments
/// - `vs3` — Vector register operand.
/// - `rs1` — Memory base register.
pub trait Vs1RVEmitter<T0, T1> {
    fn vs1r_v(&mut self, vs3: T0, rs1: T1);
}

/// RISC-V `vs2r.v` instruction.
///
/// # Forms
/// Assembly: `vs2r.v xs1, vs3`
/// Rust: `vs2r_v(vs3, rs1)`
///
/// # Arguments
/// - `vs3` — Vector register operand.
/// - `rs1` — Memory base register.
pub trait Vs2RVEmitter<T0, T1> {
    fn vs2r_v(&mut self, vs3: T0, rs1: T1);
}

/// RISC-V `vs4r.v` instruction.
///
/// # Forms
/// Assembly: `vs4r.v xs1, vs3`
/// Rust: `vs4r_v(vs3, rs1)`
///
/// # Arguments
/// - `vs3` — Vector register operand.
/// - `rs1` — Memory base register.
pub trait Vs4RVEmitter<T0, T1> {
    fn vs4r_v(&mut self, vs3: T0, rs1: T1);
}

/// RISC-V `vs8r.v` instruction.
///
/// # Forms
/// Assembly: `vs8r.v xs1, vs3`
/// Rust: `vs8r_v(vs3, rs1)`
///
/// # Arguments
/// - `vs3` — Vector register operand.
/// - `rs1` — Memory base register.
pub trait Vs8RVEmitter<T0, T1> {
    fn vs8r_v(&mut self, vs3: T0, rs1: T1);
}

/// RISC-V `vsadd.vi` instruction.
///
/// # Forms
/// Assembly: `vsadd.vi vm, vs2, vd, imm`
/// Rust: `vsadd_vi(vd, vs2, simm5, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `simm5` — Immediate encoding value.
/// - `vm` — Vector mask control.
pub trait VsaddViEmitter<T0, T1, T2, T3> {
    fn vsadd_vi(&mut self, vd: T0, vs2: T1, simm5: T2, vm: T3);
}

/// RISC-V `vsadd.vv` instruction.
///
/// # Forms
/// Assembly: `vsadd.vv vm, vs2, vs1, vd`
/// Rust: `vsadd_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VsaddVvEmitter<T0, T1, T2, T3> {
    fn vsadd_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vsadd.vx` instruction.
///
/// # Forms
/// Assembly: `vsadd.vx vm, vs2, xs1, vd`
/// Rust: `vsadd_vx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VsaddVxEmitter<T0, T1, T2, T3> {
    fn vsadd_vx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vsaddu.vi` instruction.
///
/// # Forms
/// Assembly: `vsaddu.vi vm, vs2, vd, imm`
/// Rust: `vsaddu_vi(vd, vs2, simm5, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `simm5` — Immediate encoding value.
/// - `vm` — Vector mask control.
pub trait VsadduViEmitter<T0, T1, T2, T3> {
    fn vsaddu_vi(&mut self, vd: T0, vs2: T1, simm5: T2, vm: T3);
}

/// RISC-V `vsaddu.vv` instruction.
///
/// # Forms
/// Assembly: `vsaddu.vv vm, vs2, vs1, vd`
/// Rust: `vsaddu_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VsadduVvEmitter<T0, T1, T2, T3> {
    fn vsaddu_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vsaddu.vx` instruction.
///
/// # Forms
/// Assembly: `vsaddu.vx vm, vs2, xs1, vd`
/// Rust: `vsaddu_vx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VsadduVxEmitter<T0, T1, T2, T3> {
    fn vsaddu_vx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vsbc.vvm` instruction.
///
/// # Forms
/// Assembly: `vsbc.vvm vs2, vs1, vd`
/// Rust: `vsbc_vvm(vd, vs1, vs2)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
pub trait VsbcVvmEmitter<T0, T1, T2> {
    fn vsbc_vvm(&mut self, vd: T0, vs1: T1, vs2: T2);
}

/// RISC-V `vsbc.vxm` instruction.
///
/// # Forms
/// Assembly: `vsbc.vxm vs2, xs1, vd`
/// Rust: `vsbc_vxm(vd, rs1, vs2)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `rs1` — Source register.
/// - `vs2` — Vector register operand.
pub trait VsbcVxmEmitter<T0, T1, T2> {
    fn vsbc_vxm(&mut self, vd: T0, rs1: T1, vs2: T2);
}

/// RISC-V `vse16.v` instruction.
///
/// # Forms
/// Assembly: `vse16.v vm, xs1, vs3`
/// Rust: `vse16_v(vs3, rs1, vm, nf)`
///
/// # Arguments
/// - `vs3` — Vector register operand.
/// - `rs1` — Memory base register.
/// - `vm` — Vector mask control.
/// - `nf` — Vector segment field count.
pub trait Vse16VEmitter<T0, T1, T2, T3> {
    fn vse16_v(&mut self, vs3: T0, rs1: T1, vm: T2, nf: T3);
}

/// RISC-V `vse1.v` instruction.
///
/// # Forms
/// Assembly: `vse1.v vs3 rs1`
/// Rust: `vse1_v(vs3, rs1)`
///
/// # Arguments
/// - `vs3` — Vector register operand.
/// - `rs1` — Memory base register.
pub trait Vse1VEmitter<T0, T1> {
    fn vse1_v(&mut self, vs3: T0, rs1: T1);
}

/// RISC-V `vse32.v` instruction.
///
/// # Forms
/// Assembly: `vse32.v vm, xs1, vs3`
/// Rust: `vse32_v(vs3, rs1, vm, nf)`
///
/// # Arguments
/// - `vs3` — Vector register operand.
/// - `rs1` — Memory base register.
/// - `vm` — Vector mask control.
/// - `nf` — Vector segment field count.
pub trait Vse32VEmitter<T0, T1, T2, T3> {
    fn vse32_v(&mut self, vs3: T0, rs1: T1, vm: T2, nf: T3);
}

/// RISC-V `vse64.v` instruction.
///
/// # Forms
/// Assembly: `vse64.v vm, xs1, vs3`
/// Rust: `vse64_v(vs3, rs1, vm, nf)`
///
/// # Arguments
/// - `vs3` — Vector register operand.
/// - `rs1` — Memory base register.
/// - `vm` — Vector mask control.
/// - `nf` — Vector segment field count.
pub trait Vse64VEmitter<T0, T1, T2, T3> {
    fn vse64_v(&mut self, vs3: T0, rs1: T1, vm: T2, nf: T3);
}

/// RISC-V `vse8.v` instruction.
///
/// # Forms
/// Assembly: `vse8.v vm, xs1, vs3`
/// Rust: `vse8_v(vs3, rs1, vm, nf)`
///
/// # Arguments
/// - `vs3` — Vector register operand.
/// - `rs1` — Memory base register.
/// - `vm` — Vector mask control.
/// - `nf` — Vector segment field count.
pub trait Vse8VEmitter<T0, T1, T2, T3> {
    fn vse8_v(&mut self, vs3: T0, rs1: T1, vm: T2, nf: T3);
}

/// RISC-V `vsetivli` instruction.
///
/// # Forms
/// Assembly: `vsetivli xd, imm`
/// Rust: `vsetivli(rd, zimm5, zimm10)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `zimm5` — Immediate encoding value.
/// - `zimm10` — Immediate encoding value.
pub trait VsetivliEmitter<T0, T1, T2> {
    fn vsetivli(&mut self, rd: T0, zimm5: T1, zimm10: T2);
}

/// RISC-V `vsetvl` instruction.
///
/// # Forms
/// Assembly: `vsetvl xs2, xs1, xd`
/// Rust: `vsetvl(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait VsetvlEmitter<T0, T1, T2> {
    fn vsetvl(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `vsetvli` instruction.
///
/// # Forms
/// Assembly: `vsetvli xs1, xd, imm`
/// Rust: `vsetvli(rd, rs1, zimm11)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `zimm11` — Immediate encoding value.
pub trait VsetvliEmitter<T0, T1, T2> {
    fn vsetvli(&mut self, rd: T0, rs1: T1, zimm11: T2);
}

/// RISC-V `vsext.vf2` instruction.
///
/// # Forms
/// Assembly: `vsext.vf2 vm, vs2, vd`
/// Rust: `vsext_vf2(vd, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VsextVf2Emitter<T0, T1, T2> {
    fn vsext_vf2(&mut self, vd: T0, vs2: T1, vm: T2);
}

/// RISC-V `vsext.vf4` instruction.
///
/// # Forms
/// Assembly: `vsext.vf4 vm, vs2, vd`
/// Rust: `vsext_vf4(vd, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VsextVf4Emitter<T0, T1, T2> {
    fn vsext_vf4(&mut self, vd: T0, vs2: T1, vm: T2);
}

/// RISC-V `vsext.vf8` instruction.
///
/// # Forms
/// Assembly: `vsext.vf8 vm, vs2, vd`
/// Rust: `vsext_vf8(vd, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VsextVf8Emitter<T0, T1, T2> {
    fn vsext_vf8(&mut self, vd: T0, vs2: T1, vm: T2);
}

/// RISC-V `vsha2ch.vv` instruction.
///
/// # Forms
/// Assembly: `vsha2ch.vv vs2, vs1, vd`
/// Rust: `vsha2ch_vv(vd, vs1, vs2)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
pub trait Vsha2ChVvEmitter<T0, T1, T2> {
    fn vsha2ch_vv(&mut self, vd: T0, vs1: T1, vs2: T2);
}

/// RISC-V `vsha2cl.vv` instruction.
///
/// # Forms
/// Assembly: `vsha2cl.vv vs2, vs1, vd`
/// Rust: `vsha2cl_vv(vd, vs1, vs2)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
pub trait Vsha2ClVvEmitter<T0, T1, T2> {
    fn vsha2cl_vv(&mut self, vd: T0, vs1: T1, vs2: T2);
}

/// RISC-V `vsha2ms.vv` instruction.
///
/// # Forms
/// Assembly: `vsha2ms.vv vs2, vs1, vd`
/// Rust: `vsha2ms_vv(vd, vs1, vs2)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
pub trait Vsha2MsVvEmitter<T0, T1, T2> {
    fn vsha2ms_vv(&mut self, vd: T0, vs1: T1, vs2: T2);
}

/// RISC-V `vslide1down.vx` instruction.
///
/// # Forms
/// Assembly: `vslide1down.vx vm, vs2, xs1, vd`
/// Rust: `vslide1down_vx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait Vslide1DownVxEmitter<T0, T1, T2, T3> {
    fn vslide1down_vx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vslide1up.vx` instruction.
///
/// # Forms
/// Assembly: `vslide1up.vx vm, vs2, xs1, vd`
/// Rust: `vslide1up_vx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait Vslide1UpVxEmitter<T0, T1, T2, T3> {
    fn vslide1up_vx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vslidedown.vi` instruction.
///
/// # Forms
/// Assembly: `vslidedown.vi vm, vs2, vd, imm`
/// Rust: `vslidedown_vi(vd, vs2, zimm5, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `zimm5` — Immediate encoding value.
/// - `vm` — Vector mask control.
pub trait VslidedownViEmitter<T0, T1, T2, T3> {
    fn vslidedown_vi(&mut self, vd: T0, vs2: T1, zimm5: T2, vm: T3);
}

/// RISC-V `vslidedown.vx` instruction.
///
/// # Forms
/// Assembly: `vslidedown.vx vm, vs2, xs1, vd`
/// Rust: `vslidedown_vx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VslidedownVxEmitter<T0, T1, T2, T3> {
    fn vslidedown_vx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vslideup.vi` instruction.
///
/// # Forms
/// Assembly: `vslideup.vi vm, vs2, vd, imm`
/// Rust: `vslideup_vi(vd, vs2, zimm5, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `zimm5` — Immediate encoding value.
/// - `vm` — Vector mask control.
pub trait VslideupViEmitter<T0, T1, T2, T3> {
    fn vslideup_vi(&mut self, vd: T0, vs2: T1, zimm5: T2, vm: T3);
}

/// RISC-V `vslideup.vx` instruction.
///
/// # Forms
/// Assembly: `vslideup.vx vm, vs2, xs1, vd`
/// Rust: `vslideup_vx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VslideupVxEmitter<T0, T1, T2, T3> {
    fn vslideup_vx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vsll.vi` instruction.
///
/// # Forms
/// Assembly: `vsll.vi vm, vs2, vd, imm`
/// Rust: `vsll_vi(vd, vs2, zimm5, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `zimm5` — Immediate encoding value.
/// - `vm` — Vector mask control.
pub trait VsllViEmitter<T0, T1, T2, T3> {
    fn vsll_vi(&mut self, vd: T0, vs2: T1, zimm5: T2, vm: T3);
}

/// RISC-V `vsll.vv` instruction.
///
/// # Forms
/// Assembly: `vsll.vv vm, vs2, vs1, vd`
/// Rust: `vsll_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VsllVvEmitter<T0, T1, T2, T3> {
    fn vsll_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vsll.vx` instruction.
///
/// # Forms
/// Assembly: `vsll.vx vm, vs2, xs1, vd`
/// Rust: `vsll_vx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VsllVxEmitter<T0, T1, T2, T3> {
    fn vsll_vx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vsm3c.vi` instruction.
///
/// # Forms
/// Assembly: `vsm3c.vi vs2, vd, imm`
/// Rust: `vsm3c_vi(vd, vs2, zimm5)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `zimm5` — Immediate encoding value.
pub trait Vsm3CViEmitter<T0, T1, T2> {
    fn vsm3c_vi(&mut self, vd: T0, vs2: T1, zimm5: T2);
}

/// RISC-V `vsm3me.vv` instruction.
///
/// # Forms
/// Assembly: `vsm3me.vv vs2, vs1, vd`
/// Rust: `vsm3me_vv(vd, vs1, vs2)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
pub trait Vsm3MeVvEmitter<T0, T1, T2> {
    fn vsm3me_vv(&mut self, vd: T0, vs1: T1, vs2: T2);
}

/// RISC-V `vsm4k.vi` instruction.
///
/// # Forms
/// Assembly: `vsm4k.vi vs2, vd, imm`
/// Rust: `vsm4k_vi(vd, vs2, zimm5)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `zimm5` — Immediate encoding value.
pub trait Vsm4KViEmitter<T0, T1, T2> {
    fn vsm4k_vi(&mut self, vd: T0, vs2: T1, zimm5: T2);
}

/// RISC-V `vsm4r.vs` instruction.
///
/// # Forms
/// Assembly: `vsm4r.vs vs2, vd`
/// Rust: `vsm4r_vs(vd, vs2)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
pub trait Vsm4RVsEmitter<T0, T1> {
    fn vsm4r_vs(&mut self, vd: T0, vs2: T1);
}

/// RISC-V `vsm4r.vv` instruction.
///
/// # Forms
/// Assembly: `vsm4r.vv vs2, vd`
/// Rust: `vsm4r_vv(vd, vs2)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
pub trait Vsm4RVvEmitter<T0, T1> {
    fn vsm4r_vv(&mut self, vd: T0, vs2: T1);
}

/// RISC-V `vsm.v` instruction.
///
/// # Forms
/// Assembly: `vsm.v xs1, vs3`
/// Rust: `vsm_v(vs3, rs1)`
///
/// # Arguments
/// - `vs3` — Vector register operand.
/// - `rs1` — Memory base register.
pub trait VsmVEmitter<T0, T1> {
    fn vsm_v(&mut self, vs3: T0, rs1: T1);
}

/// RISC-V `vsmul.vv` instruction.
///
/// # Forms
/// Assembly: `vsmul.vv vm, vs2, vs1, vd`
/// Rust: `vsmul_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VsmulVvEmitter<T0, T1, T2, T3> {
    fn vsmul_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vsmul.vx` instruction.
///
/// # Forms
/// Assembly: `vsmul.vx vm, vs2, xs1, vd`
/// Rust: `vsmul_vx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VsmulVxEmitter<T0, T1, T2, T3> {
    fn vsmul_vx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vsoxei16.v` instruction.
///
/// # Forms
/// Assembly: `vsoxei16.v vm, vs2, xs1, vs3`
/// Rust: `vsoxei16_v(vs3, rs1, vs2, vm, nf)`
///
/// # Arguments
/// - `vs3` — Vector register operand.
/// - `rs1` — Memory base register.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
/// - `nf` — Vector segment field count.
pub trait Vsoxei16VEmitter<T0, T1, T2, T3, T4> {
    fn vsoxei16_v(&mut self, vs3: T0, rs1: T1, vs2: T2, vm: T3, nf: T4);
}

/// RISC-V `vsoxei32.v` instruction.
///
/// # Forms
/// Assembly: `vsoxei32.v vm, vs2, xs1, vs3`
/// Rust: `vsoxei32_v(vs3, rs1, vs2, vm, nf)`
///
/// # Arguments
/// - `vs3` — Vector register operand.
/// - `rs1` — Memory base register.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
/// - `nf` — Vector segment field count.
pub trait Vsoxei32VEmitter<T0, T1, T2, T3, T4> {
    fn vsoxei32_v(&mut self, vs3: T0, rs1: T1, vs2: T2, vm: T3, nf: T4);
}

/// RISC-V `vsoxei64.v` instruction.
///
/// # Forms
/// Assembly: `vsoxei64.v vm, vs2, xs1, vs3`
/// Rust: `vsoxei64_v(vs3, rs1, vs2, vm, nf)`
///
/// # Arguments
/// - `vs3` — Vector register operand.
/// - `rs1` — Memory base register.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
/// - `nf` — Vector segment field count.
pub trait Vsoxei64VEmitter<T0, T1, T2, T3, T4> {
    fn vsoxei64_v(&mut self, vs3: T0, rs1: T1, vs2: T2, vm: T3, nf: T4);
}

/// RISC-V `vsoxei8.v` instruction.
///
/// # Forms
/// Assembly: `vsoxei8.v vm, vs2, xs1, vs3`
/// Rust: `vsoxei8_v(vs3, rs1, vs2, vm, nf)`
///
/// # Arguments
/// - `vs3` — Vector register operand.
/// - `rs1` — Memory base register.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
/// - `nf` — Vector segment field count.
pub trait Vsoxei8VEmitter<T0, T1, T2, T3, T4> {
    fn vsoxei8_v(&mut self, vs3: T0, rs1: T1, vs2: T2, vm: T3, nf: T4);
}

/// RISC-V `vsra.vi` instruction.
///
/// # Forms
/// Assembly: `vsra.vi vm, vs2, vd, imm`
/// Rust: `vsra_vi(vd, vs2, zimm5, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `zimm5` — Immediate encoding value.
/// - `vm` — Vector mask control.
pub trait VsraViEmitter<T0, T1, T2, T3> {
    fn vsra_vi(&mut self, vd: T0, vs2: T1, zimm5: T2, vm: T3);
}

/// RISC-V `vsra.vv` instruction.
///
/// # Forms
/// Assembly: `vsra.vv vm, vs2, vs1, vd`
/// Rust: `vsra_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VsraVvEmitter<T0, T1, T2, T3> {
    fn vsra_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vsra.vx` instruction.
///
/// # Forms
/// Assembly: `vsra.vx vm, vs2, xs1, vd`
/// Rust: `vsra_vx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VsraVxEmitter<T0, T1, T2, T3> {
    fn vsra_vx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vsrl.vi` instruction.
///
/// # Forms
/// Assembly: `vsrl.vi vm, vs2, vd, imm`
/// Rust: `vsrl_vi(vd, vs2, zimm5, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `zimm5` — Immediate encoding value.
/// - `vm` — Vector mask control.
pub trait VsrlViEmitter<T0, T1, T2, T3> {
    fn vsrl_vi(&mut self, vd: T0, vs2: T1, zimm5: T2, vm: T3);
}

/// RISC-V `vsrl.vv` instruction.
///
/// # Forms
/// Assembly: `vsrl.vv vm, vs2, vs1, vd`
/// Rust: `vsrl_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VsrlVvEmitter<T0, T1, T2, T3> {
    fn vsrl_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vsrl.vx` instruction.
///
/// # Forms
/// Assembly: `vsrl.vx vm, vs2, xs1, vd`
/// Rust: `vsrl_vx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VsrlVxEmitter<T0, T1, T2, T3> {
    fn vsrl_vx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vsse16.v` instruction.
///
/// # Forms
/// Assembly: `vsse16.v vm, xs2, xs1, vs3`
/// Rust: `vsse16_v(vs3, rs1, rs2, vm, nf)`
///
/// # Arguments
/// - `vs3` — Vector register operand.
/// - `rs1` — Memory base register.
/// - `rs2` — Source register.
/// - `vm` — Vector mask control.
/// - `nf` — Vector segment field count.
pub trait Vsse16VEmitter<T0, T1, T2, T3, T4> {
    fn vsse16_v(&mut self, vs3: T0, rs1: T1, rs2: T2, vm: T3, nf: T4);
}

/// RISC-V `vsse32.v` instruction.
///
/// # Forms
/// Assembly: `vsse32.v vm, xs2, xs1, vs3`
/// Rust: `vsse32_v(vs3, rs1, rs2, vm, nf)`
///
/// # Arguments
/// - `vs3` — Vector register operand.
/// - `rs1` — Memory base register.
/// - `rs2` — Source register.
/// - `vm` — Vector mask control.
/// - `nf` — Vector segment field count.
pub trait Vsse32VEmitter<T0, T1, T2, T3, T4> {
    fn vsse32_v(&mut self, vs3: T0, rs1: T1, rs2: T2, vm: T3, nf: T4);
}

/// RISC-V `vsse64.v` instruction.
///
/// # Forms
/// Assembly: `vsse64.v vm, xs2, xs1, vs3`
/// Rust: `vsse64_v(vs3, rs1, rs2, vm, nf)`
///
/// # Arguments
/// - `vs3` — Vector register operand.
/// - `rs1` — Memory base register.
/// - `rs2` — Source register.
/// - `vm` — Vector mask control.
/// - `nf` — Vector segment field count.
pub trait Vsse64VEmitter<T0, T1, T2, T3, T4> {
    fn vsse64_v(&mut self, vs3: T0, rs1: T1, rs2: T2, vm: T3, nf: T4);
}

/// RISC-V `vsse8.v` instruction.
///
/// # Forms
/// Assembly: `vsse8.v vm, xs2, xs1, vs3`
/// Rust: `vsse8_v(vs3, rs1, rs2, vm, nf)`
///
/// # Arguments
/// - `vs3` — Vector register operand.
/// - `rs1` — Memory base register.
/// - `rs2` — Source register.
/// - `vm` — Vector mask control.
/// - `nf` — Vector segment field count.
pub trait Vsse8VEmitter<T0, T1, T2, T3, T4> {
    fn vsse8_v(&mut self, vs3: T0, rs1: T1, rs2: T2, vm: T3, nf: T4);
}

/// RISC-V `vssra.vi` instruction.
///
/// # Forms
/// Assembly: `vssra.vi vm, vs2, vd, imm`
/// Rust: `vssra_vi(vd, vs2, zimm5, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `zimm5` — Immediate encoding value.
/// - `vm` — Vector mask control.
pub trait VssraViEmitter<T0, T1, T2, T3> {
    fn vssra_vi(&mut self, vd: T0, vs2: T1, zimm5: T2, vm: T3);
}

/// RISC-V `vssra.vv` instruction.
///
/// # Forms
/// Assembly: `vssra.vv vm, vs2, vs1, vd`
/// Rust: `vssra_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VssraVvEmitter<T0, T1, T2, T3> {
    fn vssra_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vssra.vx` instruction.
///
/// # Forms
/// Assembly: `vssra.vx vm, vs2, xs1, vd`
/// Rust: `vssra_vx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VssraVxEmitter<T0, T1, T2, T3> {
    fn vssra_vx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vssrl.vi` instruction.
///
/// # Forms
/// Assembly: `vssrl.vi vm, vs2, vd, imm`
/// Rust: `vssrl_vi(vd, vs2, zimm5, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `zimm5` — Immediate encoding value.
/// - `vm` — Vector mask control.
pub trait VssrlViEmitter<T0, T1, T2, T3> {
    fn vssrl_vi(&mut self, vd: T0, vs2: T1, zimm5: T2, vm: T3);
}

/// RISC-V `vssrl.vv` instruction.
///
/// # Forms
/// Assembly: `vssrl.vv vm, vs2, vs1, vd`
/// Rust: `vssrl_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VssrlVvEmitter<T0, T1, T2, T3> {
    fn vssrl_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vssrl.vx` instruction.
///
/// # Forms
/// Assembly: `vssrl.vx vm, vs2, xs1, vd`
/// Rust: `vssrl_vx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VssrlVxEmitter<T0, T1, T2, T3> {
    fn vssrl_vx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vssub.vv` instruction.
///
/// # Forms
/// Assembly: `vssub.vv vm, vs2, vs1, vd`
/// Rust: `vssub_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VssubVvEmitter<T0, T1, T2, T3> {
    fn vssub_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vssub.vx` instruction.
///
/// # Forms
/// Assembly: `vssub.vx vm, vs2, xs1, vd`
/// Rust: `vssub_vx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VssubVxEmitter<T0, T1, T2, T3> {
    fn vssub_vx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vssubu.vv` instruction.
///
/// # Forms
/// Assembly: `vssubu.vv vm, vs2, vs1, vd`
/// Rust: `vssubu_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VssubuVvEmitter<T0, T1, T2, T3> {
    fn vssubu_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vssubu.vx` instruction.
///
/// # Forms
/// Assembly: `vssubu.vx vm, vs2, xs1, vd`
/// Rust: `vssubu_vx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VssubuVxEmitter<T0, T1, T2, T3> {
    fn vssubu_vx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vsub.vv` instruction.
///
/// # Forms
/// Assembly: `vsub.vv vm, vs2, vs1, vd`
/// Rust: `vsub_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VsubVvEmitter<T0, T1, T2, T3> {
    fn vsub_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vsub.vx` instruction.
///
/// # Forms
/// Assembly: `vsub.vx vm, vs2, xs1, vd`
/// Rust: `vsub_vx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VsubVxEmitter<T0, T1, T2, T3> {
    fn vsub_vx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vsuxei16.v` instruction.
///
/// # Forms
/// Assembly: `vsuxei16.v vm, vs2, xs1, vs3`
/// Rust: `vsuxei16_v(vs3, rs1, vs2, vm, nf)`
///
/// # Arguments
/// - `vs3` — Vector register operand.
/// - `rs1` — Memory base register.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
/// - `nf` — Vector segment field count.
pub trait Vsuxei16VEmitter<T0, T1, T2, T3, T4> {
    fn vsuxei16_v(&mut self, vs3: T0, rs1: T1, vs2: T2, vm: T3, nf: T4);
}

/// RISC-V `vsuxei32.v` instruction.
///
/// # Forms
/// Assembly: `vsuxei32.v vm, vs2, xs1, vs3`
/// Rust: `vsuxei32_v(vs3, rs1, vs2, vm, nf)`
///
/// # Arguments
/// - `vs3` — Vector register operand.
/// - `rs1` — Memory base register.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
/// - `nf` — Vector segment field count.
pub trait Vsuxei32VEmitter<T0, T1, T2, T3, T4> {
    fn vsuxei32_v(&mut self, vs3: T0, rs1: T1, vs2: T2, vm: T3, nf: T4);
}

/// RISC-V `vsuxei64.v` instruction.
///
/// # Forms
/// Assembly: `vsuxei64.v vm, vs2, xs1, vs3`
/// Rust: `vsuxei64_v(vs3, rs1, vs2, vm, nf)`
///
/// # Arguments
/// - `vs3` — Vector register operand.
/// - `rs1` — Memory base register.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
/// - `nf` — Vector segment field count.
pub trait Vsuxei64VEmitter<T0, T1, T2, T3, T4> {
    fn vsuxei64_v(&mut self, vs3: T0, rs1: T1, vs2: T2, vm: T3, nf: T4);
}

/// RISC-V `vsuxei8.v` instruction.
///
/// # Forms
/// Assembly: `vsuxei8.v vm, vs2, xs1, vs3`
/// Rust: `vsuxei8_v(vs3, rs1, vs2, vm, nf)`
///
/// # Arguments
/// - `vs3` — Vector register operand.
/// - `rs1` — Memory base register.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
/// - `nf` — Vector segment field count.
pub trait Vsuxei8VEmitter<T0, T1, T2, T3, T4> {
    fn vsuxei8_v(&mut self, vs3: T0, rs1: T1, vs2: T2, vm: T3, nf: T4);
}

/// RISC-V `vwadd.vv` instruction.
///
/// # Forms
/// Assembly: `vwadd.vv vm, vs2, vs1, vd`
/// Rust: `vwadd_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VwaddVvEmitter<T0, T1, T2, T3> {
    fn vwadd_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vwadd.vx` instruction.
///
/// # Forms
/// Assembly: `vwadd.vx vm, vs2, xs1, vd`
/// Rust: `vwadd_vx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VwaddVxEmitter<T0, T1, T2, T3> {
    fn vwadd_vx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vwadd.wv` instruction.
///
/// # Forms
/// Assembly: `vwadd.wv vm, vs2, vs1, vd`
/// Rust: `vwadd_wv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VwaddWvEmitter<T0, T1, T2, T3> {
    fn vwadd_wv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vwadd.wx` instruction.
///
/// # Forms
/// Assembly: `vwadd.wx vm, vs2, xs1, vd`
/// Rust: `vwadd_wx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VwaddWxEmitter<T0, T1, T2, T3> {
    fn vwadd_wx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vwaddu.vv` instruction.
///
/// # Forms
/// Assembly: `vwaddu.vv vm, vs2, vs1, vd`
/// Rust: `vwaddu_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VwadduVvEmitter<T0, T1, T2, T3> {
    fn vwaddu_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vwaddu.vx` instruction.
///
/// # Forms
/// Assembly: `vwaddu.vx vm, vs2, xs1, vd`
/// Rust: `vwaddu_vx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VwadduVxEmitter<T0, T1, T2, T3> {
    fn vwaddu_vx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vwaddu.wv` instruction.
///
/// # Forms
/// Assembly: `vwaddu.wv vm, vs2, vs1, vd`
/// Rust: `vwaddu_wv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VwadduWvEmitter<T0, T1, T2, T3> {
    fn vwaddu_wv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vwaddu.wx` instruction.
///
/// # Forms
/// Assembly: `vwaddu.wx vm, vs2, xs1, vd`
/// Rust: `vwaddu_wx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VwadduWxEmitter<T0, T1, T2, T3> {
    fn vwaddu_wx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vwmacc.vv` instruction.
///
/// # Forms
/// Assembly: `vwmacc.vv vm, vs2, vs1, vd`
/// Rust: `vwmacc_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VwmaccVvEmitter<T0, T1, T2, T3> {
    fn vwmacc_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vwmacc.vx` instruction.
///
/// # Forms
/// Assembly: `vwmacc.vx vm, vs2, xs1, vd`
/// Rust: `vwmacc_vx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VwmaccVxEmitter<T0, T1, T2, T3> {
    fn vwmacc_vx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vwmaccsu.vv` instruction.
///
/// # Forms
/// Assembly: `vwmaccsu.vv vm, vs2, vs1, vd`
/// Rust: `vwmaccsu_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VwmaccsuVvEmitter<T0, T1, T2, T3> {
    fn vwmaccsu_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vwmaccsu.vx` instruction.
///
/// # Forms
/// Assembly: `vwmaccsu.vx vm, vs2, xs1, vd`
/// Rust: `vwmaccsu_vx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VwmaccsuVxEmitter<T0, T1, T2, T3> {
    fn vwmaccsu_vx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vwmaccu.vv` instruction.
///
/// # Forms
/// Assembly: `vwmaccu.vv vm, vs2, vs1, vd`
/// Rust: `vwmaccu_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VwmaccuVvEmitter<T0, T1, T2, T3> {
    fn vwmaccu_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vwmaccu.vx` instruction.
///
/// # Forms
/// Assembly: `vwmaccu.vx vm, vs2, xs1, vd`
/// Rust: `vwmaccu_vx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VwmaccuVxEmitter<T0, T1, T2, T3> {
    fn vwmaccu_vx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vwmaccus.vx` instruction.
///
/// # Forms
/// Assembly: `vwmaccus.vx vm, vs2, xs1, vd`
/// Rust: `vwmaccus_vx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VwmaccusVxEmitter<T0, T1, T2, T3> {
    fn vwmaccus_vx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vwmul.vv` instruction.
///
/// # Forms
/// Assembly: `vwmul.vv vm, vs2, vs1, vd`
/// Rust: `vwmul_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VwmulVvEmitter<T0, T1, T2, T3> {
    fn vwmul_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vwmul.vx` instruction.
///
/// # Forms
/// Assembly: `vwmul.vx vm, vs2, xs1, vd`
/// Rust: `vwmul_vx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VwmulVxEmitter<T0, T1, T2, T3> {
    fn vwmul_vx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vwmulsu.vv` instruction.
///
/// # Forms
/// Assembly: `vwmulsu.vv vm, vs2, vs1, vd`
/// Rust: `vwmulsu_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VwmulsuVvEmitter<T0, T1, T2, T3> {
    fn vwmulsu_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vwmulsu.vx` instruction.
///
/// # Forms
/// Assembly: `vwmulsu.vx vm, vs2, xs1, vd`
/// Rust: `vwmulsu_vx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VwmulsuVxEmitter<T0, T1, T2, T3> {
    fn vwmulsu_vx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vwmulu.vv` instruction.
///
/// # Forms
/// Assembly: `vwmulu.vv vm, vs2, vs1, vd`
/// Rust: `vwmulu_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VwmuluVvEmitter<T0, T1, T2, T3> {
    fn vwmulu_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vwmulu.vx` instruction.
///
/// # Forms
/// Assembly: `vwmulu.vx vm, vs2, xs1, vd`
/// Rust: `vwmulu_vx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VwmuluVxEmitter<T0, T1, T2, T3> {
    fn vwmulu_vx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vwredsum.vs` instruction.
///
/// # Forms
/// Assembly: `vwredsum.vs vm, vs2, vs1, vd`
/// Rust: `vwredsum_vs(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VwredsumVsEmitter<T0, T1, T2, T3> {
    fn vwredsum_vs(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vwredsumu.vs` instruction.
///
/// # Forms
/// Assembly: `vwredsumu.vs vm, vs2, vs1, vd`
/// Rust: `vwredsumu_vs(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VwredsumuVsEmitter<T0, T1, T2, T3> {
    fn vwredsumu_vs(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vwsll.vi` instruction.
///
/// # Forms
/// Assembly: `vwsll.vi vm, vs2, vd, imm`
/// Rust: `vwsll_vi(vd, vs2, zimm5, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `zimm5` — Immediate encoding value.
/// - `vm` — Vector mask control.
pub trait VwsllViEmitter<T0, T1, T2, T3> {
    fn vwsll_vi(&mut self, vd: T0, vs2: T1, zimm5: T2, vm: T3);
}

/// RISC-V `vwsll.vv` instruction.
///
/// # Forms
/// Assembly: `vwsll.vv vm, vs2, vs1, vd`
/// Rust: `vwsll_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VwsllVvEmitter<T0, T1, T2, T3> {
    fn vwsll_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vwsll.vx` instruction.
///
/// # Forms
/// Assembly: `vwsll.vx vm, vs2, xs1, vd`
/// Rust: `vwsll_vx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VwsllVxEmitter<T0, T1, T2, T3> {
    fn vwsll_vx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vwsub.vv` instruction.
///
/// # Forms
/// Assembly: `vwsub.vv vm, vs2, vs1, vd`
/// Rust: `vwsub_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VwsubVvEmitter<T0, T1, T2, T3> {
    fn vwsub_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vwsub.vx` instruction.
///
/// # Forms
/// Assembly: `vwsub.vx vm, vs2, xs1, vd`
/// Rust: `vwsub_vx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VwsubVxEmitter<T0, T1, T2, T3> {
    fn vwsub_vx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vwsub.wv` instruction.
///
/// # Forms
/// Assembly: `vwsub.wv vm, vs2, vs1, vd`
/// Rust: `vwsub_wv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VwsubWvEmitter<T0, T1, T2, T3> {
    fn vwsub_wv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vwsub.wx` instruction.
///
/// # Forms
/// Assembly: `vwsub.wx vm, vs2, xs1, vd`
/// Rust: `vwsub_wx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VwsubWxEmitter<T0, T1, T2, T3> {
    fn vwsub_wx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vwsubu.vv` instruction.
///
/// # Forms
/// Assembly: `vwsubu.vv vm, vs2, vs1, vd`
/// Rust: `vwsubu_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VwsubuVvEmitter<T0, T1, T2, T3> {
    fn vwsubu_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vwsubu.vx` instruction.
///
/// # Forms
/// Assembly: `vwsubu.vx vm, vs2, xs1, vd`
/// Rust: `vwsubu_vx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VwsubuVxEmitter<T0, T1, T2, T3> {
    fn vwsubu_vx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vwsubu.wv` instruction.
///
/// # Forms
/// Assembly: `vwsubu.wv vm, vs2, vs1, vd`
/// Rust: `vwsubu_wv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VwsubuWvEmitter<T0, T1, T2, T3> {
    fn vwsubu_wv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vwsubu.wx` instruction.
///
/// # Forms
/// Assembly: `vwsubu.wx vm, vs2, xs1, vd`
/// Rust: `vwsubu_wx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VwsubuWxEmitter<T0, T1, T2, T3> {
    fn vwsubu_wx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vxor.vi` instruction.
///
/// # Forms
/// Assembly: `vxor.vi vm, vs2, vd, imm`
/// Rust: `vxor_vi(vd, vs2, simm5, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `simm5` — Immediate encoding value.
/// - `vm` — Vector mask control.
pub trait VxorViEmitter<T0, T1, T2, T3> {
    fn vxor_vi(&mut self, vd: T0, vs2: T1, simm5: T2, vm: T3);
}

/// RISC-V `vxor.vv` instruction.
///
/// # Forms
/// Assembly: `vxor.vv vm, vs2, vs1, vd`
/// Rust: `vxor_vv(vd, vs1, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs1` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VxorVvEmitter<T0, T1, T2, T3> {
    fn vxor_vv(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3);
}

/// RISC-V `vxor.vx` instruction.
///
/// # Forms
/// Assembly: `vxor.vx vm, vs2, xs1, vd`
/// Rust: `vxor_vx(vd, vs2, rs1, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `rs1` — Source register.
/// - `vm` — Vector mask control.
pub trait VxorVxEmitter<T0, T1, T2, T3> {
    fn vxor_vx(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3);
}

/// RISC-V `vzext.vf2` instruction.
///
/// # Forms
/// Assembly: `vzext.vf2 vm, vs2, vd`
/// Rust: `vzext_vf2(vd, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VzextVf2Emitter<T0, T1, T2> {
    fn vzext_vf2(&mut self, vd: T0, vs2: T1, vm: T2);
}

/// RISC-V `vzext.vf4` instruction.
///
/// # Forms
/// Assembly: `vzext.vf4 vm, vs2, vd`
/// Rust: `vzext_vf4(vd, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VzextVf4Emitter<T0, T1, T2> {
    fn vzext_vf4(&mut self, vd: T0, vs2: T1, vm: T2);
}

/// RISC-V `vzext.vf8` instruction.
///
/// # Forms
/// Assembly: `vzext.vf8 vm, vs2, vd`
/// Rust: `vzext_vf8(vd, vs2, vm)`
///
/// # Arguments
/// - `vd` — Vector register operand.
/// - `vs2` — Vector register operand.
/// - `vm` — Vector mask control.
pub trait VzextVf8Emitter<T0, T1, T2> {
    fn vzext_vf8(&mut self, vd: T0, vs2: T1, vm: T2);
}

/// Wait for interrupt
///
/// Can causes the processor to enter a low-power state until the next interrupt occurs.
///
/// &lt;%- if ext?(:H) -%&gt;
/// The behavior of `wfi` is affected by the `mstatus.TW`
/// and `hstatus.VTW` bits, as summarized below.
///
/// \[%autowidth,%footer\]
/// |===
/// .2+| \[.rotate\]#`mstatus.TW`# .2+| \[.rotate\]#`hstatus.VTW`# 4+^.&gt;| `wfi` behavior
/// h| HS-mode h| U-mode h| VS-mode h| in VU-mode
///
/// | 0 | 0 | Wait | Trap (I) | Wait | Trap (V)
/// | 0 | 1 | Wait | Trap (I) | Trap (V) | Trap (V)
/// | 1 | - | Trap (I) | Trap (I) | Trap (I) | Trap (I)
///
/// 6+| Trap (I) - Trap with `Illegal Instruction` code +
/// Trap (V) - Trap with `Virtual Instruction` code
/// |===
///
/// &lt;%- else -%&gt;
/// The `wfi` instruction is also affected by `mstatus.TW`, as shown below:
///
/// \[%autowidth,%footer\]
/// |===
/// .2+| \[.rotate\]#`mstatus.TW`# 2+^.&gt;| `wfi` behavior
/// h| S-mode h| U-mode
///
/// | 0 | Wait | Trap (I)
/// | 1 | Trap (I) | Trap (I)
///
/// 3+| Trap (I) - Trap with `Illegal Instruction` code
/// |===
///
/// &lt;%- end -%&gt;
///
/// When `wfi` is marked as causing a trap above, the implementation is allowed to wait
/// for an unspecified period of time to see if an interrupt occurs before raising the trap.
/// That period of time can be zero (_i.e._, `wfi` always causes a trap in the cases identified
/// above).
///
/// # Forms
/// Assembly: `wfi ""`
/// Rust: `wfi()`
///
/// # Arguments
pub trait WfiEmitter {
    fn wfi(&mut self);
}

/// RISC-V `wrs.nto` instruction.
///
/// # Forms
/// Assembly: `wrs.nto wrs_nto`
/// Rust: `wrs_nto()`
///
/// # Arguments
pub trait WrsNtoEmitter {
    fn wrs_nto(&mut self);
}

/// RISC-V `wrs.sto` instruction.
///
/// # Forms
/// Assembly: `wrs.sto wrs_sto`
/// Rust: `wrs_sto()`
///
/// # Arguments
pub trait WrsStoEmitter {
    fn wrs_sto(&mut self);
}

/// Exclusive NOR
///
/// This instruction performs the bit-wise exclusive-NOR operation on rs1 and rs2.
///
/// # Forms
/// Assembly: `xnor xd, xs1, xs2`
/// Rust: `xnor(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait XnorEmitter<T0, T1, T2> {
    fn xnor(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// Exclusive Or
///
/// Exclusive or rs1 with rs2, and store the result in rd
///
/// # Forms
/// Assembly: `xor xd, xs1, xs2`
/// Rust: `xor(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait XorEmitter<T0, T1, T2> {
    fn xor(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// Exclusive Or immediate
///
/// Exclusive or an immediate to the value in rs1, and store the result in rd
///
/// # Forms
/// Assembly: `xori xd, xs1, imm`
/// Rust: `xori(rd, rs1, imm)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `imm` — Immediate encoding value.
pub trait XoriEmitter<T0, T1, T2> {
    fn xori(&mut self, rd: T0, rs1: T1, imm: T2);
}

/// Crossbar permutation (nibbles)
///
/// The xperm4 instruction operates on nibbles. The rs1 register contains a vector of XLEN/4 4-bit
/// elements. The rs2 register contains a vector of XLEN/4 4-bit indexes. The result is each element in
/// rs2 replaced by the indexed element in rs1, or zero if the index into rs2 is out of bounds.
///
/// # Forms
/// Assembly: `xperm4 xd, xs1, xs2`
/// Rust: `xperm4(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait Xperm4Emitter<T0, T1, T2> {
    fn xperm4(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// Crossbar permutation (bytes)
///
/// The xperm8 instruction operates on bytes. The rs1 register contains a vector of XLEN/8 8-bit
/// elements. The rs2 register contains a vector of XLEN/8 8-bit indexes. The result is each element in
/// rs2 replaced by the indexed element in rs1, or zero if the index into rs2 is out of bounds.
///
/// # Forms
/// Assembly: `xperm8 xd, xs1, xs2`
/// Rust: `xperm8(rd, rs1, rs2)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
/// - `rs2` — Source register.
pub trait Xperm8Emitter<T0, T1, T2> {
    fn xperm8(&mut self, rd: T0, rs1: T1, rs2: T2);
}

/// RISC-V `zext.b` instruction.
///
/// # Forms
/// Assembly: `zext.b rd rs1`
/// Rust: `zext_b(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait ZextBEmitter<T0, T1> {
    fn zext_b(&mut self, rd: T0, rs1: T1);
}

/// Zero-extend halfword
///
/// This instruction zero-extends the least-significant halfword of the source to XLEN by inserting
/// 0's into all of the bits more significant than 15.
///
/// \[NOTE\]
/// The *zext.h* instruction is a pseudo-op for `pack` when `Zbkb` is implemented and XLEN == 32.
///
/// \[NOTE\]
/// The *zext.h* instruction is a pseudo-op for `packw` when `Zbkb` is implemented and XLEN == 64.
///
/// # Forms
/// Assembly: `zext.h xd, xs1`
/// Rust: `zext_h(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait ZextHEmitter<T0, T1> {
    fn zext_h(&mut self, rd: T0, rs1: T1);
}

/// Zero-extend halfword
///
/// This instruction zero-extends the least-significant halfword of the source to XLEN by inserting
/// 0's into all of the bits more significant than 15.
///
/// \[NOTE\]
/// The *zext.h* instruction is a pseudo-op for `pack` when `Zbkb` is implemented and XLEN == 32.
///
/// \[NOTE\]
/// The *zext.h* instruction is a pseudo-op for `packw` when `Zbkb` is implemented and XLEN == 64.
///
/// # Forms
/// Assembly: `zext.h.rv32 xd, xs1`
/// Rust: `zext_h_rv32(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait ZextHRv32Emitter<T0, T1> {
    fn zext_h_rv32(&mut self, rd: T0, rs1: T1);
}

/// RISC-V `zext.w` instruction.
///
/// # Forms
/// Assembly: `zext.w rd rs1`
/// Rust: `zext_w(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait ZextWEmitter<T0, T1> {
    fn zext_w(&mut self, rd: T0, rs1: T1);
}

/// Bit interleave
///
/// This instruction scatters all of the odd and even bits of a source word into the high and low halves
/// of a destination word. It is the inverse of the unzip instruction. This instruction is available only on
/// RV32.
///
/// # Forms
/// Assembly: `zip xd, xs1`
/// Rust: `zip(rd, rs1)`
///
/// # Arguments
/// - `rd` — Destination register.
/// - `rs1` — Source register.
pub trait ZipEmitter<T0, T1> {
    fn zip(&mut self, rd: T0, rs1: T1);
}

impl AddEmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn add(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::ADD as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl AddUwEmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn add_uw(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::ADDUW as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl<U2: Into<Imm>> AddiEmitter<Gp, Gp, U2> for Assembler<'_> {
    fn addi(&mut self, rd: Gp, rs1: Gp, imm: U2) {
        self.emit_n(
            Opcode::ADDI as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(imm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> AddiwEmitter<Gp, Gp, U2> for Assembler<'_> {
    fn addiw(&mut self, rd: Gp, rs1: Gp, imm: U2) {
        self.emit_n(
            Opcode::ADDIW as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(imm).as_operand(),
            ],
        );
    }
}

impl AddwEmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn addw(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::ADDW as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl<U3: Into<Imm>> Aes32DsiEmitter<Gp, Gp, Gp, U3> for Assembler<'_> {
    fn aes32dsi(&mut self, rd: Gp, rs1: Gp, rs2: Gp, bs: U3) {
        self.emit_n(
            Opcode::AES32DSI as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(bs).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> Aes32DsmiEmitter<Gp, Gp, Gp, U3> for Assembler<'_> {
    fn aes32dsmi(&mut self, rd: Gp, rs1: Gp, rs2: Gp, bs: U3) {
        self.emit_n(
            Opcode::AES32DSMI as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(bs).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> Aes32EsiEmitter<Gp, Gp, Gp, U3> for Assembler<'_> {
    fn aes32esi(&mut self, rd: Gp, rs1: Gp, rs2: Gp, bs: U3) {
        self.emit_n(
            Opcode::AES32ESI as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(bs).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> Aes32EsmiEmitter<Gp, Gp, Gp, U3> for Assembler<'_> {
    fn aes32esmi(&mut self, rd: Gp, rs1: Gp, rs2: Gp, bs: U3) {
        self.emit_n(
            Opcode::AES32ESMI as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(bs).as_operand(),
            ],
        );
    }
}

impl Aes64DsEmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn aes64ds(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::AES64DS as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl Aes64DsmEmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn aes64dsm(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::AES64DSM as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl Aes64EsEmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn aes64es(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::AES64ES as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl Aes64EsmEmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn aes64esm(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::AES64ESM as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl Aes64ImEmitter<Gp, Gp> for Assembler<'_> {
    fn aes64im(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::AES64IM as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl<U2: Into<Imm>> Aes64Ks1IEmitter<Gp, Gp, U2> for Assembler<'_> {
    fn aes64ks1i(&mut self, rd: Gp, rs1: Gp, rnum: U2) {
        self.emit_n(
            Opcode::AES64KS1I as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(rnum).as_operand(),
            ],
        );
    }
}

impl Aes64Ks2Emitter<Gp, Gp, Gp> for Assembler<'_> {
    fn aes64ks2(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::AES64KS2 as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> AmoaddBEmitter<Gp, Gp, Gp, U3, U4> for Assembler<'_> {
    fn amoadd_b(&mut self, rd: Gp, rs1: Gp, rs2: Gp, aq: U3, rl: U4) {
        self.emit_n(
            Opcode::AMOADDB as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(aq).as_operand(),
                Into::<Imm>::into(rl).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> AmoaddDEmitter<Gp, Gp, Gp, U3, U4> for Assembler<'_> {
    fn amoadd_d(&mut self, rd: Gp, rs1: Gp, rs2: Gp, aq: U3, rl: U4) {
        self.emit_n(
            Opcode::AMOADDD as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(aq).as_operand(),
                Into::<Imm>::into(rl).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> AmoaddHEmitter<Gp, Gp, Gp, U3, U4> for Assembler<'_> {
    fn amoadd_h(&mut self, rd: Gp, rs1: Gp, rs2: Gp, aq: U3, rl: U4) {
        self.emit_n(
            Opcode::AMOADDH as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(aq).as_operand(),
                Into::<Imm>::into(rl).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> AmoaddWEmitter<Gp, Gp, Gp, U3, U4> for Assembler<'_> {
    fn amoadd_w(&mut self, rd: Gp, rs1: Gp, rs2: Gp, aq: U3, rl: U4) {
        self.emit_n(
            Opcode::AMOADDW as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(aq).as_operand(),
                Into::<Imm>::into(rl).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> AmoandBEmitter<Gp, Gp, Gp, U3, U4> for Assembler<'_> {
    fn amoand_b(&mut self, rd: Gp, rs1: Gp, rs2: Gp, aq: U3, rl: U4) {
        self.emit_n(
            Opcode::AMOANDB as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(aq).as_operand(),
                Into::<Imm>::into(rl).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> AmoandDEmitter<Gp, Gp, Gp, U3, U4> for Assembler<'_> {
    fn amoand_d(&mut self, rd: Gp, rs1: Gp, rs2: Gp, aq: U3, rl: U4) {
        self.emit_n(
            Opcode::AMOANDD as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(aq).as_operand(),
                Into::<Imm>::into(rl).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> AmoandHEmitter<Gp, Gp, Gp, U3, U4> for Assembler<'_> {
    fn amoand_h(&mut self, rd: Gp, rs1: Gp, rs2: Gp, aq: U3, rl: U4) {
        self.emit_n(
            Opcode::AMOANDH as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(aq).as_operand(),
                Into::<Imm>::into(rl).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> AmoandWEmitter<Gp, Gp, Gp, U3, U4> for Assembler<'_> {
    fn amoand_w(&mut self, rd: Gp, rs1: Gp, rs2: Gp, aq: U3, rl: U4) {
        self.emit_n(
            Opcode::AMOANDW as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(aq).as_operand(),
                Into::<Imm>::into(rl).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> AmocasBEmitter<Gp, Gp, Gp, U3, U4> for Assembler<'_> {
    fn amocas_b(&mut self, rd: Gp, rs1: Gp, rs2: Gp, aq: U3, rl: U4) {
        self.emit_n(
            Opcode::AMOCASB as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(aq).as_operand(),
                Into::<Imm>::into(rl).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> AmocasDEmitter<Gp, Gp, Gp, U3, U4> for Assembler<'_> {
    fn amocas_d(&mut self, rd: Gp, rs1: Gp, rs2: Gp, aq: U3, rl: U4) {
        self.emit_n(
            Opcode::AMOCASD as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(aq).as_operand(),
                Into::<Imm>::into(rl).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> AmocasHEmitter<Gp, Gp, Gp, U3, U4> for Assembler<'_> {
    fn amocas_h(&mut self, rd: Gp, rs1: Gp, rs2: Gp, aq: U3, rl: U4) {
        self.emit_n(
            Opcode::AMOCASH as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(aq).as_operand(),
                Into::<Imm>::into(rl).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> AmocasQEmitter<Gp, Gp, Gp, U3, U4> for Assembler<'_> {
    fn amocas_q(&mut self, rd: Gp, rs1: Gp, rs2: Gp, aq: U3, rl: U4) {
        self.emit_n(
            Opcode::AMOCASQ as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(aq).as_operand(),
                Into::<Imm>::into(rl).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> AmocasWEmitter<Gp, Gp, Gp, U3, U4> for Assembler<'_> {
    fn amocas_w(&mut self, rd: Gp, rs1: Gp, rs2: Gp, aq: U3, rl: U4) {
        self.emit_n(
            Opcode::AMOCASW as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(aq).as_operand(),
                Into::<Imm>::into(rl).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> AmomaxBEmitter<Gp, Gp, Gp, U3, U4> for Assembler<'_> {
    fn amomax_b(&mut self, rd: Gp, rs1: Gp, rs2: Gp, aq: U3, rl: U4) {
        self.emit_n(
            Opcode::AMOMAXB as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(aq).as_operand(),
                Into::<Imm>::into(rl).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> AmomaxDEmitter<Gp, Gp, Gp, U3, U4> for Assembler<'_> {
    fn amomax_d(&mut self, rd: Gp, rs1: Gp, rs2: Gp, aq: U3, rl: U4) {
        self.emit_n(
            Opcode::AMOMAXD as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(aq).as_operand(),
                Into::<Imm>::into(rl).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> AmomaxHEmitter<Gp, Gp, Gp, U3, U4> for Assembler<'_> {
    fn amomax_h(&mut self, rd: Gp, rs1: Gp, rs2: Gp, aq: U3, rl: U4) {
        self.emit_n(
            Opcode::AMOMAXH as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(aq).as_operand(),
                Into::<Imm>::into(rl).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> AmomaxWEmitter<Gp, Gp, Gp, U3, U4> for Assembler<'_> {
    fn amomax_w(&mut self, rd: Gp, rs1: Gp, rs2: Gp, aq: U3, rl: U4) {
        self.emit_n(
            Opcode::AMOMAXW as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(aq).as_operand(),
                Into::<Imm>::into(rl).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> AmomaxuBEmitter<Gp, Gp, Gp, U3, U4> for Assembler<'_> {
    fn amomaxu_b(&mut self, rd: Gp, rs1: Gp, rs2: Gp, aq: U3, rl: U4) {
        self.emit_n(
            Opcode::AMOMAXUB as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(aq).as_operand(),
                Into::<Imm>::into(rl).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> AmomaxuDEmitter<Gp, Gp, Gp, U3, U4> for Assembler<'_> {
    fn amomaxu_d(&mut self, rd: Gp, rs1: Gp, rs2: Gp, aq: U3, rl: U4) {
        self.emit_n(
            Opcode::AMOMAXUD as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(aq).as_operand(),
                Into::<Imm>::into(rl).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> AmomaxuHEmitter<Gp, Gp, Gp, U3, U4> for Assembler<'_> {
    fn amomaxu_h(&mut self, rd: Gp, rs1: Gp, rs2: Gp, aq: U3, rl: U4) {
        self.emit_n(
            Opcode::AMOMAXUH as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(aq).as_operand(),
                Into::<Imm>::into(rl).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> AmomaxuWEmitter<Gp, Gp, Gp, U3, U4> for Assembler<'_> {
    fn amomaxu_w(&mut self, rd: Gp, rs1: Gp, rs2: Gp, aq: U3, rl: U4) {
        self.emit_n(
            Opcode::AMOMAXUW as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(aq).as_operand(),
                Into::<Imm>::into(rl).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> AmominBEmitter<Gp, Gp, Gp, U3, U4> for Assembler<'_> {
    fn amomin_b(&mut self, rd: Gp, rs1: Gp, rs2: Gp, aq: U3, rl: U4) {
        self.emit_n(
            Opcode::AMOMINB as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(aq).as_operand(),
                Into::<Imm>::into(rl).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> AmominDEmitter<Gp, Gp, Gp, U3, U4> for Assembler<'_> {
    fn amomin_d(&mut self, rd: Gp, rs1: Gp, rs2: Gp, aq: U3, rl: U4) {
        self.emit_n(
            Opcode::AMOMIND as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(aq).as_operand(),
                Into::<Imm>::into(rl).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> AmominHEmitter<Gp, Gp, Gp, U3, U4> for Assembler<'_> {
    fn amomin_h(&mut self, rd: Gp, rs1: Gp, rs2: Gp, aq: U3, rl: U4) {
        self.emit_n(
            Opcode::AMOMINH as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(aq).as_operand(),
                Into::<Imm>::into(rl).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> AmominWEmitter<Gp, Gp, Gp, U3, U4> for Assembler<'_> {
    fn amomin_w(&mut self, rd: Gp, rs1: Gp, rs2: Gp, aq: U3, rl: U4) {
        self.emit_n(
            Opcode::AMOMINW as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(aq).as_operand(),
                Into::<Imm>::into(rl).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> AmominuBEmitter<Gp, Gp, Gp, U3, U4> for Assembler<'_> {
    fn amominu_b(&mut self, rd: Gp, rs1: Gp, rs2: Gp, aq: U3, rl: U4) {
        self.emit_n(
            Opcode::AMOMINUB as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(aq).as_operand(),
                Into::<Imm>::into(rl).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> AmominuDEmitter<Gp, Gp, Gp, U3, U4> for Assembler<'_> {
    fn amominu_d(&mut self, rd: Gp, rs1: Gp, rs2: Gp, aq: U3, rl: U4) {
        self.emit_n(
            Opcode::AMOMINUD as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(aq).as_operand(),
                Into::<Imm>::into(rl).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> AmominuHEmitter<Gp, Gp, Gp, U3, U4> for Assembler<'_> {
    fn amominu_h(&mut self, rd: Gp, rs1: Gp, rs2: Gp, aq: U3, rl: U4) {
        self.emit_n(
            Opcode::AMOMINUH as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(aq).as_operand(),
                Into::<Imm>::into(rl).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> AmominuWEmitter<Gp, Gp, Gp, U3, U4> for Assembler<'_> {
    fn amominu_w(&mut self, rd: Gp, rs1: Gp, rs2: Gp, aq: U3, rl: U4) {
        self.emit_n(
            Opcode::AMOMINUW as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(aq).as_operand(),
                Into::<Imm>::into(rl).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> AmoorBEmitter<Gp, Gp, Gp, U3, U4> for Assembler<'_> {
    fn amoor_b(&mut self, rd: Gp, rs1: Gp, rs2: Gp, aq: U3, rl: U4) {
        self.emit_n(
            Opcode::AMOORB as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(aq).as_operand(),
                Into::<Imm>::into(rl).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> AmoorDEmitter<Gp, Gp, Gp, U3, U4> for Assembler<'_> {
    fn amoor_d(&mut self, rd: Gp, rs1: Gp, rs2: Gp, aq: U3, rl: U4) {
        self.emit_n(
            Opcode::AMOORD as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(aq).as_operand(),
                Into::<Imm>::into(rl).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> AmoorHEmitter<Gp, Gp, Gp, U3, U4> for Assembler<'_> {
    fn amoor_h(&mut self, rd: Gp, rs1: Gp, rs2: Gp, aq: U3, rl: U4) {
        self.emit_n(
            Opcode::AMOORH as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(aq).as_operand(),
                Into::<Imm>::into(rl).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> AmoorWEmitter<Gp, Gp, Gp, U3, U4> for Assembler<'_> {
    fn amoor_w(&mut self, rd: Gp, rs1: Gp, rs2: Gp, aq: U3, rl: U4) {
        self.emit_n(
            Opcode::AMOORW as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(aq).as_operand(),
                Into::<Imm>::into(rl).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> AmoswapBEmitter<Gp, Gp, Gp, U3, U4> for Assembler<'_> {
    fn amoswap_b(&mut self, rd: Gp, rs1: Gp, rs2: Gp, aq: U3, rl: U4) {
        self.emit_n(
            Opcode::AMOSWAPB as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(aq).as_operand(),
                Into::<Imm>::into(rl).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> AmoswapDEmitter<Gp, Gp, Gp, U3, U4> for Assembler<'_> {
    fn amoswap_d(&mut self, rd: Gp, rs1: Gp, rs2: Gp, aq: U3, rl: U4) {
        self.emit_n(
            Opcode::AMOSWAPD as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(aq).as_operand(),
                Into::<Imm>::into(rl).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> AmoswapHEmitter<Gp, Gp, Gp, U3, U4> for Assembler<'_> {
    fn amoswap_h(&mut self, rd: Gp, rs1: Gp, rs2: Gp, aq: U3, rl: U4) {
        self.emit_n(
            Opcode::AMOSWAPH as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(aq).as_operand(),
                Into::<Imm>::into(rl).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> AmoswapWEmitter<Gp, Gp, Gp, U3, U4> for Assembler<'_> {
    fn amoswap_w(&mut self, rd: Gp, rs1: Gp, rs2: Gp, aq: U3, rl: U4) {
        self.emit_n(
            Opcode::AMOSWAPW as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(aq).as_operand(),
                Into::<Imm>::into(rl).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> AmoxorBEmitter<Gp, Gp, Gp, U3, U4> for Assembler<'_> {
    fn amoxor_b(&mut self, rd: Gp, rs1: Gp, rs2: Gp, aq: U3, rl: U4) {
        self.emit_n(
            Opcode::AMOXORB as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(aq).as_operand(),
                Into::<Imm>::into(rl).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> AmoxorDEmitter<Gp, Gp, Gp, U3, U4> for Assembler<'_> {
    fn amoxor_d(&mut self, rd: Gp, rs1: Gp, rs2: Gp, aq: U3, rl: U4) {
        self.emit_n(
            Opcode::AMOXORD as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(aq).as_operand(),
                Into::<Imm>::into(rl).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> AmoxorHEmitter<Gp, Gp, Gp, U3, U4> for Assembler<'_> {
    fn amoxor_h(&mut self, rd: Gp, rs1: Gp, rs2: Gp, aq: U3, rl: U4) {
        self.emit_n(
            Opcode::AMOXORH as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(aq).as_operand(),
                Into::<Imm>::into(rl).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> AmoxorWEmitter<Gp, Gp, Gp, U3, U4> for Assembler<'_> {
    fn amoxor_w(&mut self, rd: Gp, rs1: Gp, rs2: Gp, aq: U3, rl: U4) {
        self.emit_n(
            Opcode::AMOXORW as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(aq).as_operand(),
                Into::<Imm>::into(rl).as_operand(),
            ],
        );
    }
}

impl AndEmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn and(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::AND as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl<U2: Into<Imm>> AndiEmitter<Gp, Gp, U2> for Assembler<'_> {
    fn andi(&mut self, rd: Gp, rs1: Gp, imm: U2) {
        self.emit_n(
            Opcode::ANDI as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(imm).as_operand(),
            ],
        );
    }
}

impl AndnEmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn andn(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::ANDN as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl<U1: Into<Imm>> AuipcEmitter<Gp, U1> for Assembler<'_> {
    fn auipc(&mut self, rd: Gp, imm: U1) {
        self.emit_n(
            Opcode::AUIPC as i64,
            &[rd.as_operand(), Into::<Imm>::into(imm).as_operand()],
        );
    }
}

impl AuipcEmitter<Gp, Label> for Assembler<'_> {
    fn auipc(&mut self, rd: Gp, imm: Label) {
        self.emit_n(Opcode::AUIPC as i64, &[rd.as_operand(), imm.as_operand()]);
    }
}

impl BclrEmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn bclr(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::BCLR as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl<U2: Into<Imm>> BclriEmitter<Gp, Gp, U2> for Assembler<'_> {
    fn bclri(&mut self, rd: Gp, rs1: Gp, shamtd: U2) {
        self.emit_n(
            Opcode::BCLRI as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(shamtd).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> BclriRv32Emitter<Gp, Gp, U2> for Assembler<'_> {
    fn bclri_rv32(&mut self, rd: Gp, rs1: Gp, shamtw: U2) {
        self.emit_n(
            Opcode::BCLRIRV32 as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(shamtw).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> BeqEmitter<Gp, Gp, U2> for Assembler<'_> {
    fn beq(&mut self, rs1: Gp, rs2: Gp, imm: U2) {
        self.emit_n(
            Opcode::BEQ as i64,
            &[
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(imm).as_operand(),
            ],
        );
    }
}

impl BeqEmitter<Gp, Gp, Label> for Assembler<'_> {
    fn beq(&mut self, rs1: Gp, rs2: Gp, imm: Label) {
        self.emit_n(
            Opcode::BEQ as i64,
            &[rs1.as_operand(), rs2.as_operand(), imm.as_operand()],
        );
    }
}

impl<U1: Into<Imm>> BeqzEmitter<Gp, U1> for Assembler<'_> {
    fn beqz(&mut self, rs1: Gp, imm: U1) {
        self.emit_n(
            Opcode::BEQZ as i64,
            &[rs1.as_operand(), Into::<Imm>::into(imm).as_operand()],
        );
    }
}

impl BeqzEmitter<Gp, Label> for Assembler<'_> {
    fn beqz(&mut self, rs1: Gp, imm: Label) {
        self.emit_n(Opcode::BEQZ as i64, &[rs1.as_operand(), imm.as_operand()]);
    }
}

impl BextEmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn bext(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::BEXT as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl<U2: Into<Imm>> BextiEmitter<Gp, Gp, U2> for Assembler<'_> {
    fn bexti(&mut self, rd: Gp, rs1: Gp, shamtd: U2) {
        self.emit_n(
            Opcode::BEXTI as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(shamtd).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> BextiRv32Emitter<Gp, Gp, U2> for Assembler<'_> {
    fn bexti_rv32(&mut self, rd: Gp, rs1: Gp, shamtw: U2) {
        self.emit_n(
            Opcode::BEXTIRV32 as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(shamtw).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> BgeEmitter<Gp, Gp, U2> for Assembler<'_> {
    fn bge(&mut self, rs1: Gp, rs2: Gp, imm: U2) {
        self.emit_n(
            Opcode::BGE as i64,
            &[
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(imm).as_operand(),
            ],
        );
    }
}

impl BgeEmitter<Gp, Gp, Label> for Assembler<'_> {
    fn bge(&mut self, rs1: Gp, rs2: Gp, imm: Label) {
        self.emit_n(
            Opcode::BGE as i64,
            &[rs1.as_operand(), rs2.as_operand(), imm.as_operand()],
        );
    }
}

impl<U2: Into<Imm>> BgeuEmitter<Gp, Gp, U2> for Assembler<'_> {
    fn bgeu(&mut self, rs1: Gp, rs2: Gp, imm: U2) {
        self.emit_n(
            Opcode::BGEU as i64,
            &[
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(imm).as_operand(),
            ],
        );
    }
}

impl BgeuEmitter<Gp, Gp, Label> for Assembler<'_> {
    fn bgeu(&mut self, rs1: Gp, rs2: Gp, imm: Label) {
        self.emit_n(
            Opcode::BGEU as i64,
            &[rs1.as_operand(), rs2.as_operand(), imm.as_operand()],
        );
    }
}

impl<U1: Into<Imm>> BgezEmitter<Gp, U1> for Assembler<'_> {
    fn bgez(&mut self, rs1: Gp, imm: U1) {
        self.emit_n(
            Opcode::BGEZ as i64,
            &[rs1.as_operand(), Into::<Imm>::into(imm).as_operand()],
        );
    }
}

impl BgezEmitter<Gp, Label> for Assembler<'_> {
    fn bgez(&mut self, rs1: Gp, imm: Label) {
        self.emit_n(Opcode::BGEZ as i64, &[rs1.as_operand(), imm.as_operand()]);
    }
}

impl<U2: Into<Imm>> BgtEmitter<Gp, Gp, U2> for Assembler<'_> {
    fn bgt(&mut self, rs1: Gp, rs2: Gp, imm: U2) {
        self.emit_n(
            Opcode::BGT as i64,
            &[
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(imm).as_operand(),
            ],
        );
    }
}

impl BgtEmitter<Gp, Gp, Label> for Assembler<'_> {
    fn bgt(&mut self, rs1: Gp, rs2: Gp, imm: Label) {
        self.emit_n(
            Opcode::BGT as i64,
            &[rs1.as_operand(), rs2.as_operand(), imm.as_operand()],
        );
    }
}

impl<U2: Into<Imm>> BgtuEmitter<Gp, Gp, U2> for Assembler<'_> {
    fn bgtu(&mut self, rs1: Gp, rs2: Gp, imm: U2) {
        self.emit_n(
            Opcode::BGTU as i64,
            &[
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(imm).as_operand(),
            ],
        );
    }
}

impl BgtuEmitter<Gp, Gp, Label> for Assembler<'_> {
    fn bgtu(&mut self, rs1: Gp, rs2: Gp, imm: Label) {
        self.emit_n(
            Opcode::BGTU as i64,
            &[rs1.as_operand(), rs2.as_operand(), imm.as_operand()],
        );
    }
}

impl<U1: Into<Imm>> BgtzEmitter<Gp, U1> for Assembler<'_> {
    fn bgtz(&mut self, rs2: Gp, imm: U1) {
        self.emit_n(
            Opcode::BGTZ as i64,
            &[rs2.as_operand(), Into::<Imm>::into(imm).as_operand()],
        );
    }
}

impl BgtzEmitter<Gp, Label> for Assembler<'_> {
    fn bgtz(&mut self, rs2: Gp, imm: Label) {
        self.emit_n(Opcode::BGTZ as i64, &[rs2.as_operand(), imm.as_operand()]);
    }
}

impl BinvEmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn binv(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::BINV as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl<U2: Into<Imm>> BinviEmitter<Gp, Gp, U2> for Assembler<'_> {
    fn binvi(&mut self, rd: Gp, rs1: Gp, shamtd: U2) {
        self.emit_n(
            Opcode::BINVI as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(shamtd).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> BinviRv32Emitter<Gp, Gp, U2> for Assembler<'_> {
    fn binvi_rv32(&mut self, rd: Gp, rs1: Gp, shamtw: U2) {
        self.emit_n(
            Opcode::BINVIRV32 as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(shamtw).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> BleEmitter<Gp, Gp, U2> for Assembler<'_> {
    fn ble(&mut self, rs1: Gp, rs2: Gp, imm: U2) {
        self.emit_n(
            Opcode::BLE as i64,
            &[
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(imm).as_operand(),
            ],
        );
    }
}

impl BleEmitter<Gp, Gp, Label> for Assembler<'_> {
    fn ble(&mut self, rs1: Gp, rs2: Gp, imm: Label) {
        self.emit_n(
            Opcode::BLE as i64,
            &[rs1.as_operand(), rs2.as_operand(), imm.as_operand()],
        );
    }
}

impl<U2: Into<Imm>> BleuEmitter<Gp, Gp, U2> for Assembler<'_> {
    fn bleu(&mut self, rs1: Gp, rs2: Gp, imm: U2) {
        self.emit_n(
            Opcode::BLEU as i64,
            &[
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(imm).as_operand(),
            ],
        );
    }
}

impl BleuEmitter<Gp, Gp, Label> for Assembler<'_> {
    fn bleu(&mut self, rs1: Gp, rs2: Gp, imm: Label) {
        self.emit_n(
            Opcode::BLEU as i64,
            &[rs1.as_operand(), rs2.as_operand(), imm.as_operand()],
        );
    }
}

impl<U1: Into<Imm>> BlezEmitter<Gp, U1> for Assembler<'_> {
    fn blez(&mut self, rs2: Gp, imm: U1) {
        self.emit_n(
            Opcode::BLEZ as i64,
            &[rs2.as_operand(), Into::<Imm>::into(imm).as_operand()],
        );
    }
}

impl BlezEmitter<Gp, Label> for Assembler<'_> {
    fn blez(&mut self, rs2: Gp, imm: Label) {
        self.emit_n(Opcode::BLEZ as i64, &[rs2.as_operand(), imm.as_operand()]);
    }
}

impl<U2: Into<Imm>> BltEmitter<Gp, Gp, U2> for Assembler<'_> {
    fn blt(&mut self, rs1: Gp, rs2: Gp, imm: U2) {
        self.emit_n(
            Opcode::BLT as i64,
            &[
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(imm).as_operand(),
            ],
        );
    }
}

impl BltEmitter<Gp, Gp, Label> for Assembler<'_> {
    fn blt(&mut self, rs1: Gp, rs2: Gp, imm: Label) {
        self.emit_n(
            Opcode::BLT as i64,
            &[rs1.as_operand(), rs2.as_operand(), imm.as_operand()],
        );
    }
}

impl<U2: Into<Imm>> BltuEmitter<Gp, Gp, U2> for Assembler<'_> {
    fn bltu(&mut self, rs1: Gp, rs2: Gp, imm: U2) {
        self.emit_n(
            Opcode::BLTU as i64,
            &[
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(imm).as_operand(),
            ],
        );
    }
}

impl BltuEmitter<Gp, Gp, Label> for Assembler<'_> {
    fn bltu(&mut self, rs1: Gp, rs2: Gp, imm: Label) {
        self.emit_n(
            Opcode::BLTU as i64,
            &[rs1.as_operand(), rs2.as_operand(), imm.as_operand()],
        );
    }
}

impl<U1: Into<Imm>> BltzEmitter<Gp, U1> for Assembler<'_> {
    fn bltz(&mut self, rs1: Gp, imm: U1) {
        self.emit_n(
            Opcode::BLTZ as i64,
            &[rs1.as_operand(), Into::<Imm>::into(imm).as_operand()],
        );
    }
}

impl BltzEmitter<Gp, Label> for Assembler<'_> {
    fn bltz(&mut self, rs1: Gp, imm: Label) {
        self.emit_n(Opcode::BLTZ as i64, &[rs1.as_operand(), imm.as_operand()]);
    }
}

impl<U2: Into<Imm>> BneEmitter<Gp, Gp, U2> for Assembler<'_> {
    fn bne(&mut self, rs1: Gp, rs2: Gp, imm: U2) {
        self.emit_n(
            Opcode::BNE as i64,
            &[
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(imm).as_operand(),
            ],
        );
    }
}

impl BneEmitter<Gp, Gp, Label> for Assembler<'_> {
    fn bne(&mut self, rs1: Gp, rs2: Gp, imm: Label) {
        self.emit_n(
            Opcode::BNE as i64,
            &[rs1.as_operand(), rs2.as_operand(), imm.as_operand()],
        );
    }
}

impl<U1: Into<Imm>> BnezEmitter<Gp, U1> for Assembler<'_> {
    fn bnez(&mut self, rs1: Gp, imm: U1) {
        self.emit_n(
            Opcode::BNEZ as i64,
            &[rs1.as_operand(), Into::<Imm>::into(imm).as_operand()],
        );
    }
}

impl BnezEmitter<Gp, Label> for Assembler<'_> {
    fn bnez(&mut self, rs1: Gp, imm: Label) {
        self.emit_n(Opcode::BNEZ as i64, &[rs1.as_operand(), imm.as_operand()]);
    }
}

impl Brev8Emitter<Gp, Gp> for Assembler<'_> {
    fn brev8(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::BREV8 as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl BsetEmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn bset(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::BSET as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl<U2: Into<Imm>> BsetiEmitter<Gp, Gp, U2> for Assembler<'_> {
    fn bseti(&mut self, rd: Gp, rs1: Gp, shamtd: U2) {
        self.emit_n(
            Opcode::BSETI as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(shamtd).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> BsetiRv32Emitter<Gp, Gp, U2> for Assembler<'_> {
    fn bseti_rv32(&mut self, rd: Gp, rs1: Gp, shamtw: U2) {
        self.emit_n(
            Opcode::BSETIRV32 as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(shamtw).as_operand(),
            ],
        );
    }
}

impl CAddEmitter<Gp, Gp> for Assembler<'_> {
    fn c_add(&mut self, rd: Gp, rs2: Gp) {
        self.emit_n(Opcode::CADD as i64, &[rd.as_operand(), rs2.as_operand()]);
    }
}

impl<U1: Into<Imm>> CAddiEmitter<Gp, U1> for Assembler<'_> {
    fn c_addi(&mut self, rd: Gp, imm: U1) {
        self.emit_n(
            Opcode::CADDI as i64,
            &[rd.as_operand(), Into::<Imm>::into(imm).as_operand()],
        );
    }
}

impl<U0: Into<Imm>> CAddi16spEmitter<U0> for Assembler<'_> {
    fn c_addi16sp(&mut self, imm: U0) {
        self.emit_n(
            Opcode::CADDI16SP as i64,
            &[Into::<Imm>::into(imm).as_operand()],
        );
    }
}

impl<U1: Into<Imm>> CAddi4spnEmitter<Gp, U1> for Assembler<'_> {
    fn c_addi4spn(&mut self, rd: Gp, imm: U1) {
        self.emit_n(
            Opcode::CADDI4SPN as i64,
            &[rd.as_operand(), Into::<Imm>::into(imm).as_operand()],
        );
    }
}

impl<U1: Into<Imm>> CAddiwEmitter<Gp, U1> for Assembler<'_> {
    fn c_addiw(&mut self, rd: Gp, imm: U1) {
        self.emit_n(
            Opcode::CADDIW as i64,
            &[rd.as_operand(), Into::<Imm>::into(imm).as_operand()],
        );
    }
}

impl CAddwEmitter<Gp, Gp> for Assembler<'_> {
    fn c_addw(&mut self, rd: Gp, rs2: Gp) {
        self.emit_n(Opcode::CADDW as i64, &[rd.as_operand(), rs2.as_operand()]);
    }
}

impl CAndEmitter<Gp, Gp> for Assembler<'_> {
    fn c_and(&mut self, rd: Gp, rs2: Gp) {
        self.emit_n(Opcode::CAND as i64, &[rd.as_operand(), rs2.as_operand()]);
    }
}

impl<U1: Into<Imm>> CAndiEmitter<Gp, U1> for Assembler<'_> {
    fn c_andi(&mut self, rd: Gp, imm: U1) {
        self.emit_n(
            Opcode::CANDI as i64,
            &[rd.as_operand(), Into::<Imm>::into(imm).as_operand()],
        );
    }
}

impl<U1: Into<Imm>> CBeqzEmitter<Gp, U1> for Assembler<'_> {
    fn c_beqz(&mut self, rs1: Gp, bimm9lohi: U1) {
        self.emit_n(
            Opcode::CBEQZ as i64,
            &[rs1.as_operand(), Into::<Imm>::into(bimm9lohi).as_operand()],
        );
    }
}

impl CBeqzEmitter<Gp, Label> for Assembler<'_> {
    fn c_beqz(&mut self, rs1: Gp, bimm9lohi: Label) {
        self.emit_n(
            Opcode::CBEQZ as i64,
            &[rs1.as_operand(), bimm9lohi.as_operand()],
        );
    }
}

impl<U1: Into<Imm>> CBnezEmitter<Gp, U1> for Assembler<'_> {
    fn c_bnez(&mut self, rs1: Gp, bimm9lohi: U1) {
        self.emit_n(
            Opcode::CBNEZ as i64,
            &[rs1.as_operand(), Into::<Imm>::into(bimm9lohi).as_operand()],
        );
    }
}

impl CBnezEmitter<Gp, Label> for Assembler<'_> {
    fn c_bnez(&mut self, rs1: Gp, bimm9lohi: Label) {
        self.emit_n(
            Opcode::CBNEZ as i64,
            &[rs1.as_operand(), bimm9lohi.as_operand()],
        );
    }
}

impl CEbreakEmitter for Assembler<'_> {
    fn c_ebreak(&mut self) {
        self.emit_n(Opcode::CEBREAK as i64, &[]);
    }
}

impl<U2: Into<Imm>> CFldEmitter<Fp, Gp, U2> for Assembler<'_> {
    fn c_fld(&mut self, rd: Fp, rs1: Gp, imm: U2) {
        self.emit_n(
            Opcode::CFLD as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(imm).as_operand(),
            ],
        );
    }
}

impl<U1: Into<Imm>> CFldspEmitter<Fp, U1> for Assembler<'_> {
    fn c_fldsp(&mut self, rd: Fp, imm: U1) {
        self.emit_n(
            Opcode::CFLDSP as i64,
            &[rd.as_operand(), Into::<Imm>::into(imm).as_operand()],
        );
    }
}

impl<U2: Into<Imm>> CFlwEmitter<Fp, Gp, U2> for Assembler<'_> {
    fn c_flw(&mut self, rd: Fp, rs1: Gp, imm: U2) {
        self.emit_n(
            Opcode::CFLW as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(imm).as_operand(),
            ],
        );
    }
}

impl<U1: Into<Imm>> CFlwspEmitter<Fp, U1> for Assembler<'_> {
    fn c_flwsp(&mut self, rd: Fp, imm: U1) {
        self.emit_n(
            Opcode::CFLWSP as i64,
            &[rd.as_operand(), Into::<Imm>::into(imm).as_operand()],
        );
    }
}

impl<U2: Into<Imm>> CFsdEmitter<Gp, Fp, U2> for Assembler<'_> {
    fn c_fsd(&mut self, rs1: Gp, rs2: Fp, imm: U2) {
        self.emit_n(
            Opcode::CFSD as i64,
            &[
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(imm).as_operand(),
            ],
        );
    }
}

impl<U1: Into<Imm>> CFsdspEmitter<Fp, U1> for Assembler<'_> {
    fn c_fsdsp(&mut self, rs2: Fp, imm: U1) {
        self.emit_n(
            Opcode::CFSDSP as i64,
            &[rs2.as_operand(), Into::<Imm>::into(imm).as_operand()],
        );
    }
}

impl<U2: Into<Imm>> CFswEmitter<Gp, Fp, U2> for Assembler<'_> {
    fn c_fsw(&mut self, rs1: Gp, rs2: Fp, imm: U2) {
        self.emit_n(
            Opcode::CFSW as i64,
            &[
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(imm).as_operand(),
            ],
        );
    }
}

impl<U1: Into<Imm>> CFswspEmitter<Fp, U1> for Assembler<'_> {
    fn c_fswsp(&mut self, rs2: Fp, imm: U1) {
        self.emit_n(
            Opcode::CFSWSP as i64,
            &[rs2.as_operand(), Into::<Imm>::into(imm).as_operand()],
        );
    }
}

impl<U0: Into<Imm>> CJEmitter<U0> for Assembler<'_> {
    fn c_j(&mut self, imm: U0) {
        self.emit_n(Opcode::CJ as i64, &[Into::<Imm>::into(imm).as_operand()]);
    }
}

impl CJEmitter<Label> for Assembler<'_> {
    fn c_j(&mut self, imm: Label) {
        self.emit_n(Opcode::CJ as i64, &[imm.as_operand()]);
    }
}

impl<U0: Into<Imm>> CJalEmitter<U0> for Assembler<'_> {
    fn c_jal(&mut self, imm: U0) {
        self.emit_n(Opcode::CJAL as i64, &[Into::<Imm>::into(imm).as_operand()]);
    }
}

impl CJalEmitter<Label> for Assembler<'_> {
    fn c_jal(&mut self, imm: Label) {
        self.emit_n(Opcode::CJAL as i64, &[imm.as_operand()]);
    }
}

impl CJalrEmitter<Gp> for Assembler<'_> {
    fn c_jalr(&mut self, rs1: Gp) {
        self.emit_n(Opcode::CJALR as i64, &[rs1.as_operand()]);
    }
}

impl CJrEmitter<Gp> for Assembler<'_> {
    fn c_jr(&mut self, rs1: Gp) {
        self.emit_n(Opcode::CJR as i64, &[rs1.as_operand()]);
    }
}

impl<U2: Into<Imm>> CLbuEmitter<Gp, Gp, U2> for Assembler<'_> {
    fn c_lbu(&mut self, rd: Gp, rs1: Gp, imm: U2) {
        self.emit_n(
            Opcode::CLBU as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(imm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> CLdEmitter<Gp, Gp, U2> for Assembler<'_> {
    fn c_ld(&mut self, rd: Gp, rs1: Gp, imm: U2) {
        self.emit_n(
            Opcode::CLD as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(imm).as_operand(),
            ],
        );
    }
}

impl<U1: Into<Imm>> CLdspEmitter<Gp, U1> for Assembler<'_> {
    fn c_ldsp(&mut self, rd: Gp, imm: U1) {
        self.emit_n(
            Opcode::CLDSP as i64,
            &[rd.as_operand(), Into::<Imm>::into(imm).as_operand()],
        );
    }
}

impl<U2: Into<Imm>> CLhEmitter<Gp, Gp, U2> for Assembler<'_> {
    fn c_lh(&mut self, rd: Gp, rs1: Gp, imm: U2) {
        self.emit_n(
            Opcode::CLH as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(imm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> CLhuEmitter<Gp, Gp, U2> for Assembler<'_> {
    fn c_lhu(&mut self, rd: Gp, rs1: Gp, imm: U2) {
        self.emit_n(
            Opcode::CLHU as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(imm).as_operand(),
            ],
        );
    }
}

impl<U1: Into<Imm>> CLiEmitter<Gp, U1> for Assembler<'_> {
    fn c_li(&mut self, rd: Gp, imm: U1) {
        self.emit_n(
            Opcode::CLI as i64,
            &[rd.as_operand(), Into::<Imm>::into(imm).as_operand()],
        );
    }
}

impl<U1: Into<Imm>> CLuiEmitter<Gp, U1> for Assembler<'_> {
    fn c_lui(&mut self, rd: Gp, imm: U1) {
        self.emit_n(
            Opcode::CLUI as i64,
            &[rd.as_operand(), Into::<Imm>::into(imm).as_operand()],
        );
    }
}

impl<U2: Into<Imm>> CLwEmitter<Gp, Gp, U2> for Assembler<'_> {
    fn c_lw(&mut self, rd: Gp, rs1: Gp, imm: U2) {
        self.emit_n(
            Opcode::CLW as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(imm).as_operand(),
            ],
        );
    }
}

impl<U1: Into<Imm>> CLwspEmitter<Gp, U1> for Assembler<'_> {
    fn c_lwsp(&mut self, rd: Gp, imm: U1) {
        self.emit_n(
            Opcode::CLWSP as i64,
            &[rd.as_operand(), Into::<Imm>::into(imm).as_operand()],
        );
    }
}

impl CMop1Emitter for Assembler<'_> {
    fn c_mop_1(&mut self) {
        self.emit_n(Opcode::CMOP1 as i64, &[]);
    }
}

impl CMop11Emitter for Assembler<'_> {
    fn c_mop_11(&mut self) {
        self.emit_n(Opcode::CMOP11 as i64, &[]);
    }
}

impl CMop13Emitter for Assembler<'_> {
    fn c_mop_13(&mut self) {
        self.emit_n(Opcode::CMOP13 as i64, &[]);
    }
}

impl CMop15Emitter for Assembler<'_> {
    fn c_mop_15(&mut self) {
        self.emit_n(Opcode::CMOP15 as i64, &[]);
    }
}

impl CMop3Emitter for Assembler<'_> {
    fn c_mop_3(&mut self) {
        self.emit_n(Opcode::CMOP3 as i64, &[]);
    }
}

impl CMop5Emitter for Assembler<'_> {
    fn c_mop_5(&mut self) {
        self.emit_n(Opcode::CMOP5 as i64, &[]);
    }
}

impl CMop7Emitter for Assembler<'_> {
    fn c_mop_7(&mut self) {
        self.emit_n(Opcode::CMOP7 as i64, &[]);
    }
}

impl CMop9Emitter for Assembler<'_> {
    fn c_mop_9(&mut self) {
        self.emit_n(Opcode::CMOP9 as i64, &[]);
    }
}

impl<U0: Into<Imm>> CMopNEmitter<U0> for Assembler<'_> {
    fn c_mop_n(&mut self, mop_t: U0) {
        self.emit_n(
            Opcode::CMOPN as i64,
            &[Into::<Imm>::into(mop_t).as_operand()],
        );
    }
}

impl CMulEmitter<Gp, Gp> for Assembler<'_> {
    fn c_mul(&mut self, rd: Gp, rs2: Gp) {
        self.emit_n(Opcode::CMUL as i64, &[rd.as_operand(), rs2.as_operand()]);
    }
}

impl CMvEmitter<Gp, Gp> for Assembler<'_> {
    fn c_mv(&mut self, rd: Gp, rs2: Gp) {
        self.emit_n(Opcode::CMV as i64, &[rd.as_operand(), rs2.as_operand()]);
    }
}

impl<U0: Into<Imm>> CNopEmitter<U0> for Assembler<'_> {
    fn c_nop(&mut self, imm: U0) {
        self.emit_n(Opcode::CNOP as i64, &[Into::<Imm>::into(imm).as_operand()]);
    }
}

impl CNotEmitter<Gp> for Assembler<'_> {
    fn c_not(&mut self, rd: Gp) {
        self.emit_n(Opcode::CNOT as i64, &[rd.as_operand()]);
    }
}

impl CNtlAllEmitter for Assembler<'_> {
    fn c_ntl_all(&mut self) {
        self.emit_n(Opcode::CNTLALL as i64, &[]);
    }
}

impl CNtlP1Emitter for Assembler<'_> {
    fn c_ntl_p1(&mut self) {
        self.emit_n(Opcode::CNTLP1 as i64, &[]);
    }
}

impl CNtlPallEmitter for Assembler<'_> {
    fn c_ntl_pall(&mut self) {
        self.emit_n(Opcode::CNTLPALL as i64, &[]);
    }
}

impl CNtlS1Emitter for Assembler<'_> {
    fn c_ntl_s1(&mut self) {
        self.emit_n(Opcode::CNTLS1 as i64, &[]);
    }
}

impl COrEmitter<Gp, Gp> for Assembler<'_> {
    fn c_or(&mut self, rd: Gp, rs2: Gp) {
        self.emit_n(Opcode::COR as i64, &[rd.as_operand(), rs2.as_operand()]);
    }
}

impl<U2: Into<Imm>> CSbEmitter<Gp, Gp, U2> for Assembler<'_> {
    fn c_sb(&mut self, rs1: Gp, rs2: Gp, imm: U2) {
        self.emit_n(
            Opcode::CSB as i64,
            &[
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(imm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> CSdEmitter<Gp, Gp, U2> for Assembler<'_> {
    fn c_sd(&mut self, rs1: Gp, rs2: Gp, imm: U2) {
        self.emit_n(
            Opcode::CSD as i64,
            &[
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(imm).as_operand(),
            ],
        );
    }
}

impl<U1: Into<Imm>> CSdspEmitter<Gp, U1> for Assembler<'_> {
    fn c_sdsp(&mut self, rs2: Gp, imm: U1) {
        self.emit_n(
            Opcode::CSDSP as i64,
            &[rs2.as_operand(), Into::<Imm>::into(imm).as_operand()],
        );
    }
}

impl CSextBEmitter<Gp> for Assembler<'_> {
    fn c_sext_b(&mut self, rd: Gp) {
        self.emit_n(Opcode::CSEXTB as i64, &[rd.as_operand()]);
    }
}

impl CSextHEmitter<Gp> for Assembler<'_> {
    fn c_sext_h(&mut self, rd: Gp) {
        self.emit_n(Opcode::CSEXTH as i64, &[rd.as_operand()]);
    }
}

impl<U2: Into<Imm>> CShEmitter<Gp, Gp, U2> for Assembler<'_> {
    fn c_sh(&mut self, rs1: Gp, rs2: Gp, imm: U2) {
        self.emit_n(
            Opcode::CSH as i64,
            &[
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(imm).as_operand(),
            ],
        );
    }
}

impl<U1: Into<Imm>> CSlliEmitter<Gp, U1> for Assembler<'_> {
    fn c_slli(&mut self, rd: Gp, imm: U1) {
        self.emit_n(
            Opcode::CSLLI as i64,
            &[rd.as_operand(), Into::<Imm>::into(imm).as_operand()],
        );
    }
}

impl<U1: Into<Imm>> CSlliRv32Emitter<Gp, U1> for Assembler<'_> {
    fn c_slli_rv32(&mut self, rd: Gp, imm: U1) {
        self.emit_n(
            Opcode::CSLLIRV32 as i64,
            &[rd.as_operand(), Into::<Imm>::into(imm).as_operand()],
        );
    }
}

impl<U1: Into<Imm>> CSraiEmitter<Gp, U1> for Assembler<'_> {
    fn c_srai(&mut self, rd: Gp, imm: U1) {
        self.emit_n(
            Opcode::CSRAI as i64,
            &[rd.as_operand(), Into::<Imm>::into(imm).as_operand()],
        );
    }
}

impl<U1: Into<Imm>> CSraiRv32Emitter<Gp, U1> for Assembler<'_> {
    fn c_srai_rv32(&mut self, rd: Gp, imm: U1) {
        self.emit_n(
            Opcode::CSRAIRV32 as i64,
            &[rd.as_operand(), Into::<Imm>::into(imm).as_operand()],
        );
    }
}

impl<U1: Into<Imm>> CSrliEmitter<Gp, U1> for Assembler<'_> {
    fn c_srli(&mut self, rd: Gp, imm: U1) {
        self.emit_n(
            Opcode::CSRLI as i64,
            &[rd.as_operand(), Into::<Imm>::into(imm).as_operand()],
        );
    }
}

impl<U1: Into<Imm>> CSrliRv32Emitter<Gp, U1> for Assembler<'_> {
    fn c_srli_rv32(&mut self, rd: Gp, imm: U1) {
        self.emit_n(
            Opcode::CSRLIRV32 as i64,
            &[rd.as_operand(), Into::<Imm>::into(imm).as_operand()],
        );
    }
}

impl CSspopchkX5Emitter for Assembler<'_> {
    fn c_sspopchk_x5(&mut self) {
        self.emit_n(Opcode::CSSPOPCHKX5 as i64, &[]);
    }
}

impl CSspushX1Emitter for Assembler<'_> {
    fn c_sspush_x1(&mut self) {
        self.emit_n(Opcode::CSSPUSHX1 as i64, &[]);
    }
}

impl CSubEmitter<Gp, Gp> for Assembler<'_> {
    fn c_sub(&mut self, rd: Gp, rs2: Gp) {
        self.emit_n(Opcode::CSUB as i64, &[rd.as_operand(), rs2.as_operand()]);
    }
}

impl CSubwEmitter<Gp, Gp> for Assembler<'_> {
    fn c_subw(&mut self, rd: Gp, rs2: Gp) {
        self.emit_n(Opcode::CSUBW as i64, &[rd.as_operand(), rs2.as_operand()]);
    }
}

impl<U2: Into<Imm>> CSwEmitter<Gp, Gp, U2> for Assembler<'_> {
    fn c_sw(&mut self, rs1: Gp, rs2: Gp, imm: U2) {
        self.emit_n(
            Opcode::CSW as i64,
            &[
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(imm).as_operand(),
            ],
        );
    }
}

impl<U1: Into<Imm>> CSwspEmitter<Gp, U1> for Assembler<'_> {
    fn c_swsp(&mut self, rs2: Gp, imm: U1) {
        self.emit_n(
            Opcode::CSWSP as i64,
            &[rs2.as_operand(), Into::<Imm>::into(imm).as_operand()],
        );
    }
}

impl CXorEmitter<Gp, Gp> for Assembler<'_> {
    fn c_xor(&mut self, rd: Gp, rs2: Gp) {
        self.emit_n(Opcode::CXOR as i64, &[rd.as_operand(), rs2.as_operand()]);
    }
}

impl CZextBEmitter<Gp> for Assembler<'_> {
    fn c_zext_b(&mut self, rd: Gp) {
        self.emit_n(Opcode::CZEXTB as i64, &[rd.as_operand()]);
    }
}

impl CZextHEmitter<Gp> for Assembler<'_> {
    fn c_zext_h(&mut self, rd: Gp) {
        self.emit_n(Opcode::CZEXTH as i64, &[rd.as_operand()]);
    }
}

impl CZextWEmitter<Gp> for Assembler<'_> {
    fn c_zext_w(&mut self, rd: Gp) {
        self.emit_n(Opcode::CZEXTW as i64, &[rd.as_operand()]);
    }
}

impl CboCleanEmitter<Gp> for Assembler<'_> {
    fn cbo_clean(&mut self, rs1: Gp) {
        self.emit_n(Opcode::CBOCLEAN as i64, &[rs1.as_operand()]);
    }
}

impl CboFlushEmitter<Gp> for Assembler<'_> {
    fn cbo_flush(&mut self, rs1: Gp) {
        self.emit_n(Opcode::CBOFLUSH as i64, &[rs1.as_operand()]);
    }
}

impl CboInvalEmitter<Gp> for Assembler<'_> {
    fn cbo_inval(&mut self, rs1: Gp) {
        self.emit_n(Opcode::CBOINVAL as i64, &[rs1.as_operand()]);
    }
}

impl CboZeroEmitter<Gp> for Assembler<'_> {
    fn cbo_zero(&mut self, rs1: Gp) {
        self.emit_n(Opcode::CBOZERO as i64, &[rs1.as_operand()]);
    }
}

impl ClmulEmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn clmul(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::CLMUL as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl ClmulhEmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn clmulh(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::CLMULH as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl ClmulrEmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn clmulr(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::CLMULR as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl ClzEmitter<Gp, Gp> for Assembler<'_> {
    fn clz(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::CLZ as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl ClzwEmitter<Gp, Gp> for Assembler<'_> {
    fn clzw(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::CLZW as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl<U0: Into<Imm>> CmJaltEmitter<U0> for Assembler<'_> {
    fn cm_jalt(&mut self, index: U0) {
        self.emit_n(
            Opcode::CMJALT as i64,
            &[Into::<Imm>::into(index).as_operand()],
        );
    }
}

impl CpopEmitter<Gp, Gp> for Assembler<'_> {
    fn cpop(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::CPOP as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl CpopwEmitter<Gp, Gp> for Assembler<'_> {
    fn cpopw(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::CPOPW as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl<U1: Into<Imm>> CsrcEmitter<Gp, U1> for Assembler<'_> {
    fn csrc(&mut self, rs1: Gp, csr: U1) {
        self.emit_n(
            Opcode::CSRC as i64,
            &[rs1.as_operand(), Into::<Imm>::into(csr).as_operand()],
        );
    }
}

impl<U0: Into<Imm>, U1: Into<Imm>> CsrciEmitter<U0, U1> for Assembler<'_> {
    fn csrci(&mut self, csr: U0, zimm5: U1) {
        self.emit_n(
            Opcode::CSRCI as i64,
            &[
                Into::<Imm>::into(csr).as_operand(),
                Into::<Imm>::into(zimm5).as_operand(),
            ],
        );
    }
}

impl<U1: Into<Imm>> CsrrEmitter<Gp, U1> for Assembler<'_> {
    fn csrr(&mut self, rd: Gp, csr: U1) {
        self.emit_n(
            Opcode::CSRR as i64,
            &[rd.as_operand(), Into::<Imm>::into(csr).as_operand()],
        );
    }
}

impl<U2: Into<Imm>> CsrrcEmitter<Gp, Gp, U2> for Assembler<'_> {
    fn csrrc(&mut self, rd: Gp, rs1: Gp, csr: U2) {
        self.emit_n(
            Opcode::CSRRC as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(csr).as_operand(),
            ],
        );
    }
}

impl<U1: Into<Imm>, U2: Into<Imm>> CsrrciEmitter<Gp, U1, U2> for Assembler<'_> {
    fn csrrci(&mut self, rd: Gp, csr: U1, zimm5: U2) {
        self.emit_n(
            Opcode::CSRRCI as i64,
            &[
                rd.as_operand(),
                Into::<Imm>::into(csr).as_operand(),
                Into::<Imm>::into(zimm5).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> CsrrsEmitter<Gp, Gp, U2> for Assembler<'_> {
    fn csrrs(&mut self, rd: Gp, rs1: Gp, csr: U2) {
        self.emit_n(
            Opcode::CSRRS as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(csr).as_operand(),
            ],
        );
    }
}

impl<U1: Into<Imm>, U2: Into<Imm>> CsrrsiEmitter<Gp, U1, U2> for Assembler<'_> {
    fn csrrsi(&mut self, rd: Gp, csr: U1, zimm5: U2) {
        self.emit_n(
            Opcode::CSRRSI as i64,
            &[
                rd.as_operand(),
                Into::<Imm>::into(csr).as_operand(),
                Into::<Imm>::into(zimm5).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> CsrrwEmitter<Gp, Gp, U2> for Assembler<'_> {
    fn csrrw(&mut self, rd: Gp, rs1: Gp, csr: U2) {
        self.emit_n(
            Opcode::CSRRW as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(csr).as_operand(),
            ],
        );
    }
}

impl<U1: Into<Imm>, U2: Into<Imm>> CsrrwiEmitter<Gp, U1, U2> for Assembler<'_> {
    fn csrrwi(&mut self, rd: Gp, csr: U1, zimm5: U2) {
        self.emit_n(
            Opcode::CSRRWI as i64,
            &[
                rd.as_operand(),
                Into::<Imm>::into(csr).as_operand(),
                Into::<Imm>::into(zimm5).as_operand(),
            ],
        );
    }
}

impl<U1: Into<Imm>> CsrsEmitter<Gp, U1> for Assembler<'_> {
    fn csrs(&mut self, rs1: Gp, csr: U1) {
        self.emit_n(
            Opcode::CSRS as i64,
            &[rs1.as_operand(), Into::<Imm>::into(csr).as_operand()],
        );
    }
}

impl<U0: Into<Imm>, U1: Into<Imm>> CsrsiEmitter<U0, U1> for Assembler<'_> {
    fn csrsi(&mut self, csr: U0, zimm5: U1) {
        self.emit_n(
            Opcode::CSRSI as i64,
            &[
                Into::<Imm>::into(csr).as_operand(),
                Into::<Imm>::into(zimm5).as_operand(),
            ],
        );
    }
}

impl<U1: Into<Imm>> CsrwEmitter<Gp, U1> for Assembler<'_> {
    fn csrw(&mut self, rs1: Gp, csr: U1) {
        self.emit_n(
            Opcode::CSRW as i64,
            &[rs1.as_operand(), Into::<Imm>::into(csr).as_operand()],
        );
    }
}

impl<U0: Into<Imm>, U1: Into<Imm>> CsrwiEmitter<U0, U1> for Assembler<'_> {
    fn csrwi(&mut self, csr: U0, zimm5: U1) {
        self.emit_n(
            Opcode::CSRWI as i64,
            &[
                Into::<Imm>::into(csr).as_operand(),
                Into::<Imm>::into(zimm5).as_operand(),
            ],
        );
    }
}

impl CtzEmitter<Gp, Gp> for Assembler<'_> {
    fn ctz(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::CTZ as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl CtzwEmitter<Gp, Gp> for Assembler<'_> {
    fn ctzw(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::CTZW as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl CzeroEqzEmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn czero_eqz(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::CZEROEQZ as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl CzeroNezEmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn czero_nez(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::CZERONEZ as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl DivEmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn div(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::DIV as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl DivuEmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn divu(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::DIVU as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl DivuwEmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn divuw(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::DIVUW as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl DivwEmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn divw(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::DIVW as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl DretEmitter for Assembler<'_> {
    fn dret(&mut self) {
        self.emit_n(Opcode::DRET as i64, &[]);
    }
}

impl EbreakEmitter for Assembler<'_> {
    fn ebreak(&mut self) {
        self.emit_n(Opcode::EBREAK as i64, &[]);
    }
}

impl EcallEmitter for Assembler<'_> {
    fn ecall(&mut self) {
        self.emit_n(Opcode::ECALL as i64, &[]);
    }
}

impl FabsDEmitter<Fp, Fp, Fp> for Assembler<'_> {
    fn fabs_d(&mut self, rd: Fp, rs1: Fp, rs2: Fp) {
        self.emit_n(
            Opcode::FABSD as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl FabsHEmitter<Fp, Fp, Fp> for Assembler<'_> {
    fn fabs_h(&mut self, rd: Fp, rs1: Fp, rs2: Fp) {
        self.emit_n(
            Opcode::FABSH as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl FabsQEmitter<Fp, Fp, Fp> for Assembler<'_> {
    fn fabs_q(&mut self, rd: Fp, rs1: Fp, rs2: Fp) {
        self.emit_n(
            Opcode::FABSQ as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl FabsSEmitter<Fp, Fp, Fp> for Assembler<'_> {
    fn fabs_s(&mut self, rd: Fp, rs1: Fp, rs2: Fp) {
        self.emit_n(
            Opcode::FABSS as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl<U3: Into<Imm>> FaddDEmitter<Fp, Fp, Fp, U3> for Assembler<'_> {
    fn fadd_d(&mut self, rd: Fp, rs1: Fp, rs2: Fp, rm: U3) {
        self.emit_n(
            Opcode::FADDD as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> FaddHEmitter<Fp, Fp, Fp, U3> for Assembler<'_> {
    fn fadd_h(&mut self, rd: Fp, rs1: Fp, rs2: Fp, rm: U3) {
        self.emit_n(
            Opcode::FADDH as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> FaddQEmitter<Fp, Fp, Fp, U3> for Assembler<'_> {
    fn fadd_q(&mut self, rd: Fp, rs1: Fp, rs2: Fp, rm: U3) {
        self.emit_n(
            Opcode::FADDQ as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> FaddSEmitter<Fp, Fp, Fp, U3> for Assembler<'_> {
    fn fadd_s(&mut self, rd: Fp, rs1: Fp, rs2: Fp, rm: U3) {
        self.emit_n(
            Opcode::FADDS as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl FclassDEmitter<Gp, Fp> for Assembler<'_> {
    fn fclass_d(&mut self, rd: Gp, rs1: Fp) {
        self.emit_n(Opcode::FCLASSD as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl FclassHEmitter<Gp, Fp> for Assembler<'_> {
    fn fclass_h(&mut self, rd: Gp, rs1: Fp) {
        self.emit_n(Opcode::FCLASSH as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl FclassQEmitter<Gp, Fp> for Assembler<'_> {
    fn fclass_q(&mut self, rd: Gp, rs1: Fp) {
        self.emit_n(Opcode::FCLASSQ as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl FclassSEmitter<Gp, Fp> for Assembler<'_> {
    fn fclass_s(&mut self, rd: Gp, rs1: Fp) {
        self.emit_n(Opcode::FCLASSS as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl<U2: Into<Imm>> FcvtBf16SEmitter<Fp, Fp, U2> for Assembler<'_> {
    fn fcvt_bf16_s(&mut self, rd: Fp, rs1: Fp, rm: U2) {
        self.emit_n(
            Opcode::FCVTBF16S as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> FcvtDHEmitter<Fp, Fp, U2> for Assembler<'_> {
    fn fcvt_d_h(&mut self, rd: Fp, rs1: Fp, rm: U2) {
        self.emit_n(
            Opcode::FCVTDH as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> FcvtDLEmitter<Fp, Gp, U2> for Assembler<'_> {
    fn fcvt_d_l(&mut self, rd: Fp, rs1: Gp, rm: U2) {
        self.emit_n(
            Opcode::FCVTDL as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> FcvtDLuEmitter<Fp, Gp, U2> for Assembler<'_> {
    fn fcvt_d_lu(&mut self, rd: Fp, rs1: Gp, rm: U2) {
        self.emit_n(
            Opcode::FCVTDLU as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> FcvtDQEmitter<Fp, Fp, U2> for Assembler<'_> {
    fn fcvt_d_q(&mut self, rd: Fp, rs1: Fp, rm: U2) {
        self.emit_n(
            Opcode::FCVTDQ as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> FcvtDSEmitter<Fp, Fp, U2> for Assembler<'_> {
    fn fcvt_d_s(&mut self, rd: Fp, rs1: Fp, rm: U2) {
        self.emit_n(
            Opcode::FCVTDS as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> FcvtDWEmitter<Fp, Gp, U2> for Assembler<'_> {
    fn fcvt_d_w(&mut self, rd: Fp, rs1: Gp, rm: U2) {
        self.emit_n(
            Opcode::FCVTDW as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> FcvtDWuEmitter<Fp, Gp, U2> for Assembler<'_> {
    fn fcvt_d_wu(&mut self, rd: Fp, rs1: Gp, rm: U2) {
        self.emit_n(
            Opcode::FCVTDWU as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> FcvtHDEmitter<Fp, Fp, U2> for Assembler<'_> {
    fn fcvt_h_d(&mut self, rd: Fp, rs1: Fp, rm: U2) {
        self.emit_n(
            Opcode::FCVTHD as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> FcvtHLEmitter<Fp, Gp, U2> for Assembler<'_> {
    fn fcvt_h_l(&mut self, rd: Fp, rs1: Gp, rm: U2) {
        self.emit_n(
            Opcode::FCVTHL as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> FcvtHLuEmitter<Fp, Gp, U2> for Assembler<'_> {
    fn fcvt_h_lu(&mut self, rd: Fp, rs1: Gp, rm: U2) {
        self.emit_n(
            Opcode::FCVTHLU as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> FcvtHQEmitter<Fp, Fp, U2> for Assembler<'_> {
    fn fcvt_h_q(&mut self, rd: Fp, rs1: Fp, rm: U2) {
        self.emit_n(
            Opcode::FCVTHQ as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> FcvtHSEmitter<Fp, Fp, U2> for Assembler<'_> {
    fn fcvt_h_s(&mut self, rd: Fp, rs1: Fp, rm: U2) {
        self.emit_n(
            Opcode::FCVTHS as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> FcvtHWEmitter<Fp, Gp, U2> for Assembler<'_> {
    fn fcvt_h_w(&mut self, rd: Fp, rs1: Gp, rm: U2) {
        self.emit_n(
            Opcode::FCVTHW as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> FcvtHWuEmitter<Fp, Gp, U2> for Assembler<'_> {
    fn fcvt_h_wu(&mut self, rd: Fp, rs1: Gp, rm: U2) {
        self.emit_n(
            Opcode::FCVTHWU as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> FcvtLDEmitter<Gp, Fp, U2> for Assembler<'_> {
    fn fcvt_l_d(&mut self, rd: Gp, rs1: Fp, rm: U2) {
        self.emit_n(
            Opcode::FCVTLD as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> FcvtLHEmitter<Gp, Fp, U2> for Assembler<'_> {
    fn fcvt_l_h(&mut self, rd: Gp, rs1: Fp, rm: U2) {
        self.emit_n(
            Opcode::FCVTLH as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> FcvtLQEmitter<Gp, Fp, U2> for Assembler<'_> {
    fn fcvt_l_q(&mut self, rd: Gp, rs1: Fp, rm: U2) {
        self.emit_n(
            Opcode::FCVTLQ as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> FcvtLSEmitter<Gp, Fp, U2> for Assembler<'_> {
    fn fcvt_l_s(&mut self, rd: Gp, rs1: Fp, rm: U2) {
        self.emit_n(
            Opcode::FCVTLS as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> FcvtLuDEmitter<Gp, Fp, U2> for Assembler<'_> {
    fn fcvt_lu_d(&mut self, rd: Gp, rs1: Fp, rm: U2) {
        self.emit_n(
            Opcode::FCVTLUD as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> FcvtLuHEmitter<Gp, Fp, U2> for Assembler<'_> {
    fn fcvt_lu_h(&mut self, rd: Gp, rs1: Fp, rm: U2) {
        self.emit_n(
            Opcode::FCVTLUH as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> FcvtLuQEmitter<Gp, Fp, U2> for Assembler<'_> {
    fn fcvt_lu_q(&mut self, rd: Gp, rs1: Fp, rm: U2) {
        self.emit_n(
            Opcode::FCVTLUQ as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> FcvtLuSEmitter<Gp, Fp, U2> for Assembler<'_> {
    fn fcvt_lu_s(&mut self, rd: Gp, rs1: Fp, rm: U2) {
        self.emit_n(
            Opcode::FCVTLUS as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> FcvtQDEmitter<Fp, Fp, U2> for Assembler<'_> {
    fn fcvt_q_d(&mut self, rd: Fp, rs1: Fp, rm: U2) {
        self.emit_n(
            Opcode::FCVTQD as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> FcvtQHEmitter<Fp, Fp, U2> for Assembler<'_> {
    fn fcvt_q_h(&mut self, rd: Fp, rs1: Fp, rm: U2) {
        self.emit_n(
            Opcode::FCVTQH as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> FcvtQLEmitter<Fp, Gp, U2> for Assembler<'_> {
    fn fcvt_q_l(&mut self, rd: Fp, rs1: Gp, rm: U2) {
        self.emit_n(
            Opcode::FCVTQL as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> FcvtQLuEmitter<Fp, Gp, U2> for Assembler<'_> {
    fn fcvt_q_lu(&mut self, rd: Fp, rs1: Gp, rm: U2) {
        self.emit_n(
            Opcode::FCVTQLU as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> FcvtQSEmitter<Fp, Fp, U2> for Assembler<'_> {
    fn fcvt_q_s(&mut self, rd: Fp, rs1: Fp, rm: U2) {
        self.emit_n(
            Opcode::FCVTQS as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> FcvtQWEmitter<Fp, Gp, U2> for Assembler<'_> {
    fn fcvt_q_w(&mut self, rd: Fp, rs1: Gp, rm: U2) {
        self.emit_n(
            Opcode::FCVTQW as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> FcvtQWuEmitter<Fp, Gp, U2> for Assembler<'_> {
    fn fcvt_q_wu(&mut self, rd: Fp, rs1: Gp, rm: U2) {
        self.emit_n(
            Opcode::FCVTQWU as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> FcvtSBf16Emitter<Fp, Fp, U2> for Assembler<'_> {
    fn fcvt_s_bf16(&mut self, rd: Fp, rs1: Fp, rm: U2) {
        self.emit_n(
            Opcode::FCVTSBF16 as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> FcvtSDEmitter<Fp, Fp, U2> for Assembler<'_> {
    fn fcvt_s_d(&mut self, rd: Fp, rs1: Fp, rm: U2) {
        self.emit_n(
            Opcode::FCVTSD as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> FcvtSHEmitter<Fp, Fp, U2> for Assembler<'_> {
    fn fcvt_s_h(&mut self, rd: Fp, rs1: Fp, rm: U2) {
        self.emit_n(
            Opcode::FCVTSH as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> FcvtSLEmitter<Fp, Gp, U2> for Assembler<'_> {
    fn fcvt_s_l(&mut self, rd: Fp, rs1: Gp, rm: U2) {
        self.emit_n(
            Opcode::FCVTSL as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> FcvtSLuEmitter<Fp, Gp, U2> for Assembler<'_> {
    fn fcvt_s_lu(&mut self, rd: Fp, rs1: Gp, rm: U2) {
        self.emit_n(
            Opcode::FCVTSLU as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> FcvtSQEmitter<Fp, Fp, U2> for Assembler<'_> {
    fn fcvt_s_q(&mut self, rd: Fp, rs1: Fp, rm: U2) {
        self.emit_n(
            Opcode::FCVTSQ as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> FcvtSWEmitter<Fp, Gp, U2> for Assembler<'_> {
    fn fcvt_s_w(&mut self, rd: Fp, rs1: Gp, rm: U2) {
        self.emit_n(
            Opcode::FCVTSW as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> FcvtSWuEmitter<Fp, Gp, U2> for Assembler<'_> {
    fn fcvt_s_wu(&mut self, rd: Fp, rs1: Gp, rm: U2) {
        self.emit_n(
            Opcode::FCVTSWU as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> FcvtWDEmitter<Gp, Fp, U2> for Assembler<'_> {
    fn fcvt_w_d(&mut self, rd: Gp, rs1: Fp, rm: U2) {
        self.emit_n(
            Opcode::FCVTWD as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> FcvtWHEmitter<Gp, Fp, U2> for Assembler<'_> {
    fn fcvt_w_h(&mut self, rd: Gp, rs1: Fp, rm: U2) {
        self.emit_n(
            Opcode::FCVTWH as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> FcvtWQEmitter<Gp, Fp, U2> for Assembler<'_> {
    fn fcvt_w_q(&mut self, rd: Gp, rs1: Fp, rm: U2) {
        self.emit_n(
            Opcode::FCVTWQ as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> FcvtWSEmitter<Gp, Fp, U2> for Assembler<'_> {
    fn fcvt_w_s(&mut self, rd: Gp, rs1: Fp, rm: U2) {
        self.emit_n(
            Opcode::FCVTWS as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> FcvtWuDEmitter<Gp, Fp, U2> for Assembler<'_> {
    fn fcvt_wu_d(&mut self, rd: Gp, rs1: Fp, rm: U2) {
        self.emit_n(
            Opcode::FCVTWUD as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> FcvtWuHEmitter<Gp, Fp, U2> for Assembler<'_> {
    fn fcvt_wu_h(&mut self, rd: Gp, rs1: Fp, rm: U2) {
        self.emit_n(
            Opcode::FCVTWUH as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> FcvtWuQEmitter<Gp, Fp, U2> for Assembler<'_> {
    fn fcvt_wu_q(&mut self, rd: Gp, rs1: Fp, rm: U2) {
        self.emit_n(
            Opcode::FCVTWUQ as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> FcvtWuSEmitter<Gp, Fp, U2> for Assembler<'_> {
    fn fcvt_wu_s(&mut self, rd: Gp, rs1: Fp, rm: U2) {
        self.emit_n(
            Opcode::FCVTWUS as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl FcvtmodWDEmitter<Gp, Fp> for Assembler<'_> {
    fn fcvtmod_w_d(&mut self, rd: Gp, rs1: Fp) {
        self.emit_n(
            Opcode::FCVTMODWD as i64,
            &[rd.as_operand(), rs1.as_operand()],
        );
    }
}

impl<U3: Into<Imm>> FdivDEmitter<Fp, Fp, Fp, U3> for Assembler<'_> {
    fn fdiv_d(&mut self, rd: Fp, rs1: Fp, rs2: Fp, rm: U3) {
        self.emit_n(
            Opcode::FDIVD as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> FdivHEmitter<Fp, Fp, Fp, U3> for Assembler<'_> {
    fn fdiv_h(&mut self, rd: Fp, rs1: Fp, rs2: Fp, rm: U3) {
        self.emit_n(
            Opcode::FDIVH as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> FdivQEmitter<Fp, Fp, Fp, U3> for Assembler<'_> {
    fn fdiv_q(&mut self, rd: Fp, rs1: Fp, rs2: Fp, rm: U3) {
        self.emit_n(
            Opcode::FDIVQ as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> FdivSEmitter<Fp, Fp, Fp, U3> for Assembler<'_> {
    fn fdiv_s(&mut self, rd: Fp, rs1: Fp, rs2: Fp, rm: U3) {
        self.emit_n(
            Opcode::FDIVS as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U0: Into<Imm>, U1: Into<Imm>, U2: Into<Imm>, U3: Into<Imm>, U4: Into<Imm>>
    FenceEmitter<U0, U1, U2, U3, U4> for Assembler<'_>
{
    fn fence(&mut self, fm: U0, pred: U1, succ: U2, rs1: U3, rd: U4) {
        self.emit_n(
            Opcode::FENCE as i64,
            &[
                Into::<Imm>::into(fm).as_operand(),
                Into::<Imm>::into(pred).as_operand(),
                Into::<Imm>::into(succ).as_operand(),
                Into::<Imm>::into(rs1).as_operand(),
                Into::<Imm>::into(rd).as_operand(),
            ],
        );
    }
}

impl FenceIEmitter for Assembler<'_> {
    fn fence_i(&mut self) {
        self.emit_n(Opcode::FENCEI as i64, &[]);
    }
}

impl FenceTsoEmitter for Assembler<'_> {
    fn fence_tso(&mut self) {
        self.emit_n(Opcode::FENCETSO as i64, &[]);
    }
}

impl FeqDEmitter<Gp, Fp, Fp> for Assembler<'_> {
    fn feq_d(&mut self, rd: Gp, rs1: Fp, rs2: Fp) {
        self.emit_n(
            Opcode::FEQD as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl FeqHEmitter<Gp, Fp, Fp> for Assembler<'_> {
    fn feq_h(&mut self, rd: Gp, rs1: Fp, rs2: Fp) {
        self.emit_n(
            Opcode::FEQH as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl FeqQEmitter<Gp, Fp, Fp> for Assembler<'_> {
    fn feq_q(&mut self, rd: Gp, rs1: Fp, rs2: Fp) {
        self.emit_n(
            Opcode::FEQQ as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl FeqSEmitter<Gp, Fp, Fp> for Assembler<'_> {
    fn feq_s(&mut self, rd: Gp, rs1: Fp, rs2: Fp) {
        self.emit_n(
            Opcode::FEQS as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl<U2: Into<Imm>> FldEmitter<Fp, Gp, U2> for Assembler<'_> {
    fn fld(&mut self, rd: Fp, rs1: Gp, imm: U2) {
        self.emit_n(
            Opcode::FLD as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(imm).as_operand(),
            ],
        );
    }
}

impl FleDEmitter<Gp, Fp, Fp> for Assembler<'_> {
    fn fle_d(&mut self, rd: Gp, rs1: Fp, rs2: Fp) {
        self.emit_n(
            Opcode::FLED as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl FleHEmitter<Gp, Fp, Fp> for Assembler<'_> {
    fn fle_h(&mut self, rd: Gp, rs1: Fp, rs2: Fp) {
        self.emit_n(
            Opcode::FLEH as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl FleQEmitter<Gp, Fp, Fp> for Assembler<'_> {
    fn fle_q(&mut self, rd: Gp, rs1: Fp, rs2: Fp) {
        self.emit_n(
            Opcode::FLEQ as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl FleSEmitter<Gp, Fp, Fp> for Assembler<'_> {
    fn fle_s(&mut self, rd: Gp, rs1: Fp, rs2: Fp) {
        self.emit_n(
            Opcode::FLES as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl FleqDEmitter<Fp, Fp, Fp> for Assembler<'_> {
    fn fleq_d(&mut self, rd: Fp, rs1: Fp, rs2: Fp) {
        self.emit_n(
            Opcode::FLEQD as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl FleqHEmitter<Fp, Fp, Fp> for Assembler<'_> {
    fn fleq_h(&mut self, rd: Fp, rs1: Fp, rs2: Fp) {
        self.emit_n(
            Opcode::FLEQH as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl FleqQEmitter<Fp, Fp, Fp> for Assembler<'_> {
    fn fleq_q(&mut self, rd: Fp, rs1: Fp, rs2: Fp) {
        self.emit_n(
            Opcode::FLEQQ as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl FleqSEmitter<Fp, Fp, Fp> for Assembler<'_> {
    fn fleq_s(&mut self, rd: Fp, rs1: Fp, rs2: Fp) {
        self.emit_n(
            Opcode::FLEQS as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl<U2: Into<Imm>> FlhEmitter<Fp, Gp, U2> for Assembler<'_> {
    fn flh(&mut self, rd: Fp, rs1: Gp, imm: U2) {
        self.emit_n(
            Opcode::FLH as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(imm).as_operand(),
            ],
        );
    }
}

impl FliDEmitter<Fp, Fp> for Assembler<'_> {
    fn fli_d(&mut self, rd: Fp, rs1: Fp) {
        self.emit_n(Opcode::FLID as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl FliHEmitter<Fp, Fp> for Assembler<'_> {
    fn fli_h(&mut self, rd: Fp, rs1: Fp) {
        self.emit_n(Opcode::FLIH as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl FliQEmitter<Fp, Fp> for Assembler<'_> {
    fn fli_q(&mut self, rd: Fp, rs1: Fp) {
        self.emit_n(Opcode::FLIQ as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl FliSEmitter<Fp, Fp> for Assembler<'_> {
    fn fli_s(&mut self, rd: Fp, rs1: Fp) {
        self.emit_n(Opcode::FLIS as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl<U2: Into<Imm>> FlqEmitter<Fp, Gp, U2> for Assembler<'_> {
    fn flq(&mut self, rd: Fp, rs1: Gp, imm: U2) {
        self.emit_n(
            Opcode::FLQ as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(imm).as_operand(),
            ],
        );
    }
}

impl FltDEmitter<Gp, Fp, Fp> for Assembler<'_> {
    fn flt_d(&mut self, rd: Gp, rs1: Fp, rs2: Fp) {
        self.emit_n(
            Opcode::FLTD as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl FltHEmitter<Gp, Fp, Fp> for Assembler<'_> {
    fn flt_h(&mut self, rd: Gp, rs1: Fp, rs2: Fp) {
        self.emit_n(
            Opcode::FLTH as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl FltQEmitter<Gp, Fp, Fp> for Assembler<'_> {
    fn flt_q(&mut self, rd: Gp, rs1: Fp, rs2: Fp) {
        self.emit_n(
            Opcode::FLTQ as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl FltSEmitter<Gp, Fp, Fp> for Assembler<'_> {
    fn flt_s(&mut self, rd: Gp, rs1: Fp, rs2: Fp) {
        self.emit_n(
            Opcode::FLTS as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl FltqDEmitter<Fp, Fp, Fp> for Assembler<'_> {
    fn fltq_d(&mut self, rd: Fp, rs1: Fp, rs2: Fp) {
        self.emit_n(
            Opcode::FLTQD as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl FltqHEmitter<Fp, Fp, Fp> for Assembler<'_> {
    fn fltq_h(&mut self, rd: Fp, rs1: Fp, rs2: Fp) {
        self.emit_n(
            Opcode::FLTQH as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl FltqQEmitter<Fp, Fp, Fp> for Assembler<'_> {
    fn fltq_q(&mut self, rd: Fp, rs1: Fp, rs2: Fp) {
        self.emit_n(
            Opcode::FLTQQ as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl FltqSEmitter<Fp, Fp, Fp> for Assembler<'_> {
    fn fltq_s(&mut self, rd: Fp, rs1: Fp, rs2: Fp) {
        self.emit_n(
            Opcode::FLTQS as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl<U2: Into<Imm>> FlwEmitter<Fp, Gp, U2> for Assembler<'_> {
    fn flw(&mut self, rd: Fp, rs1: Gp, imm: U2) {
        self.emit_n(
            Opcode::FLW as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(imm).as_operand(),
            ],
        );
    }
}

impl<U4: Into<Imm>> FmaddDEmitter<Fp, Fp, Fp, Fp, U4> for Assembler<'_> {
    fn fmadd_d(&mut self, rd: Fp, rs1: Fp, rs2: Fp, rs3: Fp, rm: U4) {
        self.emit_n(
            Opcode::FMADDD as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                rs3.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U4: Into<Imm>> FmaddHEmitter<Fp, Fp, Fp, Fp, U4> for Assembler<'_> {
    fn fmadd_h(&mut self, rd: Fp, rs1: Fp, rs2: Fp, rs3: Fp, rm: U4) {
        self.emit_n(
            Opcode::FMADDH as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                rs3.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U4: Into<Imm>> FmaddQEmitter<Fp, Fp, Fp, Fp, U4> for Assembler<'_> {
    fn fmadd_q(&mut self, rd: Fp, rs1: Fp, rs2: Fp, rs3: Fp, rm: U4) {
        self.emit_n(
            Opcode::FMADDQ as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                rs3.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U4: Into<Imm>> FmaddSEmitter<Fp, Fp, Fp, Fp, U4> for Assembler<'_> {
    fn fmadd_s(&mut self, rd: Fp, rs1: Fp, rs2: Fp, rs3: Fp, rm: U4) {
        self.emit_n(
            Opcode::FMADDS as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                rs3.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl FmaxDEmitter<Fp, Fp, Fp> for Assembler<'_> {
    fn fmax_d(&mut self, rd: Fp, rs1: Fp, rs2: Fp) {
        self.emit_n(
            Opcode::FMAXD as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl FmaxHEmitter<Fp, Fp, Fp> for Assembler<'_> {
    fn fmax_h(&mut self, rd: Fp, rs1: Fp, rs2: Fp) {
        self.emit_n(
            Opcode::FMAXH as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl FmaxQEmitter<Fp, Fp, Fp> for Assembler<'_> {
    fn fmax_q(&mut self, rd: Fp, rs1: Fp, rs2: Fp) {
        self.emit_n(
            Opcode::FMAXQ as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl FmaxSEmitter<Fp, Fp, Fp> for Assembler<'_> {
    fn fmax_s(&mut self, rd: Fp, rs1: Fp, rs2: Fp) {
        self.emit_n(
            Opcode::FMAXS as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl FmaxmDEmitter<Fp, Fp, Fp> for Assembler<'_> {
    fn fmaxm_d(&mut self, rd: Fp, rs1: Fp, rs2: Fp) {
        self.emit_n(
            Opcode::FMAXMD as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl FmaxmHEmitter<Fp, Fp, Fp> for Assembler<'_> {
    fn fmaxm_h(&mut self, rd: Fp, rs1: Fp, rs2: Fp) {
        self.emit_n(
            Opcode::FMAXMH as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl FmaxmQEmitter<Fp, Fp, Fp> for Assembler<'_> {
    fn fmaxm_q(&mut self, rd: Fp, rs1: Fp, rs2: Fp) {
        self.emit_n(
            Opcode::FMAXMQ as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl FmaxmSEmitter<Fp, Fp, Fp> for Assembler<'_> {
    fn fmaxm_s(&mut self, rd: Fp, rs1: Fp, rs2: Fp) {
        self.emit_n(
            Opcode::FMAXMS as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl FminDEmitter<Fp, Fp, Fp> for Assembler<'_> {
    fn fmin_d(&mut self, rd: Fp, rs1: Fp, rs2: Fp) {
        self.emit_n(
            Opcode::FMIND as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl FminHEmitter<Fp, Fp, Fp> for Assembler<'_> {
    fn fmin_h(&mut self, rd: Fp, rs1: Fp, rs2: Fp) {
        self.emit_n(
            Opcode::FMINH as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl FminQEmitter<Fp, Fp, Fp> for Assembler<'_> {
    fn fmin_q(&mut self, rd: Fp, rs1: Fp, rs2: Fp) {
        self.emit_n(
            Opcode::FMINQ as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl FminSEmitter<Fp, Fp, Fp> for Assembler<'_> {
    fn fmin_s(&mut self, rd: Fp, rs1: Fp, rs2: Fp) {
        self.emit_n(
            Opcode::FMINS as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl FminmDEmitter<Fp, Fp, Fp> for Assembler<'_> {
    fn fminm_d(&mut self, rd: Fp, rs1: Fp, rs2: Fp) {
        self.emit_n(
            Opcode::FMINMD as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl FminmHEmitter<Fp, Fp, Fp> for Assembler<'_> {
    fn fminm_h(&mut self, rd: Fp, rs1: Fp, rs2: Fp) {
        self.emit_n(
            Opcode::FMINMH as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl FminmQEmitter<Fp, Fp, Fp> for Assembler<'_> {
    fn fminm_q(&mut self, rd: Fp, rs1: Fp, rs2: Fp) {
        self.emit_n(
            Opcode::FMINMQ as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl FminmSEmitter<Fp, Fp, Fp> for Assembler<'_> {
    fn fminm_s(&mut self, rd: Fp, rs1: Fp, rs2: Fp) {
        self.emit_n(
            Opcode::FMINMS as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl<U4: Into<Imm>> FmsubDEmitter<Fp, Fp, Fp, Fp, U4> for Assembler<'_> {
    fn fmsub_d(&mut self, rd: Fp, rs1: Fp, rs2: Fp, rs3: Fp, rm: U4) {
        self.emit_n(
            Opcode::FMSUBD as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                rs3.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U4: Into<Imm>> FmsubHEmitter<Fp, Fp, Fp, Fp, U4> for Assembler<'_> {
    fn fmsub_h(&mut self, rd: Fp, rs1: Fp, rs2: Fp, rs3: Fp, rm: U4) {
        self.emit_n(
            Opcode::FMSUBH as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                rs3.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U4: Into<Imm>> FmsubQEmitter<Fp, Fp, Fp, Fp, U4> for Assembler<'_> {
    fn fmsub_q(&mut self, rd: Fp, rs1: Fp, rs2: Fp, rs3: Fp, rm: U4) {
        self.emit_n(
            Opcode::FMSUBQ as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                rs3.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U4: Into<Imm>> FmsubSEmitter<Fp, Fp, Fp, Fp, U4> for Assembler<'_> {
    fn fmsub_s(&mut self, rd: Fp, rs1: Fp, rs2: Fp, rs3: Fp, rm: U4) {
        self.emit_n(
            Opcode::FMSUBS as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                rs3.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> FmulDEmitter<Fp, Fp, Fp, U3> for Assembler<'_> {
    fn fmul_d(&mut self, rd: Fp, rs1: Fp, rs2: Fp, rm: U3) {
        self.emit_n(
            Opcode::FMULD as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> FmulHEmitter<Fp, Fp, Fp, U3> for Assembler<'_> {
    fn fmul_h(&mut self, rd: Fp, rs1: Fp, rs2: Fp, rm: U3) {
        self.emit_n(
            Opcode::FMULH as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> FmulQEmitter<Fp, Fp, Fp, U3> for Assembler<'_> {
    fn fmul_q(&mut self, rd: Fp, rs1: Fp, rs2: Fp, rm: U3) {
        self.emit_n(
            Opcode::FMULQ as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> FmulSEmitter<Fp, Fp, Fp, U3> for Assembler<'_> {
    fn fmul_s(&mut self, rd: Fp, rs1: Fp, rs2: Fp, rm: U3) {
        self.emit_n(
            Opcode::FMULS as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl FmvDEmitter<Fp, Fp, Fp> for Assembler<'_> {
    fn fmv_d(&mut self, rd: Fp, rs1: Fp, rs2: Fp) {
        self.emit_n(
            Opcode::FMVD as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl FmvDXEmitter<Fp, Gp> for Assembler<'_> {
    fn fmv_d_x(&mut self, rd: Fp, rs1: Gp) {
        self.emit_n(Opcode::FMVDX as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl FmvHEmitter<Fp, Fp, Fp> for Assembler<'_> {
    fn fmv_h(&mut self, rd: Fp, rs1: Fp, rs2: Fp) {
        self.emit_n(
            Opcode::FMVH as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl FmvHXEmitter<Fp, Gp> for Assembler<'_> {
    fn fmv_h_x(&mut self, rd: Fp, rs1: Gp) {
        self.emit_n(Opcode::FMVHX as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl FmvQEmitter<Fp, Fp, Fp> for Assembler<'_> {
    fn fmv_q(&mut self, rd: Fp, rs1: Fp, rs2: Fp) {
        self.emit_n(
            Opcode::FMVQ as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl FmvSEmitter<Fp, Fp, Fp> for Assembler<'_> {
    fn fmv_s(&mut self, rd: Fp, rs1: Fp, rs2: Fp) {
        self.emit_n(
            Opcode::FMVS as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl FmvSXEmitter<Fp, Gp> for Assembler<'_> {
    fn fmv_s_x(&mut self, rd: Fp, rs1: Gp) {
        self.emit_n(Opcode::FMVSX as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl FmvWXEmitter<Fp, Gp> for Assembler<'_> {
    fn fmv_w_x(&mut self, rd: Fp, rs1: Gp) {
        self.emit_n(Opcode::FMVWX as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl FmvXDEmitter<Gp, Fp> for Assembler<'_> {
    fn fmv_x_d(&mut self, rd: Gp, rs1: Fp) {
        self.emit_n(Opcode::FMVXD as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl FmvXHEmitter<Gp, Fp> for Assembler<'_> {
    fn fmv_x_h(&mut self, rd: Gp, rs1: Fp) {
        self.emit_n(Opcode::FMVXH as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl FmvXSEmitter<Gp, Fp> for Assembler<'_> {
    fn fmv_x_s(&mut self, rd: Gp, rs1: Fp) {
        self.emit_n(Opcode::FMVXS as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl FmvXWEmitter<Gp, Fp> for Assembler<'_> {
    fn fmv_x_w(&mut self, rd: Gp, rs1: Fp) {
        self.emit_n(Opcode::FMVXW as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl FmvhXDEmitter<Gp, Fp> for Assembler<'_> {
    fn fmvh_x_d(&mut self, rd: Gp, rs1: Fp) {
        self.emit_n(Opcode::FMVHXD as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl FmvhXQEmitter<Gp, Fp> for Assembler<'_> {
    fn fmvh_x_q(&mut self, rd: Gp, rs1: Fp) {
        self.emit_n(Opcode::FMVHXQ as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl FmvpDXEmitter<Fp, Gp, Gp> for Assembler<'_> {
    fn fmvp_d_x(&mut self, rd: Fp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::FMVPDX as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl FmvpQXEmitter<Fp, Gp, Gp> for Assembler<'_> {
    fn fmvp_q_x(&mut self, rd: Fp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::FMVPQX as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl FnegDEmitter<Fp, Fp, Fp> for Assembler<'_> {
    fn fneg_d(&mut self, rd: Fp, rs1: Fp, rs2: Fp) {
        self.emit_n(
            Opcode::FNEGD as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl FnegHEmitter<Fp, Fp, Fp> for Assembler<'_> {
    fn fneg_h(&mut self, rd: Fp, rs1: Fp, rs2: Fp) {
        self.emit_n(
            Opcode::FNEGH as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl FnegQEmitter<Fp, Fp, Fp> for Assembler<'_> {
    fn fneg_q(&mut self, rd: Fp, rs1: Fp, rs2: Fp) {
        self.emit_n(
            Opcode::FNEGQ as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl FnegSEmitter<Fp, Fp, Fp> for Assembler<'_> {
    fn fneg_s(&mut self, rd: Fp, rs1: Fp, rs2: Fp) {
        self.emit_n(
            Opcode::FNEGS as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl<U4: Into<Imm>> FnmaddDEmitter<Fp, Fp, Fp, Fp, U4> for Assembler<'_> {
    fn fnmadd_d(&mut self, rd: Fp, rs1: Fp, rs2: Fp, rs3: Fp, rm: U4) {
        self.emit_n(
            Opcode::FNMADDD as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                rs3.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U4: Into<Imm>> FnmaddHEmitter<Fp, Fp, Fp, Fp, U4> for Assembler<'_> {
    fn fnmadd_h(&mut self, rd: Fp, rs1: Fp, rs2: Fp, rs3: Fp, rm: U4) {
        self.emit_n(
            Opcode::FNMADDH as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                rs3.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U4: Into<Imm>> FnmaddQEmitter<Fp, Fp, Fp, Fp, U4> for Assembler<'_> {
    fn fnmadd_q(&mut self, rd: Fp, rs1: Fp, rs2: Fp, rs3: Fp, rm: U4) {
        self.emit_n(
            Opcode::FNMADDQ as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                rs3.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U4: Into<Imm>> FnmaddSEmitter<Fp, Fp, Fp, Fp, U4> for Assembler<'_> {
    fn fnmadd_s(&mut self, rd: Fp, rs1: Fp, rs2: Fp, rs3: Fp, rm: U4) {
        self.emit_n(
            Opcode::FNMADDS as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                rs3.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U4: Into<Imm>> FnmsubDEmitter<Fp, Fp, Fp, Fp, U4> for Assembler<'_> {
    fn fnmsub_d(&mut self, rd: Fp, rs1: Fp, rs2: Fp, rs3: Fp, rm: U4) {
        self.emit_n(
            Opcode::FNMSUBD as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                rs3.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U4: Into<Imm>> FnmsubHEmitter<Fp, Fp, Fp, Fp, U4> for Assembler<'_> {
    fn fnmsub_h(&mut self, rd: Fp, rs1: Fp, rs2: Fp, rs3: Fp, rm: U4) {
        self.emit_n(
            Opcode::FNMSUBH as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                rs3.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U4: Into<Imm>> FnmsubQEmitter<Fp, Fp, Fp, Fp, U4> for Assembler<'_> {
    fn fnmsub_q(&mut self, rd: Fp, rs1: Fp, rs2: Fp, rs3: Fp, rm: U4) {
        self.emit_n(
            Opcode::FNMSUBQ as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                rs3.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U4: Into<Imm>> FnmsubSEmitter<Fp, Fp, Fp, Fp, U4> for Assembler<'_> {
    fn fnmsub_s(&mut self, rd: Fp, rs1: Fp, rs2: Fp, rs3: Fp, rm: U4) {
        self.emit_n(
            Opcode::FNMSUBS as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                rs3.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl FrcsrEmitter<Gp> for Assembler<'_> {
    fn frcsr(&mut self, rd: Gp) {
        self.emit_n(Opcode::FRCSR as i64, &[rd.as_operand()]);
    }
}

impl FrflagsEmitter<Gp> for Assembler<'_> {
    fn frflags(&mut self, rd: Gp) {
        self.emit_n(Opcode::FRFLAGS as i64, &[rd.as_operand()]);
    }
}

impl<U2: Into<Imm>> FroundDEmitter<Fp, Fp, U2> for Assembler<'_> {
    fn fround_d(&mut self, rd: Fp, rs1: Fp, rm: U2) {
        self.emit_n(
            Opcode::FROUNDD as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> FroundHEmitter<Fp, Fp, U2> for Assembler<'_> {
    fn fround_h(&mut self, rd: Fp, rs1: Fp, rm: U2) {
        self.emit_n(
            Opcode::FROUNDH as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> FroundQEmitter<Fp, Fp, U2> for Assembler<'_> {
    fn fround_q(&mut self, rd: Fp, rs1: Fp, rm: U2) {
        self.emit_n(
            Opcode::FROUNDQ as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> FroundSEmitter<Fp, Fp, U2> for Assembler<'_> {
    fn fround_s(&mut self, rd: Fp, rs1: Fp, rm: U2) {
        self.emit_n(
            Opcode::FROUNDS as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> FroundnxDEmitter<Fp, Fp, U2> for Assembler<'_> {
    fn froundnx_d(&mut self, rd: Fp, rs1: Fp, rm: U2) {
        self.emit_n(
            Opcode::FROUNDNXD as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> FroundnxHEmitter<Fp, Fp, U2> for Assembler<'_> {
    fn froundnx_h(&mut self, rd: Fp, rs1: Fp, rm: U2) {
        self.emit_n(
            Opcode::FROUNDNXH as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> FroundnxQEmitter<Fp, Fp, U2> for Assembler<'_> {
    fn froundnx_q(&mut self, rd: Fp, rs1: Fp, rm: U2) {
        self.emit_n(
            Opcode::FROUNDNXQ as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> FroundnxSEmitter<Fp, Fp, U2> for Assembler<'_> {
    fn froundnx_s(&mut self, rd: Fp, rs1: Fp, rm: U2) {
        self.emit_n(
            Opcode::FROUNDNXS as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl FrrmEmitter<Gp> for Assembler<'_> {
    fn frrm(&mut self, rd: Gp) {
        self.emit_n(Opcode::FRRM as i64, &[rd.as_operand()]);
    }
}

impl FscsrEmitter<Gp, Gp> for Assembler<'_> {
    fn fscsr(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::FSCSR as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl<U2: Into<Imm>> FsdEmitter<Gp, Fp, U2> for Assembler<'_> {
    fn fsd(&mut self, rs1: Gp, rs2: Fp, imm: U2) {
        self.emit_n(
            Opcode::FSD as i64,
            &[
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(imm).as_operand(),
            ],
        );
    }
}

impl FsflagsEmitter<Gp, Gp> for Assembler<'_> {
    fn fsflags(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::FSFLAGS as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl<U1: Into<Imm>> FsflagsiEmitter<Gp, U1> for Assembler<'_> {
    fn fsflagsi(&mut self, rd: Gp, zimm5: U1) {
        self.emit_n(
            Opcode::FSFLAGSI as i64,
            &[rd.as_operand(), Into::<Imm>::into(zimm5).as_operand()],
        );
    }
}

impl FsgnjDEmitter<Fp, Fp, Fp> for Assembler<'_> {
    fn fsgnj_d(&mut self, rd: Fp, rs1: Fp, rs2: Fp) {
        self.emit_n(
            Opcode::FSGNJD as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl FsgnjHEmitter<Fp, Fp, Fp> for Assembler<'_> {
    fn fsgnj_h(&mut self, rd: Fp, rs1: Fp, rs2: Fp) {
        self.emit_n(
            Opcode::FSGNJH as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl FsgnjQEmitter<Fp, Fp, Fp> for Assembler<'_> {
    fn fsgnj_q(&mut self, rd: Fp, rs1: Fp, rs2: Fp) {
        self.emit_n(
            Opcode::FSGNJQ as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl FsgnjSEmitter<Fp, Fp, Fp> for Assembler<'_> {
    fn fsgnj_s(&mut self, rd: Fp, rs1: Fp, rs2: Fp) {
        self.emit_n(
            Opcode::FSGNJS as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl FsgnjnDEmitter<Fp, Fp, Fp> for Assembler<'_> {
    fn fsgnjn_d(&mut self, rd: Fp, rs1: Fp, rs2: Fp) {
        self.emit_n(
            Opcode::FSGNJND as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl FsgnjnHEmitter<Fp, Fp, Fp> for Assembler<'_> {
    fn fsgnjn_h(&mut self, rd: Fp, rs1: Fp, rs2: Fp) {
        self.emit_n(
            Opcode::FSGNJNH as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl FsgnjnQEmitter<Fp, Fp, Fp> for Assembler<'_> {
    fn fsgnjn_q(&mut self, rd: Fp, rs1: Fp, rs2: Fp) {
        self.emit_n(
            Opcode::FSGNJNQ as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl FsgnjnSEmitter<Fp, Fp, Fp> for Assembler<'_> {
    fn fsgnjn_s(&mut self, rd: Fp, rs1: Fp, rs2: Fp) {
        self.emit_n(
            Opcode::FSGNJNS as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl FsgnjxDEmitter<Fp, Fp, Fp> for Assembler<'_> {
    fn fsgnjx_d(&mut self, rd: Fp, rs1: Fp, rs2: Fp) {
        self.emit_n(
            Opcode::FSGNJXD as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl FsgnjxHEmitter<Fp, Fp, Fp> for Assembler<'_> {
    fn fsgnjx_h(&mut self, rd: Fp, rs1: Fp, rs2: Fp) {
        self.emit_n(
            Opcode::FSGNJXH as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl FsgnjxQEmitter<Fp, Fp, Fp> for Assembler<'_> {
    fn fsgnjx_q(&mut self, rd: Fp, rs1: Fp, rs2: Fp) {
        self.emit_n(
            Opcode::FSGNJXQ as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl FsgnjxSEmitter<Fp, Fp, Fp> for Assembler<'_> {
    fn fsgnjx_s(&mut self, rd: Fp, rs1: Fp, rs2: Fp) {
        self.emit_n(
            Opcode::FSGNJXS as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl<U2: Into<Imm>> FshEmitter<Gp, Fp, U2> for Assembler<'_> {
    fn fsh(&mut self, rs1: Gp, rs2: Fp, imm: U2) {
        self.emit_n(
            Opcode::FSH as i64,
            &[
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(imm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> FsqEmitter<Gp, Fp, U2> for Assembler<'_> {
    fn fsq(&mut self, rs1: Gp, rs2: Fp, imm: U2) {
        self.emit_n(
            Opcode::FSQ as i64,
            &[
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(imm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> FsqrtDEmitter<Fp, Fp, U2> for Assembler<'_> {
    fn fsqrt_d(&mut self, rd: Fp, rs1: Fp, rm: U2) {
        self.emit_n(
            Opcode::FSQRTD as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> FsqrtHEmitter<Fp, Fp, U2> for Assembler<'_> {
    fn fsqrt_h(&mut self, rd: Fp, rs1: Fp, rm: U2) {
        self.emit_n(
            Opcode::FSQRTH as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> FsqrtQEmitter<Fp, Fp, U2> for Assembler<'_> {
    fn fsqrt_q(&mut self, rd: Fp, rs1: Fp, rm: U2) {
        self.emit_n(
            Opcode::FSQRTQ as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> FsqrtSEmitter<Fp, Fp, U2> for Assembler<'_> {
    fn fsqrt_s(&mut self, rd: Fp, rs1: Fp, rm: U2) {
        self.emit_n(
            Opcode::FSQRTS as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl FsrmEmitter<Gp, Gp> for Assembler<'_> {
    fn fsrm(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::FSRM as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl<U1: Into<Imm>> FsrmiEmitter<Gp, U1> for Assembler<'_> {
    fn fsrmi(&mut self, rd: Gp, zimm5: U1) {
        self.emit_n(
            Opcode::FSRMI as i64,
            &[rd.as_operand(), Into::<Imm>::into(zimm5).as_operand()],
        );
    }
}

impl<U3: Into<Imm>> FsubDEmitter<Fp, Fp, Fp, U3> for Assembler<'_> {
    fn fsub_d(&mut self, rd: Fp, rs1: Fp, rs2: Fp, rm: U3) {
        self.emit_n(
            Opcode::FSUBD as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> FsubHEmitter<Fp, Fp, Fp, U3> for Assembler<'_> {
    fn fsub_h(&mut self, rd: Fp, rs1: Fp, rs2: Fp, rm: U3) {
        self.emit_n(
            Opcode::FSUBH as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> FsubQEmitter<Fp, Fp, Fp, U3> for Assembler<'_> {
    fn fsub_q(&mut self, rd: Fp, rs1: Fp, rs2: Fp, rm: U3) {
        self.emit_n(
            Opcode::FSUBQ as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> FsubSEmitter<Fp, Fp, Fp, U3> for Assembler<'_> {
    fn fsub_s(&mut self, rd: Fp, rs1: Fp, rs2: Fp, rm: U3) {
        self.emit_n(
            Opcode::FSUBS as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(rm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> FswEmitter<Gp, Fp, U2> for Assembler<'_> {
    fn fsw(&mut self, rs1: Gp, rs2: Fp, imm: U2) {
        self.emit_n(
            Opcode::FSW as i64,
            &[
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(imm).as_operand(),
            ],
        );
    }
}

impl HfenceGvmaEmitter<Gp, Gp> for Assembler<'_> {
    fn hfence_gvma(&mut self, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::HFENCEGVMA as i64,
            &[rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl HfenceVvmaEmitter<Gp, Gp> for Assembler<'_> {
    fn hfence_vvma(&mut self, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::HFENCEVVMA as i64,
            &[rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl HinvalGvmaEmitter<Gp, Gp> for Assembler<'_> {
    fn hinval_gvma(&mut self, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::HINVALGVMA as i64,
            &[rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl HinvalVvmaEmitter<Gp, Gp> for Assembler<'_> {
    fn hinval_vvma(&mut self, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::HINVALVVMA as i64,
            &[rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl HlvBEmitter<Gp, Gp> for Assembler<'_> {
    fn hlv_b(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::HLVB as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl HlvBuEmitter<Gp, Gp> for Assembler<'_> {
    fn hlv_bu(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::HLVBU as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl HlvDEmitter<Gp, Gp> for Assembler<'_> {
    fn hlv_d(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::HLVD as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl HlvHEmitter<Gp, Gp> for Assembler<'_> {
    fn hlv_h(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::HLVH as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl HlvHuEmitter<Gp, Gp> for Assembler<'_> {
    fn hlv_hu(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::HLVHU as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl HlvWEmitter<Gp, Gp> for Assembler<'_> {
    fn hlv_w(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::HLVW as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl HlvWuEmitter<Gp, Gp> for Assembler<'_> {
    fn hlv_wu(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::HLVWU as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl HlvxHuEmitter<Gp, Gp> for Assembler<'_> {
    fn hlvx_hu(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::HLVXHU as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl HlvxWuEmitter<Gp, Gp> for Assembler<'_> {
    fn hlvx_wu(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::HLVXWU as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl HsvBEmitter<Gp, Gp> for Assembler<'_> {
    fn hsv_b(&mut self, rs1: Gp, rs2: Gp) {
        self.emit_n(Opcode::HSVB as i64, &[rs1.as_operand(), rs2.as_operand()]);
    }
}

impl HsvDEmitter<Gp, Gp> for Assembler<'_> {
    fn hsv_d(&mut self, rs1: Gp, rs2: Gp) {
        self.emit_n(Opcode::HSVD as i64, &[rs1.as_operand(), rs2.as_operand()]);
    }
}

impl HsvHEmitter<Gp, Gp> for Assembler<'_> {
    fn hsv_h(&mut self, rs1: Gp, rs2: Gp) {
        self.emit_n(Opcode::HSVH as i64, &[rs1.as_operand(), rs2.as_operand()]);
    }
}

impl HsvWEmitter<Gp, Gp> for Assembler<'_> {
    fn hsv_w(&mut self, rs1: Gp, rs2: Gp) {
        self.emit_n(Opcode::HSVW as i64, &[rs1.as_operand(), rs2.as_operand()]);
    }
}

impl<U0: Into<Imm>> JEmitter<U0> for Assembler<'_> {
    fn j(&mut self, imm: U0) {
        self.emit_n(Opcode::J as i64, &[Into::<Imm>::into(imm).as_operand()]);
    }
}

impl JEmitter<Label> for Assembler<'_> {
    fn j(&mut self, imm: Label) {
        self.emit_n(Opcode::J as i64, &[imm.as_operand()]);
    }
}

impl<U1: Into<Imm>> JalEmitter<Gp, U1> for Assembler<'_> {
    fn jal(&mut self, rd: Gp, imm: U1) {
        self.emit_n(
            Opcode::JAL as i64,
            &[rd.as_operand(), Into::<Imm>::into(imm).as_operand()],
        );
    }
}

impl JalEmitter<Gp, Label> for Assembler<'_> {
    fn jal(&mut self, rd: Gp, imm: Label) {
        self.emit_n(Opcode::JAL as i64, &[rd.as_operand(), imm.as_operand()]);
    }
}

impl<U0: Into<Imm>> JalPseudoEmitter<U0> for Assembler<'_> {
    fn jal_pseudo(&mut self, imm: U0) {
        self.emit_n(
            Opcode::JALPSEUDO as i64,
            &[Into::<Imm>::into(imm).as_operand()],
        );
    }
}

impl JalPseudoEmitter<Label> for Assembler<'_> {
    fn jal_pseudo(&mut self, imm: Label) {
        self.emit_n(Opcode::JALPSEUDO as i64, &[imm.as_operand()]);
    }
}

impl<U2: Into<Imm>> JalrEmitter<Gp, Gp, U2> for Assembler<'_> {
    fn jalr(&mut self, rd: Gp, rs1: Gp, imm: U2) {
        self.emit_n(
            Opcode::JALR as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(imm).as_operand(),
            ],
        );
    }
}

impl JalrPseudoEmitter<Gp> for Assembler<'_> {
    fn jalr_pseudo(&mut self, rs1: Gp) {
        self.emit_n(Opcode::JALRPSEUDO as i64, &[rs1.as_operand()]);
    }
}

impl JrEmitter<Gp> for Assembler<'_> {
    fn jr(&mut self, rs1: Gp) {
        self.emit_n(Opcode::JR as i64, &[rs1.as_operand()]);
    }
}

impl<U2: Into<Imm>> LbEmitter<Gp, Gp, U2> for Assembler<'_> {
    fn lb(&mut self, rd: Gp, rs1: Gp, imm: U2) {
        self.emit_n(
            Opcode::LB as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(imm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> LbuEmitter<Gp, Gp, U2> for Assembler<'_> {
    fn lbu(&mut self, rd: Gp, rs1: Gp, imm: U2) {
        self.emit_n(
            Opcode::LBU as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(imm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> LdEmitter<Gp, Gp, U2> for Assembler<'_> {
    fn ld(&mut self, rd: Gp, rs1: Gp, imm: U2) {
        self.emit_n(
            Opcode::LD as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(imm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> LhEmitter<Gp, Gp, U2> for Assembler<'_> {
    fn lh(&mut self, rd: Gp, rs1: Gp, imm: U2) {
        self.emit_n(
            Opcode::LH as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(imm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> LhuEmitter<Gp, Gp, U2> for Assembler<'_> {
    fn lhu(&mut self, rd: Gp, rs1: Gp, imm: U2) {
        self.emit_n(
            Opcode::LHU as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(imm).as_operand(),
            ],
        );
    }
}

impl<U0: Into<Imm>> LpadEmitter<U0> for Assembler<'_> {
    fn lpad(&mut self, imm: U0) {
        self.emit_n(Opcode::LPAD as i64, &[Into::<Imm>::into(imm).as_operand()]);
    }
}

impl<U2: Into<Imm>, U3: Into<Imm>> LrDEmitter<Gp, Gp, U2, U3> for Assembler<'_> {
    fn lr_d(&mut self, rd: Gp, rs1: Gp, aq: U2, rl: U3) {
        self.emit_n(
            Opcode::LRD as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(aq).as_operand(),
                Into::<Imm>::into(rl).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>, U3: Into<Imm>> LrWEmitter<Gp, Gp, U2, U3> for Assembler<'_> {
    fn lr_w(&mut self, rd: Gp, rs1: Gp, aq: U2, rl: U3) {
        self.emit_n(
            Opcode::LRW as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(aq).as_operand(),
                Into::<Imm>::into(rl).as_operand(),
            ],
        );
    }
}

impl<U1: Into<Imm>> LuiEmitter<Gp, U1> for Assembler<'_> {
    fn lui(&mut self, rd: Gp, imm: U1) {
        self.emit_n(
            Opcode::LUI as i64,
            &[rd.as_operand(), Into::<Imm>::into(imm).as_operand()],
        );
    }
}

impl<U2: Into<Imm>> LwEmitter<Gp, Gp, U2> for Assembler<'_> {
    fn lw(&mut self, rd: Gp, rs1: Gp, imm: U2) {
        self.emit_n(
            Opcode::LW as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(imm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> LwuEmitter<Gp, Gp, U2> for Assembler<'_> {
    fn lwu(&mut self, rd: Gp, rs1: Gp, imm: U2) {
        self.emit_n(
            Opcode::LWU as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(imm).as_operand(),
            ],
        );
    }
}

impl MaxEmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn max(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::MAX as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl MaxuEmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn maxu(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::MAXU as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl MinEmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn min(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::MIN as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl MinuEmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn minu(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::MINU as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl MnretEmitter for Assembler<'_> {
    fn mnret(&mut self) {
        self.emit_n(Opcode::MNRET as i64, &[]);
    }
}

impl MopR0Emitter<Gp, Gp> for Assembler<'_> {
    fn mop_r_0(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::MOPR0 as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl MopR1Emitter<Gp, Gp> for Assembler<'_> {
    fn mop_r_1(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::MOPR1 as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl MopR10Emitter<Gp, Gp> for Assembler<'_> {
    fn mop_r_10(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::MOPR10 as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl MopR11Emitter<Gp, Gp> for Assembler<'_> {
    fn mop_r_11(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::MOPR11 as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl MopR12Emitter<Gp, Gp> for Assembler<'_> {
    fn mop_r_12(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::MOPR12 as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl MopR13Emitter<Gp, Gp> for Assembler<'_> {
    fn mop_r_13(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::MOPR13 as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl MopR14Emitter<Gp, Gp> for Assembler<'_> {
    fn mop_r_14(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::MOPR14 as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl MopR15Emitter<Gp, Gp> for Assembler<'_> {
    fn mop_r_15(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::MOPR15 as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl MopR16Emitter<Gp, Gp> for Assembler<'_> {
    fn mop_r_16(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::MOPR16 as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl MopR17Emitter<Gp, Gp> for Assembler<'_> {
    fn mop_r_17(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::MOPR17 as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl MopR18Emitter<Gp, Gp> for Assembler<'_> {
    fn mop_r_18(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::MOPR18 as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl MopR19Emitter<Gp, Gp> for Assembler<'_> {
    fn mop_r_19(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::MOPR19 as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl MopR2Emitter<Gp, Gp> for Assembler<'_> {
    fn mop_r_2(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::MOPR2 as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl MopR20Emitter<Gp, Gp> for Assembler<'_> {
    fn mop_r_20(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::MOPR20 as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl MopR21Emitter<Gp, Gp> for Assembler<'_> {
    fn mop_r_21(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::MOPR21 as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl MopR22Emitter<Gp, Gp> for Assembler<'_> {
    fn mop_r_22(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::MOPR22 as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl MopR23Emitter<Gp, Gp> for Assembler<'_> {
    fn mop_r_23(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::MOPR23 as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl MopR24Emitter<Gp, Gp> for Assembler<'_> {
    fn mop_r_24(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::MOPR24 as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl MopR25Emitter<Gp, Gp> for Assembler<'_> {
    fn mop_r_25(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::MOPR25 as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl MopR26Emitter<Gp, Gp> for Assembler<'_> {
    fn mop_r_26(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::MOPR26 as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl MopR27Emitter<Gp, Gp> for Assembler<'_> {
    fn mop_r_27(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::MOPR27 as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl MopR28Emitter<Gp, Gp> for Assembler<'_> {
    fn mop_r_28(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::MOPR28 as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl MopR29Emitter<Gp, Gp> for Assembler<'_> {
    fn mop_r_29(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::MOPR29 as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl MopR3Emitter<Gp, Gp> for Assembler<'_> {
    fn mop_r_3(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::MOPR3 as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl MopR30Emitter<Gp, Gp> for Assembler<'_> {
    fn mop_r_30(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::MOPR30 as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl MopR31Emitter<Gp, Gp> for Assembler<'_> {
    fn mop_r_31(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::MOPR31 as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl MopR4Emitter<Gp, Gp> for Assembler<'_> {
    fn mop_r_4(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::MOPR4 as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl MopR5Emitter<Gp, Gp> for Assembler<'_> {
    fn mop_r_5(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::MOPR5 as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl MopR6Emitter<Gp, Gp> for Assembler<'_> {
    fn mop_r_6(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::MOPR6 as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl MopR7Emitter<Gp, Gp> for Assembler<'_> {
    fn mop_r_7(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::MOPR7 as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl MopR8Emitter<Gp, Gp> for Assembler<'_> {
    fn mop_r_8(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::MOPR8 as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl MopR9Emitter<Gp, Gp> for Assembler<'_> {
    fn mop_r_9(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::MOPR9 as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl MopRr0Emitter<Gp, Gp, Gp> for Assembler<'_> {
    fn mop_rr_0(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::MOPRR0 as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl MopRr1Emitter<Gp, Gp, Gp> for Assembler<'_> {
    fn mop_rr_1(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::MOPRR1 as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl MopRr2Emitter<Gp, Gp, Gp> for Assembler<'_> {
    fn mop_rr_2(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::MOPRR2 as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl MopRr3Emitter<Gp, Gp, Gp> for Assembler<'_> {
    fn mop_rr_3(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::MOPRR3 as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl MopRr4Emitter<Gp, Gp, Gp> for Assembler<'_> {
    fn mop_rr_4(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::MOPRR4 as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl MopRr5Emitter<Gp, Gp, Gp> for Assembler<'_> {
    fn mop_rr_5(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::MOPRR5 as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl MopRr6Emitter<Gp, Gp, Gp> for Assembler<'_> {
    fn mop_rr_6(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::MOPRR6 as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl MopRr7Emitter<Gp, Gp, Gp> for Assembler<'_> {
    fn mop_rr_7(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::MOPRR7 as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl MretEmitter for Assembler<'_> {
    fn mret(&mut self) {
        self.emit_n(Opcode::MRET as i64, &[]);
    }
}

impl MulEmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn mul(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::MUL as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl MulhEmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn mulh(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::MULH as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl MulhsuEmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn mulhsu(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::MULHSU as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl MulhuEmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn mulhu(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::MULHU as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl MulwEmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn mulw(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::MULW as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl MvEmitter<Gp, Gp> for Assembler<'_> {
    fn mv(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::MV as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl NegEmitter<Gp, Gp> for Assembler<'_> {
    fn neg(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::NEG as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl NopEmitter for Assembler<'_> {
    fn nop(&mut self) {
        self.emit_n(Opcode::NOP as i64, &[]);
    }
}

impl NtlAllEmitter for Assembler<'_> {
    fn ntl_all(&mut self) {
        self.emit_n(Opcode::NTLALL as i64, &[]);
    }
}

impl NtlP1Emitter for Assembler<'_> {
    fn ntl_p1(&mut self) {
        self.emit_n(Opcode::NTLP1 as i64, &[]);
    }
}

impl NtlPallEmitter for Assembler<'_> {
    fn ntl_pall(&mut self) {
        self.emit_n(Opcode::NTLPALL as i64, &[]);
    }
}

impl NtlS1Emitter for Assembler<'_> {
    fn ntl_s1(&mut self) {
        self.emit_n(Opcode::NTLS1 as i64, &[]);
    }
}

impl OrEmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn or(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::OR as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl OrcBEmitter<Gp, Gp> for Assembler<'_> {
    fn orc_b(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::ORCB as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl<U2: Into<Imm>> OriEmitter<Gp, Gp, U2> for Assembler<'_> {
    fn ori(&mut self, rd: Gp, rs1: Gp, imm: U2) {
        self.emit_n(
            Opcode::ORI as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(imm).as_operand(),
            ],
        );
    }
}

impl OrnEmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn orn(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::ORN as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl PackEmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn pack(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::PACK as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl PackhEmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn packh(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::PACKH as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl PackwEmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn packw(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::PACKW as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl PauseEmitter for Assembler<'_> {
    fn pause(&mut self) {
        self.emit_n(Opcode::PAUSE as i64, &[]);
    }
}

impl<U1: Into<Imm>> PrefetchIEmitter<Gp, U1> for Assembler<'_> {
    fn prefetch_i(&mut self, rs1: Gp, imm: U1) {
        self.emit_n(
            Opcode::PREFETCHI as i64,
            &[rs1.as_operand(), Into::<Imm>::into(imm).as_operand()],
        );
    }
}

impl<U1: Into<Imm>> PrefetchREmitter<Gp, U1> for Assembler<'_> {
    fn prefetch_r(&mut self, rs1: Gp, imm: U1) {
        self.emit_n(
            Opcode::PREFETCHR as i64,
            &[rs1.as_operand(), Into::<Imm>::into(imm).as_operand()],
        );
    }
}

impl<U1: Into<Imm>> PrefetchWEmitter<Gp, U1> for Assembler<'_> {
    fn prefetch_w(&mut self, rs1: Gp, imm: U1) {
        self.emit_n(
            Opcode::PREFETCHW as i64,
            &[rs1.as_operand(), Into::<Imm>::into(imm).as_operand()],
        );
    }
}

impl RdcycleEmitter<Gp> for Assembler<'_> {
    fn rdcycle(&mut self, rd: Gp) {
        self.emit_n(Opcode::RDCYCLE as i64, &[rd.as_operand()]);
    }
}

impl RdcyclehEmitter<Gp> for Assembler<'_> {
    fn rdcycleh(&mut self, rd: Gp) {
        self.emit_n(Opcode::RDCYCLEH as i64, &[rd.as_operand()]);
    }
}

impl RdinstretEmitter<Gp> for Assembler<'_> {
    fn rdinstret(&mut self, rd: Gp) {
        self.emit_n(Opcode::RDINSTRET as i64, &[rd.as_operand()]);
    }
}

impl RdinstrethEmitter<Gp> for Assembler<'_> {
    fn rdinstreth(&mut self, rd: Gp) {
        self.emit_n(Opcode::RDINSTRETH as i64, &[rd.as_operand()]);
    }
}

impl RdtimeEmitter<Gp> for Assembler<'_> {
    fn rdtime(&mut self, rd: Gp) {
        self.emit_n(Opcode::RDTIME as i64, &[rd.as_operand()]);
    }
}

impl RdtimehEmitter<Gp> for Assembler<'_> {
    fn rdtimeh(&mut self, rd: Gp) {
        self.emit_n(Opcode::RDTIMEH as i64, &[rd.as_operand()]);
    }
}

impl RemEmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn rem(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::REM as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl RemuEmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn remu(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::REMU as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl RemuwEmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn remuw(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::REMUW as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl RemwEmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn remw(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::REMW as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl RetEmitter for Assembler<'_> {
    fn ret(&mut self) {
        self.emit_n(Opcode::RET as i64, &[]);
    }
}

impl Rev8Emitter<Gp, Gp> for Assembler<'_> {
    fn rev8(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::REV8 as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl Rev8Rv32Emitter<Gp, Gp> for Assembler<'_> {
    fn rev8_rv32(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(
            Opcode::REV8RV32 as i64,
            &[rd.as_operand(), rs1.as_operand()],
        );
    }
}

impl RolEmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn rol(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::ROL as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl RolwEmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn rolw(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::ROLW as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl RorEmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn ror(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::ROR as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl<U2: Into<Imm>> RoriEmitter<Gp, Gp, U2> for Assembler<'_> {
    fn rori(&mut self, rd: Gp, rs1: Gp, shamtd: U2) {
        self.emit_n(
            Opcode::RORI as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(shamtd).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> RoriRv32Emitter<Gp, Gp, U2> for Assembler<'_> {
    fn rori_rv32(&mut self, rd: Gp, rs1: Gp, shamtw: U2) {
        self.emit_n(
            Opcode::RORIRV32 as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(shamtw).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> RoriwEmitter<Gp, Gp, U2> for Assembler<'_> {
    fn roriw(&mut self, rd: Gp, rs1: Gp, shamtw: U2) {
        self.emit_n(
            Opcode::RORIW as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(shamtw).as_operand(),
            ],
        );
    }
}

impl RorwEmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn rorw(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::RORW as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl<U2: Into<Imm>> SbEmitter<Gp, Gp, U2> for Assembler<'_> {
    fn sb(&mut self, rs1: Gp, rs2: Gp, imm: U2) {
        self.emit_n(
            Opcode::SB as i64,
            &[
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(imm).as_operand(),
            ],
        );
    }
}

impl SbreakEmitter for Assembler<'_> {
    fn sbreak(&mut self) {
        self.emit_n(Opcode::SBREAK as i64, &[]);
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> ScDEmitter<Gp, Gp, Gp, U3, U4> for Assembler<'_> {
    fn sc_d(&mut self, rd: Gp, rs1: Gp, rs2: Gp, aq: U3, rl: U4) {
        self.emit_n(
            Opcode::SCD as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(aq).as_operand(),
                Into::<Imm>::into(rl).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> ScWEmitter<Gp, Gp, Gp, U3, U4> for Assembler<'_> {
    fn sc_w(&mut self, rd: Gp, rs1: Gp, rs2: Gp, aq: U3, rl: U4) {
        self.emit_n(
            Opcode::SCW as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(aq).as_operand(),
                Into::<Imm>::into(rl).as_operand(),
            ],
        );
    }
}

impl ScallEmitter for Assembler<'_> {
    fn scall(&mut self) {
        self.emit_n(Opcode::SCALL as i64, &[]);
    }
}

impl SctrclrEmitter for Assembler<'_> {
    fn sctrclr(&mut self) {
        self.emit_n(Opcode::SCTRCLR as i64, &[]);
    }
}

impl<U2: Into<Imm>> SdEmitter<Gp, Gp, U2> for Assembler<'_> {
    fn sd(&mut self, rs1: Gp, rs2: Gp, imm: U2) {
        self.emit_n(
            Opcode::SD as i64,
            &[
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(imm).as_operand(),
            ],
        );
    }
}

impl SeqzEmitter<Gp, Gp> for Assembler<'_> {
    fn seqz(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::SEQZ as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl SextBEmitter<Gp, Gp> for Assembler<'_> {
    fn sext_b(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::SEXTB as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl SextHEmitter<Gp, Gp> for Assembler<'_> {
    fn sext_h(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::SEXTH as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl SextWEmitter<Gp, Gp> for Assembler<'_> {
    fn sext_w(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::SEXTW as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl SfenceInvalIrEmitter for Assembler<'_> {
    fn sfence_inval_ir(&mut self) {
        self.emit_n(Opcode::SFENCEINVALIR as i64, &[]);
    }
}

impl SfenceVmaEmitter<Gp, Gp> for Assembler<'_> {
    fn sfence_vma(&mut self, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::SFENCEVMA as i64,
            &[rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl SfenceWInvalEmitter for Assembler<'_> {
    fn sfence_w_inval(&mut self) {
        self.emit_n(Opcode::SFENCEWINVAL as i64, &[]);
    }
}

impl SgtzEmitter<Gp, Gp> for Assembler<'_> {
    fn sgtz(&mut self, rd: Gp, rs2: Gp) {
        self.emit_n(Opcode::SGTZ as i64, &[rd.as_operand(), rs2.as_operand()]);
    }
}

impl<U2: Into<Imm>> ShEmitter<Gp, Gp, U2> for Assembler<'_> {
    fn sh(&mut self, rs1: Gp, rs2: Gp, imm: U2) {
        self.emit_n(
            Opcode::SH as i64,
            &[
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(imm).as_operand(),
            ],
        );
    }
}

impl Sh1AddEmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn sh1add(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::SH1ADD as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl Sh1AddUwEmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn sh1add_uw(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::SH1ADDUW as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl Sh2AddEmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn sh2add(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::SH2ADD as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl Sh2AddUwEmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn sh2add_uw(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::SH2ADDUW as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl Sh3AddEmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn sh3add(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::SH3ADD as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl Sh3AddUwEmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn sh3add_uw(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::SH3ADDUW as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl Sha256Sig0Emitter<Gp, Gp> for Assembler<'_> {
    fn sha256sig0(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(
            Opcode::SHA256SIG0 as i64,
            &[rd.as_operand(), rs1.as_operand()],
        );
    }
}

impl Sha256Sig1Emitter<Gp, Gp> for Assembler<'_> {
    fn sha256sig1(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(
            Opcode::SHA256SIG1 as i64,
            &[rd.as_operand(), rs1.as_operand()],
        );
    }
}

impl Sha256Sum0Emitter<Gp, Gp> for Assembler<'_> {
    fn sha256sum0(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(
            Opcode::SHA256SUM0 as i64,
            &[rd.as_operand(), rs1.as_operand()],
        );
    }
}

impl Sha256Sum1Emitter<Gp, Gp> for Assembler<'_> {
    fn sha256sum1(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(
            Opcode::SHA256SUM1 as i64,
            &[rd.as_operand(), rs1.as_operand()],
        );
    }
}

impl Sha512Sig0Emitter<Gp, Gp> for Assembler<'_> {
    fn sha512sig0(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(
            Opcode::SHA512SIG0 as i64,
            &[rd.as_operand(), rs1.as_operand()],
        );
    }
}

impl Sha512Sig0HEmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn sha512sig0h(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::SHA512SIG0H as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl Sha512Sig0LEmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn sha512sig0l(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::SHA512SIG0L as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl Sha512Sig1Emitter<Gp, Gp> for Assembler<'_> {
    fn sha512sig1(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(
            Opcode::SHA512SIG1 as i64,
            &[rd.as_operand(), rs1.as_operand()],
        );
    }
}

impl Sha512Sig1HEmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn sha512sig1h(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::SHA512SIG1H as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl Sha512Sig1LEmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn sha512sig1l(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::SHA512SIG1L as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl Sha512Sum0Emitter<Gp, Gp> for Assembler<'_> {
    fn sha512sum0(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(
            Opcode::SHA512SUM0 as i64,
            &[rd.as_operand(), rs1.as_operand()],
        );
    }
}

impl Sha512Sum0REmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn sha512sum0r(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::SHA512SUM0R as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl Sha512Sum1Emitter<Gp, Gp> for Assembler<'_> {
    fn sha512sum1(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(
            Opcode::SHA512SUM1 as i64,
            &[rd.as_operand(), rs1.as_operand()],
        );
    }
}

impl Sha512Sum1REmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn sha512sum1r(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::SHA512SUM1R as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl SinvalVmaEmitter<Gp, Gp> for Assembler<'_> {
    fn sinval_vma(&mut self, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::SINVALVMA as i64,
            &[rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl SllEmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn sll(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::SLL as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl<U2: Into<Imm>> SlliEmitter<Gp, Gp, U2> for Assembler<'_> {
    fn slli(&mut self, rd: Gp, rs1: Gp, shamtd: U2) {
        self.emit_n(
            Opcode::SLLI as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(shamtd).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> SlliRv32Emitter<Gp, Gp, U2> for Assembler<'_> {
    fn slli_rv32(&mut self, rd: Gp, rs1: Gp, shamtw: U2) {
        self.emit_n(
            Opcode::SLLIRV32 as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(shamtw).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> SlliUwEmitter<Gp, Gp, U2> for Assembler<'_> {
    fn slli_uw(&mut self, rd: Gp, rs1: Gp, shamtd: U2) {
        self.emit_n(
            Opcode::SLLIUW as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(shamtd).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> SlliwEmitter<Gp, Gp, U2> for Assembler<'_> {
    fn slliw(&mut self, rd: Gp, rs1: Gp, shamtw: U2) {
        self.emit_n(
            Opcode::SLLIW as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(shamtw).as_operand(),
            ],
        );
    }
}

impl SllwEmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn sllw(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::SLLW as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl SltEmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn slt(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::SLT as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl<U2: Into<Imm>> SltiEmitter<Gp, Gp, U2> for Assembler<'_> {
    fn slti(&mut self, rd: Gp, rs1: Gp, imm: U2) {
        self.emit_n(
            Opcode::SLTI as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(imm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> SltiuEmitter<Gp, Gp, U2> for Assembler<'_> {
    fn sltiu(&mut self, rd: Gp, rs1: Gp, imm: U2) {
        self.emit_n(
            Opcode::SLTIU as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(imm).as_operand(),
            ],
        );
    }
}

impl SltuEmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn sltu(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::SLTU as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl SltzEmitter<Gp, Gp> for Assembler<'_> {
    fn sltz(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::SLTZ as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl Sm3P0Emitter<Gp, Gp> for Assembler<'_> {
    fn sm3p0(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::SM3P0 as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl Sm3P1Emitter<Gp, Gp> for Assembler<'_> {
    fn sm3p1(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::SM3P1 as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl<U3: Into<Imm>> Sm4EdEmitter<Gp, Gp, Gp, U3> for Assembler<'_> {
    fn sm4ed(&mut self, rd: Gp, rs1: Gp, rs2: Gp, bs: U3) {
        self.emit_n(
            Opcode::SM4ED as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(bs).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> Sm4KsEmitter<Gp, Gp, Gp, U3> for Assembler<'_> {
    fn sm4ks(&mut self, rd: Gp, rs1: Gp, rs2: Gp, bs: U3) {
        self.emit_n(
            Opcode::SM4KS as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(bs).as_operand(),
            ],
        );
    }
}

impl SnezEmitter<Gp, Gp> for Assembler<'_> {
    fn snez(&mut self, rd: Gp, rs2: Gp) {
        self.emit_n(Opcode::SNEZ as i64, &[rd.as_operand(), rs2.as_operand()]);
    }
}

impl SraEmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn sra(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::SRA as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl<U2: Into<Imm>> SraiEmitter<Gp, Gp, U2> for Assembler<'_> {
    fn srai(&mut self, rd: Gp, rs1: Gp, shamtd: U2) {
        self.emit_n(
            Opcode::SRAI as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(shamtd).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> SraiRv32Emitter<Gp, Gp, U2> for Assembler<'_> {
    fn srai_rv32(&mut self, rd: Gp, rs1: Gp, shamtw: U2) {
        self.emit_n(
            Opcode::SRAIRV32 as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(shamtw).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> SraiwEmitter<Gp, Gp, U2> for Assembler<'_> {
    fn sraiw(&mut self, rd: Gp, rs1: Gp, shamtw: U2) {
        self.emit_n(
            Opcode::SRAIW as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(shamtw).as_operand(),
            ],
        );
    }
}

impl SrawEmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn sraw(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::SRAW as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl SretEmitter for Assembler<'_> {
    fn sret(&mut self) {
        self.emit_n(Opcode::SRET as i64, &[]);
    }
}

impl SrlEmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn srl(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::SRL as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl<U2: Into<Imm>> SrliEmitter<Gp, Gp, U2> for Assembler<'_> {
    fn srli(&mut self, rd: Gp, rs1: Gp, shamtd: U2) {
        self.emit_n(
            Opcode::SRLI as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(shamtd).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> SrliRv32Emitter<Gp, Gp, U2> for Assembler<'_> {
    fn srli_rv32(&mut self, rd: Gp, rs1: Gp, shamtw: U2) {
        self.emit_n(
            Opcode::SRLIRV32 as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(shamtw).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> SrliwEmitter<Gp, Gp, U2> for Assembler<'_> {
    fn srliw(&mut self, rd: Gp, rs1: Gp, shamtw: U2) {
        self.emit_n(
            Opcode::SRLIW as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(shamtw).as_operand(),
            ],
        );
    }
}

impl SrlwEmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn srlw(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::SRLW as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> SsamoswapDEmitter<Gp, Gp, Gp, U3, U4> for Assembler<'_> {
    fn ssamoswap_d(&mut self, rd: Gp, rs1: Gp, rs2: Gp, aq: U3, rl: U4) {
        self.emit_n(
            Opcode::SSAMOSWAPD as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(aq).as_operand(),
                Into::<Imm>::into(rl).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> SsamoswapWEmitter<Gp, Gp, Gp, U3, U4> for Assembler<'_> {
    fn ssamoswap_w(&mut self, rd: Gp, rs1: Gp, rs2: Gp, aq: U3, rl: U4) {
        self.emit_n(
            Opcode::SSAMOSWAPW as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(aq).as_operand(),
                Into::<Imm>::into(rl).as_operand(),
            ],
        );
    }
}

impl SspopchkX1Emitter for Assembler<'_> {
    fn sspopchk_x1(&mut self) {
        self.emit_n(Opcode::SSPOPCHKX1 as i64, &[]);
    }
}

impl SspopchkX5Emitter for Assembler<'_> {
    fn sspopchk_x5(&mut self) {
        self.emit_n(Opcode::SSPOPCHKX5 as i64, &[]);
    }
}

impl SspushX1Emitter for Assembler<'_> {
    fn sspush_x1(&mut self) {
        self.emit_n(Opcode::SSPUSHX1 as i64, &[]);
    }
}

impl SspushX5Emitter for Assembler<'_> {
    fn sspush_x5(&mut self) {
        self.emit_n(Opcode::SSPUSHX5 as i64, &[]);
    }
}

impl SsrdpEmitter<Gp> for Assembler<'_> {
    fn ssrdp(&mut self, rd: Gp) {
        self.emit_n(Opcode::SSRDP as i64, &[rd.as_operand()]);
    }
}

impl SubEmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn sub(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::SUB as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl SubwEmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn subw(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::SUBW as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl<U2: Into<Imm>> SwEmitter<Gp, Gp, U2> for Assembler<'_> {
    fn sw(&mut self, rs1: Gp, rs2: Gp, imm: U2) {
        self.emit_n(
            Opcode::SW as i64,
            &[
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(imm).as_operand(),
            ],
        );
    }
}

impl UnzipEmitter<Gp, Gp> for Assembler<'_> {
    fn unzip(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::UNZIP as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl<U3: Into<Imm>> VaaddVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vaadd_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VAADDVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VaaddVxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vaadd_vx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VAADDVX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VaadduVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vaaddu_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VAADDUVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VaadduVxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vaaddu_vx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VAADDUVX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> VadcVimEmitter<Vp, Vp, U2> for Assembler<'_> {
    fn vadc_vim(&mut self, vd: Vp, vs2: Vp, simm5: U2) {
        self.emit_n(
            Opcode::VADCVIM as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(simm5).as_operand(),
            ],
        );
    }
}

impl VadcVvmEmitter<Vp, Vp, Vp> for Assembler<'_> {
    fn vadc_vvm(&mut self, vd: Vp, vs1: Vp, vs2: Vp) {
        self.emit_n(
            Opcode::VADCVVM as i64,
            &[vd.as_operand(), vs1.as_operand(), vs2.as_operand()],
        );
    }
}

impl VadcVxmEmitter<Vp, Gp, Vp> for Assembler<'_> {
    fn vadc_vxm(&mut self, vd: Vp, rs1: Gp, vs2: Vp) {
        self.emit_n(
            Opcode::VADCVXM as i64,
            &[vd.as_operand(), rs1.as_operand(), vs2.as_operand()],
        );
    }
}

impl<U2: Into<Imm>, U3: Into<Imm>> VaddViEmitter<Vp, Vp, U2, U3> for Assembler<'_> {
    fn vadd_vi(&mut self, vd: Vp, vs2: Vp, simm5: U2, vm: U3) {
        self.emit_n(
            Opcode::VADDVI as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(simm5).as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VaddVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vadd_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VADDVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VaddVxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vadd_vx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VADDVX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl VaesdfVsEmitter<Vp, Vp> for Assembler<'_> {
    fn vaesdf_vs(&mut self, vd: Vp, vs2: Vp) {
        self.emit_n(
            Opcode::VAESDFVS as i64,
            &[vd.as_operand(), vs2.as_operand()],
        );
    }
}

impl VaesdfVvEmitter<Vp, Vp> for Assembler<'_> {
    fn vaesdf_vv(&mut self, vd: Vp, vs2: Vp) {
        self.emit_n(
            Opcode::VAESDFVV as i64,
            &[vd.as_operand(), vs2.as_operand()],
        );
    }
}

impl VaesdmVsEmitter<Vp, Vp> for Assembler<'_> {
    fn vaesdm_vs(&mut self, vd: Vp, vs2: Vp) {
        self.emit_n(
            Opcode::VAESDMVS as i64,
            &[vd.as_operand(), vs2.as_operand()],
        );
    }
}

impl VaesdmVvEmitter<Vp, Vp> for Assembler<'_> {
    fn vaesdm_vv(&mut self, vd: Vp, vs2: Vp) {
        self.emit_n(
            Opcode::VAESDMVV as i64,
            &[vd.as_operand(), vs2.as_operand()],
        );
    }
}

impl VaesefVsEmitter<Vp, Vp> for Assembler<'_> {
    fn vaesef_vs(&mut self, vd: Vp, vs2: Vp) {
        self.emit_n(
            Opcode::VAESEFVS as i64,
            &[vd.as_operand(), vs2.as_operand()],
        );
    }
}

impl VaesefVvEmitter<Vp, Vp> for Assembler<'_> {
    fn vaesef_vv(&mut self, vd: Vp, vs2: Vp) {
        self.emit_n(
            Opcode::VAESEFVV as i64,
            &[vd.as_operand(), vs2.as_operand()],
        );
    }
}

impl VaesemVsEmitter<Vp, Vp> for Assembler<'_> {
    fn vaesem_vs(&mut self, vd: Vp, vs2: Vp) {
        self.emit_n(
            Opcode::VAESEMVS as i64,
            &[vd.as_operand(), vs2.as_operand()],
        );
    }
}

impl VaesemVvEmitter<Vp, Vp> for Assembler<'_> {
    fn vaesem_vv(&mut self, vd: Vp, vs2: Vp) {
        self.emit_n(
            Opcode::VAESEMVV as i64,
            &[vd.as_operand(), vs2.as_operand()],
        );
    }
}

impl<U2: Into<Imm>> Vaeskf1ViEmitter<Vp, Vp, U2> for Assembler<'_> {
    fn vaeskf1_vi(&mut self, vd: Vp, vs2: Vp, zimm5: U2) {
        self.emit_n(
            Opcode::VAESKF1VI as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(zimm5).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> Vaeskf2ViEmitter<Vp, Vp, U2> for Assembler<'_> {
    fn vaeskf2_vi(&mut self, vd: Vp, vs2: Vp, zimm5: U2) {
        self.emit_n(
            Opcode::VAESKF2VI as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(zimm5).as_operand(),
            ],
        );
    }
}

impl VaeszVsEmitter<Vp, Vp> for Assembler<'_> {
    fn vaesz_vs(&mut self, vd: Vp, vs2: Vp) {
        self.emit_n(Opcode::VAESZVS as i64, &[vd.as_operand(), vs2.as_operand()]);
    }
}

impl<U2: Into<Imm>, U3: Into<Imm>> VandViEmitter<Vp, Vp, U2, U3> for Assembler<'_> {
    fn vand_vi(&mut self, vd: Vp, vs2: Vp, simm5: U2, vm: U3) {
        self.emit_n(
            Opcode::VANDVI as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(simm5).as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VandVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vand_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VANDVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VandVxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vand_vx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VANDVX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VandnVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vandn_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VANDNVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VandnVxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vandn_vx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VANDNVX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VasubVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vasub_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VASUBVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VasubVxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vasub_vx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VASUBVX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VasubuVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vasubu_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VASUBUVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VasubuVxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vasubu_vx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VASUBUVX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> Vbrev8VEmitter<Vp, Vp, U2> for Assembler<'_> {
    fn vbrev8_v(&mut self, vd: Vp, vs2: Vp, vm: U2) {
        self.emit_n(
            Opcode::VBREV8V as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> VbrevVEmitter<Vp, Vp, U2> for Assembler<'_> {
    fn vbrev_v(&mut self, vd: Vp, vs2: Vp, vm: U2) {
        self.emit_n(
            Opcode::VBREVV as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VclmulVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vclmul_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VCLMULVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VclmulVxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vclmul_vx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VCLMULVX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VclmulhVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vclmulh_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VCLMULHVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VclmulhVxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vclmulh_vx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VCLMULHVX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> VclzVEmitter<Vp, Vp, U2> for Assembler<'_> {
    fn vclz_v(&mut self, vd: Vp, vs2: Vp, vm: U2) {
        self.emit_n(
            Opcode::VCLZV as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl VcompressVmEmitter<Vp, Vp, Vp> for Assembler<'_> {
    fn vcompress_vm(&mut self, vd: Vp, vs1: Vp, vs2: Vp) {
        self.emit_n(
            Opcode::VCOMPRESSVM as i64,
            &[vd.as_operand(), vs1.as_operand(), vs2.as_operand()],
        );
    }
}

impl<U2: Into<Imm>> VcpopMEmitter<Gp, Vp, U2> for Assembler<'_> {
    fn vcpop_m(&mut self, rd: Gp, vs2: Vp, vm: U2) {
        self.emit_n(
            Opcode::VCPOPM as i64,
            &[
                rd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> VcpopVEmitter<Vp, Vp, U2> for Assembler<'_> {
    fn vcpop_v(&mut self, vd: Vp, vs2: Vp, vm: U2) {
        self.emit_n(
            Opcode::VCPOPV as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> VctzVEmitter<Vp, Vp, U2> for Assembler<'_> {
    fn vctz_v(&mut self, vd: Vp, vs2: Vp, vm: U2) {
        self.emit_n(
            Opcode::VCTZV as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VdivVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vdiv_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VDIVVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VdivVxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vdiv_vx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VDIVVX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VdivuVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vdivu_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VDIVUVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VdivuVxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vdivu_vx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VDIVUVX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VfaddVfEmitter<Vp, Vp, Fp, U3> for Assembler<'_> {
    fn vfadd_vf(&mut self, vd: Vp, vs2: Vp, rs1: Fp, vm: U3) {
        self.emit_n(
            Opcode::VFADDVF as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VfaddVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vfadd_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VFADDVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> VfclassVEmitter<Vp, Vp, U2> for Assembler<'_> {
    fn vfclass_v(&mut self, vd: Vp, vs2: Vp, vm: U2) {
        self.emit_n(
            Opcode::VFCLASSV as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> VfcvtFXVEmitter<Vp, Vp, U2> for Assembler<'_> {
    fn vfcvt_f_x_v(&mut self, vd: Vp, vs2: Vp, vm: U2) {
        self.emit_n(
            Opcode::VFCVTFXV as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> VfcvtFXuVEmitter<Vp, Vp, U2> for Assembler<'_> {
    fn vfcvt_f_xu_v(&mut self, vd: Vp, vs2: Vp, vm: U2) {
        self.emit_n(
            Opcode::VFCVTFXUV as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> VfcvtRtzXFVEmitter<Vp, Vp, U2> for Assembler<'_> {
    fn vfcvt_rtz_x_f_v(&mut self, vd: Vp, vs2: Vp, vm: U2) {
        self.emit_n(
            Opcode::VFCVTRTZXFV as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> VfcvtRtzXuFVEmitter<Vp, Vp, U2> for Assembler<'_> {
    fn vfcvt_rtz_xu_f_v(&mut self, vd: Vp, vs2: Vp, vm: U2) {
        self.emit_n(
            Opcode::VFCVTRTZXUFV as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> VfcvtXFVEmitter<Vp, Vp, U2> for Assembler<'_> {
    fn vfcvt_x_f_v(&mut self, vd: Vp, vs2: Vp, vm: U2) {
        self.emit_n(
            Opcode::VFCVTXFV as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> VfcvtXuFVEmitter<Vp, Vp, U2> for Assembler<'_> {
    fn vfcvt_xu_f_v(&mut self, vd: Vp, vs2: Vp, vm: U2) {
        self.emit_n(
            Opcode::VFCVTXUFV as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VfdivVfEmitter<Vp, Vp, Fp, U3> for Assembler<'_> {
    fn vfdiv_vf(&mut self, vd: Vp, vs2: Vp, rs1: Fp, vm: U3) {
        self.emit_n(
            Opcode::VFDIVVF as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VfdivVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vfdiv_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VFDIVVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> VfirstMEmitter<Gp, Vp, U2> for Assembler<'_> {
    fn vfirst_m(&mut self, rd: Gp, vs2: Vp, vm: U2) {
        self.emit_n(
            Opcode::VFIRSTM as i64,
            &[
                rd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VfmaccVfEmitter<Vp, Vp, Fp, U3> for Assembler<'_> {
    fn vfmacc_vf(&mut self, vd: Vp, vs2: Vp, rs1: Fp, vm: U3) {
        self.emit_n(
            Opcode::VFMACCVF as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VfmaccVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vfmacc_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VFMACCVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VfmaddVfEmitter<Vp, Vp, Fp, U3> for Assembler<'_> {
    fn vfmadd_vf(&mut self, vd: Vp, vs2: Vp, rs1: Fp, vm: U3) {
        self.emit_n(
            Opcode::VFMADDVF as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VfmaddVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vfmadd_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VFMADDVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VfmaxVfEmitter<Vp, Vp, Fp, U3> for Assembler<'_> {
    fn vfmax_vf(&mut self, vd: Vp, vs2: Vp, rs1: Fp, vm: U3) {
        self.emit_n(
            Opcode::VFMAXVF as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VfmaxVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vfmax_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VFMAXVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl VfmergeVfmEmitter<Vp, Fp, Vp> for Assembler<'_> {
    fn vfmerge_vfm(&mut self, vd: Vp, rs1: Fp, vs2: Vp) {
        self.emit_n(
            Opcode::VFMERGEVFM as i64,
            &[vd.as_operand(), rs1.as_operand(), vs2.as_operand()],
        );
    }
}

impl<U3: Into<Imm>> VfminVfEmitter<Vp, Vp, Fp, U3> for Assembler<'_> {
    fn vfmin_vf(&mut self, vd: Vp, vs2: Vp, rs1: Fp, vm: U3) {
        self.emit_n(
            Opcode::VFMINVF as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VfminVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vfmin_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VFMINVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VfmsacVfEmitter<Vp, Vp, Fp, U3> for Assembler<'_> {
    fn vfmsac_vf(&mut self, vd: Vp, vs2: Vp, rs1: Fp, vm: U3) {
        self.emit_n(
            Opcode::VFMSACVF as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VfmsacVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vfmsac_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VFMSACVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VfmsubVfEmitter<Vp, Vp, Fp, U3> for Assembler<'_> {
    fn vfmsub_vf(&mut self, vd: Vp, vs2: Vp, rs1: Fp, vm: U3) {
        self.emit_n(
            Opcode::VFMSUBVF as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VfmsubVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vfmsub_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VFMSUBVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VfmulVfEmitter<Vp, Vp, Fp, U3> for Assembler<'_> {
    fn vfmul_vf(&mut self, vd: Vp, vs2: Vp, rs1: Fp, vm: U3) {
        self.emit_n(
            Opcode::VFMULVF as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VfmulVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vfmul_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VFMULVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl VfmvFSEmitter<Fp, Vp> for Assembler<'_> {
    fn vfmv_f_s(&mut self, rd: Fp, vs2: Vp) {
        self.emit_n(Opcode::VFMVFS as i64, &[rd.as_operand(), vs2.as_operand()]);
    }
}

impl VfmvSFEmitter<Vp, Fp> for Assembler<'_> {
    fn vfmv_s_f(&mut self, vd: Vp, rs1: Fp) {
        self.emit_n(Opcode::VFMVSF as i64, &[vd.as_operand(), rs1.as_operand()]);
    }
}

impl VfmvVFEmitter<Vp, Fp> for Assembler<'_> {
    fn vfmv_v_f(&mut self, vd: Vp, rs1: Fp) {
        self.emit_n(Opcode::VFMVVF as i64, &[vd.as_operand(), rs1.as_operand()]);
    }
}

impl<U2: Into<Imm>> VfncvtFFWEmitter<Vp, Vp, U2> for Assembler<'_> {
    fn vfncvt_f_f_w(&mut self, vd: Vp, vs2: Vp, vm: U2) {
        self.emit_n(
            Opcode::VFNCVTFFW as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> VfncvtFXWEmitter<Vp, Vp, U2> for Assembler<'_> {
    fn vfncvt_f_x_w(&mut self, vd: Vp, vs2: Vp, vm: U2) {
        self.emit_n(
            Opcode::VFNCVTFXW as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> VfncvtFXuWEmitter<Vp, Vp, U2> for Assembler<'_> {
    fn vfncvt_f_xu_w(&mut self, vd: Vp, vs2: Vp, vm: U2) {
        self.emit_n(
            Opcode::VFNCVTFXUW as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> VfncvtRodFFWEmitter<Vp, Vp, U2> for Assembler<'_> {
    fn vfncvt_rod_f_f_w(&mut self, vd: Vp, vs2: Vp, vm: U2) {
        self.emit_n(
            Opcode::VFNCVTRODFFW as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> VfncvtRtzXFWEmitter<Vp, Vp, U2> for Assembler<'_> {
    fn vfncvt_rtz_x_f_w(&mut self, vd: Vp, vs2: Vp, vm: U2) {
        self.emit_n(
            Opcode::VFNCVTRTZXFW as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> VfncvtRtzXuFWEmitter<Vp, Vp, U2> for Assembler<'_> {
    fn vfncvt_rtz_xu_f_w(&mut self, vd: Vp, vs2: Vp, vm: U2) {
        self.emit_n(
            Opcode::VFNCVTRTZXUFW as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> VfncvtXFWEmitter<Vp, Vp, U2> for Assembler<'_> {
    fn vfncvt_x_f_w(&mut self, vd: Vp, vs2: Vp, vm: U2) {
        self.emit_n(
            Opcode::VFNCVTXFW as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> VfncvtXuFWEmitter<Vp, Vp, U2> for Assembler<'_> {
    fn vfncvt_xu_f_w(&mut self, vd: Vp, vs2: Vp, vm: U2) {
        self.emit_n(
            Opcode::VFNCVTXUFW as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> Vfncvtbf16FFWEmitter<Vp, Vp, U2> for Assembler<'_> {
    fn vfncvtbf16_f_f_w(&mut self, vd: Vp, vs2: Vp, vm: U2) {
        self.emit_n(
            Opcode::VFNCVTBF16FFW as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VfnmaccVfEmitter<Vp, Vp, Fp, U3> for Assembler<'_> {
    fn vfnmacc_vf(&mut self, vd: Vp, vs2: Vp, rs1: Fp, vm: U3) {
        self.emit_n(
            Opcode::VFNMACCVF as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VfnmaccVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vfnmacc_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VFNMACCVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VfnmaddVfEmitter<Vp, Vp, Fp, U3> for Assembler<'_> {
    fn vfnmadd_vf(&mut self, vd: Vp, vs2: Vp, rs1: Fp, vm: U3) {
        self.emit_n(
            Opcode::VFNMADDVF as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VfnmaddVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vfnmadd_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VFNMADDVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VfnmsacVfEmitter<Vp, Vp, Fp, U3> for Assembler<'_> {
    fn vfnmsac_vf(&mut self, vd: Vp, vs2: Vp, rs1: Fp, vm: U3) {
        self.emit_n(
            Opcode::VFNMSACVF as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VfnmsacVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vfnmsac_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VFNMSACVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VfnmsubVfEmitter<Vp, Vp, Fp, U3> for Assembler<'_> {
    fn vfnmsub_vf(&mut self, vd: Vp, vs2: Vp, rs1: Fp, vm: U3) {
        self.emit_n(
            Opcode::VFNMSUBVF as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VfnmsubVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vfnmsub_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VFNMSUBVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VfrdivVfEmitter<Vp, Vp, Fp, U3> for Assembler<'_> {
    fn vfrdiv_vf(&mut self, vd: Vp, vs2: Vp, rs1: Fp, vm: U3) {
        self.emit_n(
            Opcode::VFRDIVVF as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> Vfrec7VEmitter<Vp, Vp, U2> for Assembler<'_> {
    fn vfrec7_v(&mut self, vd: Vp, vs2: Vp, vm: U2) {
        self.emit_n(
            Opcode::VFREC7V as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VfredmaxVsEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vfredmax_vs(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VFREDMAXVS as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VfredminVsEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vfredmin_vs(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VFREDMINVS as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VfredosumVsEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vfredosum_vs(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VFREDOSUMVS as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VfredsumVsEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vfredsum_vs(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VFREDSUMVS as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VfredusumVsEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vfredusum_vs(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VFREDUSUMVS as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> Vfrsqrt7VEmitter<Vp, Vp, U2> for Assembler<'_> {
    fn vfrsqrt7_v(&mut self, vd: Vp, vs2: Vp, vm: U2) {
        self.emit_n(
            Opcode::VFRSQRT7V as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VfrsubVfEmitter<Vp, Vp, Fp, U3> for Assembler<'_> {
    fn vfrsub_vf(&mut self, vd: Vp, vs2: Vp, rs1: Fp, vm: U3) {
        self.emit_n(
            Opcode::VFRSUBVF as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VfsgnjVfEmitter<Vp, Vp, Fp, U3> for Assembler<'_> {
    fn vfsgnj_vf(&mut self, vd: Vp, vs2: Vp, rs1: Fp, vm: U3) {
        self.emit_n(
            Opcode::VFSGNJVF as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VfsgnjVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vfsgnj_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VFSGNJVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VfsgnjnVfEmitter<Vp, Vp, Fp, U3> for Assembler<'_> {
    fn vfsgnjn_vf(&mut self, vd: Vp, vs2: Vp, rs1: Fp, vm: U3) {
        self.emit_n(
            Opcode::VFSGNJNVF as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VfsgnjnVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vfsgnjn_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VFSGNJNVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VfsgnjxVfEmitter<Vp, Vp, Fp, U3> for Assembler<'_> {
    fn vfsgnjx_vf(&mut self, vd: Vp, vs2: Vp, rs1: Fp, vm: U3) {
        self.emit_n(
            Opcode::VFSGNJXVF as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VfsgnjxVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vfsgnjx_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VFSGNJXVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> Vfslide1DownVfEmitter<Vp, Vp, Fp, U3> for Assembler<'_> {
    fn vfslide1down_vf(&mut self, vd: Vp, vs2: Vp, rs1: Fp, vm: U3) {
        self.emit_n(
            Opcode::VFSLIDE1DOWNVF as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> Vfslide1UpVfEmitter<Vp, Vp, Fp, U3> for Assembler<'_> {
    fn vfslide1up_vf(&mut self, vd: Vp, vs2: Vp, rs1: Fp, vm: U3) {
        self.emit_n(
            Opcode::VFSLIDE1UPVF as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> VfsqrtVEmitter<Vp, Vp, U2> for Assembler<'_> {
    fn vfsqrt_v(&mut self, vd: Vp, vs2: Vp, vm: U2) {
        self.emit_n(
            Opcode::VFSQRTV as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VfsubVfEmitter<Vp, Vp, Fp, U3> for Assembler<'_> {
    fn vfsub_vf(&mut self, vd: Vp, vs2: Vp, rs1: Fp, vm: U3) {
        self.emit_n(
            Opcode::VFSUBVF as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VfsubVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vfsub_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VFSUBVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VfwaddVfEmitter<Vp, Vp, Fp, U3> for Assembler<'_> {
    fn vfwadd_vf(&mut self, vd: Vp, vs2: Vp, rs1: Fp, vm: U3) {
        self.emit_n(
            Opcode::VFWADDVF as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VfwaddVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vfwadd_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VFWADDVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VfwaddWfEmitter<Vp, Vp, Fp, U3> for Assembler<'_> {
    fn vfwadd_wf(&mut self, vd: Vp, vs2: Vp, rs1: Fp, vm: U3) {
        self.emit_n(
            Opcode::VFWADDWF as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VfwaddWvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vfwadd_wv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VFWADDWV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> VfwcvtFFVEmitter<Vp, Vp, U2> for Assembler<'_> {
    fn vfwcvt_f_f_v(&mut self, vd: Vp, vs2: Vp, vm: U2) {
        self.emit_n(
            Opcode::VFWCVTFFV as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> VfwcvtFXVEmitter<Vp, Vp, U2> for Assembler<'_> {
    fn vfwcvt_f_x_v(&mut self, vd: Vp, vs2: Vp, vm: U2) {
        self.emit_n(
            Opcode::VFWCVTFXV as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> VfwcvtFXuVEmitter<Vp, Vp, U2> for Assembler<'_> {
    fn vfwcvt_f_xu_v(&mut self, vd: Vp, vs2: Vp, vm: U2) {
        self.emit_n(
            Opcode::VFWCVTFXUV as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> VfwcvtRtzXFVEmitter<Vp, Vp, U2> for Assembler<'_> {
    fn vfwcvt_rtz_x_f_v(&mut self, vd: Vp, vs2: Vp, vm: U2) {
        self.emit_n(
            Opcode::VFWCVTRTZXFV as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> VfwcvtRtzXuFVEmitter<Vp, Vp, U2> for Assembler<'_> {
    fn vfwcvt_rtz_xu_f_v(&mut self, vd: Vp, vs2: Vp, vm: U2) {
        self.emit_n(
            Opcode::VFWCVTRTZXUFV as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> VfwcvtXFVEmitter<Vp, Vp, U2> for Assembler<'_> {
    fn vfwcvt_x_f_v(&mut self, vd: Vp, vs2: Vp, vm: U2) {
        self.emit_n(
            Opcode::VFWCVTXFV as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> VfwcvtXuFVEmitter<Vp, Vp, U2> for Assembler<'_> {
    fn vfwcvt_xu_f_v(&mut self, vd: Vp, vs2: Vp, vm: U2) {
        self.emit_n(
            Opcode::VFWCVTXUFV as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> Vfwcvtbf16FFVEmitter<Vp, Vp, U2> for Assembler<'_> {
    fn vfwcvtbf16_f_f_v(&mut self, vd: Vp, vs2: Vp, vm: U2) {
        self.emit_n(
            Opcode::VFWCVTBF16FFV as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VfwmaccVfEmitter<Vp, Vp, Fp, U3> for Assembler<'_> {
    fn vfwmacc_vf(&mut self, vd: Vp, vs2: Vp, rs1: Fp, vm: U3) {
        self.emit_n(
            Opcode::VFWMACCVF as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VfwmaccVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vfwmacc_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VFWMACCVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> Vfwmaccbf16VfEmitter<Vp, Vp, Fp, U3> for Assembler<'_> {
    fn vfwmaccbf16_vf(&mut self, vd: Vp, vs2: Vp, rs1: Fp, vm: U3) {
        self.emit_n(
            Opcode::VFWMACCBF16VF as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> Vfwmaccbf16VvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vfwmaccbf16_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VFWMACCBF16VV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VfwmsacVfEmitter<Vp, Vp, Fp, U3> for Assembler<'_> {
    fn vfwmsac_vf(&mut self, vd: Vp, vs2: Vp, rs1: Fp, vm: U3) {
        self.emit_n(
            Opcode::VFWMSACVF as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VfwmsacVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vfwmsac_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VFWMSACVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VfwmulVfEmitter<Vp, Vp, Fp, U3> for Assembler<'_> {
    fn vfwmul_vf(&mut self, vd: Vp, vs2: Vp, rs1: Fp, vm: U3) {
        self.emit_n(
            Opcode::VFWMULVF as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VfwmulVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vfwmul_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VFWMULVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VfwnmaccVfEmitter<Vp, Vp, Fp, U3> for Assembler<'_> {
    fn vfwnmacc_vf(&mut self, vd: Vp, vs2: Vp, rs1: Fp, vm: U3) {
        self.emit_n(
            Opcode::VFWNMACCVF as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VfwnmaccVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vfwnmacc_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VFWNMACCVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VfwnmsacVfEmitter<Vp, Vp, Fp, U3> for Assembler<'_> {
    fn vfwnmsac_vf(&mut self, vd: Vp, vs2: Vp, rs1: Fp, vm: U3) {
        self.emit_n(
            Opcode::VFWNMSACVF as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VfwnmsacVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vfwnmsac_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VFWNMSACVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VfwredosumVsEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vfwredosum_vs(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VFWREDOSUMVS as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VfwredsumVsEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vfwredsum_vs(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VFWREDSUMVS as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VfwredusumVsEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vfwredusum_vs(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VFWREDUSUMVS as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VfwsubVfEmitter<Vp, Vp, Fp, U3> for Assembler<'_> {
    fn vfwsub_vf(&mut self, vd: Vp, vs2: Vp, rs1: Fp, vm: U3) {
        self.emit_n(
            Opcode::VFWSUBVF as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VfwsubVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vfwsub_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VFWSUBVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VfwsubWfEmitter<Vp, Vp, Fp, U3> for Assembler<'_> {
    fn vfwsub_wf(&mut self, vd: Vp, vs2: Vp, rs1: Fp, vm: U3) {
        self.emit_n(
            Opcode::VFWSUBWF as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VfwsubWvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vfwsub_wv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VFWSUBWV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl VghshVvEmitter<Vp, Vp, Vp> for Assembler<'_> {
    fn vghsh_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp) {
        self.emit_n(
            Opcode::VGHSHVV as i64,
            &[vd.as_operand(), vs1.as_operand(), vs2.as_operand()],
        );
    }
}

impl VgmulVvEmitter<Vp, Vp> for Assembler<'_> {
    fn vgmul_vv(&mut self, vd: Vp, vs2: Vp) {
        self.emit_n(Opcode::VGMULVV as i64, &[vd.as_operand(), vs2.as_operand()]);
    }
}

impl<U1: Into<Imm>> VidVEmitter<Vp, U1> for Assembler<'_> {
    fn vid_v(&mut self, vd: Vp, vm: U1) {
        self.emit_n(
            Opcode::VIDV as i64,
            &[vd.as_operand(), Into::<Imm>::into(vm).as_operand()],
        );
    }
}

impl<U2: Into<Imm>> ViotaMEmitter<Vp, Vp, U2> for Assembler<'_> {
    fn viota_m(&mut self, vd: Vp, vs2: Vp, vm: U2) {
        self.emit_n(
            Opcode::VIOTAM as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl Vl1RVEmitter<Vp, Gp> for Assembler<'_> {
    fn vl1r_v(&mut self, vd: Vp, rs1: Gp) {
        self.emit_n(Opcode::VL1RV as i64, &[vd.as_operand(), rs1.as_operand()]);
    }
}

impl Vl1Re16VEmitter<Vp, Gp> for Assembler<'_> {
    fn vl1re16_v(&mut self, vd: Vp, rs1: Gp) {
        self.emit_n(
            Opcode::VL1RE16V as i64,
            &[vd.as_operand(), rs1.as_operand()],
        );
    }
}

impl Vl1Re32VEmitter<Vp, Gp> for Assembler<'_> {
    fn vl1re32_v(&mut self, vd: Vp, rs1: Gp) {
        self.emit_n(
            Opcode::VL1RE32V as i64,
            &[vd.as_operand(), rs1.as_operand()],
        );
    }
}

impl Vl1Re64VEmitter<Vp, Gp> for Assembler<'_> {
    fn vl1re64_v(&mut self, vd: Vp, rs1: Gp) {
        self.emit_n(
            Opcode::VL1RE64V as i64,
            &[vd.as_operand(), rs1.as_operand()],
        );
    }
}

impl Vl1Re8VEmitter<Vp, Gp> for Assembler<'_> {
    fn vl1re8_v(&mut self, vd: Vp, rs1: Gp) {
        self.emit_n(Opcode::VL1RE8V as i64, &[vd.as_operand(), rs1.as_operand()]);
    }
}

impl Vl2RVEmitter<Vp, Gp> for Assembler<'_> {
    fn vl2r_v(&mut self, vd: Vp, rs1: Gp) {
        self.emit_n(Opcode::VL2RV as i64, &[vd.as_operand(), rs1.as_operand()]);
    }
}

impl Vl2Re16VEmitter<Vp, Gp> for Assembler<'_> {
    fn vl2re16_v(&mut self, vd: Vp, rs1: Gp) {
        self.emit_n(
            Opcode::VL2RE16V as i64,
            &[vd.as_operand(), rs1.as_operand()],
        );
    }
}

impl Vl2Re32VEmitter<Vp, Gp> for Assembler<'_> {
    fn vl2re32_v(&mut self, vd: Vp, rs1: Gp) {
        self.emit_n(
            Opcode::VL2RE32V as i64,
            &[vd.as_operand(), rs1.as_operand()],
        );
    }
}

impl Vl2Re64VEmitter<Vp, Gp> for Assembler<'_> {
    fn vl2re64_v(&mut self, vd: Vp, rs1: Gp) {
        self.emit_n(
            Opcode::VL2RE64V as i64,
            &[vd.as_operand(), rs1.as_operand()],
        );
    }
}

impl Vl2Re8VEmitter<Vp, Gp> for Assembler<'_> {
    fn vl2re8_v(&mut self, vd: Vp, rs1: Gp) {
        self.emit_n(Opcode::VL2RE8V as i64, &[vd.as_operand(), rs1.as_operand()]);
    }
}

impl Vl4RVEmitter<Vp, Gp> for Assembler<'_> {
    fn vl4r_v(&mut self, vd: Vp, rs1: Gp) {
        self.emit_n(Opcode::VL4RV as i64, &[vd.as_operand(), rs1.as_operand()]);
    }
}

impl Vl4Re16VEmitter<Vp, Gp> for Assembler<'_> {
    fn vl4re16_v(&mut self, vd: Vp, rs1: Gp) {
        self.emit_n(
            Opcode::VL4RE16V as i64,
            &[vd.as_operand(), rs1.as_operand()],
        );
    }
}

impl Vl4Re32VEmitter<Vp, Gp> for Assembler<'_> {
    fn vl4re32_v(&mut self, vd: Vp, rs1: Gp) {
        self.emit_n(
            Opcode::VL4RE32V as i64,
            &[vd.as_operand(), rs1.as_operand()],
        );
    }
}

impl Vl4Re64VEmitter<Vp, Gp> for Assembler<'_> {
    fn vl4re64_v(&mut self, vd: Vp, rs1: Gp) {
        self.emit_n(
            Opcode::VL4RE64V as i64,
            &[vd.as_operand(), rs1.as_operand()],
        );
    }
}

impl Vl4Re8VEmitter<Vp, Gp> for Assembler<'_> {
    fn vl4re8_v(&mut self, vd: Vp, rs1: Gp) {
        self.emit_n(Opcode::VL4RE8V as i64, &[vd.as_operand(), rs1.as_operand()]);
    }
}

impl Vl8RVEmitter<Vp, Gp> for Assembler<'_> {
    fn vl8r_v(&mut self, vd: Vp, rs1: Gp) {
        self.emit_n(Opcode::VL8RV as i64, &[vd.as_operand(), rs1.as_operand()]);
    }
}

impl Vl8Re16VEmitter<Vp, Gp> for Assembler<'_> {
    fn vl8re16_v(&mut self, vd: Vp, rs1: Gp) {
        self.emit_n(
            Opcode::VL8RE16V as i64,
            &[vd.as_operand(), rs1.as_operand()],
        );
    }
}

impl Vl8Re32VEmitter<Vp, Gp> for Assembler<'_> {
    fn vl8re32_v(&mut self, vd: Vp, rs1: Gp) {
        self.emit_n(
            Opcode::VL8RE32V as i64,
            &[vd.as_operand(), rs1.as_operand()],
        );
    }
}

impl Vl8Re64VEmitter<Vp, Gp> for Assembler<'_> {
    fn vl8re64_v(&mut self, vd: Vp, rs1: Gp) {
        self.emit_n(
            Opcode::VL8RE64V as i64,
            &[vd.as_operand(), rs1.as_operand()],
        );
    }
}

impl Vl8Re8VEmitter<Vp, Gp> for Assembler<'_> {
    fn vl8re8_v(&mut self, vd: Vp, rs1: Gp) {
        self.emit_n(Opcode::VL8RE8V as i64, &[vd.as_operand(), rs1.as_operand()]);
    }
}

impl<U2: Into<Imm>, U3: Into<Imm>> Vle16VEmitter<Vp, Gp, U2, U3> for Assembler<'_> {
    fn vle16_v(&mut self, vd: Vp, rs1: Gp, vm: U2, nf: U3) {
        self.emit_n(
            Opcode::VLE16V as i64,
            &[
                vd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
                Into::<Imm>::into(nf).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>, U3: Into<Imm>> Vle16FfVEmitter<Vp, Gp, U2, U3> for Assembler<'_> {
    fn vle16ff_v(&mut self, vd: Vp, rs1: Gp, vm: U2, nf: U3) {
        self.emit_n(
            Opcode::VLE16FFV as i64,
            &[
                vd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
                Into::<Imm>::into(nf).as_operand(),
            ],
        );
    }
}

impl Vle1VEmitter<Vp, Gp> for Assembler<'_> {
    fn vle1_v(&mut self, vd: Vp, rs1: Gp) {
        self.emit_n(Opcode::VLE1V as i64, &[vd.as_operand(), rs1.as_operand()]);
    }
}

impl<U2: Into<Imm>, U3: Into<Imm>> Vle32VEmitter<Vp, Gp, U2, U3> for Assembler<'_> {
    fn vle32_v(&mut self, vd: Vp, rs1: Gp, vm: U2, nf: U3) {
        self.emit_n(
            Opcode::VLE32V as i64,
            &[
                vd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
                Into::<Imm>::into(nf).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>, U3: Into<Imm>> Vle32FfVEmitter<Vp, Gp, U2, U3> for Assembler<'_> {
    fn vle32ff_v(&mut self, vd: Vp, rs1: Gp, vm: U2, nf: U3) {
        self.emit_n(
            Opcode::VLE32FFV as i64,
            &[
                vd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
                Into::<Imm>::into(nf).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>, U3: Into<Imm>> Vle64VEmitter<Vp, Gp, U2, U3> for Assembler<'_> {
    fn vle64_v(&mut self, vd: Vp, rs1: Gp, vm: U2, nf: U3) {
        self.emit_n(
            Opcode::VLE64V as i64,
            &[
                vd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
                Into::<Imm>::into(nf).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>, U3: Into<Imm>> Vle64FfVEmitter<Vp, Gp, U2, U3> for Assembler<'_> {
    fn vle64ff_v(&mut self, vd: Vp, rs1: Gp, vm: U2, nf: U3) {
        self.emit_n(
            Opcode::VLE64FFV as i64,
            &[
                vd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
                Into::<Imm>::into(nf).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>, U3: Into<Imm>> Vle8VEmitter<Vp, Gp, U2, U3> for Assembler<'_> {
    fn vle8_v(&mut self, vd: Vp, rs1: Gp, vm: U2, nf: U3) {
        self.emit_n(
            Opcode::VLE8V as i64,
            &[
                vd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
                Into::<Imm>::into(nf).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>, U3: Into<Imm>> Vle8FfVEmitter<Vp, Gp, U2, U3> for Assembler<'_> {
    fn vle8ff_v(&mut self, vd: Vp, rs1: Gp, vm: U2, nf: U3) {
        self.emit_n(
            Opcode::VLE8FFV as i64,
            &[
                vd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
                Into::<Imm>::into(nf).as_operand(),
            ],
        );
    }
}

impl VlmVEmitter<Vp, Gp> for Assembler<'_> {
    fn vlm_v(&mut self, vd: Vp, rs1: Gp) {
        self.emit_n(Opcode::VLMV as i64, &[vd.as_operand(), rs1.as_operand()]);
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> Vloxei16VEmitter<Vp, Gp, Vp, U3, U4> for Assembler<'_> {
    fn vloxei16_v(&mut self, vd: Vp, rs1: Gp, vs2: Vp, vm: U3, nf: U4) {
        self.emit_n(
            Opcode::VLOXEI16V as i64,
            &[
                vd.as_operand(),
                rs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
                Into::<Imm>::into(nf).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> Vloxei32VEmitter<Vp, Gp, Vp, U3, U4> for Assembler<'_> {
    fn vloxei32_v(&mut self, vd: Vp, rs1: Gp, vs2: Vp, vm: U3, nf: U4) {
        self.emit_n(
            Opcode::VLOXEI32V as i64,
            &[
                vd.as_operand(),
                rs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
                Into::<Imm>::into(nf).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> Vloxei64VEmitter<Vp, Gp, Vp, U3, U4> for Assembler<'_> {
    fn vloxei64_v(&mut self, vd: Vp, rs1: Gp, vs2: Vp, vm: U3, nf: U4) {
        self.emit_n(
            Opcode::VLOXEI64V as i64,
            &[
                vd.as_operand(),
                rs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
                Into::<Imm>::into(nf).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> Vloxei8VEmitter<Vp, Gp, Vp, U3, U4> for Assembler<'_> {
    fn vloxei8_v(&mut self, vd: Vp, rs1: Gp, vs2: Vp, vm: U3, nf: U4) {
        self.emit_n(
            Opcode::VLOXEI8V as i64,
            &[
                vd.as_operand(),
                rs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
                Into::<Imm>::into(nf).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> Vlse16VEmitter<Vp, Gp, Gp, U3, U4> for Assembler<'_> {
    fn vlse16_v(&mut self, vd: Vp, rs1: Gp, rs2: Gp, vm: U3, nf: U4) {
        self.emit_n(
            Opcode::VLSE16V as i64,
            &[
                vd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
                Into::<Imm>::into(nf).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> Vlse32VEmitter<Vp, Gp, Gp, U3, U4> for Assembler<'_> {
    fn vlse32_v(&mut self, vd: Vp, rs1: Gp, rs2: Gp, vm: U3, nf: U4) {
        self.emit_n(
            Opcode::VLSE32V as i64,
            &[
                vd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
                Into::<Imm>::into(nf).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> Vlse64VEmitter<Vp, Gp, Gp, U3, U4> for Assembler<'_> {
    fn vlse64_v(&mut self, vd: Vp, rs1: Gp, rs2: Gp, vm: U3, nf: U4) {
        self.emit_n(
            Opcode::VLSE64V as i64,
            &[
                vd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
                Into::<Imm>::into(nf).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> Vlse8VEmitter<Vp, Gp, Gp, U3, U4> for Assembler<'_> {
    fn vlse8_v(&mut self, vd: Vp, rs1: Gp, rs2: Gp, vm: U3, nf: U4) {
        self.emit_n(
            Opcode::VLSE8V as i64,
            &[
                vd.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
                Into::<Imm>::into(nf).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> Vluxei16VEmitter<Vp, Gp, Vp, U3, U4> for Assembler<'_> {
    fn vluxei16_v(&mut self, vd: Vp, rs1: Gp, vs2: Vp, vm: U3, nf: U4) {
        self.emit_n(
            Opcode::VLUXEI16V as i64,
            &[
                vd.as_operand(),
                rs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
                Into::<Imm>::into(nf).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> Vluxei32VEmitter<Vp, Gp, Vp, U3, U4> for Assembler<'_> {
    fn vluxei32_v(&mut self, vd: Vp, rs1: Gp, vs2: Vp, vm: U3, nf: U4) {
        self.emit_n(
            Opcode::VLUXEI32V as i64,
            &[
                vd.as_operand(),
                rs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
                Into::<Imm>::into(nf).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> Vluxei64VEmitter<Vp, Gp, Vp, U3, U4> for Assembler<'_> {
    fn vluxei64_v(&mut self, vd: Vp, rs1: Gp, vs2: Vp, vm: U3, nf: U4) {
        self.emit_n(
            Opcode::VLUXEI64V as i64,
            &[
                vd.as_operand(),
                rs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
                Into::<Imm>::into(nf).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> Vluxei8VEmitter<Vp, Gp, Vp, U3, U4> for Assembler<'_> {
    fn vluxei8_v(&mut self, vd: Vp, rs1: Gp, vs2: Vp, vm: U3, nf: U4) {
        self.emit_n(
            Opcode::VLUXEI8V as i64,
            &[
                vd.as_operand(),
                rs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
                Into::<Imm>::into(nf).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VmaccVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vmacc_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VMACCVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VmaccVxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vmacc_vx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VMACCVX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> VmadcViEmitter<Vp, Vp, U2> for Assembler<'_> {
    fn vmadc_vi(&mut self, vd: Vp, vs2: Vp, simm5: U2) {
        self.emit_n(
            Opcode::VMADCVI as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(simm5).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> VmadcVimEmitter<Vp, Vp, U2> for Assembler<'_> {
    fn vmadc_vim(&mut self, vd: Vp, vs2: Vp, simm5: U2) {
        self.emit_n(
            Opcode::VMADCVIM as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(simm5).as_operand(),
            ],
        );
    }
}

impl VmadcVvEmitter<Vp, Vp, Vp> for Assembler<'_> {
    fn vmadc_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp) {
        self.emit_n(
            Opcode::VMADCVV as i64,
            &[vd.as_operand(), vs1.as_operand(), vs2.as_operand()],
        );
    }
}

impl VmadcVvmEmitter<Vp, Vp, Vp> for Assembler<'_> {
    fn vmadc_vvm(&mut self, vd: Vp, vs1: Vp, vs2: Vp) {
        self.emit_n(
            Opcode::VMADCVVM as i64,
            &[vd.as_operand(), vs1.as_operand(), vs2.as_operand()],
        );
    }
}

impl VmadcVxEmitter<Vp, Gp, Vp> for Assembler<'_> {
    fn vmadc_vx(&mut self, vd: Vp, rs1: Gp, vs2: Vp) {
        self.emit_n(
            Opcode::VMADCVX as i64,
            &[vd.as_operand(), rs1.as_operand(), vs2.as_operand()],
        );
    }
}

impl VmadcVxmEmitter<Vp, Gp, Vp> for Assembler<'_> {
    fn vmadc_vxm(&mut self, vd: Vp, rs1: Gp, vs2: Vp) {
        self.emit_n(
            Opcode::VMADCVXM as i64,
            &[vd.as_operand(), rs1.as_operand(), vs2.as_operand()],
        );
    }
}

impl<U3: Into<Imm>> VmaddVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vmadd_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VMADDVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VmaddVxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vmadd_vx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VMADDVX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl VmandMmEmitter<Vp, Vp, Vp> for Assembler<'_> {
    fn vmand_mm(&mut self, vd: Vp, vs1: Vp, vs2: Vp) {
        self.emit_n(
            Opcode::VMANDMM as i64,
            &[vd.as_operand(), vs1.as_operand(), vs2.as_operand()],
        );
    }
}

impl VmandnMmEmitter<Vp, Vp, Vp> for Assembler<'_> {
    fn vmandn_mm(&mut self, vd: Vp, vs1: Vp, vs2: Vp) {
        self.emit_n(
            Opcode::VMANDNMM as i64,
            &[vd.as_operand(), vs1.as_operand(), vs2.as_operand()],
        );
    }
}

impl<U3: Into<Imm>> VmandnotMmEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vmandnot_mm(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VMANDNOTMM as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VmaxVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vmax_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VMAXVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VmaxVxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vmax_vx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VMAXVX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VmaxuVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vmaxu_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VMAXUVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VmaxuVxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vmaxu_vx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VMAXUVX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> VmergeVimEmitter<Vp, Vp, U2> for Assembler<'_> {
    fn vmerge_vim(&mut self, vd: Vp, vs2: Vp, simm5: U2) {
        self.emit_n(
            Opcode::VMERGEVIM as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(simm5).as_operand(),
            ],
        );
    }
}

impl VmergeVvmEmitter<Vp, Vp, Vp> for Assembler<'_> {
    fn vmerge_vvm(&mut self, vd: Vp, vs1: Vp, vs2: Vp) {
        self.emit_n(
            Opcode::VMERGEVVM as i64,
            &[vd.as_operand(), vs1.as_operand(), vs2.as_operand()],
        );
    }
}

impl VmergeVxmEmitter<Vp, Gp, Vp> for Assembler<'_> {
    fn vmerge_vxm(&mut self, vd: Vp, rs1: Gp, vs2: Vp) {
        self.emit_n(
            Opcode::VMERGEVXM as i64,
            &[vd.as_operand(), rs1.as_operand(), vs2.as_operand()],
        );
    }
}

impl<U3: Into<Imm>> VmfeqVfEmitter<Vp, Vp, Fp, U3> for Assembler<'_> {
    fn vmfeq_vf(&mut self, vd: Vp, vs2: Vp, rs1: Fp, vm: U3) {
        self.emit_n(
            Opcode::VMFEQVF as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VmfeqVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vmfeq_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VMFEQVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VmfgeVfEmitter<Vp, Vp, Fp, U3> for Assembler<'_> {
    fn vmfge_vf(&mut self, vd: Vp, vs2: Vp, rs1: Fp, vm: U3) {
        self.emit_n(
            Opcode::VMFGEVF as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VmfgtVfEmitter<Vp, Vp, Fp, U3> for Assembler<'_> {
    fn vmfgt_vf(&mut self, vd: Vp, vs2: Vp, rs1: Fp, vm: U3) {
        self.emit_n(
            Opcode::VMFGTVF as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VmfleVfEmitter<Vp, Vp, Fp, U3> for Assembler<'_> {
    fn vmfle_vf(&mut self, vd: Vp, vs2: Vp, rs1: Fp, vm: U3) {
        self.emit_n(
            Opcode::VMFLEVF as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VmfleVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vmfle_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VMFLEVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VmfltVfEmitter<Vp, Vp, Fp, U3> for Assembler<'_> {
    fn vmflt_vf(&mut self, vd: Vp, vs2: Vp, rs1: Fp, vm: U3) {
        self.emit_n(
            Opcode::VMFLTVF as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VmfltVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vmflt_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VMFLTVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VmfneVfEmitter<Vp, Vp, Fp, U3> for Assembler<'_> {
    fn vmfne_vf(&mut self, vd: Vp, vs2: Vp, rs1: Fp, vm: U3) {
        self.emit_n(
            Opcode::VMFNEVF as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VmfneVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vmfne_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VMFNEVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VminVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vmin_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VMINVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VminVxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vmin_vx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VMINVX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VminuVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vminu_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VMINUVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VminuVxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vminu_vx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VMINUVX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl VmnandMmEmitter<Vp, Vp, Vp> for Assembler<'_> {
    fn vmnand_mm(&mut self, vd: Vp, vs1: Vp, vs2: Vp) {
        self.emit_n(
            Opcode::VMNANDMM as i64,
            &[vd.as_operand(), vs1.as_operand(), vs2.as_operand()],
        );
    }
}

impl VmnorMmEmitter<Vp, Vp, Vp> for Assembler<'_> {
    fn vmnor_mm(&mut self, vd: Vp, vs1: Vp, vs2: Vp) {
        self.emit_n(
            Opcode::VMNORMM as i64,
            &[vd.as_operand(), vs1.as_operand(), vs2.as_operand()],
        );
    }
}

impl VmorMmEmitter<Vp, Vp, Vp> for Assembler<'_> {
    fn vmor_mm(&mut self, vd: Vp, vs1: Vp, vs2: Vp) {
        self.emit_n(
            Opcode::VMORMM as i64,
            &[vd.as_operand(), vs1.as_operand(), vs2.as_operand()],
        );
    }
}

impl VmornMmEmitter<Vp, Vp, Vp> for Assembler<'_> {
    fn vmorn_mm(&mut self, vd: Vp, vs1: Vp, vs2: Vp) {
        self.emit_n(
            Opcode::VMORNMM as i64,
            &[vd.as_operand(), vs1.as_operand(), vs2.as_operand()],
        );
    }
}

impl<U3: Into<Imm>> VmornotMmEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vmornot_mm(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VMORNOTMM as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl VmsbcVvEmitter<Vp, Vp, Vp> for Assembler<'_> {
    fn vmsbc_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp) {
        self.emit_n(
            Opcode::VMSBCVV as i64,
            &[vd.as_operand(), vs1.as_operand(), vs2.as_operand()],
        );
    }
}

impl VmsbcVvmEmitter<Vp, Vp, Vp> for Assembler<'_> {
    fn vmsbc_vvm(&mut self, vd: Vp, vs1: Vp, vs2: Vp) {
        self.emit_n(
            Opcode::VMSBCVVM as i64,
            &[vd.as_operand(), vs1.as_operand(), vs2.as_operand()],
        );
    }
}

impl VmsbcVxEmitter<Vp, Gp, Vp> for Assembler<'_> {
    fn vmsbc_vx(&mut self, vd: Vp, rs1: Gp, vs2: Vp) {
        self.emit_n(
            Opcode::VMSBCVX as i64,
            &[vd.as_operand(), rs1.as_operand(), vs2.as_operand()],
        );
    }
}

impl VmsbcVxmEmitter<Vp, Gp, Vp> for Assembler<'_> {
    fn vmsbc_vxm(&mut self, vd: Vp, rs1: Gp, vs2: Vp) {
        self.emit_n(
            Opcode::VMSBCVXM as i64,
            &[vd.as_operand(), rs1.as_operand(), vs2.as_operand()],
        );
    }
}

impl<U2: Into<Imm>> VmsbfMEmitter<Vp, Vp, U2> for Assembler<'_> {
    fn vmsbf_m(&mut self, vd: Vp, vs2: Vp, vm: U2) {
        self.emit_n(
            Opcode::VMSBFM as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>, U3: Into<Imm>> VmseqViEmitter<Vp, Vp, U2, U3> for Assembler<'_> {
    fn vmseq_vi(&mut self, vd: Vp, vs2: Vp, simm5: U2, vm: U3) {
        self.emit_n(
            Opcode::VMSEQVI as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(simm5).as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VmseqVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vmseq_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VMSEQVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VmseqVxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vmseq_vx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VMSEQVX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>, U3: Into<Imm>> VmsgtViEmitter<Vp, Vp, U2, U3> for Assembler<'_> {
    fn vmsgt_vi(&mut self, vd: Vp, vs2: Vp, simm5: U2, vm: U3) {
        self.emit_n(
            Opcode::VMSGTVI as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(simm5).as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VmsgtVxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vmsgt_vx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VMSGTVX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>, U3: Into<Imm>> VmsgtuViEmitter<Vp, Vp, U2, U3> for Assembler<'_> {
    fn vmsgtu_vi(&mut self, vd: Vp, vs2: Vp, simm5: U2, vm: U3) {
        self.emit_n(
            Opcode::VMSGTUVI as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(simm5).as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VmsgtuVxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vmsgtu_vx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VMSGTUVX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> VmsifMEmitter<Vp, Vp, U2> for Assembler<'_> {
    fn vmsif_m(&mut self, vd: Vp, vs2: Vp, vm: U2) {
        self.emit_n(
            Opcode::VMSIFM as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>, U3: Into<Imm>> VmsleViEmitter<Vp, Vp, U2, U3> for Assembler<'_> {
    fn vmsle_vi(&mut self, vd: Vp, vs2: Vp, simm5: U2, vm: U3) {
        self.emit_n(
            Opcode::VMSLEVI as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(simm5).as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VmsleVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vmsle_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VMSLEVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VmsleVxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vmsle_vx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VMSLEVX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>, U3: Into<Imm>> VmsleuViEmitter<Vp, Vp, U2, U3> for Assembler<'_> {
    fn vmsleu_vi(&mut self, vd: Vp, vs2: Vp, simm5: U2, vm: U3) {
        self.emit_n(
            Opcode::VMSLEUVI as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(simm5).as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VmsleuVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vmsleu_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VMSLEUVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VmsleuVxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vmsleu_vx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VMSLEUVX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VmsltVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vmslt_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VMSLTVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VmsltVxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vmslt_vx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VMSLTVX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VmsltuVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vmsltu_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VMSLTUVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VmsltuVxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vmsltu_vx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VMSLTUVX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>, U3: Into<Imm>> VmsneViEmitter<Vp, Vp, U2, U3> for Assembler<'_> {
    fn vmsne_vi(&mut self, vd: Vp, vs2: Vp, simm5: U2, vm: U3) {
        self.emit_n(
            Opcode::VMSNEVI as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(simm5).as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VmsneVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vmsne_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VMSNEVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VmsneVxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vmsne_vx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VMSNEVX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> VmsofMEmitter<Vp, Vp, U2> for Assembler<'_> {
    fn vmsof_m(&mut self, vd: Vp, vs2: Vp, vm: U2) {
        self.emit_n(
            Opcode::VMSOFM as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VmulVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vmul_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VMULVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VmulVxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vmul_vx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VMULVX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VmulhVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vmulh_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VMULHVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VmulhVxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vmulh_vx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VMULHVX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VmulhsuVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vmulhsu_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VMULHSUVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VmulhsuVxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vmulhsu_vx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VMULHSUVX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VmulhuVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vmulhu_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VMULHUVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VmulhuVxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vmulhu_vx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VMULHUVX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl Vmv1RVEmitter<Vp, Vp> for Assembler<'_> {
    fn vmv1r_v(&mut self, vd: Vp, vs2: Vp) {
        self.emit_n(Opcode::VMV1RV as i64, &[vd.as_operand(), vs2.as_operand()]);
    }
}

impl Vmv2RVEmitter<Vp, Vp> for Assembler<'_> {
    fn vmv2r_v(&mut self, vd: Vp, vs2: Vp) {
        self.emit_n(Opcode::VMV2RV as i64, &[vd.as_operand(), vs2.as_operand()]);
    }
}

impl Vmv4RVEmitter<Vp, Vp> for Assembler<'_> {
    fn vmv4r_v(&mut self, vd: Vp, vs2: Vp) {
        self.emit_n(Opcode::VMV4RV as i64, &[vd.as_operand(), vs2.as_operand()]);
    }
}

impl Vmv8RVEmitter<Vp, Vp> for Assembler<'_> {
    fn vmv8r_v(&mut self, vd: Vp, vs2: Vp) {
        self.emit_n(Opcode::VMV8RV as i64, &[vd.as_operand(), vs2.as_operand()]);
    }
}

impl VmvSXEmitter<Vp, Gp> for Assembler<'_> {
    fn vmv_s_x(&mut self, vd: Vp, rs1: Gp) {
        self.emit_n(Opcode::VMVSX as i64, &[vd.as_operand(), rs1.as_operand()]);
    }
}

impl<U1: Into<Imm>> VmvVIEmitter<Vp, U1> for Assembler<'_> {
    fn vmv_v_i(&mut self, vd: Vp, simm5: U1) {
        self.emit_n(
            Opcode::VMVVI as i64,
            &[vd.as_operand(), Into::<Imm>::into(simm5).as_operand()],
        );
    }
}

impl VmvVVEmitter<Vp, Vp> for Assembler<'_> {
    fn vmv_v_v(&mut self, vd: Vp, vs1: Vp) {
        self.emit_n(Opcode::VMVVV as i64, &[vd.as_operand(), vs1.as_operand()]);
    }
}

impl VmvVXEmitter<Vp, Gp> for Assembler<'_> {
    fn vmv_v_x(&mut self, vd: Vp, rs1: Gp) {
        self.emit_n(Opcode::VMVVX as i64, &[vd.as_operand(), rs1.as_operand()]);
    }
}

impl VmvXSEmitter<Gp, Vp> for Assembler<'_> {
    fn vmv_x_s(&mut self, rd: Gp, vs2: Vp) {
        self.emit_n(Opcode::VMVXS as i64, &[rd.as_operand(), vs2.as_operand()]);
    }
}

impl VmxnorMmEmitter<Vp, Vp, Vp> for Assembler<'_> {
    fn vmxnor_mm(&mut self, vd: Vp, vs1: Vp, vs2: Vp) {
        self.emit_n(
            Opcode::VMXNORMM as i64,
            &[vd.as_operand(), vs1.as_operand(), vs2.as_operand()],
        );
    }
}

impl VmxorMmEmitter<Vp, Vp, Vp> for Assembler<'_> {
    fn vmxor_mm(&mut self, vd: Vp, vs1: Vp, vs2: Vp) {
        self.emit_n(
            Opcode::VMXORMM as i64,
            &[vd.as_operand(), vs1.as_operand(), vs2.as_operand()],
        );
    }
}

impl<U2: Into<Imm>, U3: Into<Imm>> VnclipWiEmitter<Vp, Vp, U2, U3> for Assembler<'_> {
    fn vnclip_wi(&mut self, vd: Vp, vs2: Vp, zimm5: U2, vm: U3) {
        self.emit_n(
            Opcode::VNCLIPWI as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(zimm5).as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VnclipWvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vnclip_wv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VNCLIPWV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VnclipWxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vnclip_wx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VNCLIPWX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>, U3: Into<Imm>> VnclipuWiEmitter<Vp, Vp, U2, U3> for Assembler<'_> {
    fn vnclipu_wi(&mut self, vd: Vp, vs2: Vp, zimm5: U2, vm: U3) {
        self.emit_n(
            Opcode::VNCLIPUWI as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(zimm5).as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VnclipuWvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vnclipu_wv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VNCLIPUWV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VnclipuWxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vnclipu_wx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VNCLIPUWX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VnmsacVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vnmsac_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VNMSACVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VnmsacVxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vnmsac_vx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VNMSACVX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VnmsubVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vnmsub_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VNMSUBVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VnmsubVxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vnmsub_vx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VNMSUBVX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>, U3: Into<Imm>> VnsraWiEmitter<Vp, Vp, U2, U3> for Assembler<'_> {
    fn vnsra_wi(&mut self, vd: Vp, vs2: Vp, zimm5: U2, vm: U3) {
        self.emit_n(
            Opcode::VNSRAWI as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(zimm5).as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VnsraWvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vnsra_wv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VNSRAWV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VnsraWxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vnsra_wx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VNSRAWX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>, U3: Into<Imm>> VnsrlWiEmitter<Vp, Vp, U2, U3> for Assembler<'_> {
    fn vnsrl_wi(&mut self, vd: Vp, vs2: Vp, zimm5: U2, vm: U3) {
        self.emit_n(
            Opcode::VNSRLWI as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(zimm5).as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VnsrlWvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vnsrl_wv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VNSRLWV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VnsrlWxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vnsrl_wx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VNSRLWX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>, U3: Into<Imm>> VorViEmitter<Vp, Vp, U2, U3> for Assembler<'_> {
    fn vor_vi(&mut self, vd: Vp, vs2: Vp, simm5: U2, vm: U3) {
        self.emit_n(
            Opcode::VORVI as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(simm5).as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VorVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vor_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VORVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VorVxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vor_vx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VORVX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> VpopcMEmitter<Gp, Vp, U2> for Assembler<'_> {
    fn vpopc_m(&mut self, rd: Gp, vs2: Vp, vm: U2) {
        self.emit_n(
            Opcode::VPOPCM as i64,
            &[
                rd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VredandVsEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vredand_vs(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VREDANDVS as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VredmaxVsEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vredmax_vs(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VREDMAXVS as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VredmaxuVsEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vredmaxu_vs(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VREDMAXUVS as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VredminVsEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vredmin_vs(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VREDMINVS as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VredminuVsEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vredminu_vs(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VREDMINUVS as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VredorVsEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vredor_vs(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VREDORVS as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VredsumVsEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vredsum_vs(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VREDSUMVS as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VredxorVsEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vredxor_vs(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VREDXORVS as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VremVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vrem_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VREMVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VremVxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vrem_vx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VREMVX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VremuVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vremu_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VREMUVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VremuVxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vremu_vx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VREMUVX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> Vrev8VEmitter<Vp, Vp, U2> for Assembler<'_> {
    fn vrev8_v(&mut self, vd: Vp, vs2: Vp, vm: U2) {
        self.emit_n(
            Opcode::VREV8V as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>, U3: Into<Imm>> VrgatherViEmitter<Vp, Vp, U2, U3> for Assembler<'_> {
    fn vrgather_vi(&mut self, vd: Vp, vs2: Vp, zimm5: U2, vm: U3) {
        self.emit_n(
            Opcode::VRGATHERVI as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(zimm5).as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VrgatherVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vrgather_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VRGATHERVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VrgatherVxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vrgather_vx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VRGATHERVX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> Vrgatherei16VvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vrgatherei16_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VRGATHEREI16VV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VrolVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vrol_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VROLVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VrolVxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vrol_vx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VROLVX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>, U3: Into<Imm>> VrorViEmitter<Vp, Vp, U2, U3> for Assembler<'_> {
    fn vror_vi(&mut self, vd: Vp, vs2: Vp, zimm6lohi: U2, vm: U3) {
        self.emit_n(
            Opcode::VRORVI as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(zimm6lohi).as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VrorVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vror_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VRORVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VrorVxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vror_vx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VRORVX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>, U3: Into<Imm>> VrsubViEmitter<Vp, Vp, U2, U3> for Assembler<'_> {
    fn vrsub_vi(&mut self, vd: Vp, vs2: Vp, simm5: U2, vm: U3) {
        self.emit_n(
            Opcode::VRSUBVI as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(simm5).as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VrsubVxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vrsub_vx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VRSUBVX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl Vs1RVEmitter<Vp, Gp> for Assembler<'_> {
    fn vs1r_v(&mut self, vs3: Vp, rs1: Gp) {
        self.emit_n(Opcode::VS1RV as i64, &[vs3.as_operand(), rs1.as_operand()]);
    }
}

impl Vs2RVEmitter<Vp, Gp> for Assembler<'_> {
    fn vs2r_v(&mut self, vs3: Vp, rs1: Gp) {
        self.emit_n(Opcode::VS2RV as i64, &[vs3.as_operand(), rs1.as_operand()]);
    }
}

impl Vs4RVEmitter<Vp, Gp> for Assembler<'_> {
    fn vs4r_v(&mut self, vs3: Vp, rs1: Gp) {
        self.emit_n(Opcode::VS4RV as i64, &[vs3.as_operand(), rs1.as_operand()]);
    }
}

impl Vs8RVEmitter<Vp, Gp> for Assembler<'_> {
    fn vs8r_v(&mut self, vs3: Vp, rs1: Gp) {
        self.emit_n(Opcode::VS8RV as i64, &[vs3.as_operand(), rs1.as_operand()]);
    }
}

impl<U2: Into<Imm>, U3: Into<Imm>> VsaddViEmitter<Vp, Vp, U2, U3> for Assembler<'_> {
    fn vsadd_vi(&mut self, vd: Vp, vs2: Vp, simm5: U2, vm: U3) {
        self.emit_n(
            Opcode::VSADDVI as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(simm5).as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VsaddVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vsadd_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VSADDVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VsaddVxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vsadd_vx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VSADDVX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>, U3: Into<Imm>> VsadduViEmitter<Vp, Vp, U2, U3> for Assembler<'_> {
    fn vsaddu_vi(&mut self, vd: Vp, vs2: Vp, simm5: U2, vm: U3) {
        self.emit_n(
            Opcode::VSADDUVI as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(simm5).as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VsadduVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vsaddu_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VSADDUVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VsadduVxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vsaddu_vx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VSADDUVX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl VsbcVvmEmitter<Vp, Vp, Vp> for Assembler<'_> {
    fn vsbc_vvm(&mut self, vd: Vp, vs1: Vp, vs2: Vp) {
        self.emit_n(
            Opcode::VSBCVVM as i64,
            &[vd.as_operand(), vs1.as_operand(), vs2.as_operand()],
        );
    }
}

impl VsbcVxmEmitter<Vp, Gp, Vp> for Assembler<'_> {
    fn vsbc_vxm(&mut self, vd: Vp, rs1: Gp, vs2: Vp) {
        self.emit_n(
            Opcode::VSBCVXM as i64,
            &[vd.as_operand(), rs1.as_operand(), vs2.as_operand()],
        );
    }
}

impl<U2: Into<Imm>, U3: Into<Imm>> Vse16VEmitter<Vp, Gp, U2, U3> for Assembler<'_> {
    fn vse16_v(&mut self, vs3: Vp, rs1: Gp, vm: U2, nf: U3) {
        self.emit_n(
            Opcode::VSE16V as i64,
            &[
                vs3.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
                Into::<Imm>::into(nf).as_operand(),
            ],
        );
    }
}

impl Vse1VEmitter<Vp, Gp> for Assembler<'_> {
    fn vse1_v(&mut self, vs3: Vp, rs1: Gp) {
        self.emit_n(Opcode::VSE1V as i64, &[vs3.as_operand(), rs1.as_operand()]);
    }
}

impl<U2: Into<Imm>, U3: Into<Imm>> Vse32VEmitter<Vp, Gp, U2, U3> for Assembler<'_> {
    fn vse32_v(&mut self, vs3: Vp, rs1: Gp, vm: U2, nf: U3) {
        self.emit_n(
            Opcode::VSE32V as i64,
            &[
                vs3.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
                Into::<Imm>::into(nf).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>, U3: Into<Imm>> Vse64VEmitter<Vp, Gp, U2, U3> for Assembler<'_> {
    fn vse64_v(&mut self, vs3: Vp, rs1: Gp, vm: U2, nf: U3) {
        self.emit_n(
            Opcode::VSE64V as i64,
            &[
                vs3.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
                Into::<Imm>::into(nf).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>, U3: Into<Imm>> Vse8VEmitter<Vp, Gp, U2, U3> for Assembler<'_> {
    fn vse8_v(&mut self, vs3: Vp, rs1: Gp, vm: U2, nf: U3) {
        self.emit_n(
            Opcode::VSE8V as i64,
            &[
                vs3.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
                Into::<Imm>::into(nf).as_operand(),
            ],
        );
    }
}

impl<U1: Into<Imm>, U2: Into<Imm>> VsetivliEmitter<Gp, U1, U2> for Assembler<'_> {
    fn vsetivli(&mut self, rd: Gp, zimm5: U1, zimm10: U2) {
        self.emit_n(
            Opcode::VSETIVLI as i64,
            &[
                rd.as_operand(),
                Into::<Imm>::into(zimm5).as_operand(),
                Into::<Imm>::into(zimm10).as_operand(),
            ],
        );
    }
}

impl VsetvlEmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn vsetvl(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::VSETVL as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl<U2: Into<Imm>> VsetvliEmitter<Gp, Gp, U2> for Assembler<'_> {
    fn vsetvli(&mut self, rd: Gp, rs1: Gp, zimm11: U2) {
        self.emit_n(
            Opcode::VSETVLI as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(zimm11).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> VsextVf2Emitter<Vp, Vp, U2> for Assembler<'_> {
    fn vsext_vf2(&mut self, vd: Vp, vs2: Vp, vm: U2) {
        self.emit_n(
            Opcode::VSEXTVF2 as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> VsextVf4Emitter<Vp, Vp, U2> for Assembler<'_> {
    fn vsext_vf4(&mut self, vd: Vp, vs2: Vp, vm: U2) {
        self.emit_n(
            Opcode::VSEXTVF4 as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> VsextVf8Emitter<Vp, Vp, U2> for Assembler<'_> {
    fn vsext_vf8(&mut self, vd: Vp, vs2: Vp, vm: U2) {
        self.emit_n(
            Opcode::VSEXTVF8 as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl Vsha2ChVvEmitter<Vp, Vp, Vp> for Assembler<'_> {
    fn vsha2ch_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp) {
        self.emit_n(
            Opcode::VSHA2CHVV as i64,
            &[vd.as_operand(), vs1.as_operand(), vs2.as_operand()],
        );
    }
}

impl Vsha2ClVvEmitter<Vp, Vp, Vp> for Assembler<'_> {
    fn vsha2cl_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp) {
        self.emit_n(
            Opcode::VSHA2CLVV as i64,
            &[vd.as_operand(), vs1.as_operand(), vs2.as_operand()],
        );
    }
}

impl Vsha2MsVvEmitter<Vp, Vp, Vp> for Assembler<'_> {
    fn vsha2ms_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp) {
        self.emit_n(
            Opcode::VSHA2MSVV as i64,
            &[vd.as_operand(), vs1.as_operand(), vs2.as_operand()],
        );
    }
}

impl<U3: Into<Imm>> Vslide1DownVxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vslide1down_vx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VSLIDE1DOWNVX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> Vslide1UpVxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vslide1up_vx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VSLIDE1UPVX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>, U3: Into<Imm>> VslidedownViEmitter<Vp, Vp, U2, U3> for Assembler<'_> {
    fn vslidedown_vi(&mut self, vd: Vp, vs2: Vp, zimm5: U2, vm: U3) {
        self.emit_n(
            Opcode::VSLIDEDOWNVI as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(zimm5).as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VslidedownVxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vslidedown_vx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VSLIDEDOWNVX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>, U3: Into<Imm>> VslideupViEmitter<Vp, Vp, U2, U3> for Assembler<'_> {
    fn vslideup_vi(&mut self, vd: Vp, vs2: Vp, zimm5: U2, vm: U3) {
        self.emit_n(
            Opcode::VSLIDEUPVI as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(zimm5).as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VslideupVxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vslideup_vx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VSLIDEUPVX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>, U3: Into<Imm>> VsllViEmitter<Vp, Vp, U2, U3> for Assembler<'_> {
    fn vsll_vi(&mut self, vd: Vp, vs2: Vp, zimm5: U2, vm: U3) {
        self.emit_n(
            Opcode::VSLLVI as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(zimm5).as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VsllVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vsll_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VSLLVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VsllVxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vsll_vx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VSLLVX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> Vsm3CViEmitter<Vp, Vp, U2> for Assembler<'_> {
    fn vsm3c_vi(&mut self, vd: Vp, vs2: Vp, zimm5: U2) {
        self.emit_n(
            Opcode::VSM3CVI as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(zimm5).as_operand(),
            ],
        );
    }
}

impl Vsm3MeVvEmitter<Vp, Vp, Vp> for Assembler<'_> {
    fn vsm3me_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp) {
        self.emit_n(
            Opcode::VSM3MEVV as i64,
            &[vd.as_operand(), vs1.as_operand(), vs2.as_operand()],
        );
    }
}

impl<U2: Into<Imm>> Vsm4KViEmitter<Vp, Vp, U2> for Assembler<'_> {
    fn vsm4k_vi(&mut self, vd: Vp, vs2: Vp, zimm5: U2) {
        self.emit_n(
            Opcode::VSM4KVI as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(zimm5).as_operand(),
            ],
        );
    }
}

impl Vsm4RVsEmitter<Vp, Vp> for Assembler<'_> {
    fn vsm4r_vs(&mut self, vd: Vp, vs2: Vp) {
        self.emit_n(Opcode::VSM4RVS as i64, &[vd.as_operand(), vs2.as_operand()]);
    }
}

impl Vsm4RVvEmitter<Vp, Vp> for Assembler<'_> {
    fn vsm4r_vv(&mut self, vd: Vp, vs2: Vp) {
        self.emit_n(Opcode::VSM4RVV as i64, &[vd.as_operand(), vs2.as_operand()]);
    }
}

impl VsmVEmitter<Vp, Gp> for Assembler<'_> {
    fn vsm_v(&mut self, vs3: Vp, rs1: Gp) {
        self.emit_n(Opcode::VSMV as i64, &[vs3.as_operand(), rs1.as_operand()]);
    }
}

impl<U3: Into<Imm>> VsmulVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vsmul_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VSMULVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VsmulVxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vsmul_vx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VSMULVX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> Vsoxei16VEmitter<Vp, Gp, Vp, U3, U4> for Assembler<'_> {
    fn vsoxei16_v(&mut self, vs3: Vp, rs1: Gp, vs2: Vp, vm: U3, nf: U4) {
        self.emit_n(
            Opcode::VSOXEI16V as i64,
            &[
                vs3.as_operand(),
                rs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
                Into::<Imm>::into(nf).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> Vsoxei32VEmitter<Vp, Gp, Vp, U3, U4> for Assembler<'_> {
    fn vsoxei32_v(&mut self, vs3: Vp, rs1: Gp, vs2: Vp, vm: U3, nf: U4) {
        self.emit_n(
            Opcode::VSOXEI32V as i64,
            &[
                vs3.as_operand(),
                rs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
                Into::<Imm>::into(nf).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> Vsoxei64VEmitter<Vp, Gp, Vp, U3, U4> for Assembler<'_> {
    fn vsoxei64_v(&mut self, vs3: Vp, rs1: Gp, vs2: Vp, vm: U3, nf: U4) {
        self.emit_n(
            Opcode::VSOXEI64V as i64,
            &[
                vs3.as_operand(),
                rs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
                Into::<Imm>::into(nf).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> Vsoxei8VEmitter<Vp, Gp, Vp, U3, U4> for Assembler<'_> {
    fn vsoxei8_v(&mut self, vs3: Vp, rs1: Gp, vs2: Vp, vm: U3, nf: U4) {
        self.emit_n(
            Opcode::VSOXEI8V as i64,
            &[
                vs3.as_operand(),
                rs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
                Into::<Imm>::into(nf).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>, U3: Into<Imm>> VsraViEmitter<Vp, Vp, U2, U3> for Assembler<'_> {
    fn vsra_vi(&mut self, vd: Vp, vs2: Vp, zimm5: U2, vm: U3) {
        self.emit_n(
            Opcode::VSRAVI as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(zimm5).as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VsraVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vsra_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VSRAVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VsraVxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vsra_vx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VSRAVX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>, U3: Into<Imm>> VsrlViEmitter<Vp, Vp, U2, U3> for Assembler<'_> {
    fn vsrl_vi(&mut self, vd: Vp, vs2: Vp, zimm5: U2, vm: U3) {
        self.emit_n(
            Opcode::VSRLVI as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(zimm5).as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VsrlVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vsrl_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VSRLVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VsrlVxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vsrl_vx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VSRLVX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> Vsse16VEmitter<Vp, Gp, Gp, U3, U4> for Assembler<'_> {
    fn vsse16_v(&mut self, vs3: Vp, rs1: Gp, rs2: Gp, vm: U3, nf: U4) {
        self.emit_n(
            Opcode::VSSE16V as i64,
            &[
                vs3.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
                Into::<Imm>::into(nf).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> Vsse32VEmitter<Vp, Gp, Gp, U3, U4> for Assembler<'_> {
    fn vsse32_v(&mut self, vs3: Vp, rs1: Gp, rs2: Gp, vm: U3, nf: U4) {
        self.emit_n(
            Opcode::VSSE32V as i64,
            &[
                vs3.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
                Into::<Imm>::into(nf).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> Vsse64VEmitter<Vp, Gp, Gp, U3, U4> for Assembler<'_> {
    fn vsse64_v(&mut self, vs3: Vp, rs1: Gp, rs2: Gp, vm: U3, nf: U4) {
        self.emit_n(
            Opcode::VSSE64V as i64,
            &[
                vs3.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
                Into::<Imm>::into(nf).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> Vsse8VEmitter<Vp, Gp, Gp, U3, U4> for Assembler<'_> {
    fn vsse8_v(&mut self, vs3: Vp, rs1: Gp, rs2: Gp, vm: U3, nf: U4) {
        self.emit_n(
            Opcode::VSSE8V as i64,
            &[
                vs3.as_operand(),
                rs1.as_operand(),
                rs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
                Into::<Imm>::into(nf).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>, U3: Into<Imm>> VssraViEmitter<Vp, Vp, U2, U3> for Assembler<'_> {
    fn vssra_vi(&mut self, vd: Vp, vs2: Vp, zimm5: U2, vm: U3) {
        self.emit_n(
            Opcode::VSSRAVI as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(zimm5).as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VssraVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vssra_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VSSRAVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VssraVxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vssra_vx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VSSRAVX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>, U3: Into<Imm>> VssrlViEmitter<Vp, Vp, U2, U3> for Assembler<'_> {
    fn vssrl_vi(&mut self, vd: Vp, vs2: Vp, zimm5: U2, vm: U3) {
        self.emit_n(
            Opcode::VSSRLVI as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(zimm5).as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VssrlVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vssrl_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VSSRLVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VssrlVxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vssrl_vx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VSSRLVX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VssubVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vssub_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VSSUBVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VssubVxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vssub_vx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VSSUBVX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VssubuVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vssubu_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VSSUBUVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VssubuVxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vssubu_vx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VSSUBUVX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VsubVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vsub_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VSUBVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VsubVxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vsub_vx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VSUBVX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> Vsuxei16VEmitter<Vp, Gp, Vp, U3, U4> for Assembler<'_> {
    fn vsuxei16_v(&mut self, vs3: Vp, rs1: Gp, vs2: Vp, vm: U3, nf: U4) {
        self.emit_n(
            Opcode::VSUXEI16V as i64,
            &[
                vs3.as_operand(),
                rs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
                Into::<Imm>::into(nf).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> Vsuxei32VEmitter<Vp, Gp, Vp, U3, U4> for Assembler<'_> {
    fn vsuxei32_v(&mut self, vs3: Vp, rs1: Gp, vs2: Vp, vm: U3, nf: U4) {
        self.emit_n(
            Opcode::VSUXEI32V as i64,
            &[
                vs3.as_operand(),
                rs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
                Into::<Imm>::into(nf).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> Vsuxei64VEmitter<Vp, Gp, Vp, U3, U4> for Assembler<'_> {
    fn vsuxei64_v(&mut self, vs3: Vp, rs1: Gp, vs2: Vp, vm: U3, nf: U4) {
        self.emit_n(
            Opcode::VSUXEI64V as i64,
            &[
                vs3.as_operand(),
                rs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
                Into::<Imm>::into(nf).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>, U4: Into<Imm>> Vsuxei8VEmitter<Vp, Gp, Vp, U3, U4> for Assembler<'_> {
    fn vsuxei8_v(&mut self, vs3: Vp, rs1: Gp, vs2: Vp, vm: U3, nf: U4) {
        self.emit_n(
            Opcode::VSUXEI8V as i64,
            &[
                vs3.as_operand(),
                rs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
                Into::<Imm>::into(nf).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VwaddVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vwadd_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VWADDVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VwaddVxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vwadd_vx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VWADDVX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VwaddWvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vwadd_wv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VWADDWV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VwaddWxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vwadd_wx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VWADDWX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VwadduVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vwaddu_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VWADDUVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VwadduVxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vwaddu_vx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VWADDUVX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VwadduWvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vwaddu_wv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VWADDUWV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VwadduWxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vwaddu_wx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VWADDUWX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VwmaccVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vwmacc_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VWMACCVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VwmaccVxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vwmacc_vx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VWMACCVX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VwmaccsuVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vwmaccsu_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VWMACCSUVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VwmaccsuVxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vwmaccsu_vx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VWMACCSUVX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VwmaccuVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vwmaccu_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VWMACCUVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VwmaccuVxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vwmaccu_vx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VWMACCUVX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VwmaccusVxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vwmaccus_vx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VWMACCUSVX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VwmulVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vwmul_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VWMULVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VwmulVxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vwmul_vx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VWMULVX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VwmulsuVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vwmulsu_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VWMULSUVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VwmulsuVxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vwmulsu_vx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VWMULSUVX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VwmuluVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vwmulu_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VWMULUVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VwmuluVxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vwmulu_vx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VWMULUVX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VwredsumVsEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vwredsum_vs(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VWREDSUMVS as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VwredsumuVsEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vwredsumu_vs(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VWREDSUMUVS as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>, U3: Into<Imm>> VwsllViEmitter<Vp, Vp, U2, U3> for Assembler<'_> {
    fn vwsll_vi(&mut self, vd: Vp, vs2: Vp, zimm5: U2, vm: U3) {
        self.emit_n(
            Opcode::VWSLLVI as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(zimm5).as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VwsllVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vwsll_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VWSLLVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VwsllVxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vwsll_vx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VWSLLVX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VwsubVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vwsub_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VWSUBVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VwsubVxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vwsub_vx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VWSUBVX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VwsubWvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vwsub_wv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VWSUBWV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VwsubWxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vwsub_wx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VWSUBWX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VwsubuVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vwsubu_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VWSUBUVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VwsubuVxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vwsubu_vx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VWSUBUVX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VwsubuWvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vwsubu_wv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VWSUBUWV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VwsubuWxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vwsubu_wx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VWSUBUWX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>, U3: Into<Imm>> VxorViEmitter<Vp, Vp, U2, U3> for Assembler<'_> {
    fn vxor_vi(&mut self, vd: Vp, vs2: Vp, simm5: U2, vm: U3) {
        self.emit_n(
            Opcode::VXORVI as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(simm5).as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VxorVvEmitter<Vp, Vp, Vp, U3> for Assembler<'_> {
    fn vxor_vv(&mut self, vd: Vp, vs1: Vp, vs2: Vp, vm: U3) {
        self.emit_n(
            Opcode::VXORVV as i64,
            &[
                vd.as_operand(),
                vs1.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U3: Into<Imm>> VxorVxEmitter<Vp, Vp, Gp, U3> for Assembler<'_> {
    fn vxor_vx(&mut self, vd: Vp, vs2: Vp, rs1: Gp, vm: U3) {
        self.emit_n(
            Opcode::VXORVX as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> VzextVf2Emitter<Vp, Vp, U2> for Assembler<'_> {
    fn vzext_vf2(&mut self, vd: Vp, vs2: Vp, vm: U2) {
        self.emit_n(
            Opcode::VZEXTVF2 as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> VzextVf4Emitter<Vp, Vp, U2> for Assembler<'_> {
    fn vzext_vf4(&mut self, vd: Vp, vs2: Vp, vm: U2) {
        self.emit_n(
            Opcode::VZEXTVF4 as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl<U2: Into<Imm>> VzextVf8Emitter<Vp, Vp, U2> for Assembler<'_> {
    fn vzext_vf8(&mut self, vd: Vp, vs2: Vp, vm: U2) {
        self.emit_n(
            Opcode::VZEXTVF8 as i64,
            &[
                vd.as_operand(),
                vs2.as_operand(),
                Into::<Imm>::into(vm).as_operand(),
            ],
        );
    }
}

impl WfiEmitter for Assembler<'_> {
    fn wfi(&mut self) {
        self.emit_n(Opcode::WFI as i64, &[]);
    }
}

impl WrsNtoEmitter for Assembler<'_> {
    fn wrs_nto(&mut self) {
        self.emit_n(Opcode::WRSNTO as i64, &[]);
    }
}

impl WrsStoEmitter for Assembler<'_> {
    fn wrs_sto(&mut self) {
        self.emit_n(Opcode::WRSSTO as i64, &[]);
    }
}

impl XnorEmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn xnor(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::XNOR as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl XorEmitter<Gp, Gp, Gp> for Assembler<'_> {
    fn xor(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::XOR as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl<U2: Into<Imm>> XoriEmitter<Gp, Gp, U2> for Assembler<'_> {
    fn xori(&mut self, rd: Gp, rs1: Gp, imm: U2) {
        self.emit_n(
            Opcode::XORI as i64,
            &[
                rd.as_operand(),
                rs1.as_operand(),
                Into::<Imm>::into(imm).as_operand(),
            ],
        );
    }
}

impl Xperm4Emitter<Gp, Gp, Gp> for Assembler<'_> {
    fn xperm4(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::XPERM4 as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl Xperm8Emitter<Gp, Gp, Gp> for Assembler<'_> {
    fn xperm8(&mut self, rd: Gp, rs1: Gp, rs2: Gp) {
        self.emit_n(
            Opcode::XPERM8 as i64,
            &[rd.as_operand(), rs1.as_operand(), rs2.as_operand()],
        );
    }
}

impl ZextBEmitter<Gp, Gp> for Assembler<'_> {
    fn zext_b(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::ZEXTB as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl ZextHEmitter<Gp, Gp> for Assembler<'_> {
    fn zext_h(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::ZEXTH as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl ZextHRv32Emitter<Gp, Gp> for Assembler<'_> {
    fn zext_h_rv32(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(
            Opcode::ZEXTHRV32 as i64,
            &[rd.as_operand(), rs1.as_operand()],
        );
    }
}

impl ZextWEmitter<Gp, Gp> for Assembler<'_> {
    fn zext_w(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::ZEXTW as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl ZipEmitter<Gp, Gp> for Assembler<'_> {
    fn zip(&mut self, rd: Gp, rs1: Gp) {
        self.emit_n(Opcode::ZIP as i64, &[rd.as_operand(), rs1.as_operand()]);
    }
}

impl Assembler<'_> {
    /// Integer add
    ///
    /// Add the value in rs1 to rs2, and store the result in rd.
    /// Any overflow is thrown away.
    ///
    /// # Forms
    /// Assembly: `add xd, xs1, xs2`
    /// Rust: `add(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn add<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: AddEmitter<T0, T1, T2>,
    {
        <Self as AddEmitter<T0, T1, T2>>::add(self, rd, rs1, rs2);
    }
    /// Add unsigned word
    ///
    /// This instruction performs an XLEN-wide addition between rs2 and the
    /// zero-extended least-significant word of rs1.
    ///
    /// # Forms
    /// Assembly: `add.uw xd, xs1, xs2`
    /// Rust: `add_uw(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn add_uw<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: AddUwEmitter<T0, T1, T2>,
    {
        <Self as AddUwEmitter<T0, T1, T2>>::add_uw(self, rd, rs1, rs2);
    }
    /// Add immediate
    ///
    /// Add an immediate to the value in rs1, and store the result in rd
    ///
    /// # Forms
    /// Assembly: `addi xd, xs1, imm`
    /// Rust: `addi(rd, rs1, imm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `imm` — Immediate encoding value.
    pub fn addi<T0, T1, T2>(&mut self, rd: T0, rs1: T1, imm: T2)
    where
        Self: AddiEmitter<T0, T1, T2>,
    {
        <Self as AddiEmitter<T0, T1, T2>>::addi(self, rd, rs1, imm);
    }
    /// Add immediate word
    ///
    /// Add an immediate to the 32-bit value in rs1, and store the sign extended result in rd
    ///
    /// # Forms
    /// Assembly: `addiw xd, xs1, imm`
    /// Rust: `addiw(rd, rs1, imm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `imm` — Immediate encoding value.
    pub fn addiw<T0, T1, T2>(&mut self, rd: T0, rs1: T1, imm: T2)
    where
        Self: AddiwEmitter<T0, T1, T2>,
    {
        <Self as AddiwEmitter<T0, T1, T2>>::addiw(self, rd, rs1, imm);
    }
    /// Add word
    ///
    /// Add the 32-bit values in rs1 to rs2, and store the sign-extended result in rd.
    /// Any overflow is thrown away.
    ///
    /// # Forms
    /// Assembly: `addw xd, xs1, xs2`
    /// Rust: `addw(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn addw<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: AddwEmitter<T0, T1, T2>,
    {
        <Self as AddwEmitter<T0, T1, T2>>::addw(self, rd, rs1, rs2);
    }
    /// RISC-V `aes32dsi` instruction.
    ///
    /// # Forms
    /// Assembly: `aes32dsi xd, xs1, xs2, bs`
    /// Rust: `aes32dsi(rd, rs1, rs2, bs)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    /// - `bs` — Immediate encoding value.
    pub fn aes32dsi<T0, T1, T2, T3>(&mut self, rd: T0, rs1: T1, rs2: T2, bs: T3)
    where
        Self: Aes32DsiEmitter<T0, T1, T2, T3>,
    {
        <Self as Aes32DsiEmitter<T0, T1, T2, T3>>::aes32dsi(self, rd, rs1, rs2, bs);
    }
    /// RISC-V `aes32dsmi` instruction.
    ///
    /// # Forms
    /// Assembly: `aes32dsmi xd, xs1, xs2, bs`
    /// Rust: `aes32dsmi(rd, rs1, rs2, bs)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    /// - `bs` — Immediate encoding value.
    pub fn aes32dsmi<T0, T1, T2, T3>(&mut self, rd: T0, rs1: T1, rs2: T2, bs: T3)
    where
        Self: Aes32DsmiEmitter<T0, T1, T2, T3>,
    {
        <Self as Aes32DsmiEmitter<T0, T1, T2, T3>>::aes32dsmi(self, rd, rs1, rs2, bs);
    }
    /// RISC-V `aes32esi` instruction.
    ///
    /// # Forms
    /// Assembly: `aes32esi xd, xs1, xs2, bs`
    /// Rust: `aes32esi(rd, rs1, rs2, bs)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    /// - `bs` — Immediate encoding value.
    pub fn aes32esi<T0, T1, T2, T3>(&mut self, rd: T0, rs1: T1, rs2: T2, bs: T3)
    where
        Self: Aes32EsiEmitter<T0, T1, T2, T3>,
    {
        <Self as Aes32EsiEmitter<T0, T1, T2, T3>>::aes32esi(self, rd, rs1, rs2, bs);
    }
    /// RISC-V `aes32esmi` instruction.
    ///
    /// # Forms
    /// Assembly: `aes32esmi xd, xs1, xs2, bs`
    /// Rust: `aes32esmi(rd, rs1, rs2, bs)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    /// - `bs` — Immediate encoding value.
    pub fn aes32esmi<T0, T1, T2, T3>(&mut self, rd: T0, rs1: T1, rs2: T2, bs: T3)
    where
        Self: Aes32EsmiEmitter<T0, T1, T2, T3>,
    {
        <Self as Aes32EsmiEmitter<T0, T1, T2, T3>>::aes32esmi(self, rd, rs1, rs2, bs);
    }
    /// RISC-V `aes64ds` instruction.
    ///
    /// # Forms
    /// Assembly: `aes64ds xd, xs1, xs2`
    /// Rust: `aes64ds(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn aes64ds<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: Aes64DsEmitter<T0, T1, T2>,
    {
        <Self as Aes64DsEmitter<T0, T1, T2>>::aes64ds(self, rd, rs1, rs2);
    }
    /// RISC-V `aes64dsm` instruction.
    ///
    /// # Forms
    /// Assembly: `aes64dsm xd, xs1, xs2`
    /// Rust: `aes64dsm(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn aes64dsm<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: Aes64DsmEmitter<T0, T1, T2>,
    {
        <Self as Aes64DsmEmitter<T0, T1, T2>>::aes64dsm(self, rd, rs1, rs2);
    }
    /// RISC-V `aes64es` instruction.
    ///
    /// # Forms
    /// Assembly: `aes64es xd, xs1, xs2`
    /// Rust: `aes64es(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn aes64es<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: Aes64EsEmitter<T0, T1, T2>,
    {
        <Self as Aes64EsEmitter<T0, T1, T2>>::aes64es(self, rd, rs1, rs2);
    }
    /// RISC-V `aes64esm` instruction.
    ///
    /// # Forms
    /// Assembly: `aes64esm xd, xs1, xs2`
    /// Rust: `aes64esm(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn aes64esm<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: Aes64EsmEmitter<T0, T1, T2>,
    {
        <Self as Aes64EsmEmitter<T0, T1, T2>>::aes64esm(self, rd, rs1, rs2);
    }
    /// RISC-V `aes64im` instruction.
    ///
    /// # Forms
    /// Assembly: `aes64im xd, xs1`
    /// Rust: `aes64im(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn aes64im<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: Aes64ImEmitter<T0, T1>,
    {
        <Self as Aes64ImEmitter<T0, T1>>::aes64im(self, rd, rs1);
    }
    /// RISC-V `aes64ks1i` instruction.
    ///
    /// # Forms
    /// Assembly: `aes64ks1i xd, xs1, rnum`
    /// Rust: `aes64ks1i(rd, rs1, rnum)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rnum` — Immediate encoding value.
    pub fn aes64ks1i<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rnum: T2)
    where
        Self: Aes64Ks1IEmitter<T0, T1, T2>,
    {
        <Self as Aes64Ks1IEmitter<T0, T1, T2>>::aes64ks1i(self, rd, rs1, rnum);
    }
    /// RISC-V `aes64ks2` instruction.
    ///
    /// # Forms
    /// Assembly: `aes64ks2 xd, xs1, xs2`
    /// Rust: `aes64ks2(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn aes64ks2<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: Aes64Ks2Emitter<T0, T1, T2>,
    {
        <Self as Aes64Ks2Emitter<T0, T1, T2>>::aes64ks2(self, rd, rs1, rs2);
    }
    /// RISC-V `amoadd.b` instruction.
    ///
    /// # Forms
    /// Assembly: `amoadd.b xd, xs1, xs2, aq, rl`
    /// Rust: `amoadd_b(rd, rs1, rs2, aq, rl)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Memory base register.
    /// - `rs2` — Source register.
    /// - `aq` — Acquire-order bit.
    /// - `rl` — Release-order bit; retained for the existing emitter API.
    pub fn amoadd_b<T0, T1, T2, T3, T4>(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4)
    where
        Self: AmoaddBEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as AmoaddBEmitter<T0, T1, T2, T3, T4>>::amoadd_b(self, rd, rs1, rs2, aq, rl);
    }
    /// Atomic fetch-and-add doubleword
    ///
    /// Atomically:
    ///
    ///   * Load the doubleword at address _rs1_
    ///   * Write the loaded value into _rd_
    ///   * Add the value of register _rs2_ to the loaded value
    ///   * Write the sum to the address in _rs1_
    ///
    /// # Forms
    /// Assembly: `amoadd.d xd, xs2, (xs1)`
    /// Rust: `amoadd_d(rd, rs1, rs2, aq, rl)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Memory base register.
    /// - `rs2` — Source register.
    /// - `aq` — Acquire-order bit.
    /// - `rl` — Release-order bit; retained for the existing emitter API.
    pub fn amoadd_d<T0, T1, T2, T3, T4>(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4)
    where
        Self: AmoaddDEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as AmoaddDEmitter<T0, T1, T2, T3, T4>>::amoadd_d(self, rd, rs1, rs2, aq, rl);
    }
    /// RISC-V `amoadd.h` instruction.
    ///
    /// # Forms
    /// Assembly: `amoadd.h xd, xs1, xs2, aq, rl`
    /// Rust: `amoadd_h(rd, rs1, rs2, aq, rl)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Memory base register.
    /// - `rs2` — Source register.
    /// - `aq` — Acquire-order bit.
    /// - `rl` — Release-order bit; retained for the existing emitter API.
    pub fn amoadd_h<T0, T1, T2, T3, T4>(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4)
    where
        Self: AmoaddHEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as AmoaddHEmitter<T0, T1, T2, T3, T4>>::amoadd_h(self, rd, rs1, rs2, aq, rl);
    }
    /// Atomic fetch-and-add word
    ///
    /// Atomically:
    ///
    ///   * Load the word at address _rs1_
    ///   * Write the sign-extended value into _rd_
    ///   * Add the least-significant word of register _rs2_ to the loaded value
    ///   * Write the sum to the address in _rs1_
    ///
    /// # Forms
    /// Assembly: `amoadd.w xd, xs2, (xrs1)`
    /// Rust: `amoadd_w(rd, rs1, rs2, aq, rl)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Memory base register.
    /// - `rs2` — Source register.
    /// - `aq` — Acquire-order bit.
    /// - `rl` — Release-order bit; retained for the existing emitter API.
    pub fn amoadd_w<T0, T1, T2, T3, T4>(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4)
    where
        Self: AmoaddWEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as AmoaddWEmitter<T0, T1, T2, T3, T4>>::amoadd_w(self, rd, rs1, rs2, aq, rl);
    }
    /// RISC-V `amoand.b` instruction.
    ///
    /// # Forms
    /// Assembly: `amoand.b xd, xs1, xs2, aq, rl`
    /// Rust: `amoand_b(rd, rs1, rs2, aq, rl)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Memory base register.
    /// - `rs2` — Source register.
    /// - `aq` — Acquire-order bit.
    /// - `rl` — Release-order bit; retained for the existing emitter API.
    pub fn amoand_b<T0, T1, T2, T3, T4>(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4)
    where
        Self: AmoandBEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as AmoandBEmitter<T0, T1, T2, T3, T4>>::amoand_b(self, rd, rs1, rs2, aq, rl);
    }
    /// Atomic fetch-and-and doubleword
    ///
    /// Atomically:
    ///
    ///   * Load the doubleword at address _rs1_
    ///   * Write the loaded value into _rd_
    ///   * AND the value of register _rs2_ to the loaded value
    ///   * Write the result to the address in _rs1_
    ///
    /// # Forms
    /// Assembly: `amoand.d xd, xs2, (xrs1)`
    /// Rust: `amoand_d(rd, rs1, rs2, aq, rl)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Memory base register.
    /// - `rs2` — Source register.
    /// - `aq` — Acquire-order bit.
    /// - `rl` — Release-order bit; retained for the existing emitter API.
    pub fn amoand_d<T0, T1, T2, T3, T4>(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4)
    where
        Self: AmoandDEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as AmoandDEmitter<T0, T1, T2, T3, T4>>::amoand_d(self, rd, rs1, rs2, aq, rl);
    }
    /// RISC-V `amoand.h` instruction.
    ///
    /// # Forms
    /// Assembly: `amoand.h xd, xs1, xs2, aq, rl`
    /// Rust: `amoand_h(rd, rs1, rs2, aq, rl)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Memory base register.
    /// - `rs2` — Source register.
    /// - `aq` — Acquire-order bit.
    /// - `rl` — Release-order bit; retained for the existing emitter API.
    pub fn amoand_h<T0, T1, T2, T3, T4>(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4)
    where
        Self: AmoandHEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as AmoandHEmitter<T0, T1, T2, T3, T4>>::amoand_h(self, rd, rs1, rs2, aq, rl);
    }
    /// Atomic fetch-and-and word
    ///
    /// Atomically:
    ///
    ///   * Load the word at address _rs1_
    ///   * Write the sign-extended value into _rd_
    ///   * AND the least-significant word of register _rs2_ to the loaded value
    ///   * Write the result to the address in _rs1_
    ///
    /// # Forms
    /// Assembly: `amoand.w xd, xs2, (xrs1)`
    /// Rust: `amoand_w(rd, rs1, rs2, aq, rl)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Memory base register.
    /// - `rs2` — Source register.
    /// - `aq` — Acquire-order bit.
    /// - `rl` — Release-order bit; retained for the existing emitter API.
    pub fn amoand_w<T0, T1, T2, T3, T4>(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4)
    where
        Self: AmoandWEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as AmoandWEmitter<T0, T1, T2, T3, T4>>::amoand_w(self, rd, rs1, rs2, aq, rl);
    }
    /// RISC-V `amocas.b` instruction.
    ///
    /// # Forms
    /// Assembly: `amocas.b xd, xs1, xs2, aq, rl`
    /// Rust: `amocas_b(rd, rs1, rs2, aq, rl)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Memory base register.
    /// - `rs2` — Source register.
    /// - `aq` — Acquire-order bit.
    /// - `rl` — Release-order bit; retained for the existing emitter API.
    pub fn amocas_b<T0, T1, T2, T3, T4>(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4)
    where
        Self: AmocasBEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as AmocasBEmitter<T0, T1, T2, T3, T4>>::amocas_b(self, rd, rs1, rs2, aq, rl);
    }
    /// RISC-V `amocas.d` instruction.
    ///
    /// # Forms
    /// Assembly: `amocas.d xd, xs1, xs2, aq, rl`
    /// Rust: `amocas_d(rd, rs1, rs2, aq, rl)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Memory base register.
    /// - `rs2` — Source register.
    /// - `aq` — Acquire-order bit.
    /// - `rl` — Release-order bit; retained for the existing emitter API.
    pub fn amocas_d<T0, T1, T2, T3, T4>(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4)
    where
        Self: AmocasDEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as AmocasDEmitter<T0, T1, T2, T3, T4>>::amocas_d(self, rd, rs1, rs2, aq, rl);
    }
    /// RISC-V `amocas.h` instruction.
    ///
    /// # Forms
    /// Assembly: `amocas.h xd, xs1, xs2, aq, rl`
    /// Rust: `amocas_h(rd, rs1, rs2, aq, rl)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Memory base register.
    /// - `rs2` — Source register.
    /// - `aq` — Acquire-order bit.
    /// - `rl` — Release-order bit; retained for the existing emitter API.
    pub fn amocas_h<T0, T1, T2, T3, T4>(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4)
    where
        Self: AmocasHEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as AmocasHEmitter<T0, T1, T2, T3, T4>>::amocas_h(self, rd, rs1, rs2, aq, rl);
    }
    /// RISC-V `amocas.q` instruction.
    ///
    /// # Forms
    /// Assembly: `amocas.q xd, xs1, xs2, aq, rl`
    /// Rust: `amocas_q(rd, rs1, rs2, aq, rl)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Memory base register.
    /// - `rs2` — Source register.
    /// - `aq` — Acquire-order bit.
    /// - `rl` — Release-order bit; retained for the existing emitter API.
    pub fn amocas_q<T0, T1, T2, T3, T4>(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4)
    where
        Self: AmocasQEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as AmocasQEmitter<T0, T1, T2, T3, T4>>::amocas_q(self, rd, rs1, rs2, aq, rl);
    }
    /// RISC-V `amocas.w` instruction.
    ///
    /// # Forms
    /// Assembly: `amocas.w xd, xs1, xs2, aq, rl`
    /// Rust: `amocas_w(rd, rs1, rs2, aq, rl)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Memory base register.
    /// - `rs2` — Source register.
    /// - `aq` — Acquire-order bit.
    /// - `rl` — Release-order bit; retained for the existing emitter API.
    pub fn amocas_w<T0, T1, T2, T3, T4>(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4)
    where
        Self: AmocasWEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as AmocasWEmitter<T0, T1, T2, T3, T4>>::amocas_w(self, rd, rs1, rs2, aq, rl);
    }
    /// RISC-V `amomax.b` instruction.
    ///
    /// # Forms
    /// Assembly: `amomax.b xd, xs1, xs2, aq, rl`
    /// Rust: `amomax_b(rd, rs1, rs2, aq, rl)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Memory base register.
    /// - `rs2` — Source register.
    /// - `aq` — Acquire-order bit.
    /// - `rl` — Release-order bit; retained for the existing emitter API.
    pub fn amomax_b<T0, T1, T2, T3, T4>(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4)
    where
        Self: AmomaxBEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as AmomaxBEmitter<T0, T1, T2, T3, T4>>::amomax_b(self, rd, rs1, rs2, aq, rl);
    }
    /// Atomic MAX doubleword
    ///
    /// Atomically:
    ///
    ///   * Load the doubleword at address _rs1_
    ///   * Write the loaded value into _rd_
    ///   * Signed compare the value of register _rs2_ to the loaded value, and select the maximum value
    ///   * Write the maximum to the address in _rs1_
    ///
    /// # Forms
    /// Assembly: `amomax.d xd, xs2, (xrs1)`
    /// Rust: `amomax_d(rd, rs1, rs2, aq, rl)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Memory base register.
    /// - `rs2` — Source register.
    /// - `aq` — Acquire-order bit.
    /// - `rl` — Release-order bit; retained for the existing emitter API.
    pub fn amomax_d<T0, T1, T2, T3, T4>(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4)
    where
        Self: AmomaxDEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as AmomaxDEmitter<T0, T1, T2, T3, T4>>::amomax_d(self, rd, rs1, rs2, aq, rl);
    }
    /// RISC-V `amomax.h` instruction.
    ///
    /// # Forms
    /// Assembly: `amomax.h xd, xs1, xs2, aq, rl`
    /// Rust: `amomax_h(rd, rs1, rs2, aq, rl)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Memory base register.
    /// - `rs2` — Source register.
    /// - `aq` — Acquire-order bit.
    /// - `rl` — Release-order bit; retained for the existing emitter API.
    pub fn amomax_h<T0, T1, T2, T3, T4>(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4)
    where
        Self: AmomaxHEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as AmomaxHEmitter<T0, T1, T2, T3, T4>>::amomax_h(self, rd, rs1, rs2, aq, rl);
    }
    /// Atomic MAX word
    ///
    /// Atomically:
    ///
    ///   * Load the word at address _rs1_
    ///   * Write the sign-extended value into _rd_
    ///   * Signed compare the least-significant word of register _rs2_ to the loaded value, and select the maximum value
    ///   * Write the maximum to the address in _rs1_
    ///
    /// # Forms
    /// Assembly: `amomax.w xd, xs2, (xrs1)`
    /// Rust: `amomax_w(rd, rs1, rs2, aq, rl)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Memory base register.
    /// - `rs2` — Source register.
    /// - `aq` — Acquire-order bit.
    /// - `rl` — Release-order bit; retained for the existing emitter API.
    pub fn amomax_w<T0, T1, T2, T3, T4>(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4)
    where
        Self: AmomaxWEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as AmomaxWEmitter<T0, T1, T2, T3, T4>>::amomax_w(self, rd, rs1, rs2, aq, rl);
    }
    /// RISC-V `amomaxu.b` instruction.
    ///
    /// # Forms
    /// Assembly: `amomaxu.b xd, xs1, xs2, aq, rl`
    /// Rust: `amomaxu_b(rd, rs1, rs2, aq, rl)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Memory base register.
    /// - `rs2` — Source register.
    /// - `aq` — Acquire-order bit.
    /// - `rl` — Release-order bit; retained for the existing emitter API.
    pub fn amomaxu_b<T0, T1, T2, T3, T4>(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4)
    where
        Self: AmomaxuBEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as AmomaxuBEmitter<T0, T1, T2, T3, T4>>::amomaxu_b(self, rd, rs1, rs2, aq, rl);
    }
    /// Atomic MAX unsigned doubleword
    ///
    /// Atomically:
    ///
    ///   * Load the doubleword at address _rs1_
    ///   * Write the loaded value into _rd_
    ///   * Unsigned compare the value of register _rs2_ to the loaded value, and select the maximum value
    ///   * Write the maximum to the address in _rs1_
    ///
    /// # Forms
    /// Assembly: `amomaxu.d xd, xs2, (xrs1)`
    /// Rust: `amomaxu_d(rd, rs1, rs2, aq, rl)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Memory base register.
    /// - `rs2` — Source register.
    /// - `aq` — Acquire-order bit.
    /// - `rl` — Release-order bit; retained for the existing emitter API.
    pub fn amomaxu_d<T0, T1, T2, T3, T4>(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4)
    where
        Self: AmomaxuDEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as AmomaxuDEmitter<T0, T1, T2, T3, T4>>::amomaxu_d(self, rd, rs1, rs2, aq, rl);
    }
    /// RISC-V `amomaxu.h` instruction.
    ///
    /// # Forms
    /// Assembly: `amomaxu.h xd, xs1, xs2, aq, rl`
    /// Rust: `amomaxu_h(rd, rs1, rs2, aq, rl)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Memory base register.
    /// - `rs2` — Source register.
    /// - `aq` — Acquire-order bit.
    /// - `rl` — Release-order bit; retained for the existing emitter API.
    pub fn amomaxu_h<T0, T1, T2, T3, T4>(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4)
    where
        Self: AmomaxuHEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as AmomaxuHEmitter<T0, T1, T2, T3, T4>>::amomaxu_h(self, rd, rs1, rs2, aq, rl);
    }
    /// Atomic MAX unsigned word
    ///
    /// Atomically:
    ///
    ///   * Load the word at address _rs1_
    ///   * Write the sign-extended value into _rd_
    ///   * Unsigned compare the least-significant word of register _rs2_ to the loaded value, and select the maximum value
    ///   * Write the maximum to the address in _rs1_
    ///
    /// # Forms
    /// Assembly: `amomaxu.w xd, xs2, (xrs1)`
    /// Rust: `amomaxu_w(rd, rs1, rs2, aq, rl)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Memory base register.
    /// - `rs2` — Source register.
    /// - `aq` — Acquire-order bit.
    /// - `rl` — Release-order bit; retained for the existing emitter API.
    pub fn amomaxu_w<T0, T1, T2, T3, T4>(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4)
    where
        Self: AmomaxuWEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as AmomaxuWEmitter<T0, T1, T2, T3, T4>>::amomaxu_w(self, rd, rs1, rs2, aq, rl);
    }
    /// RISC-V `amomin.b` instruction.
    ///
    /// # Forms
    /// Assembly: `amomin.b xd, xs1, xs2, aq, rl`
    /// Rust: `amomin_b(rd, rs1, rs2, aq, rl)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Memory base register.
    /// - `rs2` — Source register.
    /// - `aq` — Acquire-order bit.
    /// - `rl` — Release-order bit; retained for the existing emitter API.
    pub fn amomin_b<T0, T1, T2, T3, T4>(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4)
    where
        Self: AmominBEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as AmominBEmitter<T0, T1, T2, T3, T4>>::amomin_b(self, rd, rs1, rs2, aq, rl);
    }
    /// Atomic MIN doubleword
    ///
    /// Atomically:
    ///
    ///   * Load the doubleword at address _rs1_
    ///   * Write the loaded value into _rd_
    ///   * Signed compare the value of register _rs2_ to the loaded value, and select the minimum value
    ///   * Write the minimum to the address in _rs1_
    ///
    /// # Forms
    /// Assembly: `amomin.d xd, xs2, (xrs1)`
    /// Rust: `amomin_d(rd, rs1, rs2, aq, rl)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Memory base register.
    /// - `rs2` — Source register.
    /// - `aq` — Acquire-order bit.
    /// - `rl` — Release-order bit; retained for the existing emitter API.
    pub fn amomin_d<T0, T1, T2, T3, T4>(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4)
    where
        Self: AmominDEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as AmominDEmitter<T0, T1, T2, T3, T4>>::amomin_d(self, rd, rs1, rs2, aq, rl);
    }
    /// RISC-V `amomin.h` instruction.
    ///
    /// # Forms
    /// Assembly: `amomin.h xd, xs1, xs2, aq, rl`
    /// Rust: `amomin_h(rd, rs1, rs2, aq, rl)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Memory base register.
    /// - `rs2` — Source register.
    /// - `aq` — Acquire-order bit.
    /// - `rl` — Release-order bit; retained for the existing emitter API.
    pub fn amomin_h<T0, T1, T2, T3, T4>(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4)
    where
        Self: AmominHEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as AmominHEmitter<T0, T1, T2, T3, T4>>::amomin_h(self, rd, rs1, rs2, aq, rl);
    }
    /// Atomic MIN word
    ///
    /// Atomically:
    ///
    ///   * Load the word at address _rs1_
    ///   * Write the sign-extended value into _rd_
    ///   * Signed compare the least-significant word of register _rs2_ to the loaded value, and select the minimum value
    ///   * Write the result to the address in _rs1_
    ///
    /// # Forms
    /// Assembly: `amomin.w xd, xs2, (xrs1)`
    /// Rust: `amomin_w(rd, rs1, rs2, aq, rl)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Memory base register.
    /// - `rs2` — Source register.
    /// - `aq` — Acquire-order bit.
    /// - `rl` — Release-order bit; retained for the existing emitter API.
    pub fn amomin_w<T0, T1, T2, T3, T4>(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4)
    where
        Self: AmominWEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as AmominWEmitter<T0, T1, T2, T3, T4>>::amomin_w(self, rd, rs1, rs2, aq, rl);
    }
    /// RISC-V `amominu.b` instruction.
    ///
    /// # Forms
    /// Assembly: `amominu.b xd, xs1, xs2, aq, rl`
    /// Rust: `amominu_b(rd, rs1, rs2, aq, rl)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Memory base register.
    /// - `rs2` — Source register.
    /// - `aq` — Acquire-order bit.
    /// - `rl` — Release-order bit; retained for the existing emitter API.
    pub fn amominu_b<T0, T1, T2, T3, T4>(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4)
    where
        Self: AmominuBEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as AmominuBEmitter<T0, T1, T2, T3, T4>>::amominu_b(self, rd, rs1, rs2, aq, rl);
    }
    /// Atomic MIN unsigned doubleword
    ///
    /// Atomically:
    ///
    ///   * Load the doubleword at address _rs1_
    ///   * Write the loaded value into _rd_
    ///   * Unsigned compare the value of register _rs2_ to the loaded value, and select the minimum value
    ///   * Write the minimum to the address in _rs1_
    ///
    /// # Forms
    /// Assembly: `amominu.d xd, xs2, (xrs1)`
    /// Rust: `amominu_d(rd, rs1, rs2, aq, rl)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Memory base register.
    /// - `rs2` — Source register.
    /// - `aq` — Acquire-order bit.
    /// - `rl` — Release-order bit; retained for the existing emitter API.
    pub fn amominu_d<T0, T1, T2, T3, T4>(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4)
    where
        Self: AmominuDEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as AmominuDEmitter<T0, T1, T2, T3, T4>>::amominu_d(self, rd, rs1, rs2, aq, rl);
    }
    /// RISC-V `amominu.h` instruction.
    ///
    /// # Forms
    /// Assembly: `amominu.h xd, xs1, xs2, aq, rl`
    /// Rust: `amominu_h(rd, rs1, rs2, aq, rl)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Memory base register.
    /// - `rs2` — Source register.
    /// - `aq` — Acquire-order bit.
    /// - `rl` — Release-order bit; retained for the existing emitter API.
    pub fn amominu_h<T0, T1, T2, T3, T4>(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4)
    where
        Self: AmominuHEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as AmominuHEmitter<T0, T1, T2, T3, T4>>::amominu_h(self, rd, rs1, rs2, aq, rl);
    }
    /// Atomic MIN unsigned word
    ///
    /// Atomically:
    ///
    ///   * Load the word at address _rs1_
    ///   * Write the sign-extended value into _rd_
    ///   * Unsigned compare the least-significant word of register _rs2_ to the loaded word, and select the minimum value
    ///   * Write the result to the address in _rs1_
    ///
    /// # Forms
    /// Assembly: `amominu.w xd, xs2, (xrs1)`
    /// Rust: `amominu_w(rd, rs1, rs2, aq, rl)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Memory base register.
    /// - `rs2` — Source register.
    /// - `aq` — Acquire-order bit.
    /// - `rl` — Release-order bit; retained for the existing emitter API.
    pub fn amominu_w<T0, T1, T2, T3, T4>(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4)
    where
        Self: AmominuWEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as AmominuWEmitter<T0, T1, T2, T3, T4>>::amominu_w(self, rd, rs1, rs2, aq, rl);
    }
    /// RISC-V `amoor.b` instruction.
    ///
    /// # Forms
    /// Assembly: `amoor.b xd, xs1, xs2, aq, rl`
    /// Rust: `amoor_b(rd, rs1, rs2, aq, rl)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Memory base register.
    /// - `rs2` — Source register.
    /// - `aq` — Acquire-order bit.
    /// - `rl` — Release-order bit; retained for the existing emitter API.
    pub fn amoor_b<T0, T1, T2, T3, T4>(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4)
    where
        Self: AmoorBEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as AmoorBEmitter<T0, T1, T2, T3, T4>>::amoor_b(self, rd, rs1, rs2, aq, rl);
    }
    /// Atomic fetch-and-or doubleword
    ///
    /// Atomically:
    ///
    ///   * Load the doubleword at address _rs1_
    ///   * Write the loaded value into _rd_
    ///   * OR the value of register _rs2_ to the loaded value
    ///   * Write the result to the address in _rs1_
    ///
    /// # Forms
    /// Assembly: `amoor.d xd, xs2, (xrs1)`
    /// Rust: `amoor_d(rd, rs1, rs2, aq, rl)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Memory base register.
    /// - `rs2` — Source register.
    /// - `aq` — Acquire-order bit.
    /// - `rl` — Release-order bit; retained for the existing emitter API.
    pub fn amoor_d<T0, T1, T2, T3, T4>(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4)
    where
        Self: AmoorDEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as AmoorDEmitter<T0, T1, T2, T3, T4>>::amoor_d(self, rd, rs1, rs2, aq, rl);
    }
    /// RISC-V `amoor.h` instruction.
    ///
    /// # Forms
    /// Assembly: `amoor.h xd, xs1, xs2, aq, rl`
    /// Rust: `amoor_h(rd, rs1, rs2, aq, rl)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Memory base register.
    /// - `rs2` — Source register.
    /// - `aq` — Acquire-order bit.
    /// - `rl` — Release-order bit; retained for the existing emitter API.
    pub fn amoor_h<T0, T1, T2, T3, T4>(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4)
    where
        Self: AmoorHEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as AmoorHEmitter<T0, T1, T2, T3, T4>>::amoor_h(self, rd, rs1, rs2, aq, rl);
    }
    /// Atomic fetch-and-or word
    ///
    /// Atomically:
    ///
    ///   * Load the word at address _rs1_
    ///   * Write the sign-extended value into _rd_
    ///   * OR the least-significant word of register _rs2_ to the loaded value
    ///   * Write the result to the address in _rs1_
    ///
    /// # Forms
    /// Assembly: `amoor.w xd, xs2, (xrs1)`
    /// Rust: `amoor_w(rd, rs1, rs2, aq, rl)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Memory base register.
    /// - `rs2` — Source register.
    /// - `aq` — Acquire-order bit.
    /// - `rl` — Release-order bit; retained for the existing emitter API.
    pub fn amoor_w<T0, T1, T2, T3, T4>(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4)
    where
        Self: AmoorWEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as AmoorWEmitter<T0, T1, T2, T3, T4>>::amoor_w(self, rd, rs1, rs2, aq, rl);
    }
    /// RISC-V `amoswap.b` instruction.
    ///
    /// # Forms
    /// Assembly: `amoswap.b xd, xs1, xs2, aq, rl`
    /// Rust: `amoswap_b(rd, rs1, rs2, aq, rl)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Memory base register.
    /// - `rs2` — Source register.
    /// - `aq` — Acquire-order bit.
    /// - `rl` — Release-order bit; retained for the existing emitter API.
    pub fn amoswap_b<T0, T1, T2, T3, T4>(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4)
    where
        Self: AmoswapBEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as AmoswapBEmitter<T0, T1, T2, T3, T4>>::amoswap_b(self, rd, rs1, rs2, aq, rl);
    }
    /// Atomic SWAP doubleword
    ///
    /// Atomically:
    ///
    ///   * Load the doubleword at address _rs1_
    ///   * Write the value into _rd_
    ///   * Store the value of register _rs2_ to the address in _rs1_
    ///
    /// # Forms
    /// Assembly: `amoswap.d xd, xs2, (xrs1)`
    /// Rust: `amoswap_d(rd, rs1, rs2, aq, rl)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Memory base register.
    /// - `rs2` — Source register.
    /// - `aq` — Acquire-order bit.
    /// - `rl` — Release-order bit; retained for the existing emitter API.
    pub fn amoswap_d<T0, T1, T2, T3, T4>(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4)
    where
        Self: AmoswapDEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as AmoswapDEmitter<T0, T1, T2, T3, T4>>::amoswap_d(self, rd, rs1, rs2, aq, rl);
    }
    /// RISC-V `amoswap.h` instruction.
    ///
    /// # Forms
    /// Assembly: `amoswap.h xd, xs1, xs2, aq, rl`
    /// Rust: `amoswap_h(rd, rs1, rs2, aq, rl)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Memory base register.
    /// - `rs2` — Source register.
    /// - `aq` — Acquire-order bit.
    /// - `rl` — Release-order bit; retained for the existing emitter API.
    pub fn amoswap_h<T0, T1, T2, T3, T4>(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4)
    where
        Self: AmoswapHEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as AmoswapHEmitter<T0, T1, T2, T3, T4>>::amoswap_h(self, rd, rs1, rs2, aq, rl);
    }
    /// Atomic SWAP word
    ///
    /// Atomically:
    ///
    ///   * Load the word at address _rs1_
    ///   * Write the sign-extended value into _rd_
    ///   * Store the least-significant word of register _rs2_ to the address in _rs1_
    ///
    /// # Forms
    /// Assembly: `amoswap.w xd, xs2, (xrs1)`
    /// Rust: `amoswap_w(rd, rs1, rs2, aq, rl)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Memory base register.
    /// - `rs2` — Source register.
    /// - `aq` — Acquire-order bit.
    /// - `rl` — Release-order bit; retained for the existing emitter API.
    pub fn amoswap_w<T0, T1, T2, T3, T4>(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4)
    where
        Self: AmoswapWEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as AmoswapWEmitter<T0, T1, T2, T3, T4>>::amoswap_w(self, rd, rs1, rs2, aq, rl);
    }
    /// RISC-V `amoxor.b` instruction.
    ///
    /// # Forms
    /// Assembly: `amoxor.b xd, xs1, xs2, aq, rl`
    /// Rust: `amoxor_b(rd, rs1, rs2, aq, rl)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Memory base register.
    /// - `rs2` — Source register.
    /// - `aq` — Acquire-order bit.
    /// - `rl` — Release-order bit; retained for the existing emitter API.
    pub fn amoxor_b<T0, T1, T2, T3, T4>(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4)
    where
        Self: AmoxorBEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as AmoxorBEmitter<T0, T1, T2, T3, T4>>::amoxor_b(self, rd, rs1, rs2, aq, rl);
    }
    /// Atomic fetch-and-xor doubleword
    ///
    /// Atomically:
    ///
    ///   * Load the doubleword at address _rs1_
    ///   * Write the loaded value into _rd_
    ///   * XOR the value of register _rs2_ to the loaded value
    ///   * Write the result to the address in _rs1_
    ///
    /// # Forms
    /// Assembly: `amoxor.d xd, xs2, (xrs1)`
    /// Rust: `amoxor_d(rd, rs1, rs2, aq, rl)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Memory base register.
    /// - `rs2` — Source register.
    /// - `aq` — Acquire-order bit.
    /// - `rl` — Release-order bit; retained for the existing emitter API.
    pub fn amoxor_d<T0, T1, T2, T3, T4>(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4)
    where
        Self: AmoxorDEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as AmoxorDEmitter<T0, T1, T2, T3, T4>>::amoxor_d(self, rd, rs1, rs2, aq, rl);
    }
    /// RISC-V `amoxor.h` instruction.
    ///
    /// # Forms
    /// Assembly: `amoxor.h xd, xs1, xs2, aq, rl`
    /// Rust: `amoxor_h(rd, rs1, rs2, aq, rl)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Memory base register.
    /// - `rs2` — Source register.
    /// - `aq` — Acquire-order bit.
    /// - `rl` — Release-order bit; retained for the existing emitter API.
    pub fn amoxor_h<T0, T1, T2, T3, T4>(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4)
    where
        Self: AmoxorHEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as AmoxorHEmitter<T0, T1, T2, T3, T4>>::amoxor_h(self, rd, rs1, rs2, aq, rl);
    }
    /// Atomic fetch-and-xor word
    ///
    /// Atomically:
    ///
    ///   * Load the word at address _rs1_
    ///   * Write the sign-extended value into _rd_
    ///   * XOR the least-significant word of register _rs2_ to the loaded value
    ///   * Write the result to the address in _rs1_
    ///
    /// # Forms
    /// Assembly: `amoxor.w xd, xs2, (xrs1)`
    /// Rust: `amoxor_w(rd, rs1, rs2, aq, rl)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Memory base register.
    /// - `rs2` — Source register.
    /// - `aq` — Acquire-order bit.
    /// - `rl` — Release-order bit; retained for the existing emitter API.
    pub fn amoxor_w<T0, T1, T2, T3, T4>(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4)
    where
        Self: AmoxorWEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as AmoxorWEmitter<T0, T1, T2, T3, T4>>::amoxor_w(self, rd, rs1, rs2, aq, rl);
    }
    /// And
    ///
    /// And rs1 with rs2, and store the result in rd
    ///
    /// # Forms
    /// Assembly: `and xd, xs1, xs2`
    /// Rust: `and(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn and<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: AndEmitter<T0, T1, T2>,
    {
        <Self as AndEmitter<T0, T1, T2>>::and(self, rd, rs1, rs2);
    }
    /// And immediate
    ///
    /// And an immediate to the value in rs1, and store the result in rd
    ///
    /// # Forms
    /// Assembly: `andi xd, xs1, imm`
    /// Rust: `andi(rd, rs1, imm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `imm` — Immediate encoding value.
    pub fn andi<T0, T1, T2>(&mut self, rd: T0, rs1: T1, imm: T2)
    where
        Self: AndiEmitter<T0, T1, T2>,
    {
        <Self as AndiEmitter<T0, T1, T2>>::andi(self, rd, rs1, imm);
    }
    /// AND with inverted operand
    ///
    /// This instruction performs the bitwise logical AND operation between `rs1` and the
    /// bitwise inversion of `rs2`.
    ///
    /// # Forms
    /// Assembly: `andn xd, xs1, xs2`
    /// Rust: `andn(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn andn<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: AndnEmitter<T0, T1, T2>,
    {
        <Self as AndnEmitter<T0, T1, T2>>::andn(self, rd, rs1, rs2);
    }
    /// Add upper immediate to pc
    ///
    /// Add an immediate to the current PC.
    ///
    /// # Forms
    /// Assembly: `auipc xd, imm`
    /// Rust: `auipc(rd, imm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `imm` — Immediate encoding value.
    pub fn auipc<T0, T1>(&mut self, rd: T0, imm: T1)
    where
        Self: AuipcEmitter<T0, T1>,
    {
        <Self as AuipcEmitter<T0, T1>>::auipc(self, rd, imm);
    }
    /// Single-Bit clear (Register)
    ///
    /// This instruction returns rs1 with a single bit cleared at the index specified in rs2.
    /// The index is read from the lower log2(XLEN) bits of rs2.
    ///
    /// # Forms
    /// Assembly: `bclr xd, xs1, xs2`
    /// Rust: `bclr(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn bclr<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: BclrEmitter<T0, T1, T2>,
    {
        <Self as BclrEmitter<T0, T1, T2>>::bclr(self, rd, rs1, rs2);
    }
    /// Single-Bit clear (Immediate)
    ///
    /// This instruction returns rs1 with a single bit cleared at the index specified in shamt. The
    /// index is read from the lower log2(XLEN) bits of shamt. For RV32, the encodings corresponding
    /// to shamt\[5\]=1 are reserved.
    ///
    /// # Forms
    /// Assembly: `bclri xd, xs1, shamt`
    /// Rust: `bclri(rd, rs1, shamtd)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `shamtd` — Immediate encoding value.
    pub fn bclri<T0, T1, T2>(&mut self, rd: T0, rs1: T1, shamtd: T2)
    where
        Self: BclriEmitter<T0, T1, T2>,
    {
        <Self as BclriEmitter<T0, T1, T2>>::bclri(self, rd, rs1, shamtd);
    }
    /// Single-Bit clear (Immediate)
    ///
    /// This instruction returns rs1 with a single bit cleared at the index specified in shamt. The
    /// index is read from the lower log2(XLEN) bits of shamt. For RV32, the encodings corresponding
    /// to shamt\[5\]=1 are reserved.
    ///
    /// # Forms
    /// Assembly: `bclri.rv32 xd, xs1, shamt`
    /// Rust: `bclri_rv32(rd, rs1, shamtw)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `shamtw` — Immediate encoding value.
    pub fn bclri_rv32<T0, T1, T2>(&mut self, rd: T0, rs1: T1, shamtw: T2)
    where
        Self: BclriRv32Emitter<T0, T1, T2>,
    {
        <Self as BclriRv32Emitter<T0, T1, T2>>::bclri_rv32(self, rd, rs1, shamtw);
    }
    /// Branch if equal
    ///
    /// Branch to PC + imm if
    /// the value in register rs1 is equal to the value in register rs2.
    ///
    /// Raise a `MisalignedAddress` exception if PC + imm is misaligned.
    ///
    /// # Forms
    /// Assembly: `beq xs1, xs2, imm`
    /// Rust: `beq(rs1, rs2, imm)`
    ///
    /// # Arguments
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    /// - `imm` — Immediate encoding value.
    pub fn beq<T0, T1, T2>(&mut self, rs1: T0, rs2: T1, imm: T2)
    where
        Self: BeqEmitter<T0, T1, T2>,
    {
        <Self as BeqEmitter<T0, T1, T2>>::beq(self, rs1, rs2, imm);
    }
    /// RISC-V `beqz` instruction.
    ///
    /// # Forms
    /// Assembly: `beqz rs1 bimm12lohi`
    /// Rust: `beqz(rs1, imm)`
    ///
    /// # Arguments
    /// - `rs1` — Source register.
    /// - `imm` — Immediate encoding value.
    pub fn beqz<T0, T1>(&mut self, rs1: T0, imm: T1)
    where
        Self: BeqzEmitter<T0, T1>,
    {
        <Self as BeqzEmitter<T0, T1>>::beqz(self, rs1, imm);
    }
    /// Single-Bit extract (Register)
    ///
    /// This instruction returns a single bit extracted from rs1 at the index specified in rs2.
    /// The index is read from the lower log2(XLEN) bits of rs2.
    ///
    /// # Forms
    /// Assembly: `bext xd, xs1, xs2`
    /// Rust: `bext(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn bext<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: BextEmitter<T0, T1, T2>,
    {
        <Self as BextEmitter<T0, T1, T2>>::bext(self, rd, rs1, rs2);
    }
    /// Single-Bit extract (Immediate)
    ///
    /// This instruction returns a single bit extracted from rs1 at the index specified in rs2.
    /// The index is read from the lower log2(XLEN) bits of shamt. For RV32, the encodings
    /// corresponding to shamt\[5\]=1 are reserved.
    ///
    /// # Forms
    /// Assembly: `bexti xd, xs1, shamt`
    /// Rust: `bexti(rd, rs1, shamtd)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `shamtd` — Immediate encoding value.
    pub fn bexti<T0, T1, T2>(&mut self, rd: T0, rs1: T1, shamtd: T2)
    where
        Self: BextiEmitter<T0, T1, T2>,
    {
        <Self as BextiEmitter<T0, T1, T2>>::bexti(self, rd, rs1, shamtd);
    }
    /// Single-Bit extract (Immediate)
    ///
    /// This instruction returns a single bit extracted from rs1 at the index specified in rs2.
    /// The index is read from the lower log2(XLEN) bits of shamt. For RV32, the encodings
    /// corresponding to shamt\[5\]=1 are reserved.
    ///
    /// # Forms
    /// Assembly: `bexti.rv32 xd, xs1, shamt`
    /// Rust: `bexti_rv32(rd, rs1, shamtw)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `shamtw` — Immediate encoding value.
    pub fn bexti_rv32<T0, T1, T2>(&mut self, rd: T0, rs1: T1, shamtw: T2)
    where
        Self: BextiRv32Emitter<T0, T1, T2>,
    {
        <Self as BextiRv32Emitter<T0, T1, T2>>::bexti_rv32(self, rd, rs1, shamtw);
    }
    /// Branch if greater than or equal
    ///
    /// Branch to PC + imm if
    /// the signed value in register rs1 is greater than or equal to the signed value in register rs2.
    ///
    /// Raise a `MisalignedAddress` exception if PC + imm is misaligned.
    ///
    /// # Forms
    /// Assembly: `bge xs1, xs2, imm`
    /// Rust: `bge(rs1, rs2, imm)`
    ///
    /// # Arguments
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    /// - `imm` — Immediate encoding value.
    pub fn bge<T0, T1, T2>(&mut self, rs1: T0, rs2: T1, imm: T2)
    where
        Self: BgeEmitter<T0, T1, T2>,
    {
        <Self as BgeEmitter<T0, T1, T2>>::bge(self, rs1, rs2, imm);
    }
    /// Branch if greater than or equal unsigned
    ///
    /// Branch to PC + imm if
    /// the unsigned value in register rs1 is greater than or equal to the unsigned value in register rs2.
    ///
    /// Raise a `MisalignedAddress` exception if PC + imm is misaligned.
    ///
    /// # Forms
    /// Assembly: `bgeu xs1, xs2, imm`
    /// Rust: `bgeu(rs1, rs2, imm)`
    ///
    /// # Arguments
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    /// - `imm` — Immediate encoding value.
    pub fn bgeu<T0, T1, T2>(&mut self, rs1: T0, rs2: T1, imm: T2)
    where
        Self: BgeuEmitter<T0, T1, T2>,
    {
        <Self as BgeuEmitter<T0, T1, T2>>::bgeu(self, rs1, rs2, imm);
    }
    /// RISC-V `bgez` instruction.
    ///
    /// # Forms
    /// Assembly: `bgez rs1 bimm12lohi`
    /// Rust: `bgez(rs1, imm)`
    ///
    /// # Arguments
    /// - `rs1` — Source register.
    /// - `imm` — Immediate encoding value.
    pub fn bgez<T0, T1>(&mut self, rs1: T0, imm: T1)
    where
        Self: BgezEmitter<T0, T1>,
    {
        <Self as BgezEmitter<T0, T1>>::bgez(self, rs1, imm);
    }
    /// RISC-V `bgt` instruction.
    ///
    /// # Forms
    /// Assembly: `bgt rs1 rs2 bimm12lohi`
    /// Rust: `bgt(rs1, rs2, imm)`
    ///
    /// # Arguments
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    /// - `imm` — Immediate encoding value.
    pub fn bgt<T0, T1, T2>(&mut self, rs1: T0, rs2: T1, imm: T2)
    where
        Self: BgtEmitter<T0, T1, T2>,
    {
        <Self as BgtEmitter<T0, T1, T2>>::bgt(self, rs1, rs2, imm);
    }
    /// RISC-V `bgtu` instruction.
    ///
    /// # Forms
    /// Assembly: `bgtu rs1 rs2 bimm12lohi`
    /// Rust: `bgtu(rs1, rs2, imm)`
    ///
    /// # Arguments
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    /// - `imm` — Immediate encoding value.
    pub fn bgtu<T0, T1, T2>(&mut self, rs1: T0, rs2: T1, imm: T2)
    where
        Self: BgtuEmitter<T0, T1, T2>,
    {
        <Self as BgtuEmitter<T0, T1, T2>>::bgtu(self, rs1, rs2, imm);
    }
    /// RISC-V `bgtz` instruction.
    ///
    /// # Forms
    /// Assembly: `bgtz rs2 bimm12lohi`
    /// Rust: `bgtz(rs2, imm)`
    ///
    /// # Arguments
    /// - `rs2` — Source register.
    /// - `imm` — Immediate encoding value.
    pub fn bgtz<T0, T1>(&mut self, rs2: T0, imm: T1)
    where
        Self: BgtzEmitter<T0, T1>,
    {
        <Self as BgtzEmitter<T0, T1>>::bgtz(self, rs2, imm);
    }
    /// Single-Bit invert (Register)
    ///
    /// This instruction returns rs1 with a single bit inverted at the index specified in rs2.
    /// The index is read from the lower log2(XLEN) bits of rs2.
    ///
    /// # Forms
    /// Assembly: `binv xd, xs1, xs2`
    /// Rust: `binv(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn binv<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: BinvEmitter<T0, T1, T2>,
    {
        <Self as BinvEmitter<T0, T1, T2>>::binv(self, rd, rs1, rs2);
    }
    /// Single-Bit invert (Immediate)
    ///
    /// This instruction returns rs1 with a single bit inverted at the index specified in shamt.
    /// The index is read from the lower log2(XLEN) bits of shamt.
    /// For RV32, the encodings corresponding to shamt\[5\]=1 are reserved.
    ///
    /// # Forms
    /// Assembly: `binvi xd, xs1, shamt`
    /// Rust: `binvi(rd, rs1, shamtd)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `shamtd` — Immediate encoding value.
    pub fn binvi<T0, T1, T2>(&mut self, rd: T0, rs1: T1, shamtd: T2)
    where
        Self: BinviEmitter<T0, T1, T2>,
    {
        <Self as BinviEmitter<T0, T1, T2>>::binvi(self, rd, rs1, shamtd);
    }
    /// Single-Bit invert (Immediate)
    ///
    /// This instruction returns rs1 with a single bit inverted at the index specified in shamt.
    /// The index is read from the lower log2(XLEN) bits of shamt.
    /// For RV32, the encodings corresponding to shamt\[5\]=1 are reserved.
    ///
    /// # Forms
    /// Assembly: `binvi.rv32 xd, xs1, shamt`
    /// Rust: `binvi_rv32(rd, rs1, shamtw)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `shamtw` — Immediate encoding value.
    pub fn binvi_rv32<T0, T1, T2>(&mut self, rd: T0, rs1: T1, shamtw: T2)
    where
        Self: BinviRv32Emitter<T0, T1, T2>,
    {
        <Self as BinviRv32Emitter<T0, T1, T2>>::binvi_rv32(self, rd, rs1, shamtw);
    }
    /// RISC-V `ble` instruction.
    ///
    /// # Forms
    /// Assembly: `ble rs1 rs2 bimm12lohi`
    /// Rust: `ble(rs1, rs2, imm)`
    ///
    /// # Arguments
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    /// - `imm` — Immediate encoding value.
    pub fn ble<T0, T1, T2>(&mut self, rs1: T0, rs2: T1, imm: T2)
    where
        Self: BleEmitter<T0, T1, T2>,
    {
        <Self as BleEmitter<T0, T1, T2>>::ble(self, rs1, rs2, imm);
    }
    /// RISC-V `bleu` instruction.
    ///
    /// # Forms
    /// Assembly: `bleu rs1 rs2 bimm12lohi`
    /// Rust: `bleu(rs1, rs2, imm)`
    ///
    /// # Arguments
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    /// - `imm` — Immediate encoding value.
    pub fn bleu<T0, T1, T2>(&mut self, rs1: T0, rs2: T1, imm: T2)
    where
        Self: BleuEmitter<T0, T1, T2>,
    {
        <Self as BleuEmitter<T0, T1, T2>>::bleu(self, rs1, rs2, imm);
    }
    /// RISC-V `blez` instruction.
    ///
    /// # Forms
    /// Assembly: `blez rs2 bimm12lohi`
    /// Rust: `blez(rs2, imm)`
    ///
    /// # Arguments
    /// - `rs2` — Source register.
    /// - `imm` — Immediate encoding value.
    pub fn blez<T0, T1>(&mut self, rs2: T0, imm: T1)
    where
        Self: BlezEmitter<T0, T1>,
    {
        <Self as BlezEmitter<T0, T1>>::blez(self, rs2, imm);
    }
    /// Branch if less than
    ///
    /// Branch to PC + imm if
    /// the signed value in register rs1 is less than the signed value in register rs2.
    ///
    /// Raise a `MisalignedAddress` exception if PC + imm is misaligned.
    ///
    /// # Forms
    /// Assembly: `blt xs1, xs2, imm`
    /// Rust: `blt(rs1, rs2, imm)`
    ///
    /// # Arguments
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    /// - `imm` — Immediate encoding value.
    pub fn blt<T0, T1, T2>(&mut self, rs1: T0, rs2: T1, imm: T2)
    where
        Self: BltEmitter<T0, T1, T2>,
    {
        <Self as BltEmitter<T0, T1, T2>>::blt(self, rs1, rs2, imm);
    }
    /// Branch if less than unsigned
    ///
    /// Branch to PC + imm if
    /// the unsigned value in register rs1 is less than the unsigned value in register rs2.
    ///
    /// Raise a `MisalignedAddress` exception if PC + imm is misaligned.
    ///
    /// # Forms
    /// Assembly: `bltu xs1, xs2, imm`
    /// Rust: `bltu(rs1, rs2, imm)`
    ///
    /// # Arguments
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    /// - `imm` — Immediate encoding value.
    pub fn bltu<T0, T1, T2>(&mut self, rs1: T0, rs2: T1, imm: T2)
    where
        Self: BltuEmitter<T0, T1, T2>,
    {
        <Self as BltuEmitter<T0, T1, T2>>::bltu(self, rs1, rs2, imm);
    }
    /// RISC-V `bltz` instruction.
    ///
    /// # Forms
    /// Assembly: `bltz rs1 bimm12lohi`
    /// Rust: `bltz(rs1, imm)`
    ///
    /// # Arguments
    /// - `rs1` — Source register.
    /// - `imm` — Immediate encoding value.
    pub fn bltz<T0, T1>(&mut self, rs1: T0, imm: T1)
    where
        Self: BltzEmitter<T0, T1>,
    {
        <Self as BltzEmitter<T0, T1>>::bltz(self, rs1, imm);
    }
    /// Branch if not equal
    ///
    /// Branch to PC + imm if
    /// the value in register rs1 is not equal to the value in register rs2.
    ///
    /// Raise a `MisalignedAddress` exception if PC + imm is misaligned.
    ///
    /// # Forms
    /// Assembly: `bne xs1, xs2, imm`
    /// Rust: `bne(rs1, rs2, imm)`
    ///
    /// # Arguments
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    /// - `imm` — Immediate encoding value.
    pub fn bne<T0, T1, T2>(&mut self, rs1: T0, rs2: T1, imm: T2)
    where
        Self: BneEmitter<T0, T1, T2>,
    {
        <Self as BneEmitter<T0, T1, T2>>::bne(self, rs1, rs2, imm);
    }
    /// RISC-V `bnez` instruction.
    ///
    /// # Forms
    /// Assembly: `bnez rs1 bimm12lohi`
    /// Rust: `bnez(rs1, imm)`
    ///
    /// # Arguments
    /// - `rs1` — Source register.
    /// - `imm` — Immediate encoding value.
    pub fn bnez<T0, T1>(&mut self, rs1: T0, imm: T1)
    where
        Self: BnezEmitter<T0, T1>,
    {
        <Self as BnezEmitter<T0, T1>>::bnez(self, rs1, imm);
    }
    /// Reverse bits in bytes
    ///
    /// This instruction reverses the order of the bits in every byte of a register.
    ///
    /// # Forms
    /// Assembly: `brev8 xd, xs1`
    /// Rust: `brev8(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn brev8<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: Brev8Emitter<T0, T1>,
    {
        <Self as Brev8Emitter<T0, T1>>::brev8(self, rd, rs1);
    }
    /// Single-Bit set (Register)
    ///
    /// This instruction returns rs1 with a single bit set at the index specified in rs2.
    /// The index is read from the lower log2(XLEN) bits of rs2.
    ///
    /// # Forms
    /// Assembly: `bset xd, xs1, xs2`
    /// Rust: `bset(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn bset<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: BsetEmitter<T0, T1, T2>,
    {
        <Self as BsetEmitter<T0, T1, T2>>::bset(self, rd, rs1, rs2);
    }
    /// Single-Bit set (Immediate)
    ///
    /// This instruction returns rs1 with a single bit set at the index specified in shamt.
    /// The index is read from the lower log2(XLEN) bits of shamt.
    /// For RV32, the encodings corresponding to shamt\[5\]=1 are reserved.
    ///
    /// # Forms
    /// Assembly: `bseti xd, xs1, shamt`
    /// Rust: `bseti(rd, rs1, shamtd)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `shamtd` — Immediate encoding value.
    pub fn bseti<T0, T1, T2>(&mut self, rd: T0, rs1: T1, shamtd: T2)
    where
        Self: BsetiEmitter<T0, T1, T2>,
    {
        <Self as BsetiEmitter<T0, T1, T2>>::bseti(self, rd, rs1, shamtd);
    }
    /// Single-Bit set (Immediate)
    ///
    /// This instruction returns rs1 with a single bit set at the index specified in shamt.
    /// The index is read from the lower log2(XLEN) bits of shamt.
    /// For RV32, the encodings corresponding to shamt\[5\]=1 are reserved.
    ///
    /// # Forms
    /// Assembly: `bseti.rv32 xd, xs1, shamt`
    /// Rust: `bseti_rv32(rd, rs1, shamtw)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `shamtw` — Immediate encoding value.
    pub fn bseti_rv32<T0, T1, T2>(&mut self, rd: T0, rs1: T1, shamtw: T2)
    where
        Self: BsetiRv32Emitter<T0, T1, T2>,
    {
        <Self as BsetiRv32Emitter<T0, T1, T2>>::bseti_rv32(self, rd, rs1, shamtw);
    }
    /// Add
    ///
    /// Add the value in rs2 to rd, and store the result in rd.
    /// C.ADD expands into `add rd, rd, rs2`.
    ///
    /// # Forms
    /// Assembly: `c.add xd, rs2`
    /// Rust: `c_add(rd, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination/source register.
    /// - `rs2` — Instruction operand.
    pub fn c_add<T0, T1>(&mut self, rd: T0, rs2: T1)
    where
        Self: CAddEmitter<T0, T1>,
    {
        <Self as CAddEmitter<T0, T1>>::c_add(self, rd, rs2);
    }
    /// Add a sign-extended non-zero immediate
    ///
    /// C.ADDI adds the non-zero sign-extended 6-bit immediate to the value in register rd then writes the result to rd.
    /// C.ADDI expands into `addi rd, rd, imm`.
    /// C.ADDI is only valid when rd &ne; x0 and imm &ne; 0.
    /// The code points with rd=x0 encode the C.NOP instruction; the remaining code points with imm=0 encode HINTs.
    ///
    /// # Forms
    /// Assembly: `c.addi xd, imm`
    /// Rust: `c_addi(rd, imm)`
    ///
    /// # Arguments
    /// - `rd` — Destination/source register.
    /// - `imm` — Immediate encoding value.
    pub fn c_addi<T0, T1>(&mut self, rd: T0, imm: T1)
    where
        Self: CAddiEmitter<T0, T1>,
    {
        <Self as CAddiEmitter<T0, T1>>::c_addi(self, rd, imm);
    }
    /// Add a sign-extended non-zero immediate
    ///
    /// C.ADDI16SP adds the non-zero sign-extended 6-bit immediate to the value in the stack pointer (sp=x2), where the immediate is scaled to represent multiples of 16 in the range (-512,496).
    /// C.ADDI16SP is used to adjust the stack pointer in procedure prologues and epilogues.
    /// It expands into `addi x2, x2, nzimm\[9:4\]`.
    /// C.ADDI16SP is only valid when nzimm &ne; 0; the code point with nzimm=0 is reserved.
    ///
    /// # Forms
    /// Assembly: `c.addi16sp imm`
    /// Rust: `c_addi16sp(imm)`
    ///
    /// # Arguments
    /// - `imm` — Immediate encoding value.
    pub fn c_addi16sp<T0>(&mut self, imm: T0)
    where
        Self: CAddi16spEmitter<T0>,
    {
        <Self as CAddi16spEmitter<T0>>::c_addi16sp(self, imm);
    }
    /// Add a zero-extended non-zero immediate, scaled by 4, to the stack pointer
    ///
    /// Adds a zero-extended non-zero immediate, scaled by 4, to the stack pointer, x2, and writes the result to rd'.
    /// This instruction is used to generate pointers to stack-allocated variables.
    /// It expands to `addi rd', x2, nzuimm\[9:2\]`.
    /// C.ADDI4SPN is only valid when nzuimm &ne; 0; the code points with nzuimm=0 are reserved.
    ///
    /// # Forms
    /// Assembly: `c.addi4spn xd, imm`
    /// Rust: `c_addi4spn(rd, imm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `imm` — Immediate encoding value.
    pub fn c_addi4spn<T0, T1>(&mut self, rd: T0, imm: T1)
    where
        Self: CAddi4spnEmitter<T0, T1>,
    {
        <Self as CAddi4spnEmitter<T0, T1>>::c_addi4spn(self, rd, imm);
    }
    /// Add a sign-extended non-zero immediate
    ///
    /// C.ADDIW is an RV64C/RV128C-only instruction that performs the same computation as C.ADDI but produces a 32-bit result, then sign-extends result to 64 bits.
    /// C.ADDIW expands into `addiw rd, rd, imm`.
    /// The immediate can be zero for C.ADDIW, where this corresponds to `sext.w rd`.
    /// C.ADDIW is only valid when rd &ne; x0; the code points with rd=x0 are reserved.
    ///
    /// # Forms
    /// Assembly: `c.addiw xd, imm`
    /// Rust: `c_addiw(rd, imm)`
    ///
    /// # Arguments
    /// - `rd` — Destination/source register.
    /// - `imm` — Immediate encoding value.
    pub fn c_addiw<T0, T1>(&mut self, rd: T0, imm: T1)
    where
        Self: CAddiwEmitter<T0, T1>,
    {
        <Self as CAddiwEmitter<T0, T1>>::c_addiw(self, rd, imm);
    }
    /// Add word
    ///
    /// Add the 32-bit values in rs2 from rd, and store the result in rd.
    /// The rd and rs2 register indexes should be used as rd+8 and rs2+8 (registers x8-x15).
    /// C.ADDW expands into `addw rd, rd, rs2`.
    ///
    /// # Forms
    /// Assembly: `c.addw xd, rs2`
    /// Rust: `c_addw(rd, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination/source register.
    /// - `rs2` — Source register.
    pub fn c_addw<T0, T1>(&mut self, rd: T0, rs2: T1)
    where
        Self: CAddwEmitter<T0, T1>,
    {
        <Self as CAddwEmitter<T0, T1>>::c_addw(self, rd, rs2);
    }
    /// And
    ///
    /// And rd with rs2, and store the result in rd
    /// The rd and rs2 register indexes should be used as rd+8 and rs2+8 (registers x8-x15).
    /// C.AND expands into `and rd, rd, rs2`.
    ///
    /// # Forms
    /// Assembly: `c.and xd, rs2`
    /// Rust: `c_and(rd, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination/source register.
    /// - `rs2` — Source register.
    pub fn c_and<T0, T1>(&mut self, rd: T0, rs2: T1)
    where
        Self: CAndEmitter<T0, T1>,
    {
        <Self as CAndEmitter<T0, T1>>::c_and(self, rd, rs2);
    }
    /// And immediate
    ///
    /// And an immediate to the value in rd, and store the result in rd.
    /// The rd register index should be used as rd+8 (registers x8-x15).
    /// C.ANDI expands into `andi rd, rd, imm`.
    ///
    /// # Forms
    /// Assembly: `c.andi xd, imm`
    /// Rust: `c_andi(rd, imm)`
    ///
    /// # Arguments
    /// - `rd` — Destination/source register.
    /// - `imm` — Immediate encoding value.
    pub fn c_andi<T0, T1>(&mut self, rd: T0, imm: T1)
    where
        Self: CAndiEmitter<T0, T1>,
    {
        <Self as CAndiEmitter<T0, T1>>::c_andi(self, rd, imm);
    }
    /// Branch if Equal Zero
    ///
    /// C.BEQZ performs conditional control transfers. The offset is sign-extended and added to the pc to form the branch target address. It can therefore target a &pm;256 B range. C.BEQZ takes the branch if the value in register rs1' is zero.
    /// It expands to `beq` `rs1, x0, offset`.
    ///
    /// # Forms
    /// Assembly: `c.beqz xs1, imm`
    /// Rust: `c_beqz(rs1, bimm9lohi)`
    ///
    /// # Arguments
    /// - `rs1` — Source register.
    /// - `bimm9lohi` — Immediate encoding value.
    pub fn c_beqz<T0, T1>(&mut self, rs1: T0, bimm9lohi: T1)
    where
        Self: CBeqzEmitter<T0, T1>,
    {
        <Self as CBeqzEmitter<T0, T1>>::c_beqz(self, rs1, bimm9lohi);
    }
    /// Branch if NOT Equal Zero
    ///
    /// C.BEQZ performs conditional control transfers. The offset is sign-extended and added to the pc to form the branch target address. It can therefore target a &pm;256 B range. C.BEQZ takes the branch if the value in register rs1' is NOT zero.
    /// It expands to `beq` `rs1, x0, offset`.
    ///
    /// # Forms
    /// Assembly: `c.bnez xs1, imm`
    /// Rust: `c_bnez(rs1, bimm9lohi)`
    ///
    /// # Arguments
    /// - `rs1` — Source register.
    /// - `bimm9lohi` — Immediate encoding value.
    pub fn c_bnez<T0, T1>(&mut self, rs1: T0, bimm9lohi: T1)
    where
        Self: CBnezEmitter<T0, T1>,
    {
        <Self as CBnezEmitter<T0, T1>>::c_bnez(self, rs1, bimm9lohi);
    }
    /// Breakpoint exception.
    ///
    /// The C.EBREAK instruction is used by debuggers to cause control to be transferred back to
    /// a debugging environment. Unless overridden by an external debug environment,
    /// C.EBREAK raises a breakpoint exception and performs no other operation.
    ///
    /// \[NOTE\]
    /// As described in the `C` Standard Extension for Compressed Instructions, the `c.ebreak`
    /// instruction performs the same operation as the EBREAK instruction.
    ///
    /// EBREAK causes the receiving privilege mode's epc register to be set to the address of
    /// the EBREAK instruction itself, not the address of the following instruction.
    /// As EBREAK causes a synchronous exception, it is not considered to retire,
    /// and should not increment the `minstret` CSR.
    ///
    /// # Forms
    /// Assembly: `c.ebreak " "`
    /// Rust: `c_ebreak()`
    ///
    /// # Arguments
    pub fn c_ebreak(&mut self)
    where
        Self: CEbreakEmitter,
    {
        <Self as CEbreakEmitter>::c_ebreak(self);
    }
    /// Load double-precision
    ///
    /// Loads a double precision floating-point value from memory into register rd.
    /// It computes an effective address by adding the zero-extended offset, scaled by 8,
    /// to the base address in register rs1.
    /// It expands to `fld` `rd, offset(rs1)`.
    ///
    /// # Forms
    /// Assembly: `c.fld xd, imm(xs1)`
    /// Rust: `c_fld(rd, rs1, imm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Memory base register.
    /// - `imm` — Immediate encoding value.
    pub fn c_fld<T0, T1, T2>(&mut self, rd: T0, rs1: T1, imm: T2)
    where
        Self: CFldEmitter<T0, T1, T2>,
    {
        <Self as CFldEmitter<T0, T1, T2>>::c_fld(self, rd, rs1, imm);
    }
    /// Load doubleword into floating-point register from stack
    ///
    /// Loads a double-precision floating-point value from memory into floating-point register rd.
    /// It computes its effective address by adding the zero-extended offset, scaled by 8,
    /// to the stack pointer, x2.
    /// It expands to `fld` `rd, offset(x2)`.
    ///
    /// # Forms
    /// Assembly: `c.fldsp fd, imm(sp)`
    /// Rust: `c_fldsp(rd, imm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `imm` — Immediate encoding value.
    pub fn c_fldsp<T0, T1>(&mut self, rd: T0, imm: T1)
    where
        Self: CFldspEmitter<T0, T1>,
    {
        <Self as CFldspEmitter<T0, T1>>::c_fldsp(self, rd, imm);
    }
    /// Load single-precision
    ///
    /// Loads a single precision floating-point value from memory into register rd.
    /// It computes an effective address by adding the zero-extended offset, scaled by 4,
    /// to the base address in register rs1.
    /// It expands to `flw` `rd, offset(rs1)`.
    ///
    /// # Forms
    /// Assembly: `c.flw xd, imm(xs1)`
    /// Rust: `c_flw(rd, rs1, imm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Memory base register.
    /// - `imm` — Immediate encoding value.
    pub fn c_flw<T0, T1, T2>(&mut self, rd: T0, rs1: T1, imm: T2)
    where
        Self: CFlwEmitter<T0, T1, T2>,
    {
        <Self as CFlwEmitter<T0, T1, T2>>::c_flw(self, rd, rs1, imm);
    }
    /// Load word into floating-point register from stack
    ///
    /// Loads a single-precision floating-point value from memory into floating-point register rd.
    /// It computes its effective address by adding the zero-extended offset, scaled by 4,
    /// to the stack pointer, x2.
    /// It expands to `flw` `rd, offset(x2)`.
    ///
    /// # Forms
    /// Assembly: `c.flwsp fd, imm(sp)`
    /// Rust: `c_flwsp(rd, imm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `imm` — Immediate encoding value.
    pub fn c_flwsp<T0, T1>(&mut self, rd: T0, imm: T1)
    where
        Self: CFlwspEmitter<T0, T1>,
    {
        <Self as CFlwspEmitter<T0, T1>>::c_flwsp(self, rd, imm);
    }
    /// Store double-precision
    ///
    /// Stores a double precision floating-point value in register rs2 to memory.
    /// It computes an effective address by adding the zero-extended offset, scaled by 8,
    /// to the base address in register rs1.
    /// It expands to `fsd` `rs2, offset(rs1)`.
    ///
    /// # Forms
    /// Assembly: `c.fsd xs2, imm(xs1)`
    /// Rust: `c_fsd(rs1, rs2, imm)`
    ///
    /// # Arguments
    /// - `rs1` — Memory base register.
    /// - `rs2` — Source register.
    /// - `imm` — Immediate encoding value.
    pub fn c_fsd<T0, T1, T2>(&mut self, rs1: T0, rs2: T1, imm: T2)
    where
        Self: CFsdEmitter<T0, T1, T2>,
    {
        <Self as CFsdEmitter<T0, T1, T2>>::c_fsd(self, rs1, rs2, imm);
    }
    /// Store double-precision value to stack
    ///
    /// Stores a double-precision floating-point value in floating-point register rs2 to memory.
    /// It computes an effective address by adding the zero-extended offset, scaled by 8,
    /// to the stack pointer, x2.
    /// It expands to `fsd` `rs2, offset(x2)`.
    ///
    /// # Forms
    /// Assembly: `c.fsdsp fs2, imm(sp)`
    /// Rust: `c_fsdsp(rs2, imm)`
    ///
    /// # Arguments
    /// - `rs2` — Instruction operand.
    /// - `imm` — Immediate encoding value.
    pub fn c_fsdsp<T0, T1>(&mut self, rs2: T0, imm: T1)
    where
        Self: CFsdspEmitter<T0, T1>,
    {
        <Self as CFsdspEmitter<T0, T1>>::c_fsdsp(self, rs2, imm);
    }
    /// Store single-precision
    ///
    /// Stores a single precision floating-point value in register rs2 to memory.
    /// It computes an effective address by adding the zero-extended offset, scaled by 4,
    /// to the base address in register rs1.
    /// It expands to `fsw` `rs2, offset(rs1)`.
    ///
    /// # Forms
    /// Assembly: `c.fsw xs2, imm(xs1)`
    /// Rust: `c_fsw(rs1, rs2, imm)`
    ///
    /// # Arguments
    /// - `rs1` — Memory base register.
    /// - `rs2` — Source register.
    /// - `imm` — Immediate encoding value.
    pub fn c_fsw<T0, T1, T2>(&mut self, rs1: T0, rs2: T1, imm: T2)
    where
        Self: CFswEmitter<T0, T1, T2>,
    {
        <Self as CFswEmitter<T0, T1, T2>>::c_fsw(self, rs1, rs2, imm);
    }
    /// Store single-precision value to stack
    ///
    /// Stores a single-precision floating-point value in floating-point register rs2 to memory.
    /// It computes an effective address by adding the zero-extended offset, scaled by 4,
    /// to the stack pointer, x2.
    /// It expands to `fsw` `rs2, offset(x2)`.
    ///
    /// # Forms
    /// Assembly: `c.fswsp fs2, imm(sp)`
    /// Rust: `c_fswsp(rs2, imm)`
    ///
    /// # Arguments
    /// - `rs2` — Instruction operand.
    /// - `imm` — Immediate encoding value.
    pub fn c_fswsp<T0, T1>(&mut self, rs2: T0, imm: T1)
    where
        Self: CFswspEmitter<T0, T1>,
    {
        <Self as CFswspEmitter<T0, T1>>::c_fswsp(self, rs2, imm);
    }
    /// Jump
    ///
    /// C.J performs an unconditional control transfer. The offset is sign-extended and added to the pc to form the jump target address. C.J can therefore target a &pm;2 KiB range.
    /// It expands to `jal` `x0, offset`.
    ///
    /// # Forms
    /// Assembly: `c.j imm`
    /// Rust: `c_j(imm)`
    ///
    /// # Arguments
    /// - `imm` — Immediate encoding value.
    pub fn c_j<T0>(&mut self, imm: T0)
    where
        Self: CJEmitter<T0>,
    {
        <Self as CJEmitter<T0>>::c_j(self, imm);
    }
    /// Jump and Link
    ///
    /// C.JAL is an RV32C-only instruction that performs the same operation as C.J, but additionally writes the address of the instruction following the jump (pc+2) to the link register, x1.
    /// It expands to `jal` `x1, offset`.
    ///
    /// # Forms
    /// Assembly: `c.jal imm`
    /// Rust: `c_jal(imm)`
    ///
    /// # Arguments
    /// - `imm` — Immediate encoding value.
    pub fn c_jal<T0>(&mut self, imm: T0)
    where
        Self: CJalEmitter<T0>,
    {
        <Self as CJalEmitter<T0>>::c_jal(self, imm);
    }
    /// Jump and Link Register.
    ///
    /// C.JALR (jump and link register) performs the same operation as C.JR, but additionally writes the address of the instruction following the jump (pc+2) to the link register, x1.
    /// C.JALR expands to jalr x1, 0(rs1).
    ///
    /// # Forms
    /// Assembly: `c.jalr xs1`
    /// Rust: `c_jalr(rs1)`
    ///
    /// # Arguments
    /// - `rs1` — Instruction operand.
    pub fn c_jalr<T0>(&mut self, rs1: T0)
    where
        Self: CJalrEmitter<T0>,
    {
        <Self as CJalrEmitter<T0>>::c_jalr(self, rs1);
    }
    /// Jump Register
    ///
    /// C.JR (jump register) performs an unconditional control transfer to the address in register rs1.
    /// C.JR expands to jalr x0, 0(rs1).
    ///
    /// # Forms
    /// Assembly: `c.jr xs1`
    /// Rust: `c_jr(rs1)`
    ///
    /// # Arguments
    /// - `rs1` — Source register.
    pub fn c_jr<T0>(&mut self, rs1: T0)
    where
        Self: CJrEmitter<T0>,
    {
        <Self as CJrEmitter<T0>>::c_jr(self, rs1);
    }
    /// Load unsigned byte, 16-bit encoding
    ///
    /// Loads a 8-bit value from memory into register rd.
    /// It computes an effective address by adding the zero-extended offset, to the base address in register rs1.
    /// It expands to `lbu` `rd, offset(rs1)`.
    ///
    /// # Forms
    /// Assembly: `c.lbu xd, imm(xs1)`
    /// Rust: `c_lbu(rd, rs1, imm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `imm` — Immediate encoding value.
    pub fn c_lbu<T0, T1, T2>(&mut self, rd: T0, rs1: T1, imm: T2)
    where
        Self: CLbuEmitter<T0, T1, T2>,
    {
        <Self as CLbuEmitter<T0, T1, T2>>::c_lbu(self, rd, rs1, imm);
    }
    /// Load double
    ///
    /// Loads a 64-bit value from memory into register rd.
    /// It computes an effective address by adding the zero-extended offset, scaled by 8,
    /// to the base address in register rs1.
    /// It expands to `ld` `rd, offset(rs1)`.
    ///
    /// # Forms
    /// Assembly: `c.ld xd, imm(xs1)`
    /// Rust: `c_ld(rd, rs1, imm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Memory base register.
    /// - `imm` — Immediate encoding value.
    pub fn c_ld<T0, T1, T2>(&mut self, rd: T0, rs1: T1, imm: T2)
    where
        Self: CLdEmitter<T0, T1, T2>,
    {
        <Self as CLdEmitter<T0, T1, T2>>::c_ld(self, rd, rs1, imm);
    }
    /// Load doubleword from stack pointer
    ///
    /// C.LDSP is an RV64C/RV128C-only instruction that loads a 64-bit value from memory
    /// into register rd.
    /// It computes its effective address by adding the zero-extended offset, scaled by 8,
    /// to the stack pointer, x2.
    /// It expands to `ld` `rd, offset(x2)`.
    /// C.LDSP is only valid when rd &ne; x0 the code points with rd=x0 are reserved.
    ///
    /// # Forms
    /// Assembly: `c.ldsp xd, imm(sp)`
    /// Rust: `c_ldsp(rd, imm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `imm` — Immediate encoding value.
    pub fn c_ldsp<T0, T1>(&mut self, rd: T0, imm: T1)
    where
        Self: CLdspEmitter<T0, T1>,
    {
        <Self as CLdspEmitter<T0, T1>>::c_ldsp(self, rd, imm);
    }
    /// Load signed halfword, 16-bit encoding
    ///
    /// Loads a 16-bit value from memory into register rd.
    /// It computes an effective address by adding the zero-extended offset, to the base address in register rs1.
    /// It expands to `lh` `rd, offset(rs1)`.
    ///
    /// # Forms
    /// Assembly: `c.lh xd, imm(xs1)`
    /// Rust: `c_lh(rd, rs1, imm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `imm` — Immediate encoding value.
    pub fn c_lh<T0, T1, T2>(&mut self, rd: T0, rs1: T1, imm: T2)
    where
        Self: CLhEmitter<T0, T1, T2>,
    {
        <Self as CLhEmitter<T0, T1, T2>>::c_lh(self, rd, rs1, imm);
    }
    /// Load unsigned halfword, 16-bit encoding
    ///
    /// Loads a 16-bit value from memory into register rd.
    /// It computes an effective address by adding the zero-extended offset, to the base address in register rs1.
    /// It expands to `lhu` `rd, offset(rs1)`.
    ///
    /// # Forms
    /// Assembly: `c.lhu xd, imm(xs1)`
    /// Rust: `c_lhu(rd, rs1, imm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `imm` — Immediate encoding value.
    pub fn c_lhu<T0, T1, T2>(&mut self, rd: T0, rs1: T1, imm: T2)
    where
        Self: CLhuEmitter<T0, T1, T2>,
    {
        <Self as CLhuEmitter<T0, T1, T2>>::c_lhu(self, rd, rs1, imm);
    }
    /// Load the sign-extended 6-bit immediate
    ///
    /// C.LI loads the sign-extended 6-bit immediate, imm, into register rd.
    /// C.LI expands into `addi rd, x0, imm`.
    /// C.LI is only valid when rd &ne; x0; the code points with rd=x0 encode HINTs.
    ///
    /// # Forms
    /// Assembly: `c.li xd, imm`
    /// Rust: `c_li(rd, imm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `imm` — Immediate encoding value.
    pub fn c_li<T0, T1>(&mut self, rd: T0, imm: T1)
    where
        Self: CLiEmitter<T0, T1>,
    {
        <Self as CLiEmitter<T0, T1>>::c_li(self, rd, imm);
    }
    /// Load the non-zero 6-bit immediate field into bits 17-12 of the destination register
    ///
    /// C.LUI loads the non-zero 6-bit immediate field into bits 17-12 of the destination register, clears the bottom 12 bits, and sign-extends bit 17 into all higher bits of the destination.
    /// C.LUI expands into `lui rd, imm`.
    /// C.LUI is only valid when rd&ne;x0 and rd&ne;x2, and when the immediate is not equal to zero.
    /// The code points with imm=0 are reserved; the remaining code points with rd=x0 are HINTs; and the remaining code points with rd=x2 correspond to the C.ADDI16SP instruction
    ///
    /// # Forms
    /// Assembly: `c.lui xd, imm`
    /// Rust: `c_lui(rd, imm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `imm` — Immediate encoding value.
    pub fn c_lui<T0, T1>(&mut self, rd: T0, imm: T1)
    where
        Self: CLuiEmitter<T0, T1>,
    {
        <Self as CLuiEmitter<T0, T1>>::c_lui(self, rd, imm);
    }
    /// Load word
    ///
    /// Loads a 32-bit value from memory into register rd.
    /// It computes an effective address by adding the zero-extended offset, scaled by 4,
    /// to the base address in register rs1.
    /// It expands to `lw` `rd, offset(rs1)`.
    ///
    /// # Forms
    /// Assembly: `c.lw xd, imm(xs1)`
    /// Rust: `c_lw(rd, rs1, imm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Memory base register.
    /// - `imm` — Immediate encoding value.
    pub fn c_lw<T0, T1, T2>(&mut self, rd: T0, rs1: T1, imm: T2)
    where
        Self: CLwEmitter<T0, T1, T2>,
    {
        <Self as CLwEmitter<T0, T1, T2>>::c_lw(self, rd, rs1, imm);
    }
    /// Load word from stack pointer
    ///
    /// Loads a 32-bit value from memory into register rd.
    /// It computes an effective address by adding the zero-extended offset, scaled by 4,
    /// to the stack pointer, x2.
    /// It expands to `lw` `rd, offset(x2)`.
    /// C.LWSP is only valid when rd &ne; x0. The code points with rd=x0 are reserved.
    ///
    /// # Forms
    /// Assembly: `c.lwsp xd, imm(sp)`
    /// Rust: `c_lwsp(rd, imm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `imm` — Immediate encoding value.
    pub fn c_lwsp<T0, T1>(&mut self, rd: T0, imm: T1)
    where
        Self: CLwspEmitter<T0, T1>,
    {
        <Self as CLwspEmitter<T0, T1>>::c_lwsp(self, rd, imm);
    }
    /// RISC-V `c.mop.1` instruction.
    ///
    /// # Forms
    /// Assembly: `c.mop.1`
    /// Rust: `c_mop_1()`
    ///
    /// # Arguments
    pub fn c_mop_1(&mut self)
    where
        Self: CMop1Emitter,
    {
        <Self as CMop1Emitter>::c_mop_1(self);
    }
    /// RISC-V `c.mop.11` instruction.
    ///
    /// # Forms
    /// Assembly: `c.mop.11`
    /// Rust: `c_mop_11()`
    ///
    /// # Arguments
    pub fn c_mop_11(&mut self)
    where
        Self: CMop11Emitter,
    {
        <Self as CMop11Emitter>::c_mop_11(self);
    }
    /// RISC-V `c.mop.13` instruction.
    ///
    /// # Forms
    /// Assembly: `c.mop.13`
    /// Rust: `c_mop_13()`
    ///
    /// # Arguments
    pub fn c_mop_13(&mut self)
    where
        Self: CMop13Emitter,
    {
        <Self as CMop13Emitter>::c_mop_13(self);
    }
    /// RISC-V `c.mop.15` instruction.
    ///
    /// # Forms
    /// Assembly: `c.mop.15`
    /// Rust: `c_mop_15()`
    ///
    /// # Arguments
    pub fn c_mop_15(&mut self)
    where
        Self: CMop15Emitter,
    {
        <Self as CMop15Emitter>::c_mop_15(self);
    }
    /// RISC-V `c.mop.3` instruction.
    ///
    /// # Forms
    /// Assembly: `c.mop.3`
    /// Rust: `c_mop_3()`
    ///
    /// # Arguments
    pub fn c_mop_3(&mut self)
    where
        Self: CMop3Emitter,
    {
        <Self as CMop3Emitter>::c_mop_3(self);
    }
    /// RISC-V `c.mop.5` instruction.
    ///
    /// # Forms
    /// Assembly: `c.mop.5`
    /// Rust: `c_mop_5()`
    ///
    /// # Arguments
    pub fn c_mop_5(&mut self)
    where
        Self: CMop5Emitter,
    {
        <Self as CMop5Emitter>::c_mop_5(self);
    }
    /// RISC-V `c.mop.7` instruction.
    ///
    /// # Forms
    /// Assembly: `c.mop.7`
    /// Rust: `c_mop_7()`
    ///
    /// # Arguments
    pub fn c_mop_7(&mut self)
    where
        Self: CMop7Emitter,
    {
        <Self as CMop7Emitter>::c_mop_7(self);
    }
    /// RISC-V `c.mop.9` instruction.
    ///
    /// # Forms
    /// Assembly: `c.mop.9`
    /// Rust: `c_mop_9()`
    ///
    /// # Arguments
    pub fn c_mop_9(&mut self)
    where
        Self: CMop9Emitter,
    {
        <Self as CMop9Emitter>::c_mop_9(self);
    }
    /// RISC-V `c.mop.n` instruction.
    ///
    /// # Forms
    /// Assembly: `c.mop.n c_mop_t`
    /// Rust: `c_mop_n(mop_t)`
    ///
    /// # Arguments
    /// - `mop_t` — Instruction operand.
    pub fn c_mop_n<T0>(&mut self, mop_t: T0)
    where
        Self: CMopNEmitter<T0>,
    {
        <Self as CMopNEmitter<T0>>::c_mop_n(self, mop_t);
    }
    /// Multiply, 16-bit encoding
    ///
    /// This instruction multiplies XLEN bits of the source operands from rsd' and rs2' and writes the lowest XLEN bits of the result to rsd'.
    ///
    /// # Forms
    /// Assembly: `c.mul xd, xs2`
    /// Rust: `c_mul(rd, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination/source register.
    /// - `rs2` — Source register.
    pub fn c_mul<T0, T1>(&mut self, rd: T0, rs2: T1)
    where
        Self: CMulEmitter<T0, T1>,
    {
        <Self as CMulEmitter<T0, T1>>::c_mul(self, rd, rs2);
    }
    /// Move Register
    ///
    /// C.MV (move register) performs copy of the data in register rs2 to register rd
    /// C.MV expands to addi rd, x0, rs2.
    ///
    /// # Forms
    /// Assembly: `c.mv xd, xs2`
    /// Rust: `c_mv(rd, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs2` — Instruction operand.
    pub fn c_mv<T0, T1>(&mut self, rd: T0, rs2: T1)
    where
        Self: CMvEmitter<T0, T1>,
    {
        <Self as CMvEmitter<T0, T1>>::c_mv(self, rd, rs2);
    }
    /// Non-operation
    ///
    /// C.NOP expands into `addi x0, x0, imm`.
    ///
    /// # Forms
    /// Assembly: `c.nop imm`
    /// Rust: `c_nop(imm)`
    ///
    /// # Arguments
    /// - `imm` — Immediate encoding value.
    pub fn c_nop<T0>(&mut self, imm: T0)
    where
        Self: CNopEmitter<T0>,
    {
        <Self as CNopEmitter<T0>>::c_nop(self, imm);
    }
    /// Bitwise not, 16-bit encoding
    ///
    /// This instruction takes a single source/destination operand.
    /// This instruction takes the one's complement of rd'/rs1' and writes the result to the same register.
    ///
    /// # Forms
    /// Assembly: `c.not xd`
    /// Rust: `c_not(rd)`
    ///
    /// # Arguments
    /// - `rd` — Destination/source register.
    pub fn c_not<T0>(&mut self, rd: T0)
    where
        Self: CNotEmitter<T0>,
    {
        <Self as CNotEmitter<T0>>::c_not(self, rd);
    }
    /// RISC-V `c.ntl.all` instruction.
    ///
    /// # Forms
    /// Assembly: `c.ntl.all`
    /// Rust: `c_ntl_all()`
    ///
    /// # Arguments
    pub fn c_ntl_all(&mut self)
    where
        Self: CNtlAllEmitter,
    {
        <Self as CNtlAllEmitter>::c_ntl_all(self);
    }
    /// RISC-V `c.ntl.p1` instruction.
    ///
    /// # Forms
    /// Assembly: `c.ntl.p1`
    /// Rust: `c_ntl_p1()`
    ///
    /// # Arguments
    pub fn c_ntl_p1(&mut self)
    where
        Self: CNtlP1Emitter,
    {
        <Self as CNtlP1Emitter>::c_ntl_p1(self);
    }
    /// RISC-V `c.ntl.pall` instruction.
    ///
    /// # Forms
    /// Assembly: `c.ntl.pall`
    /// Rust: `c_ntl_pall()`
    ///
    /// # Arguments
    pub fn c_ntl_pall(&mut self)
    where
        Self: CNtlPallEmitter,
    {
        <Self as CNtlPallEmitter>::c_ntl_pall(self);
    }
    /// RISC-V `c.ntl.s1` instruction.
    ///
    /// # Forms
    /// Assembly: `c.ntl.s1`
    /// Rust: `c_ntl_s1()`
    ///
    /// # Arguments
    pub fn c_ntl_s1(&mut self)
    where
        Self: CNtlS1Emitter,
    {
        <Self as CNtlS1Emitter>::c_ntl_s1(self);
    }
    /// Or
    ///
    /// Or rd with rs2, and store the result in rd
    /// The rd and rs2 register indexes should be used as rd+8 and rs2+8 (registers x8-x15).
    /// C.OR expands into `or rd, rd, rs2`.
    ///
    /// # Forms
    /// Assembly: `c.or xd, rs2`
    /// Rust: `c_or(rd, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination/source register.
    /// - `rs2` — Source register.
    pub fn c_or<T0, T1>(&mut self, rd: T0, rs2: T1)
    where
        Self: COrEmitter<T0, T1>,
    {
        <Self as COrEmitter<T0, T1>>::c_or(self, rd, rs2);
    }
    /// Store unsigned byte, 16-bit encoding
    ///
    /// Stores a 8-bit value from register rs2 into memory.
    /// It computes an effective address by adding the zero-extended offset, to the base address in register rs1.
    /// It expands to `sb` `rs2, offset(rs1)`.
    ///
    /// # Forms
    /// Assembly: `c.sb xs2, imm(xs1)`
    /// Rust: `c_sb(rs1, rs2, imm)`
    ///
    /// # Arguments
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    /// - `imm` — Immediate encoding value.
    pub fn c_sb<T0, T1, T2>(&mut self, rs1: T0, rs2: T1, imm: T2)
    where
        Self: CSbEmitter<T0, T1, T2>,
    {
        <Self as CSbEmitter<T0, T1, T2>>::c_sb(self, rs1, rs2, imm);
    }
    /// Store double
    ///
    /// Stores a 64-bit value in register rs2 to memory.
    /// It computes an effective address by adding the zero-extended offset, scaled by 8,
    /// to the base address in register rs1.
    /// It expands to `sd` `rs2, offset(rs1)`.
    ///
    /// # Forms
    /// Assembly: `c.sd xs2, imm(xs1)`
    /// Rust: `c_sd(rs1, rs2, imm)`
    ///
    /// # Arguments
    /// - `rs1` — Memory base register.
    /// - `rs2` — Source register.
    /// - `imm` — Immediate encoding value.
    pub fn c_sd<T0, T1, T2>(&mut self, rs1: T0, rs2: T1, imm: T2)
    where
        Self: CSdEmitter<T0, T1, T2>,
    {
        <Self as CSdEmitter<T0, T1, T2>>::c_sd(self, rs1, rs2, imm);
    }
    /// Store doubleword to stack
    ///
    /// Stores a 64-bit value in register rs2 to memory.
    /// It computes an effective address by adding the zero-extended offset, scaled by 8,
    /// to the stack pointer, x2.
    /// It expands to `sd` `rs2, offset(x2)`.
    ///
    /// # Forms
    /// Assembly: `c.sdsp xs2, imm(sp)`
    /// Rust: `c_sdsp(rs2, imm)`
    ///
    /// # Arguments
    /// - `rs2` — Instruction operand.
    /// - `imm` — Immediate encoding value.
    pub fn c_sdsp<T0, T1>(&mut self, rs2: T0, imm: T1)
    where
        Self: CSdspEmitter<T0, T1>,
    {
        <Self as CSdspEmitter<T0, T1>>::c_sdsp(self, rs2, imm);
    }
    /// Sign-extend byte, 16-bit encoding
    ///
    /// This instruction takes a single source/destination operand.
    /// This instruction sign-extends the least-significant byte of the source to XLEN by copying
    /// the most-significant bit in the byte (i.e., bit 7) to all of the more-significant bits.
    ///
    /// # Forms
    /// Assembly: `c.sext.b xd`
    /// Rust: `c_sext_b(rd)`
    ///
    /// # Arguments
    /// - `rd` — Destination/source register.
    pub fn c_sext_b<T0>(&mut self, rd: T0)
    where
        Self: CSextBEmitter<T0>,
    {
        <Self as CSextBEmitter<T0>>::c_sext_b(self, rd);
    }
    /// Sign-extend halfword, 16-bit encoding
    ///
    /// This instruction takes a single source/destination operand.
    /// This instruction sign-extends the least-significant halfword of the source to XLEN by copying
    /// the most-significant bit in the halfword (i.e., bit 15) to all of the more-significant bits.
    ///
    /// # Forms
    /// Assembly: `c.sext.h xd`
    /// Rust: `c_sext_h(rd)`
    ///
    /// # Arguments
    /// - `rd` — Destination/source register.
    pub fn c_sext_h<T0>(&mut self, rd: T0)
    where
        Self: CSextHEmitter<T0>,
    {
        <Self as CSextHEmitter<T0>>::c_sext_h(self, rd);
    }
    /// Store unsigned halfword, 16-bit encoding
    ///
    /// Stores a 16-bit value from register rs2 into memory.
    /// It computes an effective address by adding the zero-extended offset, to the base address in register rs1.
    /// It expands to `sh` `rs2, offset(rs1)`.
    ///
    /// # Forms
    /// Assembly: `c.sh xs2, imm(xs1)`
    /// Rust: `c_sh(rs1, rs2, imm)`
    ///
    /// # Arguments
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    /// - `imm` — Immediate encoding value.
    pub fn c_sh<T0, T1, T2>(&mut self, rs1: T0, rs2: T1, imm: T2)
    where
        Self: CShEmitter<T0, T1, T2>,
    {
        <Self as CShEmitter<T0, T1, T2>>::c_sh(self, rs1, rs2, imm);
    }
    /// Shift left logical immediate
    ///
    /// Shift the value in rd left by shamt, and store the result back in rd.
    /// C.SLLI expands into `slli rd, rd, shamt`.
    ///
    /// # Forms
    /// Assembly: `c.slli xd, shamt`
    /// Rust: `c_slli(rd, imm)`
    ///
    /// # Arguments
    /// - `rd` — Destination/source register.
    /// - `imm` — Immediate encoding value.
    pub fn c_slli<T0, T1>(&mut self, rd: T0, imm: T1)
    where
        Self: CSlliEmitter<T0, T1>,
    {
        <Self as CSlliEmitter<T0, T1>>::c_slli(self, rd, imm);
    }
    /// Shift left logical immediate
    ///
    /// Shift the value in rd left by shamt, and store the result back in rd.
    /// C.SLLI expands into `slli rd, rd, shamt`.
    ///
    /// # Forms
    /// Assembly: `c.slli.rv32 xd, shamt`
    /// Rust: `c_slli_rv32(rd, imm)`
    ///
    /// # Arguments
    /// - `rd` — Destination/source register.
    /// - `imm` — Immediate encoding value.
    pub fn c_slli_rv32<T0, T1>(&mut self, rd: T0, imm: T1)
    where
        Self: CSlliRv32Emitter<T0, T1>,
    {
        <Self as CSlliRv32Emitter<T0, T1>>::c_slli_rv32(self, rd, imm);
    }
    /// Shift right arithmetical immediate
    ///
    /// Arithmetic shift (the original sign bit is copied into the vacated upper bits) the value in rd right by shamt, and store the result in rd.
    /// The rd register index should be used as rd+8 (registers x8-x15).
    /// C.SRAI expands into `srai rd, rd, shamt`.
    ///
    /// # Forms
    /// Assembly: `c.srai xd, shamt`
    /// Rust: `c_srai(rd, imm)`
    ///
    /// # Arguments
    /// - `rd` — Destination/source register.
    /// - `imm` — Immediate encoding value.
    pub fn c_srai<T0, T1>(&mut self, rd: T0, imm: T1)
    where
        Self: CSraiEmitter<T0, T1>,
    {
        <Self as CSraiEmitter<T0, T1>>::c_srai(self, rd, imm);
    }
    /// Shift right arithmetical immediate
    ///
    /// Arithmetic shift (the original sign bit is copied into the vacated upper bits) the value in rd right by shamt, and store the result in rd.
    /// The rd register index should be used as rd+8 (registers x8-x15).
    /// C.SRAI expands into `srai rd, rd, shamt`.
    ///
    /// # Forms
    /// Assembly: `c.srai.rv32 xd, shamt`
    /// Rust: `c_srai_rv32(rd, imm)`
    ///
    /// # Arguments
    /// - `rd` — Destination/source register.
    /// - `imm` — Immediate encoding value.
    pub fn c_srai_rv32<T0, T1>(&mut self, rd: T0, imm: T1)
    where
        Self: CSraiRv32Emitter<T0, T1>,
    {
        <Self as CSraiRv32Emitter<T0, T1>>::c_srai_rv32(self, rd, imm);
    }
    /// Shift right logical immediate
    ///
    /// Shift the value in rd right by shamt, and store the result back in rd.
    /// The rd register index should be used as rd+8 (registers x8-x15).
    /// C.SRLI expands into `srli rd, rd, shamt`.
    ///
    /// # Forms
    /// Assembly: `c.srli xd, shamt`
    /// Rust: `c_srli(rd, imm)`
    ///
    /// # Arguments
    /// - `rd` — Destination/source register.
    /// - `imm` — Immediate encoding value.
    pub fn c_srli<T0, T1>(&mut self, rd: T0, imm: T1)
    where
        Self: CSrliEmitter<T0, T1>,
    {
        <Self as CSrliEmitter<T0, T1>>::c_srli(self, rd, imm);
    }
    /// Shift right logical immediate
    ///
    /// Shift the value in rd right by shamt, and store the result back in rd.
    /// The rd register index should be used as rd+8 (registers x8-x15).
    /// C.SRLI expands into `srli rd, rd, shamt`.
    ///
    /// # Forms
    /// Assembly: `c.srli.rv32 xd, shamt`
    /// Rust: `c_srli_rv32(rd, imm)`
    ///
    /// # Arguments
    /// - `rd` — Destination/source register.
    /// - `imm` — Immediate encoding value.
    pub fn c_srli_rv32<T0, T1>(&mut self, rd: T0, imm: T1)
    where
        Self: CSrliRv32Emitter<T0, T1>,
    {
        <Self as CSrliRv32Emitter<T0, T1>>::c_srli_rv32(self, rd, imm);
    }
    /// RISC-V `c.sspopchk.x5` instruction.
    ///
    /// # Forms
    /// Assembly: `c.sspopchk.x5`
    /// Rust: `c_sspopchk_x5()`
    ///
    /// # Arguments
    pub fn c_sspopchk_x5(&mut self)
    where
        Self: CSspopchkX5Emitter,
    {
        <Self as CSspopchkX5Emitter>::c_sspopchk_x5(self);
    }
    /// RISC-V `c.sspush.x1` instruction.
    ///
    /// # Forms
    /// Assembly: `c.sspush.x1`
    /// Rust: `c_sspush_x1()`
    ///
    /// # Arguments
    pub fn c_sspush_x1(&mut self)
    where
        Self: CSspushX1Emitter,
    {
        <Self as CSspushX1Emitter>::c_sspush_x1(self);
    }
    /// Subtract
    ///
    /// Subtract the value in rs2 from rd, and store the result in rd.
    /// The rd and rs2 register indexes should be used as rd+8 and rs2+8 (registers x8-x15).
    /// C.SUB expands into `sub rd, rd, rs2`.
    ///
    /// # Forms
    /// Assembly: `c.sub xd, rs2`
    /// Rust: `c_sub(rd, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination/source register.
    /// - `rs2` — Source register.
    pub fn c_sub<T0, T1>(&mut self, rd: T0, rs2: T1)
    where
        Self: CSubEmitter<T0, T1>,
    {
        <Self as CSubEmitter<T0, T1>>::c_sub(self, rd, rs2);
    }
    /// Subtract word
    ///
    /// Subtract the 32-bit values in rs2 from rd, and store the result in rd.
    /// The rd and rs2 register indexes should be used as rd+8 and rs2+8 (registers x8-x15).
    /// C.SUBW expands into `subw rd, rd, rs2`.
    ///
    /// # Forms
    /// Assembly: `c.subw xd, rs2`
    /// Rust: `c_subw(rd, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination/source register.
    /// - `rs2` — Source register.
    pub fn c_subw<T0, T1>(&mut self, rd: T0, rs2: T1)
    where
        Self: CSubwEmitter<T0, T1>,
    {
        <Self as CSubwEmitter<T0, T1>>::c_subw(self, rd, rs2);
    }
    /// Store word
    ///
    /// Stores a 32-bit value in register rs2 to memory.
    /// It computes an effective address by adding the zero-extended offset, scaled by 4,
    /// to the base address in register rs1.
    /// It expands to `sw` `rs2, offset(rs1)`.
    ///
    /// # Forms
    /// Assembly: `c.sw xs2, imm(xs1)`
    /// Rust: `c_sw(rs1, rs2, imm)`
    ///
    /// # Arguments
    /// - `rs1` — Memory base register.
    /// - `rs2` — Source register.
    /// - `imm` — Immediate encoding value.
    pub fn c_sw<T0, T1, T2>(&mut self, rs1: T0, rs2: T1, imm: T2)
    where
        Self: CSwEmitter<T0, T1, T2>,
    {
        <Self as CSwEmitter<T0, T1, T2>>::c_sw(self, rs1, rs2, imm);
    }
    /// Store word to stack
    ///
    /// Stores a 32-bit value in register rs2 to memory.
    /// It computes an effective address by adding the zero-extended offset, scaled by 4,
    /// to the stack pointer, x2.
    /// It expands to `sw` `rs2, offset(x2)`.
    ///
    /// # Forms
    /// Assembly: `c.swsp xs2, imm(sp)`
    /// Rust: `c_swsp(rs2, imm)`
    ///
    /// # Arguments
    /// - `rs2` — Instruction operand.
    /// - `imm` — Immediate encoding value.
    pub fn c_swsp<T0, T1>(&mut self, rs2: T0, imm: T1)
    where
        Self: CSwspEmitter<T0, T1>,
    {
        <Self as CSwspEmitter<T0, T1>>::c_swsp(self, rs2, imm);
    }
    /// Exclusive Or
    ///
    /// Exclusive or rd with rs2, and store the result in rd
    /// The rd and rs2 register indexes should be used as rd+8 and rs2+8 (registers x8-x15).
    /// C.XOR expands into `xor rd, rd, rs2`.
    ///
    /// # Forms
    /// Assembly: `c.xor xd, rs2`
    /// Rust: `c_xor(rd, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination/source register.
    /// - `rs2` — Source register.
    pub fn c_xor<T0, T1>(&mut self, rd: T0, rs2: T1)
    where
        Self: CXorEmitter<T0, T1>,
    {
        <Self as CXorEmitter<T0, T1>>::c_xor(self, rd, rs2);
    }
    /// Zero-extend byte, 16-bit encoding
    ///
    /// This instruction takes a single source/destination operand.
    /// This instruction zero-extends the least-significant byte of the source to XLEN by inserting
    /// 0's into all of the bits more significant than 7.
    ///
    /// # Forms
    /// Assembly: `c.zext.b xd`
    /// Rust: `c_zext_b(rd)`
    ///
    /// # Arguments
    /// - `rd` — Destination/source register.
    pub fn c_zext_b<T0>(&mut self, rd: T0)
    where
        Self: CZextBEmitter<T0>,
    {
        <Self as CZextBEmitter<T0>>::c_zext_b(self, rd);
    }
    /// Zero-extend halfword, 16-bit encoding
    ///
    /// This instruction takes a single source/destination operand.
    /// This instruction zero-extends the least-significant halfword of the source to XLEN by inserting
    /// 0's into all of the bits more significant than 15.
    ///
    /// # Forms
    /// Assembly: `c.zext.h xd`
    /// Rust: `c_zext_h(rd)`
    ///
    /// # Arguments
    /// - `rd` — Destination/source register.
    pub fn c_zext_h<T0>(&mut self, rd: T0)
    where
        Self: CZextHEmitter<T0>,
    {
        <Self as CZextHEmitter<T0>>::c_zext_h(self, rd);
    }
    /// Zero-extend word, 16-bit encoding
    ///
    /// This instruction takes a single source/destination operand.
    /// It zero-extends the least-significant word of the operand to XLEN bits by inserting zeros into all of the bits more significant than 31.
    ///
    /// # Forms
    /// Assembly: `c.zext.w xd`
    /// Rust: `c_zext_w(rd)`
    ///
    /// # Arguments
    /// - `rd` — Destination/source register.
    pub fn c_zext_w<T0>(&mut self, rd: T0)
    where
        Self: CZextWEmitter<T0>,
    {
        <Self as CZextWEmitter<T0>>::c_zext_w(self, rd);
    }
    /// Cache Block Clean
    ///
    /// Cleans an entire cache block globally throughout the system.
    ///
    /// Exactly what happens is coherence protocol-dependent, but in general it is expected that after this
    /// operation():
    ///
    ///   * The cache block will be in the clean (not dirty) state in any coherent cache holding a valid copy of the line.
    ///   * The data will be cleaned to a point such that an incoherent load can observe the cleaned data.
    ///
    /// `cbo.clean` is ordered by `FENCE` instructions but not `FENCE.I` or `SFENCE.VMA`.
    ///
    /// &lt;%- if CACHE_BLOCK_SIZE.bit_length &gt; \[PMP_GRANULARITY, PMA_GRANULARITY\].min -%&gt;
    /// Both PMP and PMA access control must be the same for all bytes in the block; otherwise, `cbo.clean` has UNSPECIFIED behavior.
    /// &lt;%- end -%&gt;
    ///
    /// Clean operations are treated as stores for page and access permissions. If permission checks fail,
    /// one of the following exceptions will occur:
    ///
    ///   &lt;%- if ext?(:H) -%&gt;
    ///   * `Store/AMO Guest-Page Fault` if virtual memory translation fails during G-stage translation.
    ///   &lt;%- end -%&gt;
    ///   * `Store/AMO Page Fault` if virtual memory translation fails &lt;% if ext?(:H) %&gt;when V=0 or during VS-stage translation&lt;% end %&gt;
    ///   * `Store/AMO Access Fault` if a PMP or PMA access check fails
    ///
    /// &lt;%- if CACHE_BLOCK_SIZE.bit_length &lt;= \[PMP_GRANULARITY, PMA_GRANULARITY\].min -%&gt;
    /// Because cache blocks are naturally aligned and always fit in a single PMP or PMA regions, the PMP
    /// and PMA access checks only need to check a single address in the line.
    /// &lt;%- end -%&gt;
    ///
    /// CBO operations never raise a misaligned address fault.
    ///
    /// # Forms
    /// Assembly: `cbo.clean "TODO"`
    /// Rust: `cbo_clean(rs1)`
    ///
    /// # Arguments
    /// - `rs1` — Source register.
    pub fn cbo_clean<T0>(&mut self, rs1: T0)
    where
        Self: CboCleanEmitter<T0>,
    {
        <Self as CboCleanEmitter<T0>>::cbo_clean(self, rs1);
    }
    /// Cache Block Flush
    ///
    /// Flushes an entire cache block by cleaning it and then invalidating it in all caches.
    ///
    /// `cbo.flush` is ordered by `FENCE` instructions but not `FENCE.I` or `SFENCE.VMA`.
    ///
    /// &lt;%- if CACHE_BLOCK_SIZE.bit_length &gt; \[PMP_GRANULARITY, PMA_GRANULARITY\].min -%&gt;
    /// Both PMP and PMA access control must be the same for all bytes in the block; otherwise, `cbo.flush` has UNSPECIFIED behavior.
    /// &lt;%- end -%&gt;
    ///
    /// Flush operations are treated as stores for page and access permissions. If permission checks fail,
    /// one of the following exceptions will occur:
    ///
    ///   &lt;%- if ext?(:H) -%&gt;
    ///   * `Store/AMO Guest-Page Fault` if virtual memory translation fails during G-stage translation.
    ///   &lt;%- end -%&gt;
    ///   * `Store/AMO Page Fault` if virtual memory translation fails &lt;% if ext?(:H) %&gt;when V=0 or during VS-stage translation&lt;% end %&gt;
    ///   * `Store/AMO Access Fault` if a PMP or PMA access check fails.
    ///
    /// &lt;%- if CACHE_BLOCK_SIZE.bit_length &lt;= \[PMP_GRANULARITY, PMA_GRANULARITY\].min -%&gt;
    /// Because cache blocks are naturally aligned and always fit in a single PMP or PMA regions, the PMP
    /// and PMA access checks only need to check a single address in the line.
    /// &lt;%- end -%&gt;
    ///
    /// CBO operations never raise a misaligned address fault.
    ///
    /// # Forms
    /// Assembly: `cbo.flush "TODO"`
    /// Rust: `cbo_flush(rs1)`
    ///
    /// # Arguments
    /// - `rs1` — Source register.
    pub fn cbo_flush<T0>(&mut self, rs1: T0)
    where
        Self: CboFlushEmitter<T0>,
    {
        <Self as CboFlushEmitter<T0>>::cbo_flush(self, rs1);
    }
    /// Cache Block Invalidate
    ///
    /// Either invalidates or flushes (clean + invalidate) a cache block, depending on the current mode and value of
    /// `menvcfg.CBIE`, `senvcfg.CBIE`, and/or `henvcfg.CBIE`.
    ///
    /// The instruction is an invalidate (without a clean) when:
    ///
    ///   * In M-mode
    ///   * In (H)S-mode and `menvcfg.CBIE` == 11
    ///   * In U-mode and `menvcfg.CBIE` == 11 and `senvcfg.CBIE` == 11
    ///   * In VS-mode and `menvcfg.CBIE` == 11 and `henvcfg.CBIE` == 11
    ///   * In VU-mode and `menvcfg.CBIE` == 11 and `henvcfg.CBIE` == 11 and `senvcfg.CBIE` == 11
    ///
    /// Otherwise, if the instruction does not trap (see Access section), the operation is a flush.
    /// The table below summarizes the options.
    ///
    /// \[%autowidth,cols="1,1,1,1,1,1,1,1",separator="!"\]
    /// !===
    /// .2+h!\[.rotate\]#`menvcfg.CBIE`# .2+h! \[.rotate\]#`senvcfg.CBIE`# .2+h! \[.rotate\]#`henvcfg.CBIE`#
    /// 5+^.&gt;h! `cbe.inval` Operation
    /// .^h! M-mode .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode
    ///
    /// ! 00 ! - ! - ! Invalidate ! `Illegal Instruction` ! `Illegal Instruction` ! `Virtual Instruction` ! `Virtual Instruction`
    /// ! 01 ! 00 ! 00 ! Invalidate ! Flush  ! `Illegal Instruction` ! `Virtual Instruction` ! `Virtual Instruction`
    /// ! 01 ! 00 ! 01 ! Invalidate ! Flush  ! `Illegal Instruction` ! Flush ! `Virtual Instruction`
    /// ! 01 ! 00 ! 11 ! Invalidate ! Flush  ! `Illegal Instruction` ! Flush ! `Virtual Instruction`
    /// ! 01 ! 01 ! 00 ! Invalidate ! Flush  ! Flush ! `Virtual Instruction` ! `Virtual Instruction`
    /// ! 01 ! 01 ! 01 ! Invalidate ! Flush  ! Flush ! Flush ! Flush
    /// ! 01 ! 01 ! 11 ! Invalidate ! Flush  ! Flush ! Flush ! Flush
    /// ! 01 ! 11 ! 00 ! Invalidate ! Flush  ! Flush ! `Virtual Instruction` ! `Virtual Instruction`
    /// ! 01 ! 11 ! 01 ! Invalidate ! Flush  ! Flush ! Flush ! Flush
    /// ! 01 ! 11 ! 11 ! Invalidate ! Flush  ! Flush ! Flush ! Flush
    /// ! 11 ! 00 ! 00  ! Invalidate ! Invalidate  ! `Illegal Instruction` ! `Virtual Instruction` ! `Virtual Instruction`
    /// ! 11 ! 00 ! 01  ! Invalidate ! Invalidate  ! `Illegal Instruction` ! Flush ! `Virtual Instruction`
    /// ! 11 ! 00 ! 11  ! Invalidate ! Invalidate  ! `Illegal Instruction` ! Invalidate ! `Virtual Instruction`
    /// ! 11 ! 01 ! 00 ! Invalidate ! Invalidate  ! Flush ! `Virtual Instruction` ! `Virtual Instruction`
    /// ! 11 ! 01 ! 01 ! Invalidate ! Invalidate  ! Flush ! Flush ! Flush
    /// ! 11 ! 01 ! 11 ! Invalidate ! Invalidate  ! Flush ! Invalidate ! Flush
    /// ! 11 ! 11 ! 00 ! Invalidate ! Invalidate  ! Invalidate ! `Virtual Instruction` ! `Virtual Instruction`
    /// ! 11 ! 11 ! 01 ! Invalidate ! Invalidate  ! Invalidate ! Flush ! Flush
    /// ! 11 ! 11 ! 11 ! Invalidate ! Invalidate  ! Invalidate ! Invalidate ! Invalidate
    /// !===
    ///
    /// `cbo.inval` is ordered by `FENCE` instructions but not `FENCE.I` or `SFENCE.VMA`.
    ///
    /// &lt;%- if CACHE_BLOCK_SIZE.bit_length &gt; \[PMP_GRANULARITY, PMA_GRANULARITY\].min -%&gt;
    /// Both PMP and PMA access control must be the same for all bytes in the block; otherwise, `cbo.zero` has UNSPECIFIED behavior.
    /// &lt;%- end -%&gt;
    ///
    /// Invalidate operations are treated as stores for page and access permissions. If permission checks fail,
    /// one of the following exceptions will occur:
    ///
    ///   &lt;%- if ext?(:H) -%&gt;
    ///   * `Store/AMO Guest-Page Fault` if virtual memory translation fails during G-stage translation.
    ///   &lt;%- end -%&gt;
    ///   * `Store/AMO Page Fault` if virtual memory translation fails &lt;% if ext?(:H) %&gt;when V=0 or during VS-stage translation&lt;% end %&gt;
    ///   * `Store/AMO Access Fault` if a PMP or PMA access check fails.
    ///
    /// &lt;%- if CACHE_BLOCK_SIZE.bit_length &lt;= \[PMP_GRANULARITY, PMA_GRANULARITY\].min -%&gt;
    /// Because cache blocks are naturally aligned and always fit in a single PMP or PMA regions, the PMP
    /// and PMA access checks only need to check a single address in the line.
    /// &lt;%- end -%&gt;
    ///
    /// CBO operations never raise a misaligned address fault.
    ///
    /// # Forms
    /// Assembly: `cbo.inval "TODO"`
    /// Rust: `cbo_inval(rs1)`
    ///
    /// # Arguments
    /// - `rs1` — Source register.
    pub fn cbo_inval<T0>(&mut self, rs1: T0)
    where
        Self: CboInvalEmitter<T0>,
    {
        <Self as CboInvalEmitter<T0>>::cbo_inval(self, rs1);
    }
    /// Cache Block Zero
    ///
    /// Zeros an entire cache block
    ///
    /// The block zeroing does not need to be atomic.
    ///
    /// `cbo.zero` is ordered by `FENCE` instructions but not `FENCE.I` or `SFENCE.VMA`.
    ///
    /// &lt;%- if CACHE_BLOCK_SIZE.bit_length &gt; \[PMP_GRANULARITY, PMA_GRANULARITY\].min -%&gt;
    /// Both PMP and PMA access control must be the same for all bytes in the block; otherwise, `cbo.zero` has UNSPECIFIED behavior.
    /// &lt;%- end -%&gt;
    ///
    /// Clean operations are treated as stores for page and access permissions. If permission checks fail,
    /// one of the following exceptions will occur:
    ///
    ///   &lt;%- if ext?(:H) -%&gt;
    ///   * `Store/AMO Guest-Page Fault` if virtual memory translation fails during G-stage translation.
    ///   &lt;%- end -%&gt;
    ///   * `Store/AMO Page Fault` if virtual memory translation fails &lt;% if ext?(:H) %&gt;when V=0 or during VS-stage translation&lt;% end %&gt;
    ///   * `Store/AMO Access Fault` if a PMP or PMA access check fails.
    ///
    /// &lt;%- if CACHE_BLOCK_SIZE.bit_length &lt;= \[PMP_GRANULARITY, PMA_GRANULARITY\].min -%&gt;
    /// Because cache blocks are naturally aligned and always fit in a single PMP or PMA regions, the PMP
    /// and PMA access checks only need to check a single address in the line.
    /// &lt;%- end -%&gt;
    ///
    /// CBO operations never raise a misaligned address fault.
    ///
    /// # Forms
    /// Assembly: `cbo.zero "TODO"`
    /// Rust: `cbo_zero(rs1)`
    ///
    /// # Arguments
    /// - `rs1` — Source register.
    pub fn cbo_zero<T0>(&mut self, rs1: T0)
    where
        Self: CboZeroEmitter<T0>,
    {
        <Self as CboZeroEmitter<T0>>::cbo_zero(self, rs1);
    }
    /// Carry-less multiply (low-part)
    ///
    /// `clmul` produces the lower half of the 2*XLEN carry-less product
    ///
    /// # Forms
    /// Assembly: `clmul xd, xs1, xs2`
    /// Rust: `clmul(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn clmul<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: ClmulEmitter<T0, T1, T2>,
    {
        <Self as ClmulEmitter<T0, T1, T2>>::clmul(self, rd, rs1, rs2);
    }
    /// Carry-less multiply (high-part)
    ///
    /// `clmulh` produces the upper half of the 2*XLEN carry-less product
    ///
    /// # Forms
    /// Assembly: `clmulh xd, xs1, xs2`
    /// Rust: `clmulh(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn clmulh<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: ClmulhEmitter<T0, T1, T2>,
    {
        <Self as ClmulhEmitter<T0, T1, T2>>::clmulh(self, rd, rs1, rs2);
    }
    /// Carry-less multiply (reversed)
    ///
    /// `clmulr` produces bits 2*XLEN-2:XLEN-1 of the 2*XLEN carry-less product
    ///
    /// # Forms
    /// Assembly: `clmulr xd, xs1, xs2`
    /// Rust: `clmulr(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn clmulr<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: ClmulrEmitter<T0, T1, T2>,
    {
        <Self as ClmulrEmitter<T0, T1, T2>>::clmulr(self, rd, rs1, rs2);
    }
    /// Count leading zero bits
    ///
    /// This instruction counts the number of 0's before the first 1,
    /// starting at the most-significant bit (i.e., XLEN-1) and progressing to bit 0.
    /// Accordingly, if the input is 0, the output is XLEN, and if the most-significant
    /// bit of the input is a 1, the output is 0.
    ///
    /// # Forms
    /// Assembly: `clz xd, xs1`
    /// Rust: `clz(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn clz<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: ClzEmitter<T0, T1>,
    {
        <Self as ClzEmitter<T0, T1>>::clz(self, rd, rs1);
    }
    /// Count leading zero bits in word
    ///
    /// This instruction counts the number of 0's before the first 1 starting at bit 31 and progressing to bit 0.
    /// Accordingly, if the least-significant word is 0, the output is 32, and if the most-significant
    /// bit of the word (_i.e._, bit 31) is a 1, the output is 0.
    ///
    /// # Forms
    /// Assembly: `clzw xd, xs1`
    /// Rust: `clzw(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn clzw<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: ClzwEmitter<T0, T1>,
    {
        <Self as ClzwEmitter<T0, T1>>::clzw(self, rd, rs1);
    }
    /// RISC-V `cm.jalt` instruction.
    ///
    /// # Forms
    /// Assembly: `cm.jalt c_index`
    /// Rust: `cm_jalt(index)`
    ///
    /// # Arguments
    /// - `index` — Instruction operand.
    pub fn cm_jalt<T0>(&mut self, index: T0)
    where
        Self: CmJaltEmitter<T0>,
    {
        <Self as CmJaltEmitter<T0>>::cm_jalt(self, index);
    }
    /// Count set bits
    ///
    /// This instructions counts the number of 1's (i.e., set bits) in the source register.
    ///
    /// .Software Hint
    /// \[NOTE\]
    /// ----
    /// This operations is known as population count, popcount, sideways sum,
    /// bit summation, or Hamming weight.
    ///
    /// The GCC builtin function `__builtin_popcount (unsigned int x)` is
    /// implemented by cpop on RV32 and by cpopw on RV64. The GCC builtin
    /// function `__builtin_popcountl (unsigned long x)` for LP64 is
    /// implemented by cpop on RV64.
    /// ----
    ///
    /// # Forms
    /// Assembly: `cpop xd, xs1`
    /// Rust: `cpop(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn cpop<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: CpopEmitter<T0, T1>,
    {
        <Self as CpopEmitter<T0, T1>>::cpop(self, rd, rs1);
    }
    /// Count set bits in word
    ///
    /// This instructions counts the number of 1's (i.e., set bits) in the least-significant word of the source register.
    ///
    /// .Software Hint
    /// \[NOTE\]
    /// ----
    /// This operations is known as population count, popcount, sideways sum,
    /// bit summation, or Hamming weight.
    ///
    /// The GCC builtin function `__builtin_popcount (unsigned int x)` is
    /// implemented by cpop on RV32 and by cpopw on RV64. The GCC builtin
    /// function `__builtin_popcountl (unsigned long x)` for LP64 is
    /// implemented by cpop on RV64.
    /// ----
    ///
    /// # Forms
    /// Assembly: `cpopw xd, xs1`
    /// Rust: `cpopw(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn cpopw<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: CpopwEmitter<T0, T1>,
    {
        <Self as CpopwEmitter<T0, T1>>::cpopw(self, rd, rs1);
    }
    /// RISC-V `csrc` instruction.
    ///
    /// # Forms
    /// Assembly: `csrc rs1 csr`
    /// Rust: `csrc(rs1, csr)`
    ///
    /// # Arguments
    /// - `rs1` — Source register.
    /// - `csr` — Control and status register number.
    pub fn csrc<T0, T1>(&mut self, rs1: T0, csr: T1)
    where
        Self: CsrcEmitter<T0, T1>,
    {
        <Self as CsrcEmitter<T0, T1>>::csrc(self, rs1, csr);
    }
    /// RISC-V `csrci` instruction.
    ///
    /// # Forms
    /// Assembly: `csrci csr zimm5`
    /// Rust: `csrci(csr, zimm5)`
    ///
    /// # Arguments
    /// - `csr` — Control and status register number.
    /// - `zimm5` — Immediate encoding value.
    pub fn csrci<T0, T1>(&mut self, csr: T0, zimm5: T1)
    where
        Self: CsrciEmitter<T0, T1>,
    {
        <Self as CsrciEmitter<T0, T1>>::csrci(self, csr, zimm5);
    }
    /// RISC-V `csrr` instruction.
    ///
    /// # Forms
    /// Assembly: `csrr rd csr`
    /// Rust: `csrr(rd, csr)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `csr` — Control and status register number.
    pub fn csrr<T0, T1>(&mut self, rd: T0, csr: T1)
    where
        Self: CsrrEmitter<T0, T1>,
    {
        <Self as CsrrEmitter<T0, T1>>::csrr(self, rd, csr);
    }
    /// RISC-V `csrrc` instruction.
    ///
    /// # Forms
    /// Assembly: `csrrc xd, xs1, csr`
    /// Rust: `csrrc(rd, rs1, csr)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `csr` — Control and status register number.
    pub fn csrrc<T0, T1, T2>(&mut self, rd: T0, rs1: T1, csr: T2)
    where
        Self: CsrrcEmitter<T0, T1, T2>,
    {
        <Self as CsrrcEmitter<T0, T1, T2>>::csrrc(self, rd, rs1, csr);
    }
    /// RISC-V `csrrci` instruction.
    ///
    /// # Forms
    /// Assembly: `csrrci xd, csr, imm`
    /// Rust: `csrrci(rd, csr, zimm5)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `csr` — Control and status register number.
    /// - `zimm5` — Immediate encoding value.
    pub fn csrrci<T0, T1, T2>(&mut self, rd: T0, csr: T1, zimm5: T2)
    where
        Self: CsrrciEmitter<T0, T1, T2>,
    {
        <Self as CsrrciEmitter<T0, T1, T2>>::csrrci(self, rd, csr, zimm5);
    }
    /// Atomic Read and Set Bits in CSR
    ///
    /// Atomically read and set bits in a CSR.
    ///
    /// Reads the value of the CSR, zero-extends the value to `XLEN` bits,
    /// and writes it to integer register `rd`. The initial value in integer
    /// register `rs1` is treated as a bit mask that specifies bit positions
    /// to be set in the CSR. Any bit that is high in `rs1` will cause the
    /// corresponding bit to be set in the CSR, if that CSR bit is writable.
    /// Other bits in the CSR are not explicitly written.
    ///
    /// # Forms
    /// Assembly: `csrrs xd, xs1, csr`
    /// Rust: `csrrs(rd, rs1, csr)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `csr` — Control and status register number.
    pub fn csrrs<T0, T1, T2>(&mut self, rd: T0, rs1: T1, csr: T2)
    where
        Self: CsrrsEmitter<T0, T1, T2>,
    {
        <Self as CsrrsEmitter<T0, T1, T2>>::csrrs(self, rd, rs1, csr);
    }
    /// RISC-V `csrrsi` instruction.
    ///
    /// # Forms
    /// Assembly: `csrrsi xd, csr, imm`
    /// Rust: `csrrsi(rd, csr, zimm5)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `csr` — Control and status register number.
    /// - `zimm5` — Immediate encoding value.
    pub fn csrrsi<T0, T1, T2>(&mut self, rd: T0, csr: T1, zimm5: T2)
    where
        Self: CsrrsiEmitter<T0, T1, T2>,
    {
        <Self as CsrrsiEmitter<T0, T1, T2>>::csrrsi(self, rd, csr, zimm5);
    }
    /// Atomic Read/Write CSR
    ///
    /// Atomically swap values in the CSRs and integer registers.
    ///
    /// Read the old value of the CSR, zero-extends the value to `XLEN` bits,
    /// and then write it to integer register rd.
    /// The initial value in rs1 is written to the CSR.
    /// If `rd=x0`, then the instruction shall not read the CSR and shall not
    /// cause any of the side effects that might occur on a CSR read.
    ///
    /// # Forms
    /// Assembly: `csrrw xd, xs1, csr`
    /// Rust: `csrrw(rd, rs1, csr)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `csr` — Control and status register number.
    pub fn csrrw<T0, T1, T2>(&mut self, rd: T0, rs1: T1, csr: T2)
    where
        Self: CsrrwEmitter<T0, T1, T2>,
    {
        <Self as CsrrwEmitter<T0, T1, T2>>::csrrw(self, rd, rs1, csr);
    }
    /// Atomic Read/Write CSR Immediate
    ///
    /// Atomically write CSR using a 5-bit immediate, and load the previous value into 'rd'.
    ///
    /// Read the old value of the CSR, zero-extends the value to `XLEN` bits,
    /// and then write it to integer register rd.
    /// The 5-bit uimm field is zero-extended and written to the CSR.
    /// If `rd=x0`, then the instruction shall not read the CSR and shall not
    /// cause any of the side effects that might occur on a CSR read.
    ///
    /// # Forms
    /// Assembly: `csrrwi xd, zimm, csr`
    /// Rust: `csrrwi(rd, csr, zimm5)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `csr` — Control and status register number.
    /// - `zimm5` — Immediate encoding value.
    pub fn csrrwi<T0, T1, T2>(&mut self, rd: T0, csr: T1, zimm5: T2)
    where
        Self: CsrrwiEmitter<T0, T1, T2>,
    {
        <Self as CsrrwiEmitter<T0, T1, T2>>::csrrwi(self, rd, csr, zimm5);
    }
    /// RISC-V `csrs` instruction.
    ///
    /// # Forms
    /// Assembly: `csrs rs1 csr`
    /// Rust: `csrs(rs1, csr)`
    ///
    /// # Arguments
    /// - `rs1` — Source register.
    /// - `csr` — Control and status register number.
    pub fn csrs<T0, T1>(&mut self, rs1: T0, csr: T1)
    where
        Self: CsrsEmitter<T0, T1>,
    {
        <Self as CsrsEmitter<T0, T1>>::csrs(self, rs1, csr);
    }
    /// RISC-V `csrsi` instruction.
    ///
    /// # Forms
    /// Assembly: `csrsi csr zimm5`
    /// Rust: `csrsi(csr, zimm5)`
    ///
    /// # Arguments
    /// - `csr` — Control and status register number.
    /// - `zimm5` — Immediate encoding value.
    pub fn csrsi<T0, T1>(&mut self, csr: T0, zimm5: T1)
    where
        Self: CsrsiEmitter<T0, T1>,
    {
        <Self as CsrsiEmitter<T0, T1>>::csrsi(self, csr, zimm5);
    }
    /// RISC-V `csrw` instruction.
    ///
    /// # Forms
    /// Assembly: `csrw rs1 csr`
    /// Rust: `csrw(rs1, csr)`
    ///
    /// # Arguments
    /// - `rs1` — Source register.
    /// - `csr` — Control and status register number.
    pub fn csrw<T0, T1>(&mut self, rs1: T0, csr: T1)
    where
        Self: CsrwEmitter<T0, T1>,
    {
        <Self as CsrwEmitter<T0, T1>>::csrw(self, rs1, csr);
    }
    /// RISC-V `csrwi` instruction.
    ///
    /// # Forms
    /// Assembly: `csrwi csr zimm5`
    /// Rust: `csrwi(csr, zimm5)`
    ///
    /// # Arguments
    /// - `csr` — Control and status register number.
    /// - `zimm5` — Immediate encoding value.
    pub fn csrwi<T0, T1>(&mut self, csr: T0, zimm5: T1)
    where
        Self: CsrwiEmitter<T0, T1>,
    {
        <Self as CsrwiEmitter<T0, T1>>::csrwi(self, csr, zimm5);
    }
    /// Count trailing zero bits
    ///
    /// This instruction counts the number of 0's before the first 1,
    /// starting at the least-significant bit (i.e., 0) and progressing
    /// to the most-significant bit (i.e., XLEN-1). Accordingly, if the
    /// input is 0, the output is XLEN, and if the least-significant bit
    /// of the input is a 1, the output is 0.
    ///
    /// # Forms
    /// Assembly: `ctz xd, xs1`
    /// Rust: `ctz(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn ctz<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: CtzEmitter<T0, T1>,
    {
        <Self as CtzEmitter<T0, T1>>::ctz(self, rd, rs1);
    }
    /// Count trailing zero bits in word
    ///
    /// This instruction counts the number of 0's before the first 1,
    /// starting at the least-significant bit (i.e., 0) and progressing
    /// to the most-significant bit of the least-significant word (i.e., 31). Accordingly, if the
    /// least-significant word is 0, the output is 32, and if the least-significant bit
    /// of the input is a 1, the output is 0.
    ///
    /// # Forms
    /// Assembly: `ctzw xd, xs1`
    /// Rust: `ctzw(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn ctzw<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: CtzwEmitter<T0, T1>,
    {
        <Self as CtzwEmitter<T0, T1>>::ctzw(self, rd, rs1);
    }
    /// RISC-V `czero.eqz` instruction.
    ///
    /// # Forms
    /// Assembly: `czero.eqz xd, xs1, xs2`
    /// Rust: `czero_eqz(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn czero_eqz<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: CzeroEqzEmitter<T0, T1, T2>,
    {
        <Self as CzeroEqzEmitter<T0, T1, T2>>::czero_eqz(self, rd, rs1, rs2);
    }
    /// RISC-V `czero.nez` instruction.
    ///
    /// # Forms
    /// Assembly: `czero.nez xd, xs1, xs2`
    /// Rust: `czero_nez(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn czero_nez<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: CzeroNezEmitter<T0, T1, T2>,
    {
        <Self as CzeroNezEmitter<T0, T1, T2>>::czero_nez(self, rd, rs1, rs2);
    }
    /// Signed division
    ///
    /// Divide rs1 by rs2, and store the result in rd. The remainder is discarded.
    ///
    /// Division by zero will put -1 into rd.
    ///
    /// Division resulting in signed overflow (when most negative number is divided by -1)
    /// will put the most negative number into rd;
    ///
    /// # Forms
    /// Assembly: `div xd, xs1, xs2`
    /// Rust: `div(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn div<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: DivEmitter<T0, T1, T2>,
    {
        <Self as DivEmitter<T0, T1, T2>>::div(self, rd, rs1, rs2);
    }
    /// Unsigned division
    ///
    /// Divide unsigned values in rs1 by rs2, and store the result in rd.
    ///
    /// The remainder is discarded.
    ///
    /// If the value in rs2 is zero, rd gets the largest unsigned value.
    ///
    /// # Forms
    /// Assembly: `divu xd, xs1, xs2`
    /// Rust: `divu(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn divu<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: DivuEmitter<T0, T1, T2>,
    {
        <Self as DivuEmitter<T0, T1, T2>>::divu(self, rd, rs1, rs2);
    }
    /// Unsigned 32-bit division
    ///
    /// Divide the unsigned 32-bit values in rs1 and rs2, and store the sign-extended result in rd.
    ///
    /// The remainder is discarded.
    ///
    /// If the value in rs2 is zero, rd is written with all 1s.
    ///
    /// # Forms
    /// Assembly: `divuw xd, xs1, xs2`
    /// Rust: `divuw(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn divuw<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: DivuwEmitter<T0, T1, T2>,
    {
        <Self as DivuwEmitter<T0, T1, T2>>::divuw(self, rd, rs1, rs2);
    }
    /// Signed 32-bit division
    ///
    /// Divide the lower 32-bits of register rs1 by the lower 32-bits of register rs2,
    /// and store the sign-extended result in rd.
    ///
    /// The remainder is discarded.
    ///
    /// Division by zero will put -1 into rd.
    ///
    /// Division resulting in signed overflow (when most negative number is divided by -1)
    /// will put the most negative number into rd;
    ///
    /// # Forms
    /// Assembly: `divw xd, xs1, xs2`
    /// Rust: `divw(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn divw<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: DivwEmitter<T0, T1, T2>,
    {
        <Self as DivwEmitter<T0, T1, T2>>::divw(self, rd, rs1, rs2);
    }
    /// RISC-V `dret` instruction.
    ///
    /// # Forms
    /// Assembly: `dret dret`
    /// Rust: `dret()`
    ///
    /// # Arguments
    pub fn dret(&mut self)
    where
        Self: DretEmitter,
    {
        <Self as DretEmitter>::dret(self);
    }
    /// Breakpoint exception
    ///
    /// The EBREAK instruction is used by debuggers to cause control to be transferred back to
    /// a debugging environment. Unless overridden by an external debug environment,
    /// EBREAK raises a breakpoint exception and performs no other operation.
    ///
    /// \[NOTE\]
    /// As described in the `C` Standard Extension for Compressed Instructions, the `c.ebreak`
    /// instruction performs the same operation as the EBREAK instruction.
    ///
    /// EBREAK causes the receiving privilege mode's epc register to be set to the address of
    /// the EBREAK instruction itself, not the address of the following instruction.
    /// As EBREAK causes a synchronous exception, it is not considered to retire,
    /// and should not increment the `minstret` CSR.
    ///
    /// # Forms
    /// Assembly: `ebreak ""`
    /// Rust: `ebreak()`
    ///
    /// # Arguments
    pub fn ebreak(&mut self)
    where
        Self: EbreakEmitter,
    {
        <Self as EbreakEmitter>::ebreak(self);
    }
    /// Environment call
    ///
    /// The ECALL instruction is used to make a request to the supporting execution environment.
    /// When executed in U-mode, S-mode, or M-mode, it generates an environment-call-from-U-mode
    /// exception, environment-call-from-S-mode exception, or environment-call-from-M-mode
    /// exception, respectively, and performs no other operation.
    ///
    /// \[NOTE\]
    /// ECALL generates a different exception for each originating privilege mode so that
    /// environment call exceptions can be selectively delegated.
    /// A typical use case for Unix-like operating systems is to delegate to S-mode
    /// the environment-call-from-U-mode exception but not the others.
    ///
    /// ECALL causes the receiving privilege mode's epc register to be set to the address of
    /// the ECALL instruction itself, not the address of the following instruction.
    /// As ECALL causes a synchronous exception, it is not considered to retire,
    /// and should not increment the `minstret` CSR.
    ///
    /// # Forms
    /// Assembly: `ecall ""`
    /// Rust: `ecall()`
    ///
    /// # Arguments
    pub fn ecall(&mut self)
    where
        Self: EcallEmitter,
    {
        <Self as EcallEmitter>::ecall(self);
    }
    /// RISC-V `fabs.d` instruction.
    ///
    /// # Forms
    /// Assembly: `fabs.d rd rs1 rs2_eq_rs1`
    /// Rust: `fabs_d(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn fabs_d<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: FabsDEmitter<T0, T1, T2>,
    {
        <Self as FabsDEmitter<T0, T1, T2>>::fabs_d(self, rd, rs1, rs2);
    }
    /// RISC-V `fabs.h` instruction.
    ///
    /// # Forms
    /// Assembly: `fabs.h rd rs1 rs2_eq_rs1`
    /// Rust: `fabs_h(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn fabs_h<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: FabsHEmitter<T0, T1, T2>,
    {
        <Self as FabsHEmitter<T0, T1, T2>>::fabs_h(self, rd, rs1, rs2);
    }
    /// RISC-V `fabs.q` instruction.
    ///
    /// # Forms
    /// Assembly: `fabs.q rd rs1 rs2_eq_rs1`
    /// Rust: `fabs_q(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn fabs_q<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: FabsQEmitter<T0, T1, T2>,
    {
        <Self as FabsQEmitter<T0, T1, T2>>::fabs_q(self, rd, rs1, rs2);
    }
    /// RISC-V `fabs.s` instruction.
    ///
    /// # Forms
    /// Assembly: `fabs.s rd rs1 rs2_eq_rs1`
    /// Rust: `fabs_s(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn fabs_s<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: FabsSEmitter<T0, T1, T2>,
    {
        <Self as FabsSEmitter<T0, T1, T2>>::fabs_s(self, rd, rs1, rs2);
    }
    /// RISC-V `fadd.d` instruction.
    ///
    /// # Forms
    /// Assembly: `fadd.d xd, xs1, xs2, rm`
    /// Rust: `fadd_d(rd, rs1, rs2, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fadd_d<T0, T1, T2, T3>(&mut self, rd: T0, rs1: T1, rs2: T2, rm: T3)
    where
        Self: FaddDEmitter<T0, T1, T2, T3>,
    {
        <Self as FaddDEmitter<T0, T1, T2, T3>>::fadd_d(self, rd, rs1, rs2, rm);
    }
    /// RISC-V `fadd.h` instruction.
    ///
    /// # Forms
    /// Assembly: `fadd.h xd, xs1, xs2, rm`
    /// Rust: `fadd_h(rd, rs1, rs2, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fadd_h<T0, T1, T2, T3>(&mut self, rd: T0, rs1: T1, rs2: T2, rm: T3)
    where
        Self: FaddHEmitter<T0, T1, T2, T3>,
    {
        <Self as FaddHEmitter<T0, T1, T2, T3>>::fadd_h(self, rd, rs1, rs2, rm);
    }
    /// RISC-V `fadd.q` instruction.
    ///
    /// # Forms
    /// Assembly: `fadd.q qd, qs1, qs2, rm`
    /// Rust: `fadd_q(rd, rs1, rs2, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fadd_q<T0, T1, T2, T3>(&mut self, rd: T0, rs1: T1, rs2: T2, rm: T3)
    where
        Self: FaddQEmitter<T0, T1, T2, T3>,
    {
        <Self as FaddQEmitter<T0, T1, T2, T3>>::fadd_q(self, rd, rs1, rs2, rm);
    }
    /// Single-precision floating-point addition
    ///
    /// Do the single-precision floating-point addition of fs1 and fs2 and store the result in fd.
    /// rm is the dynamic Rounding Mode.
    ///
    /// # Forms
    /// Assembly: `fadd.s fd, fs1, fs2, rm`
    /// Rust: `fadd_s(rd, rs1, rs2, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fadd_s<T0, T1, T2, T3>(&mut self, rd: T0, rs1: T1, rs2: T2, rm: T3)
    where
        Self: FaddSEmitter<T0, T1, T2, T3>,
    {
        <Self as FaddSEmitter<T0, T1, T2, T3>>::fadd_s(self, rd, rs1, rs2, rm);
    }
    /// RISC-V `fclass.d` instruction.
    ///
    /// # Forms
    /// Assembly: `fclass.d xd, xs1`
    /// Rust: `fclass_d(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn fclass_d<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: FclassDEmitter<T0, T1>,
    {
        <Self as FclassDEmitter<T0, T1>>::fclass_d(self, rd, rs1);
    }
    /// RISC-V `fclass.h` instruction.
    ///
    /// # Forms
    /// Assembly: `fclass.h xd, xs1`
    /// Rust: `fclass_h(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn fclass_h<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: FclassHEmitter<T0, T1>,
    {
        <Self as FclassHEmitter<T0, T1>>::fclass_h(self, rd, rs1);
    }
    /// RISC-V `fclass.q` instruction.
    ///
    /// # Forms
    /// Assembly: `fclass.q xd, qs1`
    /// Rust: `fclass_q(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn fclass_q<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: FclassQEmitter<T0, T1>,
    {
        <Self as FclassQEmitter<T0, T1>>::fclass_q(self, rd, rs1);
    }
    /// Single-precision floating-point classify.
    ///
    /// The `fclass.s` instruction examines the value in floating-point register
    /// _fs1_ and writes to integer register _rd_ a 10-bit mask that indicates
    /// the class of the floating-point number.
    /// The format of the mask is described in the table below.
    /// The corresponding bit in _rd_ will be set if the property is true and
    /// clear otherwise.
    /// All other bits in _rd_ are cleared.
    /// Note that exactly one bit in rd will be set.
    /// `fclass.s` does not set the floating-point exception flags.
    ///
    /// .Format of result of `fclass` instruction.
    /// \[%autowidth,float="center",align="center",cols="^,&lt;",options="header",\]
    /// |===
    /// |_rd_ bit |Meaning
    /// |0 |_rs1_ is latexmath:\[$-\infty$\].
    /// |1 |_rs1_ is a negative normal number.
    /// |2 |_rs1_ is a negative subnormal number.
    /// |3 |_rs1_ is latexmath:\[$-0$\].
    /// |4 |_rs1_ is latexmath:\[$+0$\].
    /// |5 |_rs1_ is a positive subnormal number.
    /// |6 |_rs1_ is a positive normal number.
    /// |7 |_rs1_ is latexmath:\[$+\infty$\].
    /// |8 |_rs1_ is a signaling NaN.
    /// |9 |_rs1_ is a quiet NaN.
    /// |===
    ///
    /// # Forms
    /// Assembly: `fclass.s xd, fs1`
    /// Rust: `fclass_s(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn fclass_s<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: FclassSEmitter<T0, T1>,
    {
        <Self as FclassSEmitter<T0, T1>>::fclass_s(self, rd, rs1);
    }
    /// RISC-V `fcvt.bf16.s` instruction.
    ///
    /// # Forms
    /// Assembly: `fcvt.bf16.s xd, xs1, rm`
    /// Rust: `fcvt_bf16_s(rd, rs1, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fcvt_bf16_s<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
    where
        Self: FcvtBf16SEmitter<T0, T1, T2>,
    {
        <Self as FcvtBf16SEmitter<T0, T1, T2>>::fcvt_bf16_s(self, rd, rs1, rm);
    }
    /// RISC-V `fcvt.d.h` instruction.
    ///
    /// # Forms
    /// Assembly: `fcvt.d.h xd, xs1, rm`
    /// Rust: `fcvt_d_h(rd, rs1, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fcvt_d_h<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
    where
        Self: FcvtDHEmitter<T0, T1, T2>,
    {
        <Self as FcvtDHEmitter<T0, T1, T2>>::fcvt_d_h(self, rd, rs1, rm);
    }
    /// RISC-V `fcvt.d.l` instruction.
    ///
    /// # Forms
    /// Assembly: `fcvt.d.l xd, xs1, rm`
    /// Rust: `fcvt_d_l(rd, rs1, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fcvt_d_l<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
    where
        Self: FcvtDLEmitter<T0, T1, T2>,
    {
        <Self as FcvtDLEmitter<T0, T1, T2>>::fcvt_d_l(self, rd, rs1, rm);
    }
    /// RISC-V `fcvt.d.lu` instruction.
    ///
    /// # Forms
    /// Assembly: `fcvt.d.lu xd, xs1, rm`
    /// Rust: `fcvt_d_lu(rd, rs1, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fcvt_d_lu<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
    where
        Self: FcvtDLuEmitter<T0, T1, T2>,
    {
        <Self as FcvtDLuEmitter<T0, T1, T2>>::fcvt_d_lu(self, rd, rs1, rm);
    }
    /// RISC-V `fcvt.d.q` instruction.
    ///
    /// # Forms
    /// Assembly: `fcvt.d.q xd, qs1, rm`
    /// Rust: `fcvt_d_q(rd, rs1, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fcvt_d_q<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
    where
        Self: FcvtDQEmitter<T0, T1, T2>,
    {
        <Self as FcvtDQEmitter<T0, T1, T2>>::fcvt_d_q(self, rd, rs1, rm);
    }
    /// RISC-V `fcvt.d.s` instruction.
    ///
    /// # Forms
    /// Assembly: `fcvt.d.s xd, xs1, rm`
    /// Rust: `fcvt_d_s(rd, rs1, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fcvt_d_s<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
    where
        Self: FcvtDSEmitter<T0, T1, T2>,
    {
        <Self as FcvtDSEmitter<T0, T1, T2>>::fcvt_d_s(self, rd, rs1, rm);
    }
    /// RISC-V `fcvt.d.w` instruction.
    ///
    /// # Forms
    /// Assembly: `fcvt.d.w xd, xs1, rm`
    /// Rust: `fcvt_d_w(rd, rs1, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fcvt_d_w<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
    where
        Self: FcvtDWEmitter<T0, T1, T2>,
    {
        <Self as FcvtDWEmitter<T0, T1, T2>>::fcvt_d_w(self, rd, rs1, rm);
    }
    /// RISC-V `fcvt.d.wu` instruction.
    ///
    /// # Forms
    /// Assembly: `fcvt.d.wu xd, xs1, rm`
    /// Rust: `fcvt_d_wu(rd, rs1, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fcvt_d_wu<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
    where
        Self: FcvtDWuEmitter<T0, T1, T2>,
    {
        <Self as FcvtDWuEmitter<T0, T1, T2>>::fcvt_d_wu(self, rd, rs1, rm);
    }
    /// RISC-V `fcvt.h.d` instruction.
    ///
    /// # Forms
    /// Assembly: `fcvt.h.d xd, xs1, rm`
    /// Rust: `fcvt_h_d(rd, rs1, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fcvt_h_d<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
    where
        Self: FcvtHDEmitter<T0, T1, T2>,
    {
        <Self as FcvtHDEmitter<T0, T1, T2>>::fcvt_h_d(self, rd, rs1, rm);
    }
    /// RISC-V `fcvt.h.l` instruction.
    ///
    /// # Forms
    /// Assembly: `fcvt.h.l xd, xs1, rm`
    /// Rust: `fcvt_h_l(rd, rs1, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fcvt_h_l<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
    where
        Self: FcvtHLEmitter<T0, T1, T2>,
    {
        <Self as FcvtHLEmitter<T0, T1, T2>>::fcvt_h_l(self, rd, rs1, rm);
    }
    /// RISC-V `fcvt.h.lu` instruction.
    ///
    /// # Forms
    /// Assembly: `fcvt.h.lu xd, xs1, rm`
    /// Rust: `fcvt_h_lu(rd, rs1, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fcvt_h_lu<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
    where
        Self: FcvtHLuEmitter<T0, T1, T2>,
    {
        <Self as FcvtHLuEmitter<T0, T1, T2>>::fcvt_h_lu(self, rd, rs1, rm);
    }
    /// RISC-V `fcvt.h.q` instruction.
    ///
    /// # Forms
    /// Assembly: `fcvt.h.q xd, qs1, rm`
    /// Rust: `fcvt_h_q(rd, rs1, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fcvt_h_q<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
    where
        Self: FcvtHQEmitter<T0, T1, T2>,
    {
        <Self as FcvtHQEmitter<T0, T1, T2>>::fcvt_h_q(self, rd, rs1, rm);
    }
    /// Convert half-precision float to a single-precision float
    ///
    /// Converts a half-precision number in floating-point register _fs1_ into a single-precision floating-point number in
    /// floating-point register _fd_.
    ///
    /// `fcvt.h.s` rounds according to the _rm_ field.
    ///
    /// All floating-point conversion instructions set the Inexact exception flag if the rounded
    /// result differs from the operand value and the Invalid exception flag is not set.
    ///
    /// # Forms
    /// Assembly: `fcvt.h.s fd, xs1`
    /// Rust: `fcvt_h_s(rd, rs1, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fcvt_h_s<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
    where
        Self: FcvtHSEmitter<T0, T1, T2>,
    {
        <Self as FcvtHSEmitter<T0, T1, T2>>::fcvt_h_s(self, rd, rs1, rm);
    }
    /// RISC-V `fcvt.h.w` instruction.
    ///
    /// # Forms
    /// Assembly: `fcvt.h.w xd, xs1, rm`
    /// Rust: `fcvt_h_w(rd, rs1, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fcvt_h_w<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
    where
        Self: FcvtHWEmitter<T0, T1, T2>,
    {
        <Self as FcvtHWEmitter<T0, T1, T2>>::fcvt_h_w(self, rd, rs1, rm);
    }
    /// RISC-V `fcvt.h.wu` instruction.
    ///
    /// # Forms
    /// Assembly: `fcvt.h.wu xd, xs1, rm`
    /// Rust: `fcvt_h_wu(rd, rs1, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fcvt_h_wu<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
    where
        Self: FcvtHWuEmitter<T0, T1, T2>,
    {
        <Self as FcvtHWuEmitter<T0, T1, T2>>::fcvt_h_wu(self, rd, rs1, rm);
    }
    /// RISC-V `fcvt.l.d` instruction.
    ///
    /// # Forms
    /// Assembly: `fcvt.l.d xd, xs1, rm`
    /// Rust: `fcvt_l_d(rd, rs1, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fcvt_l_d<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
    where
        Self: FcvtLDEmitter<T0, T1, T2>,
    {
        <Self as FcvtLDEmitter<T0, T1, T2>>::fcvt_l_d(self, rd, rs1, rm);
    }
    /// RISC-V `fcvt.l.h` instruction.
    ///
    /// # Forms
    /// Assembly: `fcvt.l.h xd, xs1, rm`
    /// Rust: `fcvt_l_h(rd, rs1, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fcvt_l_h<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
    where
        Self: FcvtLHEmitter<T0, T1, T2>,
    {
        <Self as FcvtLHEmitter<T0, T1, T2>>::fcvt_l_h(self, rd, rs1, rm);
    }
    /// RISC-V `fcvt.l.q` instruction.
    ///
    /// # Forms
    /// Assembly: `fcvt.l.q xd, qs1, rm`
    /// Rust: `fcvt_l_q(rd, rs1, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fcvt_l_q<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
    where
        Self: FcvtLQEmitter<T0, T1, T2>,
    {
        <Self as FcvtLQEmitter<T0, T1, T2>>::fcvt_l_q(self, rd, rs1, rm);
    }
    /// RISC-V `fcvt.l.s` instruction.
    ///
    /// # Forms
    /// Assembly: `fcvt.l.s xd, fs1, rm`
    /// Rust: `fcvt_l_s(rd, rs1, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fcvt_l_s<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
    where
        Self: FcvtLSEmitter<T0, T1, T2>,
    {
        <Self as FcvtLSEmitter<T0, T1, T2>>::fcvt_l_s(self, rd, rs1, rm);
    }
    /// RISC-V `fcvt.lu.d` instruction.
    ///
    /// # Forms
    /// Assembly: `fcvt.lu.d xd, xs1, rm`
    /// Rust: `fcvt_lu_d(rd, rs1, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fcvt_lu_d<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
    where
        Self: FcvtLuDEmitter<T0, T1, T2>,
    {
        <Self as FcvtLuDEmitter<T0, T1, T2>>::fcvt_lu_d(self, rd, rs1, rm);
    }
    /// RISC-V `fcvt.lu.h` instruction.
    ///
    /// # Forms
    /// Assembly: `fcvt.lu.h xd, xs1, rm`
    /// Rust: `fcvt_lu_h(rd, rs1, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fcvt_lu_h<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
    where
        Self: FcvtLuHEmitter<T0, T1, T2>,
    {
        <Self as FcvtLuHEmitter<T0, T1, T2>>::fcvt_lu_h(self, rd, rs1, rm);
    }
    /// RISC-V `fcvt.lu.q` instruction.
    ///
    /// # Forms
    /// Assembly: `fcvt.lu.q qd, hs1, rm`
    /// Rust: `fcvt_lu_q(rd, rs1, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fcvt_lu_q<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
    where
        Self: FcvtLuQEmitter<T0, T1, T2>,
    {
        <Self as FcvtLuQEmitter<T0, T1, T2>>::fcvt_lu_q(self, rd, rs1, rm);
    }
    /// RISC-V `fcvt.lu.s` instruction.
    ///
    /// # Forms
    /// Assembly: `fcvt.lu.s xd, fs1, rm`
    /// Rust: `fcvt_lu_s(rd, rs1, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fcvt_lu_s<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
    where
        Self: FcvtLuSEmitter<T0, T1, T2>,
    {
        <Self as FcvtLuSEmitter<T0, T1, T2>>::fcvt_lu_s(self, rd, rs1, rm);
    }
    /// RISC-V `fcvt.q.d` instruction.
    ///
    /// # Forms
    /// Assembly: `fcvt.q.d dd, fs1, rm`
    /// Rust: `fcvt_q_d(rd, rs1, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fcvt_q_d<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
    where
        Self: FcvtQDEmitter<T0, T1, T2>,
    {
        <Self as FcvtQDEmitter<T0, T1, T2>>::fcvt_q_d(self, rd, rs1, rm);
    }
    /// RISC-V `fcvt.q.h` instruction.
    ///
    /// # Forms
    /// Assembly: `fcvt.q.h hd, qs1, rm`
    /// Rust: `fcvt_q_h(rd, rs1, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fcvt_q_h<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
    where
        Self: FcvtQHEmitter<T0, T1, T2>,
    {
        <Self as FcvtQHEmitter<T0, T1, T2>>::fcvt_q_h(self, rd, rs1, rm);
    }
    /// RISC-V `fcvt.q.l` instruction.
    ///
    /// # Forms
    /// Assembly: `fcvt.q.l qd, xs1, rm`
    /// Rust: `fcvt_q_l(rd, rs1, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fcvt_q_l<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
    where
        Self: FcvtQLEmitter<T0, T1, T2>,
    {
        <Self as FcvtQLEmitter<T0, T1, T2>>::fcvt_q_l(self, rd, rs1, rm);
    }
    /// RISC-V `fcvt.q.lu` instruction.
    ///
    /// # Forms
    /// Assembly: `fcvt.q.lu qd, xs1, rm`
    /// Rust: `fcvt_q_lu(rd, rs1, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fcvt_q_lu<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
    where
        Self: FcvtQLuEmitter<T0, T1, T2>,
    {
        <Self as FcvtQLuEmitter<T0, T1, T2>>::fcvt_q_lu(self, rd, rs1, rm);
    }
    /// RISC-V `fcvt.q.s` instruction.
    ///
    /// # Forms
    /// Assembly: `fcvt.q.s qd, fs1, rm`
    /// Rust: `fcvt_q_s(rd, rs1, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fcvt_q_s<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
    where
        Self: FcvtQSEmitter<T0, T1, T2>,
    {
        <Self as FcvtQSEmitter<T0, T1, T2>>::fcvt_q_s(self, rd, rs1, rm);
    }
    /// RISC-V `fcvt.q.w` instruction.
    ///
    /// # Forms
    /// Assembly: `fcvt.q.w fd, xs1, rm`
    /// Rust: `fcvt_q_w(rd, rs1, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fcvt_q_w<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
    where
        Self: FcvtQWEmitter<T0, T1, T2>,
    {
        <Self as FcvtQWEmitter<T0, T1, T2>>::fcvt_q_w(self, rd, rs1, rm);
    }
    /// RISC-V `fcvt.q.wu` instruction.
    ///
    /// # Forms
    /// Assembly: `fcvt.q.wu qd, xs1, rm`
    /// Rust: `fcvt_q_wu(rd, rs1, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fcvt_q_wu<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
    where
        Self: FcvtQWuEmitter<T0, T1, T2>,
    {
        <Self as FcvtQWuEmitter<T0, T1, T2>>::fcvt_q_wu(self, rd, rs1, rm);
    }
    /// RISC-V `fcvt.s.bf16` instruction.
    ///
    /// # Forms
    /// Assembly: `fcvt.s.bf16 xd, xs1, rm`
    /// Rust: `fcvt_s_bf16(rd, rs1, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fcvt_s_bf16<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
    where
        Self: FcvtSBf16Emitter<T0, T1, T2>,
    {
        <Self as FcvtSBf16Emitter<T0, T1, T2>>::fcvt_s_bf16(self, rd, rs1, rm);
    }
    /// RISC-V `fcvt.s.d` instruction.
    ///
    /// # Forms
    /// Assembly: `fcvt.s.d xd, xs1, rm`
    /// Rust: `fcvt_s_d(rd, rs1, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fcvt_s_d<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
    where
        Self: FcvtSDEmitter<T0, T1, T2>,
    {
        <Self as FcvtSDEmitter<T0, T1, T2>>::fcvt_s_d(self, rd, rs1, rm);
    }
    /// Convert single-precision float to a half-precision float
    ///
    /// Converts a single-precision number in floating-point register _fs1_ into a half-precision floating-point number in
    /// floating-point register _fd_.
    ///
    /// `fcvt.s.h` will never round, and so the 'rm' field is effectively ignored.
    ///
    /// # Forms
    /// Assembly: `fcvt.s.h fd, xs1`
    /// Rust: `fcvt_s_h(rd, rs1, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fcvt_s_h<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
    where
        Self: FcvtSHEmitter<T0, T1, T2>,
    {
        <Self as FcvtSHEmitter<T0, T1, T2>>::fcvt_s_h(self, rd, rs1, rm);
    }
    /// RISC-V `fcvt.s.l` instruction.
    ///
    /// # Forms
    /// Assembly: `fcvt.s.l fd, xs1, rm`
    /// Rust: `fcvt_s_l(rd, rs1, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fcvt_s_l<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
    where
        Self: FcvtSLEmitter<T0, T1, T2>,
    {
        <Self as FcvtSLEmitter<T0, T1, T2>>::fcvt_s_l(self, rd, rs1, rm);
    }
    /// RISC-V `fcvt.s.lu` instruction.
    ///
    /// # Forms
    /// Assembly: `fcvt.s.lu fd, xs1, rm`
    /// Rust: `fcvt_s_lu(rd, rs1, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fcvt_s_lu<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
    where
        Self: FcvtSLuEmitter<T0, T1, T2>,
    {
        <Self as FcvtSLuEmitter<T0, T1, T2>>::fcvt_s_lu(self, rd, rs1, rm);
    }
    /// RISC-V `fcvt.s.q` instruction.
    ///
    /// # Forms
    /// Assembly: `fcvt.s.q fd, qs1, rm`
    /// Rust: `fcvt_s_q(rd, rs1, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fcvt_s_q<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
    where
        Self: FcvtSQEmitter<T0, T1, T2>,
    {
        <Self as FcvtSQEmitter<T0, T1, T2>>::fcvt_s_q(self, rd, rs1, rm);
    }
    /// Convert signed 32-bit integer to single-precision float
    ///
    /// Converts a 32-bit signed integer in integer register _rs1_ into a floating-point number in
    /// floating-point register _fd_.
    ///
    /// All floating-point to integer and integer to floating-point conversion instructions round
    /// according to the _rm_ field.
    /// A floating-point register can be initialized to floating-point positive zero using
    /// `fcvt.s.w rd, x0`, which will never set any exception flags.
    ///
    /// All floating-point conversion instructions set the Inexact exception flag if the rounded
    /// result differs from the operand value and the Invalid exception flag is not set.
    ///
    /// # Forms
    /// Assembly: `fcvt.s.w fd, xs1`
    /// Rust: `fcvt_s_w(rd, rs1, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fcvt_s_w<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
    where
        Self: FcvtSWEmitter<T0, T1, T2>,
    {
        <Self as FcvtSWEmitter<T0, T1, T2>>::fcvt_s_w(self, rd, rs1, rm);
    }
    /// RISC-V `fcvt.s.wu` instruction.
    ///
    /// # Forms
    /// Assembly: `fcvt.s.wu fd, xs1, rm`
    /// Rust: `fcvt_s_wu(rd, rs1, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fcvt_s_wu<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
    where
        Self: FcvtSWuEmitter<T0, T1, T2>,
    {
        <Self as FcvtSWuEmitter<T0, T1, T2>>::fcvt_s_wu(self, rd, rs1, rm);
    }
    /// RISC-V `fcvt.w.d` instruction.
    ///
    /// # Forms
    /// Assembly: `fcvt.w.d xd, xs1, rm`
    /// Rust: `fcvt_w_d(rd, rs1, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fcvt_w_d<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
    where
        Self: FcvtWDEmitter<T0, T1, T2>,
    {
        <Self as FcvtWDEmitter<T0, T1, T2>>::fcvt_w_d(self, rd, rs1, rm);
    }
    /// RISC-V `fcvt.w.h` instruction.
    ///
    /// # Forms
    /// Assembly: `fcvt.w.h xd, xs1, rm`
    /// Rust: `fcvt_w_h(rd, rs1, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fcvt_w_h<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
    where
        Self: FcvtWHEmitter<T0, T1, T2>,
    {
        <Self as FcvtWHEmitter<T0, T1, T2>>::fcvt_w_h(self, rd, rs1, rm);
    }
    /// RISC-V `fcvt.w.q` instruction.
    ///
    /// # Forms
    /// Assembly: `fcvt.w.q xd, qs1, rm`
    /// Rust: `fcvt_w_q(rd, rs1, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fcvt_w_q<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
    where
        Self: FcvtWQEmitter<T0, T1, T2>,
    {
        <Self as FcvtWQEmitter<T0, T1, T2>>::fcvt_w_q(self, rd, rs1, rm);
    }
    /// Convert single-precision float to integer word to signed 32-bit integer.
    ///
    /// Converts a floating-point number in floating-point register _fs1_ to a signed 32-bit integer indicates
    /// integer register _rd_.
    ///
    /// For XLEN &gt;32, `fcvt.w.s` sign-extends the 32-bit result to the destination register width.
    ///
    /// If the rounded result is not representable as a 32-bit signed integer, it is clipped to the
    /// nearest value and the invalid flag is set.
    ///
    /// The range of valid inputs and behavior for invalid inputs are:
    ///
    /// \[separator="!"\]
    /// !===
    /// ! ! Value
    ///
    /// h! Minimum valid input (after rounding) ! `-2^31`
    /// h! Maximum valid input (after rounding) ! `2^31 - 1`
    /// h! Output for out-of-range negative input ! `-2^31`
    /// h! Output for `-&infin;` ! `-2^31`
    /// h! Output for out-of-range positive input ! `2^31 - 1`
    /// h! Output for `+&infin;` for `NaN` ! `2^31 - 1`
    /// !===
    ///
    /// All floating-point to integer and integer to floating-point conversion instructions round
    /// according to the _rm_ field.
    /// A floating-point register can be initialized to floating-point positive zero using
    /// `fcvt.s.w rd, x0`, which will never set any exception flags.
    ///
    /// All floating-point conversion instructions set the Inexact exception flag if the rounded
    /// result differs from the operand value and the Invalid exception flag is not set.
    ///
    /// # Forms
    /// Assembly: `fcvt.w.s xd, fs1`
    /// Rust: `fcvt_w_s(rd, rs1, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fcvt_w_s<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
    where
        Self: FcvtWSEmitter<T0, T1, T2>,
    {
        <Self as FcvtWSEmitter<T0, T1, T2>>::fcvt_w_s(self, rd, rs1, rm);
    }
    /// RISC-V `fcvt.wu.d` instruction.
    ///
    /// # Forms
    /// Assembly: `fcvt.wu.d xd, xs1, rm`
    /// Rust: `fcvt_wu_d(rd, rs1, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fcvt_wu_d<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
    where
        Self: FcvtWuDEmitter<T0, T1, T2>,
    {
        <Self as FcvtWuDEmitter<T0, T1, T2>>::fcvt_wu_d(self, rd, rs1, rm);
    }
    /// RISC-V `fcvt.wu.h` instruction.
    ///
    /// # Forms
    /// Assembly: `fcvt.wu.h xd, xs1, rm`
    /// Rust: `fcvt_wu_h(rd, rs1, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fcvt_wu_h<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
    where
        Self: FcvtWuHEmitter<T0, T1, T2>,
    {
        <Self as FcvtWuHEmitter<T0, T1, T2>>::fcvt_wu_h(self, rd, rs1, rm);
    }
    /// RISC-V `fcvt.wu.q` instruction.
    ///
    /// # Forms
    /// Assembly: `fcvt.wu.q xd, xs1, rm`
    /// Rust: `fcvt_wu_q(rd, rs1, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fcvt_wu_q<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
    where
        Self: FcvtWuQEmitter<T0, T1, T2>,
    {
        <Self as FcvtWuQEmitter<T0, T1, T2>>::fcvt_wu_q(self, rd, rs1, rm);
    }
    /// RISC-V `fcvt.wu.s` instruction.
    ///
    /// # Forms
    /// Assembly: `fcvt.wu.s xd, fs1, rm`
    /// Rust: `fcvt_wu_s(rd, rs1, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fcvt_wu_s<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
    where
        Self: FcvtWuSEmitter<T0, T1, T2>,
    {
        <Self as FcvtWuSEmitter<T0, T1, T2>>::fcvt_wu_s(self, rd, rs1, rm);
    }
    /// RISC-V `fcvtmod.w.d` instruction.
    ///
    /// # Forms
    /// Assembly: `fcvtmod.w.d xd, xs1`
    /// Rust: `fcvtmod_w_d(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn fcvtmod_w_d<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: FcvtmodWDEmitter<T0, T1>,
    {
        <Self as FcvtmodWDEmitter<T0, T1>>::fcvtmod_w_d(self, rd, rs1);
    }
    /// RISC-V `fdiv.d` instruction.
    ///
    /// # Forms
    /// Assembly: `fdiv.d xd, xs1, xs2, rm`
    /// Rust: `fdiv_d(rd, rs1, rs2, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fdiv_d<T0, T1, T2, T3>(&mut self, rd: T0, rs1: T1, rs2: T2, rm: T3)
    where
        Self: FdivDEmitter<T0, T1, T2, T3>,
    {
        <Self as FdivDEmitter<T0, T1, T2, T3>>::fdiv_d(self, rd, rs1, rs2, rm);
    }
    /// RISC-V `fdiv.h` instruction.
    ///
    /// # Forms
    /// Assembly: `fdiv.h xd, xs1, xs2, rm`
    /// Rust: `fdiv_h(rd, rs1, rs2, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fdiv_h<T0, T1, T2, T3>(&mut self, rd: T0, rs1: T1, rs2: T2, rm: T3)
    where
        Self: FdivHEmitter<T0, T1, T2, T3>,
    {
        <Self as FdivHEmitter<T0, T1, T2, T3>>::fdiv_h(self, rd, rs1, rs2, rm);
    }
    /// RISC-V `fdiv.q` instruction.
    ///
    /// # Forms
    /// Assembly: `fdiv.q qd, qs1, qs2, rm`
    /// Rust: `fdiv_q(rd, rs1, rs2, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fdiv_q<T0, T1, T2, T3>(&mut self, rd: T0, rs1: T1, rs2: T2, rm: T3)
    where
        Self: FdivQEmitter<T0, T1, T2, T3>,
    {
        <Self as FdivQEmitter<T0, T1, T2, T3>>::fdiv_q(self, rd, rs1, rs2, rm);
    }
    /// RISC-V `fdiv.s` instruction.
    ///
    /// # Forms
    /// Assembly: `fdiv.s fd, fs1, fs2, rm`
    /// Rust: `fdiv_s(rd, rs1, rs2, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fdiv_s<T0, T1, T2, T3>(&mut self, rd: T0, rs1: T1, rs2: T2, rm: T3)
    where
        Self: FdivSEmitter<T0, T1, T2, T3>,
    {
        <Self as FdivSEmitter<T0, T1, T2, T3>>::fdiv_s(self, rd, rs1, rs2, rm);
    }
    /// Memory ordering fence
    ///
    /// Orders memory operations.
    ///
    /// The `fence` instruction is used to order device I/O and memory accesses as
    /// viewed by other RISC-V harts and external devices or coprocessors. Any
    /// combination of device input (I), device output (O), memory reads \(R),
    /// and memory writes (W) may be ordered with respect to any combination of
    /// the same. Informally, no other RISC-V hart or external device can
    /// observe any operation in the _successor_ set following a `fence` before
    /// any operation in the _predecessor_ set preceding the `fence`.
    ///
    /// The predecessor and successor fields have the same format to specify operation types:
    ///
    /// \[%autowidth\]
    /// |===
    /// 4+| `pred` 4+| `succ`
    ///
    /// | 27 | 26 |25 | 24 | 23 | 22 | 21| 20
    /// | PI | PO |PR | PW | SI | SO |SR | SW
    /// |===
    ///
    /// \[%autowidth,align="center",cols="^1,^1,&lt;3",options="header"\]
    /// .Fence mode encoding
    /// |===
    /// |_fm_ field |Mnemonic |Meaning
    /// |0000 |_none_ |Normal Fence
    /// |1000 |TSO |With `FENCE RW,RW`: exclude write-to-read ordering; otherwise: _Reserved for future use._
    /// 2+|_other_ |_Reserved for future use._
    /// |===
    ///
    /// When the mode field _fm_ is `0001` and both the predecessor and successor sets are 'RW',
    /// then the instruction acts as a special-case `fence.tso`. `fence.tso` orders all load operations
    /// in its predecessor set before all memory operations in its successor set, and all store operations
    /// in its predecessor set before all store operations in its successor set. This leaves non-AMO store
    /// operations in the 'fence.tso's predecessor set unordered with non-AMO loads in its successor set.
    ///
    /// When mode field _fm_ is not `0001`, or when mode field _fm_ is `0001` but the _pred_ and
    /// _succ_ fields are not both 'RW' (0x3), then the fence acts as a baseline fence (_e.g._, _fm_ is
    /// effectively `0000`). This is unaffected by the FIOM bits, described below (implicit promotion does
    /// not change how `fence.tso` is decoded).
    ///
    /// The `rs1` and `rd` fields are unused and ignored.
    ///
    /// In modes other than M-mode, `fence` is further affected by `menvcfg.FIOM`,
    /// `senvcfg.FIOM`&lt;% if ext?(:H) %&gt;, and/or `henvcfg.FIOM`&lt;% end %&gt;
    /// as follows:
    ///
    /// .Effective PR/PW/SR/SW in (H)S-mode
    /// \[%autowidth,cols=",,,",options="header",separator="!"\]
    /// !===
    /// ! \[.rotate\]#`menvcfg.FIOM`# ! `pred.PI` +
    /// `pred.PO` +
    /// `succ.SI` +
    /// `succ.SO`
    /// ! -&gt; +
    /// -&gt; +
    /// -&gt; +
    /// -&gt;
    /// ! effective `PR` +
    /// effective `PW` +
    /// effective `SR` +
    /// effective `SW`
    ///
    /// ! 0 ! - ! ! from encoding
    /// ! 1 ! 0 ! ! from encoding
    /// ! 1 ! 1 ! ! 1
    /// !===
    ///
    /// .Effective PR/PW/SR/SW in U-mode
    /// \[%autowidth,options="header",separator="!",cols=",,,,"\]
    /// !===
    /// ! \[.rotate\]#`menvcfg.FIOM`# ! \[.rotate\]#`senvcfg.FIOM`# !  `pred.PI` +
    /// `pred.PO` +
    /// `succ.SI` +
    /// `succ.SO`
    /// ! -&gt; +
    /// -&gt; +
    /// -&gt; +
    /// -&gt;
    /// ! effective `PR` +
    /// effective `PW` +
    /// effective `SR` +
    /// effective `SW`
    ///
    /// ! 0 ! 0 ! - ! ! from encoding
    /// ! 0 ! 1 ! 0 ! ! from encoding
    /// ! 0 ! 1 ! 1 ! ! 1
    /// ! 1 ! - ! 0 ! ! from encoding
    /// ! 1 ! - ! 1 ! ! 1
    /// !===
    ///
    /// &lt;%- if ext?(:H) -%&gt;
    /// .Effective PR/PW/SR/SW in VS-mode and VU-mode
    /// \[%autowidth,options="header",separator="!",cols=",,,,"\]
    /// !===
    /// ! \[.rotate\]#`menvcfg.FIOM`# ! \[.rotate\]#`henvcfg.FIOM`# !  `pred.PI` +
    /// `pred.PO` +
    /// `succ.SI` +
    /// `succ.SO`
    /// ! -&gt; +
    /// -&gt; +
    /// -&gt; +
    /// -&gt;
    /// ! effective `PR` +
    /// effective `PW` +
    /// effective `SR` +
    /// effective `SW`
    ///
    /// ! 0 ! 0 ! - ! ! from encoding
    /// ! 0 ! 1 ! 0 ! ! from encoding
    /// ! 0 ! 1 ! 1 ! ! 1
    /// ! 1 ! - ! 0 ! ! from encoding
    /// ! 1 ! - ! 1 ! ! 1
    /// !===
    /// &lt;%- end -%&gt;
    ///
    /// # Forms
    /// Assembly: `fence "TODO"`
    /// Rust: `fence(fm, pred, succ, rs1, rd)`
    ///
    /// # Arguments
    /// - `fm` — Immediate encoding value.
    /// - `pred` — Immediate encoding value.
    /// - `succ` — Immediate encoding value.
    /// - `rs1` — Source register.
    /// - `rd` — Destination/source register.
    pub fn fence<T0, T1, T2, T3, T4>(&mut self, fm: T0, pred: T1, succ: T2, rs1: T3, rd: T4)
    where
        Self: FenceEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as FenceEmitter<T0, T1, T2, T3, T4>>::fence(self, fm, pred, succ, rs1, rd);
    }
    /// Instruction fence
    ///
    /// The FENCE.I instruction is used to synchronize the instruction and data
    /// streams. RISC-V does not guarantee that stores to instruction memory
    /// will be made visible to instruction fetches on a RISC-V hart until that
    /// hart executes a FENCE.I instruction. A FENCE.I instruction ensures that
    /// a subsequent instruction fetch on a RISC-V hart will see any previous
    /// data stores already visible to the same RISC-V hart. FENCE.I does _not_
    /// ensure that other RISC-V harts' instruction fetches will observe the
    /// local hart's stores in a multiprocessor system. To make a store to
    /// instruction memory visible to all RISC-V harts, the writing hart also
    /// has to execute a data FENCE before requesting that all remote RISC-V
    /// harts execute a FENCE.I.
    ///
    /// The unused fields in the FENCE.I instruction, _imm\[11:0\]_, _rs1_, and
    /// _rd_, are reserved for finer-grain fences in future extensions. For
    /// forward compatibility, base implementations shall ignore these fields,
    /// and standard software shall zero these fields.
    /// (((FENCE.I, finer-grained)))
    /// (((FENCE.I, forward compatibility)))
    ///
    /// \[NOTE\]
    /// ====
    /// Because FENCE.I only orders stores with a hart's own instruction
    /// fetches, application code should only rely upon FENCE.I if the
    /// application thread will not be migrated to a different hart. The EEI can
    /// provide mechanisms for efficient multiprocessor instruction-stream
    /// synchronization.
    /// ====
    ///
    /// # Forms
    /// Assembly: `fence.i ""`
    /// Rust: `fence_i()`
    ///
    /// # Arguments
    pub fn fence_i(&mut self)
    where
        Self: FenceIEmitter,
    {
        <Self as FenceIEmitter>::fence_i(self);
    }
    /// RISC-V `fence.tso` instruction.
    ///
    /// # Forms
    /// Assembly: `fence.tso`
    /// Rust: `fence_tso()`
    ///
    /// # Arguments
    pub fn fence_tso(&mut self)
    where
        Self: FenceTsoEmitter,
    {
        <Self as FenceTsoEmitter>::fence_tso(self);
    }
    /// RISC-V `feq.d` instruction.
    ///
    /// # Forms
    /// Assembly: `feq.d xd, xs1, xs2`
    /// Rust: `feq_d(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn feq_d<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: FeqDEmitter<T0, T1, T2>,
    {
        <Self as FeqDEmitter<T0, T1, T2>>::feq_d(self, rd, rs1, rs2);
    }
    /// RISC-V `feq.h` instruction.
    ///
    /// # Forms
    /// Assembly: `feq.h xd, xs1, xs2`
    /// Rust: `feq_h(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn feq_h<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: FeqHEmitter<T0, T1, T2>,
    {
        <Self as FeqHEmitter<T0, T1, T2>>::feq_h(self, rd, rs1, rs2);
    }
    /// RISC-V `feq.q` instruction.
    ///
    /// # Forms
    /// Assembly: `feq.q xd, qs1, qs2`
    /// Rust: `feq_q(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn feq_q<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: FeqQEmitter<T0, T1, T2>,
    {
        <Self as FeqQEmitter<T0, T1, T2>>::feq_q(self, rd, rs1, rs2);
    }
    /// Single-precision floating-point equal
    ///
    /// Writes 1 to _rd_ if _fs1_ and _fs2_ are equal, and 0 otherwise.
    ///
    /// If either operand is NaN, the result is 0 (not equal). If either operand is a signaling NaN, the invalid flag is set.
    ///
    /// Positive zero is considered equal to negative zero.
    ///
    /// # Forms
    /// Assembly: `feq.s xd, fs1, fs2`
    /// Rust: `feq_s(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn feq_s<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: FeqSEmitter<T0, T1, T2>,
    {
        <Self as FeqSEmitter<T0, T1, T2>>::feq_s(self, rd, rs1, rs2);
    }
    /// RISC-V `fld` instruction.
    ///
    /// # Forms
    /// Assembly: `fld xd, xs1, imm`
    /// Rust: `fld(rd, rs1, imm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Memory base register.
    /// - `imm` — Immediate encoding value.
    pub fn fld<T0, T1, T2>(&mut self, rd: T0, rs1: T1, imm: T2)
    where
        Self: FldEmitter<T0, T1, T2>,
    {
        <Self as FldEmitter<T0, T1, T2>>::fld(self, rd, rs1, imm);
    }
    /// RISC-V `fle.d` instruction.
    ///
    /// # Forms
    /// Assembly: `fle.d xd, xs1, xs2`
    /// Rust: `fle_d(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn fle_d<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: FleDEmitter<T0, T1, T2>,
    {
        <Self as FleDEmitter<T0, T1, T2>>::fle_d(self, rd, rs1, rs2);
    }
    /// RISC-V `fle.h` instruction.
    ///
    /// # Forms
    /// Assembly: `fle.h xd, xs1, xs2`
    /// Rust: `fle_h(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn fle_h<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: FleHEmitter<T0, T1, T2>,
    {
        <Self as FleHEmitter<T0, T1, T2>>::fle_h(self, rd, rs1, rs2);
    }
    /// RISC-V `fle.q` instruction.
    ///
    /// # Forms
    /// Assembly: `fle.q xd, qs1, qs2`
    /// Rust: `fle_q(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn fle_q<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: FleQEmitter<T0, T1, T2>,
    {
        <Self as FleQEmitter<T0, T1, T2>>::fle_q(self, rd, rs1, rs2);
    }
    /// Single-precision floating-point less than or equal
    ///
    /// Writes 1 to _rd_ if _fs1_ is less than or equal to _fs2_, and 0 otherwise.
    ///
    /// If either operand is NaN, the result is 0 (not equal).
    /// If either operand is a NaN (signaling or quiet), the invalid flag is set.
    ///
    /// Positive zero and negative zero are considered equal.
    ///
    /// # Forms
    /// Assembly: `fle.s xd, fs1, fs2`
    /// Rust: `fle_s(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn fle_s<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: FleSEmitter<T0, T1, T2>,
    {
        <Self as FleSEmitter<T0, T1, T2>>::fle_s(self, rd, rs1, rs2);
    }
    /// RISC-V `fleq.d` instruction.
    ///
    /// # Forms
    /// Assembly: `fleq.d xd, xs1, xs2`
    /// Rust: `fleq_d(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn fleq_d<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: FleqDEmitter<T0, T1, T2>,
    {
        <Self as FleqDEmitter<T0, T1, T2>>::fleq_d(self, rd, rs1, rs2);
    }
    /// RISC-V `fleq.h` instruction.
    ///
    /// # Forms
    /// Assembly: `fleq.h xd, xs1, xs2`
    /// Rust: `fleq_h(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn fleq_h<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: FleqHEmitter<T0, T1, T2>,
    {
        <Self as FleqHEmitter<T0, T1, T2>>::fleq_h(self, rd, rs1, rs2);
    }
    /// RISC-V `fleq.q` instruction.
    ///
    /// # Forms
    /// Assembly: `fleq.q xd, qs1, qs2`
    /// Rust: `fleq_q(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn fleq_q<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: FleqQEmitter<T0, T1, T2>,
    {
        <Self as FleqQEmitter<T0, T1, T2>>::fleq_q(self, rd, rs1, rs2);
    }
    /// RISC-V `fleq.s` instruction.
    ///
    /// # Forms
    /// Assembly: `fleq.s xd, fs1, fs2`
    /// Rust: `fleq_s(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn fleq_s<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: FleqSEmitter<T0, T1, T2>,
    {
        <Self as FleqSEmitter<T0, T1, T2>>::fleq_s(self, rd, rs1, rs2);
    }
    /// Half-precision floating-point load
    ///
    /// The `flh` instruction loads a single-precision floating-point value from memory at address _rs1_ + _imm_ into floating-point register _rd_.
    ///
    /// `flh` does not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved.
    ///
    /// `flh` is only guaranteed to execute atomically if the effective address is naturally aligned.
    ///
    /// # Forms
    /// Assembly: `flh fd, imm(xs1)`
    /// Rust: `flh(rd, rs1, imm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Memory base register.
    /// - `imm` — Immediate encoding value.
    pub fn flh<T0, T1, T2>(&mut self, rd: T0, rs1: T1, imm: T2)
    where
        Self: FlhEmitter<T0, T1, T2>,
    {
        <Self as FlhEmitter<T0, T1, T2>>::flh(self, rd, rs1, imm);
    }
    /// RISC-V `fli.d` instruction.
    ///
    /// # Forms
    /// Assembly: `fli.d xd, xs1`
    /// Rust: `fli_d(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn fli_d<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: FliDEmitter<T0, T1>,
    {
        <Self as FliDEmitter<T0, T1>>::fli_d(self, rd, rs1);
    }
    /// RISC-V `fli.h` instruction.
    ///
    /// # Forms
    /// Assembly: `fli.h xd, xs1`
    /// Rust: `fli_h(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn fli_h<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: FliHEmitter<T0, T1>,
    {
        <Self as FliHEmitter<T0, T1>>::fli_h(self, rd, rs1);
    }
    /// RISC-V `fli.q` instruction.
    ///
    /// # Forms
    /// Assembly: `fli.q fd, qs1`
    /// Rust: `fli_q(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn fli_q<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: FliQEmitter<T0, T1>,
    {
        <Self as FliQEmitter<T0, T1>>::fli_q(self, rd, rs1);
    }
    /// RISC-V `fli.s` instruction.
    ///
    /// # Forms
    /// Assembly: `fli.s fd, fs1`
    /// Rust: `fli_s(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn fli_s<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: FliSEmitter<T0, T1>,
    {
        <Self as FliSEmitter<T0, T1>>::fli_s(self, rd, rs1);
    }
    /// RISC-V `flq` instruction.
    ///
    /// # Forms
    /// Assembly: `flq qd, xs1, imm`
    /// Rust: `flq(rd, rs1, imm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Memory base register.
    /// - `imm` — Immediate encoding value.
    pub fn flq<T0, T1, T2>(&mut self, rd: T0, rs1: T1, imm: T2)
    where
        Self: FlqEmitter<T0, T1, T2>,
    {
        <Self as FlqEmitter<T0, T1, T2>>::flq(self, rd, rs1, imm);
    }
    /// RISC-V `flt.d` instruction.
    ///
    /// # Forms
    /// Assembly: `flt.d xd, xs1, xs2`
    /// Rust: `flt_d(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn flt_d<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: FltDEmitter<T0, T1, T2>,
    {
        <Self as FltDEmitter<T0, T1, T2>>::flt_d(self, rd, rs1, rs2);
    }
    /// RISC-V `flt.h` instruction.
    ///
    /// # Forms
    /// Assembly: `flt.h xd, xs1, xs2`
    /// Rust: `flt_h(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn flt_h<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: FltHEmitter<T0, T1, T2>,
    {
        <Self as FltHEmitter<T0, T1, T2>>::flt_h(self, rd, rs1, rs2);
    }
    /// RISC-V `flt.q` instruction.
    ///
    /// # Forms
    /// Assembly: `flt.q xd, qs1, qs2`
    /// Rust: `flt_q(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn flt_q<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: FltQEmitter<T0, T1, T2>,
    {
        <Self as FltQEmitter<T0, T1, T2>>::flt_q(self, rd, rs1, rs2);
    }
    /// Single-precision floating-point less than
    ///
    /// Writes 1 to _rd_ if _fs1_ is less than _fs2_, and 0 otherwise.
    ///
    /// If either operand is NaN, the result is 0 (not equal).
    /// If either operand is a NaN (signaling or quiet), the invalid flag is set.
    ///
    /// # Forms
    /// Assembly: `flt.s xd, fs1, fs2`
    /// Rust: `flt_s(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn flt_s<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: FltSEmitter<T0, T1, T2>,
    {
        <Self as FltSEmitter<T0, T1, T2>>::flt_s(self, rd, rs1, rs2);
    }
    /// RISC-V `fltq.d` instruction.
    ///
    /// # Forms
    /// Assembly: `fltq.d xd, xs1, xs2`
    /// Rust: `fltq_d(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn fltq_d<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: FltqDEmitter<T0, T1, T2>,
    {
        <Self as FltqDEmitter<T0, T1, T2>>::fltq_d(self, rd, rs1, rs2);
    }
    /// RISC-V `fltq.h` instruction.
    ///
    /// # Forms
    /// Assembly: `fltq.h xd, xs1, xs2`
    /// Rust: `fltq_h(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn fltq_h<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: FltqHEmitter<T0, T1, T2>,
    {
        <Self as FltqHEmitter<T0, T1, T2>>::fltq_h(self, rd, rs1, rs2);
    }
    /// RISC-V `fltq.q` instruction.
    ///
    /// # Forms
    /// Assembly: `fltq.q qd, qs1, qs2`
    /// Rust: `fltq_q(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn fltq_q<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: FltqQEmitter<T0, T1, T2>,
    {
        <Self as FltqQEmitter<T0, T1, T2>>::fltq_q(self, rd, rs1, rs2);
    }
    /// RISC-V `fltq.s` instruction.
    ///
    /// # Forms
    /// Assembly: `fltq.s xd, fs1, fs2`
    /// Rust: `fltq_s(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn fltq_s<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: FltqSEmitter<T0, T1, T2>,
    {
        <Self as FltqSEmitter<T0, T1, T2>>::fltq_s(self, rd, rs1, rs2);
    }
    /// Single-precision floating-point load
    ///
    /// The `flw` instruction loads a single-precision floating-point value from memory at address _rs1_ + _imm_ into floating-point register _fd_.
    ///
    /// `flw` does not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved.
    ///
    /// # Forms
    /// Assembly: `flw fd, xs1, imm`
    /// Rust: `flw(rd, rs1, imm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Memory base register.
    /// - `imm` — Immediate encoding value.
    pub fn flw<T0, T1, T2>(&mut self, rd: T0, rs1: T1, imm: T2)
    where
        Self: FlwEmitter<T0, T1, T2>,
    {
        <Self as FlwEmitter<T0, T1, T2>>::flw(self, rd, rs1, imm);
    }
    /// RISC-V `fmadd.d` instruction.
    ///
    /// # Forms
    /// Assembly: `fmadd.d xd, xs1, xs2, xs3, rm`
    /// Rust: `fmadd_d(rd, rs1, rs2, rs3, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    /// - `rs3` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fmadd_d<T0, T1, T2, T3, T4>(&mut self, rd: T0, rs1: T1, rs2: T2, rs3: T3, rm: T4)
    where
        Self: FmaddDEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as FmaddDEmitter<T0, T1, T2, T3, T4>>::fmadd_d(self, rd, rs1, rs2, rs3, rm);
    }
    /// RISC-V `fmadd.h` instruction.
    ///
    /// # Forms
    /// Assembly: `fmadd.h xd, xs1, xs2, xs3, rm`
    /// Rust: `fmadd_h(rd, rs1, rs2, rs3, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    /// - `rs3` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fmadd_h<T0, T1, T2, T3, T4>(&mut self, rd: T0, rs1: T1, rs2: T2, rs3: T3, rm: T4)
    where
        Self: FmaddHEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as FmaddHEmitter<T0, T1, T2, T3, T4>>::fmadd_h(self, rd, rs1, rs2, rs3, rm);
    }
    /// RISC-V `fmadd.q` instruction.
    ///
    /// # Forms
    /// Assembly: `fmadd.q qd, qs1, qs2, qs3, rm`
    /// Rust: `fmadd_q(rd, rs1, rs2, rs3, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    /// - `rs3` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fmadd_q<T0, T1, T2, T3, T4>(&mut self, rd: T0, rs1: T1, rs2: T2, rs3: T3, rm: T4)
    where
        Self: FmaddQEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as FmaddQEmitter<T0, T1, T2, T3, T4>>::fmadd_q(self, rd, rs1, rs2, rs3, rm);
    }
    /// RISC-V `fmadd.s` instruction.
    ///
    /// # Forms
    /// Assembly: `fmadd.s fd, fs1, fs2, fs3, rm`
    /// Rust: `fmadd_s(rd, rs1, rs2, rs3, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    /// - `rs3` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fmadd_s<T0, T1, T2, T3, T4>(&mut self, rd: T0, rs1: T1, rs2: T2, rs3: T3, rm: T4)
    where
        Self: FmaddSEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as FmaddSEmitter<T0, T1, T2, T3, T4>>::fmadd_s(self, rd, rs1, rs2, rs3, rm);
    }
    /// RISC-V `fmax.d` instruction.
    ///
    /// # Forms
    /// Assembly: `fmax.d xd, xs1, xs2`
    /// Rust: `fmax_d(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn fmax_d<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: FmaxDEmitter<T0, T1, T2>,
    {
        <Self as FmaxDEmitter<T0, T1, T2>>::fmax_d(self, rd, rs1, rs2);
    }
    /// RISC-V `fmax.h` instruction.
    ///
    /// # Forms
    /// Assembly: `fmax.h xd, xs1, xs2`
    /// Rust: `fmax_h(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn fmax_h<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: FmaxHEmitter<T0, T1, T2>,
    {
        <Self as FmaxHEmitter<T0, T1, T2>>::fmax_h(self, rd, rs1, rs2);
    }
    /// RISC-V `fmax.q` instruction.
    ///
    /// # Forms
    /// Assembly: `fmax.q qd, qs1, qs2`
    /// Rust: `fmax_q(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn fmax_q<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: FmaxQEmitter<T0, T1, T2>,
    {
        <Self as FmaxQEmitter<T0, T1, T2>>::fmax_q(self, rd, rs1, rs2);
    }
    /// RISC-V `fmax.s` instruction.
    ///
    /// # Forms
    /// Assembly: `fmax.s fd, fs1, fs2`
    /// Rust: `fmax_s(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn fmax_s<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: FmaxSEmitter<T0, T1, T2>,
    {
        <Self as FmaxSEmitter<T0, T1, T2>>::fmax_s(self, rd, rs1, rs2);
    }
    /// RISC-V `fmaxm.d` instruction.
    ///
    /// # Forms
    /// Assembly: `fmaxm.d xd, xs1, xs2`
    /// Rust: `fmaxm_d(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn fmaxm_d<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: FmaxmDEmitter<T0, T1, T2>,
    {
        <Self as FmaxmDEmitter<T0, T1, T2>>::fmaxm_d(self, rd, rs1, rs2);
    }
    /// RISC-V `fmaxm.h` instruction.
    ///
    /// # Forms
    /// Assembly: `fmaxm.h xd, xs1, xs2`
    /// Rust: `fmaxm_h(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn fmaxm_h<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: FmaxmHEmitter<T0, T1, T2>,
    {
        <Self as FmaxmHEmitter<T0, T1, T2>>::fmaxm_h(self, rd, rs1, rs2);
    }
    /// RISC-V `fmaxm.q` instruction.
    ///
    /// # Forms
    /// Assembly: `fmaxm.q qd, qs1, qs2`
    /// Rust: `fmaxm_q(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn fmaxm_q<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: FmaxmQEmitter<T0, T1, T2>,
    {
        <Self as FmaxmQEmitter<T0, T1, T2>>::fmaxm_q(self, rd, rs1, rs2);
    }
    /// RISC-V `fmaxm.s` instruction.
    ///
    /// # Forms
    /// Assembly: `fmaxm.s xd, xs1, xs2`
    /// Rust: `fmaxm_s(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn fmaxm_s<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: FmaxmSEmitter<T0, T1, T2>,
    {
        <Self as FmaxmSEmitter<T0, T1, T2>>::fmaxm_s(self, rd, rs1, rs2);
    }
    /// RISC-V `fmin.d` instruction.
    ///
    /// # Forms
    /// Assembly: `fmin.d xd, xs1, xs2`
    /// Rust: `fmin_d(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn fmin_d<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: FminDEmitter<T0, T1, T2>,
    {
        <Self as FminDEmitter<T0, T1, T2>>::fmin_d(self, rd, rs1, rs2);
    }
    /// RISC-V `fmin.h` instruction.
    ///
    /// # Forms
    /// Assembly: `fmin.h xd, xs1, xs2`
    /// Rust: `fmin_h(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn fmin_h<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: FminHEmitter<T0, T1, T2>,
    {
        <Self as FminHEmitter<T0, T1, T2>>::fmin_h(self, rd, rs1, rs2);
    }
    /// RISC-V `fmin.q` instruction.
    ///
    /// # Forms
    /// Assembly: `fmin.q xd, xs1, xs2`
    /// Rust: `fmin_q(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn fmin_q<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: FminQEmitter<T0, T1, T2>,
    {
        <Self as FminQEmitter<T0, T1, T2>>::fmin_q(self, rd, rs1, rs2);
    }
    /// RISC-V `fmin.s` instruction.
    ///
    /// # Forms
    /// Assembly: `fmin.s xd, xs1, xs2`
    /// Rust: `fmin_s(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn fmin_s<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: FminSEmitter<T0, T1, T2>,
    {
        <Self as FminSEmitter<T0, T1, T2>>::fmin_s(self, rd, rs1, rs2);
    }
    /// RISC-V `fminm.d` instruction.
    ///
    /// # Forms
    /// Assembly: `fminm.d xd, xs1, xs2`
    /// Rust: `fminm_d(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn fminm_d<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: FminmDEmitter<T0, T1, T2>,
    {
        <Self as FminmDEmitter<T0, T1, T2>>::fminm_d(self, rd, rs1, rs2);
    }
    /// RISC-V `fminm.h` instruction.
    ///
    /// # Forms
    /// Assembly: `fminm.h xd, xs1, xs2`
    /// Rust: `fminm_h(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn fminm_h<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: FminmHEmitter<T0, T1, T2>,
    {
        <Self as FminmHEmitter<T0, T1, T2>>::fminm_h(self, rd, rs1, rs2);
    }
    /// RISC-V `fminm.q` instruction.
    ///
    /// # Forms
    /// Assembly: `fminm.q qd, qs1, qs2`
    /// Rust: `fminm_q(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn fminm_q<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: FminmQEmitter<T0, T1, T2>,
    {
        <Self as FminmQEmitter<T0, T1, T2>>::fminm_q(self, rd, rs1, rs2);
    }
    /// RISC-V `fminm.s` instruction.
    ///
    /// # Forms
    /// Assembly: `fminm.s fd, fs1, fs2`
    /// Rust: `fminm_s(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn fminm_s<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: FminmSEmitter<T0, T1, T2>,
    {
        <Self as FminmSEmitter<T0, T1, T2>>::fminm_s(self, rd, rs1, rs2);
    }
    /// RISC-V `fmsub.d` instruction.
    ///
    /// # Forms
    /// Assembly: `fmsub.d xd, xs1, xs2, xs3, rm`
    /// Rust: `fmsub_d(rd, rs1, rs2, rs3, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    /// - `rs3` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fmsub_d<T0, T1, T2, T3, T4>(&mut self, rd: T0, rs1: T1, rs2: T2, rs3: T3, rm: T4)
    where
        Self: FmsubDEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as FmsubDEmitter<T0, T1, T2, T3, T4>>::fmsub_d(self, rd, rs1, rs2, rs3, rm);
    }
    /// RISC-V `fmsub.h` instruction.
    ///
    /// # Forms
    /// Assembly: `fmsub.h xd, xs1, xs2, xs3, rm`
    /// Rust: `fmsub_h(rd, rs1, rs2, rs3, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    /// - `rs3` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fmsub_h<T0, T1, T2, T3, T4>(&mut self, rd: T0, rs1: T1, rs2: T2, rs3: T3, rm: T4)
    where
        Self: FmsubHEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as FmsubHEmitter<T0, T1, T2, T3, T4>>::fmsub_h(self, rd, rs1, rs2, rs3, rm);
    }
    /// RISC-V `fmsub.q` instruction.
    ///
    /// # Forms
    /// Assembly: `fmsub.q qd, qs1, qs2, qs3, rm`
    /// Rust: `fmsub_q(rd, rs1, rs2, rs3, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    /// - `rs3` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fmsub_q<T0, T1, T2, T3, T4>(&mut self, rd: T0, rs1: T1, rs2: T2, rs3: T3, rm: T4)
    where
        Self: FmsubQEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as FmsubQEmitter<T0, T1, T2, T3, T4>>::fmsub_q(self, rd, rs1, rs2, rs3, rm);
    }
    /// RISC-V `fmsub.s` instruction.
    ///
    /// # Forms
    /// Assembly: `fmsub.s fd, fs1, fs2, fs3, rm`
    /// Rust: `fmsub_s(rd, rs1, rs2, rs3, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    /// - `rs3` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fmsub_s<T0, T1, T2, T3, T4>(&mut self, rd: T0, rs1: T1, rs2: T2, rs3: T3, rm: T4)
    where
        Self: FmsubSEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as FmsubSEmitter<T0, T1, T2, T3, T4>>::fmsub_s(self, rd, rs1, rs2, rs3, rm);
    }
    /// RISC-V `fmul.d` instruction.
    ///
    /// # Forms
    /// Assembly: `fmul.d xd, xs1, xs2, rm`
    /// Rust: `fmul_d(rd, rs1, rs2, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fmul_d<T0, T1, T2, T3>(&mut self, rd: T0, rs1: T1, rs2: T2, rm: T3)
    where
        Self: FmulDEmitter<T0, T1, T2, T3>,
    {
        <Self as FmulDEmitter<T0, T1, T2, T3>>::fmul_d(self, rd, rs1, rs2, rm);
    }
    /// RISC-V `fmul.h` instruction.
    ///
    /// # Forms
    /// Assembly: `fmul.h xd, xs1, xs2, rm`
    /// Rust: `fmul_h(rd, rs1, rs2, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fmul_h<T0, T1, T2, T3>(&mut self, rd: T0, rs1: T1, rs2: T2, rm: T3)
    where
        Self: FmulHEmitter<T0, T1, T2, T3>,
    {
        <Self as FmulHEmitter<T0, T1, T2, T3>>::fmul_h(self, rd, rs1, rs2, rm);
    }
    /// RISC-V `fmul.q` instruction.
    ///
    /// # Forms
    /// Assembly: `fmul.q qd, qs1, qs2, rm`
    /// Rust: `fmul_q(rd, rs1, rs2, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fmul_q<T0, T1, T2, T3>(&mut self, rd: T0, rs1: T1, rs2: T2, rm: T3)
    where
        Self: FmulQEmitter<T0, T1, T2, T3>,
    {
        <Self as FmulQEmitter<T0, T1, T2, T3>>::fmul_q(self, rd, rs1, rs2, rm);
    }
    /// RISC-V `fmul.s` instruction.
    ///
    /// # Forms
    /// Assembly: `fmul.s fd, fs1, fs2, rm`
    /// Rust: `fmul_s(rd, rs1, rs2, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fmul_s<T0, T1, T2, T3>(&mut self, rd: T0, rs1: T1, rs2: T2, rm: T3)
    where
        Self: FmulSEmitter<T0, T1, T2, T3>,
    {
        <Self as FmulSEmitter<T0, T1, T2, T3>>::fmul_s(self, rd, rs1, rs2, rm);
    }
    /// RISC-V `fmv.d` instruction.
    ///
    /// # Forms
    /// Assembly: `fmv.d rd rs1 rs2_eq_rs1`
    /// Rust: `fmv_d(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn fmv_d<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: FmvDEmitter<T0, T1, T2>,
    {
        <Self as FmvDEmitter<T0, T1, T2>>::fmv_d(self, rd, rs1, rs2);
    }
    /// RISC-V `fmv.d.x` instruction.
    ///
    /// # Forms
    /// Assembly: `fmv.d.x xd, xs1`
    /// Rust: `fmv_d_x(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn fmv_d_x<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: FmvDXEmitter<T0, T1>,
    {
        <Self as FmvDXEmitter<T0, T1>>::fmv_d_x(self, rd, rs1);
    }
    /// RISC-V `fmv.h` instruction.
    ///
    /// # Forms
    /// Assembly: `fmv.h rd rs1 rs2_eq_rs1`
    /// Rust: `fmv_h(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn fmv_h<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: FmvHEmitter<T0, T1, T2>,
    {
        <Self as FmvHEmitter<T0, T1, T2>>::fmv_h(self, rd, rs1, rs2);
    }
    /// Half-precision floating-point move from integer
    ///
    /// Moves the half-precision value encoded in IEEE 754-2008 standard encoding
    /// from the lower 16 bits of integer register `rs1` to the floating-point
    /// register `fd`. The bits are not modified in the transfer, and in particular,
    /// the payloads of non-canonical NaNs are preserved.
    ///
    /// # Forms
    /// Assembly: `fmv.h.x fd, xs1`
    /// Rust: `fmv_h_x(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn fmv_h_x<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: FmvHXEmitter<T0, T1>,
    {
        <Self as FmvHXEmitter<T0, T1>>::fmv_h_x(self, rd, rs1);
    }
    /// RISC-V `fmv.q` instruction.
    ///
    /// # Forms
    /// Assembly: `fmv.q rd rs1 rs2_eq_rs1`
    /// Rust: `fmv_q(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn fmv_q<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: FmvQEmitter<T0, T1, T2>,
    {
        <Self as FmvQEmitter<T0, T1, T2>>::fmv_q(self, rd, rs1, rs2);
    }
    /// RISC-V `fmv.s` instruction.
    ///
    /// # Forms
    /// Assembly: `fmv.s rd rs1 rs2_eq_rs1`
    /// Rust: `fmv_s(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn fmv_s<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: FmvSEmitter<T0, T1, T2>,
    {
        <Self as FmvSEmitter<T0, T1, T2>>::fmv_s(self, rd, rs1, rs2);
    }
    /// RISC-V `fmv.s.x` instruction.
    ///
    /// # Forms
    /// Assembly: `fmv.s.x rd rs1`
    /// Rust: `fmv_s_x(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn fmv_s_x<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: FmvSXEmitter<T0, T1>,
    {
        <Self as FmvSXEmitter<T0, T1>>::fmv_s_x(self, rd, rs1);
    }
    /// Single-precision floating-point move from integer
    ///
    /// Moves the single-precision value encoded in IEEE 754-2008 standard encoding
    /// from the lower 32 bits of integer register `rs1` to the floating-point
    /// register `fd`. The bits are not modified in the transfer, and in particular,
    /// the payloads of non-canonical NaNs are preserved.
    ///
    /// # Forms
    /// Assembly: `fmv.w.x fd, xs1`
    /// Rust: `fmv_w_x(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn fmv_w_x<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: FmvWXEmitter<T0, T1>,
    {
        <Self as FmvWXEmitter<T0, T1>>::fmv_w_x(self, rd, rs1);
    }
    /// RISC-V `fmv.x.d` instruction.
    ///
    /// # Forms
    /// Assembly: `fmv.x.d xd, xs1`
    /// Rust: `fmv_x_d(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn fmv_x_d<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: FmvXDEmitter<T0, T1>,
    {
        <Self as FmvXDEmitter<T0, T1>>::fmv_x_d(self, rd, rs1);
    }
    /// Move half-precision value from floating-point to integer register
    ///
    /// Moves the half-precision value in floating-point register rs1 represented in IEEE 754-2008
    /// encoding to the lower 16 bits of integer register rd.
    ///
    /// The bits are not modified in the transfer, and in particular, the payloads of non-canonical
    /// NaNs are preserved.
    ///
    /// The highest XLEN-16 bits of the destination register are filled with copies of the
    /// floating-point number's sign bit.
    ///
    /// # Forms
    /// Assembly: `fmv.x.h rd, fs1`
    /// Rust: `fmv_x_h(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn fmv_x_h<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: FmvXHEmitter<T0, T1>,
    {
        <Self as FmvXHEmitter<T0, T1>>::fmv_x_h(self, rd, rs1);
    }
    /// RISC-V `fmv.x.s` instruction.
    ///
    /// # Forms
    /// Assembly: `fmv.x.s rd rs1`
    /// Rust: `fmv_x_s(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn fmv_x_s<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: FmvXSEmitter<T0, T1>,
    {
        <Self as FmvXSEmitter<T0, T1>>::fmv_x_s(self, rd, rs1);
    }
    /// Move single-precision value from floating-point to integer register
    ///
    /// Moves the single-precision value in floating-point register rs1 represented in IEEE 754-2008
    /// encoding to the lower 32 bits of integer register rd.
    /// The bits are not modified in the transfer, and in particular, the payloads of non-canonical
    /// NaNs are preserved.
    /// For RV64, the higher 32 bits of the destination register are filled with copies of the
    /// floating-point number's sign bit.
    ///
    /// # Forms
    /// Assembly: `fmv.x.w xd, fs1`
    /// Rust: `fmv_x_w(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn fmv_x_w<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: FmvXWEmitter<T0, T1>,
    {
        <Self as FmvXWEmitter<T0, T1>>::fmv_x_w(self, rd, rs1);
    }
    /// RISC-V `fmvh.x.d` instruction.
    ///
    /// # Forms
    /// Assembly: `fmvh.x.d xd, xs1`
    /// Rust: `fmvh_x_d(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn fmvh_x_d<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: FmvhXDEmitter<T0, T1>,
    {
        <Self as FmvhXDEmitter<T0, T1>>::fmvh_x_d(self, rd, rs1);
    }
    /// RISC-V `fmvh.x.q` instruction.
    ///
    /// # Forms
    /// Assembly: `fmvh.x.q xd, qs1`
    /// Rust: `fmvh_x_q(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn fmvh_x_q<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: FmvhXQEmitter<T0, T1>,
    {
        <Self as FmvhXQEmitter<T0, T1>>::fmvh_x_q(self, rd, rs1);
    }
    /// RISC-V `fmvp.d.x` instruction.
    ///
    /// # Forms
    /// Assembly: `fmvp.d.x xd, xs1, xs2`
    /// Rust: `fmvp_d_x(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn fmvp_d_x<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: FmvpDXEmitter<T0, T1, T2>,
    {
        <Self as FmvpDXEmitter<T0, T1, T2>>::fmvp_d_x(self, rd, rs1, rs2);
    }
    /// RISC-V `fmvp.q.x` instruction.
    ///
    /// # Forms
    /// Assembly: `fmvp.q.x qd, xs1, xs2`
    /// Rust: `fmvp_q_x(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn fmvp_q_x<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: FmvpQXEmitter<T0, T1, T2>,
    {
        <Self as FmvpQXEmitter<T0, T1, T2>>::fmvp_q_x(self, rd, rs1, rs2);
    }
    /// RISC-V `fneg.d` instruction.
    ///
    /// # Forms
    /// Assembly: `fneg.d rd rs1 rs2_eq_rs1`
    /// Rust: `fneg_d(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn fneg_d<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: FnegDEmitter<T0, T1, T2>,
    {
        <Self as FnegDEmitter<T0, T1, T2>>::fneg_d(self, rd, rs1, rs2);
    }
    /// RISC-V `fneg.h` instruction.
    ///
    /// # Forms
    /// Assembly: `fneg.h rd rs1 rs2_eq_rs1`
    /// Rust: `fneg_h(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn fneg_h<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: FnegHEmitter<T0, T1, T2>,
    {
        <Self as FnegHEmitter<T0, T1, T2>>::fneg_h(self, rd, rs1, rs2);
    }
    /// RISC-V `fneg.q` instruction.
    ///
    /// # Forms
    /// Assembly: `fneg.q rd rs1 rs2_eq_rs1`
    /// Rust: `fneg_q(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn fneg_q<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: FnegQEmitter<T0, T1, T2>,
    {
        <Self as FnegQEmitter<T0, T1, T2>>::fneg_q(self, rd, rs1, rs2);
    }
    /// RISC-V `fneg.s` instruction.
    ///
    /// # Forms
    /// Assembly: `fneg.s rd rs1 rs2_eq_rs1`
    /// Rust: `fneg_s(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn fneg_s<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: FnegSEmitter<T0, T1, T2>,
    {
        <Self as FnegSEmitter<T0, T1, T2>>::fneg_s(self, rd, rs1, rs2);
    }
    /// RISC-V `fnmadd.d` instruction.
    ///
    /// # Forms
    /// Assembly: `fnmadd.d xd, xs1, xs2, xs3, rm`
    /// Rust: `fnmadd_d(rd, rs1, rs2, rs3, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    /// - `rs3` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fnmadd_d<T0, T1, T2, T3, T4>(&mut self, rd: T0, rs1: T1, rs2: T2, rs3: T3, rm: T4)
    where
        Self: FnmaddDEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as FnmaddDEmitter<T0, T1, T2, T3, T4>>::fnmadd_d(self, rd, rs1, rs2, rs3, rm);
    }
    /// RISC-V `fnmadd.h` instruction.
    ///
    /// # Forms
    /// Assembly: `fnmadd.h xd, xs1, xs2, xs3, rm`
    /// Rust: `fnmadd_h(rd, rs1, rs2, rs3, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    /// - `rs3` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fnmadd_h<T0, T1, T2, T3, T4>(&mut self, rd: T0, rs1: T1, rs2: T2, rs3: T3, rm: T4)
    where
        Self: FnmaddHEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as FnmaddHEmitter<T0, T1, T2, T3, T4>>::fnmadd_h(self, rd, rs1, rs2, rs3, rm);
    }
    /// RISC-V `fnmadd.q` instruction.
    ///
    /// # Forms
    /// Assembly: `fnmadd.q qd, qs1, qs2, qs3, rm`
    /// Rust: `fnmadd_q(rd, rs1, rs2, rs3, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    /// - `rs3` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fnmadd_q<T0, T1, T2, T3, T4>(&mut self, rd: T0, rs1: T1, rs2: T2, rs3: T3, rm: T4)
    where
        Self: FnmaddQEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as FnmaddQEmitter<T0, T1, T2, T3, T4>>::fnmadd_q(self, rd, rs1, rs2, rs3, rm);
    }
    /// RISC-V `fnmadd.s` instruction.
    ///
    /// # Forms
    /// Assembly: `fnmadd.s fd, fs1, fs2, fs3, rm`
    /// Rust: `fnmadd_s(rd, rs1, rs2, rs3, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    /// - `rs3` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fnmadd_s<T0, T1, T2, T3, T4>(&mut self, rd: T0, rs1: T1, rs2: T2, rs3: T3, rm: T4)
    where
        Self: FnmaddSEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as FnmaddSEmitter<T0, T1, T2, T3, T4>>::fnmadd_s(self, rd, rs1, rs2, rs3, rm);
    }
    /// RISC-V `fnmsub.d` instruction.
    ///
    /// # Forms
    /// Assembly: `fnmsub.d xd, xs1, xs2, xs3, rm`
    /// Rust: `fnmsub_d(rd, rs1, rs2, rs3, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    /// - `rs3` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fnmsub_d<T0, T1, T2, T3, T4>(&mut self, rd: T0, rs1: T1, rs2: T2, rs3: T3, rm: T4)
    where
        Self: FnmsubDEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as FnmsubDEmitter<T0, T1, T2, T3, T4>>::fnmsub_d(self, rd, rs1, rs2, rs3, rm);
    }
    /// RISC-V `fnmsub.h` instruction.
    ///
    /// # Forms
    /// Assembly: `fnmsub.h xd, xs1, xs2, xs3, rm`
    /// Rust: `fnmsub_h(rd, rs1, rs2, rs3, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    /// - `rs3` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fnmsub_h<T0, T1, T2, T3, T4>(&mut self, rd: T0, rs1: T1, rs2: T2, rs3: T3, rm: T4)
    where
        Self: FnmsubHEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as FnmsubHEmitter<T0, T1, T2, T3, T4>>::fnmsub_h(self, rd, rs1, rs2, rs3, rm);
    }
    /// RISC-V `fnmsub.q` instruction.
    ///
    /// # Forms
    /// Assembly: `fnmsub.q qd, qs1, qs2, qs3, rm`
    /// Rust: `fnmsub_q(rd, rs1, rs2, rs3, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    /// - `rs3` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fnmsub_q<T0, T1, T2, T3, T4>(&mut self, rd: T0, rs1: T1, rs2: T2, rs3: T3, rm: T4)
    where
        Self: FnmsubQEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as FnmsubQEmitter<T0, T1, T2, T3, T4>>::fnmsub_q(self, rd, rs1, rs2, rs3, rm);
    }
    /// RISC-V `fnmsub.s` instruction.
    ///
    /// # Forms
    /// Assembly: `fnmsub.s xd, xs1, xs2, xs3, rm`
    /// Rust: `fnmsub_s(rd, rs1, rs2, rs3, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    /// - `rs3` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fnmsub_s<T0, T1, T2, T3, T4>(&mut self, rd: T0, rs1: T1, rs2: T2, rs3: T3, rm: T4)
    where
        Self: FnmsubSEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as FnmsubSEmitter<T0, T1, T2, T3, T4>>::fnmsub_s(self, rd, rs1, rs2, rs3, rm);
    }
    /// RISC-V `frcsr` instruction.
    ///
    /// # Forms
    /// Assembly: `frcsr rd`
    /// Rust: `frcsr(rd)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    pub fn frcsr<T0>(&mut self, rd: T0)
    where
        Self: FrcsrEmitter<T0>,
    {
        <Self as FrcsrEmitter<T0>>::frcsr(self, rd);
    }
    /// RISC-V `frflags` instruction.
    ///
    /// # Forms
    /// Assembly: `frflags rd`
    /// Rust: `frflags(rd)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    pub fn frflags<T0>(&mut self, rd: T0)
    where
        Self: FrflagsEmitter<T0>,
    {
        <Self as FrflagsEmitter<T0>>::frflags(self, rd);
    }
    /// RISC-V `fround.d` instruction.
    ///
    /// # Forms
    /// Assembly: `fround.d xd, xs1, rm`
    /// Rust: `fround_d(rd, rs1, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fround_d<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
    where
        Self: FroundDEmitter<T0, T1, T2>,
    {
        <Self as FroundDEmitter<T0, T1, T2>>::fround_d(self, rd, rs1, rm);
    }
    /// RISC-V `fround.h` instruction.
    ///
    /// # Forms
    /// Assembly: `fround.h xd, xs1, rm`
    /// Rust: `fround_h(rd, rs1, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fround_h<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
    where
        Self: FroundHEmitter<T0, T1, T2>,
    {
        <Self as FroundHEmitter<T0, T1, T2>>::fround_h(self, rd, rs1, rm);
    }
    /// RISC-V `fround.q` instruction.
    ///
    /// # Forms
    /// Assembly: `fround.q qd, qs1, rm`
    /// Rust: `fround_q(rd, rs1, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fround_q<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
    where
        Self: FroundQEmitter<T0, T1, T2>,
    {
        <Self as FroundQEmitter<T0, T1, T2>>::fround_q(self, rd, rs1, rm);
    }
    /// RISC-V `fround.s` instruction.
    ///
    /// # Forms
    /// Assembly: `fround.s fd, xs1, rm`
    /// Rust: `fround_s(rd, rs1, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fround_s<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
    where
        Self: FroundSEmitter<T0, T1, T2>,
    {
        <Self as FroundSEmitter<T0, T1, T2>>::fround_s(self, rd, rs1, rm);
    }
    /// RISC-V `froundnx.d` instruction.
    ///
    /// # Forms
    /// Assembly: `froundnx.d xd, xs1, rm`
    /// Rust: `froundnx_d(rd, rs1, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rm` — Rounding mode.
    pub fn froundnx_d<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
    where
        Self: FroundnxDEmitter<T0, T1, T2>,
    {
        <Self as FroundnxDEmitter<T0, T1, T2>>::froundnx_d(self, rd, rs1, rm);
    }
    /// RISC-V `froundnx.h` instruction.
    ///
    /// # Forms
    /// Assembly: `froundnx.h xd, xs1, rm`
    /// Rust: `froundnx_h(rd, rs1, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rm` — Rounding mode.
    pub fn froundnx_h<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
    where
        Self: FroundnxHEmitter<T0, T1, T2>,
    {
        <Self as FroundnxHEmitter<T0, T1, T2>>::froundnx_h(self, rd, rs1, rm);
    }
    /// RISC-V `froundnx.q` instruction.
    ///
    /// # Forms
    /// Assembly: `froundnx.q qd, qs1, rm`
    /// Rust: `froundnx_q(rd, rs1, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rm` — Rounding mode.
    pub fn froundnx_q<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
    where
        Self: FroundnxQEmitter<T0, T1, T2>,
    {
        <Self as FroundnxQEmitter<T0, T1, T2>>::froundnx_q(self, rd, rs1, rm);
    }
    /// RISC-V `froundnx.s` instruction.
    ///
    /// # Forms
    /// Assembly: `froundnx.s fd, rs1, rm`
    /// Rust: `froundnx_s(rd, rs1, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rm` — Rounding mode.
    pub fn froundnx_s<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
    where
        Self: FroundnxSEmitter<T0, T1, T2>,
    {
        <Self as FroundnxSEmitter<T0, T1, T2>>::froundnx_s(self, rd, rs1, rm);
    }
    /// RISC-V `frrm` instruction.
    ///
    /// # Forms
    /// Assembly: `frrm rd`
    /// Rust: `frrm(rd)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    pub fn frrm<T0>(&mut self, rd: T0)
    where
        Self: FrrmEmitter<T0>,
    {
        <Self as FrrmEmitter<T0>>::frrm(self, rd);
    }
    /// RISC-V `fscsr` instruction.
    ///
    /// # Forms
    /// Assembly: `fscsr rd rs1`
    /// Rust: `fscsr(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn fscsr<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: FscsrEmitter<T0, T1>,
    {
        <Self as FscsrEmitter<T0, T1>>::fscsr(self, rd, rs1);
    }
    /// RISC-V `fsd` instruction.
    ///
    /// # Forms
    /// Assembly: `fsd xs1, xs2, imm`
    /// Rust: `fsd(rs1, rs2, imm)`
    ///
    /// # Arguments
    /// - `rs1` — Memory base register.
    /// - `rs2` — Source register.
    /// - `imm` — Immediate encoding value.
    pub fn fsd<T0, T1, T2>(&mut self, rs1: T0, rs2: T1, imm: T2)
    where
        Self: FsdEmitter<T0, T1, T2>,
    {
        <Self as FsdEmitter<T0, T1, T2>>::fsd(self, rs1, rs2, imm);
    }
    /// RISC-V `fsflags` instruction.
    ///
    /// # Forms
    /// Assembly: `fsflags rd rs1`
    /// Rust: `fsflags(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn fsflags<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: FsflagsEmitter<T0, T1>,
    {
        <Self as FsflagsEmitter<T0, T1>>::fsflags(self, rd, rs1);
    }
    /// RISC-V `fsflagsi` instruction.
    ///
    /// # Forms
    /// Assembly: `fsflagsi rd zimm5`
    /// Rust: `fsflagsi(rd, zimm5)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `zimm5` — Immediate encoding value.
    pub fn fsflagsi<T0, T1>(&mut self, rd: T0, zimm5: T1)
    where
        Self: FsflagsiEmitter<T0, T1>,
    {
        <Self as FsflagsiEmitter<T0, T1>>::fsflagsi(self, rd, zimm5);
    }
    /// RISC-V `fsgnj.d` instruction.
    ///
    /// # Forms
    /// Assembly: `fsgnj.d xd, xs1, xs2`
    /// Rust: `fsgnj_d(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn fsgnj_d<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: FsgnjDEmitter<T0, T1, T2>,
    {
        <Self as FsgnjDEmitter<T0, T1, T2>>::fsgnj_d(self, rd, rs1, rs2);
    }
    /// RISC-V `fsgnj.h` instruction.
    ///
    /// # Forms
    /// Assembly: `fsgnj.h xd, xs1, xs2`
    /// Rust: `fsgnj_h(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn fsgnj_h<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: FsgnjHEmitter<T0, T1, T2>,
    {
        <Self as FsgnjHEmitter<T0, T1, T2>>::fsgnj_h(self, rd, rs1, rs2);
    }
    /// RISC-V `fsgnj.q` instruction.
    ///
    /// # Forms
    /// Assembly: `fsgnj.q qd, qs1, qs2`
    /// Rust: `fsgnj_q(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn fsgnj_q<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: FsgnjQEmitter<T0, T1, T2>,
    {
        <Self as FsgnjQEmitter<T0, T1, T2>>::fsgnj_q(self, rd, rs1, rs2);
    }
    /// Single-precision sign inject
    ///
    /// Writes _fd_ with sign bit of _fs2_ and the exponent and mantissa of _fs1_.
    ///
    /// Sign-injection instructions do not set floating-point exception flags, nor do they canonicalize NaNs.
    ///
    /// # Forms
    /// Assembly: `fsgnj.s fd, fs1, fs2`
    /// Rust: `fsgnj_s(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn fsgnj_s<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: FsgnjSEmitter<T0, T1, T2>,
    {
        <Self as FsgnjSEmitter<T0, T1, T2>>::fsgnj_s(self, rd, rs1, rs2);
    }
    /// RISC-V `fsgnjn.d` instruction.
    ///
    /// # Forms
    /// Assembly: `fsgnjn.d xd, xs1, xs2`
    /// Rust: `fsgnjn_d(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn fsgnjn_d<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: FsgnjnDEmitter<T0, T1, T2>,
    {
        <Self as FsgnjnDEmitter<T0, T1, T2>>::fsgnjn_d(self, rd, rs1, rs2);
    }
    /// RISC-V `fsgnjn.h` instruction.
    ///
    /// # Forms
    /// Assembly: `fsgnjn.h xd, xs1, xs2`
    /// Rust: `fsgnjn_h(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn fsgnjn_h<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: FsgnjnHEmitter<T0, T1, T2>,
    {
        <Self as FsgnjnHEmitter<T0, T1, T2>>::fsgnjn_h(self, rd, rs1, rs2);
    }
    /// RISC-V `fsgnjn.q` instruction.
    ///
    /// # Forms
    /// Assembly: `fsgnjn.q qd, qs1, qs2`
    /// Rust: `fsgnjn_q(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn fsgnjn_q<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: FsgnjnQEmitter<T0, T1, T2>,
    {
        <Self as FsgnjnQEmitter<T0, T1, T2>>::fsgnjn_q(self, rd, rs1, rs2);
    }
    /// Single-precision sign inject negate
    ///
    /// Writes _fd_ with the opposite of the sign bit of _fs2_ and the exponent and mantissa of _fs1_.
    ///
    /// Sign-injection instructions do not set floating-point exception flags, nor do they canonicalize NaNs.
    ///
    /// # Forms
    /// Assembly: `fsgnjn.s fd, fs1, fs2`
    /// Rust: `fsgnjn_s(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn fsgnjn_s<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: FsgnjnSEmitter<T0, T1, T2>,
    {
        <Self as FsgnjnSEmitter<T0, T1, T2>>::fsgnjn_s(self, rd, rs1, rs2);
    }
    /// RISC-V `fsgnjx.d` instruction.
    ///
    /// # Forms
    /// Assembly: `fsgnjx.d xd, xs1, xs2`
    /// Rust: `fsgnjx_d(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn fsgnjx_d<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: FsgnjxDEmitter<T0, T1, T2>,
    {
        <Self as FsgnjxDEmitter<T0, T1, T2>>::fsgnjx_d(self, rd, rs1, rs2);
    }
    /// RISC-V `fsgnjx.h` instruction.
    ///
    /// # Forms
    /// Assembly: `fsgnjx.h xd, xs1, xs2`
    /// Rust: `fsgnjx_h(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn fsgnjx_h<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: FsgnjxHEmitter<T0, T1, T2>,
    {
        <Self as FsgnjxHEmitter<T0, T1, T2>>::fsgnjx_h(self, rd, rs1, rs2);
    }
    /// RISC-V `fsgnjx.q` instruction.
    ///
    /// # Forms
    /// Assembly: `fsgnjx.q qd, qs1, qs2`
    /// Rust: `fsgnjx_q(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn fsgnjx_q<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: FsgnjxQEmitter<T0, T1, T2>,
    {
        <Self as FsgnjxQEmitter<T0, T1, T2>>::fsgnjx_q(self, rd, rs1, rs2);
    }
    /// Single-precision sign inject exclusive or
    ///
    /// Writes _fd_ with the xor of the sign bits of _fs2_ and _fs1_ and the exponent and mantissa of _fs1_.
    ///
    /// Sign-injection instructions do not set floating-point exception flags, nor do they canonicalize NaNs.
    ///
    /// # Forms
    /// Assembly: `fsgnjx.s fd, fs1, fs2`
    /// Rust: `fsgnjx_s(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn fsgnjx_s<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: FsgnjxSEmitter<T0, T1, T2>,
    {
        <Self as FsgnjxSEmitter<T0, T1, T2>>::fsgnjx_s(self, rd, rs1, rs2);
    }
    /// Half-precision floating-point store
    ///
    /// The `fsh` instruction stores a half-precision floating-point value
    /// from register _rd_ to memory at address _rs1_ + _imm_.
    ///
    /// `fsh` does not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved.
    ///
    /// `fsh` ignores all but the lower 16 bits in _rs2_.
    ///
    /// `fsh` is only guaranteed to execute atomically if the effective address is naturally aligned.
    ///
    /// # Forms
    /// Assembly: `fsh fs2, imm(xs1)`
    /// Rust: `fsh(rs1, rs2, imm)`
    ///
    /// # Arguments
    /// - `rs1` — Memory base register.
    /// - `rs2` — Source register.
    /// - `imm` — Immediate encoding value.
    pub fn fsh<T0, T1, T2>(&mut self, rs1: T0, rs2: T1, imm: T2)
    where
        Self: FshEmitter<T0, T1, T2>,
    {
        <Self as FshEmitter<T0, T1, T2>>::fsh(self, rs1, rs2, imm);
    }
    /// RISC-V `fsq` instruction.
    ///
    /// # Forms
    /// Assembly: `fsq xs1, qs2, imm`
    /// Rust: `fsq(rs1, rs2, imm)`
    ///
    /// # Arguments
    /// - `rs1` — Memory base register.
    /// - `rs2` — Source register.
    /// - `imm` — Immediate encoding value.
    pub fn fsq<T0, T1, T2>(&mut self, rs1: T0, rs2: T1, imm: T2)
    where
        Self: FsqEmitter<T0, T1, T2>,
    {
        <Self as FsqEmitter<T0, T1, T2>>::fsq(self, rs1, rs2, imm);
    }
    /// RISC-V `fsqrt.d` instruction.
    ///
    /// # Forms
    /// Assembly: `fsqrt.d xd, xs1, rm`
    /// Rust: `fsqrt_d(rd, rs1, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fsqrt_d<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
    where
        Self: FsqrtDEmitter<T0, T1, T2>,
    {
        <Self as FsqrtDEmitter<T0, T1, T2>>::fsqrt_d(self, rd, rs1, rm);
    }
    /// RISC-V `fsqrt.h` instruction.
    ///
    /// # Forms
    /// Assembly: `fsqrt.h xd, xs1, rm`
    /// Rust: `fsqrt_h(rd, rs1, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fsqrt_h<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
    where
        Self: FsqrtHEmitter<T0, T1, T2>,
    {
        <Self as FsqrtHEmitter<T0, T1, T2>>::fsqrt_h(self, rd, rs1, rm);
    }
    /// RISC-V `fsqrt.q` instruction.
    ///
    /// # Forms
    /// Assembly: `fsqrt.q qd, qs1, rm`
    /// Rust: `fsqrt_q(rd, rs1, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fsqrt_q<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
    where
        Self: FsqrtQEmitter<T0, T1, T2>,
    {
        <Self as FsqrtQEmitter<T0, T1, T2>>::fsqrt_q(self, rd, rs1, rm);
    }
    /// RISC-V `fsqrt.s` instruction.
    ///
    /// # Forms
    /// Assembly: `fsqrt.s fd, fs1, rm`
    /// Rust: `fsqrt_s(rd, rs1, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fsqrt_s<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
    where
        Self: FsqrtSEmitter<T0, T1, T2>,
    {
        <Self as FsqrtSEmitter<T0, T1, T2>>::fsqrt_s(self, rd, rs1, rm);
    }
    /// RISC-V `fsrm` instruction.
    ///
    /// # Forms
    /// Assembly: `fsrm rd rs1`
    /// Rust: `fsrm(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn fsrm<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: FsrmEmitter<T0, T1>,
    {
        <Self as FsrmEmitter<T0, T1>>::fsrm(self, rd, rs1);
    }
    /// RISC-V `fsrmi` instruction.
    ///
    /// # Forms
    /// Assembly: `fsrmi rd zimm5`
    /// Rust: `fsrmi(rd, zimm5)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `zimm5` — Immediate encoding value.
    pub fn fsrmi<T0, T1>(&mut self, rd: T0, zimm5: T1)
    where
        Self: FsrmiEmitter<T0, T1>,
    {
        <Self as FsrmiEmitter<T0, T1>>::fsrmi(self, rd, zimm5);
    }
    /// RISC-V `fsub.d` instruction.
    ///
    /// # Forms
    /// Assembly: `fsub.d xd, xs1, xs2, rm`
    /// Rust: `fsub_d(rd, rs1, rs2, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fsub_d<T0, T1, T2, T3>(&mut self, rd: T0, rs1: T1, rs2: T2, rm: T3)
    where
        Self: FsubDEmitter<T0, T1, T2, T3>,
    {
        <Self as FsubDEmitter<T0, T1, T2, T3>>::fsub_d(self, rd, rs1, rs2, rm);
    }
    /// RISC-V `fsub.h` instruction.
    ///
    /// # Forms
    /// Assembly: `fsub.h xd, xs1, xs2, rm`
    /// Rust: `fsub_h(rd, rs1, rs2, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fsub_h<T0, T1, T2, T3>(&mut self, rd: T0, rs1: T1, rs2: T2, rm: T3)
    where
        Self: FsubHEmitter<T0, T1, T2, T3>,
    {
        <Self as FsubHEmitter<T0, T1, T2, T3>>::fsub_h(self, rd, rs1, rs2, rm);
    }
    /// RISC-V `fsub.q` instruction.
    ///
    /// # Forms
    /// Assembly: `fsub.q qd, qs1, qs2, rm`
    /// Rust: `fsub_q(rd, rs1, rs2, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fsub_q<T0, T1, T2, T3>(&mut self, rd: T0, rs1: T1, rs2: T2, rm: T3)
    where
        Self: FsubQEmitter<T0, T1, T2, T3>,
    {
        <Self as FsubQEmitter<T0, T1, T2, T3>>::fsub_q(self, rd, rs1, rs2, rm);
    }
    /// Single-precision floating-point subtraction
    ///
    /// Do the single-precision floating-point subtraction of fs2 from fs1 and store the result in fd.
    /// rm is the dynamic Rounding Mode.
    ///
    /// # Forms
    /// Assembly: `fsub.s fd, fs1, fs2, rm`
    /// Rust: `fsub_s(rd, rs1, rs2, rm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    /// - `rm` — Rounding mode.
    pub fn fsub_s<T0, T1, T2, T3>(&mut self, rd: T0, rs1: T1, rs2: T2, rm: T3)
    where
        Self: FsubSEmitter<T0, T1, T2, T3>,
    {
        <Self as FsubSEmitter<T0, T1, T2, T3>>::fsub_s(self, rd, rs1, rs2, rm);
    }
    /// Single-precision floating-point store
    ///
    /// The `fsw` instruction stores a single-precision floating-point value in _fs2_ to memory at address _rs1_ + _imm_.
    ///
    /// `fsw` does not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved.
    ///
    /// # Forms
    /// Assembly: `fsw fs2, xs1, imm`
    /// Rust: `fsw(rs1, rs2, imm)`
    ///
    /// # Arguments
    /// - `rs1` — Memory base register.
    /// - `rs2` — Source register.
    /// - `imm` — Immediate encoding value.
    pub fn fsw<T0, T1, T2>(&mut self, rs1: T0, rs2: T1, imm: T2)
    where
        Self: FswEmitter<T0, T1, T2>,
    {
        <Self as FswEmitter<T0, T1, T2>>::fsw(self, rs1, rs2, imm);
    }
    /// RISC-V `hfence.gvma` instruction.
    ///
    /// # Forms
    /// Assembly: `hfence.gvma xs1, xs2`
    /// Rust: `hfence_gvma(rs1, rs2)`
    ///
    /// # Arguments
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn hfence_gvma<T0, T1>(&mut self, rs1: T0, rs2: T1)
    where
        Self: HfenceGvmaEmitter<T0, T1>,
    {
        <Self as HfenceGvmaEmitter<T0, T1>>::hfence_gvma(self, rs1, rs2);
    }
    /// RISC-V `hfence.vvma` instruction.
    ///
    /// # Forms
    /// Assembly: `hfence.vvma xs1, xs2`
    /// Rust: `hfence_vvma(rs1, rs2)`
    ///
    /// # Arguments
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn hfence_vvma<T0, T1>(&mut self, rs1: T0, rs2: T1)
    where
        Self: HfenceVvmaEmitter<T0, T1>,
    {
        <Self as HfenceVvmaEmitter<T0, T1>>::hfence_vvma(self, rs1, rs2);
    }
    /// Invalidate cached address translations
    ///
    /// `hinval.gvma` has the same semantics as `sinval.vma` except that it combines with
    /// `sfence.w.inval` and `sfence.inval.ir` to replace `hfence.gvma` and uses VMID instead of ASID.
    ///
    /// # Forms
    /// Assembly: `hinval.gvma xs1, xs2`
    /// Rust: `hinval_gvma(rs1, rs2)`
    ///
    /// # Arguments
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn hinval_gvma<T0, T1>(&mut self, rs1: T0, rs2: T1)
    where
        Self: HinvalGvmaEmitter<T0, T1>,
    {
        <Self as HinvalGvmaEmitter<T0, T1>>::hinval_gvma(self, rs1, rs2);
    }
    /// Invalidate cached address translations
    ///
    /// `hinval.vvma` has the same semantics as `sinval.vma` except that it combines with
    /// `sfence.w.inval` and `sfence.inval.ir` to replace `hfence.vvma`.
    ///
    /// # Forms
    /// Assembly: `hinval.vvma xs1, xs2`
    /// Rust: `hinval_vvma(rs1, rs2)`
    ///
    /// # Arguments
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn hinval_vvma<T0, T1>(&mut self, rs1: T0, rs2: T1)
    where
        Self: HinvalVvmaEmitter<T0, T1>,
    {
        <Self as HinvalVvmaEmitter<T0, T1>>::hinval_vvma(self, rs1, rs2);
    }
    /// RISC-V `hlv.b` instruction.
    ///
    /// # Forms
    /// Assembly: `hlv.b xd, xs1`
    /// Rust: `hlv_b(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn hlv_b<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: HlvBEmitter<T0, T1>,
    {
        <Self as HlvBEmitter<T0, T1>>::hlv_b(self, rd, rs1);
    }
    /// RISC-V `hlv.bu` instruction.
    ///
    /// # Forms
    /// Assembly: `hlv.bu xd, xs1`
    /// Rust: `hlv_bu(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn hlv_bu<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: HlvBuEmitter<T0, T1>,
    {
        <Self as HlvBuEmitter<T0, T1>>::hlv_bu(self, rd, rs1);
    }
    /// RISC-V `hlv.d` instruction.
    ///
    /// # Forms
    /// Assembly: `hlv.d xd, xs1`
    /// Rust: `hlv_d(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn hlv_d<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: HlvDEmitter<T0, T1>,
    {
        <Self as HlvDEmitter<T0, T1>>::hlv_d(self, rd, rs1);
    }
    /// RISC-V `hlv.h` instruction.
    ///
    /// # Forms
    /// Assembly: `hlv.h xd, xs1`
    /// Rust: `hlv_h(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn hlv_h<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: HlvHEmitter<T0, T1>,
    {
        <Self as HlvHEmitter<T0, T1>>::hlv_h(self, rd, rs1);
    }
    /// RISC-V `hlv.hu` instruction.
    ///
    /// # Forms
    /// Assembly: `hlv.hu xd, xs1`
    /// Rust: `hlv_hu(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn hlv_hu<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: HlvHuEmitter<T0, T1>,
    {
        <Self as HlvHuEmitter<T0, T1>>::hlv_hu(self, rd, rs1);
    }
    /// RISC-V `hlv.w` instruction.
    ///
    /// # Forms
    /// Assembly: `hlv.w xd, xs1`
    /// Rust: `hlv_w(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn hlv_w<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: HlvWEmitter<T0, T1>,
    {
        <Self as HlvWEmitter<T0, T1>>::hlv_w(self, rd, rs1);
    }
    /// RISC-V `hlv.wu` instruction.
    ///
    /// # Forms
    /// Assembly: `hlv.wu xd, xs1`
    /// Rust: `hlv_wu(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn hlv_wu<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: HlvWuEmitter<T0, T1>,
    {
        <Self as HlvWuEmitter<T0, T1>>::hlv_wu(self, rd, rs1);
    }
    /// RISC-V `hlvx.hu` instruction.
    ///
    /// # Forms
    /// Assembly: `hlvx.hu xd, xs1`
    /// Rust: `hlvx_hu(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn hlvx_hu<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: HlvxHuEmitter<T0, T1>,
    {
        <Self as HlvxHuEmitter<T0, T1>>::hlvx_hu(self, rd, rs1);
    }
    /// RISC-V `hlvx.wu` instruction.
    ///
    /// # Forms
    /// Assembly: `hlvx.wu xd, xs1`
    /// Rust: `hlvx_wu(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn hlvx_wu<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: HlvxWuEmitter<T0, T1>,
    {
        <Self as HlvxWuEmitter<T0, T1>>::hlvx_wu(self, rd, rs1);
    }
    /// RISC-V `hsv.b` instruction.
    ///
    /// # Forms
    /// Assembly: `hsv.b xs1, xs2`
    /// Rust: `hsv_b(rs1, rs2)`
    ///
    /// # Arguments
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn hsv_b<T0, T1>(&mut self, rs1: T0, rs2: T1)
    where
        Self: HsvBEmitter<T0, T1>,
    {
        <Self as HsvBEmitter<T0, T1>>::hsv_b(self, rs1, rs2);
    }
    /// RISC-V `hsv.d` instruction.
    ///
    /// # Forms
    /// Assembly: `hsv.d xs1, xs2`
    /// Rust: `hsv_d(rs1, rs2)`
    ///
    /// # Arguments
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn hsv_d<T0, T1>(&mut self, rs1: T0, rs2: T1)
    where
        Self: HsvDEmitter<T0, T1>,
    {
        <Self as HsvDEmitter<T0, T1>>::hsv_d(self, rs1, rs2);
    }
    /// RISC-V `hsv.h` instruction.
    ///
    /// # Forms
    /// Assembly: `hsv.h xs1, xs2`
    /// Rust: `hsv_h(rs1, rs2)`
    ///
    /// # Arguments
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn hsv_h<T0, T1>(&mut self, rs1: T0, rs2: T1)
    where
        Self: HsvHEmitter<T0, T1>,
    {
        <Self as HsvHEmitter<T0, T1>>::hsv_h(self, rs1, rs2);
    }
    /// RISC-V `hsv.w` instruction.
    ///
    /// # Forms
    /// Assembly: `hsv.w xs1, xs2`
    /// Rust: `hsv_w(rs1, rs2)`
    ///
    /// # Arguments
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn hsv_w<T0, T1>(&mut self, rs1: T0, rs2: T1)
    where
        Self: HsvWEmitter<T0, T1>,
    {
        <Self as HsvWEmitter<T0, T1>>::hsv_w(self, rs1, rs2);
    }
    /// RISC-V `j` instruction.
    ///
    /// # Forms
    /// Assembly: `j jimm20`
    /// Rust: `j(imm)`
    ///
    /// # Arguments
    /// - `imm` — Immediate encoding value.
    pub fn j<T0>(&mut self, imm: T0)
    where
        Self: JEmitter<T0>,
    {
        <Self as JEmitter<T0>>::j(self, imm);
    }
    /// Jump and link
    ///
    /// Jump to a PC-relative offset and store the return
    /// address in rd.
    ///
    /// # Forms
    /// Assembly: `jal xd, imm`
    /// Rust: `jal(rd, imm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `imm` — Immediate encoding value.
    pub fn jal<T0, T1>(&mut self, rd: T0, imm: T1)
    where
        Self: JalEmitter<T0, T1>,
    {
        <Self as JalEmitter<T0, T1>>::jal(self, rd, imm);
    }
    /// RISC-V `jal.pseudo` instruction.
    ///
    /// # Forms
    /// Assembly: `jal.pseudo jimm20`
    /// Rust: `jal_pseudo(imm)`
    ///
    /// # Arguments
    /// - `imm` — Immediate encoding value.
    pub fn jal_pseudo<T0>(&mut self, imm: T0)
    where
        Self: JalPseudoEmitter<T0>,
    {
        <Self as JalPseudoEmitter<T0>>::jal_pseudo(self, imm);
    }
    /// Jump and link register
    ///
    /// Jump to an address formed by adding rs1
    /// to a signed offset then clearing the least
    /// significant bit, and store the return address
    /// in rd.
    ///
    /// # Forms
    /// Assembly: `jalr xd, imm(rs1)`
    /// Rust: `jalr(rd, rs1, imm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `imm` — Immediate encoding value.
    pub fn jalr<T0, T1, T2>(&mut self, rd: T0, rs1: T1, imm: T2)
    where
        Self: JalrEmitter<T0, T1, T2>,
    {
        <Self as JalrEmitter<T0, T1, T2>>::jalr(self, rd, rs1, imm);
    }
    /// RISC-V `jalr.pseudo` instruction.
    ///
    /// # Forms
    /// Assembly: `jalr.pseudo rs1`
    /// Rust: `jalr_pseudo(rs1)`
    ///
    /// # Arguments
    /// - `rs1` — Source register.
    pub fn jalr_pseudo<T0>(&mut self, rs1: T0)
    where
        Self: JalrPseudoEmitter<T0>,
    {
        <Self as JalrPseudoEmitter<T0>>::jalr_pseudo(self, rs1);
    }
    /// RISC-V `jr` instruction.
    ///
    /// # Forms
    /// Assembly: `jr rs1`
    /// Rust: `jr(rs1)`
    ///
    /// # Arguments
    /// - `rs1` — Source register.
    pub fn jr<T0>(&mut self, rs1: T0)
    where
        Self: JrEmitter<T0>,
    {
        <Self as JrEmitter<T0>>::jr(self, rs1);
    }
    /// Load byte
    ///
    /// Load 8 bits of data into register `rd` from an
    /// address formed by adding `rs1` to a signed offset.
    /// Sign extend the result.
    ///
    /// # Forms
    /// Assembly: `lb xd, imm(rs1)`
    /// Rust: `lb(rd, rs1, imm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Memory base register.
    /// - `imm` — Immediate encoding value.
    pub fn lb<T0, T1, T2>(&mut self, rd: T0, rs1: T1, imm: T2)
    where
        Self: LbEmitter<T0, T1, T2>,
    {
        <Self as LbEmitter<T0, T1, T2>>::lb(self, rd, rs1, imm);
    }
    /// Load byte unsigned
    ///
    /// Load 8 bits of data into register `rd` from an
    /// address formed by adding `rs1` to a signed offset.
    /// Zero extend the result.
    ///
    /// # Forms
    /// Assembly: `lbu xd, imm(rs1)`
    /// Rust: `lbu(rd, rs1, imm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Memory base register.
    /// - `imm` — Immediate encoding value.
    pub fn lbu<T0, T1, T2>(&mut self, rd: T0, rs1: T1, imm: T2)
    where
        Self: LbuEmitter<T0, T1, T2>,
    {
        <Self as LbuEmitter<T0, T1, T2>>::lbu(self, rd, rs1, imm);
    }
    /// Load doubleword
    ///
    /// Load 64 bits of data into register `rd` from an
    /// address formed by adding `rs1` to a signed offset.
    ///
    /// # Forms
    /// Assembly: `ld xd, imm(rs1)`
    /// Rust: `ld(rd, rs1, imm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Memory base register.
    /// - `imm` — Immediate encoding value.
    pub fn ld<T0, T1, T2>(&mut self, rd: T0, rs1: T1, imm: T2)
    where
        Self: LdEmitter<T0, T1, T2>,
    {
        <Self as LdEmitter<T0, T1, T2>>::ld(self, rd, rs1, imm);
    }
    /// Load halfword
    ///
    /// Load 16 bits of data into register `rd` from an
    /// address formed by adding `rs1` to a signed offset.
    /// Sign extend the result.
    ///
    /// # Forms
    /// Assembly: `lh xd, imm(rs1)`
    /// Rust: `lh(rd, rs1, imm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Memory base register.
    /// - `imm` — Immediate encoding value.
    pub fn lh<T0, T1, T2>(&mut self, rd: T0, rs1: T1, imm: T2)
    where
        Self: LhEmitter<T0, T1, T2>,
    {
        <Self as LhEmitter<T0, T1, T2>>::lh(self, rd, rs1, imm);
    }
    /// Load halfword unsigned
    ///
    /// Load 16 bits of data into register `rd` from an
    /// address formed by adding `rs1` to a signed offset.
    /// Zero extend the result.
    ///
    /// # Forms
    /// Assembly: `lhu xd, imm(rs1)`
    /// Rust: `lhu(rd, rs1, imm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Memory base register.
    /// - `imm` — Immediate encoding value.
    pub fn lhu<T0, T1, T2>(&mut self, rd: T0, rs1: T1, imm: T2)
    where
        Self: LhuEmitter<T0, T1, T2>,
    {
        <Self as LhuEmitter<T0, T1, T2>>::lhu(self, rd, rs1, imm);
    }
    /// RISC-V `lpad` instruction.
    ///
    /// # Forms
    /// Assembly: `lpad imm`
    /// Rust: `lpad(imm)`
    ///
    /// # Arguments
    /// - `imm` — Immediate encoding value.
    pub fn lpad<T0>(&mut self, imm: T0)
    where
        Self: LpadEmitter<T0>,
    {
        <Self as LpadEmitter<T0>>::lpad(self, imm);
    }
    /// Load reserved doubleword
    ///
    /// Loads a word from the address in rs1, places the value in rd,
    /// and registers a _reservation set_  -- a set of bytes that subsumes the bytes in the
    /// addressed word.
    ///
    /// The address in rs1 must be 8-byte aligned.
    ///
    /// If the address is not naturally aligned, a `LoadAddressMisaligned` exception or an
    /// `LoadAccessFault` exception will be generated. The access-fault exception can be generated
    /// for a memory access that would otherwise be able to complete except for the misalignment,
    /// if the misaligned access should not be emulated.
    ///
    /// An implementation can register an arbitrarily large reservation set on each LR, provided the
    /// reservation set includes all bytes of the addressed data word or doubleword.
    /// An SC can only pair with the most recent LR in program order.
    /// An SC may succeed only if no store from another hart to the reservation set can be
    /// observed to have occurred between the LR and the SC, and if there is no other SC between the
    /// LR and itself in program order.
    /// An SC may succeed only if no write from a device other than a hart to the bytes accessed by
    /// the LR instruction can be observed to have occurred between the LR and SC. Note this LR
    /// might have had a different effective address and data size, but reserved the SC's
    /// address as part of the reservation set.
    ///
    /// \[NOTE\]
    /// ----
    /// Following this model, in systems with memory translation, an SC is allowed to succeed if the
    /// earlier LR reserved the same location using an alias with a different virtual address, but is
    /// also allowed to fail if the virtual address is different.
    ///
    /// To accommodate legacy devices and buses, writes from devices other than RISC-V harts are only
    /// required to invalidate reservations when they overlap the bytes accessed by the LR.
    /// These writes are not required to invalidate the reservation when they access other bytes in
    /// the reservation set.
    /// ----
    ///
    /// Software should not set the _rl_ bit on an LR instruction unless the _aq_ bit is also set.
    /// LR.rl and SC.aq instructions are not guaranteed to provide any stronger ordering than those
    /// with both bits clear, but may result in lower performance.
    ///
    /// # Forms
    /// Assembly: `lr.d xd, xs1`
    /// Rust: `lr_d(rd, rs1, aq, rl)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Memory base register.
    /// - `aq` — Acquire-order bit.
    /// - `rl` — Release-order bit; retained for the existing emitter API.
    pub fn lr_d<T0, T1, T2, T3>(&mut self, rd: T0, rs1: T1, aq: T2, rl: T3)
    where
        Self: LrDEmitter<T0, T1, T2, T3>,
    {
        <Self as LrDEmitter<T0, T1, T2, T3>>::lr_d(self, rd, rs1, aq, rl);
    }
    /// Load reserved word
    ///
    /// Loads a word from the address in rs1, places the sign-extended value in rd,
    /// and registers a _reservation set_  -- a set of bytes that subsumes the bytes in the
    /// addressed word.
    ///
    /// &lt;%- if XLEN == 64 -%&gt;
    /// The 32-bit load result is sign-extended to 64-bits.
    /// &lt;%- end -%&gt;
    ///
    /// The address in rs1 must be naturally aligned to the size of the operand
    /// (_i.e._, eight-byte aligned for doublewords and four-byte aligned for words).
    ///
    /// If the address is not naturally aligned, a `LoadAddressMisaligned` exception or an
    /// `LoadAccessFault` exception will be generated. The access-fault exception can be generated
    /// for a memory access that would otherwise be able to complete except for the misalignment,
    /// if the misaligned access should not be emulated.
    ///
    /// An implementation can register an arbitrarily large reservation set on each LR, provided the
    /// reservation set includes all bytes of the addressed data word or doubleword.
    /// An SC can only pair with the most recent LR in program order.
    /// An SC may succeed only if no store from another hart to the reservation set can be
    /// observed to have occurred between the LR and the SC, and if there is no other SC between the
    /// LR and itself in program order.
    /// An SC may succeed only if no write from a device other than a hart to the bytes accessed by
    /// the LR instruction can be observed to have occurred between the LR and SC. Note this LR
    /// might have had a different effective address and data size, but reserved the SC's
    /// address as part of the reservation set.
    ///
    /// \[NOTE\]
    /// ----
    /// Following this model, in systems with memory translation, an SC is allowed to succeed if the
    /// earlier LR reserved the same location using an alias with a different virtual address, but is
    /// also allowed to fail if the virtual address is different.
    ///
    /// To accommodate legacy devices and buses, writes from devices other than RISC-V harts are only
    /// required to invalidate reservations when they overlap the bytes accessed by the LR.
    /// These writes are not required to invalidate the reservation when they access other bytes in
    /// the reservation set.
    /// ----
    ///
    /// Software should not set the _rl_ bit on an LR instruction unless the _aq_ bit is also set.
    /// LR.rl and SC.aq instructions are not guaranteed to provide any stronger ordering than those
    /// with both bits clear, but may result in lower performance.
    ///
    /// # Forms
    /// Assembly: `lr.w xd, xs1`
    /// Rust: `lr_w(rd, rs1, aq, rl)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Memory base register.
    /// - `aq` — Acquire-order bit.
    /// - `rl` — Release-order bit; retained for the existing emitter API.
    pub fn lr_w<T0, T1, T2, T3>(&mut self, rd: T0, rs1: T1, aq: T2, rl: T3)
    where
        Self: LrWEmitter<T0, T1, T2, T3>,
    {
        <Self as LrWEmitter<T0, T1, T2, T3>>::lr_w(self, rd, rs1, aq, rl);
    }
    /// Load upper immediate
    ///
    /// Load the zero-extended imm into rd.
    ///
    /// # Forms
    /// Assembly: `lui xd, imm`
    /// Rust: `lui(rd, imm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `imm` — Immediate encoding value.
    pub fn lui<T0, T1>(&mut self, rd: T0, imm: T1)
    where
        Self: LuiEmitter<T0, T1>,
    {
        <Self as LuiEmitter<T0, T1>>::lui(self, rd, imm);
    }
    /// Load word
    ///
    /// Load 32 bits of data into register `rd` from an
    /// address formed by adding `rs1` to a signed offset.
    /// Sign extend the result.
    ///
    /// # Forms
    /// Assembly: `lw xd, imm(rs1)`
    /// Rust: `lw(rd, rs1, imm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Memory base register.
    /// - `imm` — Immediate encoding value.
    pub fn lw<T0, T1, T2>(&mut self, rd: T0, rs1: T1, imm: T2)
    where
        Self: LwEmitter<T0, T1, T2>,
    {
        <Self as LwEmitter<T0, T1, T2>>::lw(self, rd, rs1, imm);
    }
    /// Load word unsigned
    ///
    /// Load 64 bits of data into register `rd` from an
    /// address formed by adding `rs1` to a signed offset.
    /// Zero extend the result.
    ///
    /// # Forms
    /// Assembly: `lwu xd, imm(rs1)`
    /// Rust: `lwu(rd, rs1, imm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Memory base register.
    /// - `imm` — Immediate encoding value.
    pub fn lwu<T0, T1, T2>(&mut self, rd: T0, rs1: T1, imm: T2)
    where
        Self: LwuEmitter<T0, T1, T2>,
    {
        <Self as LwuEmitter<T0, T1, T2>>::lwu(self, rd, rs1, imm);
    }
    /// Maximum
    ///
    /// This instruction returns the larger of two signed integers.
    ///
    /// .Software Hint
    /// \[NOTE\]
    /// Calculating the absolute value of a signed integer can be performed using the
    /// following sequence: `neg rD,rS` followed by `max rD,rS,rD. When using this
    /// common sequence, it is suggested that they are scheduled with no intervening
    /// instructions so that implementations that are so optimized can fuse them
    /// together.
    ///
    /// # Forms
    /// Assembly: `max xd, xs1, xs2`
    /// Rust: `max(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn max<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: MaxEmitter<T0, T1, T2>,
    {
        <Self as MaxEmitter<T0, T1, T2>>::max(self, rd, rs1, rs2);
    }
    /// Unsigned maximum
    ///
    /// This instruction returns the larger of two unsigned integers.
    ///
    /// # Forms
    /// Assembly: `maxu xd, xs1, xs2`
    /// Rust: `maxu(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn maxu<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: MaxuEmitter<T0, T1, T2>,
    {
        <Self as MaxuEmitter<T0, T1, T2>>::maxu(self, rd, rs1, rs2);
    }
    /// Minimum
    ///
    /// This instruction returns the smaller of two signed integers.
    ///
    /// # Forms
    /// Assembly: `min xd, xs1, xs2`
    /// Rust: `min(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn min<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: MinEmitter<T0, T1, T2>,
    {
        <Self as MinEmitter<T0, T1, T2>>::min(self, rd, rs1, rs2);
    }
    /// Unsigned minimum
    ///
    /// This instruction returns the smaller of two unsigned integers.
    ///
    /// # Forms
    /// Assembly: `minu xd, xs1, xs2`
    /// Rust: `minu(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn minu<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: MinuEmitter<T0, T1, T2>,
    {
        <Self as MinuEmitter<T0, T1, T2>>::minu(self, rd, rs1, rs2);
    }
    /// RISC-V `mnret` instruction.
    ///
    /// # Forms
    /// Assembly: `mnret mnret`
    /// Rust: `mnret()`
    ///
    /// # Arguments
    pub fn mnret(&mut self)
    where
        Self: MnretEmitter,
    {
        <Self as MnretEmitter>::mnret(self);
    }
    /// RISC-V `mop.r.0` instruction.
    ///
    /// # Forms
    /// Assembly: `mop.r.0 rd rs1`
    /// Rust: `mop_r_0(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn mop_r_0<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: MopR0Emitter<T0, T1>,
    {
        <Self as MopR0Emitter<T0, T1>>::mop_r_0(self, rd, rs1);
    }
    /// RISC-V `mop.r.1` instruction.
    ///
    /// # Forms
    /// Assembly: `mop.r.1 rd rs1`
    /// Rust: `mop_r_1(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn mop_r_1<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: MopR1Emitter<T0, T1>,
    {
        <Self as MopR1Emitter<T0, T1>>::mop_r_1(self, rd, rs1);
    }
    /// RISC-V `mop.r.10` instruction.
    ///
    /// # Forms
    /// Assembly: `mop.r.10 rd rs1`
    /// Rust: `mop_r_10(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn mop_r_10<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: MopR10Emitter<T0, T1>,
    {
        <Self as MopR10Emitter<T0, T1>>::mop_r_10(self, rd, rs1);
    }
    /// RISC-V `mop.r.11` instruction.
    ///
    /// # Forms
    /// Assembly: `mop.r.11 rd rs1`
    /// Rust: `mop_r_11(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn mop_r_11<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: MopR11Emitter<T0, T1>,
    {
        <Self as MopR11Emitter<T0, T1>>::mop_r_11(self, rd, rs1);
    }
    /// RISC-V `mop.r.12` instruction.
    ///
    /// # Forms
    /// Assembly: `mop.r.12 rd rs1`
    /// Rust: `mop_r_12(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn mop_r_12<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: MopR12Emitter<T0, T1>,
    {
        <Self as MopR12Emitter<T0, T1>>::mop_r_12(self, rd, rs1);
    }
    /// RISC-V `mop.r.13` instruction.
    ///
    /// # Forms
    /// Assembly: `mop.r.13 rd rs1`
    /// Rust: `mop_r_13(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn mop_r_13<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: MopR13Emitter<T0, T1>,
    {
        <Self as MopR13Emitter<T0, T1>>::mop_r_13(self, rd, rs1);
    }
    /// RISC-V `mop.r.14` instruction.
    ///
    /// # Forms
    /// Assembly: `mop.r.14 rd rs1`
    /// Rust: `mop_r_14(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn mop_r_14<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: MopR14Emitter<T0, T1>,
    {
        <Self as MopR14Emitter<T0, T1>>::mop_r_14(self, rd, rs1);
    }
    /// RISC-V `mop.r.15` instruction.
    ///
    /// # Forms
    /// Assembly: `mop.r.15 rd rs1`
    /// Rust: `mop_r_15(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn mop_r_15<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: MopR15Emitter<T0, T1>,
    {
        <Self as MopR15Emitter<T0, T1>>::mop_r_15(self, rd, rs1);
    }
    /// RISC-V `mop.r.16` instruction.
    ///
    /// # Forms
    /// Assembly: `mop.r.16 rd rs1`
    /// Rust: `mop_r_16(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn mop_r_16<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: MopR16Emitter<T0, T1>,
    {
        <Self as MopR16Emitter<T0, T1>>::mop_r_16(self, rd, rs1);
    }
    /// RISC-V `mop.r.17` instruction.
    ///
    /// # Forms
    /// Assembly: `mop.r.17 rd rs1`
    /// Rust: `mop_r_17(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn mop_r_17<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: MopR17Emitter<T0, T1>,
    {
        <Self as MopR17Emitter<T0, T1>>::mop_r_17(self, rd, rs1);
    }
    /// RISC-V `mop.r.18` instruction.
    ///
    /// # Forms
    /// Assembly: `mop.r.18 rd rs1`
    /// Rust: `mop_r_18(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn mop_r_18<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: MopR18Emitter<T0, T1>,
    {
        <Self as MopR18Emitter<T0, T1>>::mop_r_18(self, rd, rs1);
    }
    /// RISC-V `mop.r.19` instruction.
    ///
    /// # Forms
    /// Assembly: `mop.r.19 rd rs1`
    /// Rust: `mop_r_19(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn mop_r_19<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: MopR19Emitter<T0, T1>,
    {
        <Self as MopR19Emitter<T0, T1>>::mop_r_19(self, rd, rs1);
    }
    /// RISC-V `mop.r.2` instruction.
    ///
    /// # Forms
    /// Assembly: `mop.r.2 rd rs1`
    /// Rust: `mop_r_2(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn mop_r_2<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: MopR2Emitter<T0, T1>,
    {
        <Self as MopR2Emitter<T0, T1>>::mop_r_2(self, rd, rs1);
    }
    /// RISC-V `mop.r.20` instruction.
    ///
    /// # Forms
    /// Assembly: `mop.r.20 rd rs1`
    /// Rust: `mop_r_20(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn mop_r_20<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: MopR20Emitter<T0, T1>,
    {
        <Self as MopR20Emitter<T0, T1>>::mop_r_20(self, rd, rs1);
    }
    /// RISC-V `mop.r.21` instruction.
    ///
    /// # Forms
    /// Assembly: `mop.r.21 rd rs1`
    /// Rust: `mop_r_21(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn mop_r_21<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: MopR21Emitter<T0, T1>,
    {
        <Self as MopR21Emitter<T0, T1>>::mop_r_21(self, rd, rs1);
    }
    /// RISC-V `mop.r.22` instruction.
    ///
    /// # Forms
    /// Assembly: `mop.r.22 rd rs1`
    /// Rust: `mop_r_22(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn mop_r_22<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: MopR22Emitter<T0, T1>,
    {
        <Self as MopR22Emitter<T0, T1>>::mop_r_22(self, rd, rs1);
    }
    /// RISC-V `mop.r.23` instruction.
    ///
    /// # Forms
    /// Assembly: `mop.r.23 rd rs1`
    /// Rust: `mop_r_23(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn mop_r_23<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: MopR23Emitter<T0, T1>,
    {
        <Self as MopR23Emitter<T0, T1>>::mop_r_23(self, rd, rs1);
    }
    /// RISC-V `mop.r.24` instruction.
    ///
    /// # Forms
    /// Assembly: `mop.r.24 rd rs1`
    /// Rust: `mop_r_24(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn mop_r_24<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: MopR24Emitter<T0, T1>,
    {
        <Self as MopR24Emitter<T0, T1>>::mop_r_24(self, rd, rs1);
    }
    /// RISC-V `mop.r.25` instruction.
    ///
    /// # Forms
    /// Assembly: `mop.r.25 rd rs1`
    /// Rust: `mop_r_25(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn mop_r_25<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: MopR25Emitter<T0, T1>,
    {
        <Self as MopR25Emitter<T0, T1>>::mop_r_25(self, rd, rs1);
    }
    /// RISC-V `mop.r.26` instruction.
    ///
    /// # Forms
    /// Assembly: `mop.r.26 rd rs1`
    /// Rust: `mop_r_26(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn mop_r_26<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: MopR26Emitter<T0, T1>,
    {
        <Self as MopR26Emitter<T0, T1>>::mop_r_26(self, rd, rs1);
    }
    /// RISC-V `mop.r.27` instruction.
    ///
    /// # Forms
    /// Assembly: `mop.r.27 rd rs1`
    /// Rust: `mop_r_27(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn mop_r_27<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: MopR27Emitter<T0, T1>,
    {
        <Self as MopR27Emitter<T0, T1>>::mop_r_27(self, rd, rs1);
    }
    /// RISC-V `mop.r.28` instruction.
    ///
    /// # Forms
    /// Assembly: `mop.r.28 rd rs1`
    /// Rust: `mop_r_28(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn mop_r_28<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: MopR28Emitter<T0, T1>,
    {
        <Self as MopR28Emitter<T0, T1>>::mop_r_28(self, rd, rs1);
    }
    /// RISC-V `mop.r.29` instruction.
    ///
    /// # Forms
    /// Assembly: `mop.r.29 rd rs1`
    /// Rust: `mop_r_29(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn mop_r_29<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: MopR29Emitter<T0, T1>,
    {
        <Self as MopR29Emitter<T0, T1>>::mop_r_29(self, rd, rs1);
    }
    /// RISC-V `mop.r.3` instruction.
    ///
    /// # Forms
    /// Assembly: `mop.r.3 rd rs1`
    /// Rust: `mop_r_3(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn mop_r_3<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: MopR3Emitter<T0, T1>,
    {
        <Self as MopR3Emitter<T0, T1>>::mop_r_3(self, rd, rs1);
    }
    /// RISC-V `mop.r.30` instruction.
    ///
    /// # Forms
    /// Assembly: `mop.r.30 rd rs1`
    /// Rust: `mop_r_30(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn mop_r_30<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: MopR30Emitter<T0, T1>,
    {
        <Self as MopR30Emitter<T0, T1>>::mop_r_30(self, rd, rs1);
    }
    /// RISC-V `mop.r.31` instruction.
    ///
    /// # Forms
    /// Assembly: `mop.r.31 rd rs1`
    /// Rust: `mop_r_31(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn mop_r_31<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: MopR31Emitter<T0, T1>,
    {
        <Self as MopR31Emitter<T0, T1>>::mop_r_31(self, rd, rs1);
    }
    /// RISC-V `mop.r.4` instruction.
    ///
    /// # Forms
    /// Assembly: `mop.r.4 rd rs1`
    /// Rust: `mop_r_4(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn mop_r_4<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: MopR4Emitter<T0, T1>,
    {
        <Self as MopR4Emitter<T0, T1>>::mop_r_4(self, rd, rs1);
    }
    /// RISC-V `mop.r.5` instruction.
    ///
    /// # Forms
    /// Assembly: `mop.r.5 rd rs1`
    /// Rust: `mop_r_5(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn mop_r_5<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: MopR5Emitter<T0, T1>,
    {
        <Self as MopR5Emitter<T0, T1>>::mop_r_5(self, rd, rs1);
    }
    /// RISC-V `mop.r.6` instruction.
    ///
    /// # Forms
    /// Assembly: `mop.r.6 rd rs1`
    /// Rust: `mop_r_6(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn mop_r_6<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: MopR6Emitter<T0, T1>,
    {
        <Self as MopR6Emitter<T0, T1>>::mop_r_6(self, rd, rs1);
    }
    /// RISC-V `mop.r.7` instruction.
    ///
    /// # Forms
    /// Assembly: `mop.r.7 rd rs1`
    /// Rust: `mop_r_7(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn mop_r_7<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: MopR7Emitter<T0, T1>,
    {
        <Self as MopR7Emitter<T0, T1>>::mop_r_7(self, rd, rs1);
    }
    /// RISC-V `mop.r.8` instruction.
    ///
    /// # Forms
    /// Assembly: `mop.r.8 rd rs1`
    /// Rust: `mop_r_8(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn mop_r_8<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: MopR8Emitter<T0, T1>,
    {
        <Self as MopR8Emitter<T0, T1>>::mop_r_8(self, rd, rs1);
    }
    /// RISC-V `mop.r.9` instruction.
    ///
    /// # Forms
    /// Assembly: `mop.r.9 rd rs1`
    /// Rust: `mop_r_9(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn mop_r_9<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: MopR9Emitter<T0, T1>,
    {
        <Self as MopR9Emitter<T0, T1>>::mop_r_9(self, rd, rs1);
    }
    /// RISC-V `mop.rr.0` instruction.
    ///
    /// # Forms
    /// Assembly: `mop.rr.0 rd rs1 rs2`
    /// Rust: `mop_rr_0(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn mop_rr_0<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: MopRr0Emitter<T0, T1, T2>,
    {
        <Self as MopRr0Emitter<T0, T1, T2>>::mop_rr_0(self, rd, rs1, rs2);
    }
    /// RISC-V `mop.rr.1` instruction.
    ///
    /// # Forms
    /// Assembly: `mop.rr.1 rd rs1 rs2`
    /// Rust: `mop_rr_1(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn mop_rr_1<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: MopRr1Emitter<T0, T1, T2>,
    {
        <Self as MopRr1Emitter<T0, T1, T2>>::mop_rr_1(self, rd, rs1, rs2);
    }
    /// RISC-V `mop.rr.2` instruction.
    ///
    /// # Forms
    /// Assembly: `mop.rr.2 rd rs1 rs2`
    /// Rust: `mop_rr_2(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn mop_rr_2<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: MopRr2Emitter<T0, T1, T2>,
    {
        <Self as MopRr2Emitter<T0, T1, T2>>::mop_rr_2(self, rd, rs1, rs2);
    }
    /// RISC-V `mop.rr.3` instruction.
    ///
    /// # Forms
    /// Assembly: `mop.rr.3 rd rs1 rs2`
    /// Rust: `mop_rr_3(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn mop_rr_3<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: MopRr3Emitter<T0, T1, T2>,
    {
        <Self as MopRr3Emitter<T0, T1, T2>>::mop_rr_3(self, rd, rs1, rs2);
    }
    /// RISC-V `mop.rr.4` instruction.
    ///
    /// # Forms
    /// Assembly: `mop.rr.4 rd rs1 rs2`
    /// Rust: `mop_rr_4(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn mop_rr_4<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: MopRr4Emitter<T0, T1, T2>,
    {
        <Self as MopRr4Emitter<T0, T1, T2>>::mop_rr_4(self, rd, rs1, rs2);
    }
    /// RISC-V `mop.rr.5` instruction.
    ///
    /// # Forms
    /// Assembly: `mop.rr.5 rd rs1 rs2`
    /// Rust: `mop_rr_5(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn mop_rr_5<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: MopRr5Emitter<T0, T1, T2>,
    {
        <Self as MopRr5Emitter<T0, T1, T2>>::mop_rr_5(self, rd, rs1, rs2);
    }
    /// RISC-V `mop.rr.6` instruction.
    ///
    /// # Forms
    /// Assembly: `mop.rr.6 rd rs1 rs2`
    /// Rust: `mop_rr_6(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn mop_rr_6<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: MopRr6Emitter<T0, T1, T2>,
    {
        <Self as MopRr6Emitter<T0, T1, T2>>::mop_rr_6(self, rd, rs1, rs2);
    }
    /// RISC-V `mop.rr.7` instruction.
    ///
    /// # Forms
    /// Assembly: `mop.rr.7 rd rs1 rs2`
    /// Rust: `mop_rr_7(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn mop_rr_7<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: MopRr7Emitter<T0, T1, T2>,
    {
        <Self as MopRr7Emitter<T0, T1, T2>>::mop_rr_7(self, rd, rs1, rs2);
    }
    /// Machine Exception Return
    ///
    /// Returns from an exception in M-mode.
    ///
    /// # Forms
    /// Assembly: `mret ""`
    /// Rust: `mret()`
    ///
    /// # Arguments
    pub fn mret(&mut self)
    where
        Self: MretEmitter,
    {
        <Self as MretEmitter>::mret(self);
    }
    /// Signed multiply
    ///
    /// MUL performs an XLEN-bitxXLEN-bit multiplication of `rs1` by `rs2` and places the lower
    /// XLEN bits in the destination register.
    /// Any overflow is thrown away.
    ///
    /// \[NOTE\]
    /// If both the high and low bits of the same product are required, then the recommended code
    /// sequence is:
    /// MULH\[\[S\]U\] rdh, rs1, rs2; MUL rdl, rs1, rs2
    /// (source register specifiers must be in same order and rdh cannot be the same as rs1 or rs2).
    /// Microarchitectures can then fuse these into a single multiply operation instead of
    /// performing two separate multiplies.
    ///
    /// # Forms
    /// Assembly: `mul xd, xs1, xs2`
    /// Rust: `mul(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn mul<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: MulEmitter<T0, T1, T2>,
    {
        <Self as MulEmitter<T0, T1, T2>>::mul(self, rd, rs1, rs2);
    }
    /// Signed multiply high
    ///
    /// Multiply the signed values in rs1 to rs2, and store the upper half of the result in rd.
    /// The lower half is thrown away.
    ///
    /// If both the upper and lower halves are needed, it suggested to use the sequence:
    ///
    /// ---
    ///   mulh rdh, rs1, rs2
    ///   mul  rdl, rs1, rs2
    /// ---
    ///
    /// Microarchitectures may look for that sequence and fuse the operations.
    ///
    /// # Forms
    /// Assembly: `mulh xd, xs1, xs2`
    /// Rust: `mulh(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn mulh<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: MulhEmitter<T0, T1, T2>,
    {
        <Self as MulhEmitter<T0, T1, T2>>::mulh(self, rd, rs1, rs2);
    }
    /// Signed/unsigned multiply high
    ///
    /// Multiply the signed value in rs1 by the unsigned value in rs2, and store the upper half of the result in rd.
    /// The lower half is thrown away.
    ///
    /// If both the upper and lower halves are needed, it suggested to use the sequence:
    ///
    /// ---
    ///   mulhsu rdh, rs1, rs2
    ///   mul    rdl, rs1, rs2
    /// ---
    ///
    /// Microarchitectures may look for that sequence and fuse the operations.
    ///
    /// # Forms
    /// Assembly: `mulhsu xd, xs1, xs2`
    /// Rust: `mulhsu(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn mulhsu<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: MulhsuEmitter<T0, T1, T2>,
    {
        <Self as MulhsuEmitter<T0, T1, T2>>::mulhsu(self, rd, rs1, rs2);
    }
    /// Unsigned multiply high
    ///
    /// Multiply the unsigned values in rs1 to rs2, and store the upper half of the result in rd.
    /// The lower half is thrown away.
    ///
    /// If both the upper and lower halves are needed, it suggested to use the sequence:
    ///
    /// ---
    ///   mulhu rdh, rs1, rs2
    ///   mul   rdl, rs1, rs2
    /// ---
    ///
    /// Microarchitectures may look for that sequence and fuse the operations.
    ///
    /// # Forms
    /// Assembly: `mulhu xd, xs1, xs2`
    /// Rust: `mulhu(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn mulhu<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: MulhuEmitter<T0, T1, T2>,
    {
        <Self as MulhuEmitter<T0, T1, T2>>::mulhu(self, rd, rs1, rs2);
    }
    /// Signed 32-bit multiply
    ///
    /// Multiplies the lower 32 bits of the source registers, placing the sign-extension of the
    /// lower 32 bits of the result into the destination register.
    ///
    /// Any overflow is thrown away.
    ///
    /// \[NOTE\]
    /// In RV64, MUL can be used to obtain the upper 32 bits of the 64-bit product,
    /// but signed arguments must be proper 32-bit signed values, whereas unsigned arguments
    /// must have their upper 32 bits clear. If the arguments are not known to be sign- or zero-extended,
    /// an alternative is to shift both arguments left by 32 bits, then use MULH\[\[S\]U\].
    ///
    /// # Forms
    /// Assembly: `mulw xd, xs1, xs2`
    /// Rust: `mulw(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn mulw<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: MulwEmitter<T0, T1, T2>,
    {
        <Self as MulwEmitter<T0, T1, T2>>::mulw(self, rd, rs1, rs2);
    }
    /// RISC-V `mv` instruction.
    ///
    /// # Forms
    /// Assembly: `mv rd rs1`
    /// Rust: `mv(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn mv<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: MvEmitter<T0, T1>,
    {
        <Self as MvEmitter<T0, T1>>::mv(self, rd, rs1);
    }
    /// RISC-V `neg` instruction.
    ///
    /// # Forms
    /// Assembly: `neg rd rs1`
    /// Rust: `neg(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn neg<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: NegEmitter<T0, T1>,
    {
        <Self as NegEmitter<T0, T1>>::neg(self, rd, rs1);
    }
    /// RISC-V `nop` instruction.
    ///
    /// # Forms
    /// Assembly: `nop`
    /// Rust: `nop()`
    ///
    /// # Arguments
    pub fn nop(&mut self)
    where
        Self: NopEmitter,
    {
        <Self as NopEmitter>::nop(self);
    }
    /// RISC-V `ntl.all` instruction.
    ///
    /// # Forms
    /// Assembly: `ntl.all`
    /// Rust: `ntl_all()`
    ///
    /// # Arguments
    pub fn ntl_all(&mut self)
    where
        Self: NtlAllEmitter,
    {
        <Self as NtlAllEmitter>::ntl_all(self);
    }
    /// RISC-V `ntl.p1` instruction.
    ///
    /// # Forms
    /// Assembly: `ntl.p1`
    /// Rust: `ntl_p1()`
    ///
    /// # Arguments
    pub fn ntl_p1(&mut self)
    where
        Self: NtlP1Emitter,
    {
        <Self as NtlP1Emitter>::ntl_p1(self);
    }
    /// RISC-V `ntl.pall` instruction.
    ///
    /// # Forms
    /// Assembly: `ntl.pall`
    /// Rust: `ntl_pall()`
    ///
    /// # Arguments
    pub fn ntl_pall(&mut self)
    where
        Self: NtlPallEmitter,
    {
        <Self as NtlPallEmitter>::ntl_pall(self);
    }
    /// RISC-V `ntl.s1` instruction.
    ///
    /// # Forms
    /// Assembly: `ntl.s1`
    /// Rust: `ntl_s1()`
    ///
    /// # Arguments
    pub fn ntl_s1(&mut self)
    where
        Self: NtlS1Emitter,
    {
        <Self as NtlS1Emitter>::ntl_s1(self);
    }
    /// Or
    ///
    /// Or rs1 with rs2, and store the result in rd
    ///
    /// # Forms
    /// Assembly: `or xd, xs1, xs2`
    /// Rust: `or(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn or<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: OrEmitter<T0, T1, T2>,
    {
        <Self as OrEmitter<T0, T1, T2>>::or(self, rd, rs1, rs2);
    }
    /// Bitware OR-combine, byte granule
    ///
    /// Combines the bits within each byte using bitwise logical OR. This sets the bits
    /// of each byte in the result rd to all zeros if no bit within the respective byte
    /// of rs is set, or to all ones if any bit within the respective byte of rs is set.
    ///
    /// # Forms
    /// Assembly: `orc.b xd, xs1, xs2`
    /// Rust: `orc_b(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn orc_b<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: OrcBEmitter<T0, T1>,
    {
        <Self as OrcBEmitter<T0, T1>>::orc_b(self, rd, rs1);
    }
    /// Or immediate
    ///
    /// Or an immediate to the value in rs1, and store the result in rd
    ///
    /// # Forms
    /// Assembly: `ori xd, xs1, imm`
    /// Rust: `ori(rd, rs1, imm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `imm` — Immediate encoding value.
    pub fn ori<T0, T1, T2>(&mut self, rd: T0, rs1: T1, imm: T2)
    where
        Self: OriEmitter<T0, T1, T2>,
    {
        <Self as OriEmitter<T0, T1, T2>>::ori(self, rd, rs1, imm);
    }
    /// OR with inverted operand
    ///
    /// This instruction performs the bitwise logical OR operation between rs1 and the bitwise inversion of rs2.
    ///
    /// # Forms
    /// Assembly: `orn xd, xs1, xs2`
    /// Rust: `orn(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn orn<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: OrnEmitter<T0, T1, T2>,
    {
        <Self as OrnEmitter<T0, T1, T2>>::orn(self, rd, rs1, rs2);
    }
    /// RISC-V `pack` instruction.
    ///
    /// # Forms
    /// Assembly: `pack xd, xs1, xs2`
    /// Rust: `pack(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn pack<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: PackEmitter<T0, T1, T2>,
    {
        <Self as PackEmitter<T0, T1, T2>>::pack(self, rd, rs1, rs2);
    }
    /// RISC-V `packh` instruction.
    ///
    /// # Forms
    /// Assembly: `packh xd, xs1, xs2`
    /// Rust: `packh(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn packh<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: PackhEmitter<T0, T1, T2>,
    {
        <Self as PackhEmitter<T0, T1, T2>>::packh(self, rd, rs1, rs2);
    }
    /// RISC-V `packw` instruction.
    ///
    /// # Forms
    /// Assembly: `packw xd, xs1, xs2`
    /// Rust: `packw(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn packw<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: PackwEmitter<T0, T1, T2>,
    {
        <Self as PackwEmitter<T0, T1, T2>>::packw(self, rd, rs1, rs2);
    }
    /// RISC-V `pause` instruction.
    ///
    /// # Forms
    /// Assembly: `pause`
    /// Rust: `pause()`
    ///
    /// # Arguments
    pub fn pause(&mut self)
    where
        Self: PauseEmitter,
    {
        <Self as PauseEmitter>::pause(self);
    }
    /// RISC-V `prefetch.i` instruction.
    ///
    /// # Forms
    /// Assembly: `prefetch.i rs1 imm12lohi`
    /// Rust: `prefetch_i(rs1, imm)`
    ///
    /// # Arguments
    /// - `rs1` — Source register.
    /// - `imm` — Immediate encoding value.
    pub fn prefetch_i<T0, T1>(&mut self, rs1: T0, imm: T1)
    where
        Self: PrefetchIEmitter<T0, T1>,
    {
        <Self as PrefetchIEmitter<T0, T1>>::prefetch_i(self, rs1, imm);
    }
    /// RISC-V `prefetch.r` instruction.
    ///
    /// # Forms
    /// Assembly: `prefetch.r rs1 imm12lohi`
    /// Rust: `prefetch_r(rs1, imm)`
    ///
    /// # Arguments
    /// - `rs1` — Source register.
    /// - `imm` — Immediate encoding value.
    pub fn prefetch_r<T0, T1>(&mut self, rs1: T0, imm: T1)
    where
        Self: PrefetchREmitter<T0, T1>,
    {
        <Self as PrefetchREmitter<T0, T1>>::prefetch_r(self, rs1, imm);
    }
    /// RISC-V `prefetch.w` instruction.
    ///
    /// # Forms
    /// Assembly: `prefetch.w rs1 imm12lohi`
    /// Rust: `prefetch_w(rs1, imm)`
    ///
    /// # Arguments
    /// - `rs1` — Source register.
    /// - `imm` — Immediate encoding value.
    pub fn prefetch_w<T0, T1>(&mut self, rs1: T0, imm: T1)
    where
        Self: PrefetchWEmitter<T0, T1>,
    {
        <Self as PrefetchWEmitter<T0, T1>>::prefetch_w(self, rs1, imm);
    }
    /// RISC-V `rdcycle` instruction.
    ///
    /// # Forms
    /// Assembly: `rdcycle rd`
    /// Rust: `rdcycle(rd)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    pub fn rdcycle<T0>(&mut self, rd: T0)
    where
        Self: RdcycleEmitter<T0>,
    {
        <Self as RdcycleEmitter<T0>>::rdcycle(self, rd);
    }
    /// RISC-V `rdcycleh` instruction.
    ///
    /// # Forms
    /// Assembly: `rdcycleh rd`
    /// Rust: `rdcycleh(rd)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    pub fn rdcycleh<T0>(&mut self, rd: T0)
    where
        Self: RdcyclehEmitter<T0>,
    {
        <Self as RdcyclehEmitter<T0>>::rdcycleh(self, rd);
    }
    /// RISC-V `rdinstret` instruction.
    ///
    /// # Forms
    /// Assembly: `rdinstret rd`
    /// Rust: `rdinstret(rd)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    pub fn rdinstret<T0>(&mut self, rd: T0)
    where
        Self: RdinstretEmitter<T0>,
    {
        <Self as RdinstretEmitter<T0>>::rdinstret(self, rd);
    }
    /// RISC-V `rdinstreth` instruction.
    ///
    /// # Forms
    /// Assembly: `rdinstreth rd`
    /// Rust: `rdinstreth(rd)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    pub fn rdinstreth<T0>(&mut self, rd: T0)
    where
        Self: RdinstrethEmitter<T0>,
    {
        <Self as RdinstrethEmitter<T0>>::rdinstreth(self, rd);
    }
    /// RISC-V `rdtime` instruction.
    ///
    /// # Forms
    /// Assembly: `rdtime rd`
    /// Rust: `rdtime(rd)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    pub fn rdtime<T0>(&mut self, rd: T0)
    where
        Self: RdtimeEmitter<T0>,
    {
        <Self as RdtimeEmitter<T0>>::rdtime(self, rd);
    }
    /// RISC-V `rdtimeh` instruction.
    ///
    /// # Forms
    /// Assembly: `rdtimeh rd`
    /// Rust: `rdtimeh(rd)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    pub fn rdtimeh<T0>(&mut self, rd: T0)
    where
        Self: RdtimehEmitter<T0>,
    {
        <Self as RdtimehEmitter<T0>>::rdtimeh(self, rd);
    }
    /// Signed remainder
    ///
    /// Calculate the remainder of signed division of rs1 by rs2, and store the result in rd.
    ///
    /// If the value in register rs2 is zero, write the value in rs1 into rd;
    ///
    /// If the result of the division overflows, write zero into rd;
    ///
    /// # Forms
    /// Assembly: `rem xd, xs1, xs2`
    /// Rust: `rem(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn rem<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: RemEmitter<T0, T1, T2>,
    {
        <Self as RemEmitter<T0, T1, T2>>::rem(self, rd, rs1, rs2);
    }
    /// Unsigned remainder
    ///
    /// Calculate the remainder of unsigned division of rs1 by rs2, and store the result in rd.
    ///
    /// # Forms
    /// Assembly: `remu xd, xs1, xs2`
    /// Rust: `remu(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn remu<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: RemuEmitter<T0, T1, T2>,
    {
        <Self as RemuEmitter<T0, T1, T2>>::remu(self, rd, rs1, rs2);
    }
    /// Unsigned 32-bit remainder
    ///
    /// Calculate the remainder of unsigned division of the 32-bit values in rs1 by rs2,
    /// and store the sign-extended result in rd.
    ///
    /// If the value in rs2 is zero, rd gets the sign-extended value in rs1.
    ///
    /// # Forms
    /// Assembly: `remuw xd, xs1, xs2`
    /// Rust: `remuw(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn remuw<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: RemuwEmitter<T0, T1, T2>,
    {
        <Self as RemuwEmitter<T0, T1, T2>>::remuw(self, rd, rs1, rs2);
    }
    /// Signed 32-bit remainder
    ///
    /// Calculate the remainder of signed division of the 32-bit values rs1 by rs2,
    /// and store the sign-extended result in rd.
    ///
    /// If the value in register rs2 is zero, write the sign-extended 32-bit value in rs1 into rd;
    ///
    /// If the result of the division overflows, write zero into rd;
    ///
    /// # Forms
    /// Assembly: `remw xd, xs1, xs2`
    /// Rust: `remw(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn remw<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: RemwEmitter<T0, T1, T2>,
    {
        <Self as RemwEmitter<T0, T1, T2>>::remw(self, rd, rs1, rs2);
    }
    /// RISC-V `ret` instruction.
    ///
    /// # Forms
    /// Assembly: `ret`
    /// Rust: `ret()`
    ///
    /// # Arguments
    pub fn ret(&mut self)
    where
        Self: RetEmitter,
    {
        <Self as RetEmitter>::ret(self);
    }
    /// Byte-reverse register (RV64 encoding)
    ///
    /// This instruction reverses the order of the bytes in rs1.
    ///
    /// \[NOTE\]
    /// The rev8 mnemonic corresponds to different instruction encodings in RV32 and RV64.
    ///
    /// \[NOTE\]
    /// The byte-reverse operation is only available for the full register width. To emulate word-sized
    /// and halfword-sized byte-reversal, perform a `rev8 rd,rs` followed by a `srai rd,rd,K`, where K
    /// is XLEN-32 and XLEN-16, respectively.
    ///
    /// # Forms
    /// Assembly: `rev8 xd, xs1`
    /// Rust: `rev8(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn rev8<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: Rev8Emitter<T0, T1>,
    {
        <Self as Rev8Emitter<T0, T1>>::rev8(self, rd, rs1);
    }
    /// Byte-reverse register (RV64 encoding)
    ///
    /// This instruction reverses the order of the bytes in rs1.
    ///
    /// \[NOTE\]
    /// The rev8 mnemonic corresponds to different instruction encodings in RV32 and RV64.
    ///
    /// \[NOTE\]
    /// The byte-reverse operation is only available for the full register width. To emulate word-sized
    /// and halfword-sized byte-reversal, perform a `rev8 rd,rs` followed by a `srai rd,rd,K`, where K
    /// is XLEN-32 and XLEN-16, respectively.
    ///
    /// # Forms
    /// Assembly: `rev8.rv32 xd, xs1`
    /// Rust: `rev8_rv32(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn rev8_rv32<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: Rev8Rv32Emitter<T0, T1>,
    {
        <Self as Rev8Rv32Emitter<T0, T1>>::rev8_rv32(self, rd, rs1);
    }
    /// Rotate left (Register)
    ///
    /// This instruction performs a rotate left of rs1 by the amount in least-significant `log2(XLEN)` bits of rs2.
    ///
    /// # Forms
    /// Assembly: `rol xd, xs1, xs2`
    /// Rust: `rol(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn rol<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: RolEmitter<T0, T1, T2>,
    {
        <Self as RolEmitter<T0, T1, T2>>::rol(self, rd, rs1, rs2);
    }
    /// Rotate left word (Register)
    ///
    /// This instruction performs a rotate left of the least-significant word of rs1 by the amount in least-significant 5 bits of rs2.
    /// The resulting word value is sign-extended by copying bit 31 to all of the more-significant bits.
    ///
    /// # Forms
    /// Assembly: `rolw xd, xs1, xs2`
    /// Rust: `rolw(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn rolw<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: RolwEmitter<T0, T1, T2>,
    {
        <Self as RolwEmitter<T0, T1, T2>>::rolw(self, rd, rs1, rs2);
    }
    /// Rotate right (Register)
    ///
    /// This instruction performs a rotate right of rs1 by the amount in least-significant `log2(XLEN)` bits of rs2.
    ///
    /// # Forms
    /// Assembly: `ror xd, xs1, xs2`
    /// Rust: `ror(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn ror<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: RorEmitter<T0, T1, T2>,
    {
        <Self as RorEmitter<T0, T1, T2>>::ror(self, rd, rs1, rs2);
    }
    /// Rotate right (Immediate)
    ///
    /// This instruction performs a rotate right of rs1 by the amount in the least-significant log2(XLEN) bits of shamt.
    /// For RV32, the encodings corresponding to shamt\[5\]=1 are reserved.
    ///
    /// # Forms
    /// Assembly: `rori xd, xs1, shamt`
    /// Rust: `rori(rd, rs1, shamtd)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `shamtd` — Immediate encoding value.
    pub fn rori<T0, T1, T2>(&mut self, rd: T0, rs1: T1, shamtd: T2)
    where
        Self: RoriEmitter<T0, T1, T2>,
    {
        <Self as RoriEmitter<T0, T1, T2>>::rori(self, rd, rs1, shamtd);
    }
    /// Rotate right (Immediate)
    ///
    /// This instruction performs a rotate right of rs1 by the amount in the least-significant log2(XLEN) bits of shamt.
    /// For RV32, the encodings corresponding to shamt\[5\]=1 are reserved.
    ///
    /// # Forms
    /// Assembly: `rori.rv32 xd, xs1, shamt`
    /// Rust: `rori_rv32(rd, rs1, shamtw)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `shamtw` — Immediate encoding value.
    pub fn rori_rv32<T0, T1, T2>(&mut self, rd: T0, rs1: T1, shamtw: T2)
    where
        Self: RoriRv32Emitter<T0, T1, T2>,
    {
        <Self as RoriRv32Emitter<T0, T1, T2>>::rori_rv32(self, rd, rs1, shamtw);
    }
    /// Rotate right word (Immediate)
    ///
    /// This instruction performs a rotate right on the least-significant word of rs1 by the amount in
    /// the least-significant log2(XLEN) bits of shamt. The resulting word value is sign-extended by
    /// copying bit 31 to all of the more-significant bits.
    ///
    /// # Forms
    /// Assembly: `roriw xd, xs1, shamt`
    /// Rust: `roriw(rd, rs1, shamtw)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `shamtw` — Immediate encoding value.
    pub fn roriw<T0, T1, T2>(&mut self, rd: T0, rs1: T1, shamtw: T2)
    where
        Self: RoriwEmitter<T0, T1, T2>,
    {
        <Self as RoriwEmitter<T0, T1, T2>>::roriw(self, rd, rs1, shamtw);
    }
    /// Rotate right word (Register)
    ///
    /// This instruction performs a rotate right on the least-significant word of rs1 by the amount in
    /// least-significant 5 bits of rs2. The resultant word is sign-extended by copying bit 31 to all
    /// of the more-significant bits.
    ///
    /// # Forms
    /// Assembly: `rorw xd, xs1, xs2`
    /// Rust: `rorw(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn rorw<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: RorwEmitter<T0, T1, T2>,
    {
        <Self as RorwEmitter<T0, T1, T2>>::rorw(self, rd, rs1, rs2);
    }
    /// Store byte
    ///
    /// Store 8 bits of data from register `rs2` to an
    /// address formed by adding `rs1` to a signed offset.
    ///
    /// # Forms
    /// Assembly: `sb xs2, imm(xs1)`
    /// Rust: `sb(rs1, rs2, imm)`
    ///
    /// # Arguments
    /// - `rs1` — Memory base register.
    /// - `rs2` — Source register.
    /// - `imm` — Immediate encoding value.
    pub fn sb<T0, T1, T2>(&mut self, rs1: T0, rs2: T1, imm: T2)
    where
        Self: SbEmitter<T0, T1, T2>,
    {
        <Self as SbEmitter<T0, T1, T2>>::sb(self, rs1, rs2, imm);
    }
    /// RISC-V `sbreak` instruction.
    ///
    /// # Forms
    /// Assembly: `sbreak`
    /// Rust: `sbreak()`
    ///
    /// # Arguments
    pub fn sbreak(&mut self)
    where
        Self: SbreakEmitter,
    {
        <Self as SbreakEmitter>::sbreak(self);
    }
    /// Store conditional doubleword
    ///
    /// `sc.d` conditionally writes a doubleword in _rs2_ to the address in _rs1_:
    /// the `sc.d` succeeds only if the reservation is still valid and the
    /// reservation set contains the bytes being written. If the `sc.d` succeeds,
    /// the instruction writes the doubleword in _rs2_ to memory, and it writes zero to _rd_.
    /// If the `sc.d` fails, the instruction does not write to memory, and it writes a
    /// nonzero value to _rd_. For the purposes of memory protection, a failed `sc.d`
    /// may be treated like a store. Regardless of success or failure, executing an
    /// `sc.d` instruction invalidates any reservation held by this hart.
    ///
    /// The failure code with value 1 encodes an unspecified failure.
    /// Other failure codes are reserved at this time.
    /// Portable software should only assume the failure code will be non-zero.
    ///
    /// The address held in _rs1_ must be naturally aligned to the size of the operand
    /// (_i.e._, eight-byte aligned).
    /// If the address is not naturally aligned, an address-misaligned exception or an
    /// access-fault exception will be generated.
    /// The access-fault exception can be generated for a memory access that would otherwise
    /// be able to complete except for the misalignment,
    /// if the misaligned access should not be emulated.
    ///
    /// \[NOTE\]
    /// --
    /// Emulating misaligned LR/SC sequences is impractical in most systems.
    ///
    /// Misaligned LR/SC sequences also raise the possibility of accessing multiple
    /// reservation sets at once, which present definitions do not provide for.
    /// --
    ///
    /// An implementation can register an arbitrarily large reservation set on each LR,
    /// provided the reservation set includes all bytes of the addressed data word or
    /// doubleword.
    /// An SC can only pair with the most recent LR in program order.
    /// An SC may succeed only if no store from another hart to the reservation set
    /// can be observed to have occurred between the LR and the SC,
    /// and if there is no other SC between the LR and itself in program order.
    /// An SC may succeed only if no write from a device other than a hart to the bytes
    /// accessed by the LR instruction can be observed to have occurred between the LR
    /// and SC.
    /// Note this LR might have had a different effective address and data size,
    /// but reserved the SC's address as part of the reservation set.
    ///
    /// \[NOTE\]
    /// ----
    /// Following this model, in systems with memory translation, an SC is allowed to succeed if the
    /// earlier LR reserved the same location using an alias with a different virtual address, but is
    /// also allowed to fail if the virtual address is different.
    ///
    /// To accommodate legacy devices and buses, writes from devices other than RISC-V harts are only
    /// required to invalidate reservations when they overlap the bytes accessed by the LR.
    /// These writes are not required to invalidate the reservation when they access other bytes in
    /// the reservation set.
    /// ----
    ///
    /// The SC must fail if the address is not within the reservation set of the most
    /// recent LR in program order.
    /// The SC must fail if a store to the reservation set from another hart can be
    /// observed to occur between the LR and SC.
    /// The SC must fail if a write from some other device to the bytes accessed by the
    /// LR can be observed to occur between the LR and SC.
    /// (If such a device writes the reservation set but does not write the bytes accessed
    /// by the LR, the SC may or may not fail.)
    /// An SC must fail if there is another SC (to any address) between the LR and the SC
    /// in program order.
    /// The precise statement of the atomicity requirements for successful LR/SC sequences
    /// is defined by the Atomicity Axiom of the memory model.
    ///
    /// \[NOTE\]
    /// --
    /// The platform should provide a means to determine the size and shape of the reservation set.
    ///
    /// A platform specification may constrain the size and shape of the reservation set.
    ///
    /// A store-conditional instruction to a scratch word of memory should be used to forcibly invalidate any existing load reservation:
    ///
    ///   * during a preemptive context switch, and
    ///   * if necessary when changing virtual to physical address mappings, such as when migrating pages that might contain an active reservation.
    ///
    /// The invalidation of a hart's reservation when it executes an LR or SC imply that a hart can only hold one reservation at a time, and that an SC can only pair with the most recent LR, and LR with the next following SC, in program order. This is a restriction to the Atomicity Axiom in Section 18.1 that ensures software runs correctly on expected common implementations that operate in this manner.
    /// --
    ///
    /// An SC instruction can never be observed by another RISC-V hart before the LR instruction that established the reservation.
    ///
    /// \[NOTE\]
    /// --
    /// The LR/SC sequence can be given acquire semantics by setting the aq bit on the LR instruction. The LR/SC sequence can be given release semantics by by setting the rl bit on the SC instruction. Assuming suitable mappings for other atomic operations, setting the aq bit on the LR instruction, and setting the rl bit on the SC instruction makes the LR/SC sequence sequentially consistent in the C++ memory_order_seq_cst sense. Such a sequence does not act as a fence for ordering ordinary load and store instructions before and after the sequence. Specific instruction mappings for other C++ atomic operations, or stronger notions of "sequential consistency", may require both bits to be set on either or both of the LR or SC instruction.
    ///
    /// If neither bit is set on either LR or SC, the LR/SC sequence can be observed to occur before or after surrounding memory operations from the same RISC-V hart. This can be appropriate when the LR/SC sequence is used to implement a parallel reduction operation.
    /// --
    ///
    /// Software should not set the _rl_ bit on an LR instruction unless the _aq_ bit is also set.
    /// LR.rl and SC.aq instructions are not guaranteed to provide any stronger ordering than those
    /// with both bits clear, but may result in lower performance.
    ///
    /// # Forms
    /// Assembly: `sc.d xd, xs2, xs1`
    /// Rust: `sc_d(rd, rs1, rs2, aq, rl)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Memory base register.
    /// - `rs2` — Source register.
    /// - `aq` — Acquire-order bit.
    /// - `rl` — Release-order bit; retained for the existing emitter API.
    pub fn sc_d<T0, T1, T2, T3, T4>(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4)
    where
        Self: ScDEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as ScDEmitter<T0, T1, T2, T3, T4>>::sc_d(self, rd, rs1, rs2, aq, rl);
    }
    /// Store conditional word
    ///
    /// `sc.w` conditionally writes a word in _rs2_ to the address in _rs1_:
    /// the `sc.w` succeeds only if the reservation is still valid and the
    /// reservation set contains the bytes being written. If the `sc.w` succeeds,
    /// the instruction writes the word in _rs2_ to memory, and it writes zero to _rd_.
    /// If the `sc.w` fails, the instruction does not write to memory, and it writes a
    /// nonzero value to _rd_. For the purposes of memory protection, a failed `sc.w`
    /// may be treated like a store. Regardless of success or failure, executing an
    /// `sc.w` instruction invalidates any reservation held by this hart.
    ///
    /// &lt;%- if XLEN == 64 -%&gt;
    /// \[NOTE\]
    /// If a value other than 0 or 1 is defined as a result for `sc.w`, the value will before
    /// sign-extended into _rd_.
    /// &lt;%- end -%&gt;
    ///
    /// The failure code with value 1 encodes an unspecified failure.
    /// Other failure codes are reserved at this time.
    /// Portable software should only assume the failure code will be non-zero.
    ///
    /// The address held in _rs1_ must be naturally aligned to the size of the operand
    /// (_i.e._, eight-byte aligned for doublewords and four-byte aligned for words).
    /// If the address is not naturally aligned, an address-misaligned exception or an
    /// access-fault exception will be generated.
    /// The access-fault exception can be generated for a memory access that would otherwise
    /// be able to complete except for the misalignment,
    /// if the misaligned access should not be emulated.
    ///
    /// \[NOTE\]
    /// --
    /// Emulating misaligned LR/SC sequences is impractical in most systems.
    ///
    /// Misaligned LR/SC sequences also raise the possibility of accessing multiple
    /// reservation sets at once, which present definitions do not provide for.
    /// --
    ///
    /// An implementation can register an arbitrarily large reservation set on each LR,
    /// provided the reservation set includes all bytes of the addressed data word or
    /// doubleword.
    /// An SC can only pair with the most recent LR in program order.
    /// An SC may succeed only if no store from another hart to the reservation set
    /// can be observed to have occurred between the LR and the SC,
    /// and if there is no other SC between the LR and itself in program order.
    /// An SC may succeed only if no write from a device other than a hart to the bytes
    /// accessed by the LR instruction can be observed to have occurred between the LR
    /// and SC.
    /// Note this LR might have had a different effective address and data size,
    /// but reserved the SC's address as part of the reservation set.
    ///
    /// \[NOTE\]
    /// ----
    /// Following this model, in systems with memory translation, an SC is allowed to succeed if the
    /// earlier LR reserved the same location using an alias with a different virtual address, but is
    /// also allowed to fail if the virtual address is different.
    ///
    /// To accommodate legacy devices and buses, writes from devices other than RISC-V harts are only
    /// required to invalidate reservations when they overlap the bytes accessed by the LR.
    /// These writes are not required to invalidate the reservation when they access other bytes in
    /// the reservation set.
    /// ----
    ///
    /// The SC must fail if the address is not within the reservation set of the most
    /// recent LR in program order.
    /// The SC must fail if a store to the reservation set from another hart can be
    /// observed to occur between the LR and SC.
    /// The SC must fail if a write from some other device to the bytes accessed by the
    /// LR can be observed to occur between the LR and SC.
    /// (If such a device writes the reservation set but does not write the bytes accessed
    /// by the LR, the SC may or may not fail.)
    /// An SC must fail if there is another SC (to any address) between the LR and the SC
    /// in program order.
    /// The precise statement of the atomicity requirements for successful LR/SC sequences
    /// is defined by the Atomicity Axiom of the memory model.
    ///
    /// \[NOTE\]
    /// --
    /// The platform should provide a means to determine the size and shape of the reservation set.
    ///
    /// A platform specification may constrain the size and shape of the reservation set.
    ///
    /// A store-conditional instruction to a scratch word of memory should be used to forcibly invalidate any existing load reservation:
    ///
    ///   * during a preemptive context switch, and
    ///   * if necessary when changing virtual to physical address mappings, such as when migrating pages that might contain an active reservation.
    ///
    /// The invalidation of a hart's reservation when it executes an LR or SC imply that a hart can only hold one reservation at a time, and that an SC can only pair with the most recent LR, and LR with the next following SC, in program order. This is a restriction to the Atomicity Axiom in Section 18.1 that ensures software runs correctly on expected common implementations that operate in this manner.
    /// --
    ///
    /// An SC instruction can never be observed by another RISC-V hart before the LR instruction that established the reservation.
    ///
    /// \[NOTE\]
    /// --
    /// The LR/SC sequence can be given acquire semantics by setting the aq bit on the LR instruction. The LR/SC sequence can be given release semantics by by setting the rl bit on the SC instruction. Assuming suitable mappings for other atomic operations, setting the aq bit on the LR instruction, and setting the rl bit on the SC instruction makes the LR/SC sequence sequentially consistent in the C++ memory_order_seq_cst sense. Such a sequence does not act as a fence for ordering ordinary load and store instructions before and after the sequence. Specific instruction mappings for other C++ atomic operations, or stronger notions of "sequential consistency", may require both bits to be set on either or both of the LR or SC instruction.
    ///
    /// If neither bit is set on either LR or SC, the LR/SC sequence can be observed to occur before or after surrounding memory operations from the same RISC-V hart. This can be appropriate when the LR/SC sequence is used to implement a parallel reduction operation.
    /// --
    ///
    /// Software should not set the _rl_ bit on an LR instruction unless the _aq_ bit is also set.
    /// LR.rl and SC.aq instructions are not guaranteed to provide any stronger ordering than those
    /// with both bits clear, but may result in lower performance.
    ///
    /// # Forms
    /// Assembly: `sc.w xd, xs2, xs1`
    /// Rust: `sc_w(rd, rs1, rs2, aq, rl)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Memory base register.
    /// - `rs2` — Source register.
    /// - `aq` — Acquire-order bit.
    /// - `rl` — Release-order bit; retained for the existing emitter API.
    pub fn sc_w<T0, T1, T2, T3, T4>(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4)
    where
        Self: ScWEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as ScWEmitter<T0, T1, T2, T3, T4>>::sc_w(self, rd, rs1, rs2, aq, rl);
    }
    /// RISC-V `scall` instruction.
    ///
    /// # Forms
    /// Assembly: `scall`
    /// Rust: `scall()`
    ///
    /// # Arguments
    pub fn scall(&mut self)
    where
        Self: ScallEmitter,
    {
        <Self as ScallEmitter>::scall(self);
    }
    /// RISC-V `sctrclr` instruction.
    ///
    /// # Forms
    /// Assembly: `sctrclr sctrclr`
    /// Rust: `sctrclr()`
    ///
    /// # Arguments
    pub fn sctrclr(&mut self)
    where
        Self: SctrclrEmitter,
    {
        <Self as SctrclrEmitter>::sctrclr(self);
    }
    /// Store doubleword
    ///
    /// Store 64 bits of data from register `rs2` to an
    /// address formed by adding `rs1` to a signed offset.
    ///
    /// # Forms
    /// Assembly: `sd xs2, imm(xs1)`
    /// Rust: `sd(rs1, rs2, imm)`
    ///
    /// # Arguments
    /// - `rs1` — Memory base register.
    /// - `rs2` — Source register.
    /// - `imm` — Immediate encoding value.
    pub fn sd<T0, T1, T2>(&mut self, rs1: T0, rs2: T1, imm: T2)
    where
        Self: SdEmitter<T0, T1, T2>,
    {
        <Self as SdEmitter<T0, T1, T2>>::sd(self, rs1, rs2, imm);
    }
    /// RISC-V `seqz` instruction.
    ///
    /// # Forms
    /// Assembly: `seqz rd rs1`
    /// Rust: `seqz(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn seqz<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: SeqzEmitter<T0, T1>,
    {
        <Self as SeqzEmitter<T0, T1>>::seqz(self, rd, rs1);
    }
    /// Sign-extend byte
    ///
    /// This instruction sign-extends the least-significant byte in the source to XLEN by copying the
    /// most-significant bit in the byte (i.e., bit 7) to all of the more-significant bits.
    ///
    /// # Forms
    /// Assembly: `sext.b xd, xs1`
    /// Rust: `sext_b(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn sext_b<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: SextBEmitter<T0, T1>,
    {
        <Self as SextBEmitter<T0, T1>>::sext_b(self, rd, rs1);
    }
    /// Sign-extend halfword
    ///
    /// This instruction sign-extends the least-significant halfword in the source to XLEN by copying the
    /// most-significant bit in the halfword (i.e., bit 15) to all of the more-significant bits.
    ///
    /// # Forms
    /// Assembly: `sext.h xd, xs1`
    /// Rust: `sext_h(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn sext_h<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: SextHEmitter<T0, T1>,
    {
        <Self as SextHEmitter<T0, T1>>::sext_h(self, rd, rs1);
    }
    /// RISC-V `sext.w` instruction.
    ///
    /// # Forms
    /// Assembly: `sext.w rd rs1`
    /// Rust: `sext_w(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn sext_w<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: SextWEmitter<T0, T1>,
    {
        <Self as SextWEmitter<T0, T1>>::sext_w(self, rd, rs1);
    }
    /// Order implicit page table reads after invalidation
    ///
    /// The `sfence.inval.ir` instruction guarantees that any previous `sinval.vma`
    /// instructions executed by the current hart are ordered before subsequent implicit references by
    /// that hart to the memory-management data structures.
    ///
    /// # Forms
    /// Assembly: `sfence.inval.ir ""`
    /// Rust: `sfence_inval_ir()`
    ///
    /// # Arguments
    pub fn sfence_inval_ir(&mut self)
    where
        Self: SfenceInvalIrEmitter,
    {
        <Self as SfenceInvalIrEmitter>::sfence_inval_ir(self);
    }
    /// Supervisor memory-management fence
    ///
    /// The supervisor memory-management fence instruction `SFENCE.VMA` is used to
    /// synchronize updates to in-memory memory-management data structures with
    /// current execution. Instruction execution causes implicit reads and
    /// writes to these data structures; however, these implicit references are
    /// ordinarily not ordered with respect to explicit loads and stores.
    /// Executing an SFENCE.VMA instruction guarantees that any previous stores
    /// already visible to the current RISC-V hart are ordered before certain
    /// implicit references by subsequent instructions in that hart to the
    /// memory-management data structures. The specific set of operations
    /// ordered by SFENCE.VMA is determined by _rs1_ and _rs2_, as described
    /// below. SFENCE.VMA is also used to invalidate entries in the
    /// address-translation cache associated with a hart (see &lt;&lt;sv32algorithm&gt;&gt;). Further details on the behavior of this instruction are described in &lt;&lt;virt-control&gt;&gt; and &lt;&lt;pmp-vmem&gt;&gt;.
    ///
    /// \[NOTE\]
    /// ====
    /// The SFENCE.VMA is used to flush any local hardware caches related to
    /// address translation. It is specified as a fence rather than a TLB flush
    /// to provide cleaner semantics with respect to which instructions are
    /// affected by the flush operation and to support a wider variety of
    /// dynamic caching structures and memory-management schemes. SFENCE.VMA is
    /// also used by higher privilege levels to synchronize page table writes
    /// and the address translation hardware.
    /// ====
    ///
    /// SFENCE.VMA orders only the local hart's implicit references to the
    /// memory-management data structures.
    ///
    /// \[NOTE\]
    /// ====
    /// Consequently, other harts must be notified separately when the
    /// memory-management data structures have been modified. One approach is to
    /// use 1) a local data fence to ensure local writes are visible globally,
    /// then 2) an interprocessor interrupt to the other thread, then 3) a local
    /// SFENCE.VMA in the interrupt handler of the remote thread, and finally 4)
    /// signal back to originating thread that operation is complete. This is,
    /// of course, the RISC-V analog to a TLB shootdown.
    /// ====
    ///
    /// For the common case that the translation data structures have only been
    /// modified for a single address mapping (i.e., one page or superpage),
    /// _rs1_ can specify a virtual address within that mapping to effect a
    /// translation fence for that mapping only. Furthermore, for the common
    /// case that the translation data structures have only been modified for a
    /// single address-space identifier, _rs2_ can specify the address space.
    /// The behavior of SFENCE.VMA depends on _rs1_ and _rs2_ as follows:
    ///
    /// * If __rs1__=`x0` and __rs2__=`x0`, the fence orders all reads and writes
    /// made to any level of the page tables, for all address spaces. The fence
    /// also invalidates all address-translation cache entries, for all address
    /// spaces.
    /// * If __rs1__=`x0` and __rs2__&#8800;``x0``, the fence orders all
    /// reads and writes made to any level of the page tables, but only for the
    /// address space identified by integer register _rs2_. Accesses to _global_
    /// mappings (see &lt;&lt;translation&gt;&gt;) are not ordered. The
    /// fence also invalidates all address-translation cache entries matching
    /// the address space identified by integer register _rs2_, except for
    /// entries containing global mappings.
    /// * If __rs1__&#8800;``x0`` and __rs2__=`x0`, the fence orders only
    /// reads and writes made to leaf page table entries corresponding to the
    /// virtual address in __rs1__, for all address spaces. The fence also
    /// invalidates all address-translation cache entries that contain leaf page
    /// table entries corresponding to the virtual address in _rs1_, for all
    /// address spaces.
    /// * If __rs1__&#8800;``x0`` and __rs2__&#8800;``x0``, the
    /// fence orders only reads and writes made to leaf page table entries
    /// corresponding to the virtual address in _rs1_, for the address space
    /// identified by integer register _rs2_. Accesses to global mappings are
    /// not ordered. The fence also invalidates all address-translation cache
    /// entries that contain leaf page table entries corresponding to the
    /// virtual address in _rs1_ and that match the address space identified by
    /// integer register _rs2_, except for entries containing global mappings.
    ///
    /// If the value held in _rs1_ is not a valid virtual address, then the
    /// SFENCE.VMA instruction has no effect. No exception is raised in this
    /// case.
    ///
    /// When __rs2__&#8800;``x0``, bits SXLEN-1:ASIDMAX of the value held
    /// in _rs2_ are reserved for future standard use. Until their use is
    /// defined by a standard extension, they should be zeroed by software and
    /// ignored by current implementations. Furthermore, if
    /// ASIDLEN&lt;ASIDMAX, the implementation shall ignore bits
    /// ASIDMAX-1:ASIDLEN of the value held in _rs2_.
    ///
    /// \[NOTE\]
    /// ====
    /// It is always legal to over-fence, e.g., by fencing only based on a
    /// subset of the bits in _rs1_ and/or _rs2_, and/or by simply treating all
    /// SFENCE.VMA instructions as having _rs1_=`x0` and/or _rs2_=`x0`. For
    /// example, simpler implementations can ignore the virtual address in _rs1_
    /// and the ASID value in _rs2_ and always perform a global fence. The
    /// choice not to raise an exception when an invalid virtual address is held
    /// in _rs1_ facilitates this type of simplification.
    /// ====
    ///
    /// An implicit read of the memory-management data structures may return any
    /// translation for an address that was valid at any time since the most
    /// recent SFENCE.VMA that subsumes that address. The ordering implied by
    /// SFENCE.VMA does not place implicit reads and writes to the
    /// memory-management data structures into the global memory order in a way
    /// that interacts cleanly with the standard RVWMO ordering rules. In
    /// particular, even though an SFENCE.VMA orders prior explicit accesses
    /// before subsequent implicit accesses, and those implicit accesses are
    /// ordered before their associated explicit accesses, SFENCE.VMA does not
    /// necessarily place prior explicit accesses before subsequent explicit
    /// accesses in the global memory order. These implicit loads also need not
    /// otherwise obey normal program order semantics with respect to prior
    /// loads or stores to the same address.
    ///
    /// \[NOTE\]
    /// ====
    /// A consequence of this specification is that an implementation may use
    /// any translation for an address that was valid at any time since the most
    /// recent SFENCE.VMA that subsumes that address. In particular, if a leaf
    /// PTE is modified but a subsuming SFENCE.VMA is not executed, either the
    /// old translation or the new translation will be used, but the choice is
    /// unpredictable. The behavior is otherwise well-defined.
    ///
    /// In a conventional TLB design, it is possible for multiple entries to
    /// match a single address if, for example, a page is upgraded to a
    /// superpage without first clearing the original non-leaf PTE's valid bit
    /// and executing an SFENCE.VMA with __rs1__=`x0`. In this case, a similar
    /// remark applies: it is unpredictable whether the old non-leaf PTE or the
    /// new leaf PTE is used, but the behavior is otherwise well defined.
    ///
    /// Another consequence of this specification is that it is generally unsafe
    /// to update a PTE using a set of stores of a width less than the width of
    /// the PTE, as it is legal for the implementation to read the PTE at any
    /// time, including when only some of the partial stores have taken effect.
    ///
    /// ***
    ///
    /// This specification permits the caching of PTEs whose V (Valid) bit is
    /// clear. Operating systems must be written to cope with this possibility,
    /// but implementers are reminded that eagerly caching invalid PTEs will
    /// reduce performance by causing additional page faults.
    /// ====
    ///
    /// Implementations must only perform implicit reads of the translation data
    /// structures pointed to by the current contents of the `satp` register or
    /// a subsequent valid (V=1) translation data structure entry, and must only
    /// raise exceptions for implicit accesses that are generated as a result of
    /// instruction execution, not those that are performed speculatively.
    ///
    /// Changes to the `sstatus` fields SUM and MXR take effect immediately,
    /// without the need to execute an SFENCE.VMA instruction. Changing
    /// `satp`.MODE from Bare to other modes and vice versa also takes effect
    /// immediately, without the need to execute an SFENCE.VMA instruction.
    /// Likewise, changes to `satp`.ASID take effect immediately.
    ///
    /// \[TIP\]
    /// ====
    /// The following common situations typically require executing an
    /// SFENCE.VMA instruction:
    ///
    /// * When software recycles an ASID (i.e., reassociates it with a different
    /// page table), it should _first_ change `satp` to point to the new page
    /// table using the recycled ASID, _then_ execute SFENCE.VMA with __rs1__=`x0`
    /// and _rs2_ set to the recycled ASID. Alternatively, software can execute
    /// the same SFENCE.VMA instruction while a different ASID is loaded into
    /// `satp`, provided the next time `satp` is loaded with the recycled ASID,
    /// it is simultaneously loaded with the new page table.
    /// * If the implementation does not provide ASIDs, or software chooses to
    /// always use ASID 0, then after every `satp` write, software should
    /// execute SFENCE.VMA with __rs1__=`x0`. In the common case that no global
    /// translations have been modified, _rs2_ should be set to a register other
    /// than `x0` but which contains the value zero, so that global translations
    /// are not flushed.
    /// * If software modifies a non-leaf PTE, it should execute SFENCE.VMA with
    /// __rs1__=`x0`. If any PTE along the traversal path had its G bit set, _rs2_
    /// must be `x0`; otherwise, _rs2_ should be set to the ASID for which the
    /// translation is being modified.
    /// * If software modifies a leaf PTE, it should execute SFENCE.VMA with
    /// _rs1_ set to a virtual address within the page. If any PTE along the
    /// traversal path had its G bit set, _rs2_ must be `x0`; otherwise, _rs2_
    /// should be set to the ASID for which the translation is being modified.
    /// * For the special cases of increasing the permissions on a leaf PTE and
    /// changing an invalid PTE to a valid leaf, software may choose to execute
    /// the SFENCE.VMA lazily. After modifying the PTE but before executing
    /// SFENCE.VMA, either the new or old permissions will be used. In the
    /// latter case, a page-fault exception might occur, at which point software
    /// should execute SFENCE.VMA in accordance with the previous bullet point.
    /// ====
    ///
    /// If a hart employs an address-translation cache, that cache must appear
    /// to be private to that hart. In particular, the meaning of an ASID is
    /// local to a hart; software may choose to use the same ASID to refer to
    /// different address spaces on different harts.
    ///
    /// \[NOTE\]
    /// ====
    /// A future extension could redefine ASIDs to be global across the SEE,
    /// enabling such options as shared translation caches and hardware support
    /// for broadcast TLB shootdown. However, as OSes have evolved to
    /// significantly reduce the scope of TLB shootdowns using novel
    /// ASID-management techniques, we expect the local-ASID scheme to remain
    /// attractive for its simplicity and possibly better scalability.
    /// ====
    ///
    /// For implementations that make `satp`.MODE read-only zero (always Bare),
    /// attempts to execute an SFENCE.VMA instruction might raise an
    /// illegal-instruction exception.
    ///
    /// # Forms
    /// Assembly: `sfence.vma xs1, xs2`
    /// Rust: `sfence_vma(rs1, rs2)`
    ///
    /// # Arguments
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn sfence_vma<T0, T1>(&mut self, rs1: T0, rs2: T1)
    where
        Self: SfenceVmaEmitter<T0, T1>,
    {
        <Self as SfenceVmaEmitter<T0, T1>>::sfence_vma(self, rs1, rs2);
    }
    /// Order writes before sfence
    ///
    /// The `sfence.w.inval` instruction guarantees that any previous stores already visible to the
    /// current RISC-V hart are ordered before subsequent `sinval.vma` instructions executed by the
    /// same hart.
    ///
    /// # Forms
    /// Assembly: `sfence.w.inval ""`
    /// Rust: `sfence_w_inval()`
    ///
    /// # Arguments
    pub fn sfence_w_inval(&mut self)
    where
        Self: SfenceWInvalEmitter,
    {
        <Self as SfenceWInvalEmitter>::sfence_w_inval(self);
    }
    /// RISC-V `sgtz` instruction.
    ///
    /// # Forms
    /// Assembly: `sgtz rd rs2`
    /// Rust: `sgtz(rd, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs2` — Source register.
    pub fn sgtz<T0, T1>(&mut self, rd: T0, rs2: T1)
    where
        Self: SgtzEmitter<T0, T1>,
    {
        <Self as SgtzEmitter<T0, T1>>::sgtz(self, rd, rs2);
    }
    /// Store halfword
    ///
    /// Store 16 bits of data from register `rs2` to an
    /// address formed by adding `rs1` to a signed offset.
    ///
    /// # Forms
    /// Assembly: `sh xs2, imm(xs1)`
    /// Rust: `sh(rs1, rs2, imm)`
    ///
    /// # Arguments
    /// - `rs1` — Memory base register.
    /// - `rs2` — Source register.
    /// - `imm` — Immediate encoding value.
    pub fn sh<T0, T1, T2>(&mut self, rs1: T0, rs2: T1, imm: T2)
    where
        Self: ShEmitter<T0, T1, T2>,
    {
        <Self as ShEmitter<T0, T1, T2>>::sh(self, rs1, rs2, imm);
    }
    /// Shift left by 1 and add
    ///
    /// This instruction shifts `rs1` to the left by 1 bit and adds it to `rs2`.
    ///
    /// # Forms
    /// Assembly: `sh1add xd, xs1, xs2`
    /// Rust: `sh1add(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn sh1add<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: Sh1AddEmitter<T0, T1, T2>,
    {
        <Self as Sh1AddEmitter<T0, T1, T2>>::sh1add(self, rd, rs1, rs2);
    }
    /// Shift unsigned word left by 1 and add
    ///
    /// This instruction performs an XLEN-wide addition of two addends. The first addend is rs2.
    /// The second addend is the unsigned value formed by extracting the least-significant word of rs1
    /// and shifting it left by 1 place.
    ///
    /// # Forms
    /// Assembly: `sh1add.uw xd, xs1, xs2`
    /// Rust: `sh1add_uw(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn sh1add_uw<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: Sh1AddUwEmitter<T0, T1, T2>,
    {
        <Self as Sh1AddUwEmitter<T0, T1, T2>>::sh1add_uw(self, rd, rs1, rs2);
    }
    /// Shift left by 2 and add
    ///
    /// This instruction shifts `rs1` to the left by 2 places and adds it to `rs2`.
    ///
    /// # Forms
    /// Assembly: `sh2add xd, xs1, xs2`
    /// Rust: `sh2add(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn sh2add<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: Sh2AddEmitter<T0, T1, T2>,
    {
        <Self as Sh2AddEmitter<T0, T1, T2>>::sh2add(self, rd, rs1, rs2);
    }
    /// Shift unsigned word left by 2 and add
    ///
    /// This instruction performs an XLEN-wide addition of two addends. The first addend is rs2.
    /// The second addend is the unsigned value formed by extracting the least-significant word of rs1
    /// and shifting it left by 2 places.
    ///
    /// # Forms
    /// Assembly: `sh2add.uw xd, xs1, xs2`
    /// Rust: `sh2add_uw(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn sh2add_uw<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: Sh2AddUwEmitter<T0, T1, T2>,
    {
        <Self as Sh2AddUwEmitter<T0, T1, T2>>::sh2add_uw(self, rd, rs1, rs2);
    }
    /// Shift left by 3 and add
    ///
    /// This instruction shifts `rs1` to the left by 3 places and adds it to `rs2`.
    ///
    /// # Forms
    /// Assembly: `sh3add xd, xs1, xs2`
    /// Rust: `sh3add(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn sh3add<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: Sh3AddEmitter<T0, T1, T2>,
    {
        <Self as Sh3AddEmitter<T0, T1, T2>>::sh3add(self, rd, rs1, rs2);
    }
    /// Shift unsigned word left by 3 and add
    ///
    /// This instruction performs an XLEN-wide addition of two addends. The first addend is rs2.
    /// The second addend is the unsigned value formed by extracting the least-significant word of rs1
    /// and shifting it left by 3 places.
    ///
    /// # Forms
    /// Assembly: `sh3add.uw xd, xs1, xs2`
    /// Rust: `sh3add_uw(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn sh3add_uw<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: Sh3AddUwEmitter<T0, T1, T2>,
    {
        <Self as Sh3AddUwEmitter<T0, T1, T2>>::sh3add_uw(self, rd, rs1, rs2);
    }
    /// RISC-V `sha256sig0` instruction.
    ///
    /// # Forms
    /// Assembly: `sha256sig0 xd, xs1`
    /// Rust: `sha256sig0(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn sha256sig0<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: Sha256Sig0Emitter<T0, T1>,
    {
        <Self as Sha256Sig0Emitter<T0, T1>>::sha256sig0(self, rd, rs1);
    }
    /// RISC-V `sha256sig1` instruction.
    ///
    /// # Forms
    /// Assembly: `sha256sig1 xd, xs1`
    /// Rust: `sha256sig1(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn sha256sig1<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: Sha256Sig1Emitter<T0, T1>,
    {
        <Self as Sha256Sig1Emitter<T0, T1>>::sha256sig1(self, rd, rs1);
    }
    /// RISC-V `sha256sum0` instruction.
    ///
    /// # Forms
    /// Assembly: `sha256sum0 xd, xs1`
    /// Rust: `sha256sum0(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn sha256sum0<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: Sha256Sum0Emitter<T0, T1>,
    {
        <Self as Sha256Sum0Emitter<T0, T1>>::sha256sum0(self, rd, rs1);
    }
    /// RISC-V `sha256sum1` instruction.
    ///
    /// # Forms
    /// Assembly: `sha256sum1 xd, xs1`
    /// Rust: `sha256sum1(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn sha256sum1<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: Sha256Sum1Emitter<T0, T1>,
    {
        <Self as Sha256Sum1Emitter<T0, T1>>::sha256sum1(self, rd, rs1);
    }
    /// RISC-V `sha512sig0` instruction.
    ///
    /// # Forms
    /// Assembly: `sha512sig0 xd, xs1`
    /// Rust: `sha512sig0(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn sha512sig0<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: Sha512Sig0Emitter<T0, T1>,
    {
        <Self as Sha512Sig0Emitter<T0, T1>>::sha512sig0(self, rd, rs1);
    }
    /// RISC-V `sha512sig0h` instruction.
    ///
    /// # Forms
    /// Assembly: `sha512sig0h xd, xs1, xs2`
    /// Rust: `sha512sig0h(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn sha512sig0h<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: Sha512Sig0HEmitter<T0, T1, T2>,
    {
        <Self as Sha512Sig0HEmitter<T0, T1, T2>>::sha512sig0h(self, rd, rs1, rs2);
    }
    /// RISC-V `sha512sig0l` instruction.
    ///
    /// # Forms
    /// Assembly: `sha512sig0l xd, xs1, xs2`
    /// Rust: `sha512sig0l(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn sha512sig0l<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: Sha512Sig0LEmitter<T0, T1, T2>,
    {
        <Self as Sha512Sig0LEmitter<T0, T1, T2>>::sha512sig0l(self, rd, rs1, rs2);
    }
    /// RISC-V `sha512sig1` instruction.
    ///
    /// # Forms
    /// Assembly: `sha512sig1 xd, xs1`
    /// Rust: `sha512sig1(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn sha512sig1<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: Sha512Sig1Emitter<T0, T1>,
    {
        <Self as Sha512Sig1Emitter<T0, T1>>::sha512sig1(self, rd, rs1);
    }
    /// RISC-V `sha512sig1h` instruction.
    ///
    /// # Forms
    /// Assembly: `sha512sig1h xd, xs1, xs2`
    /// Rust: `sha512sig1h(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn sha512sig1h<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: Sha512Sig1HEmitter<T0, T1, T2>,
    {
        <Self as Sha512Sig1HEmitter<T0, T1, T2>>::sha512sig1h(self, rd, rs1, rs2);
    }
    /// RISC-V `sha512sig1l` instruction.
    ///
    /// # Forms
    /// Assembly: `sha512sig1l xd, xs1, xs2`
    /// Rust: `sha512sig1l(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn sha512sig1l<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: Sha512Sig1LEmitter<T0, T1, T2>,
    {
        <Self as Sha512Sig1LEmitter<T0, T1, T2>>::sha512sig1l(self, rd, rs1, rs2);
    }
    /// RISC-V `sha512sum0` instruction.
    ///
    /// # Forms
    /// Assembly: `sha512sum0 xd, xs1`
    /// Rust: `sha512sum0(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn sha512sum0<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: Sha512Sum0Emitter<T0, T1>,
    {
        <Self as Sha512Sum0Emitter<T0, T1>>::sha512sum0(self, rd, rs1);
    }
    /// RISC-V `sha512sum0r` instruction.
    ///
    /// # Forms
    /// Assembly: `sha512sum0r xd, xs1, xs2`
    /// Rust: `sha512sum0r(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn sha512sum0r<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: Sha512Sum0REmitter<T0, T1, T2>,
    {
        <Self as Sha512Sum0REmitter<T0, T1, T2>>::sha512sum0r(self, rd, rs1, rs2);
    }
    /// RISC-V `sha512sum1` instruction.
    ///
    /// # Forms
    /// Assembly: `sha512sum1 xd, xs1`
    /// Rust: `sha512sum1(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn sha512sum1<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: Sha512Sum1Emitter<T0, T1>,
    {
        <Self as Sha512Sum1Emitter<T0, T1>>::sha512sum1(self, rd, rs1);
    }
    /// RISC-V `sha512sum1r` instruction.
    ///
    /// # Forms
    /// Assembly: `sha512sum1r xd, xs1, xs2`
    /// Rust: `sha512sum1r(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn sha512sum1r<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: Sha512Sum1REmitter<T0, T1, T2>,
    {
        <Self as Sha512Sum1REmitter<T0, T1, T2>>::sha512sum1r(self, rd, rs1, rs2);
    }
    /// Invalidate cached address translations
    ///
    /// # Forms
    /// Assembly: `sinval.vma xs1, xs2`
    /// Rust: `sinval_vma(rs1, rs2)`
    ///
    /// # Arguments
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn sinval_vma<T0, T1>(&mut self, rs1: T0, rs2: T1)
    where
        Self: SinvalVmaEmitter<T0, T1>,
    {
        <Self as SinvalVmaEmitter<T0, T1>>::sinval_vma(self, rs1, rs2);
    }
    /// Shift left logical
    ///
    /// Shift the value in `rs1` left by the value in the lower 6 bits of `rs2`, and store the result in `rd`.
    ///
    /// # Forms
    /// Assembly: `sll xd, xs1, xs2`
    /// Rust: `sll(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn sll<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: SllEmitter<T0, T1, T2>,
    {
        <Self as SllEmitter<T0, T1, T2>>::sll(self, rd, rs1, rs2);
    }
    /// Shift left logical immediate
    ///
    /// Shift the value in rs1 left by shamt, and store the result in rd
    ///
    /// # Forms
    /// Assembly: `slli xd, xs1, shamt`
    /// Rust: `slli(rd, rs1, shamtd)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `shamtd` — Immediate encoding value.
    pub fn slli<T0, T1, T2>(&mut self, rd: T0, rs1: T1, shamtd: T2)
    where
        Self: SlliEmitter<T0, T1, T2>,
    {
        <Self as SlliEmitter<T0, T1, T2>>::slli(self, rd, rs1, shamtd);
    }
    /// Shift left logical immediate
    ///
    /// Shift the value in rs1 left by shamt, and store the result in rd
    ///
    /// # Forms
    /// Assembly: `slli.rv32 xd, xs1, shamt`
    /// Rust: `slli_rv32(rd, rs1, shamtw)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `shamtw` — Immediate encoding value.
    pub fn slli_rv32<T0, T1, T2>(&mut self, rd: T0, rs1: T1, shamtw: T2)
    where
        Self: SlliRv32Emitter<T0, T1, T2>,
    {
        <Self as SlliRv32Emitter<T0, T1, T2>>::slli_rv32(self, rd, rs1, shamtw);
    }
    /// Shift left unsigned word (Immediate)
    ///
    /// This instruction takes the least-significant word of rs1, zero-extends it, and shifts it
    /// left by the immediate.
    ///
    /// \[NOTE\]
    /// This instruction is the same as `slli` with `zext.w` performed on rs1 before shifting.
    ///
    /// # Forms
    /// Assembly: `slli.uw xd, xs1, shamt`
    /// Rust: `slli_uw(rd, rs1, shamtd)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `shamtd` — Immediate encoding value.
    pub fn slli_uw<T0, T1, T2>(&mut self, rd: T0, rs1: T1, shamtd: T2)
    where
        Self: SlliUwEmitter<T0, T1, T2>,
    {
        <Self as SlliUwEmitter<T0, T1, T2>>::slli_uw(self, rd, rs1, shamtd);
    }
    /// Shift left logical immediate word
    ///
    /// Shift the 32-bit value in rs1 left by shamt, and store the sign-extended result in rd
    ///
    /// # Forms
    /// Assembly: `slliw xd, xs1, shamt`
    /// Rust: `slliw(rd, rs1, shamtw)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `shamtw` — Immediate encoding value.
    pub fn slliw<T0, T1, T2>(&mut self, rd: T0, rs1: T1, shamtw: T2)
    where
        Self: SlliwEmitter<T0, T1, T2>,
    {
        <Self as SlliwEmitter<T0, T1, T2>>::slliw(self, rd, rs1, shamtw);
    }
    /// Shift left logical word
    ///
    /// Shift the 32-bit value in `rs1` left by the value in the lower 5 bits of `rs2`, and store the sign-extended result in `rd`.
    ///
    /// # Forms
    /// Assembly: `sllw xd, xs1, xs2`
    /// Rust: `sllw(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn sllw<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: SllwEmitter<T0, T1, T2>,
    {
        <Self as SllwEmitter<T0, T1, T2>>::sllw(self, rd, rs1, rs2);
    }
    /// Set on less than
    ///
    /// Places the value 1 in register `rd` if register `rs1` is less than the value in register `rs2`, where
    /// both sources are treated as signed numbers, else 0 is written to `rd`.
    ///
    /// # Forms
    /// Assembly: `slt xd, xs1, rs2`
    /// Rust: `slt(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn slt<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: SltEmitter<T0, T1, T2>,
    {
        <Self as SltEmitter<T0, T1, T2>>::slt(self, rd, rs1, rs2);
    }
    /// Set on less than immediate
    ///
    /// Places the value 1 in register `rd` if register `rs1` is less than the sign-extended immediate
    /// when both are treated as signed numbers, else 0 is written to `rd`.
    ///
    /// # Forms
    /// Assembly: `slti xd, xs1, imm`
    /// Rust: `slti(rd, rs1, imm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `imm` — Immediate encoding value.
    pub fn slti<T0, T1, T2>(&mut self, rd: T0, rs1: T1, imm: T2)
    where
        Self: SltiEmitter<T0, T1, T2>,
    {
        <Self as SltiEmitter<T0, T1, T2>>::slti(self, rd, rs1, imm);
    }
    /// Set on less than immediate unsigned
    ///
    /// Places the value 1 in register `rd` if register `rs1` is less than the sign-extended immediate
    /// when both are treated as unsigned numbers (_i.e._, the immediate is first sign-extended to
    /// XLEN bits then treated as an unsigned number), else 0 is written to `rd`.
    ///
    /// NOTE: `sltiu rd, rs1, 1` sets `rd` to 1 if `rs1` equals zero, otherwise sets `rd` to 0
    /// (assembler pseudoinstruction `SEQZ rd, rs`).
    ///
    /// # Forms
    /// Assembly: `sltiu xd, xs1, imm`
    /// Rust: `sltiu(rd, rs1, imm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `imm` — Immediate encoding value.
    pub fn sltiu<T0, T1, T2>(&mut self, rd: T0, rs1: T1, imm: T2)
    where
        Self: SltiuEmitter<T0, T1, T2>,
    {
        <Self as SltiuEmitter<T0, T1, T2>>::sltiu(self, rd, rs1, imm);
    }
    /// Set on less than unsigned
    ///
    /// Places the value 1 in register `rd` if register `rs1` is less than the value in register `rs2`, where
    /// both sources are treated as unsigned numbers, else 0 is written to `rd`.
    ///
    /// # Forms
    /// Assembly: `sltu xd, xs1, xs2`
    /// Rust: `sltu(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn sltu<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: SltuEmitter<T0, T1, T2>,
    {
        <Self as SltuEmitter<T0, T1, T2>>::sltu(self, rd, rs1, rs2);
    }
    /// RISC-V `sltz` instruction.
    ///
    /// # Forms
    /// Assembly: `sltz rd rs1`
    /// Rust: `sltz(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn sltz<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: SltzEmitter<T0, T1>,
    {
        <Self as SltzEmitter<T0, T1>>::sltz(self, rd, rs1);
    }
    /// RISC-V `sm3p0` instruction.
    ///
    /// # Forms
    /// Assembly: `sm3p0 xd, xs1`
    /// Rust: `sm3p0(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn sm3p0<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: Sm3P0Emitter<T0, T1>,
    {
        <Self as Sm3P0Emitter<T0, T1>>::sm3p0(self, rd, rs1);
    }
    /// RISC-V `sm3p1` instruction.
    ///
    /// # Forms
    /// Assembly: `sm3p1 xd, xs1`
    /// Rust: `sm3p1(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn sm3p1<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: Sm3P1Emitter<T0, T1>,
    {
        <Self as Sm3P1Emitter<T0, T1>>::sm3p1(self, rd, rs1);
    }
    /// RISC-V `sm4ed` instruction.
    ///
    /// # Forms
    /// Assembly: `sm4ed xd, xs1, xs2, bs`
    /// Rust: `sm4ed(rd, rs1, rs2, bs)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    /// - `bs` — Immediate encoding value.
    pub fn sm4ed<T0, T1, T2, T3>(&mut self, rd: T0, rs1: T1, rs2: T2, bs: T3)
    where
        Self: Sm4EdEmitter<T0, T1, T2, T3>,
    {
        <Self as Sm4EdEmitter<T0, T1, T2, T3>>::sm4ed(self, rd, rs1, rs2, bs);
    }
    /// RISC-V `sm4ks` instruction.
    ///
    /// # Forms
    /// Assembly: `sm4ks xd, xs1, xs2, bs`
    /// Rust: `sm4ks(rd, rs1, rs2, bs)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    /// - `bs` — Immediate encoding value.
    pub fn sm4ks<T0, T1, T2, T3>(&mut self, rd: T0, rs1: T1, rs2: T2, bs: T3)
    where
        Self: Sm4KsEmitter<T0, T1, T2, T3>,
    {
        <Self as Sm4KsEmitter<T0, T1, T2, T3>>::sm4ks(self, rd, rs1, rs2, bs);
    }
    /// RISC-V `snez` instruction.
    ///
    /// # Forms
    /// Assembly: `snez rd rs2`
    /// Rust: `snez(rd, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs2` — Source register.
    pub fn snez<T0, T1>(&mut self, rd: T0, rs2: T1)
    where
        Self: SnezEmitter<T0, T1>,
    {
        <Self as SnezEmitter<T0, T1>>::snez(self, rd, rs2);
    }
    /// Shift right arithmetic
    ///
    /// Arithmetic shift the value in `rs1` right by the value in the lower 5 bits of `rs2`, and store the result in `rd`.
    ///
    /// # Forms
    /// Assembly: `sra xd, xs1, xs2`
    /// Rust: `sra(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn sra<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: SraEmitter<T0, T1, T2>,
    {
        <Self as SraEmitter<T0, T1, T2>>::sra(self, rd, rs1, rs2);
    }
    /// Shift right arithmetic immediate
    ///
    /// Arithmetic shift (the original sign bit is copied into the vacated upper bits) the
    /// value in rs1 right by shamt, and store the result in rd.
    ///
    /// # Forms
    /// Assembly: `srai xd, xs1, shamt`
    /// Rust: `srai(rd, rs1, shamtd)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `shamtd` — Immediate encoding value.
    pub fn srai<T0, T1, T2>(&mut self, rd: T0, rs1: T1, shamtd: T2)
    where
        Self: SraiEmitter<T0, T1, T2>,
    {
        <Self as SraiEmitter<T0, T1, T2>>::srai(self, rd, rs1, shamtd);
    }
    /// Shift right arithmetic immediate
    ///
    /// Arithmetic shift (the original sign bit is copied into the vacated upper bits) the
    /// value in rs1 right by shamt, and store the result in rd.
    ///
    /// # Forms
    /// Assembly: `srai.rv32 xd, xs1, shamt`
    /// Rust: `srai_rv32(rd, rs1, shamtw)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `shamtw` — Immediate encoding value.
    pub fn srai_rv32<T0, T1, T2>(&mut self, rd: T0, rs1: T1, shamtw: T2)
    where
        Self: SraiRv32Emitter<T0, T1, T2>,
    {
        <Self as SraiRv32Emitter<T0, T1, T2>>::srai_rv32(self, rd, rs1, shamtw);
    }
    /// Shift right arithmetic immediate word
    ///
    /// Arithmetic shift (the original sign bit is copied into the vacated upper bits) the
    /// 32-bit value in rs1 right by shamt, and store the sign-extended result in rd.
    ///
    /// # Forms
    /// Assembly: `sraiw xd, xs1, shamt`
    /// Rust: `sraiw(rd, rs1, shamtw)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `shamtw` — Immediate encoding value.
    pub fn sraiw<T0, T1, T2>(&mut self, rd: T0, rs1: T1, shamtw: T2)
    where
        Self: SraiwEmitter<T0, T1, T2>,
    {
        <Self as SraiwEmitter<T0, T1, T2>>::sraiw(self, rd, rs1, shamtw);
    }
    /// Shift right arithmetic word
    ///
    /// Arithmetic shift the 32-bit value in `rs1` right by the value in the lower 5 bits of `rs2`, and store the sign-extended result in `rd`.
    ///
    /// # Forms
    /// Assembly: `sraw xd, xs1, xs2`
    /// Rust: `sraw(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn sraw<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: SrawEmitter<T0, T1, T2>,
    {
        <Self as SrawEmitter<T0, T1, T2>>::sraw(self, rd, rs1, rs2);
    }
    /// Supervisor Exception Return
    ///
    /// Returns from an exception.
    ///
    /// When `sret` is allowed to execute, its behavior depends on whether or not the current privilege
    /// mode is virtualized.
    ///
    /// *When the current privilege mode is (H)S-mode or M-mode*
    ///
    /// `sret` sets  `hstatus.HPV` = 0, `mstatus.SPP` = 0,
    /// `mstatus.SIE` = `mstatus.SPIE`, and `mstatus.SPIE` = 1,
    /// changes the privilege mode according to the table below,
    /// and then jumps to the address in `sepc`.
    ///
    /// .Next privilege mode following an `sret` in (H)S-mode or M-mode
    /// \[%autowidth\]
    /// |===
    /// | \[.rotate\]#`mstatus.SPP`# | \[.rotate\]#`hstatus.SPV`# .&gt;| Mode after `sret`
    ///
    /// | 0 | 0 | U-mode
    /// | 0 | 1 | VU-mode
    /// | 1 | 0 | (H)S-mode
    /// | 1 | 1 | VS-mode
    /// |===
    ///
    /// *When the current privilege mode is VS-mode*
    ///
    /// `sret` sets
    /// `vsstatus.SPP` = 0, `vsstatus.SIE` = `vstatus.SPIE`, and `vsstatus.SPIE` = 1,
    /// changes the privilege mode according to the table below,
    /// and then jumps to the address in `vsepc`.
    ///
    /// .Next privilege mode following an `sret` in (H)S-mode or M-mode
    /// \[%autowidth\]
    /// |===
    /// | \[.rotate\]#`vsstatus.SPP`# .&gt;| Mode after `sret`
    ///
    /// | 0 | VU-mode
    /// | 1 | VS-mode
    /// |===
    ///
    /// # Forms
    /// Assembly: `sret ""`
    /// Rust: `sret()`
    ///
    /// # Arguments
    pub fn sret(&mut self)
    where
        Self: SretEmitter,
    {
        <Self as SretEmitter>::sret(self);
    }
    /// Shift right logical
    ///
    /// Logical shift the value in `rs1` right by the value in the lower bits of `rs2`, and store the result in `rd`.
    ///
    /// # Forms
    /// Assembly: `srl xd, xs1, xs2`
    /// Rust: `srl(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn srl<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: SrlEmitter<T0, T1, T2>,
    {
        <Self as SrlEmitter<T0, T1, T2>>::srl(self, rd, rs1, rs2);
    }
    /// Shift right logical immediate
    ///
    /// Shift the value in rs1 right by shamt, and store the result in rd
    ///
    /// # Forms
    /// Assembly: `srli xd, xs1, shamt`
    /// Rust: `srli(rd, rs1, shamtd)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `shamtd` — Immediate encoding value.
    pub fn srli<T0, T1, T2>(&mut self, rd: T0, rs1: T1, shamtd: T2)
    where
        Self: SrliEmitter<T0, T1, T2>,
    {
        <Self as SrliEmitter<T0, T1, T2>>::srli(self, rd, rs1, shamtd);
    }
    /// Shift right logical immediate
    ///
    /// Shift the value in rs1 right by shamt, and store the result in rd
    ///
    /// # Forms
    /// Assembly: `srli.rv32 xd, xs1, shamt`
    /// Rust: `srli_rv32(rd, rs1, shamtw)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `shamtw` — Immediate encoding value.
    pub fn srli_rv32<T0, T1, T2>(&mut self, rd: T0, rs1: T1, shamtw: T2)
    where
        Self: SrliRv32Emitter<T0, T1, T2>,
    {
        <Self as SrliRv32Emitter<T0, T1, T2>>::srli_rv32(self, rd, rs1, shamtw);
    }
    /// Shift right logical immediate word
    ///
    /// Shift the 32-bit value in rs1 right by shamt, and store the sign-extended result in rd
    ///
    /// # Forms
    /// Assembly: `srliw xd, xs1, shamt`
    /// Rust: `srliw(rd, rs1, shamtw)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `shamtw` — Immediate encoding value.
    pub fn srliw<T0, T1, T2>(&mut self, rd: T0, rs1: T1, shamtw: T2)
    where
        Self: SrliwEmitter<T0, T1, T2>,
    {
        <Self as SrliwEmitter<T0, T1, T2>>::srliw(self, rd, rs1, shamtw);
    }
    /// Shift right logical word
    ///
    /// Logical shift the 32-bit value in `rs1` right by the value in the lower 5 bits of `rs2`, and store the sign-extended result in `rd`.
    ///
    /// # Forms
    /// Assembly: `srlw xd, xs1, xs2`
    /// Rust: `srlw(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn srlw<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: SrlwEmitter<T0, T1, T2>,
    {
        <Self as SrlwEmitter<T0, T1, T2>>::srlw(self, rd, rs1, rs2);
    }
    /// RISC-V `ssamoswap.d` instruction.
    ///
    /// # Forms
    /// Assembly: `ssamoswap.d xd, xs1, xs2, aq, rl`
    /// Rust: `ssamoswap_d(rd, rs1, rs2, aq, rl)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Memory base register.
    /// - `rs2` — Source register.
    /// - `aq` — Acquire-order bit.
    /// - `rl` — Release-order bit; retained for the existing emitter API.
    pub fn ssamoswap_d<T0, T1, T2, T3, T4>(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4)
    where
        Self: SsamoswapDEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as SsamoswapDEmitter<T0, T1, T2, T3, T4>>::ssamoswap_d(self, rd, rs1, rs2, aq, rl);
    }
    /// RISC-V `ssamoswap.w` instruction.
    ///
    /// # Forms
    /// Assembly: `ssamoswap.w xd, xs1, xs2, aq, rl`
    /// Rust: `ssamoswap_w(rd, rs1, rs2, aq, rl)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Memory base register.
    /// - `rs2` — Source register.
    /// - `aq` — Acquire-order bit.
    /// - `rl` — Release-order bit; retained for the existing emitter API.
    pub fn ssamoswap_w<T0, T1, T2, T3, T4>(&mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4)
    where
        Self: SsamoswapWEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as SsamoswapWEmitter<T0, T1, T2, T3, T4>>::ssamoswap_w(self, rd, rs1, rs2, aq, rl);
    }
    /// RISC-V `sspopchk.x1` instruction.
    ///
    /// # Forms
    /// Assembly: `sspopchk.x1 sspopchk_x1`
    /// Rust: `sspopchk_x1()`
    ///
    /// # Arguments
    pub fn sspopchk_x1(&mut self)
    where
        Self: SspopchkX1Emitter,
    {
        <Self as SspopchkX1Emitter>::sspopchk_x1(self);
    }
    /// RISC-V `sspopchk.x5` instruction.
    ///
    /// # Forms
    /// Assembly: `sspopchk.x5 sspopchk_x5`
    /// Rust: `sspopchk_x5()`
    ///
    /// # Arguments
    pub fn sspopchk_x5(&mut self)
    where
        Self: SspopchkX5Emitter,
    {
        <Self as SspopchkX5Emitter>::sspopchk_x5(self);
    }
    /// RISC-V `sspush.x1` instruction.
    ///
    /// # Forms
    /// Assembly: `sspush.x1 sspush_x1`
    /// Rust: `sspush_x1()`
    ///
    /// # Arguments
    pub fn sspush_x1(&mut self)
    where
        Self: SspushX1Emitter,
    {
        <Self as SspushX1Emitter>::sspush_x1(self);
    }
    /// RISC-V `sspush.x5` instruction.
    ///
    /// # Forms
    /// Assembly: `sspush.x5 sspush_x5`
    /// Rust: `sspush_x5()`
    ///
    /// # Arguments
    pub fn sspush_x5(&mut self)
    where
        Self: SspushX5Emitter,
    {
        <Self as SspushX5Emitter>::sspush_x5(self);
    }
    /// RISC-V `ssrdp` instruction.
    ///
    /// # Forms
    /// Assembly: `ssrdp xd`
    /// Rust: `ssrdp(rd)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    pub fn ssrdp<T0>(&mut self, rd: T0)
    where
        Self: SsrdpEmitter<T0>,
    {
        <Self as SsrdpEmitter<T0>>::ssrdp(self, rd);
    }
    /// Subtract
    ///
    /// Subtract the value in rs2 from rs1, and store the result in rd
    ///
    /// # Forms
    /// Assembly: `sub xd, xs1, xs2`
    /// Rust: `sub(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn sub<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: SubEmitter<T0, T1, T2>,
    {
        <Self as SubEmitter<T0, T1, T2>>::sub(self, rd, rs1, rs2);
    }
    /// Subtract word
    ///
    /// Subtract the 32-bit values in rs2 from rs1, and store the sign-extended result in rd
    ///
    /// # Forms
    /// Assembly: `subw xd, xs1, xs2`
    /// Rust: `subw(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn subw<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: SubwEmitter<T0, T1, T2>,
    {
        <Self as SubwEmitter<T0, T1, T2>>::subw(self, rd, rs1, rs2);
    }
    /// Store word
    ///
    /// Store 32 bits of data from register `rs2` to an
    /// address formed by adding `rs1` to a signed offset.
    ///
    /// # Forms
    /// Assembly: `sw xs2, imm(xs1)`
    /// Rust: `sw(rs1, rs2, imm)`
    ///
    /// # Arguments
    /// - `rs1` — Memory base register.
    /// - `rs2` — Source register.
    /// - `imm` — Immediate encoding value.
    pub fn sw<T0, T1, T2>(&mut self, rs1: T0, rs2: T1, imm: T2)
    where
        Self: SwEmitter<T0, T1, T2>,
    {
        <Self as SwEmitter<T0, T1, T2>>::sw(self, rs1, rs2, imm);
    }
    /// Bit deinterleave
    ///
    /// This instruction gathers bits from the high and low halves of the source word into odd/even bit
    /// positions in the destination word. It is the inverse of the zip instruction. This instruction is
    /// available only on RV32.
    ///
    /// # Forms
    /// Assembly: `unzip xd, xs1`
    /// Rust: `unzip(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn unzip<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: UnzipEmitter<T0, T1>,
    {
        <Self as UnzipEmitter<T0, T1>>::unzip(self, rd, rs1);
    }
    /// RISC-V `vaadd.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vaadd.vv vm, vs2, vs1, vd`
    /// Rust: `vaadd_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vaadd_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VaaddVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VaaddVvEmitter<T0, T1, T2, T3>>::vaadd_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vaadd.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vaadd.vx vm, vs2, xs1, vd`
    /// Rust: `vaadd_vx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vaadd_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VaaddVxEmitter<T0, T1, T2, T3>,
    {
        <Self as VaaddVxEmitter<T0, T1, T2, T3>>::vaadd_vx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vaaddu.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vaaddu.vv vm, vs2, vs1, vd`
    /// Rust: `vaaddu_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vaaddu_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VaadduVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VaadduVvEmitter<T0, T1, T2, T3>>::vaaddu_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vaaddu.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vaaddu.vx vm, vs2, xs1, vd`
    /// Rust: `vaaddu_vx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vaaddu_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VaadduVxEmitter<T0, T1, T2, T3>,
    {
        <Self as VaadduVxEmitter<T0, T1, T2, T3>>::vaaddu_vx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vadc.vim` instruction.
    ///
    /// # Forms
    /// Assembly: `vadc.vim vs2, vd, imm`
    /// Rust: `vadc_vim(vd, vs2, simm5)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `simm5` — Immediate encoding value.
    pub fn vadc_vim<T0, T1, T2>(&mut self, vd: T0, vs2: T1, simm5: T2)
    where
        Self: VadcVimEmitter<T0, T1, T2>,
    {
        <Self as VadcVimEmitter<T0, T1, T2>>::vadc_vim(self, vd, vs2, simm5);
    }
    /// RISC-V `vadc.vvm` instruction.
    ///
    /// # Forms
    /// Assembly: `vadc.vvm vs2, vs1, vd`
    /// Rust: `vadc_vvm(vd, vs1, vs2)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    pub fn vadc_vvm<T0, T1, T2>(&mut self, vd: T0, vs1: T1, vs2: T2)
    where
        Self: VadcVvmEmitter<T0, T1, T2>,
    {
        <Self as VadcVvmEmitter<T0, T1, T2>>::vadc_vvm(self, vd, vs1, vs2);
    }
    /// RISC-V `vadc.vxm` instruction.
    ///
    /// # Forms
    /// Assembly: `vadc.vxm vs2, xs1, vd`
    /// Rust: `vadc_vxm(vd, rs1, vs2)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vs2` — Vector register operand.
    pub fn vadc_vxm<T0, T1, T2>(&mut self, vd: T0, rs1: T1, vs2: T2)
    where
        Self: VadcVxmEmitter<T0, T1, T2>,
    {
        <Self as VadcVxmEmitter<T0, T1, T2>>::vadc_vxm(self, vd, rs1, vs2);
    }
    /// RISC-V `vadd.vi` instruction.
    ///
    /// # Forms
    /// Assembly: `vadd.vi vm, vs2, vd, imm`
    /// Rust: `vadd_vi(vd, vs2, simm5, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `simm5` — Immediate encoding value.
    /// - `vm` — Vector mask control.
    pub fn vadd_vi<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, simm5: T2, vm: T3)
    where
        Self: VaddViEmitter<T0, T1, T2, T3>,
    {
        <Self as VaddViEmitter<T0, T1, T2, T3>>::vadd_vi(self, vd, vs2, simm5, vm);
    }
    /// RISC-V `vadd.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vadd.vv vm, vs2, vs1, vd`
    /// Rust: `vadd_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vadd_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VaddVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VaddVvEmitter<T0, T1, T2, T3>>::vadd_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vadd.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vadd.vx vm, vs2, xs1, vd`
    /// Rust: `vadd_vx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vadd_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VaddVxEmitter<T0, T1, T2, T3>,
    {
        <Self as VaddVxEmitter<T0, T1, T2, T3>>::vadd_vx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vaesdf.vs` instruction.
    ///
    /// # Forms
    /// Assembly: `vaesdf.vs vs2, vd`
    /// Rust: `vaesdf_vs(vd, vs2)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    pub fn vaesdf_vs<T0, T1>(&mut self, vd: T0, vs2: T1)
    where
        Self: VaesdfVsEmitter<T0, T1>,
    {
        <Self as VaesdfVsEmitter<T0, T1>>::vaesdf_vs(self, vd, vs2);
    }
    /// RISC-V `vaesdf.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vaesdf.vv vs2, vd`
    /// Rust: `vaesdf_vv(vd, vs2)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    pub fn vaesdf_vv<T0, T1>(&mut self, vd: T0, vs2: T1)
    where
        Self: VaesdfVvEmitter<T0, T1>,
    {
        <Self as VaesdfVvEmitter<T0, T1>>::vaesdf_vv(self, vd, vs2);
    }
    /// RISC-V `vaesdm.vs` instruction.
    ///
    /// # Forms
    /// Assembly: `vaesdm.vs vs2, vd`
    /// Rust: `vaesdm_vs(vd, vs2)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    pub fn vaesdm_vs<T0, T1>(&mut self, vd: T0, vs2: T1)
    where
        Self: VaesdmVsEmitter<T0, T1>,
    {
        <Self as VaesdmVsEmitter<T0, T1>>::vaesdm_vs(self, vd, vs2);
    }
    /// RISC-V `vaesdm.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vaesdm.vv vs2, vd`
    /// Rust: `vaesdm_vv(vd, vs2)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    pub fn vaesdm_vv<T0, T1>(&mut self, vd: T0, vs2: T1)
    where
        Self: VaesdmVvEmitter<T0, T1>,
    {
        <Self as VaesdmVvEmitter<T0, T1>>::vaesdm_vv(self, vd, vs2);
    }
    /// RISC-V `vaesef.vs` instruction.
    ///
    /// # Forms
    /// Assembly: `vaesef.vs vs2, vd`
    /// Rust: `vaesef_vs(vd, vs2)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    pub fn vaesef_vs<T0, T1>(&mut self, vd: T0, vs2: T1)
    where
        Self: VaesefVsEmitter<T0, T1>,
    {
        <Self as VaesefVsEmitter<T0, T1>>::vaesef_vs(self, vd, vs2);
    }
    /// RISC-V `vaesef.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vaesef.vv vs2, vd`
    /// Rust: `vaesef_vv(vd, vs2)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    pub fn vaesef_vv<T0, T1>(&mut self, vd: T0, vs2: T1)
    where
        Self: VaesefVvEmitter<T0, T1>,
    {
        <Self as VaesefVvEmitter<T0, T1>>::vaesef_vv(self, vd, vs2);
    }
    /// RISC-V `vaesem.vs` instruction.
    ///
    /// # Forms
    /// Assembly: `vaesem.vs vs2, vd`
    /// Rust: `vaesem_vs(vd, vs2)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    pub fn vaesem_vs<T0, T1>(&mut self, vd: T0, vs2: T1)
    where
        Self: VaesemVsEmitter<T0, T1>,
    {
        <Self as VaesemVsEmitter<T0, T1>>::vaesem_vs(self, vd, vs2);
    }
    /// RISC-V `vaesem.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vaesem.vv vs2, vd`
    /// Rust: `vaesem_vv(vd, vs2)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    pub fn vaesem_vv<T0, T1>(&mut self, vd: T0, vs2: T1)
    where
        Self: VaesemVvEmitter<T0, T1>,
    {
        <Self as VaesemVvEmitter<T0, T1>>::vaesem_vv(self, vd, vs2);
    }
    /// RISC-V `vaeskf1.vi` instruction.
    ///
    /// # Forms
    /// Assembly: `vaeskf1.vi vs2, vd, imm`
    /// Rust: `vaeskf1_vi(vd, vs2, zimm5)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `zimm5` — Immediate encoding value.
    pub fn vaeskf1_vi<T0, T1, T2>(&mut self, vd: T0, vs2: T1, zimm5: T2)
    where
        Self: Vaeskf1ViEmitter<T0, T1, T2>,
    {
        <Self as Vaeskf1ViEmitter<T0, T1, T2>>::vaeskf1_vi(self, vd, vs2, zimm5);
    }
    /// RISC-V `vaeskf2.vi` instruction.
    ///
    /// # Forms
    /// Assembly: `vaeskf2.vi vs2, vd, imm`
    /// Rust: `vaeskf2_vi(vd, vs2, zimm5)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `zimm5` — Immediate encoding value.
    pub fn vaeskf2_vi<T0, T1, T2>(&mut self, vd: T0, vs2: T1, zimm5: T2)
    where
        Self: Vaeskf2ViEmitter<T0, T1, T2>,
    {
        <Self as Vaeskf2ViEmitter<T0, T1, T2>>::vaeskf2_vi(self, vd, vs2, zimm5);
    }
    /// Vector AES round zero
    ///
    /// # Forms
    /// Assembly: `vaesz.vs vs2, vd`
    /// Rust: `vaesz_vs(vd, vs2)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    pub fn vaesz_vs<T0, T1>(&mut self, vd: T0, vs2: T1)
    where
        Self: VaeszVsEmitter<T0, T1>,
    {
        <Self as VaeszVsEmitter<T0, T1>>::vaesz_vs(self, vd, vs2);
    }
    /// RISC-V `vand.vi` instruction.
    ///
    /// # Forms
    /// Assembly: `vand.vi vm, vs2, vd, imm`
    /// Rust: `vand_vi(vd, vs2, simm5, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `simm5` — Immediate encoding value.
    /// - `vm` — Vector mask control.
    pub fn vand_vi<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, simm5: T2, vm: T3)
    where
        Self: VandViEmitter<T0, T1, T2, T3>,
    {
        <Self as VandViEmitter<T0, T1, T2, T3>>::vand_vi(self, vd, vs2, simm5, vm);
    }
    /// RISC-V `vand.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vand.vv vm, vs2, vs1, vd`
    /// Rust: `vand_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vand_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VandVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VandVvEmitter<T0, T1, T2, T3>>::vand_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vand.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vand.vx vm, vs2, xs1, vd`
    /// Rust: `vand_vx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vand_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VandVxEmitter<T0, T1, T2, T3>,
    {
        <Self as VandVxEmitter<T0, T1, T2, T3>>::vand_vx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vandn.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vandn.vv vm, vs2, vs1, vd`
    /// Rust: `vandn_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vandn_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VandnVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VandnVvEmitter<T0, T1, T2, T3>>::vandn_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vandn.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vandn.vx vm, vs2, xs1, vd`
    /// Rust: `vandn_vx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vandn_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VandnVxEmitter<T0, T1, T2, T3>,
    {
        <Self as VandnVxEmitter<T0, T1, T2, T3>>::vandn_vx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vasub.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vasub.vv vm, vs2, vs1, vd`
    /// Rust: `vasub_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vasub_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VasubVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VasubVvEmitter<T0, T1, T2, T3>>::vasub_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vasub.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vasub.vx vm, vs2, xs1, vd`
    /// Rust: `vasub_vx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vasub_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VasubVxEmitter<T0, T1, T2, T3>,
    {
        <Self as VasubVxEmitter<T0, T1, T2, T3>>::vasub_vx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vasubu.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vasubu.vv vm, vs2, vs1, vd`
    /// Rust: `vasubu_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vasubu_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VasubuVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VasubuVvEmitter<T0, T1, T2, T3>>::vasubu_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vasubu.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vasubu.vx vm, vs2, xs1, vd`
    /// Rust: `vasubu_vx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vasubu_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VasubuVxEmitter<T0, T1, T2, T3>,
    {
        <Self as VasubuVxEmitter<T0, T1, T2, T3>>::vasubu_vx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vbrev8.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vbrev8.v vm, vs2, vd`
    /// Rust: `vbrev8_v(vd, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vbrev8_v<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
    where
        Self: Vbrev8VEmitter<T0, T1, T2>,
    {
        <Self as Vbrev8VEmitter<T0, T1, T2>>::vbrev8_v(self, vd, vs2, vm);
    }
    /// RISC-V `vbrev.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vbrev.v vm, vs2, vd`
    /// Rust: `vbrev_v(vd, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vbrev_v<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
    where
        Self: VbrevVEmitter<T0, T1, T2>,
    {
        <Self as VbrevVEmitter<T0, T1, T2>>::vbrev_v(self, vd, vs2, vm);
    }
    /// RISC-V `vclmul.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vclmul.vv vm, vs2, vs1, vd`
    /// Rust: `vclmul_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vclmul_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VclmulVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VclmulVvEmitter<T0, T1, T2, T3>>::vclmul_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vclmul.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vclmul.vx vm, vs2, xs1, vd`
    /// Rust: `vclmul_vx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vclmul_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VclmulVxEmitter<T0, T1, T2, T3>,
    {
        <Self as VclmulVxEmitter<T0, T1, T2, T3>>::vclmul_vx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vclmulh.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vclmulh.vv vm, vs2, vs1, vd`
    /// Rust: `vclmulh_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vclmulh_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VclmulhVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VclmulhVvEmitter<T0, T1, T2, T3>>::vclmulh_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vclmulh.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vclmulh.vx vm, vs2, xs1, vd`
    /// Rust: `vclmulh_vx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vclmulh_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VclmulhVxEmitter<T0, T1, T2, T3>,
    {
        <Self as VclmulhVxEmitter<T0, T1, T2, T3>>::vclmulh_vx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vclz.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vclz.v vm, vs2, vd`
    /// Rust: `vclz_v(vd, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vclz_v<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
    where
        Self: VclzVEmitter<T0, T1, T2>,
    {
        <Self as VclzVEmitter<T0, T1, T2>>::vclz_v(self, vd, vs2, vm);
    }
    /// RISC-V `vcompress.vm` instruction.
    ///
    /// # Forms
    /// Assembly: `vcompress.vm vs2, vs1, vd`
    /// Rust: `vcompress_vm(vd, vs1, vs2)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    pub fn vcompress_vm<T0, T1, T2>(&mut self, vd: T0, vs1: T1, vs2: T2)
    where
        Self: VcompressVmEmitter<T0, T1, T2>,
    {
        <Self as VcompressVmEmitter<T0, T1, T2>>::vcompress_vm(self, vd, vs1, vs2);
    }
    /// RISC-V `vcpop.m` instruction.
    ///
    /// # Forms
    /// Assembly: `vcpop.m vm, vs2, xd`
    /// Rust: `vcpop_m(rd, vs2, vm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vcpop_m<T0, T1, T2>(&mut self, rd: T0, vs2: T1, vm: T2)
    where
        Self: VcpopMEmitter<T0, T1, T2>,
    {
        <Self as VcpopMEmitter<T0, T1, T2>>::vcpop_m(self, rd, vs2, vm);
    }
    /// RISC-V `vcpop.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vcpop.v vm, vs2, vd`
    /// Rust: `vcpop_v(vd, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vcpop_v<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
    where
        Self: VcpopVEmitter<T0, T1, T2>,
    {
        <Self as VcpopVEmitter<T0, T1, T2>>::vcpop_v(self, vd, vs2, vm);
    }
    /// RISC-V `vctz.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vctz.v vm, vs2, vd`
    /// Rust: `vctz_v(vd, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vctz_v<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
    where
        Self: VctzVEmitter<T0, T1, T2>,
    {
        <Self as VctzVEmitter<T0, T1, T2>>::vctz_v(self, vd, vs2, vm);
    }
    /// RISC-V `vdiv.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vdiv.vv vm, vs2, vs1, vd`
    /// Rust: `vdiv_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vdiv_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VdivVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VdivVvEmitter<T0, T1, T2, T3>>::vdiv_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vdiv.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vdiv.vx vm, vs2, xs1, vd`
    /// Rust: `vdiv_vx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vdiv_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VdivVxEmitter<T0, T1, T2, T3>,
    {
        <Self as VdivVxEmitter<T0, T1, T2, T3>>::vdiv_vx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vdivu.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vdivu.vv vm, vs2, vs1, vd`
    /// Rust: `vdivu_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vdivu_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VdivuVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VdivuVvEmitter<T0, T1, T2, T3>>::vdivu_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vdivu.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vdivu.vx vm, vs2, xs1, vd`
    /// Rust: `vdivu_vx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vdivu_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VdivuVxEmitter<T0, T1, T2, T3>,
    {
        <Self as VdivuVxEmitter<T0, T1, T2, T3>>::vdivu_vx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vfadd.vf` instruction.
    ///
    /// # Forms
    /// Assembly: `vfadd.vf vm, vs2, xs1, vd`
    /// Rust: `vfadd_vf(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vfadd_vf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VfaddVfEmitter<T0, T1, T2, T3>,
    {
        <Self as VfaddVfEmitter<T0, T1, T2, T3>>::vfadd_vf(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vfadd.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vfadd.vv vm, vs2, vs1, vd`
    /// Rust: `vfadd_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vfadd_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VfaddVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VfaddVvEmitter<T0, T1, T2, T3>>::vfadd_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vfclass.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vfclass.v vm, vs2, vd`
    /// Rust: `vfclass_v(vd, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vfclass_v<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
    where
        Self: VfclassVEmitter<T0, T1, T2>,
    {
        <Self as VfclassVEmitter<T0, T1, T2>>::vfclass_v(self, vd, vs2, vm);
    }
    /// RISC-V `vfcvt.f.x.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vfcvt.f.x.v vm, vs2, vd`
    /// Rust: `vfcvt_f_x_v(vd, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vfcvt_f_x_v<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
    where
        Self: VfcvtFXVEmitter<T0, T1, T2>,
    {
        <Self as VfcvtFXVEmitter<T0, T1, T2>>::vfcvt_f_x_v(self, vd, vs2, vm);
    }
    /// RISC-V `vfcvt.f.xu.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vfcvt.f.xu.v vm, vs2, vd`
    /// Rust: `vfcvt_f_xu_v(vd, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vfcvt_f_xu_v<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
    where
        Self: VfcvtFXuVEmitter<T0, T1, T2>,
    {
        <Self as VfcvtFXuVEmitter<T0, T1, T2>>::vfcvt_f_xu_v(self, vd, vs2, vm);
    }
    /// RISC-V `vfcvt.rtz.x.f.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vfcvt.rtz.x.f.v vm, vs2, vd`
    /// Rust: `vfcvt_rtz_x_f_v(vd, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vfcvt_rtz_x_f_v<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
    where
        Self: VfcvtRtzXFVEmitter<T0, T1, T2>,
    {
        <Self as VfcvtRtzXFVEmitter<T0, T1, T2>>::vfcvt_rtz_x_f_v(self, vd, vs2, vm);
    }
    /// RISC-V `vfcvt.rtz.xu.f.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vfcvt.rtz.xu.f.v vm, vs2, vd`
    /// Rust: `vfcvt_rtz_xu_f_v(vd, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vfcvt_rtz_xu_f_v<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
    where
        Self: VfcvtRtzXuFVEmitter<T0, T1, T2>,
    {
        <Self as VfcvtRtzXuFVEmitter<T0, T1, T2>>::vfcvt_rtz_xu_f_v(self, vd, vs2, vm);
    }
    /// RISC-V `vfcvt.x.f.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vfcvt.x.f.v vm, vs2, vd`
    /// Rust: `vfcvt_x_f_v(vd, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vfcvt_x_f_v<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
    where
        Self: VfcvtXFVEmitter<T0, T1, T2>,
    {
        <Self as VfcvtXFVEmitter<T0, T1, T2>>::vfcvt_x_f_v(self, vd, vs2, vm);
    }
    /// RISC-V `vfcvt.xu.f.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vfcvt.xu.f.v vm, vs2, vd`
    /// Rust: `vfcvt_xu_f_v(vd, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vfcvt_xu_f_v<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
    where
        Self: VfcvtXuFVEmitter<T0, T1, T2>,
    {
        <Self as VfcvtXuFVEmitter<T0, T1, T2>>::vfcvt_xu_f_v(self, vd, vs2, vm);
    }
    /// RISC-V `vfdiv.vf` instruction.
    ///
    /// # Forms
    /// Assembly: `vfdiv.vf vm, vs2, xs1, vd`
    /// Rust: `vfdiv_vf(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vfdiv_vf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VfdivVfEmitter<T0, T1, T2, T3>,
    {
        <Self as VfdivVfEmitter<T0, T1, T2, T3>>::vfdiv_vf(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vfdiv.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vfdiv.vv vm, vs2, vs1, vd`
    /// Rust: `vfdiv_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vfdiv_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VfdivVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VfdivVvEmitter<T0, T1, T2, T3>>::vfdiv_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vfirst.m` instruction.
    ///
    /// # Forms
    /// Assembly: `vfirst.m vm, vs2, xd`
    /// Rust: `vfirst_m(rd, vs2, vm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vfirst_m<T0, T1, T2>(&mut self, rd: T0, vs2: T1, vm: T2)
    where
        Self: VfirstMEmitter<T0, T1, T2>,
    {
        <Self as VfirstMEmitter<T0, T1, T2>>::vfirst_m(self, rd, vs2, vm);
    }
    /// RISC-V `vfmacc.vf` instruction.
    ///
    /// # Forms
    /// Assembly: `vfmacc.vf vm, vs2, xs1, vd`
    /// Rust: `vfmacc_vf(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vfmacc_vf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VfmaccVfEmitter<T0, T1, T2, T3>,
    {
        <Self as VfmaccVfEmitter<T0, T1, T2, T3>>::vfmacc_vf(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vfmacc.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vfmacc.vv vm, vs2, vs1, vd`
    /// Rust: `vfmacc_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vfmacc_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VfmaccVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VfmaccVvEmitter<T0, T1, T2, T3>>::vfmacc_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vfmadd.vf` instruction.
    ///
    /// # Forms
    /// Assembly: `vfmadd.vf vm, vs2, xs1, vd`
    /// Rust: `vfmadd_vf(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vfmadd_vf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VfmaddVfEmitter<T0, T1, T2, T3>,
    {
        <Self as VfmaddVfEmitter<T0, T1, T2, T3>>::vfmadd_vf(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vfmadd.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vfmadd.vv vm, vs2, vs1, vd`
    /// Rust: `vfmadd_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vfmadd_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VfmaddVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VfmaddVvEmitter<T0, T1, T2, T3>>::vfmadd_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vfmax.vf` instruction.
    ///
    /// # Forms
    /// Assembly: `vfmax.vf vm, vs2, xs1, vd`
    /// Rust: `vfmax_vf(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vfmax_vf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VfmaxVfEmitter<T0, T1, T2, T3>,
    {
        <Self as VfmaxVfEmitter<T0, T1, T2, T3>>::vfmax_vf(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vfmax.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vfmax.vv vm, vs2, vs1, vd`
    /// Rust: `vfmax_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vfmax_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VfmaxVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VfmaxVvEmitter<T0, T1, T2, T3>>::vfmax_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vfmerge.vfm` instruction.
    ///
    /// # Forms
    /// Assembly: `vfmerge.vfm vs2, xs1, vd`
    /// Rust: `vfmerge_vfm(vd, rs1, vs2)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vs2` — Vector register operand.
    pub fn vfmerge_vfm<T0, T1, T2>(&mut self, vd: T0, rs1: T1, vs2: T2)
    where
        Self: VfmergeVfmEmitter<T0, T1, T2>,
    {
        <Self as VfmergeVfmEmitter<T0, T1, T2>>::vfmerge_vfm(self, vd, rs1, vs2);
    }
    /// RISC-V `vfmin.vf` instruction.
    ///
    /// # Forms
    /// Assembly: `vfmin.vf vm, vs2, xs1, vd`
    /// Rust: `vfmin_vf(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vfmin_vf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VfminVfEmitter<T0, T1, T2, T3>,
    {
        <Self as VfminVfEmitter<T0, T1, T2, T3>>::vfmin_vf(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vfmin.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vfmin.vv vm, vs2, vs1, vd`
    /// Rust: `vfmin_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vfmin_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VfminVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VfminVvEmitter<T0, T1, T2, T3>>::vfmin_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vfmsac.vf` instruction.
    ///
    /// # Forms
    /// Assembly: `vfmsac.vf vm, vs2, xs1, vd`
    /// Rust: `vfmsac_vf(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vfmsac_vf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VfmsacVfEmitter<T0, T1, T2, T3>,
    {
        <Self as VfmsacVfEmitter<T0, T1, T2, T3>>::vfmsac_vf(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vfmsac.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vfmsac.vv vm, vs2, vs1, vd`
    /// Rust: `vfmsac_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vfmsac_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VfmsacVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VfmsacVvEmitter<T0, T1, T2, T3>>::vfmsac_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vfmsub.vf` instruction.
    ///
    /// # Forms
    /// Assembly: `vfmsub.vf vm, vs2, xs1, vd`
    /// Rust: `vfmsub_vf(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vfmsub_vf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VfmsubVfEmitter<T0, T1, T2, T3>,
    {
        <Self as VfmsubVfEmitter<T0, T1, T2, T3>>::vfmsub_vf(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vfmsub.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vfmsub.vv vm, vs2, vs1, vd`
    /// Rust: `vfmsub_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vfmsub_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VfmsubVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VfmsubVvEmitter<T0, T1, T2, T3>>::vfmsub_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vfmul.vf` instruction.
    ///
    /// # Forms
    /// Assembly: `vfmul.vf vm, vs2, xs1, vd`
    /// Rust: `vfmul_vf(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vfmul_vf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VfmulVfEmitter<T0, T1, T2, T3>,
    {
        <Self as VfmulVfEmitter<T0, T1, T2, T3>>::vfmul_vf(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vfmul.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vfmul.vv vm, vs2, vs1, vd`
    /// Rust: `vfmul_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vfmul_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VfmulVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VfmulVvEmitter<T0, T1, T2, T3>>::vfmul_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vfmv.f.s` instruction.
    ///
    /// # Forms
    /// Assembly: `vfmv.f.s vs2, xd`
    /// Rust: `vfmv_f_s(rd, vs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `vs2` — Vector register operand.
    pub fn vfmv_f_s<T0, T1>(&mut self, rd: T0, vs2: T1)
    where
        Self: VfmvFSEmitter<T0, T1>,
    {
        <Self as VfmvFSEmitter<T0, T1>>::vfmv_f_s(self, rd, vs2);
    }
    /// RISC-V `vfmv.s.f` instruction.
    ///
    /// # Forms
    /// Assembly: `vfmv.s.f xs1, vd`
    /// Rust: `vfmv_s_f(vd, rs1)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `rs1` — Source register.
    pub fn vfmv_s_f<T0, T1>(&mut self, vd: T0, rs1: T1)
    where
        Self: VfmvSFEmitter<T0, T1>,
    {
        <Self as VfmvSFEmitter<T0, T1>>::vfmv_s_f(self, vd, rs1);
    }
    /// RISC-V `vfmv.v.f` instruction.
    ///
    /// # Forms
    /// Assembly: `vfmv.v.f xs1, vd`
    /// Rust: `vfmv_v_f(vd, rs1)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `rs1` — Source register.
    pub fn vfmv_v_f<T0, T1>(&mut self, vd: T0, rs1: T1)
    where
        Self: VfmvVFEmitter<T0, T1>,
    {
        <Self as VfmvVFEmitter<T0, T1>>::vfmv_v_f(self, vd, rs1);
    }
    /// RISC-V `vfncvt.f.f.w` instruction.
    ///
    /// # Forms
    /// Assembly: `vfncvt.f.f.w vm, vs2, vd`
    /// Rust: `vfncvt_f_f_w(vd, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vfncvt_f_f_w<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
    where
        Self: VfncvtFFWEmitter<T0, T1, T2>,
    {
        <Self as VfncvtFFWEmitter<T0, T1, T2>>::vfncvt_f_f_w(self, vd, vs2, vm);
    }
    /// RISC-V `vfncvt.f.x.w` instruction.
    ///
    /// # Forms
    /// Assembly: `vfncvt.f.x.w vm, vs2, vd`
    /// Rust: `vfncvt_f_x_w(vd, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vfncvt_f_x_w<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
    where
        Self: VfncvtFXWEmitter<T0, T1, T2>,
    {
        <Self as VfncvtFXWEmitter<T0, T1, T2>>::vfncvt_f_x_w(self, vd, vs2, vm);
    }
    /// RISC-V `vfncvt.f.xu.w` instruction.
    ///
    /// # Forms
    /// Assembly: `vfncvt.f.xu.w vm, vs2, vd`
    /// Rust: `vfncvt_f_xu_w(vd, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vfncvt_f_xu_w<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
    where
        Self: VfncvtFXuWEmitter<T0, T1, T2>,
    {
        <Self as VfncvtFXuWEmitter<T0, T1, T2>>::vfncvt_f_xu_w(self, vd, vs2, vm);
    }
    /// RISC-V `vfncvt.rod.f.f.w` instruction.
    ///
    /// # Forms
    /// Assembly: `vfncvt.rod.f.f.w vm, vs2, vd`
    /// Rust: `vfncvt_rod_f_f_w(vd, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vfncvt_rod_f_f_w<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
    where
        Self: VfncvtRodFFWEmitter<T0, T1, T2>,
    {
        <Self as VfncvtRodFFWEmitter<T0, T1, T2>>::vfncvt_rod_f_f_w(self, vd, vs2, vm);
    }
    /// RISC-V `vfncvt.rtz.x.f.w` instruction.
    ///
    /// # Forms
    /// Assembly: `vfncvt.rtz.x.f.w vm, vs2, vd`
    /// Rust: `vfncvt_rtz_x_f_w(vd, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vfncvt_rtz_x_f_w<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
    where
        Self: VfncvtRtzXFWEmitter<T0, T1, T2>,
    {
        <Self as VfncvtRtzXFWEmitter<T0, T1, T2>>::vfncvt_rtz_x_f_w(self, vd, vs2, vm);
    }
    /// RISC-V `vfncvt.rtz.xu.f.w` instruction.
    ///
    /// # Forms
    /// Assembly: `vfncvt.rtz.xu.f.w vm, vs2, vd`
    /// Rust: `vfncvt_rtz_xu_f_w(vd, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vfncvt_rtz_xu_f_w<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
    where
        Self: VfncvtRtzXuFWEmitter<T0, T1, T2>,
    {
        <Self as VfncvtRtzXuFWEmitter<T0, T1, T2>>::vfncvt_rtz_xu_f_w(self, vd, vs2, vm);
    }
    /// RISC-V `vfncvt.x.f.w` instruction.
    ///
    /// # Forms
    /// Assembly: `vfncvt.x.f.w vm, vs2, vd`
    /// Rust: `vfncvt_x_f_w(vd, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vfncvt_x_f_w<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
    where
        Self: VfncvtXFWEmitter<T0, T1, T2>,
    {
        <Self as VfncvtXFWEmitter<T0, T1, T2>>::vfncvt_x_f_w(self, vd, vs2, vm);
    }
    /// RISC-V `vfncvt.xu.f.w` instruction.
    ///
    /// # Forms
    /// Assembly: `vfncvt.xu.f.w vm, vs2, vd`
    /// Rust: `vfncvt_xu_f_w(vd, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vfncvt_xu_f_w<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
    where
        Self: VfncvtXuFWEmitter<T0, T1, T2>,
    {
        <Self as VfncvtXuFWEmitter<T0, T1, T2>>::vfncvt_xu_f_w(self, vd, vs2, vm);
    }
    /// RISC-V `vfncvtbf16.f.f.w` instruction.
    ///
    /// # Forms
    /// Assembly: `vfncvtbf16.f.f.w vm, vs2, vd`
    /// Rust: `vfncvtbf16_f_f_w(vd, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vfncvtbf16_f_f_w<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
    where
        Self: Vfncvtbf16FFWEmitter<T0, T1, T2>,
    {
        <Self as Vfncvtbf16FFWEmitter<T0, T1, T2>>::vfncvtbf16_f_f_w(self, vd, vs2, vm);
    }
    /// RISC-V `vfnmacc.vf` instruction.
    ///
    /// # Forms
    /// Assembly: `vfnmacc.vf vm, vs2, xs1, vd`
    /// Rust: `vfnmacc_vf(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vfnmacc_vf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VfnmaccVfEmitter<T0, T1, T2, T3>,
    {
        <Self as VfnmaccVfEmitter<T0, T1, T2, T3>>::vfnmacc_vf(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vfnmacc.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vfnmacc.vv vm, vs2, vs1, vd`
    /// Rust: `vfnmacc_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vfnmacc_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VfnmaccVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VfnmaccVvEmitter<T0, T1, T2, T3>>::vfnmacc_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vfnmadd.vf` instruction.
    ///
    /// # Forms
    /// Assembly: `vfnmadd.vf vm, vs2, xs1, vd`
    /// Rust: `vfnmadd_vf(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vfnmadd_vf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VfnmaddVfEmitter<T0, T1, T2, T3>,
    {
        <Self as VfnmaddVfEmitter<T0, T1, T2, T3>>::vfnmadd_vf(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vfnmadd.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vfnmadd.vv vm, vs2, vs1, vd`
    /// Rust: `vfnmadd_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vfnmadd_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VfnmaddVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VfnmaddVvEmitter<T0, T1, T2, T3>>::vfnmadd_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vfnmsac.vf` instruction.
    ///
    /// # Forms
    /// Assembly: `vfnmsac.vf vm, vs2, xs1, vd`
    /// Rust: `vfnmsac_vf(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vfnmsac_vf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VfnmsacVfEmitter<T0, T1, T2, T3>,
    {
        <Self as VfnmsacVfEmitter<T0, T1, T2, T3>>::vfnmsac_vf(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vfnmsac.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vfnmsac.vv vm, vs2, vs1, vd`
    /// Rust: `vfnmsac_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vfnmsac_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VfnmsacVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VfnmsacVvEmitter<T0, T1, T2, T3>>::vfnmsac_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vfnmsub.vf` instruction.
    ///
    /// # Forms
    /// Assembly: `vfnmsub.vf vm, vs2, xs1, vd`
    /// Rust: `vfnmsub_vf(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vfnmsub_vf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VfnmsubVfEmitter<T0, T1, T2, T3>,
    {
        <Self as VfnmsubVfEmitter<T0, T1, T2, T3>>::vfnmsub_vf(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vfnmsub.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vfnmsub.vv vm, vs2, vs1, vd`
    /// Rust: `vfnmsub_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vfnmsub_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VfnmsubVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VfnmsubVvEmitter<T0, T1, T2, T3>>::vfnmsub_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vfrdiv.vf` instruction.
    ///
    /// # Forms
    /// Assembly: `vfrdiv.vf vm, vs2, xs1, vd`
    /// Rust: `vfrdiv_vf(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vfrdiv_vf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VfrdivVfEmitter<T0, T1, T2, T3>,
    {
        <Self as VfrdivVfEmitter<T0, T1, T2, T3>>::vfrdiv_vf(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vfrec7.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vfrec7.v vm, vs2, vd`
    /// Rust: `vfrec7_v(vd, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vfrec7_v<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
    where
        Self: Vfrec7VEmitter<T0, T1, T2>,
    {
        <Self as Vfrec7VEmitter<T0, T1, T2>>::vfrec7_v(self, vd, vs2, vm);
    }
    /// RISC-V `vfredmax.vs` instruction.
    ///
    /// # Forms
    /// Assembly: `vfredmax.vs vm, vs2, vs1, vd`
    /// Rust: `vfredmax_vs(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vfredmax_vs<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VfredmaxVsEmitter<T0, T1, T2, T3>,
    {
        <Self as VfredmaxVsEmitter<T0, T1, T2, T3>>::vfredmax_vs(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vfredmin.vs` instruction.
    ///
    /// # Forms
    /// Assembly: `vfredmin.vs vm, vs2, vs1, vd`
    /// Rust: `vfredmin_vs(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vfredmin_vs<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VfredminVsEmitter<T0, T1, T2, T3>,
    {
        <Self as VfredminVsEmitter<T0, T1, T2, T3>>::vfredmin_vs(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vfredosum.vs` instruction.
    ///
    /// # Forms
    /// Assembly: `vfredosum.vs vm, vs2, vs1, vd`
    /// Rust: `vfredosum_vs(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vfredosum_vs<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VfredosumVsEmitter<T0, T1, T2, T3>,
    {
        <Self as VfredosumVsEmitter<T0, T1, T2, T3>>::vfredosum_vs(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vfredsum.vs` instruction.
    ///
    /// # Forms
    /// Assembly: `vfredsum.vs vd vs1 vs2 vm`
    /// Rust: `vfredsum_vs(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vfredsum_vs<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VfredsumVsEmitter<T0, T1, T2, T3>,
    {
        <Self as VfredsumVsEmitter<T0, T1, T2, T3>>::vfredsum_vs(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vfredusum.vs` instruction.
    ///
    /// # Forms
    /// Assembly: `vfredusum.vs vm, vs2, vs1, vd`
    /// Rust: `vfredusum_vs(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vfredusum_vs<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VfredusumVsEmitter<T0, T1, T2, T3>,
    {
        <Self as VfredusumVsEmitter<T0, T1, T2, T3>>::vfredusum_vs(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vfrsqrt7.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vfrsqrt7.v vm, vs2, vd`
    /// Rust: `vfrsqrt7_v(vd, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vfrsqrt7_v<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
    where
        Self: Vfrsqrt7VEmitter<T0, T1, T2>,
    {
        <Self as Vfrsqrt7VEmitter<T0, T1, T2>>::vfrsqrt7_v(self, vd, vs2, vm);
    }
    /// RISC-V `vfrsub.vf` instruction.
    ///
    /// # Forms
    /// Assembly: `vfrsub.vf vm, vs2, xs1, vd`
    /// Rust: `vfrsub_vf(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vfrsub_vf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VfrsubVfEmitter<T0, T1, T2, T3>,
    {
        <Self as VfrsubVfEmitter<T0, T1, T2, T3>>::vfrsub_vf(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vfsgnj.vf` instruction.
    ///
    /// # Forms
    /// Assembly: `vfsgnj.vf vm, vs2, xs1, vd`
    /// Rust: `vfsgnj_vf(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vfsgnj_vf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VfsgnjVfEmitter<T0, T1, T2, T3>,
    {
        <Self as VfsgnjVfEmitter<T0, T1, T2, T3>>::vfsgnj_vf(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vfsgnj.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vfsgnj.vv vm, vs2, vs1, vd`
    /// Rust: `vfsgnj_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vfsgnj_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VfsgnjVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VfsgnjVvEmitter<T0, T1, T2, T3>>::vfsgnj_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vfsgnjn.vf` instruction.
    ///
    /// # Forms
    /// Assembly: `vfsgnjn.vf vm, vs2, xs1, vd`
    /// Rust: `vfsgnjn_vf(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vfsgnjn_vf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VfsgnjnVfEmitter<T0, T1, T2, T3>,
    {
        <Self as VfsgnjnVfEmitter<T0, T1, T2, T3>>::vfsgnjn_vf(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vfsgnjn.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vfsgnjn.vv vm, vs2, vs1, vd`
    /// Rust: `vfsgnjn_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vfsgnjn_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VfsgnjnVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VfsgnjnVvEmitter<T0, T1, T2, T3>>::vfsgnjn_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vfsgnjx.vf` instruction.
    ///
    /// # Forms
    /// Assembly: `vfsgnjx.vf vm, vs2, xs1, vd`
    /// Rust: `vfsgnjx_vf(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vfsgnjx_vf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VfsgnjxVfEmitter<T0, T1, T2, T3>,
    {
        <Self as VfsgnjxVfEmitter<T0, T1, T2, T3>>::vfsgnjx_vf(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vfsgnjx.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vfsgnjx.vv vm, vs2, vs1, vd`
    /// Rust: `vfsgnjx_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vfsgnjx_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VfsgnjxVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VfsgnjxVvEmitter<T0, T1, T2, T3>>::vfsgnjx_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vfslide1down.vf` instruction.
    ///
    /// # Forms
    /// Assembly: `vfslide1down.vf vm, vs2, xs1, vd`
    /// Rust: `vfslide1down_vf(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vfslide1down_vf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: Vfslide1DownVfEmitter<T0, T1, T2, T3>,
    {
        <Self as Vfslide1DownVfEmitter<T0, T1, T2, T3>>::vfslide1down_vf(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vfslide1up.vf` instruction.
    ///
    /// # Forms
    /// Assembly: `vfslide1up.vf vm, vs2, xs1, vd`
    /// Rust: `vfslide1up_vf(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vfslide1up_vf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: Vfslide1UpVfEmitter<T0, T1, T2, T3>,
    {
        <Self as Vfslide1UpVfEmitter<T0, T1, T2, T3>>::vfslide1up_vf(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vfsqrt.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vfsqrt.v vm, vs2, vd`
    /// Rust: `vfsqrt_v(vd, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vfsqrt_v<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
    where
        Self: VfsqrtVEmitter<T0, T1, T2>,
    {
        <Self as VfsqrtVEmitter<T0, T1, T2>>::vfsqrt_v(self, vd, vs2, vm);
    }
    /// RISC-V `vfsub.vf` instruction.
    ///
    /// # Forms
    /// Assembly: `vfsub.vf vm, vs2, xs1, vd`
    /// Rust: `vfsub_vf(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vfsub_vf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VfsubVfEmitter<T0, T1, T2, T3>,
    {
        <Self as VfsubVfEmitter<T0, T1, T2, T3>>::vfsub_vf(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vfsub.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vfsub.vv vm, vs2, vs1, vd`
    /// Rust: `vfsub_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vfsub_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VfsubVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VfsubVvEmitter<T0, T1, T2, T3>>::vfsub_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vfwadd.vf` instruction.
    ///
    /// # Forms
    /// Assembly: `vfwadd.vf vm, vs2, xs1, vd`
    /// Rust: `vfwadd_vf(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vfwadd_vf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VfwaddVfEmitter<T0, T1, T2, T3>,
    {
        <Self as VfwaddVfEmitter<T0, T1, T2, T3>>::vfwadd_vf(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vfwadd.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vfwadd.vv vm, vs2, vs1, vd`
    /// Rust: `vfwadd_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vfwadd_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VfwaddVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VfwaddVvEmitter<T0, T1, T2, T3>>::vfwadd_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vfwadd.wf` instruction.
    ///
    /// # Forms
    /// Assembly: `vfwadd.wf vm, vs2, xs1, vd`
    /// Rust: `vfwadd_wf(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vfwadd_wf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VfwaddWfEmitter<T0, T1, T2, T3>,
    {
        <Self as VfwaddWfEmitter<T0, T1, T2, T3>>::vfwadd_wf(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vfwadd.wv` instruction.
    ///
    /// # Forms
    /// Assembly: `vfwadd.wv vm, vs2, vs1, vd`
    /// Rust: `vfwadd_wv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vfwadd_wv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VfwaddWvEmitter<T0, T1, T2, T3>,
    {
        <Self as VfwaddWvEmitter<T0, T1, T2, T3>>::vfwadd_wv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vfwcvt.f.f.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vfwcvt.f.f.v vm, vs2, vd`
    /// Rust: `vfwcvt_f_f_v(vd, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vfwcvt_f_f_v<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
    where
        Self: VfwcvtFFVEmitter<T0, T1, T2>,
    {
        <Self as VfwcvtFFVEmitter<T0, T1, T2>>::vfwcvt_f_f_v(self, vd, vs2, vm);
    }
    /// RISC-V `vfwcvt.f.x.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vfwcvt.f.x.v vm, vs2, vd`
    /// Rust: `vfwcvt_f_x_v(vd, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vfwcvt_f_x_v<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
    where
        Self: VfwcvtFXVEmitter<T0, T1, T2>,
    {
        <Self as VfwcvtFXVEmitter<T0, T1, T2>>::vfwcvt_f_x_v(self, vd, vs2, vm);
    }
    /// RISC-V `vfwcvt.f.xu.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vfwcvt.f.xu.v vm, vs2, vd`
    /// Rust: `vfwcvt_f_xu_v(vd, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vfwcvt_f_xu_v<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
    where
        Self: VfwcvtFXuVEmitter<T0, T1, T2>,
    {
        <Self as VfwcvtFXuVEmitter<T0, T1, T2>>::vfwcvt_f_xu_v(self, vd, vs2, vm);
    }
    /// RISC-V `vfwcvt.rtz.x.f.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vfwcvt.rtz.x.f.v vm, vs2, vd`
    /// Rust: `vfwcvt_rtz_x_f_v(vd, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vfwcvt_rtz_x_f_v<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
    where
        Self: VfwcvtRtzXFVEmitter<T0, T1, T2>,
    {
        <Self as VfwcvtRtzXFVEmitter<T0, T1, T2>>::vfwcvt_rtz_x_f_v(self, vd, vs2, vm);
    }
    /// RISC-V `vfwcvt.rtz.xu.f.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vfwcvt.rtz.xu.f.v vm, vs2, vd`
    /// Rust: `vfwcvt_rtz_xu_f_v(vd, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vfwcvt_rtz_xu_f_v<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
    where
        Self: VfwcvtRtzXuFVEmitter<T0, T1, T2>,
    {
        <Self as VfwcvtRtzXuFVEmitter<T0, T1, T2>>::vfwcvt_rtz_xu_f_v(self, vd, vs2, vm);
    }
    /// RISC-V `vfwcvt.x.f.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vfwcvt.x.f.v vm, vs2, vd`
    /// Rust: `vfwcvt_x_f_v(vd, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vfwcvt_x_f_v<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
    where
        Self: VfwcvtXFVEmitter<T0, T1, T2>,
    {
        <Self as VfwcvtXFVEmitter<T0, T1, T2>>::vfwcvt_x_f_v(self, vd, vs2, vm);
    }
    /// RISC-V `vfwcvt.xu.f.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vfwcvt.xu.f.v vm, vs2, vd`
    /// Rust: `vfwcvt_xu_f_v(vd, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vfwcvt_xu_f_v<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
    where
        Self: VfwcvtXuFVEmitter<T0, T1, T2>,
    {
        <Self as VfwcvtXuFVEmitter<T0, T1, T2>>::vfwcvt_xu_f_v(self, vd, vs2, vm);
    }
    /// RISC-V `vfwcvtbf16.f.f.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vfwcvtbf16.f.f.v vm, vs2, vd`
    /// Rust: `vfwcvtbf16_f_f_v(vd, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vfwcvtbf16_f_f_v<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
    where
        Self: Vfwcvtbf16FFVEmitter<T0, T1, T2>,
    {
        <Self as Vfwcvtbf16FFVEmitter<T0, T1, T2>>::vfwcvtbf16_f_f_v(self, vd, vs2, vm);
    }
    /// RISC-V `vfwmacc.vf` instruction.
    ///
    /// # Forms
    /// Assembly: `vfwmacc.vf vm, vs2, xs1, vd`
    /// Rust: `vfwmacc_vf(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vfwmacc_vf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VfwmaccVfEmitter<T0, T1, T2, T3>,
    {
        <Self as VfwmaccVfEmitter<T0, T1, T2, T3>>::vfwmacc_vf(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vfwmacc.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vfwmacc.vv vm, vs2, vs1, vd`
    /// Rust: `vfwmacc_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vfwmacc_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VfwmaccVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VfwmaccVvEmitter<T0, T1, T2, T3>>::vfwmacc_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vfwmaccbf16.vf` instruction.
    ///
    /// # Forms
    /// Assembly: `vfwmaccbf16.vf vm, vs2, xs1, vd`
    /// Rust: `vfwmaccbf16_vf(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vfwmaccbf16_vf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: Vfwmaccbf16VfEmitter<T0, T1, T2, T3>,
    {
        <Self as Vfwmaccbf16VfEmitter<T0, T1, T2, T3>>::vfwmaccbf16_vf(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vfwmaccbf16.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vfwmaccbf16.vv vm, vs2, vs1, vd`
    /// Rust: `vfwmaccbf16_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vfwmaccbf16_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: Vfwmaccbf16VvEmitter<T0, T1, T2, T3>,
    {
        <Self as Vfwmaccbf16VvEmitter<T0, T1, T2, T3>>::vfwmaccbf16_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vfwmsac.vf` instruction.
    ///
    /// # Forms
    /// Assembly: `vfwmsac.vf vm, vs2, xs1, vd`
    /// Rust: `vfwmsac_vf(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vfwmsac_vf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VfwmsacVfEmitter<T0, T1, T2, T3>,
    {
        <Self as VfwmsacVfEmitter<T0, T1, T2, T3>>::vfwmsac_vf(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vfwmsac.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vfwmsac.vv vm, vs2, vs1, vd`
    /// Rust: `vfwmsac_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vfwmsac_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VfwmsacVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VfwmsacVvEmitter<T0, T1, T2, T3>>::vfwmsac_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vfwmul.vf` instruction.
    ///
    /// # Forms
    /// Assembly: `vfwmul.vf vm, vs2, xs1, vd`
    /// Rust: `vfwmul_vf(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vfwmul_vf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VfwmulVfEmitter<T0, T1, T2, T3>,
    {
        <Self as VfwmulVfEmitter<T0, T1, T2, T3>>::vfwmul_vf(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vfwmul.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vfwmul.vv vm, vs2, vs1, vd`
    /// Rust: `vfwmul_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vfwmul_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VfwmulVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VfwmulVvEmitter<T0, T1, T2, T3>>::vfwmul_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vfwnmacc.vf` instruction.
    ///
    /// # Forms
    /// Assembly: `vfwnmacc.vf vm, vs2, xs1, vd`
    /// Rust: `vfwnmacc_vf(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vfwnmacc_vf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VfwnmaccVfEmitter<T0, T1, T2, T3>,
    {
        <Self as VfwnmaccVfEmitter<T0, T1, T2, T3>>::vfwnmacc_vf(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vfwnmacc.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vfwnmacc.vv vm, vs2, vs1, vd`
    /// Rust: `vfwnmacc_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vfwnmacc_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VfwnmaccVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VfwnmaccVvEmitter<T0, T1, T2, T3>>::vfwnmacc_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vfwnmsac.vf` instruction.
    ///
    /// # Forms
    /// Assembly: `vfwnmsac.vf vm, vs2, xs1, vd`
    /// Rust: `vfwnmsac_vf(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vfwnmsac_vf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VfwnmsacVfEmitter<T0, T1, T2, T3>,
    {
        <Self as VfwnmsacVfEmitter<T0, T1, T2, T3>>::vfwnmsac_vf(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vfwnmsac.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vfwnmsac.vv vm, vs2, vs1, vd`
    /// Rust: `vfwnmsac_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vfwnmsac_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VfwnmsacVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VfwnmsacVvEmitter<T0, T1, T2, T3>>::vfwnmsac_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vfwredosum.vs` instruction.
    ///
    /// # Forms
    /// Assembly: `vfwredosum.vs vm, vs2, vs1, vd`
    /// Rust: `vfwredosum_vs(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vfwredosum_vs<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VfwredosumVsEmitter<T0, T1, T2, T3>,
    {
        <Self as VfwredosumVsEmitter<T0, T1, T2, T3>>::vfwredosum_vs(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vfwredsum.vs` instruction.
    ///
    /// # Forms
    /// Assembly: `vfwredsum.vs vd vs1 vs2 vm`
    /// Rust: `vfwredsum_vs(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vfwredsum_vs<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VfwredsumVsEmitter<T0, T1, T2, T3>,
    {
        <Self as VfwredsumVsEmitter<T0, T1, T2, T3>>::vfwredsum_vs(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vfwredusum.vs` instruction.
    ///
    /// # Forms
    /// Assembly: `vfwredusum.vs vm, vs2, vs1, vd`
    /// Rust: `vfwredusum_vs(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vfwredusum_vs<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VfwredusumVsEmitter<T0, T1, T2, T3>,
    {
        <Self as VfwredusumVsEmitter<T0, T1, T2, T3>>::vfwredusum_vs(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vfwsub.vf` instruction.
    ///
    /// # Forms
    /// Assembly: `vfwsub.vf vm, vs2, xs1, vd`
    /// Rust: `vfwsub_vf(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vfwsub_vf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VfwsubVfEmitter<T0, T1, T2, T3>,
    {
        <Self as VfwsubVfEmitter<T0, T1, T2, T3>>::vfwsub_vf(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vfwsub.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vfwsub.vv vm, vs2, vs1, vd`
    /// Rust: `vfwsub_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vfwsub_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VfwsubVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VfwsubVvEmitter<T0, T1, T2, T3>>::vfwsub_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vfwsub.wf` instruction.
    ///
    /// # Forms
    /// Assembly: `vfwsub.wf vm, vs2, xs1, vd`
    /// Rust: `vfwsub_wf(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vfwsub_wf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VfwsubWfEmitter<T0, T1, T2, T3>,
    {
        <Self as VfwsubWfEmitter<T0, T1, T2, T3>>::vfwsub_wf(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vfwsub.wv` instruction.
    ///
    /// # Forms
    /// Assembly: `vfwsub.wv vm, vs2, vs1, vd`
    /// Rust: `vfwsub_wv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vfwsub_wv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VfwsubWvEmitter<T0, T1, T2, T3>,
    {
        <Self as VfwsubWvEmitter<T0, T1, T2, T3>>::vfwsub_wv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vghsh.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vghsh.vv vs2, vs1, vd`
    /// Rust: `vghsh_vv(vd, vs1, vs2)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    pub fn vghsh_vv<T0, T1, T2>(&mut self, vd: T0, vs1: T1, vs2: T2)
    where
        Self: VghshVvEmitter<T0, T1, T2>,
    {
        <Self as VghshVvEmitter<T0, T1, T2>>::vghsh_vv(self, vd, vs1, vs2);
    }
    /// RISC-V `vgmul.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vgmul.vv vs2, vd`
    /// Rust: `vgmul_vv(vd, vs2)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    pub fn vgmul_vv<T0, T1>(&mut self, vd: T0, vs2: T1)
    where
        Self: VgmulVvEmitter<T0, T1>,
    {
        <Self as VgmulVvEmitter<T0, T1>>::vgmul_vv(self, vd, vs2);
    }
    /// RISC-V `vid.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vid.v vm, vd`
    /// Rust: `vid_v(vd, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vid_v<T0, T1>(&mut self, vd: T0, vm: T1)
    where
        Self: VidVEmitter<T0, T1>,
    {
        <Self as VidVEmitter<T0, T1>>::vid_v(self, vd, vm);
    }
    /// RISC-V `viota.m` instruction.
    ///
    /// # Forms
    /// Assembly: `viota.m vm, vs2, vd`
    /// Rust: `viota_m(vd, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn viota_m<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
    where
        Self: ViotaMEmitter<T0, T1, T2>,
    {
        <Self as ViotaMEmitter<T0, T1, T2>>::viota_m(self, vd, vs2, vm);
    }
    /// RISC-V `vl1r.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vl1r.v vd rs1`
    /// Rust: `vl1r_v(vd, rs1)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `rs1` — Memory base register.
    pub fn vl1r_v<T0, T1>(&mut self, vd: T0, rs1: T1)
    where
        Self: Vl1RVEmitter<T0, T1>,
    {
        <Self as Vl1RVEmitter<T0, T1>>::vl1r_v(self, vd, rs1);
    }
    /// RISC-V `vl1re16.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vl1re16.v xs1, vd`
    /// Rust: `vl1re16_v(vd, rs1)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `rs1` — Memory base register.
    pub fn vl1re16_v<T0, T1>(&mut self, vd: T0, rs1: T1)
    where
        Self: Vl1Re16VEmitter<T0, T1>,
    {
        <Self as Vl1Re16VEmitter<T0, T1>>::vl1re16_v(self, vd, rs1);
    }
    /// RISC-V `vl1re32.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vl1re32.v xs1, vd`
    /// Rust: `vl1re32_v(vd, rs1)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `rs1` — Memory base register.
    pub fn vl1re32_v<T0, T1>(&mut self, vd: T0, rs1: T1)
    where
        Self: Vl1Re32VEmitter<T0, T1>,
    {
        <Self as Vl1Re32VEmitter<T0, T1>>::vl1re32_v(self, vd, rs1);
    }
    /// RISC-V `vl1re64.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vl1re64.v xs1, vd`
    /// Rust: `vl1re64_v(vd, rs1)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `rs1` — Memory base register.
    pub fn vl1re64_v<T0, T1>(&mut self, vd: T0, rs1: T1)
    where
        Self: Vl1Re64VEmitter<T0, T1>,
    {
        <Self as Vl1Re64VEmitter<T0, T1>>::vl1re64_v(self, vd, rs1);
    }
    /// RISC-V `vl1re8.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vl1re8.v xs1, vd`
    /// Rust: `vl1re8_v(vd, rs1)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `rs1` — Memory base register.
    pub fn vl1re8_v<T0, T1>(&mut self, vd: T0, rs1: T1)
    where
        Self: Vl1Re8VEmitter<T0, T1>,
    {
        <Self as Vl1Re8VEmitter<T0, T1>>::vl1re8_v(self, vd, rs1);
    }
    /// RISC-V `vl2r.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vl2r.v vd rs1`
    /// Rust: `vl2r_v(vd, rs1)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `rs1` — Memory base register.
    pub fn vl2r_v<T0, T1>(&mut self, vd: T0, rs1: T1)
    where
        Self: Vl2RVEmitter<T0, T1>,
    {
        <Self as Vl2RVEmitter<T0, T1>>::vl2r_v(self, vd, rs1);
    }
    /// RISC-V `vl2re16.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vl2re16.v xs1, vd`
    /// Rust: `vl2re16_v(vd, rs1)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `rs1` — Memory base register.
    pub fn vl2re16_v<T0, T1>(&mut self, vd: T0, rs1: T1)
    where
        Self: Vl2Re16VEmitter<T0, T1>,
    {
        <Self as Vl2Re16VEmitter<T0, T1>>::vl2re16_v(self, vd, rs1);
    }
    /// RISC-V `vl2re32.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vl2re32.v xs1, vd`
    /// Rust: `vl2re32_v(vd, rs1)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `rs1` — Memory base register.
    pub fn vl2re32_v<T0, T1>(&mut self, vd: T0, rs1: T1)
    where
        Self: Vl2Re32VEmitter<T0, T1>,
    {
        <Self as Vl2Re32VEmitter<T0, T1>>::vl2re32_v(self, vd, rs1);
    }
    /// RISC-V `vl2re64.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vl2re64.v xs1, vd`
    /// Rust: `vl2re64_v(vd, rs1)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `rs1` — Memory base register.
    pub fn vl2re64_v<T0, T1>(&mut self, vd: T0, rs1: T1)
    where
        Self: Vl2Re64VEmitter<T0, T1>,
    {
        <Self as Vl2Re64VEmitter<T0, T1>>::vl2re64_v(self, vd, rs1);
    }
    /// RISC-V `vl2re8.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vl2re8.v xs1, vd`
    /// Rust: `vl2re8_v(vd, rs1)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `rs1` — Memory base register.
    pub fn vl2re8_v<T0, T1>(&mut self, vd: T0, rs1: T1)
    where
        Self: Vl2Re8VEmitter<T0, T1>,
    {
        <Self as Vl2Re8VEmitter<T0, T1>>::vl2re8_v(self, vd, rs1);
    }
    /// RISC-V `vl4r.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vl4r.v vd rs1`
    /// Rust: `vl4r_v(vd, rs1)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `rs1` — Memory base register.
    pub fn vl4r_v<T0, T1>(&mut self, vd: T0, rs1: T1)
    where
        Self: Vl4RVEmitter<T0, T1>,
    {
        <Self as Vl4RVEmitter<T0, T1>>::vl4r_v(self, vd, rs1);
    }
    /// RISC-V `vl4re16.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vl4re16.v xs1, vd`
    /// Rust: `vl4re16_v(vd, rs1)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `rs1` — Memory base register.
    pub fn vl4re16_v<T0, T1>(&mut self, vd: T0, rs1: T1)
    where
        Self: Vl4Re16VEmitter<T0, T1>,
    {
        <Self as Vl4Re16VEmitter<T0, T1>>::vl4re16_v(self, vd, rs1);
    }
    /// RISC-V `vl4re32.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vl4re32.v xs1, vd`
    /// Rust: `vl4re32_v(vd, rs1)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `rs1` — Memory base register.
    pub fn vl4re32_v<T0, T1>(&mut self, vd: T0, rs1: T1)
    where
        Self: Vl4Re32VEmitter<T0, T1>,
    {
        <Self as Vl4Re32VEmitter<T0, T1>>::vl4re32_v(self, vd, rs1);
    }
    /// RISC-V `vl4re64.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vl4re64.v xs1, vd`
    /// Rust: `vl4re64_v(vd, rs1)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `rs1` — Memory base register.
    pub fn vl4re64_v<T0, T1>(&mut self, vd: T0, rs1: T1)
    where
        Self: Vl4Re64VEmitter<T0, T1>,
    {
        <Self as Vl4Re64VEmitter<T0, T1>>::vl4re64_v(self, vd, rs1);
    }
    /// RISC-V `vl4re8.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vl4re8.v xs1, vd`
    /// Rust: `vl4re8_v(vd, rs1)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `rs1` — Memory base register.
    pub fn vl4re8_v<T0, T1>(&mut self, vd: T0, rs1: T1)
    where
        Self: Vl4Re8VEmitter<T0, T1>,
    {
        <Self as Vl4Re8VEmitter<T0, T1>>::vl4re8_v(self, vd, rs1);
    }
    /// RISC-V `vl8r.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vl8r.v vd rs1`
    /// Rust: `vl8r_v(vd, rs1)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `rs1` — Memory base register.
    pub fn vl8r_v<T0, T1>(&mut self, vd: T0, rs1: T1)
    where
        Self: Vl8RVEmitter<T0, T1>,
    {
        <Self as Vl8RVEmitter<T0, T1>>::vl8r_v(self, vd, rs1);
    }
    /// RISC-V `vl8re16.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vl8re16.v xs1, vd`
    /// Rust: `vl8re16_v(vd, rs1)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `rs1` — Memory base register.
    pub fn vl8re16_v<T0, T1>(&mut self, vd: T0, rs1: T1)
    where
        Self: Vl8Re16VEmitter<T0, T1>,
    {
        <Self as Vl8Re16VEmitter<T0, T1>>::vl8re16_v(self, vd, rs1);
    }
    /// RISC-V `vl8re32.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vl8re32.v xs1, vd`
    /// Rust: `vl8re32_v(vd, rs1)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `rs1` — Memory base register.
    pub fn vl8re32_v<T0, T1>(&mut self, vd: T0, rs1: T1)
    where
        Self: Vl8Re32VEmitter<T0, T1>,
    {
        <Self as Vl8Re32VEmitter<T0, T1>>::vl8re32_v(self, vd, rs1);
    }
    /// RISC-V `vl8re64.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vl8re64.v xs1, vd`
    /// Rust: `vl8re64_v(vd, rs1)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `rs1` — Memory base register.
    pub fn vl8re64_v<T0, T1>(&mut self, vd: T0, rs1: T1)
    where
        Self: Vl8Re64VEmitter<T0, T1>,
    {
        <Self as Vl8Re64VEmitter<T0, T1>>::vl8re64_v(self, vd, rs1);
    }
    /// RISC-V `vl8re8.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vl8re8.v xs1, vd`
    /// Rust: `vl8re8_v(vd, rs1)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `rs1` — Memory base register.
    pub fn vl8re8_v<T0, T1>(&mut self, vd: T0, rs1: T1)
    where
        Self: Vl8Re8VEmitter<T0, T1>,
    {
        <Self as Vl8Re8VEmitter<T0, T1>>::vl8re8_v(self, vd, rs1);
    }
    /// RISC-V `vle16.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vle16.v vm, xs1, vd`
    /// Rust: `vle16_v(vd, rs1, vm, nf)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `rs1` — Memory base register.
    /// - `vm` — Vector mask control.
    /// - `nf` — Vector segment field count.
    pub fn vle16_v<T0, T1, T2, T3>(&mut self, vd: T0, rs1: T1, vm: T2, nf: T3)
    where
        Self: Vle16VEmitter<T0, T1, T2, T3>,
    {
        <Self as Vle16VEmitter<T0, T1, T2, T3>>::vle16_v(self, vd, rs1, vm, nf);
    }
    /// RISC-V `vle16ff.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vle16ff.v vm, xs1, vd`
    /// Rust: `vle16ff_v(vd, rs1, vm, nf)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `rs1` — Memory base register.
    /// - `vm` — Vector mask control.
    /// - `nf` — Vector segment field count.
    pub fn vle16ff_v<T0, T1, T2, T3>(&mut self, vd: T0, rs1: T1, vm: T2, nf: T3)
    where
        Self: Vle16FfVEmitter<T0, T1, T2, T3>,
    {
        <Self as Vle16FfVEmitter<T0, T1, T2, T3>>::vle16ff_v(self, vd, rs1, vm, nf);
    }
    /// RISC-V `vle1.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vle1.v vd rs1`
    /// Rust: `vle1_v(vd, rs1)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `rs1` — Memory base register.
    pub fn vle1_v<T0, T1>(&mut self, vd: T0, rs1: T1)
    where
        Self: Vle1VEmitter<T0, T1>,
    {
        <Self as Vle1VEmitter<T0, T1>>::vle1_v(self, vd, rs1);
    }
    /// RISC-V `vle32.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vle32.v vm, xs1, vd`
    /// Rust: `vle32_v(vd, rs1, vm, nf)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `rs1` — Memory base register.
    /// - `vm` — Vector mask control.
    /// - `nf` — Vector segment field count.
    pub fn vle32_v<T0, T1, T2, T3>(&mut self, vd: T0, rs1: T1, vm: T2, nf: T3)
    where
        Self: Vle32VEmitter<T0, T1, T2, T3>,
    {
        <Self as Vle32VEmitter<T0, T1, T2, T3>>::vle32_v(self, vd, rs1, vm, nf);
    }
    /// RISC-V `vle32ff.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vle32ff.v vm, xs1, vd`
    /// Rust: `vle32ff_v(vd, rs1, vm, nf)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `rs1` — Memory base register.
    /// - `vm` — Vector mask control.
    /// - `nf` — Vector segment field count.
    pub fn vle32ff_v<T0, T1, T2, T3>(&mut self, vd: T0, rs1: T1, vm: T2, nf: T3)
    where
        Self: Vle32FfVEmitter<T0, T1, T2, T3>,
    {
        <Self as Vle32FfVEmitter<T0, T1, T2, T3>>::vle32ff_v(self, vd, rs1, vm, nf);
    }
    /// RISC-V `vle64.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vle64.v vm, xs1, vd`
    /// Rust: `vle64_v(vd, rs1, vm, nf)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `rs1` — Memory base register.
    /// - `vm` — Vector mask control.
    /// - `nf` — Vector segment field count.
    pub fn vle64_v<T0, T1, T2, T3>(&mut self, vd: T0, rs1: T1, vm: T2, nf: T3)
    where
        Self: Vle64VEmitter<T0, T1, T2, T3>,
    {
        <Self as Vle64VEmitter<T0, T1, T2, T3>>::vle64_v(self, vd, rs1, vm, nf);
    }
    /// RISC-V `vle64ff.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vle64ff.v vm, xs1, vd`
    /// Rust: `vle64ff_v(vd, rs1, vm, nf)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `rs1` — Memory base register.
    /// - `vm` — Vector mask control.
    /// - `nf` — Vector segment field count.
    pub fn vle64ff_v<T0, T1, T2, T3>(&mut self, vd: T0, rs1: T1, vm: T2, nf: T3)
    where
        Self: Vle64FfVEmitter<T0, T1, T2, T3>,
    {
        <Self as Vle64FfVEmitter<T0, T1, T2, T3>>::vle64ff_v(self, vd, rs1, vm, nf);
    }
    /// RISC-V `vle8.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vle8.v vm, xs1, vd`
    /// Rust: `vle8_v(vd, rs1, vm, nf)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `rs1` — Memory base register.
    /// - `vm` — Vector mask control.
    /// - `nf` — Vector segment field count.
    pub fn vle8_v<T0, T1, T2, T3>(&mut self, vd: T0, rs1: T1, vm: T2, nf: T3)
    where
        Self: Vle8VEmitter<T0, T1, T2, T3>,
    {
        <Self as Vle8VEmitter<T0, T1, T2, T3>>::vle8_v(self, vd, rs1, vm, nf);
    }
    /// RISC-V `vle8ff.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vle8ff.v vm, xs1, vd`
    /// Rust: `vle8ff_v(vd, rs1, vm, nf)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `rs1` — Memory base register.
    /// - `vm` — Vector mask control.
    /// - `nf` — Vector segment field count.
    pub fn vle8ff_v<T0, T1, T2, T3>(&mut self, vd: T0, rs1: T1, vm: T2, nf: T3)
    where
        Self: Vle8FfVEmitter<T0, T1, T2, T3>,
    {
        <Self as Vle8FfVEmitter<T0, T1, T2, T3>>::vle8ff_v(self, vd, rs1, vm, nf);
    }
    /// RISC-V `vlm.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vlm.v xs1, vd`
    /// Rust: `vlm_v(vd, rs1)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `rs1` — Memory base register.
    pub fn vlm_v<T0, T1>(&mut self, vd: T0, rs1: T1)
    where
        Self: VlmVEmitter<T0, T1>,
    {
        <Self as VlmVEmitter<T0, T1>>::vlm_v(self, vd, rs1);
    }
    /// RISC-V `vloxei16.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vloxei16.v vm, vs2, xs1, vd`
    /// Rust: `vloxei16_v(vd, rs1, vs2, vm, nf)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `rs1` — Memory base register.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    /// - `nf` — Vector segment field count.
    pub fn vloxei16_v<T0, T1, T2, T3, T4>(&mut self, vd: T0, rs1: T1, vs2: T2, vm: T3, nf: T4)
    where
        Self: Vloxei16VEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as Vloxei16VEmitter<T0, T1, T2, T3, T4>>::vloxei16_v(self, vd, rs1, vs2, vm, nf);
    }
    /// RISC-V `vloxei32.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vloxei32.v vm, vs2, xs1, vd`
    /// Rust: `vloxei32_v(vd, rs1, vs2, vm, nf)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `rs1` — Memory base register.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    /// - `nf` — Vector segment field count.
    pub fn vloxei32_v<T0, T1, T2, T3, T4>(&mut self, vd: T0, rs1: T1, vs2: T2, vm: T3, nf: T4)
    where
        Self: Vloxei32VEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as Vloxei32VEmitter<T0, T1, T2, T3, T4>>::vloxei32_v(self, vd, rs1, vs2, vm, nf);
    }
    /// RISC-V `vloxei64.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vloxei64.v vm, vs2, xs1, vd`
    /// Rust: `vloxei64_v(vd, rs1, vs2, vm, nf)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `rs1` — Memory base register.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    /// - `nf` — Vector segment field count.
    pub fn vloxei64_v<T0, T1, T2, T3, T4>(&mut self, vd: T0, rs1: T1, vs2: T2, vm: T3, nf: T4)
    where
        Self: Vloxei64VEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as Vloxei64VEmitter<T0, T1, T2, T3, T4>>::vloxei64_v(self, vd, rs1, vs2, vm, nf);
    }
    /// RISC-V `vloxei8.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vloxei8.v vm, vs2, xs1, vd`
    /// Rust: `vloxei8_v(vd, rs1, vs2, vm, nf)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `rs1` — Memory base register.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    /// - `nf` — Vector segment field count.
    pub fn vloxei8_v<T0, T1, T2, T3, T4>(&mut self, vd: T0, rs1: T1, vs2: T2, vm: T3, nf: T4)
    where
        Self: Vloxei8VEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as Vloxei8VEmitter<T0, T1, T2, T3, T4>>::vloxei8_v(self, vd, rs1, vs2, vm, nf);
    }
    /// RISC-V `vlse16.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vlse16.v vm, xs2, xs1, vd`
    /// Rust: `vlse16_v(vd, rs1, rs2, vm, nf)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `rs1` — Memory base register.
    /// - `rs2` — Source register.
    /// - `vm` — Vector mask control.
    /// - `nf` — Vector segment field count.
    pub fn vlse16_v<T0, T1, T2, T3, T4>(&mut self, vd: T0, rs1: T1, rs2: T2, vm: T3, nf: T4)
    where
        Self: Vlse16VEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as Vlse16VEmitter<T0, T1, T2, T3, T4>>::vlse16_v(self, vd, rs1, rs2, vm, nf);
    }
    /// RISC-V `vlse32.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vlse32.v vm, xs2, xs1, vd`
    /// Rust: `vlse32_v(vd, rs1, rs2, vm, nf)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `rs1` — Memory base register.
    /// - `rs2` — Source register.
    /// - `vm` — Vector mask control.
    /// - `nf` — Vector segment field count.
    pub fn vlse32_v<T0, T1, T2, T3, T4>(&mut self, vd: T0, rs1: T1, rs2: T2, vm: T3, nf: T4)
    where
        Self: Vlse32VEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as Vlse32VEmitter<T0, T1, T2, T3, T4>>::vlse32_v(self, vd, rs1, rs2, vm, nf);
    }
    /// RISC-V `vlse64.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vlse64.v vm, xs2, xs1, vd`
    /// Rust: `vlse64_v(vd, rs1, rs2, vm, nf)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `rs1` — Memory base register.
    /// - `rs2` — Source register.
    /// - `vm` — Vector mask control.
    /// - `nf` — Vector segment field count.
    pub fn vlse64_v<T0, T1, T2, T3, T4>(&mut self, vd: T0, rs1: T1, rs2: T2, vm: T3, nf: T4)
    where
        Self: Vlse64VEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as Vlse64VEmitter<T0, T1, T2, T3, T4>>::vlse64_v(self, vd, rs1, rs2, vm, nf);
    }
    /// RISC-V `vlse8.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vlse8.v vm, xs2, xs1, vd`
    /// Rust: `vlse8_v(vd, rs1, rs2, vm, nf)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `rs1` — Memory base register.
    /// - `rs2` — Source register.
    /// - `vm` — Vector mask control.
    /// - `nf` — Vector segment field count.
    pub fn vlse8_v<T0, T1, T2, T3, T4>(&mut self, vd: T0, rs1: T1, rs2: T2, vm: T3, nf: T4)
    where
        Self: Vlse8VEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as Vlse8VEmitter<T0, T1, T2, T3, T4>>::vlse8_v(self, vd, rs1, rs2, vm, nf);
    }
    /// RISC-V `vluxei16.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vluxei16.v vm, vs2, xs1, vd`
    /// Rust: `vluxei16_v(vd, rs1, vs2, vm, nf)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `rs1` — Memory base register.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    /// - `nf` — Vector segment field count.
    pub fn vluxei16_v<T0, T1, T2, T3, T4>(&mut self, vd: T0, rs1: T1, vs2: T2, vm: T3, nf: T4)
    where
        Self: Vluxei16VEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as Vluxei16VEmitter<T0, T1, T2, T3, T4>>::vluxei16_v(self, vd, rs1, vs2, vm, nf);
    }
    /// RISC-V `vluxei32.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vluxei32.v vm, vs2, xs1, vd`
    /// Rust: `vluxei32_v(vd, rs1, vs2, vm, nf)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `rs1` — Memory base register.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    /// - `nf` — Vector segment field count.
    pub fn vluxei32_v<T0, T1, T2, T3, T4>(&mut self, vd: T0, rs1: T1, vs2: T2, vm: T3, nf: T4)
    where
        Self: Vluxei32VEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as Vluxei32VEmitter<T0, T1, T2, T3, T4>>::vluxei32_v(self, vd, rs1, vs2, vm, nf);
    }
    /// RISC-V `vluxei64.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vluxei64.v vm, vs2, xs1, vd`
    /// Rust: `vluxei64_v(vd, rs1, vs2, vm, nf)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `rs1` — Memory base register.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    /// - `nf` — Vector segment field count.
    pub fn vluxei64_v<T0, T1, T2, T3, T4>(&mut self, vd: T0, rs1: T1, vs2: T2, vm: T3, nf: T4)
    where
        Self: Vluxei64VEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as Vluxei64VEmitter<T0, T1, T2, T3, T4>>::vluxei64_v(self, vd, rs1, vs2, vm, nf);
    }
    /// RISC-V `vluxei8.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vluxei8.v vm, vs2, xs1, vd`
    /// Rust: `vluxei8_v(vd, rs1, vs2, vm, nf)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `rs1` — Memory base register.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    /// - `nf` — Vector segment field count.
    pub fn vluxei8_v<T0, T1, T2, T3, T4>(&mut self, vd: T0, rs1: T1, vs2: T2, vm: T3, nf: T4)
    where
        Self: Vluxei8VEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as Vluxei8VEmitter<T0, T1, T2, T3, T4>>::vluxei8_v(self, vd, rs1, vs2, vm, nf);
    }
    /// RISC-V `vmacc.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vmacc.vv vm, vs2, vs1, vd`
    /// Rust: `vmacc_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vmacc_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VmaccVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VmaccVvEmitter<T0, T1, T2, T3>>::vmacc_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vmacc.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vmacc.vx vm, vs2, xs1, vd`
    /// Rust: `vmacc_vx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vmacc_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VmaccVxEmitter<T0, T1, T2, T3>,
    {
        <Self as VmaccVxEmitter<T0, T1, T2, T3>>::vmacc_vx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vmadc.vi` instruction.
    ///
    /// # Forms
    /// Assembly: `vmadc.vi vs2, vd, imm`
    /// Rust: `vmadc_vi(vd, vs2, simm5)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `simm5` — Immediate encoding value.
    pub fn vmadc_vi<T0, T1, T2>(&mut self, vd: T0, vs2: T1, simm5: T2)
    where
        Self: VmadcViEmitter<T0, T1, T2>,
    {
        <Self as VmadcViEmitter<T0, T1, T2>>::vmadc_vi(self, vd, vs2, simm5);
    }
    /// RISC-V `vmadc.vim` instruction.
    ///
    /// # Forms
    /// Assembly: `vmadc.vim vs2, vd, imm`
    /// Rust: `vmadc_vim(vd, vs2, simm5)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `simm5` — Immediate encoding value.
    pub fn vmadc_vim<T0, T1, T2>(&mut self, vd: T0, vs2: T1, simm5: T2)
    where
        Self: VmadcVimEmitter<T0, T1, T2>,
    {
        <Self as VmadcVimEmitter<T0, T1, T2>>::vmadc_vim(self, vd, vs2, simm5);
    }
    /// RISC-V `vmadc.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vmadc.vv vs2, vs1, vd`
    /// Rust: `vmadc_vv(vd, vs1, vs2)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    pub fn vmadc_vv<T0, T1, T2>(&mut self, vd: T0, vs1: T1, vs2: T2)
    where
        Self: VmadcVvEmitter<T0, T1, T2>,
    {
        <Self as VmadcVvEmitter<T0, T1, T2>>::vmadc_vv(self, vd, vs1, vs2);
    }
    /// RISC-V `vmadc.vvm` instruction.
    ///
    /// # Forms
    /// Assembly: `vmadc.vvm vs2, vs1, vd`
    /// Rust: `vmadc_vvm(vd, vs1, vs2)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    pub fn vmadc_vvm<T0, T1, T2>(&mut self, vd: T0, vs1: T1, vs2: T2)
    where
        Self: VmadcVvmEmitter<T0, T1, T2>,
    {
        <Self as VmadcVvmEmitter<T0, T1, T2>>::vmadc_vvm(self, vd, vs1, vs2);
    }
    /// RISC-V `vmadc.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vmadc.vx vs2, xs1, vd`
    /// Rust: `vmadc_vx(vd, rs1, vs2)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vs2` — Vector register operand.
    pub fn vmadc_vx<T0, T1, T2>(&mut self, vd: T0, rs1: T1, vs2: T2)
    where
        Self: VmadcVxEmitter<T0, T1, T2>,
    {
        <Self as VmadcVxEmitter<T0, T1, T2>>::vmadc_vx(self, vd, rs1, vs2);
    }
    /// RISC-V `vmadc.vxm` instruction.
    ///
    /// # Forms
    /// Assembly: `vmadc.vxm vs2, xs1, vd`
    /// Rust: `vmadc_vxm(vd, rs1, vs2)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vs2` — Vector register operand.
    pub fn vmadc_vxm<T0, T1, T2>(&mut self, vd: T0, rs1: T1, vs2: T2)
    where
        Self: VmadcVxmEmitter<T0, T1, T2>,
    {
        <Self as VmadcVxmEmitter<T0, T1, T2>>::vmadc_vxm(self, vd, rs1, vs2);
    }
    /// RISC-V `vmadd.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vmadd.vv vm, vs2, vs1, vd`
    /// Rust: `vmadd_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vmadd_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VmaddVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VmaddVvEmitter<T0, T1, T2, T3>>::vmadd_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vmadd.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vmadd.vx vm, vs2, xs1, vd`
    /// Rust: `vmadd_vx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vmadd_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VmaddVxEmitter<T0, T1, T2, T3>,
    {
        <Self as VmaddVxEmitter<T0, T1, T2, T3>>::vmadd_vx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vmand.mm` instruction.
    ///
    /// # Forms
    /// Assembly: `vmand.mm vs2, vs1, vd`
    /// Rust: `vmand_mm(vd, vs1, vs2)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    pub fn vmand_mm<T0, T1, T2>(&mut self, vd: T0, vs1: T1, vs2: T2)
    where
        Self: VmandMmEmitter<T0, T1, T2>,
    {
        <Self as VmandMmEmitter<T0, T1, T2>>::vmand_mm(self, vd, vs1, vs2);
    }
    /// RISC-V `vmandn.mm` instruction.
    ///
    /// # Forms
    /// Assembly: `vmandn.mm vs2, vs1, vd`
    /// Rust: `vmandn_mm(vd, vs1, vs2)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    pub fn vmandn_mm<T0, T1, T2>(&mut self, vd: T0, vs1: T1, vs2: T2)
    where
        Self: VmandnMmEmitter<T0, T1, T2>,
    {
        <Self as VmandnMmEmitter<T0, T1, T2>>::vmandn_mm(self, vd, vs1, vs2);
    }
    /// RISC-V `vmandnot.mm` instruction.
    ///
    /// # Forms
    /// Assembly: `vmandnot.mm vd vs1 vs2 vm`
    /// Rust: `vmandnot_mm(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vmandnot_mm<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VmandnotMmEmitter<T0, T1, T2, T3>,
    {
        <Self as VmandnotMmEmitter<T0, T1, T2, T3>>::vmandnot_mm(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vmax.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vmax.vv vm, vs2, vs1, vd`
    /// Rust: `vmax_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vmax_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VmaxVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VmaxVvEmitter<T0, T1, T2, T3>>::vmax_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vmax.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vmax.vx vm, vs2, xs1, vd`
    /// Rust: `vmax_vx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vmax_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VmaxVxEmitter<T0, T1, T2, T3>,
    {
        <Self as VmaxVxEmitter<T0, T1, T2, T3>>::vmax_vx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vmaxu.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vmaxu.vv vm, vs2, vs1, vd`
    /// Rust: `vmaxu_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vmaxu_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VmaxuVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VmaxuVvEmitter<T0, T1, T2, T3>>::vmaxu_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vmaxu.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vmaxu.vx vm, vs2, xs1, vd`
    /// Rust: `vmaxu_vx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vmaxu_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VmaxuVxEmitter<T0, T1, T2, T3>,
    {
        <Self as VmaxuVxEmitter<T0, T1, T2, T3>>::vmaxu_vx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vmerge.vim` instruction.
    ///
    /// # Forms
    /// Assembly: `vmerge.vim vs2, vd, imm`
    /// Rust: `vmerge_vim(vd, vs2, simm5)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `simm5` — Immediate encoding value.
    pub fn vmerge_vim<T0, T1, T2>(&mut self, vd: T0, vs2: T1, simm5: T2)
    where
        Self: VmergeVimEmitter<T0, T1, T2>,
    {
        <Self as VmergeVimEmitter<T0, T1, T2>>::vmerge_vim(self, vd, vs2, simm5);
    }
    /// RISC-V `vmerge.vvm` instruction.
    ///
    /// # Forms
    /// Assembly: `vmerge.vvm vs2, vs1, vd`
    /// Rust: `vmerge_vvm(vd, vs1, vs2)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    pub fn vmerge_vvm<T0, T1, T2>(&mut self, vd: T0, vs1: T1, vs2: T2)
    where
        Self: VmergeVvmEmitter<T0, T1, T2>,
    {
        <Self as VmergeVvmEmitter<T0, T1, T2>>::vmerge_vvm(self, vd, vs1, vs2);
    }
    /// RISC-V `vmerge.vxm` instruction.
    ///
    /// # Forms
    /// Assembly: `vmerge.vxm vs2, xs1, vd`
    /// Rust: `vmerge_vxm(vd, rs1, vs2)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vs2` — Vector register operand.
    pub fn vmerge_vxm<T0, T1, T2>(&mut self, vd: T0, rs1: T1, vs2: T2)
    where
        Self: VmergeVxmEmitter<T0, T1, T2>,
    {
        <Self as VmergeVxmEmitter<T0, T1, T2>>::vmerge_vxm(self, vd, rs1, vs2);
    }
    /// RISC-V `vmfeq.vf` instruction.
    ///
    /// # Forms
    /// Assembly: `vmfeq.vf vm, vs2, xs1, vd`
    /// Rust: `vmfeq_vf(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vmfeq_vf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VmfeqVfEmitter<T0, T1, T2, T3>,
    {
        <Self as VmfeqVfEmitter<T0, T1, T2, T3>>::vmfeq_vf(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vmfeq.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vmfeq.vv vm, vs2, vs1, vd`
    /// Rust: `vmfeq_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vmfeq_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VmfeqVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VmfeqVvEmitter<T0, T1, T2, T3>>::vmfeq_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vmfge.vf` instruction.
    ///
    /// # Forms
    /// Assembly: `vmfge.vf vm, vs2, xs1, vd`
    /// Rust: `vmfge_vf(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vmfge_vf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VmfgeVfEmitter<T0, T1, T2, T3>,
    {
        <Self as VmfgeVfEmitter<T0, T1, T2, T3>>::vmfge_vf(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vmfgt.vf` instruction.
    ///
    /// # Forms
    /// Assembly: `vmfgt.vf vm, vs2, xs1, vd`
    /// Rust: `vmfgt_vf(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vmfgt_vf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VmfgtVfEmitter<T0, T1, T2, T3>,
    {
        <Self as VmfgtVfEmitter<T0, T1, T2, T3>>::vmfgt_vf(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vmfle.vf` instruction.
    ///
    /// # Forms
    /// Assembly: `vmfle.vf vm, vs2, xs1, vd`
    /// Rust: `vmfle_vf(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vmfle_vf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VmfleVfEmitter<T0, T1, T2, T3>,
    {
        <Self as VmfleVfEmitter<T0, T1, T2, T3>>::vmfle_vf(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vmfle.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vmfle.vv vm, vs2, vs1, vd`
    /// Rust: `vmfle_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vmfle_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VmfleVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VmfleVvEmitter<T0, T1, T2, T3>>::vmfle_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vmflt.vf` instruction.
    ///
    /// # Forms
    /// Assembly: `vmflt.vf vm, vs2, xs1, vd`
    /// Rust: `vmflt_vf(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vmflt_vf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VmfltVfEmitter<T0, T1, T2, T3>,
    {
        <Self as VmfltVfEmitter<T0, T1, T2, T3>>::vmflt_vf(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vmflt.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vmflt.vv vm, vs2, vs1, vd`
    /// Rust: `vmflt_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vmflt_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VmfltVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VmfltVvEmitter<T0, T1, T2, T3>>::vmflt_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vmfne.vf` instruction.
    ///
    /// # Forms
    /// Assembly: `vmfne.vf vm, vs2, xs1, vd`
    /// Rust: `vmfne_vf(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vmfne_vf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VmfneVfEmitter<T0, T1, T2, T3>,
    {
        <Self as VmfneVfEmitter<T0, T1, T2, T3>>::vmfne_vf(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vmfne.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vmfne.vv vm, vs2, vs1, vd`
    /// Rust: `vmfne_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vmfne_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VmfneVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VmfneVvEmitter<T0, T1, T2, T3>>::vmfne_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vmin.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vmin.vv vm, vs2, vs1, vd`
    /// Rust: `vmin_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vmin_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VminVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VminVvEmitter<T0, T1, T2, T3>>::vmin_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vmin.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vmin.vx vm, vs2, xs1, vd`
    /// Rust: `vmin_vx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vmin_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VminVxEmitter<T0, T1, T2, T3>,
    {
        <Self as VminVxEmitter<T0, T1, T2, T3>>::vmin_vx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vminu.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vminu.vv vm, vs2, vs1, vd`
    /// Rust: `vminu_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vminu_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VminuVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VminuVvEmitter<T0, T1, T2, T3>>::vminu_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vminu.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vminu.vx vm, vs2, xs1, vd`
    /// Rust: `vminu_vx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vminu_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VminuVxEmitter<T0, T1, T2, T3>,
    {
        <Self as VminuVxEmitter<T0, T1, T2, T3>>::vminu_vx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vmnand.mm` instruction.
    ///
    /// # Forms
    /// Assembly: `vmnand.mm vs2, vs1, vd`
    /// Rust: `vmnand_mm(vd, vs1, vs2)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    pub fn vmnand_mm<T0, T1, T2>(&mut self, vd: T0, vs1: T1, vs2: T2)
    where
        Self: VmnandMmEmitter<T0, T1, T2>,
    {
        <Self as VmnandMmEmitter<T0, T1, T2>>::vmnand_mm(self, vd, vs1, vs2);
    }
    /// RISC-V `vmnor.mm` instruction.
    ///
    /// # Forms
    /// Assembly: `vmnor.mm vs2, vs1, vd`
    /// Rust: `vmnor_mm(vd, vs1, vs2)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    pub fn vmnor_mm<T0, T1, T2>(&mut self, vd: T0, vs1: T1, vs2: T2)
    where
        Self: VmnorMmEmitter<T0, T1, T2>,
    {
        <Self as VmnorMmEmitter<T0, T1, T2>>::vmnor_mm(self, vd, vs1, vs2);
    }
    /// RISC-V `vmor.mm` instruction.
    ///
    /// # Forms
    /// Assembly: `vmor.mm vs2, vs1, vd`
    /// Rust: `vmor_mm(vd, vs1, vs2)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    pub fn vmor_mm<T0, T1, T2>(&mut self, vd: T0, vs1: T1, vs2: T2)
    where
        Self: VmorMmEmitter<T0, T1, T2>,
    {
        <Self as VmorMmEmitter<T0, T1, T2>>::vmor_mm(self, vd, vs1, vs2);
    }
    /// RISC-V `vmorn.mm` instruction.
    ///
    /// # Forms
    /// Assembly: `vmorn.mm vs2, vs1, vd`
    /// Rust: `vmorn_mm(vd, vs1, vs2)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    pub fn vmorn_mm<T0, T1, T2>(&mut self, vd: T0, vs1: T1, vs2: T2)
    where
        Self: VmornMmEmitter<T0, T1, T2>,
    {
        <Self as VmornMmEmitter<T0, T1, T2>>::vmorn_mm(self, vd, vs1, vs2);
    }
    /// RISC-V `vmornot.mm` instruction.
    ///
    /// # Forms
    /// Assembly: `vmornot.mm vd vs1 vs2 vm`
    /// Rust: `vmornot_mm(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vmornot_mm<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VmornotMmEmitter<T0, T1, T2, T3>,
    {
        <Self as VmornotMmEmitter<T0, T1, T2, T3>>::vmornot_mm(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vmsbc.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vmsbc.vv vs2, vs1, vd`
    /// Rust: `vmsbc_vv(vd, vs1, vs2)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    pub fn vmsbc_vv<T0, T1, T2>(&mut self, vd: T0, vs1: T1, vs2: T2)
    where
        Self: VmsbcVvEmitter<T0, T1, T2>,
    {
        <Self as VmsbcVvEmitter<T0, T1, T2>>::vmsbc_vv(self, vd, vs1, vs2);
    }
    /// RISC-V `vmsbc.vvm` instruction.
    ///
    /// # Forms
    /// Assembly: `vmsbc.vvm vs2, vs1, vd`
    /// Rust: `vmsbc_vvm(vd, vs1, vs2)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    pub fn vmsbc_vvm<T0, T1, T2>(&mut self, vd: T0, vs1: T1, vs2: T2)
    where
        Self: VmsbcVvmEmitter<T0, T1, T2>,
    {
        <Self as VmsbcVvmEmitter<T0, T1, T2>>::vmsbc_vvm(self, vd, vs1, vs2);
    }
    /// RISC-V `vmsbc.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vmsbc.vx vs2, xs1, vd`
    /// Rust: `vmsbc_vx(vd, rs1, vs2)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vs2` — Vector register operand.
    pub fn vmsbc_vx<T0, T1, T2>(&mut self, vd: T0, rs1: T1, vs2: T2)
    where
        Self: VmsbcVxEmitter<T0, T1, T2>,
    {
        <Self as VmsbcVxEmitter<T0, T1, T2>>::vmsbc_vx(self, vd, rs1, vs2);
    }
    /// RISC-V `vmsbc.vxm` instruction.
    ///
    /// # Forms
    /// Assembly: `vmsbc.vxm vs2, xs1, vd`
    /// Rust: `vmsbc_vxm(vd, rs1, vs2)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vs2` — Vector register operand.
    pub fn vmsbc_vxm<T0, T1, T2>(&mut self, vd: T0, rs1: T1, vs2: T2)
    where
        Self: VmsbcVxmEmitter<T0, T1, T2>,
    {
        <Self as VmsbcVxmEmitter<T0, T1, T2>>::vmsbc_vxm(self, vd, rs1, vs2);
    }
    /// RISC-V `vmsbf.m` instruction.
    ///
    /// # Forms
    /// Assembly: `vmsbf.m vm, vs2, vd`
    /// Rust: `vmsbf_m(vd, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vmsbf_m<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
    where
        Self: VmsbfMEmitter<T0, T1, T2>,
    {
        <Self as VmsbfMEmitter<T0, T1, T2>>::vmsbf_m(self, vd, vs2, vm);
    }
    /// RISC-V `vmseq.vi` instruction.
    ///
    /// # Forms
    /// Assembly: `vmseq.vi vm, vs2, vd, imm`
    /// Rust: `vmseq_vi(vd, vs2, simm5, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `simm5` — Immediate encoding value.
    /// - `vm` — Vector mask control.
    pub fn vmseq_vi<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, simm5: T2, vm: T3)
    where
        Self: VmseqViEmitter<T0, T1, T2, T3>,
    {
        <Self as VmseqViEmitter<T0, T1, T2, T3>>::vmseq_vi(self, vd, vs2, simm5, vm);
    }
    /// RISC-V `vmseq.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vmseq.vv vm, vs2, vs1, vd`
    /// Rust: `vmseq_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vmseq_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VmseqVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VmseqVvEmitter<T0, T1, T2, T3>>::vmseq_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vmseq.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vmseq.vx vm, vs2, xs1, vd`
    /// Rust: `vmseq_vx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vmseq_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VmseqVxEmitter<T0, T1, T2, T3>,
    {
        <Self as VmseqVxEmitter<T0, T1, T2, T3>>::vmseq_vx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vmsgt.vi` instruction.
    ///
    /// # Forms
    /// Assembly: `vmsgt.vi vm, vs2, vd, imm`
    /// Rust: `vmsgt_vi(vd, vs2, simm5, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `simm5` — Immediate encoding value.
    /// - `vm` — Vector mask control.
    pub fn vmsgt_vi<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, simm5: T2, vm: T3)
    where
        Self: VmsgtViEmitter<T0, T1, T2, T3>,
    {
        <Self as VmsgtViEmitter<T0, T1, T2, T3>>::vmsgt_vi(self, vd, vs2, simm5, vm);
    }
    /// RISC-V `vmsgt.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vmsgt.vx vm, vs2, xs1, vd`
    /// Rust: `vmsgt_vx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vmsgt_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VmsgtVxEmitter<T0, T1, T2, T3>,
    {
        <Self as VmsgtVxEmitter<T0, T1, T2, T3>>::vmsgt_vx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vmsgtu.vi` instruction.
    ///
    /// # Forms
    /// Assembly: `vmsgtu.vi vm, vs2, vd, imm`
    /// Rust: `vmsgtu_vi(vd, vs2, simm5, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `simm5` — Immediate encoding value.
    /// - `vm` — Vector mask control.
    pub fn vmsgtu_vi<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, simm5: T2, vm: T3)
    where
        Self: VmsgtuViEmitter<T0, T1, T2, T3>,
    {
        <Self as VmsgtuViEmitter<T0, T1, T2, T3>>::vmsgtu_vi(self, vd, vs2, simm5, vm);
    }
    /// RISC-V `vmsgtu.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vmsgtu.vx vm, vs2, xs1, vd`
    /// Rust: `vmsgtu_vx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vmsgtu_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VmsgtuVxEmitter<T0, T1, T2, T3>,
    {
        <Self as VmsgtuVxEmitter<T0, T1, T2, T3>>::vmsgtu_vx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vmsif.m` instruction.
    ///
    /// # Forms
    /// Assembly: `vmsif.m vm, vs2, vd`
    /// Rust: `vmsif_m(vd, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vmsif_m<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
    where
        Self: VmsifMEmitter<T0, T1, T2>,
    {
        <Self as VmsifMEmitter<T0, T1, T2>>::vmsif_m(self, vd, vs2, vm);
    }
    /// RISC-V `vmsle.vi` instruction.
    ///
    /// # Forms
    /// Assembly: `vmsle.vi vm, vs2, vd, imm`
    /// Rust: `vmsle_vi(vd, vs2, simm5, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `simm5` — Immediate encoding value.
    /// - `vm` — Vector mask control.
    pub fn vmsle_vi<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, simm5: T2, vm: T3)
    where
        Self: VmsleViEmitter<T0, T1, T2, T3>,
    {
        <Self as VmsleViEmitter<T0, T1, T2, T3>>::vmsle_vi(self, vd, vs2, simm5, vm);
    }
    /// RISC-V `vmsle.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vmsle.vv vm, vs2, vs1, vd`
    /// Rust: `vmsle_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vmsle_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VmsleVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VmsleVvEmitter<T0, T1, T2, T3>>::vmsle_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vmsle.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vmsle.vx vm, vs2, xs1, vd`
    /// Rust: `vmsle_vx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vmsle_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VmsleVxEmitter<T0, T1, T2, T3>,
    {
        <Self as VmsleVxEmitter<T0, T1, T2, T3>>::vmsle_vx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vmsleu.vi` instruction.
    ///
    /// # Forms
    /// Assembly: `vmsleu.vi vm, vs2, vd, imm`
    /// Rust: `vmsleu_vi(vd, vs2, simm5, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `simm5` — Immediate encoding value.
    /// - `vm` — Vector mask control.
    pub fn vmsleu_vi<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, simm5: T2, vm: T3)
    where
        Self: VmsleuViEmitter<T0, T1, T2, T3>,
    {
        <Self as VmsleuViEmitter<T0, T1, T2, T3>>::vmsleu_vi(self, vd, vs2, simm5, vm);
    }
    /// RISC-V `vmsleu.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vmsleu.vv vm, vs2, vs1, vd`
    /// Rust: `vmsleu_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vmsleu_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VmsleuVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VmsleuVvEmitter<T0, T1, T2, T3>>::vmsleu_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vmsleu.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vmsleu.vx vm, vs2, xs1, vd`
    /// Rust: `vmsleu_vx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vmsleu_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VmsleuVxEmitter<T0, T1, T2, T3>,
    {
        <Self as VmsleuVxEmitter<T0, T1, T2, T3>>::vmsleu_vx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vmslt.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vmslt.vv vm, vs2, vs1, vd`
    /// Rust: `vmslt_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vmslt_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VmsltVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VmsltVvEmitter<T0, T1, T2, T3>>::vmslt_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vmslt.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vmslt.vx vm, vs2, xs1, vd`
    /// Rust: `vmslt_vx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vmslt_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VmsltVxEmitter<T0, T1, T2, T3>,
    {
        <Self as VmsltVxEmitter<T0, T1, T2, T3>>::vmslt_vx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vmsltu.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vmsltu.vv vm, vs2, vs1, vd`
    /// Rust: `vmsltu_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vmsltu_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VmsltuVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VmsltuVvEmitter<T0, T1, T2, T3>>::vmsltu_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vmsltu.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vmsltu.vx vm, vs2, xs1, vd`
    /// Rust: `vmsltu_vx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vmsltu_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VmsltuVxEmitter<T0, T1, T2, T3>,
    {
        <Self as VmsltuVxEmitter<T0, T1, T2, T3>>::vmsltu_vx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vmsne.vi` instruction.
    ///
    /// # Forms
    /// Assembly: `vmsne.vi vm, vs2, vd, imm`
    /// Rust: `vmsne_vi(vd, vs2, simm5, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `simm5` — Immediate encoding value.
    /// - `vm` — Vector mask control.
    pub fn vmsne_vi<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, simm5: T2, vm: T3)
    where
        Self: VmsneViEmitter<T0, T1, T2, T3>,
    {
        <Self as VmsneViEmitter<T0, T1, T2, T3>>::vmsne_vi(self, vd, vs2, simm5, vm);
    }
    /// RISC-V `vmsne.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vmsne.vv vm, vs2, vs1, vd`
    /// Rust: `vmsne_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vmsne_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VmsneVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VmsneVvEmitter<T0, T1, T2, T3>>::vmsne_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vmsne.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vmsne.vx vm, vs2, xs1, vd`
    /// Rust: `vmsne_vx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vmsne_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VmsneVxEmitter<T0, T1, T2, T3>,
    {
        <Self as VmsneVxEmitter<T0, T1, T2, T3>>::vmsne_vx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vmsof.m` instruction.
    ///
    /// # Forms
    /// Assembly: `vmsof.m vm, vs2, vd`
    /// Rust: `vmsof_m(vd, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vmsof_m<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
    where
        Self: VmsofMEmitter<T0, T1, T2>,
    {
        <Self as VmsofMEmitter<T0, T1, T2>>::vmsof_m(self, vd, vs2, vm);
    }
    /// RISC-V `vmul.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vmul.vv vm, vs2, vs1, vd`
    /// Rust: `vmul_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vmul_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VmulVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VmulVvEmitter<T0, T1, T2, T3>>::vmul_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vmul.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vmul.vx vm, vs2, xs1, vd`
    /// Rust: `vmul_vx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vmul_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VmulVxEmitter<T0, T1, T2, T3>,
    {
        <Self as VmulVxEmitter<T0, T1, T2, T3>>::vmul_vx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vmulh.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vmulh.vv vm, vs2, vs1, vd`
    /// Rust: `vmulh_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vmulh_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VmulhVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VmulhVvEmitter<T0, T1, T2, T3>>::vmulh_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vmulh.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vmulh.vx vm, vs2, xs1, vd`
    /// Rust: `vmulh_vx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vmulh_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VmulhVxEmitter<T0, T1, T2, T3>,
    {
        <Self as VmulhVxEmitter<T0, T1, T2, T3>>::vmulh_vx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vmulhsu.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vmulhsu.vv vm, vs2, vs1, vd`
    /// Rust: `vmulhsu_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vmulhsu_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VmulhsuVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VmulhsuVvEmitter<T0, T1, T2, T3>>::vmulhsu_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vmulhsu.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vmulhsu.vx vm, vs2, xs1, vd`
    /// Rust: `vmulhsu_vx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vmulhsu_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VmulhsuVxEmitter<T0, T1, T2, T3>,
    {
        <Self as VmulhsuVxEmitter<T0, T1, T2, T3>>::vmulhsu_vx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vmulhu.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vmulhu.vv vm, vs2, vs1, vd`
    /// Rust: `vmulhu_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vmulhu_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VmulhuVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VmulhuVvEmitter<T0, T1, T2, T3>>::vmulhu_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vmulhu.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vmulhu.vx vm, vs2, xs1, vd`
    /// Rust: `vmulhu_vx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vmulhu_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VmulhuVxEmitter<T0, T1, T2, T3>,
    {
        <Self as VmulhuVxEmitter<T0, T1, T2, T3>>::vmulhu_vx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vmv1r.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vmv1r.v vs2, vd`
    /// Rust: `vmv1r_v(vd, vs2)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    pub fn vmv1r_v<T0, T1>(&mut self, vd: T0, vs2: T1)
    where
        Self: Vmv1RVEmitter<T0, T1>,
    {
        <Self as Vmv1RVEmitter<T0, T1>>::vmv1r_v(self, vd, vs2);
    }
    /// RISC-V `vmv2r.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vmv2r.v vs2, vd`
    /// Rust: `vmv2r_v(vd, vs2)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    pub fn vmv2r_v<T0, T1>(&mut self, vd: T0, vs2: T1)
    where
        Self: Vmv2RVEmitter<T0, T1>,
    {
        <Self as Vmv2RVEmitter<T0, T1>>::vmv2r_v(self, vd, vs2);
    }
    /// RISC-V `vmv4r.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vmv4r.v vs2, vd`
    /// Rust: `vmv4r_v(vd, vs2)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    pub fn vmv4r_v<T0, T1>(&mut self, vd: T0, vs2: T1)
    where
        Self: Vmv4RVEmitter<T0, T1>,
    {
        <Self as Vmv4RVEmitter<T0, T1>>::vmv4r_v(self, vd, vs2);
    }
    /// RISC-V `vmv8r.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vmv8r.v vs2, vd`
    /// Rust: `vmv8r_v(vd, vs2)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    pub fn vmv8r_v<T0, T1>(&mut self, vd: T0, vs2: T1)
    where
        Self: Vmv8RVEmitter<T0, T1>,
    {
        <Self as Vmv8RVEmitter<T0, T1>>::vmv8r_v(self, vd, vs2);
    }
    /// RISC-V `vmv.s.x` instruction.
    ///
    /// # Forms
    /// Assembly: `vmv.s.x xs1, vd`
    /// Rust: `vmv_s_x(vd, rs1)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `rs1` — Source register.
    pub fn vmv_s_x<T0, T1>(&mut self, vd: T0, rs1: T1)
    where
        Self: VmvSXEmitter<T0, T1>,
    {
        <Self as VmvSXEmitter<T0, T1>>::vmv_s_x(self, vd, rs1);
    }
    /// RISC-V `vmv.v.i` instruction.
    ///
    /// # Forms
    /// Assembly: `vmv.v.i vd, imm`
    /// Rust: `vmv_v_i(vd, simm5)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `simm5` — Immediate encoding value.
    pub fn vmv_v_i<T0, T1>(&mut self, vd: T0, simm5: T1)
    where
        Self: VmvVIEmitter<T0, T1>,
    {
        <Self as VmvVIEmitter<T0, T1>>::vmv_v_i(self, vd, simm5);
    }
    /// RISC-V `vmv.v.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vmv.v.v vs1, vd`
    /// Rust: `vmv_v_v(vd, vs1)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    pub fn vmv_v_v<T0, T1>(&mut self, vd: T0, vs1: T1)
    where
        Self: VmvVVEmitter<T0, T1>,
    {
        <Self as VmvVVEmitter<T0, T1>>::vmv_v_v(self, vd, vs1);
    }
    /// RISC-V `vmv.v.x` instruction.
    ///
    /// # Forms
    /// Assembly: `vmv.v.x xs1, vd`
    /// Rust: `vmv_v_x(vd, rs1)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `rs1` — Source register.
    pub fn vmv_v_x<T0, T1>(&mut self, vd: T0, rs1: T1)
    where
        Self: VmvVXEmitter<T0, T1>,
    {
        <Self as VmvVXEmitter<T0, T1>>::vmv_v_x(self, vd, rs1);
    }
    /// RISC-V `vmv.x.s` instruction.
    ///
    /// # Forms
    /// Assembly: `vmv.x.s vs2, xd`
    /// Rust: `vmv_x_s(rd, vs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `vs2` — Vector register operand.
    pub fn vmv_x_s<T0, T1>(&mut self, rd: T0, vs2: T1)
    where
        Self: VmvXSEmitter<T0, T1>,
    {
        <Self as VmvXSEmitter<T0, T1>>::vmv_x_s(self, rd, vs2);
    }
    /// RISC-V `vmxnor.mm` instruction.
    ///
    /// # Forms
    /// Assembly: `vmxnor.mm vs2, vs1, vd`
    /// Rust: `vmxnor_mm(vd, vs1, vs2)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    pub fn vmxnor_mm<T0, T1, T2>(&mut self, vd: T0, vs1: T1, vs2: T2)
    where
        Self: VmxnorMmEmitter<T0, T1, T2>,
    {
        <Self as VmxnorMmEmitter<T0, T1, T2>>::vmxnor_mm(self, vd, vs1, vs2);
    }
    /// RISC-V `vmxor.mm` instruction.
    ///
    /// # Forms
    /// Assembly: `vmxor.mm vs2, vs1, vd`
    /// Rust: `vmxor_mm(vd, vs1, vs2)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    pub fn vmxor_mm<T0, T1, T2>(&mut self, vd: T0, vs1: T1, vs2: T2)
    where
        Self: VmxorMmEmitter<T0, T1, T2>,
    {
        <Self as VmxorMmEmitter<T0, T1, T2>>::vmxor_mm(self, vd, vs1, vs2);
    }
    /// RISC-V `vnclip.wi` instruction.
    ///
    /// # Forms
    /// Assembly: `vnclip.wi vm, vs2, vd, imm`
    /// Rust: `vnclip_wi(vd, vs2, zimm5, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `zimm5` — Immediate encoding value.
    /// - `vm` — Vector mask control.
    pub fn vnclip_wi<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, zimm5: T2, vm: T3)
    where
        Self: VnclipWiEmitter<T0, T1, T2, T3>,
    {
        <Self as VnclipWiEmitter<T0, T1, T2, T3>>::vnclip_wi(self, vd, vs2, zimm5, vm);
    }
    /// RISC-V `vnclip.wv` instruction.
    ///
    /// # Forms
    /// Assembly: `vnclip.wv vm, vs2, vs1, vd`
    /// Rust: `vnclip_wv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vnclip_wv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VnclipWvEmitter<T0, T1, T2, T3>,
    {
        <Self as VnclipWvEmitter<T0, T1, T2, T3>>::vnclip_wv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vnclip.wx` instruction.
    ///
    /// # Forms
    /// Assembly: `vnclip.wx vm, vs2, xs1, vd`
    /// Rust: `vnclip_wx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vnclip_wx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VnclipWxEmitter<T0, T1, T2, T3>,
    {
        <Self as VnclipWxEmitter<T0, T1, T2, T3>>::vnclip_wx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vnclipu.wi` instruction.
    ///
    /// # Forms
    /// Assembly: `vnclipu.wi vm, vs2, vd, imm`
    /// Rust: `vnclipu_wi(vd, vs2, zimm5, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `zimm5` — Immediate encoding value.
    /// - `vm` — Vector mask control.
    pub fn vnclipu_wi<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, zimm5: T2, vm: T3)
    where
        Self: VnclipuWiEmitter<T0, T1, T2, T3>,
    {
        <Self as VnclipuWiEmitter<T0, T1, T2, T3>>::vnclipu_wi(self, vd, vs2, zimm5, vm);
    }
    /// RISC-V `vnclipu.wv` instruction.
    ///
    /// # Forms
    /// Assembly: `vnclipu.wv vm, vs2, vs1, vd`
    /// Rust: `vnclipu_wv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vnclipu_wv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VnclipuWvEmitter<T0, T1, T2, T3>,
    {
        <Self as VnclipuWvEmitter<T0, T1, T2, T3>>::vnclipu_wv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vnclipu.wx` instruction.
    ///
    /// # Forms
    /// Assembly: `vnclipu.wx vm, vs2, xs1, vd`
    /// Rust: `vnclipu_wx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vnclipu_wx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VnclipuWxEmitter<T0, T1, T2, T3>,
    {
        <Self as VnclipuWxEmitter<T0, T1, T2, T3>>::vnclipu_wx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vnmsac.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vnmsac.vv vm, vs2, vs1, vd`
    /// Rust: `vnmsac_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vnmsac_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VnmsacVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VnmsacVvEmitter<T0, T1, T2, T3>>::vnmsac_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vnmsac.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vnmsac.vx vm, vs2, xs1, vd`
    /// Rust: `vnmsac_vx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vnmsac_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VnmsacVxEmitter<T0, T1, T2, T3>,
    {
        <Self as VnmsacVxEmitter<T0, T1, T2, T3>>::vnmsac_vx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vnmsub.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vnmsub.vv vm, vs2, vs1, vd`
    /// Rust: `vnmsub_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vnmsub_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VnmsubVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VnmsubVvEmitter<T0, T1, T2, T3>>::vnmsub_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vnmsub.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vnmsub.vx vm, vs2, xs1, vd`
    /// Rust: `vnmsub_vx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vnmsub_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VnmsubVxEmitter<T0, T1, T2, T3>,
    {
        <Self as VnmsubVxEmitter<T0, T1, T2, T3>>::vnmsub_vx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vnsra.wi` instruction.
    ///
    /// # Forms
    /// Assembly: `vnsra.wi vm, vs2, vd, imm`
    /// Rust: `vnsra_wi(vd, vs2, zimm5, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `zimm5` — Immediate encoding value.
    /// - `vm` — Vector mask control.
    pub fn vnsra_wi<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, zimm5: T2, vm: T3)
    where
        Self: VnsraWiEmitter<T0, T1, T2, T3>,
    {
        <Self as VnsraWiEmitter<T0, T1, T2, T3>>::vnsra_wi(self, vd, vs2, zimm5, vm);
    }
    /// RISC-V `vnsra.wv` instruction.
    ///
    /// # Forms
    /// Assembly: `vnsra.wv vm, vs2, vs1, vd`
    /// Rust: `vnsra_wv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vnsra_wv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VnsraWvEmitter<T0, T1, T2, T3>,
    {
        <Self as VnsraWvEmitter<T0, T1, T2, T3>>::vnsra_wv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vnsra.wx` instruction.
    ///
    /// # Forms
    /// Assembly: `vnsra.wx vm, vs2, xs1, vd`
    /// Rust: `vnsra_wx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vnsra_wx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VnsraWxEmitter<T0, T1, T2, T3>,
    {
        <Self as VnsraWxEmitter<T0, T1, T2, T3>>::vnsra_wx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vnsrl.wi` instruction.
    ///
    /// # Forms
    /// Assembly: `vnsrl.wi vm, vs2, vd, imm`
    /// Rust: `vnsrl_wi(vd, vs2, zimm5, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `zimm5` — Immediate encoding value.
    /// - `vm` — Vector mask control.
    pub fn vnsrl_wi<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, zimm5: T2, vm: T3)
    where
        Self: VnsrlWiEmitter<T0, T1, T2, T3>,
    {
        <Self as VnsrlWiEmitter<T0, T1, T2, T3>>::vnsrl_wi(self, vd, vs2, zimm5, vm);
    }
    /// RISC-V `vnsrl.wv` instruction.
    ///
    /// # Forms
    /// Assembly: `vnsrl.wv vm, vs2, vs1, vd`
    /// Rust: `vnsrl_wv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vnsrl_wv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VnsrlWvEmitter<T0, T1, T2, T3>,
    {
        <Self as VnsrlWvEmitter<T0, T1, T2, T3>>::vnsrl_wv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vnsrl.wx` instruction.
    ///
    /// # Forms
    /// Assembly: `vnsrl.wx vm, vs2, xs1, vd`
    /// Rust: `vnsrl_wx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vnsrl_wx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VnsrlWxEmitter<T0, T1, T2, T3>,
    {
        <Self as VnsrlWxEmitter<T0, T1, T2, T3>>::vnsrl_wx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vor.vi` instruction.
    ///
    /// # Forms
    /// Assembly: `vor.vi vm, vs2, vd, imm`
    /// Rust: `vor_vi(vd, vs2, simm5, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `simm5` — Immediate encoding value.
    /// - `vm` — Vector mask control.
    pub fn vor_vi<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, simm5: T2, vm: T3)
    where
        Self: VorViEmitter<T0, T1, T2, T3>,
    {
        <Self as VorViEmitter<T0, T1, T2, T3>>::vor_vi(self, vd, vs2, simm5, vm);
    }
    /// RISC-V `vor.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vor.vv vm, vs2, vs1, vd`
    /// Rust: `vor_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vor_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VorVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VorVvEmitter<T0, T1, T2, T3>>::vor_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vor.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vor.vx vm, vs2, xs1, vd`
    /// Rust: `vor_vx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vor_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VorVxEmitter<T0, T1, T2, T3>,
    {
        <Self as VorVxEmitter<T0, T1, T2, T3>>::vor_vx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vpopc.m` instruction.
    ///
    /// # Forms
    /// Assembly: `vpopc.m rd vs2 vm`
    /// Rust: `vpopc_m(rd, vs2, vm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vpopc_m<T0, T1, T2>(&mut self, rd: T0, vs2: T1, vm: T2)
    where
        Self: VpopcMEmitter<T0, T1, T2>,
    {
        <Self as VpopcMEmitter<T0, T1, T2>>::vpopc_m(self, rd, vs2, vm);
    }
    /// RISC-V `vredand.vs` instruction.
    ///
    /// # Forms
    /// Assembly: `vredand.vs vm, vs2, vs1, vd`
    /// Rust: `vredand_vs(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vredand_vs<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VredandVsEmitter<T0, T1, T2, T3>,
    {
        <Self as VredandVsEmitter<T0, T1, T2, T3>>::vredand_vs(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vredmax.vs` instruction.
    ///
    /// # Forms
    /// Assembly: `vredmax.vs vm, vs2, vs1, vd`
    /// Rust: `vredmax_vs(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vredmax_vs<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VredmaxVsEmitter<T0, T1, T2, T3>,
    {
        <Self as VredmaxVsEmitter<T0, T1, T2, T3>>::vredmax_vs(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vredmaxu.vs` instruction.
    ///
    /// # Forms
    /// Assembly: `vredmaxu.vs vm, vs2, vs1, vd`
    /// Rust: `vredmaxu_vs(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vredmaxu_vs<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VredmaxuVsEmitter<T0, T1, T2, T3>,
    {
        <Self as VredmaxuVsEmitter<T0, T1, T2, T3>>::vredmaxu_vs(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vredmin.vs` instruction.
    ///
    /// # Forms
    /// Assembly: `vredmin.vs vm, vs2, vs1, vd`
    /// Rust: `vredmin_vs(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vredmin_vs<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VredminVsEmitter<T0, T1, T2, T3>,
    {
        <Self as VredminVsEmitter<T0, T1, T2, T3>>::vredmin_vs(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vredminu.vs` instruction.
    ///
    /// # Forms
    /// Assembly: `vredminu.vs vm, vs2, vs1, vd`
    /// Rust: `vredminu_vs(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vredminu_vs<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VredminuVsEmitter<T0, T1, T2, T3>,
    {
        <Self as VredminuVsEmitter<T0, T1, T2, T3>>::vredminu_vs(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vredor.vs` instruction.
    ///
    /// # Forms
    /// Assembly: `vredor.vs vm, vs2, vs1, vd`
    /// Rust: `vredor_vs(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vredor_vs<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VredorVsEmitter<T0, T1, T2, T3>,
    {
        <Self as VredorVsEmitter<T0, T1, T2, T3>>::vredor_vs(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vredsum.vs` instruction.
    ///
    /// # Forms
    /// Assembly: `vredsum.vs vm, vs2, vs1, vd`
    /// Rust: `vredsum_vs(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vredsum_vs<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VredsumVsEmitter<T0, T1, T2, T3>,
    {
        <Self as VredsumVsEmitter<T0, T1, T2, T3>>::vredsum_vs(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vredxor.vs` instruction.
    ///
    /// # Forms
    /// Assembly: `vredxor.vs vm, vs2, vs1, vd`
    /// Rust: `vredxor_vs(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vredxor_vs<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VredxorVsEmitter<T0, T1, T2, T3>,
    {
        <Self as VredxorVsEmitter<T0, T1, T2, T3>>::vredxor_vs(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vrem.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vrem.vv vm, vs2, vs1, vd`
    /// Rust: `vrem_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vrem_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VremVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VremVvEmitter<T0, T1, T2, T3>>::vrem_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vrem.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vrem.vx vm, vs2, xs1, vd`
    /// Rust: `vrem_vx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vrem_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VremVxEmitter<T0, T1, T2, T3>,
    {
        <Self as VremVxEmitter<T0, T1, T2, T3>>::vrem_vx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vremu.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vremu.vv vm, vs2, vs1, vd`
    /// Rust: `vremu_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vremu_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VremuVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VremuVvEmitter<T0, T1, T2, T3>>::vremu_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vremu.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vremu.vx vm, vs2, xs1, vd`
    /// Rust: `vremu_vx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vremu_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VremuVxEmitter<T0, T1, T2, T3>,
    {
        <Self as VremuVxEmitter<T0, T1, T2, T3>>::vremu_vx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vrev8.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vrev8.v vm, vs2, vd`
    /// Rust: `vrev8_v(vd, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vrev8_v<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
    where
        Self: Vrev8VEmitter<T0, T1, T2>,
    {
        <Self as Vrev8VEmitter<T0, T1, T2>>::vrev8_v(self, vd, vs2, vm);
    }
    /// RISC-V `vrgather.vi` instruction.
    ///
    /// # Forms
    /// Assembly: `vrgather.vi vm, vs2, vd, imm`
    /// Rust: `vrgather_vi(vd, vs2, zimm5, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `zimm5` — Immediate encoding value.
    /// - `vm` — Vector mask control.
    pub fn vrgather_vi<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, zimm5: T2, vm: T3)
    where
        Self: VrgatherViEmitter<T0, T1, T2, T3>,
    {
        <Self as VrgatherViEmitter<T0, T1, T2, T3>>::vrgather_vi(self, vd, vs2, zimm5, vm);
    }
    /// RISC-V `vrgather.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vrgather.vv vm, vs2, vs1, vd`
    /// Rust: `vrgather_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vrgather_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VrgatherVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VrgatherVvEmitter<T0, T1, T2, T3>>::vrgather_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vrgather.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vrgather.vx vm, vs2, xs1, vd`
    /// Rust: `vrgather_vx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vrgather_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VrgatherVxEmitter<T0, T1, T2, T3>,
    {
        <Self as VrgatherVxEmitter<T0, T1, T2, T3>>::vrgather_vx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vrgatherei16.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vrgatherei16.vv vm, vs2, vs1, vd`
    /// Rust: `vrgatherei16_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vrgatherei16_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: Vrgatherei16VvEmitter<T0, T1, T2, T3>,
    {
        <Self as Vrgatherei16VvEmitter<T0, T1, T2, T3>>::vrgatherei16_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vrol.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vrol.vv vm, vs2, vs1, vd`
    /// Rust: `vrol_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vrol_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VrolVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VrolVvEmitter<T0, T1, T2, T3>>::vrol_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vrol.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vrol.vx vm, vs2, xs1, vd`
    /// Rust: `vrol_vx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vrol_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VrolVxEmitter<T0, T1, T2, T3>,
    {
        <Self as VrolVxEmitter<T0, T1, T2, T3>>::vrol_vx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vror.vi` instruction.
    ///
    /// # Forms
    /// Assembly: `vror.vi vm, vs2, vd, imm`
    /// Rust: `vror_vi(vd, vs2, zimm6lohi, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `zimm6lohi` — Immediate encoding value.
    /// - `vm` — Vector mask control.
    pub fn vror_vi<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, zimm6lohi: T2, vm: T3)
    where
        Self: VrorViEmitter<T0, T1, T2, T3>,
    {
        <Self as VrorViEmitter<T0, T1, T2, T3>>::vror_vi(self, vd, vs2, zimm6lohi, vm);
    }
    /// RISC-V `vror.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vror.vv vm, vs2, vs1, vd`
    /// Rust: `vror_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vror_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VrorVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VrorVvEmitter<T0, T1, T2, T3>>::vror_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vror.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vror.vx vm, vs2, xs1, vd`
    /// Rust: `vror_vx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vror_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VrorVxEmitter<T0, T1, T2, T3>,
    {
        <Self as VrorVxEmitter<T0, T1, T2, T3>>::vror_vx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vrsub.vi` instruction.
    ///
    /// # Forms
    /// Assembly: `vrsub.vi vm, vs2, vd, imm`
    /// Rust: `vrsub_vi(vd, vs2, simm5, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `simm5` — Immediate encoding value.
    /// - `vm` — Vector mask control.
    pub fn vrsub_vi<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, simm5: T2, vm: T3)
    where
        Self: VrsubViEmitter<T0, T1, T2, T3>,
    {
        <Self as VrsubViEmitter<T0, T1, T2, T3>>::vrsub_vi(self, vd, vs2, simm5, vm);
    }
    /// RISC-V `vrsub.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vrsub.vx vm, vs2, xs1, vd`
    /// Rust: `vrsub_vx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vrsub_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VrsubVxEmitter<T0, T1, T2, T3>,
    {
        <Self as VrsubVxEmitter<T0, T1, T2, T3>>::vrsub_vx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vs1r.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vs1r.v xs1, vs3`
    /// Rust: `vs1r_v(vs3, rs1)`
    ///
    /// # Arguments
    /// - `vs3` — Vector register operand.
    /// - `rs1` — Memory base register.
    pub fn vs1r_v<T0, T1>(&mut self, vs3: T0, rs1: T1)
    where
        Self: Vs1RVEmitter<T0, T1>,
    {
        <Self as Vs1RVEmitter<T0, T1>>::vs1r_v(self, vs3, rs1);
    }
    /// RISC-V `vs2r.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vs2r.v xs1, vs3`
    /// Rust: `vs2r_v(vs3, rs1)`
    ///
    /// # Arguments
    /// - `vs3` — Vector register operand.
    /// - `rs1` — Memory base register.
    pub fn vs2r_v<T0, T1>(&mut self, vs3: T0, rs1: T1)
    where
        Self: Vs2RVEmitter<T0, T1>,
    {
        <Self as Vs2RVEmitter<T0, T1>>::vs2r_v(self, vs3, rs1);
    }
    /// RISC-V `vs4r.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vs4r.v xs1, vs3`
    /// Rust: `vs4r_v(vs3, rs1)`
    ///
    /// # Arguments
    /// - `vs3` — Vector register operand.
    /// - `rs1` — Memory base register.
    pub fn vs4r_v<T0, T1>(&mut self, vs3: T0, rs1: T1)
    where
        Self: Vs4RVEmitter<T0, T1>,
    {
        <Self as Vs4RVEmitter<T0, T1>>::vs4r_v(self, vs3, rs1);
    }
    /// RISC-V `vs8r.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vs8r.v xs1, vs3`
    /// Rust: `vs8r_v(vs3, rs1)`
    ///
    /// # Arguments
    /// - `vs3` — Vector register operand.
    /// - `rs1` — Memory base register.
    pub fn vs8r_v<T0, T1>(&mut self, vs3: T0, rs1: T1)
    where
        Self: Vs8RVEmitter<T0, T1>,
    {
        <Self as Vs8RVEmitter<T0, T1>>::vs8r_v(self, vs3, rs1);
    }
    /// RISC-V `vsadd.vi` instruction.
    ///
    /// # Forms
    /// Assembly: `vsadd.vi vm, vs2, vd, imm`
    /// Rust: `vsadd_vi(vd, vs2, simm5, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `simm5` — Immediate encoding value.
    /// - `vm` — Vector mask control.
    pub fn vsadd_vi<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, simm5: T2, vm: T3)
    where
        Self: VsaddViEmitter<T0, T1, T2, T3>,
    {
        <Self as VsaddViEmitter<T0, T1, T2, T3>>::vsadd_vi(self, vd, vs2, simm5, vm);
    }
    /// RISC-V `vsadd.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vsadd.vv vm, vs2, vs1, vd`
    /// Rust: `vsadd_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vsadd_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VsaddVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VsaddVvEmitter<T0, T1, T2, T3>>::vsadd_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vsadd.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vsadd.vx vm, vs2, xs1, vd`
    /// Rust: `vsadd_vx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vsadd_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VsaddVxEmitter<T0, T1, T2, T3>,
    {
        <Self as VsaddVxEmitter<T0, T1, T2, T3>>::vsadd_vx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vsaddu.vi` instruction.
    ///
    /// # Forms
    /// Assembly: `vsaddu.vi vm, vs2, vd, imm`
    /// Rust: `vsaddu_vi(vd, vs2, simm5, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `simm5` — Immediate encoding value.
    /// - `vm` — Vector mask control.
    pub fn vsaddu_vi<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, simm5: T2, vm: T3)
    where
        Self: VsadduViEmitter<T0, T1, T2, T3>,
    {
        <Self as VsadduViEmitter<T0, T1, T2, T3>>::vsaddu_vi(self, vd, vs2, simm5, vm);
    }
    /// RISC-V `vsaddu.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vsaddu.vv vm, vs2, vs1, vd`
    /// Rust: `vsaddu_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vsaddu_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VsadduVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VsadduVvEmitter<T0, T1, T2, T3>>::vsaddu_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vsaddu.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vsaddu.vx vm, vs2, xs1, vd`
    /// Rust: `vsaddu_vx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vsaddu_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VsadduVxEmitter<T0, T1, T2, T3>,
    {
        <Self as VsadduVxEmitter<T0, T1, T2, T3>>::vsaddu_vx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vsbc.vvm` instruction.
    ///
    /// # Forms
    /// Assembly: `vsbc.vvm vs2, vs1, vd`
    /// Rust: `vsbc_vvm(vd, vs1, vs2)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    pub fn vsbc_vvm<T0, T1, T2>(&mut self, vd: T0, vs1: T1, vs2: T2)
    where
        Self: VsbcVvmEmitter<T0, T1, T2>,
    {
        <Self as VsbcVvmEmitter<T0, T1, T2>>::vsbc_vvm(self, vd, vs1, vs2);
    }
    /// RISC-V `vsbc.vxm` instruction.
    ///
    /// # Forms
    /// Assembly: `vsbc.vxm vs2, xs1, vd`
    /// Rust: `vsbc_vxm(vd, rs1, vs2)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vs2` — Vector register operand.
    pub fn vsbc_vxm<T0, T1, T2>(&mut self, vd: T0, rs1: T1, vs2: T2)
    where
        Self: VsbcVxmEmitter<T0, T1, T2>,
    {
        <Self as VsbcVxmEmitter<T0, T1, T2>>::vsbc_vxm(self, vd, rs1, vs2);
    }
    /// RISC-V `vse16.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vse16.v vm, xs1, vs3`
    /// Rust: `vse16_v(vs3, rs1, vm, nf)`
    ///
    /// # Arguments
    /// - `vs3` — Vector register operand.
    /// - `rs1` — Memory base register.
    /// - `vm` — Vector mask control.
    /// - `nf` — Vector segment field count.
    pub fn vse16_v<T0, T1, T2, T3>(&mut self, vs3: T0, rs1: T1, vm: T2, nf: T3)
    where
        Self: Vse16VEmitter<T0, T1, T2, T3>,
    {
        <Self as Vse16VEmitter<T0, T1, T2, T3>>::vse16_v(self, vs3, rs1, vm, nf);
    }
    /// RISC-V `vse1.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vse1.v vs3 rs1`
    /// Rust: `vse1_v(vs3, rs1)`
    ///
    /// # Arguments
    /// - `vs3` — Vector register operand.
    /// - `rs1` — Memory base register.
    pub fn vse1_v<T0, T1>(&mut self, vs3: T0, rs1: T1)
    where
        Self: Vse1VEmitter<T0, T1>,
    {
        <Self as Vse1VEmitter<T0, T1>>::vse1_v(self, vs3, rs1);
    }
    /// RISC-V `vse32.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vse32.v vm, xs1, vs3`
    /// Rust: `vse32_v(vs3, rs1, vm, nf)`
    ///
    /// # Arguments
    /// - `vs3` — Vector register operand.
    /// - `rs1` — Memory base register.
    /// - `vm` — Vector mask control.
    /// - `nf` — Vector segment field count.
    pub fn vse32_v<T0, T1, T2, T3>(&mut self, vs3: T0, rs1: T1, vm: T2, nf: T3)
    where
        Self: Vse32VEmitter<T0, T1, T2, T3>,
    {
        <Self as Vse32VEmitter<T0, T1, T2, T3>>::vse32_v(self, vs3, rs1, vm, nf);
    }
    /// RISC-V `vse64.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vse64.v vm, xs1, vs3`
    /// Rust: `vse64_v(vs3, rs1, vm, nf)`
    ///
    /// # Arguments
    /// - `vs3` — Vector register operand.
    /// - `rs1` — Memory base register.
    /// - `vm` — Vector mask control.
    /// - `nf` — Vector segment field count.
    pub fn vse64_v<T0, T1, T2, T3>(&mut self, vs3: T0, rs1: T1, vm: T2, nf: T3)
    where
        Self: Vse64VEmitter<T0, T1, T2, T3>,
    {
        <Self as Vse64VEmitter<T0, T1, T2, T3>>::vse64_v(self, vs3, rs1, vm, nf);
    }
    /// RISC-V `vse8.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vse8.v vm, xs1, vs3`
    /// Rust: `vse8_v(vs3, rs1, vm, nf)`
    ///
    /// # Arguments
    /// - `vs3` — Vector register operand.
    /// - `rs1` — Memory base register.
    /// - `vm` — Vector mask control.
    /// - `nf` — Vector segment field count.
    pub fn vse8_v<T0, T1, T2, T3>(&mut self, vs3: T0, rs1: T1, vm: T2, nf: T3)
    where
        Self: Vse8VEmitter<T0, T1, T2, T3>,
    {
        <Self as Vse8VEmitter<T0, T1, T2, T3>>::vse8_v(self, vs3, rs1, vm, nf);
    }
    /// RISC-V `vsetivli` instruction.
    ///
    /// # Forms
    /// Assembly: `vsetivli xd, imm`
    /// Rust: `vsetivli(rd, zimm5, zimm10)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `zimm5` — Immediate encoding value.
    /// - `zimm10` — Immediate encoding value.
    pub fn vsetivli<T0, T1, T2>(&mut self, rd: T0, zimm5: T1, zimm10: T2)
    where
        Self: VsetivliEmitter<T0, T1, T2>,
    {
        <Self as VsetivliEmitter<T0, T1, T2>>::vsetivli(self, rd, zimm5, zimm10);
    }
    /// RISC-V `vsetvl` instruction.
    ///
    /// # Forms
    /// Assembly: `vsetvl xs2, xs1, xd`
    /// Rust: `vsetvl(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn vsetvl<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: VsetvlEmitter<T0, T1, T2>,
    {
        <Self as VsetvlEmitter<T0, T1, T2>>::vsetvl(self, rd, rs1, rs2);
    }
    /// RISC-V `vsetvli` instruction.
    ///
    /// # Forms
    /// Assembly: `vsetvli xs1, xd, imm`
    /// Rust: `vsetvli(rd, rs1, zimm11)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `zimm11` — Immediate encoding value.
    pub fn vsetvli<T0, T1, T2>(&mut self, rd: T0, rs1: T1, zimm11: T2)
    where
        Self: VsetvliEmitter<T0, T1, T2>,
    {
        <Self as VsetvliEmitter<T0, T1, T2>>::vsetvli(self, rd, rs1, zimm11);
    }
    /// RISC-V `vsext.vf2` instruction.
    ///
    /// # Forms
    /// Assembly: `vsext.vf2 vm, vs2, vd`
    /// Rust: `vsext_vf2(vd, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vsext_vf2<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
    where
        Self: VsextVf2Emitter<T0, T1, T2>,
    {
        <Self as VsextVf2Emitter<T0, T1, T2>>::vsext_vf2(self, vd, vs2, vm);
    }
    /// RISC-V `vsext.vf4` instruction.
    ///
    /// # Forms
    /// Assembly: `vsext.vf4 vm, vs2, vd`
    /// Rust: `vsext_vf4(vd, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vsext_vf4<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
    where
        Self: VsextVf4Emitter<T0, T1, T2>,
    {
        <Self as VsextVf4Emitter<T0, T1, T2>>::vsext_vf4(self, vd, vs2, vm);
    }
    /// RISC-V `vsext.vf8` instruction.
    ///
    /// # Forms
    /// Assembly: `vsext.vf8 vm, vs2, vd`
    /// Rust: `vsext_vf8(vd, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vsext_vf8<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
    where
        Self: VsextVf8Emitter<T0, T1, T2>,
    {
        <Self as VsextVf8Emitter<T0, T1, T2>>::vsext_vf8(self, vd, vs2, vm);
    }
    /// RISC-V `vsha2ch.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vsha2ch.vv vs2, vs1, vd`
    /// Rust: `vsha2ch_vv(vd, vs1, vs2)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    pub fn vsha2ch_vv<T0, T1, T2>(&mut self, vd: T0, vs1: T1, vs2: T2)
    where
        Self: Vsha2ChVvEmitter<T0, T1, T2>,
    {
        <Self as Vsha2ChVvEmitter<T0, T1, T2>>::vsha2ch_vv(self, vd, vs1, vs2);
    }
    /// RISC-V `vsha2cl.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vsha2cl.vv vs2, vs1, vd`
    /// Rust: `vsha2cl_vv(vd, vs1, vs2)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    pub fn vsha2cl_vv<T0, T1, T2>(&mut self, vd: T0, vs1: T1, vs2: T2)
    where
        Self: Vsha2ClVvEmitter<T0, T1, T2>,
    {
        <Self as Vsha2ClVvEmitter<T0, T1, T2>>::vsha2cl_vv(self, vd, vs1, vs2);
    }
    /// RISC-V `vsha2ms.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vsha2ms.vv vs2, vs1, vd`
    /// Rust: `vsha2ms_vv(vd, vs1, vs2)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    pub fn vsha2ms_vv<T0, T1, T2>(&mut self, vd: T0, vs1: T1, vs2: T2)
    where
        Self: Vsha2MsVvEmitter<T0, T1, T2>,
    {
        <Self as Vsha2MsVvEmitter<T0, T1, T2>>::vsha2ms_vv(self, vd, vs1, vs2);
    }
    /// RISC-V `vslide1down.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vslide1down.vx vm, vs2, xs1, vd`
    /// Rust: `vslide1down_vx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vslide1down_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: Vslide1DownVxEmitter<T0, T1, T2, T3>,
    {
        <Self as Vslide1DownVxEmitter<T0, T1, T2, T3>>::vslide1down_vx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vslide1up.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vslide1up.vx vm, vs2, xs1, vd`
    /// Rust: `vslide1up_vx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vslide1up_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: Vslide1UpVxEmitter<T0, T1, T2, T3>,
    {
        <Self as Vslide1UpVxEmitter<T0, T1, T2, T3>>::vslide1up_vx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vslidedown.vi` instruction.
    ///
    /// # Forms
    /// Assembly: `vslidedown.vi vm, vs2, vd, imm`
    /// Rust: `vslidedown_vi(vd, vs2, zimm5, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `zimm5` — Immediate encoding value.
    /// - `vm` — Vector mask control.
    pub fn vslidedown_vi<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, zimm5: T2, vm: T3)
    where
        Self: VslidedownViEmitter<T0, T1, T2, T3>,
    {
        <Self as VslidedownViEmitter<T0, T1, T2, T3>>::vslidedown_vi(self, vd, vs2, zimm5, vm);
    }
    /// RISC-V `vslidedown.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vslidedown.vx vm, vs2, xs1, vd`
    /// Rust: `vslidedown_vx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vslidedown_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VslidedownVxEmitter<T0, T1, T2, T3>,
    {
        <Self as VslidedownVxEmitter<T0, T1, T2, T3>>::vslidedown_vx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vslideup.vi` instruction.
    ///
    /// # Forms
    /// Assembly: `vslideup.vi vm, vs2, vd, imm`
    /// Rust: `vslideup_vi(vd, vs2, zimm5, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `zimm5` — Immediate encoding value.
    /// - `vm` — Vector mask control.
    pub fn vslideup_vi<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, zimm5: T2, vm: T3)
    where
        Self: VslideupViEmitter<T0, T1, T2, T3>,
    {
        <Self as VslideupViEmitter<T0, T1, T2, T3>>::vslideup_vi(self, vd, vs2, zimm5, vm);
    }
    /// RISC-V `vslideup.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vslideup.vx vm, vs2, xs1, vd`
    /// Rust: `vslideup_vx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vslideup_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VslideupVxEmitter<T0, T1, T2, T3>,
    {
        <Self as VslideupVxEmitter<T0, T1, T2, T3>>::vslideup_vx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vsll.vi` instruction.
    ///
    /// # Forms
    /// Assembly: `vsll.vi vm, vs2, vd, imm`
    /// Rust: `vsll_vi(vd, vs2, zimm5, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `zimm5` — Immediate encoding value.
    /// - `vm` — Vector mask control.
    pub fn vsll_vi<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, zimm5: T2, vm: T3)
    where
        Self: VsllViEmitter<T0, T1, T2, T3>,
    {
        <Self as VsllViEmitter<T0, T1, T2, T3>>::vsll_vi(self, vd, vs2, zimm5, vm);
    }
    /// RISC-V `vsll.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vsll.vv vm, vs2, vs1, vd`
    /// Rust: `vsll_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vsll_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VsllVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VsllVvEmitter<T0, T1, T2, T3>>::vsll_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vsll.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vsll.vx vm, vs2, xs1, vd`
    /// Rust: `vsll_vx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vsll_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VsllVxEmitter<T0, T1, T2, T3>,
    {
        <Self as VsllVxEmitter<T0, T1, T2, T3>>::vsll_vx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vsm3c.vi` instruction.
    ///
    /// # Forms
    /// Assembly: `vsm3c.vi vs2, vd, imm`
    /// Rust: `vsm3c_vi(vd, vs2, zimm5)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `zimm5` — Immediate encoding value.
    pub fn vsm3c_vi<T0, T1, T2>(&mut self, vd: T0, vs2: T1, zimm5: T2)
    where
        Self: Vsm3CViEmitter<T0, T1, T2>,
    {
        <Self as Vsm3CViEmitter<T0, T1, T2>>::vsm3c_vi(self, vd, vs2, zimm5);
    }
    /// RISC-V `vsm3me.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vsm3me.vv vs2, vs1, vd`
    /// Rust: `vsm3me_vv(vd, vs1, vs2)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    pub fn vsm3me_vv<T0, T1, T2>(&mut self, vd: T0, vs1: T1, vs2: T2)
    where
        Self: Vsm3MeVvEmitter<T0, T1, T2>,
    {
        <Self as Vsm3MeVvEmitter<T0, T1, T2>>::vsm3me_vv(self, vd, vs1, vs2);
    }
    /// RISC-V `vsm4k.vi` instruction.
    ///
    /// # Forms
    /// Assembly: `vsm4k.vi vs2, vd, imm`
    /// Rust: `vsm4k_vi(vd, vs2, zimm5)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `zimm5` — Immediate encoding value.
    pub fn vsm4k_vi<T0, T1, T2>(&mut self, vd: T0, vs2: T1, zimm5: T2)
    where
        Self: Vsm4KViEmitter<T0, T1, T2>,
    {
        <Self as Vsm4KViEmitter<T0, T1, T2>>::vsm4k_vi(self, vd, vs2, zimm5);
    }
    /// RISC-V `vsm4r.vs` instruction.
    ///
    /// # Forms
    /// Assembly: `vsm4r.vs vs2, vd`
    /// Rust: `vsm4r_vs(vd, vs2)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    pub fn vsm4r_vs<T0, T1>(&mut self, vd: T0, vs2: T1)
    where
        Self: Vsm4RVsEmitter<T0, T1>,
    {
        <Self as Vsm4RVsEmitter<T0, T1>>::vsm4r_vs(self, vd, vs2);
    }
    /// RISC-V `vsm4r.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vsm4r.vv vs2, vd`
    /// Rust: `vsm4r_vv(vd, vs2)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    pub fn vsm4r_vv<T0, T1>(&mut self, vd: T0, vs2: T1)
    where
        Self: Vsm4RVvEmitter<T0, T1>,
    {
        <Self as Vsm4RVvEmitter<T0, T1>>::vsm4r_vv(self, vd, vs2);
    }
    /// RISC-V `vsm.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vsm.v xs1, vs3`
    /// Rust: `vsm_v(vs3, rs1)`
    ///
    /// # Arguments
    /// - `vs3` — Vector register operand.
    /// - `rs1` — Memory base register.
    pub fn vsm_v<T0, T1>(&mut self, vs3: T0, rs1: T1)
    where
        Self: VsmVEmitter<T0, T1>,
    {
        <Self as VsmVEmitter<T0, T1>>::vsm_v(self, vs3, rs1);
    }
    /// RISC-V `vsmul.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vsmul.vv vm, vs2, vs1, vd`
    /// Rust: `vsmul_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vsmul_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VsmulVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VsmulVvEmitter<T0, T1, T2, T3>>::vsmul_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vsmul.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vsmul.vx vm, vs2, xs1, vd`
    /// Rust: `vsmul_vx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vsmul_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VsmulVxEmitter<T0, T1, T2, T3>,
    {
        <Self as VsmulVxEmitter<T0, T1, T2, T3>>::vsmul_vx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vsoxei16.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vsoxei16.v vm, vs2, xs1, vs3`
    /// Rust: `vsoxei16_v(vs3, rs1, vs2, vm, nf)`
    ///
    /// # Arguments
    /// - `vs3` — Vector register operand.
    /// - `rs1` — Memory base register.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    /// - `nf` — Vector segment field count.
    pub fn vsoxei16_v<T0, T1, T2, T3, T4>(&mut self, vs3: T0, rs1: T1, vs2: T2, vm: T3, nf: T4)
    where
        Self: Vsoxei16VEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as Vsoxei16VEmitter<T0, T1, T2, T3, T4>>::vsoxei16_v(self, vs3, rs1, vs2, vm, nf);
    }
    /// RISC-V `vsoxei32.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vsoxei32.v vm, vs2, xs1, vs3`
    /// Rust: `vsoxei32_v(vs3, rs1, vs2, vm, nf)`
    ///
    /// # Arguments
    /// - `vs3` — Vector register operand.
    /// - `rs1` — Memory base register.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    /// - `nf` — Vector segment field count.
    pub fn vsoxei32_v<T0, T1, T2, T3, T4>(&mut self, vs3: T0, rs1: T1, vs2: T2, vm: T3, nf: T4)
    where
        Self: Vsoxei32VEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as Vsoxei32VEmitter<T0, T1, T2, T3, T4>>::vsoxei32_v(self, vs3, rs1, vs2, vm, nf);
    }
    /// RISC-V `vsoxei64.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vsoxei64.v vm, vs2, xs1, vs3`
    /// Rust: `vsoxei64_v(vs3, rs1, vs2, vm, nf)`
    ///
    /// # Arguments
    /// - `vs3` — Vector register operand.
    /// - `rs1` — Memory base register.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    /// - `nf` — Vector segment field count.
    pub fn vsoxei64_v<T0, T1, T2, T3, T4>(&mut self, vs3: T0, rs1: T1, vs2: T2, vm: T3, nf: T4)
    where
        Self: Vsoxei64VEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as Vsoxei64VEmitter<T0, T1, T2, T3, T4>>::vsoxei64_v(self, vs3, rs1, vs2, vm, nf);
    }
    /// RISC-V `vsoxei8.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vsoxei8.v vm, vs2, xs1, vs3`
    /// Rust: `vsoxei8_v(vs3, rs1, vs2, vm, nf)`
    ///
    /// # Arguments
    /// - `vs3` — Vector register operand.
    /// - `rs1` — Memory base register.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    /// - `nf` — Vector segment field count.
    pub fn vsoxei8_v<T0, T1, T2, T3, T4>(&mut self, vs3: T0, rs1: T1, vs2: T2, vm: T3, nf: T4)
    where
        Self: Vsoxei8VEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as Vsoxei8VEmitter<T0, T1, T2, T3, T4>>::vsoxei8_v(self, vs3, rs1, vs2, vm, nf);
    }
    /// RISC-V `vsra.vi` instruction.
    ///
    /// # Forms
    /// Assembly: `vsra.vi vm, vs2, vd, imm`
    /// Rust: `vsra_vi(vd, vs2, zimm5, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `zimm5` — Immediate encoding value.
    /// - `vm` — Vector mask control.
    pub fn vsra_vi<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, zimm5: T2, vm: T3)
    where
        Self: VsraViEmitter<T0, T1, T2, T3>,
    {
        <Self as VsraViEmitter<T0, T1, T2, T3>>::vsra_vi(self, vd, vs2, zimm5, vm);
    }
    /// RISC-V `vsra.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vsra.vv vm, vs2, vs1, vd`
    /// Rust: `vsra_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vsra_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VsraVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VsraVvEmitter<T0, T1, T2, T3>>::vsra_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vsra.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vsra.vx vm, vs2, xs1, vd`
    /// Rust: `vsra_vx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vsra_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VsraVxEmitter<T0, T1, T2, T3>,
    {
        <Self as VsraVxEmitter<T0, T1, T2, T3>>::vsra_vx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vsrl.vi` instruction.
    ///
    /// # Forms
    /// Assembly: `vsrl.vi vm, vs2, vd, imm`
    /// Rust: `vsrl_vi(vd, vs2, zimm5, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `zimm5` — Immediate encoding value.
    /// - `vm` — Vector mask control.
    pub fn vsrl_vi<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, zimm5: T2, vm: T3)
    where
        Self: VsrlViEmitter<T0, T1, T2, T3>,
    {
        <Self as VsrlViEmitter<T0, T1, T2, T3>>::vsrl_vi(self, vd, vs2, zimm5, vm);
    }
    /// RISC-V `vsrl.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vsrl.vv vm, vs2, vs1, vd`
    /// Rust: `vsrl_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vsrl_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VsrlVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VsrlVvEmitter<T0, T1, T2, T3>>::vsrl_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vsrl.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vsrl.vx vm, vs2, xs1, vd`
    /// Rust: `vsrl_vx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vsrl_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VsrlVxEmitter<T0, T1, T2, T3>,
    {
        <Self as VsrlVxEmitter<T0, T1, T2, T3>>::vsrl_vx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vsse16.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vsse16.v vm, xs2, xs1, vs3`
    /// Rust: `vsse16_v(vs3, rs1, rs2, vm, nf)`
    ///
    /// # Arguments
    /// - `vs3` — Vector register operand.
    /// - `rs1` — Memory base register.
    /// - `rs2` — Source register.
    /// - `vm` — Vector mask control.
    /// - `nf` — Vector segment field count.
    pub fn vsse16_v<T0, T1, T2, T3, T4>(&mut self, vs3: T0, rs1: T1, rs2: T2, vm: T3, nf: T4)
    where
        Self: Vsse16VEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as Vsse16VEmitter<T0, T1, T2, T3, T4>>::vsse16_v(self, vs3, rs1, rs2, vm, nf);
    }
    /// RISC-V `vsse32.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vsse32.v vm, xs2, xs1, vs3`
    /// Rust: `vsse32_v(vs3, rs1, rs2, vm, nf)`
    ///
    /// # Arguments
    /// - `vs3` — Vector register operand.
    /// - `rs1` — Memory base register.
    /// - `rs2` — Source register.
    /// - `vm` — Vector mask control.
    /// - `nf` — Vector segment field count.
    pub fn vsse32_v<T0, T1, T2, T3, T4>(&mut self, vs3: T0, rs1: T1, rs2: T2, vm: T3, nf: T4)
    where
        Self: Vsse32VEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as Vsse32VEmitter<T0, T1, T2, T3, T4>>::vsse32_v(self, vs3, rs1, rs2, vm, nf);
    }
    /// RISC-V `vsse64.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vsse64.v vm, xs2, xs1, vs3`
    /// Rust: `vsse64_v(vs3, rs1, rs2, vm, nf)`
    ///
    /// # Arguments
    /// - `vs3` — Vector register operand.
    /// - `rs1` — Memory base register.
    /// - `rs2` — Source register.
    /// - `vm` — Vector mask control.
    /// - `nf` — Vector segment field count.
    pub fn vsse64_v<T0, T1, T2, T3, T4>(&mut self, vs3: T0, rs1: T1, rs2: T2, vm: T3, nf: T4)
    where
        Self: Vsse64VEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as Vsse64VEmitter<T0, T1, T2, T3, T4>>::vsse64_v(self, vs3, rs1, rs2, vm, nf);
    }
    /// RISC-V `vsse8.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vsse8.v vm, xs2, xs1, vs3`
    /// Rust: `vsse8_v(vs3, rs1, rs2, vm, nf)`
    ///
    /// # Arguments
    /// - `vs3` — Vector register operand.
    /// - `rs1` — Memory base register.
    /// - `rs2` — Source register.
    /// - `vm` — Vector mask control.
    /// - `nf` — Vector segment field count.
    pub fn vsse8_v<T0, T1, T2, T3, T4>(&mut self, vs3: T0, rs1: T1, rs2: T2, vm: T3, nf: T4)
    where
        Self: Vsse8VEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as Vsse8VEmitter<T0, T1, T2, T3, T4>>::vsse8_v(self, vs3, rs1, rs2, vm, nf);
    }
    /// RISC-V `vssra.vi` instruction.
    ///
    /// # Forms
    /// Assembly: `vssra.vi vm, vs2, vd, imm`
    /// Rust: `vssra_vi(vd, vs2, zimm5, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `zimm5` — Immediate encoding value.
    /// - `vm` — Vector mask control.
    pub fn vssra_vi<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, zimm5: T2, vm: T3)
    where
        Self: VssraViEmitter<T0, T1, T2, T3>,
    {
        <Self as VssraViEmitter<T0, T1, T2, T3>>::vssra_vi(self, vd, vs2, zimm5, vm);
    }
    /// RISC-V `vssra.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vssra.vv vm, vs2, vs1, vd`
    /// Rust: `vssra_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vssra_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VssraVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VssraVvEmitter<T0, T1, T2, T3>>::vssra_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vssra.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vssra.vx vm, vs2, xs1, vd`
    /// Rust: `vssra_vx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vssra_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VssraVxEmitter<T0, T1, T2, T3>,
    {
        <Self as VssraVxEmitter<T0, T1, T2, T3>>::vssra_vx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vssrl.vi` instruction.
    ///
    /// # Forms
    /// Assembly: `vssrl.vi vm, vs2, vd, imm`
    /// Rust: `vssrl_vi(vd, vs2, zimm5, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `zimm5` — Immediate encoding value.
    /// - `vm` — Vector mask control.
    pub fn vssrl_vi<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, zimm5: T2, vm: T3)
    where
        Self: VssrlViEmitter<T0, T1, T2, T3>,
    {
        <Self as VssrlViEmitter<T0, T1, T2, T3>>::vssrl_vi(self, vd, vs2, zimm5, vm);
    }
    /// RISC-V `vssrl.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vssrl.vv vm, vs2, vs1, vd`
    /// Rust: `vssrl_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vssrl_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VssrlVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VssrlVvEmitter<T0, T1, T2, T3>>::vssrl_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vssrl.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vssrl.vx vm, vs2, xs1, vd`
    /// Rust: `vssrl_vx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vssrl_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VssrlVxEmitter<T0, T1, T2, T3>,
    {
        <Self as VssrlVxEmitter<T0, T1, T2, T3>>::vssrl_vx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vssub.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vssub.vv vm, vs2, vs1, vd`
    /// Rust: `vssub_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vssub_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VssubVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VssubVvEmitter<T0, T1, T2, T3>>::vssub_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vssub.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vssub.vx vm, vs2, xs1, vd`
    /// Rust: `vssub_vx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vssub_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VssubVxEmitter<T0, T1, T2, T3>,
    {
        <Self as VssubVxEmitter<T0, T1, T2, T3>>::vssub_vx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vssubu.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vssubu.vv vm, vs2, vs1, vd`
    /// Rust: `vssubu_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vssubu_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VssubuVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VssubuVvEmitter<T0, T1, T2, T3>>::vssubu_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vssubu.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vssubu.vx vm, vs2, xs1, vd`
    /// Rust: `vssubu_vx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vssubu_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VssubuVxEmitter<T0, T1, T2, T3>,
    {
        <Self as VssubuVxEmitter<T0, T1, T2, T3>>::vssubu_vx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vsub.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vsub.vv vm, vs2, vs1, vd`
    /// Rust: `vsub_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vsub_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VsubVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VsubVvEmitter<T0, T1, T2, T3>>::vsub_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vsub.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vsub.vx vm, vs2, xs1, vd`
    /// Rust: `vsub_vx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vsub_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VsubVxEmitter<T0, T1, T2, T3>,
    {
        <Self as VsubVxEmitter<T0, T1, T2, T3>>::vsub_vx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vsuxei16.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vsuxei16.v vm, vs2, xs1, vs3`
    /// Rust: `vsuxei16_v(vs3, rs1, vs2, vm, nf)`
    ///
    /// # Arguments
    /// - `vs3` — Vector register operand.
    /// - `rs1` — Memory base register.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    /// - `nf` — Vector segment field count.
    pub fn vsuxei16_v<T0, T1, T2, T3, T4>(&mut self, vs3: T0, rs1: T1, vs2: T2, vm: T3, nf: T4)
    where
        Self: Vsuxei16VEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as Vsuxei16VEmitter<T0, T1, T2, T3, T4>>::vsuxei16_v(self, vs3, rs1, vs2, vm, nf);
    }
    /// RISC-V `vsuxei32.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vsuxei32.v vm, vs2, xs1, vs3`
    /// Rust: `vsuxei32_v(vs3, rs1, vs2, vm, nf)`
    ///
    /// # Arguments
    /// - `vs3` — Vector register operand.
    /// - `rs1` — Memory base register.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    /// - `nf` — Vector segment field count.
    pub fn vsuxei32_v<T0, T1, T2, T3, T4>(&mut self, vs3: T0, rs1: T1, vs2: T2, vm: T3, nf: T4)
    where
        Self: Vsuxei32VEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as Vsuxei32VEmitter<T0, T1, T2, T3, T4>>::vsuxei32_v(self, vs3, rs1, vs2, vm, nf);
    }
    /// RISC-V `vsuxei64.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vsuxei64.v vm, vs2, xs1, vs3`
    /// Rust: `vsuxei64_v(vs3, rs1, vs2, vm, nf)`
    ///
    /// # Arguments
    /// - `vs3` — Vector register operand.
    /// - `rs1` — Memory base register.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    /// - `nf` — Vector segment field count.
    pub fn vsuxei64_v<T0, T1, T2, T3, T4>(&mut self, vs3: T0, rs1: T1, vs2: T2, vm: T3, nf: T4)
    where
        Self: Vsuxei64VEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as Vsuxei64VEmitter<T0, T1, T2, T3, T4>>::vsuxei64_v(self, vs3, rs1, vs2, vm, nf);
    }
    /// RISC-V `vsuxei8.v` instruction.
    ///
    /// # Forms
    /// Assembly: `vsuxei8.v vm, vs2, xs1, vs3`
    /// Rust: `vsuxei8_v(vs3, rs1, vs2, vm, nf)`
    ///
    /// # Arguments
    /// - `vs3` — Vector register operand.
    /// - `rs1` — Memory base register.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    /// - `nf` — Vector segment field count.
    pub fn vsuxei8_v<T0, T1, T2, T3, T4>(&mut self, vs3: T0, rs1: T1, vs2: T2, vm: T3, nf: T4)
    where
        Self: Vsuxei8VEmitter<T0, T1, T2, T3, T4>,
    {
        <Self as Vsuxei8VEmitter<T0, T1, T2, T3, T4>>::vsuxei8_v(self, vs3, rs1, vs2, vm, nf);
    }
    /// RISC-V `vwadd.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vwadd.vv vm, vs2, vs1, vd`
    /// Rust: `vwadd_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vwadd_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VwaddVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VwaddVvEmitter<T0, T1, T2, T3>>::vwadd_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vwadd.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vwadd.vx vm, vs2, xs1, vd`
    /// Rust: `vwadd_vx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vwadd_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VwaddVxEmitter<T0, T1, T2, T3>,
    {
        <Self as VwaddVxEmitter<T0, T1, T2, T3>>::vwadd_vx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vwadd.wv` instruction.
    ///
    /// # Forms
    /// Assembly: `vwadd.wv vm, vs2, vs1, vd`
    /// Rust: `vwadd_wv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vwadd_wv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VwaddWvEmitter<T0, T1, T2, T3>,
    {
        <Self as VwaddWvEmitter<T0, T1, T2, T3>>::vwadd_wv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vwadd.wx` instruction.
    ///
    /// # Forms
    /// Assembly: `vwadd.wx vm, vs2, xs1, vd`
    /// Rust: `vwadd_wx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vwadd_wx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VwaddWxEmitter<T0, T1, T2, T3>,
    {
        <Self as VwaddWxEmitter<T0, T1, T2, T3>>::vwadd_wx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vwaddu.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vwaddu.vv vm, vs2, vs1, vd`
    /// Rust: `vwaddu_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vwaddu_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VwadduVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VwadduVvEmitter<T0, T1, T2, T3>>::vwaddu_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vwaddu.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vwaddu.vx vm, vs2, xs1, vd`
    /// Rust: `vwaddu_vx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vwaddu_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VwadduVxEmitter<T0, T1, T2, T3>,
    {
        <Self as VwadduVxEmitter<T0, T1, T2, T3>>::vwaddu_vx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vwaddu.wv` instruction.
    ///
    /// # Forms
    /// Assembly: `vwaddu.wv vm, vs2, vs1, vd`
    /// Rust: `vwaddu_wv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vwaddu_wv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VwadduWvEmitter<T0, T1, T2, T3>,
    {
        <Self as VwadduWvEmitter<T0, T1, T2, T3>>::vwaddu_wv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vwaddu.wx` instruction.
    ///
    /// # Forms
    /// Assembly: `vwaddu.wx vm, vs2, xs1, vd`
    /// Rust: `vwaddu_wx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vwaddu_wx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VwadduWxEmitter<T0, T1, T2, T3>,
    {
        <Self as VwadduWxEmitter<T0, T1, T2, T3>>::vwaddu_wx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vwmacc.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vwmacc.vv vm, vs2, vs1, vd`
    /// Rust: `vwmacc_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vwmacc_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VwmaccVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VwmaccVvEmitter<T0, T1, T2, T3>>::vwmacc_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vwmacc.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vwmacc.vx vm, vs2, xs1, vd`
    /// Rust: `vwmacc_vx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vwmacc_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VwmaccVxEmitter<T0, T1, T2, T3>,
    {
        <Self as VwmaccVxEmitter<T0, T1, T2, T3>>::vwmacc_vx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vwmaccsu.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vwmaccsu.vv vm, vs2, vs1, vd`
    /// Rust: `vwmaccsu_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vwmaccsu_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VwmaccsuVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VwmaccsuVvEmitter<T0, T1, T2, T3>>::vwmaccsu_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vwmaccsu.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vwmaccsu.vx vm, vs2, xs1, vd`
    /// Rust: `vwmaccsu_vx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vwmaccsu_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VwmaccsuVxEmitter<T0, T1, T2, T3>,
    {
        <Self as VwmaccsuVxEmitter<T0, T1, T2, T3>>::vwmaccsu_vx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vwmaccu.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vwmaccu.vv vm, vs2, vs1, vd`
    /// Rust: `vwmaccu_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vwmaccu_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VwmaccuVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VwmaccuVvEmitter<T0, T1, T2, T3>>::vwmaccu_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vwmaccu.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vwmaccu.vx vm, vs2, xs1, vd`
    /// Rust: `vwmaccu_vx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vwmaccu_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VwmaccuVxEmitter<T0, T1, T2, T3>,
    {
        <Self as VwmaccuVxEmitter<T0, T1, T2, T3>>::vwmaccu_vx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vwmaccus.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vwmaccus.vx vm, vs2, xs1, vd`
    /// Rust: `vwmaccus_vx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vwmaccus_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VwmaccusVxEmitter<T0, T1, T2, T3>,
    {
        <Self as VwmaccusVxEmitter<T0, T1, T2, T3>>::vwmaccus_vx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vwmul.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vwmul.vv vm, vs2, vs1, vd`
    /// Rust: `vwmul_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vwmul_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VwmulVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VwmulVvEmitter<T0, T1, T2, T3>>::vwmul_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vwmul.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vwmul.vx vm, vs2, xs1, vd`
    /// Rust: `vwmul_vx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vwmul_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VwmulVxEmitter<T0, T1, T2, T3>,
    {
        <Self as VwmulVxEmitter<T0, T1, T2, T3>>::vwmul_vx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vwmulsu.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vwmulsu.vv vm, vs2, vs1, vd`
    /// Rust: `vwmulsu_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vwmulsu_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VwmulsuVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VwmulsuVvEmitter<T0, T1, T2, T3>>::vwmulsu_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vwmulsu.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vwmulsu.vx vm, vs2, xs1, vd`
    /// Rust: `vwmulsu_vx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vwmulsu_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VwmulsuVxEmitter<T0, T1, T2, T3>,
    {
        <Self as VwmulsuVxEmitter<T0, T1, T2, T3>>::vwmulsu_vx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vwmulu.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vwmulu.vv vm, vs2, vs1, vd`
    /// Rust: `vwmulu_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vwmulu_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VwmuluVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VwmuluVvEmitter<T0, T1, T2, T3>>::vwmulu_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vwmulu.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vwmulu.vx vm, vs2, xs1, vd`
    /// Rust: `vwmulu_vx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vwmulu_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VwmuluVxEmitter<T0, T1, T2, T3>,
    {
        <Self as VwmuluVxEmitter<T0, T1, T2, T3>>::vwmulu_vx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vwredsum.vs` instruction.
    ///
    /// # Forms
    /// Assembly: `vwredsum.vs vm, vs2, vs1, vd`
    /// Rust: `vwredsum_vs(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vwredsum_vs<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VwredsumVsEmitter<T0, T1, T2, T3>,
    {
        <Self as VwredsumVsEmitter<T0, T1, T2, T3>>::vwredsum_vs(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vwredsumu.vs` instruction.
    ///
    /// # Forms
    /// Assembly: `vwredsumu.vs vm, vs2, vs1, vd`
    /// Rust: `vwredsumu_vs(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vwredsumu_vs<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VwredsumuVsEmitter<T0, T1, T2, T3>,
    {
        <Self as VwredsumuVsEmitter<T0, T1, T2, T3>>::vwredsumu_vs(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vwsll.vi` instruction.
    ///
    /// # Forms
    /// Assembly: `vwsll.vi vm, vs2, vd, imm`
    /// Rust: `vwsll_vi(vd, vs2, zimm5, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `zimm5` — Immediate encoding value.
    /// - `vm` — Vector mask control.
    pub fn vwsll_vi<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, zimm5: T2, vm: T3)
    where
        Self: VwsllViEmitter<T0, T1, T2, T3>,
    {
        <Self as VwsllViEmitter<T0, T1, T2, T3>>::vwsll_vi(self, vd, vs2, zimm5, vm);
    }
    /// RISC-V `vwsll.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vwsll.vv vm, vs2, vs1, vd`
    /// Rust: `vwsll_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vwsll_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VwsllVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VwsllVvEmitter<T0, T1, T2, T3>>::vwsll_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vwsll.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vwsll.vx vm, vs2, xs1, vd`
    /// Rust: `vwsll_vx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vwsll_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VwsllVxEmitter<T0, T1, T2, T3>,
    {
        <Self as VwsllVxEmitter<T0, T1, T2, T3>>::vwsll_vx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vwsub.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vwsub.vv vm, vs2, vs1, vd`
    /// Rust: `vwsub_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vwsub_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VwsubVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VwsubVvEmitter<T0, T1, T2, T3>>::vwsub_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vwsub.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vwsub.vx vm, vs2, xs1, vd`
    /// Rust: `vwsub_vx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vwsub_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VwsubVxEmitter<T0, T1, T2, T3>,
    {
        <Self as VwsubVxEmitter<T0, T1, T2, T3>>::vwsub_vx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vwsub.wv` instruction.
    ///
    /// # Forms
    /// Assembly: `vwsub.wv vm, vs2, vs1, vd`
    /// Rust: `vwsub_wv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vwsub_wv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VwsubWvEmitter<T0, T1, T2, T3>,
    {
        <Self as VwsubWvEmitter<T0, T1, T2, T3>>::vwsub_wv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vwsub.wx` instruction.
    ///
    /// # Forms
    /// Assembly: `vwsub.wx vm, vs2, xs1, vd`
    /// Rust: `vwsub_wx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vwsub_wx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VwsubWxEmitter<T0, T1, T2, T3>,
    {
        <Self as VwsubWxEmitter<T0, T1, T2, T3>>::vwsub_wx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vwsubu.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vwsubu.vv vm, vs2, vs1, vd`
    /// Rust: `vwsubu_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vwsubu_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VwsubuVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VwsubuVvEmitter<T0, T1, T2, T3>>::vwsubu_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vwsubu.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vwsubu.vx vm, vs2, xs1, vd`
    /// Rust: `vwsubu_vx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vwsubu_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VwsubuVxEmitter<T0, T1, T2, T3>,
    {
        <Self as VwsubuVxEmitter<T0, T1, T2, T3>>::vwsubu_vx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vwsubu.wv` instruction.
    ///
    /// # Forms
    /// Assembly: `vwsubu.wv vm, vs2, vs1, vd`
    /// Rust: `vwsubu_wv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vwsubu_wv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VwsubuWvEmitter<T0, T1, T2, T3>,
    {
        <Self as VwsubuWvEmitter<T0, T1, T2, T3>>::vwsubu_wv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vwsubu.wx` instruction.
    ///
    /// # Forms
    /// Assembly: `vwsubu.wx vm, vs2, xs1, vd`
    /// Rust: `vwsubu_wx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vwsubu_wx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VwsubuWxEmitter<T0, T1, T2, T3>,
    {
        <Self as VwsubuWxEmitter<T0, T1, T2, T3>>::vwsubu_wx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vxor.vi` instruction.
    ///
    /// # Forms
    /// Assembly: `vxor.vi vm, vs2, vd, imm`
    /// Rust: `vxor_vi(vd, vs2, simm5, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `simm5` — Immediate encoding value.
    /// - `vm` — Vector mask control.
    pub fn vxor_vi<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, simm5: T2, vm: T3)
    where
        Self: VxorViEmitter<T0, T1, T2, T3>,
    {
        <Self as VxorViEmitter<T0, T1, T2, T3>>::vxor_vi(self, vd, vs2, simm5, vm);
    }
    /// RISC-V `vxor.vv` instruction.
    ///
    /// # Forms
    /// Assembly: `vxor.vv vm, vs2, vs1, vd`
    /// Rust: `vxor_vv(vd, vs1, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs1` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vxor_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
    where
        Self: VxorVvEmitter<T0, T1, T2, T3>,
    {
        <Self as VxorVvEmitter<T0, T1, T2, T3>>::vxor_vv(self, vd, vs1, vs2, vm);
    }
    /// RISC-V `vxor.vx` instruction.
    ///
    /// # Forms
    /// Assembly: `vxor.vx vm, vs2, xs1, vd`
    /// Rust: `vxor_vx(vd, vs2, rs1, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `rs1` — Source register.
    /// - `vm` — Vector mask control.
    pub fn vxor_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
    where
        Self: VxorVxEmitter<T0, T1, T2, T3>,
    {
        <Self as VxorVxEmitter<T0, T1, T2, T3>>::vxor_vx(self, vd, vs2, rs1, vm);
    }
    /// RISC-V `vzext.vf2` instruction.
    ///
    /// # Forms
    /// Assembly: `vzext.vf2 vm, vs2, vd`
    /// Rust: `vzext_vf2(vd, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vzext_vf2<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
    where
        Self: VzextVf2Emitter<T0, T1, T2>,
    {
        <Self as VzextVf2Emitter<T0, T1, T2>>::vzext_vf2(self, vd, vs2, vm);
    }
    /// RISC-V `vzext.vf4` instruction.
    ///
    /// # Forms
    /// Assembly: `vzext.vf4 vm, vs2, vd`
    /// Rust: `vzext_vf4(vd, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vzext_vf4<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
    where
        Self: VzextVf4Emitter<T0, T1, T2>,
    {
        <Self as VzextVf4Emitter<T0, T1, T2>>::vzext_vf4(self, vd, vs2, vm);
    }
    /// RISC-V `vzext.vf8` instruction.
    ///
    /// # Forms
    /// Assembly: `vzext.vf8 vm, vs2, vd`
    /// Rust: `vzext_vf8(vd, vs2, vm)`
    ///
    /// # Arguments
    /// - `vd` — Vector register operand.
    /// - `vs2` — Vector register operand.
    /// - `vm` — Vector mask control.
    pub fn vzext_vf8<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
    where
        Self: VzextVf8Emitter<T0, T1, T2>,
    {
        <Self as VzextVf8Emitter<T0, T1, T2>>::vzext_vf8(self, vd, vs2, vm);
    }
    /// Wait for interrupt
    ///
    /// Can causes the processor to enter a low-power state until the next interrupt occurs.
    ///
    /// &lt;%- if ext?(:H) -%&gt;
    /// The behavior of `wfi` is affected by the `mstatus.TW`
    /// and `hstatus.VTW` bits, as summarized below.
    ///
    /// \[%autowidth,%footer\]
    /// |===
    /// .2+| \[.rotate\]#`mstatus.TW`# .2+| \[.rotate\]#`hstatus.VTW`# 4+^.&gt;| `wfi` behavior
    /// h| HS-mode h| U-mode h| VS-mode h| in VU-mode
    ///
    /// | 0 | 0 | Wait | Trap (I) | Wait | Trap (V)
    /// | 0 | 1 | Wait | Trap (I) | Trap (V) | Trap (V)
    /// | 1 | - | Trap (I) | Trap (I) | Trap (I) | Trap (I)
    ///
    /// 6+| Trap (I) - Trap with `Illegal Instruction` code +
    /// Trap (V) - Trap with `Virtual Instruction` code
    /// |===
    ///
    /// &lt;%- else -%&gt;
    /// The `wfi` instruction is also affected by `mstatus.TW`, as shown below:
    ///
    /// \[%autowidth,%footer\]
    /// |===
    /// .2+| \[.rotate\]#`mstatus.TW`# 2+^.&gt;| `wfi` behavior
    /// h| S-mode h| U-mode
    ///
    /// | 0 | Wait | Trap (I)
    /// | 1 | Trap (I) | Trap (I)
    ///
    /// 3+| Trap (I) - Trap with `Illegal Instruction` code
    /// |===
    ///
    /// &lt;%- end -%&gt;
    ///
    /// When `wfi` is marked as causing a trap above, the implementation is allowed to wait
    /// for an unspecified period of time to see if an interrupt occurs before raising the trap.
    /// That period of time can be zero (_i.e._, `wfi` always causes a trap in the cases identified
    /// above).
    ///
    /// # Forms
    /// Assembly: `wfi ""`
    /// Rust: `wfi()`
    ///
    /// # Arguments
    pub fn wfi(&mut self)
    where
        Self: WfiEmitter,
    {
        <Self as WfiEmitter>::wfi(self);
    }
    /// RISC-V `wrs.nto` instruction.
    ///
    /// # Forms
    /// Assembly: `wrs.nto wrs_nto`
    /// Rust: `wrs_nto()`
    ///
    /// # Arguments
    pub fn wrs_nto(&mut self)
    where
        Self: WrsNtoEmitter,
    {
        <Self as WrsNtoEmitter>::wrs_nto(self);
    }
    /// RISC-V `wrs.sto` instruction.
    ///
    /// # Forms
    /// Assembly: `wrs.sto wrs_sto`
    /// Rust: `wrs_sto()`
    ///
    /// # Arguments
    pub fn wrs_sto(&mut self)
    where
        Self: WrsStoEmitter,
    {
        <Self as WrsStoEmitter>::wrs_sto(self);
    }
    /// Exclusive NOR
    ///
    /// This instruction performs the bit-wise exclusive-NOR operation on rs1 and rs2.
    ///
    /// # Forms
    /// Assembly: `xnor xd, xs1, xs2`
    /// Rust: `xnor(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn xnor<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: XnorEmitter<T0, T1, T2>,
    {
        <Self as XnorEmitter<T0, T1, T2>>::xnor(self, rd, rs1, rs2);
    }
    /// Exclusive Or
    ///
    /// Exclusive or rs1 with rs2, and store the result in rd
    ///
    /// # Forms
    /// Assembly: `xor xd, xs1, xs2`
    /// Rust: `xor(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn xor<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: XorEmitter<T0, T1, T2>,
    {
        <Self as XorEmitter<T0, T1, T2>>::xor(self, rd, rs1, rs2);
    }
    /// Exclusive Or immediate
    ///
    /// Exclusive or an immediate to the value in rs1, and store the result in rd
    ///
    /// # Forms
    /// Assembly: `xori xd, xs1, imm`
    /// Rust: `xori(rd, rs1, imm)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `imm` — Immediate encoding value.
    pub fn xori<T0, T1, T2>(&mut self, rd: T0, rs1: T1, imm: T2)
    where
        Self: XoriEmitter<T0, T1, T2>,
    {
        <Self as XoriEmitter<T0, T1, T2>>::xori(self, rd, rs1, imm);
    }
    /// Crossbar permutation (nibbles)
    ///
    /// The xperm4 instruction operates on nibbles. The rs1 register contains a vector of XLEN/4 4-bit
    /// elements. The rs2 register contains a vector of XLEN/4 4-bit indexes. The result is each element in
    /// rs2 replaced by the indexed element in rs1, or zero if the index into rs2 is out of bounds.
    ///
    /// # Forms
    /// Assembly: `xperm4 xd, xs1, xs2`
    /// Rust: `xperm4(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn xperm4<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: Xperm4Emitter<T0, T1, T2>,
    {
        <Self as Xperm4Emitter<T0, T1, T2>>::xperm4(self, rd, rs1, rs2);
    }
    /// Crossbar permutation (bytes)
    ///
    /// The xperm8 instruction operates on bytes. The rs1 register contains a vector of XLEN/8 8-bit
    /// elements. The rs2 register contains a vector of XLEN/8 8-bit indexes. The result is each element in
    /// rs2 replaced by the indexed element in rs1, or zero if the index into rs2 is out of bounds.
    ///
    /// # Forms
    /// Assembly: `xperm8 xd, xs1, xs2`
    /// Rust: `xperm8(rd, rs1, rs2)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    /// - `rs2` — Source register.
    pub fn xperm8<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
    where
        Self: Xperm8Emitter<T0, T1, T2>,
    {
        <Self as Xperm8Emitter<T0, T1, T2>>::xperm8(self, rd, rs1, rs2);
    }
    /// RISC-V `zext.b` instruction.
    ///
    /// # Forms
    /// Assembly: `zext.b rd rs1`
    /// Rust: `zext_b(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn zext_b<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: ZextBEmitter<T0, T1>,
    {
        <Self as ZextBEmitter<T0, T1>>::zext_b(self, rd, rs1);
    }
    /// Zero-extend halfword
    ///
    /// This instruction zero-extends the least-significant halfword of the source to XLEN by inserting
    /// 0's into all of the bits more significant than 15.
    ///
    /// \[NOTE\]
    /// The *zext.h* instruction is a pseudo-op for `pack` when `Zbkb` is implemented and XLEN == 32.
    ///
    /// \[NOTE\]
    /// The *zext.h* instruction is a pseudo-op for `packw` when `Zbkb` is implemented and XLEN == 64.
    ///
    /// # Forms
    /// Assembly: `zext.h xd, xs1`
    /// Rust: `zext_h(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn zext_h<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: ZextHEmitter<T0, T1>,
    {
        <Self as ZextHEmitter<T0, T1>>::zext_h(self, rd, rs1);
    }
    /// Zero-extend halfword
    ///
    /// This instruction zero-extends the least-significant halfword of the source to XLEN by inserting
    /// 0's into all of the bits more significant than 15.
    ///
    /// \[NOTE\]
    /// The *zext.h* instruction is a pseudo-op for `pack` when `Zbkb` is implemented and XLEN == 32.
    ///
    /// \[NOTE\]
    /// The *zext.h* instruction is a pseudo-op for `packw` when `Zbkb` is implemented and XLEN == 64.
    ///
    /// # Forms
    /// Assembly: `zext.h.rv32 xd, xs1`
    /// Rust: `zext_h_rv32(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn zext_h_rv32<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: ZextHRv32Emitter<T0, T1>,
    {
        <Self as ZextHRv32Emitter<T0, T1>>::zext_h_rv32(self, rd, rs1);
    }
    /// RISC-V `zext.w` instruction.
    ///
    /// # Forms
    /// Assembly: `zext.w rd rs1`
    /// Rust: `zext_w(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn zext_w<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: ZextWEmitter<T0, T1>,
    {
        <Self as ZextWEmitter<T0, T1>>::zext_w(self, rd, rs1);
    }
    /// Bit interleave
    ///
    /// This instruction scatters all of the odd and even bits of a source word into the high and low halves
    /// of a destination word. It is the inverse of the unzip instruction. This instruction is available only on
    /// RV32.
    ///
    /// # Forms
    /// Assembly: `zip xd, xs1`
    /// Rust: `zip(rd, rs1)`
    ///
    /// # Arguments
    /// - `rd` — Destination register.
    /// - `rs1` — Source register.
    pub fn zip<T0, T1>(&mut self, rd: T0, rs1: T1)
    where
        Self: ZipEmitter<T0, T1>,
    {
        <Self as ZipEmitter<T0, T1>>::zip(self, rd, rs1);
    }
}