asmkit/aarch64/
emitter.rs

1//! AArch64 emitter traits generated by `meta/arm64.py` from `meta/arm64.txt`
2//! and AsmJit's pinned `db/isa_aarch64.json`. Do not edit by hand; regenerate
3//! instead.
4//!
5//! Each trait represents one mnemonic and operand arity. `Assembler` forwards
6//! every implementation to `emit_n`; the Rust parameter names describe the
7//! corresponding AArch64 assembly operand where that is known.
8#![allow(non_snake_case, non_camel_case_types)]
9use super::{assembler::*, instdb::*, operands::*};
10use crate::core::globals::CondCode;
11use crate::core::operand::*;
12
13/// Emits the `ADC` instruction.
14/// Assembly forms: `ADC WD, WN, WM`; `ADC XD, XN, XM`.
15/// Operands: `rd`, `rn`, `rm`.
16pub trait AdcEmitter<T0, T1, T2> {
17    fn adc(&mut self, rd: T0, rn: T1, rm: T2);
18}
19
20/// Emits the `ADCS` instruction.
21/// Assembly forms: `ADCS WD, WN, WM`; `ADCS XD, XN, XM`.
22/// Operands: `rd`, `rn`, `rm`.
23pub trait AdcsEmitter<T0, T1, T2> {
24    fn adcs(&mut self, rd: T0, rn: T1, rm: T2);
25}
26
27/// Emits the `ADD` instruction.
28/// Assembly forms: `ADD WD, WN, WM, {LSL|LSR|ASR #N}`; `ADD XD, XN, XM, {LSL|LSR|ASR #N}`; `ADD WD|WSP, WN|WSP, WM, {EXTEND #N}`; `ADD XD|SP, XN|SP, RM, {EXTEND #N}` (and related forms).
29/// Operands: `rd`, `rn`, `rm_or_imm`.
30pub trait AddEmitter<T0, T1, T2> {
31    fn add(&mut self, rd: T0, rn: T1, rm_or_imm: T2);
32}
33
34/// Emits the `ADD_4` instruction.
35/// Assembly forms: `ADD WD, WN, WM, {LSL|LSR|ASR #N}`; `ADD XD, XN, XM, {LSL|LSR|ASR #N}`; `ADD WD|WSP, WN|WSP, WM, {EXTEND #N}`; `ADD XD|SP, XN|SP, RM, {EXTEND #N}` (and related forms).
36/// Operands: `rd`, `rn`, `rm_or_imm`, `shift`.
37pub trait Add4Emitter<T0, T1, T2, T3> {
38    fn add_4(&mut self, rd: T0, rn: T1, rm_or_imm: T2, shift: T3);
39}
40
41/// Emits the `ADDS` instruction.
42/// Assembly forms: `ADDS WD, WN, WM, {LSL|LSR|ASR #N}`; `ADDS XD, XN, XM, {LSL|LSR|ASR #N}`; `ADDS WD, WN|WSP, WM, {EXTEND #N}`; `ADDS XD, XN|SP, RM, {EXTEND #N}` (and related forms).
43/// Operands: `rd`, `rn`, `rm_or_imm`.
44pub trait AddsEmitter<T0, T1, T2> {
45    fn adds(&mut self, rd: T0, rn: T1, rm_or_imm: T2);
46}
47
48/// Emits the `ADDS_4` instruction.
49/// Assembly forms: `ADDS WD, WN, WM, {LSL|LSR|ASR #N}`; `ADDS XD, XN, XM, {LSL|LSR|ASR #N}`; `ADDS WD, WN|WSP, WM, {EXTEND #N}`; `ADDS XD, XN|SP, RM, {EXTEND #N}` (and related forms).
50/// Operands: `rd`, `rn`, `rm_or_imm`, `shift`.
51pub trait Adds4Emitter<T0, T1, T2, T3> {
52    fn adds_4(&mut self, rd: T0, rn: T1, rm_or_imm: T2, shift: T3);
53}
54
55/// Emits the `ADR` instruction.
56/// Assembly forms: `ADR XD, #RELS`.
57/// Operands: `rd`, `target`.
58pub trait AdrEmitter<T0, T1> {
59    fn adr(&mut self, rd: T0, target: T1);
60}
61
62/// Emits the `ADRP` instruction.
63/// Assembly forms: `ADRP XD, #RELS`.
64/// Operands: `rd`, `target`.
65pub trait AdrpEmitter<T0, T1> {
66    fn adrp(&mut self, rd: T0, target: T1);
67}
68
69/// Emits the `AND_` instruction.
70/// Assembly forms: `AND WD|WSP, WN, WM, {SOP #N}`; `AND XD|SP, XN, XM, {SOP #N}`; `AND WD|WSP, WN, #IMM`; `AND XD|SP, XN, #IMM` (and related forms).
71/// Operands: `rd`, `rn`, `rm_or_imm`.
72pub trait AndEmitter<T0, T1, T2> {
73    fn and_(&mut self, rd: T0, rn: T1, rm_or_imm: T2);
74}
75
76/// Emits the `AND__4` instruction.
77/// Assembly forms: `AND WD|WSP, WN, WM, {SOP #N}`; `AND XD|SP, XN, XM, {SOP #N}`; `AND WD|WSP, WN, #IMM`; `AND XD|SP, XN, #IMM` (and related forms).
78/// Operands: `rd`, `rn`, `rm`, `shift`.
79pub trait And4Emitter<T0, T1, T2, T3> {
80    fn and__4(&mut self, rd: T0, rn: T1, rm: T2, shift: T3);
81}
82
83/// Emits the `ANDS` instruction.
84/// Assembly forms: `ANDS WD|WSP, WN, WM, {SOP #N}`; `ANDS XD|SP, XN, XM, {SOP #N}`; `ANDS WD|WSP, WN, #IMM`; `ANDS XD|SP, XN, #IMM`.
85/// Operands: `rd`, `rn`, `rm_or_imm`.
86pub trait AndsEmitter<T0, T1, T2> {
87    fn ands(&mut self, rd: T0, rn: T1, rm_or_imm: T2);
88}
89
90/// Emits the `ANDS_4` instruction.
91/// Assembly forms: `ANDS WD|WSP, WN, WM, {SOP #N}`; `ANDS XD|SP, XN, XM, {SOP #N}`; `ANDS WD|WSP, WN, #IMM`; `ANDS XD|SP, XN, #IMM`.
92/// Operands: `rd`, `rn`, `rm`, `shift`.
93pub trait Ands4Emitter<T0, T1, T2, T3> {
94    fn ands_4(&mut self, rd: T0, rn: T1, rm: T2, shift: T3);
95}
96
97/// Emits the `ASR` instruction.
98/// Assembly forms: `ASR|ASRV WD, WN, WM`; `ASR|ASRV XD, XN, XM`; `ASR WD, WN, #N`; `ASR XD, XN, #N`.
99/// Operands: `rd`, `rn`, `rm_or_shift`.
100pub trait AsrEmitter<T0, T1, T2> {
101    fn asr(&mut self, rd: T0, rn: T1, rm_or_shift: T2);
102}
103
104/// Emits the `ASRV` instruction.
105/// Assembly forms: `ASR|ASRV WD, WN, WM`; `ASR|ASRV XD, XN, XM`.
106/// Operands: `rd`, `rn`, `rm`.
107pub trait AsrvEmitter<T0, T1, T2> {
108    fn asrv(&mut self, rd: T0, rn: T1, rm: T2);
109}
110
111/// Emits the `AT` instruction.
112/// Assembly forms: `AT #AT_OP, XT`.
113/// Operands: `at_op`, `rt`.
114pub trait AtEmitter<T0, T1> {
115    fn at(&mut self, at_op: T0, rt: T1);
116}
117
118/// Emits the `BFC` instruction.
119/// Assembly forms: `BFC WD, #LSB, #WIDTH`; `BFC XD, #LSB, #WIDTH`.
120/// Operands: `rd`, `lsb`, `width`.
121pub trait BfcEmitter<T0, T1, T2> {
122    fn bfc(&mut self, rd: T0, lsb: T1, width: T2);
123}
124
125/// Emits the `BFI` instruction.
126/// Assembly forms: `BFI WD, WN, #LSB, #WIDTH`; `BFI XD, XN, #LSB, #WIDTH`.
127/// Operands: `rd`, `rn`, `lsb`, `width`.
128pub trait BfiEmitter<T0, T1, T2, T3> {
129    fn bfi(&mut self, rd: T0, rn: T1, lsb: T2, width: T3);
130}
131
132/// Emits the `BFM` instruction.
133/// Assembly forms: `BFM WD, WN, #IMMR, #IMMS`; `BFM XD, XN, #IMMR, #IMMS`.
134/// Operands: `rd`, `rn`, `imm`, `imm_2`.
135pub trait BfmEmitter<T0, T1, T2, T3> {
136    fn bfm(&mut self, rd: T0, rn: T1, imm: T2, imm_2: T3);
137}
138
139/// Emits the `BFXIL` instruction.
140/// Assembly forms: `BFXIL WD, WN, #LSB, #WIDTH`; `BFXIL XD, XN, #LSB, #WIDTH`.
141/// Operands: `rd`, `rn`, `lsb`, `width`.
142pub trait BfxilEmitter<T0, T1, T2, T3> {
143    fn bfxil(&mut self, rd: T0, rn: T1, lsb: T2, width: T3);
144}
145
146/// Emits the `BIC` instruction.
147/// Assembly forms: `BIC WD, WN, WM, {SOP #N}`; `BIC XD, XN, XM, {SOP #N}`; `BIC VD.8B, VN.8B, VM.8B`; `BIC VD.16B, VN.16B, VM.16B` (and related forms).
148/// Operands: `rd`, `rn_or_imm`, `rm_or_shift`.
149pub trait BicEmitter<T0, T1, T2> {
150    fn bic(&mut self, rd: T0, rn_or_imm: T1, rm_or_shift: T2);
151}
152
153/// Emits the `BIC_4` instruction.
154/// Assembly forms: `BIC WD, WN, WM, {SOP #N}`; `BIC XD, XN, XM, {SOP #N}`; `BIC VD.8B, VN.8B, VM.8B`; `BIC VD.16B, VN.16B, VM.16B` (and related forms).
155/// Operands: `rd`, `rn`, `rm`, `shift`.
156pub trait Bic4Emitter<T0, T1, T2, T3> {
157    fn bic_4(&mut self, rd: T0, rn: T1, rm: T2, shift: T3);
158}
159
160/// Emits the `BICS` instruction.
161/// Assembly forms: `BICS WD, WN, WM, {SOP #N}`; `BICS XD, XN, XM, {SOP #N}`.
162/// Operands: `rd`, `rn`, `rm`.
163pub trait BicsEmitter<T0, T1, T2> {
164    fn bics(&mut self, rd: T0, rn: T1, rm: T2);
165}
166
167/// Emits the `BICS_4` instruction.
168/// Assembly forms: `BICS WD, WN, WM, {SOP #N}`; `BICS XD, XN, XM, {SOP #N}`.
169/// Operands: `rd`, `rn`, `rm`, `shift`.
170pub trait Bics4Emitter<T0, T1, T2, T3> {
171    fn bics_4(&mut self, rd: T0, rn: T1, rm: T2, shift: T3);
172}
173
174/// Emits the `BRK` instruction.
175/// Assembly forms: `BRK #IMM`.
176/// Operands: `imm`.
177pub trait BrkEmitter<T0> {
178    fn brk(&mut self, imm: T0);
179}
180
181/// Emits the `CCMN` instruction.
182/// Assembly forms: `CCMN WN, WM, #NZCV, #COND`; `CCMN XN, XM, #NZCV, #COND`; `CCMN WN, #IMM, #NZCV, #COND`; `CCMN XN, #IMM, #NZCV, #COND`.
183/// Operands: `rn`, `rm_or_imm`, `flags`, `condition`.
184pub trait CcmnEmitter<T0, T1, T2, T3> {
185    fn ccmn(&mut self, rn: T0, rm_or_imm: T1, flags: T2, condition: T3);
186}
187
188/// Emits the `CCMP` instruction.
189/// Assembly forms: `CCMP WN, WM, #NZCV, #COND`; `CCMP XN, XM, #NZCV, #COND`; `CCMP WN, #IMM, #NZCV, #COND`; `CCMP XN, #IMM, #NZCV, #COND`.
190/// Operands: `rn`, `rm_or_imm`, `flags`, `condition`.
191pub trait CcmpEmitter<T0, T1, T2, T3> {
192    fn ccmp(&mut self, rn: T0, rm_or_imm: T1, flags: T2, condition: T3);
193}
194
195/// Emits the `CINC` instruction.
196/// Assembly forms: `CINC WD, WN, #COND`; `CINC XD, XN, #COND`.
197/// Operands: `rd`, `rn`, `condition`.
198pub trait CincEmitter<T0, T1, T2> {
199    fn cinc(&mut self, rd: T0, rn: T1, condition: T2);
200}
201
202/// Emits the `CINV` instruction.
203/// Assembly forms: `CINV WD, WN, #COND`; `CINV XD, XN, #COND`.
204/// Operands: `rd`, `rn`, `condition`.
205pub trait CinvEmitter<T0, T1, T2> {
206    fn cinv(&mut self, rd: T0, rn: T1, condition: T2);
207}
208
209/// Emits the `CLREX` instruction.
210/// Assembly forms: `CLREX {#IMM=15}`.
211/// Operands: `imm`.
212pub trait ClrexEmitter<T0> {
213    fn clrex(&mut self, imm: T0);
214}
215
216/// Emits the `CLS` instruction.
217/// Assembly forms: `CLS WD, WN`; `CLS XD, XN`; `CLS VD.T, VN.T`; `CLS VD.T, VN.T`.
218/// Operands: `rd`, `rn`.
219pub trait ClsEmitter<T0, T1> {
220    fn cls(&mut self, rd: T0, rn: T1);
221}
222
223/// Emits the `CLZ` instruction.
224/// Assembly forms: `CLZ WD, WN`; `CLZ XD, XN`; `CLZ VD.T, VN.T`; `CLZ VD.T, VN.T`.
225/// Operands: `rd`, `rn`.
226pub trait ClzEmitter<T0, T1> {
227    fn clz(&mut self, rd: T0, rn: T1);
228}
229
230/// Emits the `CMN` instruction.
231/// Assembly forms: `CMN WN|WSP, #IMM, {LSL #N=0|12}`; `CMN XN|SP, #IMM, {LSL #N=0|12}`; `CMN WN|WSP, WM, {EXTEND #N}`; `CMN XN|SP, RM, {EXTEND #N}` (and related forms).
232/// Operands: `rn`, `imm_or_rm`.
233pub trait CmnEmitter<T0, T1> {
234    fn cmn(&mut self, rn: T0, imm_or_rm: T1);
235}
236
237/// Emits the `CMN_3` instruction.
238/// Assembly forms: `CMN WN|WSP, #IMM, {LSL #N=0|12}`; `CMN XN|SP, #IMM, {LSL #N=0|12}`; `CMN WN|WSP, WM, {EXTEND #N}`; `CMN XN|SP, RM, {EXTEND #N}` (and related forms).
239/// Operands: `rn`, `imm_or_rm`, `shift`.
240pub trait Cmn3Emitter<T0, T1, T2> {
241    fn cmn_3(&mut self, rn: T0, imm_or_rm: T1, shift: T2);
242}
243
244/// Emits the `CMP` instruction.
245/// Assembly forms: `CMP WN, WM, {LSL|LSR|ASR #N}`; `CMP XN, XM, {LSL|LSR|ASR #N}`; `CMP WN|WSP, WM, {EXTEND #N}`; `CMP XN|SP, RM, {EXTEND #N}` (and related forms).
246/// Operands: `rn`, `rm_or_imm`.
247pub trait CmpEmitter<T0, T1> {
248    fn cmp(&mut self, rn: T0, rm_or_imm: T1);
249}
250
251/// Emits the `CMP_3` instruction.
252/// Assembly forms: `CMP WN, WM, {LSL|LSR|ASR #N}`; `CMP XN, XM, {LSL|LSR|ASR #N}`; `CMP WN|WSP, WM, {EXTEND #N}`; `CMP XN|SP, RM, {EXTEND #N}` (and related forms).
253/// Operands: `rn`, `rm_or_imm`, `shift`.
254pub trait Cmp3Emitter<T0, T1, T2> {
255    fn cmp_3(&mut self, rn: T0, rm_or_imm: T1, shift: T2);
256}
257
258/// Emits the `CNEG` instruction.
259/// Assembly forms: `CNEG WD, WN, #COND`; `CNEG XD, XN, #COND`.
260/// Operands: `rd`, `rn`, `condition`.
261pub trait CnegEmitter<T0, T1, T2> {
262    fn cneg(&mut self, rd: T0, rn: T1, condition: T2);
263}
264
265/// Emits the `CSEL` instruction.
266/// Assembly forms: `CSEL WD, WN, WM, #COND`; `CSEL XD, XN, XM, #COND`.
267/// Operands: `rd`, `rn`, `rm`, `condition`.
268pub trait CselEmitter<T0, T1, T2, T3> {
269    fn csel(&mut self, rd: T0, rn: T1, rm: T2, condition: T3);
270}
271
272/// Emits the `CSET` instruction.
273/// Assembly forms: `CSET WD, #COND`; `CSET XD, #COND`.
274/// Operands: `rd`, `condition`.
275pub trait CsetEmitter<T0, T1> {
276    fn cset(&mut self, rd: T0, condition: T1);
277}
278
279/// Emits the `CSETM` instruction.
280/// Assembly forms: `CSETM WD, #COND`; `CSETM XD, #COND`.
281/// Operands: `rd`, `condition`.
282pub trait CsetmEmitter<T0, T1> {
283    fn csetm(&mut self, rd: T0, condition: T1);
284}
285
286/// Emits the `CSINC` instruction.
287/// Assembly forms: `CSINC WD, WN, WM, #COND`; `CSINC XD, XN, XM, #COND`.
288/// Operands: `rd`, `rn`, `rm`, `condition`.
289pub trait CsincEmitter<T0, T1, T2, T3> {
290    fn csinc(&mut self, rd: T0, rn: T1, rm: T2, condition: T3);
291}
292
293/// Emits the `CSINV` instruction.
294/// Assembly forms: `CSINV WD, WN, WM, #COND`; `CSINV XD, XN, XM, #COND`.
295/// Operands: `rd`, `rn`, `rm`, `condition`.
296pub trait CsinvEmitter<T0, T1, T2, T3> {
297    fn csinv(&mut self, rd: T0, rn: T1, rm: T2, condition: T3);
298}
299
300/// Emits the `CSNEG` instruction.
301/// Assembly forms: `CSNEG WD, WN, WM, #COND`; `CSNEG XD, XN, XM, #COND`.
302/// Operands: `rd`, `rn`, `rm`, `condition`.
303pub trait CsnegEmitter<T0, T1, T2, T3> {
304    fn csneg(&mut self, rd: T0, rn: T1, rm: T2, condition: T3);
305}
306
307/// Emits the `DC` instruction.
308/// Assembly forms: `DC #DC_OP, XT`.
309/// Operands: `dc_op`, `rt`.
310pub trait DcEmitter<T0, T1> {
311    fn dc(&mut self, dc_op: T0, rt: T1);
312}
313
314/// Emits the `DMB` instruction.
315/// Assembly forms: `DMB #BARRIER_OP`.
316/// Operands: `barrier_op`.
317pub trait DmbEmitter<T0> {
318    fn dmb(&mut self, barrier_op: T0);
319}
320
321/// Emits the `DSB` instruction.
322/// Assembly forms: `DSB #BARRIER_OP`.
323/// Operands: `barrier_op`.
324pub trait DsbEmitter<T0> {
325    fn dsb(&mut self, barrier_op: T0);
326}
327
328/// Emits the `DRPS` instruction.
329/// Assembly forms: `DRPS`.
330pub trait DrpsEmitter {
331    fn drps(&mut self);
332}
333
334/// Emits the `EON` instruction.
335/// Assembly forms: `EON WD, WN, WM, {SOP #N}`; `EON XD, XN, XM, {SOP #N}`.
336/// Operands: `rd`, `rn`, `rm`.
337pub trait EonEmitter<T0, T1, T2> {
338    fn eon(&mut self, rd: T0, rn: T1, rm: T2);
339}
340
341/// Emits the `EON_4` instruction.
342/// Assembly forms: `EON WD, WN, WM, {SOP #N}`; `EON XD, XN, XM, {SOP #N}`.
343/// Operands: `rd`, `rn`, `rm`, `shift`.
344pub trait Eon4Emitter<T0, T1, T2, T3> {
345    fn eon_4(&mut self, rd: T0, rn: T1, rm: T2, shift: T3);
346}
347
348/// Emits the `EOR` instruction.
349/// Assembly forms: `EOR WD, WN, WM, {SOP #N}`; `EOR XD, XN, XM, {SOP #N}`; `EOR WD|WSP, WN, #IMM`; `EOR XD|SP, XN, #IMM` (and related forms).
350/// Operands: `rd`, `rn`, `rm_or_imm`.
351pub trait EorEmitter<T0, T1, T2> {
352    fn eor(&mut self, rd: T0, rn: T1, rm_or_imm: T2);
353}
354
355/// Emits the `EOR_4` instruction.
356/// Assembly forms: `EOR WD, WN, WM, {SOP #N}`; `EOR XD, XN, XM, {SOP #N}`; `EOR WD|WSP, WN, #IMM`; `EOR XD|SP, XN, #IMM` (and related forms).
357/// Operands: `rd`, `rn`, `rm`, `shift`.
358pub trait Eor4Emitter<T0, T1, T2, T3> {
359    fn eor_4(&mut self, rd: T0, rn: T1, rm: T2, shift: T3);
360}
361
362/// Emits the `ERET` instruction.
363/// Assembly forms: `ERET`.
364pub trait EretEmitter {
365    fn eret(&mut self);
366}
367
368/// Emits the `ESB` instruction.
369/// Assembly forms: `ESB`.
370pub trait EsbEmitter {
371    fn esb(&mut self);
372}
373
374/// Emits the `EXTR` instruction.
375/// Assembly forms: `EXTR WD, WN, WM, #IMM`; `EXTR XD, XN, XM, #IMM`.
376/// Operands: `rd`, `rn`, `rm`, `imm`.
377pub trait ExtrEmitter<T0, T1, T2, T3> {
378    fn extr(&mut self, rd: T0, rn: T1, rm: T2, imm: T3);
379}
380
381/// Emits the `HLT` instruction.
382/// Assembly forms: `HLT #IMM`.
383/// Operands: `imm`.
384pub trait HltEmitter<T0> {
385    fn hlt(&mut self, imm: T0);
386}
387
388/// Emits the `HVC` instruction.
389/// Assembly forms: `HVC #IMM`.
390/// Operands: `imm`.
391pub trait HvcEmitter<T0> {
392    fn hvc(&mut self, imm: T0);
393}
394
395/// Emits the `IC` instruction.
396/// Assembly forms: `IC #IC_OP`; `IC #IC_OP, XT`.
397/// Operands: `ic_op`, `rt`.
398pub trait IcEmitter<T0, T1> {
399    fn ic(&mut self, ic_op: T0, rt: T1);
400}
401
402/// Emits the `ISB` instruction.
403/// Assembly forms: `ISB {#ISB_OP=15}`.
404/// Operands: `isb_op`.
405pub trait IsbEmitter<T0> {
406    fn isb(&mut self, isb_op: T0);
407}
408
409/// Emits the `LSL` instruction.
410/// Assembly forms: `LSL|LSLV WD, WN, WM`; `LSL|LSLV XD, XN, XM`; `LSL WD, WN, #N`; `LSL XD, XN, #N`.
411/// Operands: `rd`, `rn`, `rm_or_shift`.
412pub trait LslEmitter<T0, T1, T2> {
413    fn lsl(&mut self, rd: T0, rn: T1, rm_or_shift: T2);
414}
415
416/// Emits the `LSLV` instruction.
417/// Assembly forms: `LSL|LSLV WD, WN, WM`; `LSL|LSLV XD, XN, XM`.
418/// Operands: `rd`, `rn`, `rm`.
419pub trait LslvEmitter<T0, T1, T2> {
420    fn lslv(&mut self, rd: T0, rn: T1, rm: T2);
421}
422
423/// Emits the `LSR` instruction.
424/// Assembly forms: `LSR|LSRV WD, WN, WM`; `LSR|LSRV XD, XN, XM`; `LSR WD, WN, #N`; `LSR XD, XN, #N`.
425/// Operands: `rd`, `rn`, `rm_or_shift`.
426pub trait LsrEmitter<T0, T1, T2> {
427    fn lsr(&mut self, rd: T0, rn: T1, rm_or_shift: T2);
428}
429
430/// Emits the `LSRV` instruction.
431/// Assembly forms: `LSR|LSRV WD, WN, WM`; `LSR|LSRV XD, XN, XM`.
432/// Operands: `rd`, `rn`, `rm`.
433pub trait LsrvEmitter<T0, T1, T2> {
434    fn lsrv(&mut self, rd: T0, rn: T1, rm: T2);
435}
436
437/// Emits the `MADD` instruction.
438/// Assembly forms: `MADD WD, WN, WM, WA`; `MADD XD, XN, XM, XA`.
439/// Operands: `rd`, `rn`, `rm`, `operand_4`.
440pub trait MaddEmitter<T0, T1, T2, T3> {
441    fn madd(&mut self, rd: T0, rn: T1, rm: T2, operand_4: T3);
442}
443
444/// Emits the `MNEG` instruction.
445/// Assembly forms: `MNEG WD, WN, WM`; `MNEG XD, XN, XM`.
446/// Operands: `rd`, `rn`, `rm`.
447pub trait MnegEmitter<T0, T1, T2> {
448    fn mneg(&mut self, rd: T0, rn: T1, rm: T2);
449}
450
451/// Emits the `MOV` instruction.
452/// Assembly forms: `MOV WD, WM`; `MOV XD, XM`; `MOV WD|WSP, WN|WSP`; `MOV XD|SP, XN|SP` (and related forms).
453/// Operands: `rd`, `rm_or_rn_or_imm_or_log_imm`.
454pub trait MovEmitter<T0, T1> {
455    fn mov(&mut self, rd: T0, rm_or_rn_or_imm_or_log_imm: T1);
456}
457
458/// Emits the `MOVK` instruction.
459/// Assembly forms: `MOVK WD, #IMM, {LSL #N}`; `MOVK XD, #IMM, {LSL #N}`.
460/// Operands: `rd`, `imm`.
461pub trait MovkEmitter<T0, T1> {
462    fn movk(&mut self, rd: T0, imm: T1);
463}
464
465/// Emits the `MOVK_3` instruction.
466/// Assembly forms: `MOVK WD, #IMM, {LSL #N}`; `MOVK XD, #IMM, {LSL #N}`.
467/// Operands: `rd`, `imm`, `shift`.
468pub trait Movk3Emitter<T0, T1, T2> {
469    fn movk_3(&mut self, rd: T0, imm: T1, shift: T2);
470}
471
472/// Emits the `MOVN` instruction.
473/// Assembly forms: `MOVN WD, #IMM, {LSL #N}`; `MOVN XD, #IMM, {LSL #N}`.
474/// Operands: `rd`, `imm`.
475pub trait MovnEmitter<T0, T1> {
476    fn movn(&mut self, rd: T0, imm: T1);
477}
478
479/// Emits the `MOVN_3` instruction.
480/// Assembly forms: `MOVN WD, #IMM, {LSL #N}`; `MOVN XD, #IMM, {LSL #N}`.
481/// Operands: `rd`, `imm`, `shift`.
482pub trait Movn3Emitter<T0, T1, T2> {
483    fn movn_3(&mut self, rd: T0, imm: T1, shift: T2);
484}
485
486/// Emits the `MOVZ` instruction.
487/// Assembly forms: `MOVZ WD, #IMM, {LSL #N}`; `MOVZ XD, #IMM, {LSL #N}`.
488/// Operands: `rd`, `imm`.
489pub trait MovzEmitter<T0, T1> {
490    fn movz(&mut self, rd: T0, imm: T1);
491}
492
493/// Emits the `MOVZ_3` instruction.
494/// Assembly forms: `MOVZ WD, #IMM, {LSL #N}`; `MOVZ XD, #IMM, {LSL #N}`.
495/// Operands: `rd`, `imm`, `shift`.
496pub trait Movz3Emitter<T0, T1, T2> {
497    fn movz_3(&mut self, rd: T0, imm: T1, shift: T2);
498}
499
500/// Emits the `MRS` instruction.
501/// Assembly forms: `MRS XD, #SYSREG`.
502/// Operands: `rd`, `sysreg`.
503pub trait MrsEmitter<T0, T1> {
504    fn mrs(&mut self, rd: T0, sysreg: T1);
505}
506
507/// Emits the `MSR` instruction.
508/// Assembly forms: `MSR #SYSREG, XS`; `MSR #PSTATEFIELD, #IMM`.
509/// Operands: `sysreg_or_pstatefield`, `rs_or_imm`.
510pub trait MsrEmitter<T0, T1> {
511    fn msr(&mut self, sysreg_or_pstatefield: T0, rs_or_imm: T1);
512}
513
514/// Emits the `MSUB` instruction.
515/// Assembly forms: `MSUB WD, WN, WM, WA`; `MSUB XD, XN, XM, XA`.
516/// Operands: `rd`, `rn`, `rm`, `operand_4`.
517pub trait MsubEmitter<T0, T1, T2, T3> {
518    fn msub(&mut self, rd: T0, rn: T1, rm: T2, operand_4: T3);
519}
520
521/// Emits the `MUL` instruction.
522/// Assembly forms: `MUL WD, WN, WM`; `MUL XD, XN, XM`; `MUL VD.T, VN.T, VM.T`; `MUL VD.T, VN.T, VM.T` (and related forms).
523/// Operands: `rd`, `rn`, `rm`.
524pub trait MulEmitter<T0, T1, T2> {
525    fn mul(&mut self, rd: T0, rn: T1, rm: T2);
526}
527
528/// Emits the `MVN` instruction.
529/// Assembly forms: `MVN WD, WN, {SOP #N}`; `MVN XD, XN, {SOP #N}`; `NOT|MVN VD.8B, VN.8B`; `NOT|MVN VD.16B, VN.16B`.
530/// Operands: `rd`, `rn`.
531pub trait MvnEmitter<T0, T1> {
532    fn mvn(&mut self, rd: T0, rn: T1);
533}
534
535/// Emits the `MVN_3` instruction.
536/// Assembly forms: `MVN WD, WN, {SOP #N}`; `MVN XD, XN, {SOP #N}`; `NOT|MVN VD.8B, VN.8B`; `NOT|MVN VD.16B, VN.16B`.
537/// Operands: `rd`, `rn`, `shift`.
538pub trait Mvn3Emitter<T0, T1, T2> {
539    fn mvn_3(&mut self, rd: T0, rn: T1, shift: T2);
540}
541
542/// Emits the `MVN_` instruction.
543/// Assembly forms: `MVN WD, WN, {SOP #N}`; `MVN XD, XN, {SOP #N}`; `NOT|MVN VD.8B, VN.8B`; `NOT|MVN VD.16B, VN.16B`.
544/// Operands: `rd`, `rn`.
545pub trait Mvn_Emitter<T0, T1> {
546    fn mvn_(&mut self, rd: T0, rn: T1);
547}
548
549/// Emits the `MVN__3` instruction.
550/// Assembly forms: `MVN WD, WN, {SOP #N}`; `MVN XD, XN, {SOP #N}`; `NOT|MVN VD.8B, VN.8B`; `NOT|MVN VD.16B, VN.16B`.
551/// Operands: `rd`, `rn`, `shift`.
552pub trait Mvn_3Emitter<T0, T1, T2> {
553    fn mvn__3(&mut self, rd: T0, rn: T1, shift: T2);
554}
555
556/// Emits the `NEG` instruction.
557/// Assembly forms: `NEG WD, WM, {LSL|LSR|ASR #N}`; `NEG XD, XM, {LSL|LSR|ASR #N}`; `NEG DD, DN`; `NEG VD.T, VN.T` (and related forms).
558/// Operands: `rd`, `rm_or_rn`.
559pub trait NegEmitter<T0, T1> {
560    fn neg(&mut self, rd: T0, rm_or_rn: T1);
561}
562
563/// Emits the `NEG_3` instruction.
564/// Assembly forms: `NEG WD, WM, {LSL|LSR|ASR #N}`; `NEG XD, XM, {LSL|LSR|ASR #N}`; `NEG DD, DN`; `NEG VD.T, VN.T` (and related forms).
565/// Operands: `rd`, `rm`, `shift`.
566pub trait Neg3Emitter<T0, T1, T2> {
567    fn neg_3(&mut self, rd: T0, rm: T1, shift: T2);
568}
569
570/// Emits the `NEGS` instruction.
571/// Assembly forms: `NEGS WD, WM, {LSL|LSR|ASR #N}`; `NEGS XD, XM, {LSL|LSR|ASR #N}`.
572/// Operands: `rd`, `rm`.
573pub trait NegsEmitter<T0, T1> {
574    fn negs(&mut self, rd: T0, rm: T1);
575}
576
577/// Emits the `NEGS_3` instruction.
578/// Assembly forms: `NEGS WD, WM, {LSL|LSR|ASR #N}`; `NEGS XD, XM, {LSL|LSR|ASR #N}`.
579/// Operands: `rd`, `rm`, `shift`.
580pub trait Negs3Emitter<T0, T1, T2> {
581    fn negs_3(&mut self, rd: T0, rm: T1, shift: T2);
582}
583
584/// Emits the `NGC` instruction.
585/// Assembly forms: `NGC WD, WM`; `NGC XD, XM`.
586/// Operands: `rd`, `rm`.
587pub trait NgcEmitter<T0, T1> {
588    fn ngc(&mut self, rd: T0, rm: T1);
589}
590
591/// Emits the `NGCS` instruction.
592/// Assembly forms: `NGCS WD, WM`; `NGCS XD, XM`.
593/// Operands: `rd`, `rm`.
594pub trait NgcsEmitter<T0, T1> {
595    fn ngcs(&mut self, rd: T0, rm: T1);
596}
597
598/// Emits the `ORN` instruction.
599/// Assembly forms: `ORN WD, WN, WM, {SOP #N}`; `ORN XD, XN, XM, {SOP #N}`; `ORN VD.8B, VN.8B, VM.8B`; `ORN VD.16B, VN.16B, VM.16B`.
600/// Operands: `rd`, `rn`, `rm`.
601pub trait OrnEmitter<T0, T1, T2> {
602    fn orn(&mut self, rd: T0, rn: T1, rm: T2);
603}
604
605/// Emits the `ORN_4` instruction.
606/// Assembly forms: `ORN WD, WN, WM, {SOP #N}`; `ORN XD, XN, XM, {SOP #N}`; `ORN VD.8B, VN.8B, VM.8B`; `ORN VD.16B, VN.16B, VM.16B`.
607/// Operands: `rd`, `rn`, `rm`, `shift`.
608pub trait Orn4Emitter<T0, T1, T2, T3> {
609    fn orn_4(&mut self, rd: T0, rn: T1, rm: T2, shift: T3);
610}
611
612/// Emits the `ORR` instruction.
613/// Assembly forms: `ORR WD, WN, WM, {SOP #N}`; `ORR XD, XN, XM, {SOP #N}`; `ORR WD|WSP, WN, #LOG_IMM`; `ORR XD|SP, XN, #LOG_IMM` (and related forms).
614/// Operands: `rd`, `rn_or_imm`, `rm_or_log_imm_or_shift`.
615pub trait OrrEmitter<T0, T1, T2> {
616    fn orr(&mut self, rd: T0, rn_or_imm: T1, rm_or_log_imm_or_shift: T2);
617}
618
619/// Emits the `ORR_4` instruction.
620/// Assembly forms: `ORR WD, WN, WM, {SOP #N}`; `ORR XD, XN, XM, {SOP #N}`; `ORR WD|WSP, WN, #LOG_IMM`; `ORR XD|SP, XN, #LOG_IMM` (and related forms).
621/// Operands: `rd`, `rn`, `rm`, `shift`.
622pub trait Orr4Emitter<T0, T1, T2, T3> {
623    fn orr_4(&mut self, rd: T0, rn: T1, rm: T2, shift: T3);
624}
625
626/// Emits the `RBIT` instruction.
627/// Assembly forms: `RBIT WD, WN`; `RBIT XD, XN`; `RBIT VD.8B, VN.8B`; `RBIT VD.16B, VN.16B`.
628/// Operands: `rd`, `rn`.
629pub trait RbitEmitter<T0, T1> {
630    fn rbit(&mut self, rd: T0, rn: T1);
631}
632
633/// Emits the `RET` instruction.
634/// Assembly forms: `RET XN`.
635/// Operands: `rn`.
636pub trait RetEmitter<T0> {
637    fn ret(&mut self, rn: T0);
638}
639
640/// Emits the `REV` instruction.
641/// Assembly forms: `REV WD, WN`; `REV|REV64 XD, XN`.
642/// Operands: `rd`, `rn`.
643pub trait RevEmitter<T0, T1> {
644    fn rev(&mut self, rd: T0, rn: T1);
645}
646
647/// Emits the `REV16` instruction.
648/// Assembly forms: `REV16 WD, WN`; `REV16 XD, XN`; `REV16 VD.8B, VN.8B`; `REV16 VD.16B, VN.16B`.
649/// Operands: `rd`, `rn`.
650pub trait Rev16Emitter<T0, T1> {
651    fn rev16(&mut self, rd: T0, rn: T1);
652}
653
654/// Emits the `REV32` instruction.
655/// Assembly forms: `REV32 XD, XN`; `REV32 VD.T, VN.T`; `REV32 VD.T, VN.T`.
656/// Operands: `rd`, `rn`.
657pub trait Rev32Emitter<T0, T1> {
658    fn rev32(&mut self, rd: T0, rn: T1);
659}
660
661/// Emits the `REV64` instruction.
662/// Assembly forms: `REV|REV64 XD, XN`; `REV64 VD.T, VN.T`; `REV64 VD.T, VN.T`.
663/// Operands: `rd`, `rn`.
664pub trait Rev64Emitter<T0, T1> {
665    fn rev64(&mut self, rd: T0, rn: T1);
666}
667
668/// Emits the `ROR` instruction.
669/// Assembly forms: `ROR|RORV WD, WN, WM`; `ROR|RORV XD, XN, XM`; `ROR WD, WN, #N`; `ROR XD, XN, #N`.
670/// Operands: `rd`, `rn`, `rm_or_shift`.
671pub trait RorEmitter<T0, T1, T2> {
672    fn ror(&mut self, rd: T0, rn: T1, rm_or_shift: T2);
673}
674
675/// Emits the `RORV` instruction.
676/// Assembly forms: `ROR|RORV WD, WN, WM`; `ROR|RORV XD, XN, XM`.
677/// Operands: `rd`, `rn`, `rm`.
678pub trait RorvEmitter<T0, T1, T2> {
679    fn rorv(&mut self, rd: T0, rn: T1, rm: T2);
680}
681
682/// Emits the `SBC` instruction.
683/// Assembly forms: `SBC WD, WN, WM`; `SBC XD, XN, XM`.
684/// Operands: `rd`, `rn`, `rm`.
685pub trait SbcEmitter<T0, T1, T2> {
686    fn sbc(&mut self, rd: T0, rn: T1, rm: T2);
687}
688
689/// Emits the `SBCS` instruction.
690/// Assembly forms: `SBCS WD, WN, WM`; `SBCS XD, XN, XM`.
691/// Operands: `rd`, `rn`, `rm`.
692pub trait SbcsEmitter<T0, T1, T2> {
693    fn sbcs(&mut self, rd: T0, rn: T1, rm: T2);
694}
695
696/// Emits the `SBFIZ` instruction.
697/// Assembly forms: `SBFIZ WD, WN, #LSB, #WIDTH`; `SBFIZ XD, XN, #LSB, #WIDTH`.
698/// Operands: `rd`, `rn`, `lsb`, `width`.
699pub trait SbfizEmitter<T0, T1, T2, T3> {
700    fn sbfiz(&mut self, rd: T0, rn: T1, lsb: T2, width: T3);
701}
702
703/// Emits the `SBFM` instruction.
704/// Assembly forms: `SBFM WD, WN, #IMMR, #IMMS`; `SBFM XD, XN, #IMMR, #IMMS`.
705/// Operands: `rd`, `rn`, `imm`, `imm_2`.
706pub trait SbfmEmitter<T0, T1, T2, T3> {
707    fn sbfm(&mut self, rd: T0, rn: T1, imm: T2, imm_2: T3);
708}
709
710/// Emits the `SBFX` instruction.
711/// Assembly forms: `SBFX WD, WN, #LSB, #WIDTH`; `SBFX XD, XN, #LSB, #WIDTH`.
712/// Operands: `rd`, `rn`, `lsb`, `width`.
713pub trait SbfxEmitter<T0, T1, T2, T3> {
714    fn sbfx(&mut self, rd: T0, rn: T1, lsb: T2, width: T3);
715}
716
717/// Emits the `SDIV` instruction.
718/// Assembly forms: `SDIV WD, WN, WM`; `SDIV XD, XN, XM`.
719/// Operands: `rd`, `rn`, `rm`.
720pub trait SdivEmitter<T0, T1, T2> {
721    fn sdiv(&mut self, rd: T0, rn: T1, rm: T2);
722}
723
724/// Emits the `SMADDL` instruction.
725/// Assembly forms: `SMADDL XD, WN, WM, XA`.
726/// Operands: `rd`, `rn`, `rm`, `operand_4`.
727pub trait SmaddlEmitter<T0, T1, T2, T3> {
728    fn smaddl(&mut self, rd: T0, rn: T1, rm: T2, operand_4: T3);
729}
730
731/// Emits the `SMC` instruction.
732/// Assembly forms: `SMC #IMMZ`.
733/// Operands: `imm`.
734pub trait SmcEmitter<T0> {
735    fn smc(&mut self, imm: T0);
736}
737
738/// Emits the `SMNEGL` instruction.
739/// Assembly forms: `SMNEGL XD, WN, WM`.
740/// Operands: `rd`, `rn`, `rm`.
741pub trait SmneglEmitter<T0, T1, T2> {
742    fn smnegl(&mut self, rd: T0, rn: T1, rm: T2);
743}
744
745/// Emits the `SMSUBL` instruction.
746/// Assembly forms: `SMSUBL XD, WN, WM, XA`.
747/// Operands: `rd`, `rn`, `rm`, `operand_4`.
748pub trait SmsublEmitter<T0, T1, T2, T3> {
749    fn smsubl(&mut self, rd: T0, rn: T1, rm: T2, operand_4: T3);
750}
751
752/// Emits the `SMULH` instruction.
753/// Assembly forms: `SMULH XD, XN, XM`.
754/// Operands: `rd`, `rn`, `rm`.
755pub trait SmulhEmitter<T0, T1, T2> {
756    fn smulh(&mut self, rd: T0, rn: T1, rm: T2);
757}
758
759/// Emits the `SMULL` instruction.
760/// Assembly forms: `SMULL XD, WN, WM`; `SMULL VD.TA, VN.TB, VM.TB`; `SMULL VD.4S, VN.4H, VM.H[#IDX]`; `SMULL VD.2D, VN.2S, VM.S[#IDX]`.
761/// Operands: `rd`, `rn`, `rm`.
762pub trait SmullEmitter<T0, T1, T2> {
763    fn smull(&mut self, rd: T0, rn: T1, rm: T2);
764}
765
766/// Emits the `SUB` instruction.
767/// Assembly forms: `SUB WD, WN, WM, {LSL|LSR|ASR #N}`; `SUB XD, XN, XM, {LSL|LSR|ASR #N}`; `SUB WD|WSP, WN|WSP, WM, {EXTEND #N}`; `SUB XD|SP, XN|SP, RM, {EXTEND #N}` (and related forms).
768/// Operands: `rd`, `rn`, `rm_or_imm`.
769pub trait SubEmitter<T0, T1, T2> {
770    fn sub(&mut self, rd: T0, rn: T1, rm_or_imm: T2);
771}
772
773/// Emits the `SUB_4` instruction.
774/// Assembly forms: `SUB WD, WN, WM, {LSL|LSR|ASR #N}`; `SUB XD, XN, XM, {LSL|LSR|ASR #N}`; `SUB WD|WSP, WN|WSP, WM, {EXTEND #N}`; `SUB XD|SP, XN|SP, RM, {EXTEND #N}` (and related forms).
775/// Operands: `rd`, `rn`, `rm_or_imm`, `shift`.
776pub trait Sub4Emitter<T0, T1, T2, T3> {
777    fn sub_4(&mut self, rd: T0, rn: T1, rm_or_imm: T2, shift: T3);
778}
779
780/// Emits the `SUBS` instruction.
781/// Assembly forms: `SUBS WD, WN, WM, {LSL|LSR|ASR #N}`; `SUBS XD, XN, XM, {LSL|LSR|ASR #N}`; `SUBS WD, WN|WSP, WM, {EXTEND #N}`; `SUBS XD, XN|SP, RM, {EXTEND #N}` (and related forms).
782/// Operands: `rd`, `rn`, `rm_or_imm`.
783pub trait SubsEmitter<T0, T1, T2> {
784    fn subs(&mut self, rd: T0, rn: T1, rm_or_imm: T2);
785}
786
787/// Emits the `SUBS_4` instruction.
788/// Assembly forms: `SUBS WD, WN, WM, {LSL|LSR|ASR #N}`; `SUBS XD, XN, XM, {LSL|LSR|ASR #N}`; `SUBS WD, WN|WSP, WM, {EXTEND #N}`; `SUBS XD, XN|SP, RM, {EXTEND #N}` (and related forms).
789/// Operands: `rd`, `rn`, `rm_or_imm`, `shift`.
790pub trait Subs4Emitter<T0, T1, T2, T3> {
791    fn subs_4(&mut self, rd: T0, rn: T1, rm_or_imm: T2, shift: T3);
792}
793
794/// Emits the `SVC` instruction.
795/// Assembly forms: `SVC #IMMZ`.
796/// Operands: `imm`.
797pub trait SvcEmitter<T0> {
798    fn svc(&mut self, imm: T0);
799}
800
801/// Emits the `SXTB` instruction.
802/// Assembly forms: `SXTB WD, WN`; `SXTB XD, WN`.
803/// Operands: `rd`, `rn`.
804pub trait SxtbEmitter<T0, T1> {
805    fn sxtb(&mut self, rd: T0, rn: T1);
806}
807
808/// Emits the `SXTH` instruction.
809/// Assembly forms: `SXTH WD, WN`; `SXTH XD, WN`.
810/// Operands: `rd`, `rn`.
811pub trait SxthEmitter<T0, T1> {
812    fn sxth(&mut self, rd: T0, rn: T1);
813}
814
815/// Emits the `SXTW` instruction.
816/// Assembly forms: `SXTW XD, WN`.
817/// Operands: `rd`, `rn`.
818pub trait SxtwEmitter<T0, T1> {
819    fn sxtw(&mut self, rd: T0, rn: T1);
820}
821
822/// Emits the `SYS` instruction.
823/// Assembly forms: `SYS #OP1, #CN, #CM, #OP2`; `SYS #OP1, #CN, #CM, #OP2, XT`.
824/// Operands: `system_op1`, `cn`, `cm`, `system_op2`.
825pub trait SysEmitter<T0, T1, T2, T3> {
826    fn sys(&mut self, system_op1: T0, cn: T1, cm: T2, system_op2: T3);
827}
828
829/// Emits the `SYS_5` instruction.
830/// Assembly forms: `SYS #OP1, #CN, #CM, #OP2`; `SYS #OP1, #CN, #CM, #OP2, XT`.
831/// Operands: `system_op1`, `cn`, `cm`, `system_op2`, `rt`.
832pub trait Sys5Emitter<T0, T1, T2, T3, T4> {
833    fn sys_5(&mut self, system_op1: T0, cn: T1, cm: T2, system_op2: T3, rt: T4);
834}
835
836/// Emits the `TLBI` instruction.
837/// Assembly forms: `TLBI #TLBI_OP`; `TLBI #TLBI_OP, XT`.
838/// Operands: `tlbi_op`, `rt`.
839pub trait TlbiEmitter<T0, T1> {
840    fn tlbi(&mut self, tlbi_op: T0, rt: T1);
841}
842
843/// Emits the `TST` instruction.
844/// Assembly forms: `TST WN, WM, {SOP #N}`; `TST XN, XM, {SOP #N}`; `TST WN, #IMM`; `TST XN, #IMM`.
845/// Operands: `rn`, `rm_or_imm`.
846pub trait TstEmitter<T0, T1> {
847    fn tst(&mut self, rn: T0, rm_or_imm: T1);
848}
849
850/// Emits the `TST_3` instruction.
851/// Assembly forms: `TST WN, WM, {SOP #N}`; `TST XN, XM, {SOP #N}`; `TST WN, #IMM`; `TST XN, #IMM`.
852/// Operands: `rn`, `rm`, `shift`.
853pub trait Tst3Emitter<T0, T1, T2> {
854    fn tst_3(&mut self, rn: T0, rm: T1, shift: T2);
855}
856
857/// Emits the `UDIV` instruction.
858/// Assembly forms: `UDIV WD, WN, WM`; `UDIV XD, XN, XM`.
859/// Operands: `rd`, `rn`, `rm`.
860pub trait UdivEmitter<T0, T1, T2> {
861    fn udiv(&mut self, rd: T0, rn: T1, rm: T2);
862}
863
864/// Emits the `UBFIZ` instruction.
865/// Assembly forms: `UBFIZ WD, WN, #LSB, #WIDTH`; `UBFIZ XD, XN, #LSB, #WIDTH`.
866/// Operands: `rd`, `rn`, `lsb`, `width`.
867pub trait UbfizEmitter<T0, T1, T2, T3> {
868    fn ubfiz(&mut self, rd: T0, rn: T1, lsb: T2, width: T3);
869}
870
871/// Emits the `UBFM` instruction.
872/// Assembly forms: `UBFM WD, WN, #IMMR, #IMMS`; `UBFM XD, XN, #IMMR, #IMMS`.
873/// Operands: `rd`, `rn`, `imm`, `imm_2`.
874pub trait UbfmEmitter<T0, T1, T2, T3> {
875    fn ubfm(&mut self, rd: T0, rn: T1, imm: T2, imm_2: T3);
876}
877
878/// Emits the `UBFX` instruction.
879/// Assembly forms: `UBFX WD, WN, #LSB, #WIDTH`; `UBFX XD, XN, #LSB, #WIDTH`.
880/// Operands: `rd`, `rn`, `lsb`, `width`.
881pub trait UbfxEmitter<T0, T1, T2, T3> {
882    fn ubfx(&mut self, rd: T0, rn: T1, lsb: T2, width: T3);
883}
884
885/// Emits the `UMADDL` instruction.
886/// Assembly forms: `UMADDL XD, WN, WM, XA`.
887/// Operands: `rd`, `rn`, `rm`, `operand_4`.
888pub trait UmaddlEmitter<T0, T1, T2, T3> {
889    fn umaddl(&mut self, rd: T0, rn: T1, rm: T2, operand_4: T3);
890}
891
892/// Emits the `UMNEGL` instruction.
893/// Assembly forms: `UMNEGL XD, WN, WM`.
894/// Operands: `rd`, `rn`, `rm`.
895pub trait UmneglEmitter<T0, T1, T2> {
896    fn umnegl(&mut self, rd: T0, rn: T1, rm: T2);
897}
898
899/// Emits the `UMSUBL` instruction.
900/// Assembly forms: `UMSUBL XD, WN, WM, XA`.
901/// Operands: `rd`, `rn`, `rm`, `operand_4`.
902pub trait UmsublEmitter<T0, T1, T2, T3> {
903    fn umsubl(&mut self, rd: T0, rn: T1, rm: T2, operand_4: T3);
904}
905
906/// Emits the `UMULL` instruction.
907/// Assembly forms: `UMULL XD, WN, WM`; `UMULL VD.TA, VN.TB, VM.TB`; `UMULL VD.4S, VN.4H, VM.H[#IDX]`; `UMULL VD.2D, VN.2S, VM.S[#IDX]`.
908/// Operands: `rd`, `rn`, `rm`.
909pub trait UmullEmitter<T0, T1, T2> {
910    fn umull(&mut self, rd: T0, rn: T1, rm: T2);
911}
912
913/// Emits the `UMULH` instruction.
914/// Assembly forms: `UMULH XD, XN, XM`.
915/// Operands: `rd`, `rn`, `rm`.
916pub trait UmulhEmitter<T0, T1, T2> {
917    fn umulh(&mut self, rd: T0, rn: T1, rm: T2);
918}
919
920/// Emits the `UXTB` instruction.
921/// Assembly forms: `UXTB WD, WN`.
922/// Operands: `rd`, `rn`.
923pub trait UxtbEmitter<T0, T1> {
924    fn uxtb(&mut self, rd: T0, rn: T1);
925}
926
927/// Emits the `UXTH` instruction.
928/// Assembly forms: `UXTH WD, WN`.
929/// Operands: `rd`, `rn`.
930pub trait UxthEmitter<T0, T1> {
931    fn uxth(&mut self, rd: T0, rn: T1);
932}
933
934/// Emits the `CSDB` instruction.
935/// Assembly forms: `CSDB`.
936pub trait CsdbEmitter {
937    fn csdb(&mut self);
938}
939
940/// Emits the `DCPS1` instruction.
941/// Assembly forms: `DCPS1 {#IMM}`.
942/// Operands: `imm`.
943pub trait Dcps1Emitter<T0> {
944    fn dcps1(&mut self, imm: T0);
945}
946
947/// Emits the `DCPS2` instruction.
948/// Assembly forms: `DCPS2 {#IMM}`.
949/// Operands: `imm`.
950pub trait Dcps2Emitter<T0> {
951    fn dcps2(&mut self, imm: T0);
952}
953
954/// Emits the `DCPS3` instruction.
955/// Assembly forms: `DCPS3 {#IMM}`.
956/// Operands: `imm`.
957pub trait Dcps3Emitter<T0> {
958    fn dcps3(&mut self, imm: T0);
959}
960
961/// Emits the `PSSBB` instruction.
962/// Assembly forms: `PSSBB`.
963pub trait PssbbEmitter {
964    fn pssbb(&mut self);
965}
966
967/// Emits the `SSBB` instruction.
968/// Assembly forms: `SSBB`.
969pub trait SsbbEmitter {
970    fn ssbb(&mut self);
971}
972
973/// Emits the `UDF` instruction.
974/// Assembly forms: `UDF #IMM`.
975/// Operands: `imm`.
976pub trait UdfEmitter<T0> {
977    fn udf(&mut self, imm: T0);
978}
979
980/// Emits the `B` instruction.
981/// Assembly forms: `B #RELS*4`; `B.<COND> #RELS*4`.
982/// Operands: `target`.
983pub trait BEmitter<T0> {
984    fn b(&mut self, target: T0);
985    fn b_eq(&mut self, target: T0);
986    fn b_ne(&mut self, target: T0);
987    fn b_cs(&mut self, target: T0);
988    fn b_hs(&mut self, target: T0);
989    fn b_cc(&mut self, target: T0);
990    fn b_lo(&mut self, target: T0);
991    fn b_mi(&mut self, target: T0);
992    fn b_pl(&mut self, target: T0);
993    fn b_vs(&mut self, target: T0);
994    fn b_vc(&mut self, target: T0);
995    fn b_hi(&mut self, target: T0);
996    fn b_ls(&mut self, target: T0);
997    fn b_ge(&mut self, target: T0);
998    fn b_lt(&mut self, target: T0);
999    fn b_gt(&mut self, target: T0);
1000    fn b_le(&mut self, target: T0);
1001    fn b_al(&mut self, target: T0);
1002}
1003
1004/// Emits the `BL` instruction.
1005/// Assembly forms: `BL #RELS*4`.
1006/// Operands: `target`.
1007pub trait BlEmitter<T0> {
1008    fn bl(&mut self, target: T0);
1009}
1010
1011/// Emits the `BLR` instruction.
1012/// Assembly forms: `BLR XN`.
1013/// Operands: `rn`.
1014pub trait BlrEmitter<T0> {
1015    fn blr(&mut self, rn: T0);
1016}
1017
1018/// Emits the `BR` instruction.
1019/// Assembly forms: `BR XN`.
1020/// Operands: `rn`.
1021pub trait BrEmitter<T0> {
1022    fn br(&mut self, rn: T0);
1023}
1024
1025/// Emits the `CBZ` instruction.
1026/// Assembly forms: `CBZ WN, #RELS*4`; `CBZ XN, #RELS*4`.
1027/// Operands: `rn`, `target`.
1028pub trait CbzEmitter<T0, T1> {
1029    fn cbz(&mut self, rn: T0, target: T1);
1030}
1031
1032/// Emits the `CBNZ` instruction.
1033/// Assembly forms: `CBNZ WN, #RELS*4`; `CBNZ XN, #RELS*4`.
1034/// Operands: `rn`, `target`.
1035pub trait CbnzEmitter<T0, T1> {
1036    fn cbnz(&mut self, rn: T0, target: T1);
1037}
1038
1039/// Emits the `TBNZ` instruction.
1040/// Assembly forms: `TBNZ WT, #IMM, #RELS*4`; `TBNZ XT, #IMM, #RELS*4`.
1041/// Operands: `rt`, `imm`, `target`.
1042pub trait TbnzEmitter<T0, T1, T2> {
1043    fn tbnz(&mut self, rt: T0, imm: T1, target: T2);
1044}
1045
1046/// Emits the `TBZ` instruction.
1047/// Assembly forms: `TBZ WT, #IMM, #RELS*4`; `TBZ XT, #IMM, #RELS*4`.
1048/// Operands: `rt`, `imm`, `target`.
1049pub trait TbzEmitter<T0, T1, T2> {
1050    fn tbz(&mut self, rt: T0, imm: T1, target: T2);
1051}
1052
1053/// Emits the `CAS` instruction.
1054/// Assembly forms: `CAS WS, WD, [XN|SP]`; `CAS XS, XD, [XN|SP]`.
1055/// Operands: `rs`, `rd`, `addr`.
1056pub trait CasEmitter<T0, T1, T2> {
1057    fn cas(&mut self, rs: T0, rd: T1, addr: T2);
1058}
1059
1060/// Emits the `CASA` instruction.
1061/// Assembly forms: `CASA WS, WD, [XN|SP]`; `CASA XS, XD, [XN|SP]`.
1062/// Operands: `rs`, `rd`, `addr`.
1063pub trait CasaEmitter<T0, T1, T2> {
1064    fn casa(&mut self, rs: T0, rd: T1, addr: T2);
1065}
1066
1067/// Emits the `CASAB` instruction.
1068/// Assembly forms: `CASAB WS, WD, [XN|SP]`.
1069/// Operands: `rs`, `rd`, `addr`.
1070pub trait CasabEmitter<T0, T1, T2> {
1071    fn casab(&mut self, rs: T0, rd: T1, addr: T2);
1072}
1073
1074/// Emits the `CASAH` instruction.
1075/// Assembly forms: `CASAH WS, WD, [XN|SP]`.
1076/// Operands: `rs`, `rd`, `addr`.
1077pub trait CasahEmitter<T0, T1, T2> {
1078    fn casah(&mut self, rs: T0, rd: T1, addr: T2);
1079}
1080
1081/// Emits the `CASAL` instruction.
1082/// Assembly forms: `CASAL WS, WD, [XN|SP]`; `CASAL XS, XD, [XN|SP]`.
1083/// Operands: `rs`, `rd`, `addr`.
1084pub trait CasalEmitter<T0, T1, T2> {
1085    fn casal(&mut self, rs: T0, rd: T1, addr: T2);
1086}
1087
1088/// Emits the `CASALB` instruction.
1089/// Assembly forms: `CASALB WS, WD, [XN|SP]`.
1090/// Operands: `rs`, `rd`, `addr`.
1091pub trait CasalbEmitter<T0, T1, T2> {
1092    fn casalb(&mut self, rs: T0, rd: T1, addr: T2);
1093}
1094
1095/// Emits the `CASALH` instruction.
1096/// Assembly forms: `CASALH WS, WD, [XN|SP]`.
1097/// Operands: `rs`, `rd`, `addr`.
1098pub trait CasalhEmitter<T0, T1, T2> {
1099    fn casalh(&mut self, rs: T0, rd: T1, addr: T2);
1100}
1101
1102/// Emits the `CASB` instruction.
1103/// Assembly forms: `CASB WS, WD, [XN|SP]`.
1104/// Operands: `rs`, `rd`, `addr`.
1105pub trait CasbEmitter<T0, T1, T2> {
1106    fn casb(&mut self, rs: T0, rd: T1, addr: T2);
1107}
1108
1109/// Emits the `CASH` instruction.
1110/// Assembly forms: `CASH WS, WD, [XN|SP]`.
1111/// Operands: `rs`, `rd`, `addr`.
1112pub trait CashEmitter<T0, T1, T2> {
1113    fn cash(&mut self, rs: T0, rd: T1, addr: T2);
1114}
1115
1116/// Emits the `CASL` instruction.
1117/// Assembly forms: `CASL WS, WD, [XN|SP]`; `CASL XS, XD, [XN|SP]`.
1118/// Operands: `rs`, `rd`, `addr`.
1119pub trait CaslEmitter<T0, T1, T2> {
1120    fn casl(&mut self, rs: T0, rd: T1, addr: T2);
1121}
1122
1123/// Emits the `CASLB` instruction.
1124/// Assembly forms: `CASLB WS, WD, [XN|SP]`.
1125/// Operands: `rs`, `rd`, `addr`.
1126pub trait CaslbEmitter<T0, T1, T2> {
1127    fn caslb(&mut self, rs: T0, rd: T1, addr: T2);
1128}
1129
1130/// Emits the `CASLH` instruction.
1131/// Assembly forms: `CASLH WS, WD, [XN|SP]`.
1132/// Operands: `rs`, `rd`, `addr`.
1133pub trait CaslhEmitter<T0, T1, T2> {
1134    fn caslh(&mut self, rs: T0, rd: T1, addr: T2);
1135}
1136
1137/// Emits the `CASP` instruction.
1138/// Assembly forms: `CASP 2X{WS}+, 2X{WD}+, [XN|SP]`; `CASP 2X{XS}+, 2X{XD}+, [XN|SP]`.
1139/// Operands: `rd`, `rn`, `rm1`, `rm2`, `addr`.
1140pub trait CaspEmitter<T0, T1, T2, T3, T4> {
1141    fn casp(&mut self, rd: T0, rn: T1, rm1: T2, rm2: T3, addr: T4);
1142}
1143
1144/// Emits the `CASPA` instruction.
1145/// Assembly forms: `CASPA 2X{WS}+, 2X{WD}+, [XN|SP]`; `CASPA 2X{XS}+, 2X{XD}+, [XN|SP]`.
1146/// Operands: `rd`, `rn`, `rm1`, `rm2`, `addr`.
1147pub trait CaspaEmitter<T0, T1, T2, T3, T4> {
1148    fn caspa(&mut self, rd: T0, rn: T1, rm1: T2, rm2: T3, addr: T4);
1149}
1150
1151/// Emits the `CASPAL` instruction.
1152/// Assembly forms: `CASPAL 2X{WS}+, 2X{WD}+, [XN|SP]`; `CASPAL 2X{XS}+, 2X{XD}+, [XN|SP]`.
1153/// Operands: `rd`, `rn`, `rm1`, `rm2`, `addr`.
1154pub trait CaspalEmitter<T0, T1, T2, T3, T4> {
1155    fn caspal(&mut self, rd: T0, rn: T1, rm1: T2, rm2: T3, addr: T4);
1156}
1157
1158/// Emits the `CASPL` instruction.
1159/// Assembly forms: `CASPL 2X{WS}+, 2X{WD}+, [XN|SP]`; `CASPL 2X{XS}+, 2X{XD}+, [XN|SP]`.
1160/// Operands: `rd`, `rn`, `rm1`, `rm2`, `addr`.
1161pub trait CasplEmitter<T0, T1, T2, T3, T4> {
1162    fn caspl(&mut self, rd: T0, rn: T1, rm1: T2, rm2: T3, addr: T4);
1163}
1164
1165/// Emits the `LDADD` instruction.
1166/// Assembly forms: `LDADD WS, WD, [XN|SP]`; `LDADD XS, XD, [XN|SP]`.
1167/// Operands: `rs`, `rd`, `addr`.
1168pub trait LdaddEmitter<T0, T1, T2> {
1169    fn ldadd(&mut self, rs: T0, rd: T1, addr: T2);
1170}
1171
1172/// Emits the `LDADDA` instruction.
1173/// Assembly forms: `LDADDA WS, WD, [XN|SP]`; `LDADDA XS, XD, [XN|SP]`.
1174/// Operands: `rs`, `rd`, `addr`.
1175pub trait LdaddaEmitter<T0, T1, T2> {
1176    fn ldadda(&mut self, rs: T0, rd: T1, addr: T2);
1177}
1178
1179/// Emits the `LDADDAB` instruction.
1180/// Assembly forms: `LDADDAB WS, WD, [XN|SP]`.
1181/// Operands: `rs`, `rd`, `addr`.
1182pub trait LdaddabEmitter<T0, T1, T2> {
1183    fn ldaddab(&mut self, rs: T0, rd: T1, addr: T2);
1184}
1185
1186/// Emits the `LDADDAH` instruction.
1187/// Assembly forms: `LDADDAH WS, WD, [XN|SP]`.
1188/// Operands: `rs`, `rd`, `addr`.
1189pub trait LdaddahEmitter<T0, T1, T2> {
1190    fn ldaddah(&mut self, rs: T0, rd: T1, addr: T2);
1191}
1192
1193/// Emits the `LDADDAL` instruction.
1194/// Assembly forms: `LDADDAL WS, WD, [XN|SP]`; `LDADDAL XS, XD, [XN|SP]`.
1195/// Operands: `rs`, `rd`, `addr`.
1196pub trait LdaddalEmitter<T0, T1, T2> {
1197    fn ldaddal(&mut self, rs: T0, rd: T1, addr: T2);
1198}
1199
1200/// Emits the `LDADDALB` instruction.
1201/// Assembly forms: `LDADDALB WS, WD, [XN|SP]`.
1202/// Operands: `rs`, `rd`, `addr`.
1203pub trait LdaddalbEmitter<T0, T1, T2> {
1204    fn ldaddalb(&mut self, rs: T0, rd: T1, addr: T2);
1205}
1206
1207/// Emits the `LDADDALH` instruction.
1208/// Assembly forms: `LDADDALH WS, WD, [XN|SP]`.
1209/// Operands: `rs`, `rd`, `addr`.
1210pub trait LdaddalhEmitter<T0, T1, T2> {
1211    fn ldaddalh(&mut self, rs: T0, rd: T1, addr: T2);
1212}
1213
1214/// Emits the `LDADDB` instruction.
1215/// Assembly forms: `LDADDB WS, WD, [XN|SP]`.
1216/// Operands: `rs`, `rd`, `addr`.
1217pub trait LdaddbEmitter<T0, T1, T2> {
1218    fn ldaddb(&mut self, rs: T0, rd: T1, addr: T2);
1219}
1220
1221/// Emits the `LDADDH` instruction.
1222/// Assembly forms: `LDADDH WS, WD, [XN|SP]`.
1223/// Operands: `rs`, `rd`, `addr`.
1224pub trait LdaddhEmitter<T0, T1, T2> {
1225    fn ldaddh(&mut self, rs: T0, rd: T1, addr: T2);
1226}
1227
1228/// Emits the `LDADDL` instruction.
1229/// Assembly forms: `LDADDL WS, WD, [XN|SP]`; `LDADDL XS, XD, [XN|SP]`.
1230/// Operands: `rs`, `rd`, `addr`.
1231pub trait LdaddlEmitter<T0, T1, T2> {
1232    fn ldaddl(&mut self, rs: T0, rd: T1, addr: T2);
1233}
1234
1235/// Emits the `LDADDLB` instruction.
1236/// Assembly forms: `LDADDLB WS, WD, [XN|SP]`.
1237/// Operands: `rs`, `rd`, `addr`.
1238pub trait LdaddlbEmitter<T0, T1, T2> {
1239    fn ldaddlb(&mut self, rs: T0, rd: T1, addr: T2);
1240}
1241
1242/// Emits the `LDADDLH` instruction.
1243/// Assembly forms: `LDADDLH WS, WD, [XN|SP]`.
1244/// Operands: `rs`, `rd`, `addr`.
1245pub trait LdaddlhEmitter<T0, T1, T2> {
1246    fn ldaddlh(&mut self, rs: T0, rd: T1, addr: T2);
1247}
1248
1249/// Emits the `LDAR` instruction.
1250/// Assembly forms: `LDAR WD, [XN|SP]`; `LDAR XD, [XN|SP]`.
1251/// Operands: `rd`, `addr`.
1252pub trait LdarEmitter<T0, T1> {
1253    fn ldar(&mut self, rd: T0, addr: T1);
1254}
1255
1256/// Emits the `LDARB` instruction.
1257/// Assembly forms: `LDARB WD, [XN|SP]`.
1258/// Operands: `rd`, `addr`.
1259pub trait LdarbEmitter<T0, T1> {
1260    fn ldarb(&mut self, rd: T0, addr: T1);
1261}
1262
1263/// Emits the `LDARH` instruction.
1264/// Assembly forms: `LDARH WD, [XN|SP]`.
1265/// Operands: `rd`, `addr`.
1266pub trait LdarhEmitter<T0, T1> {
1267    fn ldarh(&mut self, rd: T0, addr: T1);
1268}
1269
1270/// Emits the `LDAXR` instruction.
1271/// Assembly forms: `LDAXR WD, [XN|SP]`; `LDAXR XD, [XN|SP]`.
1272/// Operands: `rd`, `addr`.
1273pub trait LdaxrEmitter<T0, T1> {
1274    fn ldaxr(&mut self, rd: T0, addr: T1);
1275}
1276
1277/// Emits the `LDAXRB` instruction.
1278/// Assembly forms: `LDAXRB WD, [XN|SP]`.
1279/// Operands: `rd`, `addr`.
1280pub trait LdaxrbEmitter<T0, T1> {
1281    fn ldaxrb(&mut self, rd: T0, addr: T1);
1282}
1283
1284/// Emits the `LDAXRH` instruction.
1285/// Assembly forms: `LDAXRH XD, [XN|SP]`.
1286/// Operands: `rd`, `addr`.
1287pub trait LdaxrhEmitter<T0, T1> {
1288    fn ldaxrh(&mut self, rd: T0, addr: T1);
1289}
1290
1291/// Emits the `LDCLR` instruction.
1292/// Assembly forms: `LDCLR WS, WD, [XN|SP]`; `LDCLR XS, XD, [XN|SP]`.
1293/// Operands: `rs`, `rd`, `addr`.
1294pub trait LdclrEmitter<T0, T1, T2> {
1295    fn ldclr(&mut self, rs: T0, rd: T1, addr: T2);
1296}
1297
1298/// Emits the `LDCLRA` instruction.
1299/// Assembly forms: `LDCLRA WS, WD, [XN|SP]`; `LDCLRA XS, XD, [XN|SP]`.
1300/// Operands: `rs`, `rd`, `addr`.
1301pub trait LdclraEmitter<T0, T1, T2> {
1302    fn ldclra(&mut self, rs: T0, rd: T1, addr: T2);
1303}
1304
1305/// Emits the `LDCLRAB` instruction.
1306/// Assembly forms: `LDCLRAB WS, WD, [XN|SP]`.
1307/// Operands: `rs`, `rd`, `addr`.
1308pub trait LdclrabEmitter<T0, T1, T2> {
1309    fn ldclrab(&mut self, rs: T0, rd: T1, addr: T2);
1310}
1311
1312/// Emits the `LDCLRAH` instruction.
1313/// Assembly forms: `LDCLRAH WS, WD, [XN|SP]`.
1314/// Operands: `rs`, `rd`, `addr`.
1315pub trait LdclrahEmitter<T0, T1, T2> {
1316    fn ldclrah(&mut self, rs: T0, rd: T1, addr: T2);
1317}
1318
1319/// Emits the `LDCLRAL` instruction.
1320/// Assembly forms: `LDCLRAL WS, WD, [XN|SP]`; `LDCLRAL XS, XD, [XN|SP]`.
1321/// Operands: `rs`, `rd`, `addr`.
1322pub trait LdclralEmitter<T0, T1, T2> {
1323    fn ldclral(&mut self, rs: T0, rd: T1, addr: T2);
1324}
1325
1326/// Emits the `LDCLRALB` instruction.
1327/// Assembly forms: `LDCLRALB WS, WD, [XN|SP]`.
1328/// Operands: `rs`, `rd`, `addr`.
1329pub trait LdclralbEmitter<T0, T1, T2> {
1330    fn ldclralb(&mut self, rs: T0, rd: T1, addr: T2);
1331}
1332
1333/// Emits the `LDCLRALH` instruction.
1334/// Assembly forms: `LDCLRALH WS, WD, [XN|SP]`.
1335/// Operands: `rs`, `rd`, `addr`.
1336pub trait LdclralhEmitter<T0, T1, T2> {
1337    fn ldclralh(&mut self, rs: T0, rd: T1, addr: T2);
1338}
1339
1340/// Emits the `LDCLRB` instruction.
1341/// Assembly forms: `LDCLRB WS, WD, [XN|SP]`.
1342/// Operands: `rs`, `rd`, `addr`.
1343pub trait LdclrbEmitter<T0, T1, T2> {
1344    fn ldclrb(&mut self, rs: T0, rd: T1, addr: T2);
1345}
1346
1347/// Emits the `LDCLRH` instruction.
1348/// Assembly forms: `LDCLRH WS, WD, [XN|SP]`.
1349/// Operands: `rs`, `rd`, `addr`.
1350pub trait LdclrhEmitter<T0, T1, T2> {
1351    fn ldclrh(&mut self, rs: T0, rd: T1, addr: T2);
1352}
1353
1354/// Emits the `LDCLRL` instruction.
1355/// Assembly forms: `LDCLRL WS, WD, [XN|SP]`; `LDCLRL XS, XD, [XN|SP]`.
1356/// Operands: `rs`, `rd`, `addr`.
1357pub trait LdclrlEmitter<T0, T1, T2> {
1358    fn ldclrl(&mut self, rs: T0, rd: T1, addr: T2);
1359}
1360
1361/// Emits the `LDCLRLB` instruction.
1362/// Assembly forms: `LDCLRLB WS, WD, [XN|SP]`.
1363/// Operands: `rs`, `rd`, `addr`.
1364pub trait LdclrlbEmitter<T0, T1, T2> {
1365    fn ldclrlb(&mut self, rs: T0, rd: T1, addr: T2);
1366}
1367
1368/// Emits the `LDCLRLH` instruction.
1369/// Assembly forms: `LDCLRLH WS, WD, [XN|SP]`.
1370/// Operands: `rs`, `rd`, `addr`.
1371pub trait LdclrlhEmitter<T0, T1, T2> {
1372    fn ldclrlh(&mut self, rs: T0, rd: T1, addr: T2);
1373}
1374
1375/// Emits the `LDEOR` instruction.
1376/// Assembly forms: `LDEOR WS, WD, [XN|SP]`; `LDEOR XS, XD, [XN|SP]`.
1377/// Operands: `rs`, `rd`, `addr`.
1378pub trait LdeorEmitter<T0, T1, T2> {
1379    fn ldeor(&mut self, rs: T0, rd: T1, addr: T2);
1380}
1381
1382/// Emits the `LDEORA` instruction.
1383/// Assembly forms: `LDEORA WS, WD, [XN|SP]`; `LDEORA XS, XD, [XN|SP]`.
1384/// Operands: `rs`, `rd`, `addr`.
1385pub trait LdeoraEmitter<T0, T1, T2> {
1386    fn ldeora(&mut self, rs: T0, rd: T1, addr: T2);
1387}
1388
1389/// Emits the `LDEORAB` instruction.
1390/// Assembly forms: `LDEORAB WS, WD, [XN|SP]`.
1391/// Operands: `rs`, `rd`, `addr`.
1392pub trait LdeorabEmitter<T0, T1, T2> {
1393    fn ldeorab(&mut self, rs: T0, rd: T1, addr: T2);
1394}
1395
1396/// Emits the `LDEORAH` instruction.
1397/// Assembly forms: `LDEORAH WS, WD, [XN|SP]`.
1398/// Operands: `rs`, `rd`, `addr`.
1399pub trait LdeorahEmitter<T0, T1, T2> {
1400    fn ldeorah(&mut self, rs: T0, rd: T1, addr: T2);
1401}
1402
1403/// Emits the `LDEORAL` instruction.
1404/// Assembly forms: `LDEORAL WS, WD, [XN|SP]`; `LDEORAL XS, XD, [XN|SP]`.
1405/// Operands: `rs`, `rd`, `addr`.
1406pub trait LdeoralEmitter<T0, T1, T2> {
1407    fn ldeoral(&mut self, rs: T0, rd: T1, addr: T2);
1408}
1409
1410/// Emits the `LDEORALB` instruction.
1411/// Assembly forms: `LDEORALB WS, WD, [XN|SP]`.
1412/// Operands: `rs`, `rd`, `addr`.
1413pub trait LdeoralbEmitter<T0, T1, T2> {
1414    fn ldeoralb(&mut self, rs: T0, rd: T1, addr: T2);
1415}
1416
1417/// Emits the `LDEORALH` instruction.
1418/// Assembly forms: `LDEORALH WS, WD, [XN|SP]`.
1419/// Operands: `rs`, `rd`, `addr`.
1420pub trait LdeoralhEmitter<T0, T1, T2> {
1421    fn ldeoralh(&mut self, rs: T0, rd: T1, addr: T2);
1422}
1423
1424/// Emits the `LDEORB` instruction.
1425/// Assembly forms: `LDEORB WS, WD, [XN|SP]`.
1426/// Operands: `rs`, `rd`, `addr`.
1427pub trait LdeorbEmitter<T0, T1, T2> {
1428    fn ldeorb(&mut self, rs: T0, rd: T1, addr: T2);
1429}
1430
1431/// Emits the `LDEORH` instruction.
1432/// Assembly forms: `LDEORH WS, WD, [XN|SP]`.
1433/// Operands: `rs`, `rd`, `addr`.
1434pub trait LdeorhEmitter<T0, T1, T2> {
1435    fn ldeorh(&mut self, rs: T0, rd: T1, addr: T2);
1436}
1437
1438/// Emits the `LDEORL` instruction.
1439/// Assembly forms: `LDEORL WS, WD, [XN|SP]`; `LDEORL XS, XD, [XN|SP]`.
1440/// Operands: `rs`, `rd`, `addr`.
1441pub trait LdeorlEmitter<T0, T1, T2> {
1442    fn ldeorl(&mut self, rs: T0, rd: T1, addr: T2);
1443}
1444
1445/// Emits the `LDEORLB` instruction.
1446/// Assembly forms: `LDEORLB WS, WD, [XN|SP]`.
1447/// Operands: `rs`, `rd`, `addr`.
1448pub trait LdeorlbEmitter<T0, T1, T2> {
1449    fn ldeorlb(&mut self, rs: T0, rd: T1, addr: T2);
1450}
1451
1452/// Emits the `LDEORLH` instruction.
1453/// Assembly forms: `LDEORLH WS, WD, [XN|SP]`.
1454/// Operands: `rs`, `rd`, `addr`.
1455pub trait LdeorlhEmitter<T0, T1, T2> {
1456    fn ldeorlh(&mut self, rs: T0, rd: T1, addr: T2);
1457}
1458
1459/// Emits the `LDLAR` instruction.
1460/// Assembly forms: `LDLAR WD, [XN|SP]`; `LDLAR XD, [XN|SP]`.
1461/// Operands: `rd`, `addr`.
1462pub trait LdlarEmitter<T0, T1> {
1463    fn ldlar(&mut self, rd: T0, addr: T1);
1464}
1465
1466/// Emits the `LDLARB` instruction.
1467/// Assembly forms: `LDLARB WD, [XN|SP]`.
1468/// Operands: `rd`, `addr`.
1469pub trait LdlarbEmitter<T0, T1> {
1470    fn ldlarb(&mut self, rd: T0, addr: T1);
1471}
1472
1473/// Emits the `LDLARH` instruction.
1474/// Assembly forms: `LDLARH WD, [XN|SP]`.
1475/// Operands: `rd`, `addr`.
1476pub trait LdlarhEmitter<T0, T1> {
1477    fn ldlarh(&mut self, rd: T0, addr: T1);
1478}
1479
1480/// Emits the `LDNP` instruction.
1481/// Assembly forms: `LDNP WD, WD2, [XN|SP, #OFFS*4]`; `LDNP XD, XD2, [XN|SP, #OFFS*8]`; `LDNP SD, SD2, [XN|SP, #OFFS*4]`; `LDNP DD, DD2, [XN|SP, #OFFS*8]` (and related forms).
1482/// Operands: `rd`, `rd2`, `addr`.
1483pub trait LdnpEmitter<T0, T1, T2> {
1484    fn ldnp(&mut self, rd: T0, rd2: T1, addr: T2);
1485}
1486
1487/// Emits the `LDP` instruction.
1488/// Assembly forms: `LDP WD, WD2, [XN|SP, #OFFS*4]{@}{!}`; `LDP XD, XD2, [XN|SP, #OFFS*8]{@}{!}`; `LDP SD, SD2, [XN|SP, #OFFS*4]{@}{!}`; `LDP DD, DD2, [XN|SP, #OFFS*8]{@}{!}` (and related forms).
1489/// Operands: `rd`, `rd2`, `addr`.
1490pub trait LdpEmitter<T0, T1, T2> {
1491    fn ldp(&mut self, rd: T0, rd2: T1, addr: T2);
1492}
1493
1494/// Emits the `LDPSW` instruction.
1495/// Assembly forms: `LDPSW XD, XD2, [XN|SP, #OFFS*4]{@}{!}`.
1496/// Operands: `rd`, `rd2`, `addr`.
1497pub trait LdpswEmitter<T0, T1, T2> {
1498    fn ldpsw(&mut self, rd: T0, rd2: T1, addr: T2);
1499}
1500
1501/// Emits the `LDR` instruction.
1502/// Assembly forms: `LDR WD, [XN|SP, #OFFZ*4]`; `LDR XD, [XN|SP, #OFFZ*8]`; `LDR WD, [XN|SP, #OFFS*4]@`; `LDR XD, [XN|SP, #OFFS*8]@` (and related forms).
1503/// Operands: `rd`, `addr`.
1504pub trait LdrEmitter<T0, T1> {
1505    fn ldr(&mut self, rd: T0, addr: T1);
1506}
1507
1508/// Emits the `LDRB` instruction.
1509/// Assembly forms: `LDRB WD, [XN|SP, #OFFZ]`; `LDRB WD, [XN|SP, #OFFS]@`; `LDRB WD, [XN|SP, #OFFS]!`; `LDRB WD, [XN|SP, RM, {UXTW|LSL|SXTW|SXTX #N}]`.
1510/// Operands: `rd`, `addr`.
1511pub trait LdrbEmitter<T0, T1> {
1512    fn ldrb(&mut self, rd: T0, addr: T1);
1513}
1514
1515/// Emits the `LDRH` instruction.
1516/// Assembly forms: `LDRH WD, [XN|SP, #OFFZ*2]`; `LDRH WD, [XN|SP, #OFFS*2]@`; `LDRH WD, [XN|SP, #OFFS*2]!`; `LDRH WD, [XN|SP, RM, {UXTW|LSL|SXTW|SXTX #N}]`.
1517/// Operands: `rd`, `addr`.
1518pub trait LdrhEmitter<T0, T1> {
1519    fn ldrh(&mut self, rd: T0, addr: T1);
1520}
1521
1522/// Emits the `LDRSB` instruction.
1523/// Assembly forms: `LDRSB WD, [XN|SP, #OFFZ]`; `LDRSB XD, [XN|SP, #OFFZ]`; `LDRSB WD, [XN|SP, #OFFS]@`; `LDRSB XD, [XN|SP, #OFFS]@` (and related forms).
1524/// Operands: `rd`, `addr`.
1525pub trait LdrsbEmitter<T0, T1> {
1526    fn ldrsb(&mut self, rd: T0, addr: T1);
1527}
1528
1529/// Emits the `LDRSH` instruction.
1530/// Assembly forms: `LDRSH WD, [XN|SP, #OFFZ*2]`; `LDRSH XD, [XN|SP, #OFFZ*2]`; `LDRSH WD, [XN|SP, #OFFS*2]@`; `LDRSH XD, [XN|SP, #OFFS*2]@` (and related forms).
1531/// Operands: `rd`, `addr`.
1532pub trait LdrshEmitter<T0, T1> {
1533    fn ldrsh(&mut self, rd: T0, addr: T1);
1534}
1535
1536/// Emits the `LDRSW` instruction.
1537/// Assembly forms: `LDRSW XD, [XN|SP, #OFFZ*4]`; `LDRSW XD, [XN|SP, #OFFS*4]@`; `LDRSW XD, [XN|SP, #OFFS*4]!`; `LDRSW XD, [PC, #OFFS*4]` (and related forms).
1538/// Operands: `rd`, `addr`.
1539pub trait LdrswEmitter<T0, T1> {
1540    fn ldrsw(&mut self, rd: T0, addr: T1);
1541}
1542
1543/// Emits the `LDSET` instruction.
1544/// Assembly forms: `LDSET WS, WD, [XN|SP]`; `LDSET XS, WD, [XN|SP]`.
1545/// Operands: `rs`, `rd`, `addr`.
1546pub trait LdsetEmitter<T0, T1, T2> {
1547    fn ldset(&mut self, rs: T0, rd: T1, addr: T2);
1548}
1549
1550/// Emits the `LDSETA` instruction.
1551/// Assembly forms: `LDSETA WS, WD, [XN|SP]`; `LDSETA XS, WD, [XN|SP]`.
1552/// Operands: `rs`, `rd`, `addr`.
1553pub trait LdsetaEmitter<T0, T1, T2> {
1554    fn ldseta(&mut self, rs: T0, rd: T1, addr: T2);
1555}
1556
1557/// Emits the `LDSETAB` instruction.
1558/// Assembly forms: `LDSETAB WS, WD, [XN|SP]`.
1559/// Operands: `rs`, `rd`, `addr`.
1560pub trait LdsetabEmitter<T0, T1, T2> {
1561    fn ldsetab(&mut self, rs: T0, rd: T1, addr: T2);
1562}
1563
1564/// Emits the `LDSETAH` instruction.
1565/// Assembly forms: `LDSETAH WS, WD, [XN|SP]`.
1566/// Operands: `rs`, `rd`, `addr`.
1567pub trait LdsetahEmitter<T0, T1, T2> {
1568    fn ldsetah(&mut self, rs: T0, rd: T1, addr: T2);
1569}
1570
1571/// Emits the `LDSETAL` instruction.
1572/// Assembly forms: `LDSETAL WS, WD, [XN|SP]`; `LDSETAL XS, WD, [XN|SP]`.
1573/// Operands: `rs`, `rd`, `addr`.
1574pub trait LdsetalEmitter<T0, T1, T2> {
1575    fn ldsetal(&mut self, rs: T0, rd: T1, addr: T2);
1576}
1577
1578/// Emits the `LDSETALB` instruction.
1579/// Assembly forms: `LDSETALB WS, WD, [XN|SP]`.
1580/// Operands: `rs`, `rd`, `addr`.
1581pub trait LdsetalbEmitter<T0, T1, T2> {
1582    fn ldsetalb(&mut self, rs: T0, rd: T1, addr: T2);
1583}
1584
1585/// Emits the `LDSETALH` instruction.
1586/// Assembly forms: `LDSETALH WS, WD, [XN|SP]`.
1587/// Operands: `rs`, `rd`, `addr`.
1588pub trait LdsetalhEmitter<T0, T1, T2> {
1589    fn ldsetalh(&mut self, rs: T0, rd: T1, addr: T2);
1590}
1591
1592/// Emits the `LDSETB` instruction.
1593/// Assembly forms: `LDSETB WS, WD, [XN|SP]`.
1594/// Operands: `rs`, `rd`, `addr`.
1595pub trait LdsetbEmitter<T0, T1, T2> {
1596    fn ldsetb(&mut self, rs: T0, rd: T1, addr: T2);
1597}
1598
1599/// Emits the `LDSETH` instruction.
1600/// Assembly forms: `LDSETH WS, WD, [XN|SP]`.
1601/// Operands: `rs`, `rd`, `addr`.
1602pub trait LdsethEmitter<T0, T1, T2> {
1603    fn ldseth(&mut self, rs: T0, rd: T1, addr: T2);
1604}
1605
1606/// Emits the `LDSETL` instruction.
1607/// Assembly forms: `LDSETL WS, WD, [XN|SP]`; `LDSETL XS, WD, [XN|SP]`.
1608/// Operands: `rs`, `rd`, `addr`.
1609pub trait LdsetlEmitter<T0, T1, T2> {
1610    fn ldsetl(&mut self, rs: T0, rd: T1, addr: T2);
1611}
1612
1613/// Emits the `LDSETLB` instruction.
1614/// Assembly forms: `LDSETLB WS, WD, [XN|SP]`.
1615/// Operands: `rs`, `rd`, `addr`.
1616pub trait LdsetlbEmitter<T0, T1, T2> {
1617    fn ldsetlb(&mut self, rs: T0, rd: T1, addr: T2);
1618}
1619
1620/// Emits the `LDSETLH` instruction.
1621/// Assembly forms: `LDSETLH WS, WD, [XN|SP]`.
1622/// Operands: `rs`, `rd`, `addr`.
1623pub trait LdsetlhEmitter<T0, T1, T2> {
1624    fn ldsetlh(&mut self, rs: T0, rd: T1, addr: T2);
1625}
1626
1627/// Emits the `LDSMAX` instruction.
1628/// Assembly forms: `LDSMAX WS, WD, [XN|SP]`; `LDSMAX XS, XD, [XN|SP]`.
1629/// Operands: `rs`, `rd`, `addr`.
1630pub trait LdsmaxEmitter<T0, T1, T2> {
1631    fn ldsmax(&mut self, rs: T0, rd: T1, addr: T2);
1632}
1633
1634/// Emits the `LDSMAXA` instruction.
1635/// Assembly forms: `LDSMAXA WS, WD, [XN|SP]`; `LDSMAXA XS, XD, [XN|SP]`.
1636/// Operands: `rs`, `rd`, `addr`.
1637pub trait LdsmaxaEmitter<T0, T1, T2> {
1638    fn ldsmaxa(&mut self, rs: T0, rd: T1, addr: T2);
1639}
1640
1641/// Emits the `LDSMAXAB` instruction.
1642/// Assembly forms: `LDSMAXAB WS, WD, [XN|SP]`.
1643/// Operands: `rs`, `rd`, `addr`.
1644pub trait LdsmaxabEmitter<T0, T1, T2> {
1645    fn ldsmaxab(&mut self, rs: T0, rd: T1, addr: T2);
1646}
1647
1648/// Emits the `LDSMAXAH` instruction.
1649/// Assembly forms: `LDSMAXAH WS, WD, [XN|SP]`.
1650/// Operands: `rs`, `rd`, `addr`.
1651pub trait LdsmaxahEmitter<T0, T1, T2> {
1652    fn ldsmaxah(&mut self, rs: T0, rd: T1, addr: T2);
1653}
1654
1655/// Emits the `LDSMAXAL` instruction.
1656/// Assembly forms: `LDSMAXAL WS, WD, [XN|SP]`; `LDSMAXAL XS, XD, [XN|SP]`.
1657/// Operands: `rs`, `rd`, `addr`.
1658pub trait LdsmaxalEmitter<T0, T1, T2> {
1659    fn ldsmaxal(&mut self, rs: T0, rd: T1, addr: T2);
1660}
1661
1662/// Emits the `LDSMAXALB` instruction.
1663/// Assembly forms: `LDSMAXALB WS, WD, [XN|SP]`.
1664/// Operands: `rs`, `rd`, `addr`.
1665pub trait LdsmaxalbEmitter<T0, T1, T2> {
1666    fn ldsmaxalb(&mut self, rs: T0, rd: T1, addr: T2);
1667}
1668
1669/// Emits the `LDSMAXALH` instruction.
1670/// Assembly forms: `LDSMAXALH WS, WD, [XN|SP]`.
1671/// Operands: `rs`, `rd`, `addr`.
1672pub trait LdsmaxalhEmitter<T0, T1, T2> {
1673    fn ldsmaxalh(&mut self, rs: T0, rd: T1, addr: T2);
1674}
1675
1676/// Emits the `LDSMAXB` instruction.
1677/// Assembly forms: `LDSMAXB WS, WD, [XN|SP]`.
1678/// Operands: `rs`, `rd`, `addr`.
1679pub trait LdsmaxbEmitter<T0, T1, T2> {
1680    fn ldsmaxb(&mut self, rs: T0, rd: T1, addr: T2);
1681}
1682
1683/// Emits the `LDSMAXH` instruction.
1684/// Assembly forms: `LDSMAXH WS, WD, [XN|SP]`.
1685/// Operands: `rs`, `rd`, `addr`.
1686pub trait LdsmaxhEmitter<T0, T1, T2> {
1687    fn ldsmaxh(&mut self, rs: T0, rd: T1, addr: T2);
1688}
1689
1690/// Emits the `LDSMAXL` instruction.
1691/// Assembly forms: `LDSMAXL WS, WD, [XN|SP]`; `LDSMAXL XS, XD, [XN|SP]`.
1692/// Operands: `rs`, `rd`, `addr`.
1693pub trait LdsmaxlEmitter<T0, T1, T2> {
1694    fn ldsmaxl(&mut self, rs: T0, rd: T1, addr: T2);
1695}
1696
1697/// Emits the `LDSMAXLB` instruction.
1698/// Assembly forms: `LDSMAXLB WS, WD, [XN|SP]`.
1699/// Operands: `rs`, `rd`, `addr`.
1700pub trait LdsmaxlbEmitter<T0, T1, T2> {
1701    fn ldsmaxlb(&mut self, rs: T0, rd: T1, addr: T2);
1702}
1703
1704/// Emits the `LDSMAXLH` instruction.
1705/// Assembly forms: `LDSMAXLH WS, WD, [XN|SP]`.
1706/// Operands: `rs`, `rd`, `addr`.
1707pub trait LdsmaxlhEmitter<T0, T1, T2> {
1708    fn ldsmaxlh(&mut self, rs: T0, rd: T1, addr: T2);
1709}
1710
1711/// Emits the `LDSMIN` instruction.
1712/// Assembly forms: `LDSMIN WS, WD, [XN|SP]`; `LDSMIN XS, XD, [XN|SP]`.
1713/// Operands: `rs`, `rd`, `addr`.
1714pub trait LdsminEmitter<T0, T1, T2> {
1715    fn ldsmin(&mut self, rs: T0, rd: T1, addr: T2);
1716}
1717
1718/// Emits the `LDSMINA` instruction.
1719/// Assembly forms: `LDSMINA WS, WD, [XN|SP]`; `LDSMINA XS, XD, [XN|SP]`.
1720/// Operands: `rs`, `rd`, `addr`.
1721pub trait LdsminaEmitter<T0, T1, T2> {
1722    fn ldsmina(&mut self, rs: T0, rd: T1, addr: T2);
1723}
1724
1725/// Emits the `LDSMINAB` instruction.
1726/// Assembly forms: `LDSMINAB WS, WD, [XN|SP]`.
1727/// Operands: `rs`, `rd`, `addr`.
1728pub trait LdsminabEmitter<T0, T1, T2> {
1729    fn ldsminab(&mut self, rs: T0, rd: T1, addr: T2);
1730}
1731
1732/// Emits the `LDSMINAH` instruction.
1733/// Assembly forms: `LDSMINAH WS, WD, [XN|SP]`.
1734/// Operands: `rs`, `rd`, `addr`.
1735pub trait LdsminahEmitter<T0, T1, T2> {
1736    fn ldsminah(&mut self, rs: T0, rd: T1, addr: T2);
1737}
1738
1739/// Emits the `LDSMINAL` instruction.
1740/// Assembly forms: `LDSMINAL WS, WD, [XN|SP]`; `LDSMINAL XS, XD, [XN|SP]`.
1741/// Operands: `rs`, `rd`, `addr`.
1742pub trait LdsminalEmitter<T0, T1, T2> {
1743    fn ldsminal(&mut self, rs: T0, rd: T1, addr: T2);
1744}
1745
1746/// Emits the `LDSMINALB` instruction.
1747/// Assembly forms: `LDSMINALB WS, WD, [XN|SP]`.
1748/// Operands: `rs`, `rd`, `addr`.
1749pub trait LdsminalbEmitter<T0, T1, T2> {
1750    fn ldsminalb(&mut self, rs: T0, rd: T1, addr: T2);
1751}
1752
1753/// Emits the `LDSMINALH` instruction.
1754/// Assembly forms: `LDSMINALH WS, WD, [XN|SP]`.
1755/// Operands: `rs`, `rd`, `addr`.
1756pub trait LdsminalhEmitter<T0, T1, T2> {
1757    fn ldsminalh(&mut self, rs: T0, rd: T1, addr: T2);
1758}
1759
1760/// Emits the `LDSMINB` instruction.
1761/// Assembly forms: `LDSMINB WS, WD, [XN|SP]`.
1762/// Operands: `rs`, `rd`, `addr`.
1763pub trait LdsminbEmitter<T0, T1, T2> {
1764    fn ldsminb(&mut self, rs: T0, rd: T1, addr: T2);
1765}
1766
1767/// Emits the `LDSMINH` instruction.
1768/// Assembly forms: `LDSMINH WS, WD, [XN|SP]`.
1769/// Operands: `rs`, `rd`, `addr`.
1770pub trait LdsminhEmitter<T0, T1, T2> {
1771    fn ldsminh(&mut self, rs: T0, rd: T1, addr: T2);
1772}
1773
1774/// Emits the `LDSMINL` instruction.
1775/// Assembly forms: `LDSMINL WS, WD, [XN|SP]`; `LDSMINL XS, XD, [XN|SP]`.
1776/// Operands: `rs`, `rd`, `addr`.
1777pub trait LdsminlEmitter<T0, T1, T2> {
1778    fn ldsminl(&mut self, rs: T0, rd: T1, addr: T2);
1779}
1780
1781/// Emits the `LDSMINLB` instruction.
1782/// Assembly forms: `LDSMINLB WS, WD, [XN|SP]`.
1783/// Operands: `rs`, `rd`, `addr`.
1784pub trait LdsminlbEmitter<T0, T1, T2> {
1785    fn ldsminlb(&mut self, rs: T0, rd: T1, addr: T2);
1786}
1787
1788/// Emits the `LDSMINLH` instruction.
1789/// Assembly forms: `LDSMINLH WS, WD, [XN|SP]`.
1790/// Operands: `rs`, `rd`, `addr`.
1791pub trait LdsminlhEmitter<T0, T1, T2> {
1792    fn ldsminlh(&mut self, rs: T0, rd: T1, addr: T2);
1793}
1794
1795/// Emits the `LDTR` instruction.
1796/// Assembly forms: `LDTR WD, [XN|SP, #OFFS]`; `LDTR XD, [XN|SP, #OFFS]`.
1797/// Operands: `rd`, `addr`.
1798pub trait LdtrEmitter<T0, T1> {
1799    fn ldtr(&mut self, rd: T0, addr: T1);
1800}
1801
1802/// Emits the `LDTRB` instruction.
1803/// Assembly forms: `LDTRB WD, [XN|SP, #OFFS]`.
1804/// Operands: `rd`, `addr`.
1805pub trait LdtrbEmitter<T0, T1> {
1806    fn ldtrb(&mut self, rd: T0, addr: T1);
1807}
1808
1809/// Emits the `LDTRH` instruction.
1810/// Assembly forms: `LDTRH WD, [XN|SP, #OFFS]`.
1811/// Operands: `rd`, `addr`.
1812pub trait LdtrhEmitter<T0, T1> {
1813    fn ldtrh(&mut self, rd: T0, addr: T1);
1814}
1815
1816/// Emits the `LDTRSB` instruction.
1817/// Assembly forms: `LDTRSB WD, [XN|SP, #OFFS]`; `LDTRSB XD, [XN|SP, #OFFS]`.
1818/// Operands: `rd`, `addr`.
1819pub trait LdtrsbEmitter<T0, T1> {
1820    fn ldtrsb(&mut self, rd: T0, addr: T1);
1821}
1822
1823/// Emits the `LDTRSH` instruction.
1824/// Assembly forms: `LDTRSH WD, [XN|SP, #OFFS]`; `LDTRSH XD, [XN|SP, #OFFS]`.
1825/// Operands: `rd`, `addr`.
1826pub trait LdtrshEmitter<T0, T1> {
1827    fn ldtrsh(&mut self, rd: T0, addr: T1);
1828}
1829
1830/// Emits the `LDTRSW` instruction.
1831/// Assembly forms: `LDTRSW XD, [XN|SP, #OFFS]`.
1832/// Operands: `rd`, `addr`.
1833pub trait LdtrswEmitter<T0, T1> {
1834    fn ldtrsw(&mut self, rd: T0, addr: T1);
1835}
1836
1837/// Emits the `LDUMAX` instruction.
1838/// Assembly forms: `LDUMAX WS, WD, [XN|SP]`; `LDUMAX XS, XD, [XN|SP]`.
1839/// Operands: `rs`, `rd`, `addr`.
1840pub trait LdumaxEmitter<T0, T1, T2> {
1841    fn ldumax(&mut self, rs: T0, rd: T1, addr: T2);
1842}
1843
1844/// Emits the `LDUMAXA` instruction.
1845/// Assembly forms: `LDUMAXA WS, WD, [XN|SP]`; `LDUMAXA XS, XD, [XN|SP]`.
1846/// Operands: `rs`, `rd`, `addr`.
1847pub trait LdumaxaEmitter<T0, T1, T2> {
1848    fn ldumaxa(&mut self, rs: T0, rd: T1, addr: T2);
1849}
1850
1851/// Emits the `LDUMAXAB` instruction.
1852/// Assembly forms: `LDUMAXAB WS, WD, [XN|SP]`.
1853/// Operands: `rs`, `rd`, `addr`.
1854pub trait LdumaxabEmitter<T0, T1, T2> {
1855    fn ldumaxab(&mut self, rs: T0, rd: T1, addr: T2);
1856}
1857
1858/// Emits the `LDUMAXAH` instruction.
1859/// Assembly forms: `LDUMAXAH WS, WD, [XN|SP]`.
1860/// Operands: `rs`, `rd`, `addr`.
1861pub trait LdumaxahEmitter<T0, T1, T2> {
1862    fn ldumaxah(&mut self, rs: T0, rd: T1, addr: T2);
1863}
1864
1865/// Emits the `LDUMAXAL` instruction.
1866/// Assembly forms: `LDUMAXAL WS, WD, [XN|SP]`; `LDUMAXAL XS, XD, [XN|SP]`.
1867/// Operands: `rs`, `rd`, `addr`.
1868pub trait LdumaxalEmitter<T0, T1, T2> {
1869    fn ldumaxal(&mut self, rs: T0, rd: T1, addr: T2);
1870}
1871
1872/// Emits the `LDUMAXALB` instruction.
1873/// Assembly forms: `LDUMAXALB WS, WD, [XN|SP]`.
1874/// Operands: `rs`, `rd`, `addr`.
1875pub trait LdumaxalbEmitter<T0, T1, T2> {
1876    fn ldumaxalb(&mut self, rs: T0, rd: T1, addr: T2);
1877}
1878
1879/// Emits the `LDUMAXALH` instruction.
1880/// Assembly forms: `LDUMAXALH WS, WD, [XN|SP]`.
1881/// Operands: `rs`, `rd`, `addr`.
1882pub trait LdumaxalhEmitter<T0, T1, T2> {
1883    fn ldumaxalh(&mut self, rs: T0, rd: T1, addr: T2);
1884}
1885
1886/// Emits the `LDUMAXB` instruction.
1887/// Assembly forms: `LDUMAXB WS, WD, [XN|SP]`.
1888/// Operands: `rs`, `rd`, `addr`.
1889pub trait LdumaxbEmitter<T0, T1, T2> {
1890    fn ldumaxb(&mut self, rs: T0, rd: T1, addr: T2);
1891}
1892
1893/// Emits the `LDUMAXH` instruction.
1894/// Assembly forms: `LDUMAXH WS, WD, [XN|SP]`.
1895/// Operands: `rs`, `rd`, `addr`.
1896pub trait LdumaxhEmitter<T0, T1, T2> {
1897    fn ldumaxh(&mut self, rs: T0, rd: T1, addr: T2);
1898}
1899
1900/// Emits the `LDUMAXL` instruction.
1901/// Assembly forms: `LDUMAXL WS, WD, [XN|SP]`; `LDUMAXL XS, XD, [XN|SP]`.
1902/// Operands: `rs`, `rd`, `addr`.
1903pub trait LdumaxlEmitter<T0, T1, T2> {
1904    fn ldumaxl(&mut self, rs: T0, rd: T1, addr: T2);
1905}
1906
1907/// Emits the `LDUMAXLB` instruction.
1908/// Assembly forms: `LDUMAXLB WS, WD, [XN|SP]`.
1909/// Operands: `rs`, `rd`, `addr`.
1910pub trait LdumaxlbEmitter<T0, T1, T2> {
1911    fn ldumaxlb(&mut self, rs: T0, rd: T1, addr: T2);
1912}
1913
1914/// Emits the `LDUMAXLH` instruction.
1915/// Assembly forms: `LDUMAXLH WS, WD, [XN|SP]`.
1916/// Operands: `rs`, `rd`, `addr`.
1917pub trait LdumaxlhEmitter<T0, T1, T2> {
1918    fn ldumaxlh(&mut self, rs: T0, rd: T1, addr: T2);
1919}
1920
1921/// Emits the `LDUMIN` instruction.
1922/// Assembly forms: `LDUMIN WS, WD, [XN|SP]`; `LDUMIN XS, XD, [XN|SP]`.
1923/// Operands: `rs`, `rd`, `addr`.
1924pub trait LduminEmitter<T0, T1, T2> {
1925    fn ldumin(&mut self, rs: T0, rd: T1, addr: T2);
1926}
1927
1928/// Emits the `LDUMINA` instruction.
1929/// Assembly forms: `LDUMINA WS, WD, [XN|SP]`; `LDUMINA XS, XD, [XN|SP]`.
1930/// Operands: `rs`, `rd`, `addr`.
1931pub trait LduminaEmitter<T0, T1, T2> {
1932    fn ldumina(&mut self, rs: T0, rd: T1, addr: T2);
1933}
1934
1935/// Emits the `LDUMINAB` instruction.
1936/// Assembly forms: `LDUMINAB WS, WD, [XN|SP]`.
1937/// Operands: `rs`, `rd`, `addr`.
1938pub trait LduminabEmitter<T0, T1, T2> {
1939    fn lduminab(&mut self, rs: T0, rd: T1, addr: T2);
1940}
1941
1942/// Emits the `LDUMINAH` instruction.
1943/// Assembly forms: `LDUMINAH WS, WD, [XN|SP]`.
1944/// Operands: `rs`, `rd`, `addr`.
1945pub trait LduminahEmitter<T0, T1, T2> {
1946    fn lduminah(&mut self, rs: T0, rd: T1, addr: T2);
1947}
1948
1949/// Emits the `LDUMINAL` instruction.
1950/// Assembly forms: `LDUMINAL WS, WD, [XN|SP]`; `LDUMINAL XS, XD, [XN|SP]`.
1951/// Operands: `rs`, `rd`, `addr`.
1952pub trait LduminalEmitter<T0, T1, T2> {
1953    fn lduminal(&mut self, rs: T0, rd: T1, addr: T2);
1954}
1955
1956/// Emits the `LDUMINALB` instruction.
1957/// Assembly forms: `LDUMINALB WS, WD, [XN|SP]`.
1958/// Operands: `rs`, `rd`, `addr`.
1959pub trait LduminalbEmitter<T0, T1, T2> {
1960    fn lduminalb(&mut self, rs: T0, rd: T1, addr: T2);
1961}
1962
1963/// Emits the `LDUMINALH` instruction.
1964/// Assembly forms: `LDUMINALH WS, WD, [XN|SP]`.
1965/// Operands: `rs`, `rd`, `addr`.
1966pub trait LduminalhEmitter<T0, T1, T2> {
1967    fn lduminalh(&mut self, rs: T0, rd: T1, addr: T2);
1968}
1969
1970/// Emits the `LDUMINB` instruction.
1971/// Assembly forms: `LDUMINB WS, WD, [XN|SP]`.
1972/// Operands: `rs`, `rd`, `addr`.
1973pub trait LduminbEmitter<T0, T1, T2> {
1974    fn lduminb(&mut self, rs: T0, rd: T1, addr: T2);
1975}
1976
1977/// Emits the `LDUMINH` instruction.
1978/// Assembly forms: `LDUMINH WS, WD, [XN|SP]`.
1979/// Operands: `rs`, `rd`, `addr`.
1980pub trait LduminhEmitter<T0, T1, T2> {
1981    fn lduminh(&mut self, rs: T0, rd: T1, addr: T2);
1982}
1983
1984/// Emits the `LDUMINL` instruction.
1985/// Assembly forms: `LDUMINL WS, WD, [XN|SP]`; `LDUMINL XS, XD, [XN|SP]`.
1986/// Operands: `rs`, `rd`, `addr`.
1987pub trait LduminlEmitter<T0, T1, T2> {
1988    fn lduminl(&mut self, rs: T0, rd: T1, addr: T2);
1989}
1990
1991/// Emits the `LDUMINLB` instruction.
1992/// Assembly forms: `LDUMINLB WS, WD, [XN|SP]`.
1993/// Operands: `rs`, `rd`, `addr`.
1994pub trait LduminlbEmitter<T0, T1, T2> {
1995    fn lduminlb(&mut self, rs: T0, rd: T1, addr: T2);
1996}
1997
1998/// Emits the `LDUMINLH` instruction.
1999/// Assembly forms: `LDUMINLH WS, WD, [XN|SP]`.
2000/// Operands: `rs`, `rd`, `addr`.
2001pub trait LduminlhEmitter<T0, T1, T2> {
2002    fn lduminlh(&mut self, rs: T0, rd: T1, addr: T2);
2003}
2004
2005/// Emits the `LDUR` instruction.
2006/// Assembly forms: `LDUR WD, [XN|SP, #OFFS]`; `LDUR XD, [XN|SP, #OFFS]`; `LDUR BD, [XN|SP, #OFFS]`; `LDUR HD, [XN|SP, #OFFS]` (and related forms).
2007/// Operands: `rd`, `addr`.
2008pub trait LdurEmitter<T0, T1> {
2009    fn ldur(&mut self, rd: T0, addr: T1);
2010}
2011
2012/// Emits the `LDURB` instruction.
2013/// Assembly forms: `LDURB WD, [XN|SP, #OFFS]`.
2014/// Operands: `rd`, `addr`.
2015pub trait LdurbEmitter<T0, T1> {
2016    fn ldurb(&mut self, rd: T0, addr: T1);
2017}
2018
2019/// Emits the `LDURH` instruction.
2020/// Assembly forms: `LDURH WD, [XN|SP, #OFFS]`.
2021/// Operands: `rd`, `addr`.
2022pub trait LdurhEmitter<T0, T1> {
2023    fn ldurh(&mut self, rd: T0, addr: T1);
2024}
2025
2026/// Emits the `LDURSB` instruction.
2027/// Assembly forms: `LDURSB WD, [XN|SP, #OFFS]`; `LDURSB XD, [XN|SP, #OFFS]`.
2028/// Operands: `rd`, `addr`.
2029pub trait LdursbEmitter<T0, T1> {
2030    fn ldursb(&mut self, rd: T0, addr: T1);
2031}
2032
2033/// Emits the `LDURSH` instruction.
2034/// Assembly forms: `LDURSH WD, [XN|SP, #OFFS]`; `LDURSH XD, [XN|SP, #OFFS]`.
2035/// Operands: `rd`, `addr`.
2036pub trait LdurshEmitter<T0, T1> {
2037    fn ldursh(&mut self, rd: T0, addr: T1);
2038}
2039
2040/// Emits the `LDURSW` instruction.
2041/// Assembly forms: `LDURSW XD, [XN|SP, #OFFS]`.
2042/// Operands: `rd`, `addr`.
2043pub trait LdurswEmitter<T0, T1> {
2044    fn ldursw(&mut self, rd: T0, addr: T1);
2045}
2046
2047/// Emits the `LDXP` instruction.
2048/// Assembly forms: `LDXP WD, WD2, [XN|SP, #OFFS*4]`; `LDXP XD, XD2, [XN|SP, #OFFS*8]`.
2049/// Operands: `rd`, `rd2`, `addr`.
2050pub trait LdxpEmitter<T0, T1, T2> {
2051    fn ldxp(&mut self, rd: T0, rd2: T1, addr: T2);
2052}
2053
2054/// Emits the `LDAXP` instruction.
2055/// Assembly forms: `LDAXP WD, WD2, [XN|SP]`; `LDAXP XD, XD2, [XN|SP]`.
2056/// Operands: `rd`, `rd2`, `addr`.
2057pub trait LdaxpEmitter<T0, T1, T2> {
2058    fn ldaxp(&mut self, rd: T0, rd2: T1, addr: T2);
2059}
2060
2061/// Emits the `LDXR` instruction.
2062/// Assembly forms: `LDXR WD, [XN|SP]`; `LDXR XD, [XN|SP]`.
2063/// Operands: `rd`, `addr`.
2064pub trait LdxrEmitter<T0, T1> {
2065    fn ldxr(&mut self, rd: T0, addr: T1);
2066}
2067
2068/// Emits the `LDXRB` instruction.
2069/// Assembly forms: `LDXRB WD, [XN|SP]`.
2070/// Operands: `rd`, `addr`.
2071pub trait LdxrbEmitter<T0, T1> {
2072    fn ldxrb(&mut self, rd: T0, addr: T1);
2073}
2074
2075/// Emits the `LDXRH` instruction.
2076/// Assembly forms: `LDXRH WD, [XN|SP]`.
2077/// Operands: `rd`, `addr`.
2078pub trait LdxrhEmitter<T0, T1> {
2079    fn ldxrh(&mut self, rd: T0, addr: T1);
2080}
2081
2082/// Emits the `PRFM` instruction.
2083/// Assembly forms: `PRFM #PRF_OP, [XN|SP, RM, {UXTW|LSL|SXTW|SXTX #N*8}]`; `PRFM #PRF_OP, [XN|SP, #OFFZ]`; `PRFM #PRF_OP, [PC, #OFFS*4]`.
2084/// Operands: `prf_op`, `addr`.
2085pub trait PrfmEmitter<T0, T1> {
2086    fn prfm(&mut self, prf_op: T0, addr: T1);
2087}
2088
2089/// Emits the `STADD` instruction.
2090/// Assembly forms: `STADD WS, [XN|SP]`; `STADD XS, [XN|SP]`.
2091/// Operands: `rs`, `addr`.
2092pub trait StaddEmitter<T0, T1> {
2093    fn stadd(&mut self, rs: T0, addr: T1);
2094}
2095
2096/// Emits the `STADDB` instruction.
2097/// Assembly forms: `STADDB WS, [XN|SP]`.
2098/// Operands: `rs`, `addr`.
2099pub trait StaddbEmitter<T0, T1> {
2100    fn staddb(&mut self, rs: T0, addr: T1);
2101}
2102
2103/// Emits the `STADDH` instruction.
2104/// Assembly forms: `STADDH WS, [XN|SP]`.
2105/// Operands: `rs`, `addr`.
2106pub trait StaddhEmitter<T0, T1> {
2107    fn staddh(&mut self, rs: T0, addr: T1);
2108}
2109
2110/// Emits the `STADDL` instruction.
2111/// Assembly forms: `STADDL WS, [XN|SP]`; `STADDL XS, [XN|SP]`.
2112/// Operands: `rs`, `addr`.
2113pub trait StaddlEmitter<T0, T1> {
2114    fn staddl(&mut self, rs: T0, addr: T1);
2115}
2116
2117/// Emits the `STADDLB` instruction.
2118/// Assembly forms: `STADDLB WS, [XN|SP]`.
2119/// Operands: `rs`, `addr`.
2120pub trait StaddlbEmitter<T0, T1> {
2121    fn staddlb(&mut self, rs: T0, addr: T1);
2122}
2123
2124/// Emits the `STADDLH` instruction.
2125/// Assembly forms: `STADDLH WS, [XN|SP]`.
2126/// Operands: `rs`, `addr`.
2127pub trait StaddlhEmitter<T0, T1> {
2128    fn staddlh(&mut self, rs: T0, addr: T1);
2129}
2130
2131/// Emits the `STCLR` instruction.
2132/// Assembly forms: `STCLR WS, [XN|SP]`; `STCLR XS, [XN|SP]`.
2133/// Operands: `rs`, `addr`.
2134pub trait StclrEmitter<T0, T1> {
2135    fn stclr(&mut self, rs: T0, addr: T1);
2136}
2137
2138/// Emits the `STCLRB` instruction.
2139/// Assembly forms: `STCLRB WS, [XN|SP]`.
2140/// Operands: `rs`, `addr`.
2141pub trait StclrbEmitter<T0, T1> {
2142    fn stclrb(&mut self, rs: T0, addr: T1);
2143}
2144
2145/// Emits the `STCLRH` instruction.
2146/// Assembly forms: `STCLRH WS, [XN|SP]`.
2147/// Operands: `rs`, `addr`.
2148pub trait StclrhEmitter<T0, T1> {
2149    fn stclrh(&mut self, rs: T0, addr: T1);
2150}
2151
2152/// Emits the `STCLRL` instruction.
2153/// Assembly forms: `STCLRL WS, [XN|SP]`; `STCLRL XS, [XN|SP]`.
2154/// Operands: `rs`, `addr`.
2155pub trait StclrlEmitter<T0, T1> {
2156    fn stclrl(&mut self, rs: T0, addr: T1);
2157}
2158
2159/// Emits the `STCLRLB` instruction.
2160/// Assembly forms: `STCLRLB WS, [XN|SP]`.
2161/// Operands: `rs`, `addr`.
2162pub trait StclrlbEmitter<T0, T1> {
2163    fn stclrlb(&mut self, rs: T0, addr: T1);
2164}
2165
2166/// Emits the `STCLRLH` instruction.
2167/// Assembly forms: `STCLRLH WS, [XN|SP]`.
2168/// Operands: `rs`, `addr`.
2169pub trait StclrlhEmitter<T0, T1> {
2170    fn stclrlh(&mut self, rs: T0, addr: T1);
2171}
2172
2173/// Emits the `STEOR` instruction.
2174/// Assembly forms: `STEOR WS, [XN|SP]`; `STEOR XS, [XN|SP]`.
2175/// Operands: `rs`, `addr`.
2176pub trait SteorEmitter<T0, T1> {
2177    fn steor(&mut self, rs: T0, addr: T1);
2178}
2179
2180/// Emits the `STEORB` instruction.
2181/// Assembly forms: `STEORB WS, [XN|SP]`.
2182/// Operands: `rs`, `addr`.
2183pub trait SteorbEmitter<T0, T1> {
2184    fn steorb(&mut self, rs: T0, addr: T1);
2185}
2186
2187/// Emits the `STEORH` instruction.
2188/// Assembly forms: `STEORH WS, [XN|SP]`.
2189/// Operands: `rs`, `addr`.
2190pub trait SteorhEmitter<T0, T1> {
2191    fn steorh(&mut self, rs: T0, addr: T1);
2192}
2193
2194/// Emits the `STEORL` instruction.
2195/// Assembly forms: `STEORL WS, [XN|SP]`; `STEORL XS, [XN|SP]`.
2196/// Operands: `rs`, `addr`.
2197pub trait SteorlEmitter<T0, T1> {
2198    fn steorl(&mut self, rs: T0, addr: T1);
2199}
2200
2201/// Emits the `STEORLB` instruction.
2202/// Assembly forms: `STEORLB WS, [XN|SP]`.
2203/// Operands: `rs`, `addr`.
2204pub trait SteorlbEmitter<T0, T1> {
2205    fn steorlb(&mut self, rs: T0, addr: T1);
2206}
2207
2208/// Emits the `STEORLH` instruction.
2209/// Assembly forms: `STEORLH WS, [XN|SP]`.
2210/// Operands: `rs`, `addr`.
2211pub trait SteorlhEmitter<T0, T1> {
2212    fn steorlh(&mut self, rs: T0, addr: T1);
2213}
2214
2215/// Emits the `STLLR` instruction.
2216/// Assembly forms: `STLLR WS, [XN|SP]`; `STLLR XS, [XN|SP]`.
2217/// Operands: `rs`, `addr`.
2218pub trait StllrEmitter<T0, T1> {
2219    fn stllr(&mut self, rs: T0, addr: T1);
2220}
2221
2222/// Emits the `STLLRB` instruction.
2223/// Assembly forms: `STLLRB WS, [XN|SP]`.
2224/// Operands: `rs`, `addr`.
2225pub trait StllrbEmitter<T0, T1> {
2226    fn stllrb(&mut self, rs: T0, addr: T1);
2227}
2228
2229/// Emits the `STLLRH` instruction.
2230/// Assembly forms: `STLLRH WS, [XN|SP]`.
2231/// Operands: `rs`, `addr`.
2232pub trait StllrhEmitter<T0, T1> {
2233    fn stllrh(&mut self, rs: T0, addr: T1);
2234}
2235
2236/// Emits the `STLR` instruction.
2237/// Assembly forms: `STLR WS, [XN|SP]`; `STLR XS, [XN|SP]`.
2238/// Operands: `rs`, `addr`.
2239pub trait StlrEmitter<T0, T1> {
2240    fn stlr(&mut self, rs: T0, addr: T1);
2241}
2242
2243/// Emits the `STLRB` instruction.
2244/// Assembly forms: `STLRB WS, [XN|SP]`.
2245/// Operands: `rs`, `addr`.
2246pub trait StlrbEmitter<T0, T1> {
2247    fn stlrb(&mut self, rs: T0, addr: T1);
2248}
2249
2250/// Emits the `STLRH` instruction.
2251/// Assembly forms: `STLRH WS, [XN|SP]`.
2252/// Operands: `rs`, `addr`.
2253pub trait StlrhEmitter<T0, T1> {
2254    fn stlrh(&mut self, rs: T0, addr: T1);
2255}
2256
2257/// Emits the `STLXR` instruction.
2258/// Assembly forms: `STLXR WD, WS, [XN|SP]`; `STLXR WD, XS, [XN|SP]`.
2259/// Operands: `rd`, `rs`, `addr`.
2260pub trait StlxrEmitter<T0, T1, T2> {
2261    fn stlxr(&mut self, rd: T0, rs: T1, addr: T2);
2262}
2263
2264/// Emits the `STLXRB` instruction.
2265/// Assembly forms: `STLXRB WD, WS, [XN|SP]`.
2266/// Operands: `rd`, `rs`, `addr`.
2267pub trait StlxrbEmitter<T0, T1, T2> {
2268    fn stlxrb(&mut self, rd: T0, rs: T1, addr: T2);
2269}
2270
2271/// Emits the `STLXRH` instruction.
2272/// Assembly forms: `STLXRH WD, XS, [XN|SP]`.
2273/// Operands: `rd`, `rs`, `addr`.
2274pub trait StlxrhEmitter<T0, T1, T2> {
2275    fn stlxrh(&mut self, rd: T0, rs: T1, addr: T2);
2276}
2277
2278/// Emits the `STNP` instruction.
2279/// Assembly forms: `STNP WS, WS2, [XN|SP, #OFFS*4]`; `STNP XS, XS2, [XN|SP, #OFFS*8]`; `STNP SD, SD2, [XN|SP, #OFFS*4]`; `STNP DD, DD2, [XN|SP, #OFFS*8]` (and related forms).
2280/// Operands: `rs_or_rd`, `rs2_or_rd2`, `addr`.
2281pub trait StnpEmitter<T0, T1, T2> {
2282    fn stnp(&mut self, rs_or_rd: T0, rs2_or_rd2: T1, addr: T2);
2283}
2284
2285/// Emits the `STP` instruction.
2286/// Assembly forms: `STP WS, WS2, [XN|SP, #OFFS*4]{@}{!}`; `STP XS, XS2, [XN|SP, #OFFS*8]{@}{!}`; `STP SD, SD2, [XN|SP, #OFFS*4]{@}{!}`; `STP DD, DD2, [XN|SP, #OFFS*8]{@}{!}` (and related forms).
2287/// Operands: `rs_or_rd`, `rs2_or_rd2`, `addr`.
2288pub trait StpEmitter<T0, T1, T2> {
2289    fn stp(&mut self, rs_or_rd: T0, rs2_or_rd2: T1, addr: T2);
2290}
2291
2292/// Emits the `STR` instruction.
2293/// Assembly forms: `STR WS, [XN|SP, #OFFZ*4]`; `STR XS, [XN|SP, #OFFZ*8]`; `STR WS, [XN|SP, #OFFS*4]@`; `STR XS, [XN|SP, #OFFS*8]@` (and related forms).
2294/// Operands: `rs_or_rd`, `addr`.
2295pub trait StrEmitter<T0, T1> {
2296    fn str(&mut self, rs_or_rd: T0, addr: T1);
2297}
2298
2299/// Emits the `STRB` instruction.
2300/// Assembly forms: `STRB WS, [XN|SP, #OFFZ]`; `STRB WS, [XN|SP, #OFFS]@`; `STRB WS, [XN|SP, #OFFS]!`; `STRB WS, [XN|SP, RM, {UXTW|LSL|SXTW|SXTX #N}]`.
2301/// Operands: `rs`, `addr`.
2302pub trait StrbEmitter<T0, T1> {
2303    fn strb(&mut self, rs: T0, addr: T1);
2304}
2305
2306/// Emits the `STRH` instruction.
2307/// Assembly forms: `STRH WS, [XN|SP, #OFFZ*2]`; `STRH WS, [XN|SP, #OFFS*2]@`; `STRH WS, [XN|SP, #OFFS*2]!`; `STRH WS, [XN|SP, RM, {UXTW|LSL|SXTW|SXTX #N}]`.
2308/// Operands: `rs`, `addr`.
2309pub trait StrhEmitter<T0, T1> {
2310    fn strh(&mut self, rs: T0, addr: T1);
2311}
2312
2313/// Emits the `STSET` instruction.
2314/// Assembly forms: `STSET WS, [XN|SP]`; `STSET XS, [XN|SP]`.
2315/// Operands: `rs`, `addr`.
2316pub trait StsetEmitter<T0, T1> {
2317    fn stset(&mut self, rs: T0, addr: T1);
2318}
2319
2320/// Emits the `STSETB` instruction.
2321/// Assembly forms: `STSETB WS, [XN|SP]`.
2322/// Operands: `rs`, `addr`.
2323pub trait StsetbEmitter<T0, T1> {
2324    fn stsetb(&mut self, rs: T0, addr: T1);
2325}
2326
2327/// Emits the `STSETH` instruction.
2328/// Assembly forms: `STSETH WS, [XN|SP]`.
2329/// Operands: `rs`, `addr`.
2330pub trait StsethEmitter<T0, T1> {
2331    fn stseth(&mut self, rs: T0, addr: T1);
2332}
2333
2334/// Emits the `STSETL` instruction.
2335/// Assembly forms: `STSETL WS, [XN|SP]`; `STSETL XS, [XN|SP]`.
2336/// Operands: `rs`, `addr`.
2337pub trait StsetlEmitter<T0, T1> {
2338    fn stsetl(&mut self, rs: T0, addr: T1);
2339}
2340
2341/// Emits the `STSETLB` instruction.
2342/// Assembly forms: `STSETLB WS, [XN|SP]`.
2343/// Operands: `rs`, `addr`.
2344pub trait StsetlbEmitter<T0, T1> {
2345    fn stsetlb(&mut self, rs: T0, addr: T1);
2346}
2347
2348/// Emits the `STSETLH` instruction.
2349/// Assembly forms: `STSETLH WS, [XN|SP]`.
2350/// Operands: `rs`, `addr`.
2351pub trait StsetlhEmitter<T0, T1> {
2352    fn stsetlh(&mut self, rs: T0, addr: T1);
2353}
2354
2355/// Emits the `STSMAX` instruction.
2356/// Assembly forms: `STSMAX WS, [XN|SP]`; `STSMAX XS, [XN|SP]`.
2357/// Operands: `rs`, `addr`.
2358pub trait StsmaxEmitter<T0, T1> {
2359    fn stsmax(&mut self, rs: T0, addr: T1);
2360}
2361
2362/// Emits the `STSMAXB` instruction.
2363/// Assembly forms: `STSMAXB WS, [XN|SP]`.
2364/// Operands: `rs`, `addr`.
2365pub trait StsmaxbEmitter<T0, T1> {
2366    fn stsmaxb(&mut self, rs: T0, addr: T1);
2367}
2368
2369/// Emits the `STSMAXH` instruction.
2370/// Assembly forms: `STSMAXH WS, [XN|SP]`.
2371/// Operands: `rs`, `addr`.
2372pub trait StsmaxhEmitter<T0, T1> {
2373    fn stsmaxh(&mut self, rs: T0, addr: T1);
2374}
2375
2376/// Emits the `STSMAXL` instruction.
2377/// Assembly forms: `STSMAXL WS, [XN|SP]`; `STSMAXL XS, [XN|SP]`.
2378/// Operands: `rs`, `addr`.
2379pub trait StsmaxlEmitter<T0, T1> {
2380    fn stsmaxl(&mut self, rs: T0, addr: T1);
2381}
2382
2383/// Emits the `STSMAXLB` instruction.
2384/// Assembly forms: `STSMAXLB WS, [XN|SP]`.
2385/// Operands: `rs`, `addr`.
2386pub trait StsmaxlbEmitter<T0, T1> {
2387    fn stsmaxlb(&mut self, rs: T0, addr: T1);
2388}
2389
2390/// Emits the `STSMAXLH` instruction.
2391/// Assembly forms: `STSMAXLH WS, [XN|SP]`.
2392/// Operands: `rs`, `addr`.
2393pub trait StsmaxlhEmitter<T0, T1> {
2394    fn stsmaxlh(&mut self, rs: T0, addr: T1);
2395}
2396
2397/// Emits the `STSMIN` instruction.
2398/// Assembly forms: `STSMIN WS, [XN|SP]`; `STSMIN XS, [XN|SP]`.
2399/// Operands: `rs`, `addr`.
2400pub trait StsminEmitter<T0, T1> {
2401    fn stsmin(&mut self, rs: T0, addr: T1);
2402}
2403
2404/// Emits the `STSMINB` instruction.
2405/// Assembly forms: `STSMINB WS, [XN|SP]`.
2406/// Operands: `rs`, `addr`.
2407pub trait StsminbEmitter<T0, T1> {
2408    fn stsminb(&mut self, rs: T0, addr: T1);
2409}
2410
2411/// Emits the `STSMINH` instruction.
2412/// Assembly forms: `STSMINH WS, [XN|SP]`.
2413/// Operands: `rs`, `addr`.
2414pub trait StsminhEmitter<T0, T1> {
2415    fn stsminh(&mut self, rs: T0, addr: T1);
2416}
2417
2418/// Emits the `STSMINL` instruction.
2419/// Assembly forms: `STSMINL WS, [XN|SP]`; `STSMINL XS, [XN|SP]`.
2420/// Operands: `rs`, `addr`.
2421pub trait StsminlEmitter<T0, T1> {
2422    fn stsminl(&mut self, rs: T0, addr: T1);
2423}
2424
2425/// Emits the `STSMINLB` instruction.
2426/// Assembly forms: `STSMINLB WS, [XN|SP]`.
2427/// Operands: `rs`, `addr`.
2428pub trait StsminlbEmitter<T0, T1> {
2429    fn stsminlb(&mut self, rs: T0, addr: T1);
2430}
2431
2432/// Emits the `STSMINLH` instruction.
2433/// Assembly forms: `STSMINLH WS, [XN|SP]`.
2434/// Operands: `rs`, `addr`.
2435pub trait StsminlhEmitter<T0, T1> {
2436    fn stsminlh(&mut self, rs: T0, addr: T1);
2437}
2438
2439/// Emits the `STTR` instruction.
2440/// Assembly forms: `STTR WS, [XN|SP, #OFFS]`; `STTR XS, [XN|SP, #OFFS]`.
2441/// Operands: `rs`, `addr`.
2442pub trait SttrEmitter<T0, T1> {
2443    fn sttr(&mut self, rs: T0, addr: T1);
2444}
2445
2446/// Emits the `STTRB` instruction.
2447/// Assembly forms: `STTRB WS, [XN|SP, #OFFS]`.
2448/// Operands: `rs`, `addr`.
2449pub trait SttrbEmitter<T0, T1> {
2450    fn sttrb(&mut self, rs: T0, addr: T1);
2451}
2452
2453/// Emits the `STTRH` instruction.
2454/// Assembly forms: `STTRH WS, [XN|SP, #OFFS]`.
2455/// Operands: `rs`, `addr`.
2456pub trait SttrhEmitter<T0, T1> {
2457    fn sttrh(&mut self, rs: T0, addr: T1);
2458}
2459
2460/// Emits the `STUMAX` instruction.
2461/// Assembly forms: `STUMAX WS, [XN|SP]`; `STUMAX XS, [XN|SP]`.
2462/// Operands: `rs`, `addr`.
2463pub trait StumaxEmitter<T0, T1> {
2464    fn stumax(&mut self, rs: T0, addr: T1);
2465}
2466
2467/// Emits the `STUMAXB` instruction.
2468/// Assembly forms: `STUMAXB WS, [XN|SP]`.
2469/// Operands: `rs`, `addr`.
2470pub trait StumaxbEmitter<T0, T1> {
2471    fn stumaxb(&mut self, rs: T0, addr: T1);
2472}
2473
2474/// Emits the `STUMAXH` instruction.
2475/// Assembly forms: `STUMAXH WS, [XN|SP]`.
2476/// Operands: `rs`, `addr`.
2477pub trait StumaxhEmitter<T0, T1> {
2478    fn stumaxh(&mut self, rs: T0, addr: T1);
2479}
2480
2481/// Emits the `STUMAXL` instruction.
2482/// Assembly forms: `STUMAXL WS, [XN|SP]`; `STUMAXL XS, [XN|SP]`.
2483/// Operands: `rs`, `addr`.
2484pub trait StumaxlEmitter<T0, T1> {
2485    fn stumaxl(&mut self, rs: T0, addr: T1);
2486}
2487
2488/// Emits the `STUMAXLB` instruction.
2489/// Assembly forms: `STUMAXLB WS, [XN|SP]`.
2490/// Operands: `rs`, `addr`.
2491pub trait StumaxlbEmitter<T0, T1> {
2492    fn stumaxlb(&mut self, rs: T0, addr: T1);
2493}
2494
2495/// Emits the `STUMAXLH` instruction.
2496/// Assembly forms: `STUMAXLH WS, [XN|SP]`.
2497/// Operands: `rs`, `addr`.
2498pub trait StumaxlhEmitter<T0, T1> {
2499    fn stumaxlh(&mut self, rs: T0, addr: T1);
2500}
2501
2502/// Emits the `STUMIN` instruction.
2503/// Assembly forms: `STUMIN WS, [XN|SP]`; `STUMIN XS, [XN|SP]`.
2504/// Operands: `rs`, `addr`.
2505pub trait StuminEmitter<T0, T1> {
2506    fn stumin(&mut self, rs: T0, addr: T1);
2507}
2508
2509/// Emits the `STUMINB` instruction.
2510/// Assembly forms: `STUMINB WS, [XN|SP]`.
2511/// Operands: `rs`, `addr`.
2512pub trait StuminbEmitter<T0, T1> {
2513    fn stuminb(&mut self, rs: T0, addr: T1);
2514}
2515
2516/// Emits the `STUMINH` instruction.
2517/// Assembly forms: `STUMINH WS, [XN|SP]`.
2518/// Operands: `rs`, `addr`.
2519pub trait StuminhEmitter<T0, T1> {
2520    fn stuminh(&mut self, rs: T0, addr: T1);
2521}
2522
2523/// Emits the `STUMINL` instruction.
2524/// Assembly forms: `STUMINL WS, [XN|SP]`; `STUMINL XS, [XN|SP]`.
2525/// Operands: `rs`, `addr`.
2526pub trait StuminlEmitter<T0, T1> {
2527    fn stuminl(&mut self, rs: T0, addr: T1);
2528}
2529
2530/// Emits the `STUMINLB` instruction.
2531/// Assembly forms: `STUMINLB WS, [XN|SP]`.
2532/// Operands: `rs`, `addr`.
2533pub trait StuminlbEmitter<T0, T1> {
2534    fn stuminlb(&mut self, rs: T0, addr: T1);
2535}
2536
2537/// Emits the `STUMINLH` instruction.
2538/// Assembly forms: `STUMINLH WS, [XN|SP]`.
2539/// Operands: `rs`, `addr`.
2540pub trait StuminlhEmitter<T0, T1> {
2541    fn stuminlh(&mut self, rs: T0, addr: T1);
2542}
2543
2544/// Emits the `STUR` instruction.
2545/// Assembly forms: `STUR WS, [XN|SP, #OFFS]`; `STUR XS, [XN|SP, #OFFS]`; `STUR BD, [XN|SP, #OFFS]`; `STUR HD, [XN|SP, #OFFS]` (and related forms).
2546/// Operands: `rs_or_rd`, `addr`.
2547pub trait SturEmitter<T0, T1> {
2548    fn stur(&mut self, rs_or_rd: T0, addr: T1);
2549}
2550
2551/// Emits the `STURB` instruction.
2552/// Assembly forms: `STURB WS, [XN|SP, #OFFS]`.
2553/// Operands: `rs`, `addr`.
2554pub trait SturbEmitter<T0, T1> {
2555    fn sturb(&mut self, rs: T0, addr: T1);
2556}
2557
2558/// Emits the `STURH` instruction.
2559/// Assembly forms: `STURH WS, [XN|SP, #OFFS]`.
2560/// Operands: `rs`, `addr`.
2561pub trait SturhEmitter<T0, T1> {
2562    fn sturh(&mut self, rs: T0, addr: T1);
2563}
2564
2565/// Emits the `STXP` instruction.
2566/// Assembly forms: `STXP WD, WS, WS2, [XN|SP]`; `STXP WD, XS, XS2, [XN|SP]`.
2567/// Operands: `rd`, `rs`, `rs2`, `addr`.
2568pub trait StxpEmitter<T0, T1, T2, T3> {
2569    fn stxp(&mut self, rd: T0, rs: T1, rs2: T2, addr: T3);
2570}
2571
2572/// Emits the `STLXP` instruction.
2573/// Assembly forms: `STLXP WD, WS, WS2, [XN|SP]`; `STLXP WD, XS, XS2, [XN|SP]`.
2574/// Operands: `rd`, `rs`, `rs2`, `addr`.
2575pub trait StlxpEmitter<T0, T1, T2, T3> {
2576    fn stlxp(&mut self, rd: T0, rs: T1, rs2: T2, addr: T3);
2577}
2578
2579/// Emits the `STXR` instruction.
2580/// Assembly forms: `STXR WD, WS, [XN|SP]`; `STXR WD, XS, [XN|SP]`.
2581/// Operands: `rd`, `rs`, `addr`.
2582pub trait StxrEmitter<T0, T1, T2> {
2583    fn stxr(&mut self, rd: T0, rs: T1, addr: T2);
2584}
2585
2586/// Emits the `STXRB` instruction.
2587/// Assembly forms: `STXRB WD, WS, [XN|SP]`.
2588/// Operands: `rd`, `rs`, `addr`.
2589pub trait StxrbEmitter<T0, T1, T2> {
2590    fn stxrb(&mut self, rd: T0, rs: T1, addr: T2);
2591}
2592
2593/// Emits the `STXRH` instruction.
2594/// Assembly forms: `STXRH WD, XS, [XN|SP]`.
2595/// Operands: `rd`, `rs`, `addr`.
2596pub trait StxrhEmitter<T0, T1, T2> {
2597    fn stxrh(&mut self, rd: T0, rs: T1, addr: T2);
2598}
2599
2600/// Emits the `SWP` instruction.
2601/// Assembly forms: `SWP WS, WD, [XN|SP]`; `SWP XS, XD, [XN|SP]`.
2602/// Operands: `rs`, `rd`, `addr`.
2603pub trait SwpEmitter<T0, T1, T2> {
2604    fn swp(&mut self, rs: T0, rd: T1, addr: T2);
2605}
2606
2607/// Emits the `SWPA` instruction.
2608/// Assembly forms: `SWPA WS, WD, [XN|SP]`; `SWPA XS, XD, [XN|SP]`.
2609/// Operands: `rs`, `rd`, `addr`.
2610pub trait SwpaEmitter<T0, T1, T2> {
2611    fn swpa(&mut self, rs: T0, rd: T1, addr: T2);
2612}
2613
2614/// Emits the `SWPAB` instruction.
2615/// Assembly forms: `SWPAB WS, WD, [XN|SP]`.
2616/// Operands: `rs`, `rd`, `addr`.
2617pub trait SwpabEmitter<T0, T1, T2> {
2618    fn swpab(&mut self, rs: T0, rd: T1, addr: T2);
2619}
2620
2621/// Emits the `SWPAH` instruction.
2622/// Assembly forms: `SWPAH WS, WD, [XN|SP]`.
2623/// Operands: `rs`, `rd`, `addr`.
2624pub trait SwpahEmitter<T0, T1, T2> {
2625    fn swpah(&mut self, rs: T0, rd: T1, addr: T2);
2626}
2627
2628/// Emits the `SWPAL` instruction.
2629/// Assembly forms: `SWPAL WS, WD, [XN|SP]`; `SWPAL XS, XD, [XN|SP]`.
2630/// Operands: `rs`, `rd`, `addr`.
2631pub trait SwpalEmitter<T0, T1, T2> {
2632    fn swpal(&mut self, rs: T0, rd: T1, addr: T2);
2633}
2634
2635/// Emits the `SWPALB` instruction.
2636/// Assembly forms: `SWPALB WS, WD, [XN|SP]`.
2637/// Operands: `rs`, `rd`, `addr`.
2638pub trait SwpalbEmitter<T0, T1, T2> {
2639    fn swpalb(&mut self, rs: T0, rd: T1, addr: T2);
2640}
2641
2642/// Emits the `SWPALH` instruction.
2643/// Assembly forms: `SWPALH WS, WD, [XN|SP]`.
2644/// Operands: `rs`, `rd`, `addr`.
2645pub trait SwpalhEmitter<T0, T1, T2> {
2646    fn swpalh(&mut self, rs: T0, rd: T1, addr: T2);
2647}
2648
2649/// Emits the `SWPB` instruction.
2650/// Assembly forms: `SWPB WS, WD, [XN|SP]`.
2651/// Operands: `rs`, `rd`, `addr`.
2652pub trait SwpbEmitter<T0, T1, T2> {
2653    fn swpb(&mut self, rs: T0, rd: T1, addr: T2);
2654}
2655
2656/// Emits the `SWPH` instruction.
2657/// Assembly forms: `SWPH WS, WD, [XN|SP]`.
2658/// Operands: `rs`, `rd`, `addr`.
2659pub trait SwphEmitter<T0, T1, T2> {
2660    fn swph(&mut self, rs: T0, rd: T1, addr: T2);
2661}
2662
2663/// Emits the `SWPL` instruction.
2664/// Assembly forms: `SWPL WS, WD, [XN|SP]`; `SWPL XS, XD, [XN|SP]`.
2665/// Operands: `rs`, `rd`, `addr`.
2666pub trait SwplEmitter<T0, T1, T2> {
2667    fn swpl(&mut self, rs: T0, rd: T1, addr: T2);
2668}
2669
2670/// Emits the `SWPLB` instruction.
2671/// Assembly forms: `SWPLB WS, WD, [XN|SP]`.
2672/// Operands: `rs`, `rd`, `addr`.
2673pub trait SwplbEmitter<T0, T1, T2> {
2674    fn swplb(&mut self, rs: T0, rd: T1, addr: T2);
2675}
2676
2677/// Emits the `SWPLH` instruction.
2678/// Assembly forms: `SWPLH WS, WD, [XN|SP]`.
2679/// Operands: `rs`, `rd`, `addr`.
2680pub trait SwplhEmitter<T0, T1, T2> {
2681    fn swplh(&mut self, rs: T0, rd: T1, addr: T2);
2682}
2683
2684/// Emits the `BTI` instruction.
2685/// Assembly forms: `BTI {#TARGETS}`.
2686/// Operands: `targets`.
2687pub trait BtiEmitter<T0> {
2688    fn bti(&mut self, targets: T0);
2689}
2690
2691/// Emits the `CHKFEAT` instruction.
2692/// Assembly forms: `CHKFEAT`.
2693/// Operands: `rd`.
2694pub trait ChkfeatEmitter<T0> {
2695    fn chkfeat(&mut self, rd: T0);
2696}
2697
2698/// Emits the `CLRBHB` instruction.
2699/// Assembly forms: `CLRBHB`.
2700pub trait ClrbhbEmitter {
2701    fn clrbhb(&mut self);
2702}
2703
2704/// Emits the `CRC32B` instruction.
2705/// Assembly forms: `CRC32B WD, WN, WM`.
2706/// Operands: `rd`, `rn`, `rm`.
2707pub trait Crc32bEmitter<T0, T1, T2> {
2708    fn crc32b(&mut self, rd: T0, rn: T1, rm: T2);
2709}
2710
2711/// Emits the `CRC32H` instruction.
2712/// Assembly forms: `CRC32H WD, WN, WM`.
2713/// Operands: `rd`, `rn`, `rm`.
2714pub trait Crc32hEmitter<T0, T1, T2> {
2715    fn crc32h(&mut self, rd: T0, rn: T1, rm: T2);
2716}
2717
2718/// Emits the `CRC32W` instruction.
2719/// Assembly forms: `CRC32W WD, WN, WM`.
2720/// Operands: `rd`, `rn`, `rm`.
2721pub trait Crc32wEmitter<T0, T1, T2> {
2722    fn crc32w(&mut self, rd: T0, rn: T1, rm: T2);
2723}
2724
2725/// Emits the `CRC32X` instruction.
2726/// Assembly forms: `CRC32X XD, XN, XM`.
2727/// Operands: `rd`, `rn`, `rm`.
2728pub trait Crc32xEmitter<T0, T1, T2> {
2729    fn crc32x(&mut self, rd: T0, rn: T1, rm: T2);
2730}
2731
2732/// Emits the `CRC32CB` instruction.
2733/// Assembly forms: `CRC32CB WD, WN, WM`.
2734/// Operands: `rd`, `rn`, `rm`.
2735pub trait Crc32cbEmitter<T0, T1, T2> {
2736    fn crc32cb(&mut self, rd: T0, rn: T1, rm: T2);
2737}
2738
2739/// Emits the `CRC32CH` instruction.
2740/// Assembly forms: `CRC32CH WD, WN, WM`.
2741/// Operands: `rd`, `rn`, `rm`.
2742pub trait Crc32chEmitter<T0, T1, T2> {
2743    fn crc32ch(&mut self, rd: T0, rn: T1, rm: T2);
2744}
2745
2746/// Emits the `CRC32CW` instruction.
2747/// Assembly forms: `CRC32CW WD, WN, WM`.
2748/// Operands: `rd`, `rn`, `rm`.
2749pub trait Crc32cwEmitter<T0, T1, T2> {
2750    fn crc32cw(&mut self, rd: T0, rn: T1, rm: T2);
2751}
2752
2753/// Emits the `CRC32CX` instruction.
2754/// Assembly forms: `CRC32CX XD, XN, XM`.
2755/// Operands: `rd`, `rn`, `rm`.
2756pub trait Crc32cxEmitter<T0, T1, T2> {
2757    fn crc32cx(&mut self, rd: T0, rn: T1, rm: T2);
2758}
2759
2760/// Emits the `ABS` instruction.
2761/// Assembly forms: `ABS WD, WN`; `ABS XD, XN`; `ABS DD, DN`; `ABS VD.T, VN.T` (and related forms).
2762/// Operands: `rd`, `rn`.
2763pub trait AbsEmitter<T0, T1> {
2764    fn abs(&mut self, rd: T0, rn: T1);
2765}
2766
2767/// Emits the `CNT` instruction.
2768/// Assembly forms: `CNT WD, WN`; `CNT XD, XN`; `CNT VD.8B, VN.8B`; `CNT VD.16B, VN.16B`.
2769/// Operands: `rd`, `rn`.
2770pub trait CntEmitter<T0, T1> {
2771    fn cnt(&mut self, rd: T0, rn: T1);
2772}
2773
2774/// Emits the `CTZ` instruction.
2775/// Assembly forms: `CTZ WD, WN`; `CTZ XD, XN`.
2776/// Operands: `rd`, `rn`.
2777pub trait CtzEmitter<T0, T1> {
2778    fn ctz(&mut self, rd: T0, rn: T1);
2779}
2780
2781/// Emits the `SMAX` instruction.
2782/// Assembly forms: `SMAX WD, WN, WM`; `SMAX XD, XN, XM`; `SMAX WD, WN, #IMMS`; `SMAX XD, XN, #IMMS` (and related forms).
2783/// Operands: `rd`, `rn`, `rm_or_imm`.
2784pub trait SmaxEmitter<T0, T1, T2> {
2785    fn smax(&mut self, rd: T0, rn: T1, rm_or_imm: T2);
2786}
2787
2788/// Emits the `SMIN` instruction.
2789/// Assembly forms: `SMIN WD, WN, WM`; `SMIN XD, XN, XM`; `SMIN WD, WN, #IMMS`; `SMIN XD, XN, #IMMS` (and related forms).
2790/// Operands: `rd`, `rn`, `rm_or_imm`.
2791pub trait SminEmitter<T0, T1, T2> {
2792    fn smin(&mut self, rd: T0, rn: T1, rm_or_imm: T2);
2793}
2794
2795/// Emits the `UMAX` instruction.
2796/// Assembly forms: `UMAX WD, WN, WM`; `UMAX XD, XN, XM`; `UMAX WD, WN, #IMMZ`; `UMAX XD, XN, #IMMZ` (and related forms).
2797/// Operands: `rd`, `rn`, `rm_or_imm`.
2798pub trait UmaxEmitter<T0, T1, T2> {
2799    fn umax(&mut self, rd: T0, rn: T1, rm_or_imm: T2);
2800}
2801
2802/// Emits the `UMIN` instruction.
2803/// Assembly forms: `UMIN WD, WN, WM`; `UMIN XD, XN, XM`; `UMIN WD, WN, #IMMZ`; `UMIN XD, XN, #IMMZ` (and related forms).
2804/// Operands: `rd`, `rn`, `rm_or_imm`.
2805pub trait UminEmitter<T0, T1, T2> {
2806    fn umin(&mut self, rd: T0, rn: T1, rm_or_imm: T2);
2807}
2808
2809/// Emits the `DGH` instruction.
2810/// Assembly forms: `DGH`.
2811pub trait DghEmitter {
2812    fn dgh(&mut self);
2813}
2814
2815/// Emits the `CFINV` instruction.
2816/// Assembly forms: `CFINV`.
2817pub trait CfinvEmitter {
2818    fn cfinv(&mut self);
2819}
2820
2821/// Emits the `SETF8` instruction.
2822/// Assembly forms: `SETF8 WN`.
2823/// Operands: `rn`.
2824pub trait Setf8Emitter<T0> {
2825    fn setf8(&mut self, rn: T0);
2826}
2827
2828/// Emits the `SETF16` instruction.
2829/// Assembly forms: `SETF16 WN`.
2830/// Operands: `rn`.
2831pub trait Setf16Emitter<T0> {
2832    fn setf16(&mut self, rn: T0);
2833}
2834
2835/// Emits the `AXFLAG` instruction.
2836/// Assembly forms: `AXFLAG`.
2837pub trait AxflagEmitter {
2838    fn axflag(&mut self);
2839}
2840
2841/// Emits the `XAFLAG` instruction.
2842/// Assembly forms: `XAFLAG`.
2843pub trait XaflagEmitter {
2844    fn xaflag(&mut self);
2845}
2846
2847/// Emits the `BC` instruction.
2848/// Assembly forms: `BC.<COND> #RELS*4`.
2849/// Operands: `target`.
2850pub trait BcEmitter<T0> {
2851    fn bc(&mut self, target: T0);
2852    fn bc_eq(&mut self, target: T0);
2853    fn bc_ne(&mut self, target: T0);
2854    fn bc_cs(&mut self, target: T0);
2855    fn bc_hs(&mut self, target: T0);
2856    fn bc_cc(&mut self, target: T0);
2857    fn bc_lo(&mut self, target: T0);
2858    fn bc_mi(&mut self, target: T0);
2859    fn bc_pl(&mut self, target: T0);
2860    fn bc_vs(&mut self, target: T0);
2861    fn bc_vc(&mut self, target: T0);
2862    fn bc_hi(&mut self, target: T0);
2863    fn bc_ls(&mut self, target: T0);
2864    fn bc_ge(&mut self, target: T0);
2865    fn bc_lt(&mut self, target: T0);
2866    fn bc_gt(&mut self, target: T0);
2867    fn bc_le(&mut self, target: T0);
2868    fn bc_al(&mut self, target: T0);
2869}
2870
2871/// Emits the `AUTDA` instruction.
2872/// Assembly forms: `AUTDA XD, XN|SP`.
2873/// Operands: `rd`, `rn`.
2874pub trait AutdaEmitter<T0, T1> {
2875    fn autda(&mut self, rd: T0, rn: T1);
2876}
2877
2878/// Emits the `AUTDB` instruction.
2879/// Assembly forms: `AUTDB XD, XN|SP`.
2880/// Operands: `rd`, `rn`.
2881pub trait AutdbEmitter<T0, T1> {
2882    fn autdb(&mut self, rd: T0, rn: T1);
2883}
2884
2885/// Emits the `AUTDZA` instruction.
2886/// Assembly forms: `AUTDZA XD`.
2887/// Operands: `rd`.
2888pub trait AutdzaEmitter<T0> {
2889    fn autdza(&mut self, rd: T0);
2890}
2891
2892/// Emits the `AUTDZB` instruction.
2893/// Assembly forms: `AUTDZB XD`.
2894/// Operands: `rd`.
2895pub trait AutdzbEmitter<T0> {
2896    fn autdzb(&mut self, rd: T0);
2897}
2898
2899/// Emits the `AUTIA` instruction.
2900/// Assembly forms: `AUTIA XD, XN|SP`.
2901/// Operands: `rd`, `rn`.
2902pub trait AutiaEmitter<T0, T1> {
2903    fn autia(&mut self, rd: T0, rn: T1);
2904}
2905
2906/// Emits the `AUTIA1716` instruction.
2907/// Assembly forms: `AUTIA1716`.
2908pub trait Autia1716Emitter {
2909    fn autia1716(&mut self);
2910}
2911
2912/// Emits the `AUTIASP` instruction.
2913/// Assembly forms: `AUTIASP`.
2914pub trait AutiaspEmitter {
2915    fn autiasp(&mut self);
2916}
2917
2918/// Emits the `AUTIAZ` instruction.
2919/// Assembly forms: `AUTIAZ`.
2920pub trait AutiazEmitter {
2921    fn autiaz(&mut self);
2922}
2923
2924/// Emits the `AUTIB` instruction.
2925/// Assembly forms: `AUTIB XD, XN|SP`.
2926/// Operands: `rd`, `rn`.
2927pub trait AutibEmitter<T0, T1> {
2928    fn autib(&mut self, rd: T0, rn: T1);
2929}
2930
2931/// Emits the `AUTIB1716` instruction.
2932/// Assembly forms: `AUTIB1716`.
2933pub trait Autib1716Emitter {
2934    fn autib1716(&mut self);
2935}
2936
2937/// Emits the `AUTIBSP` instruction.
2938/// Assembly forms: `AUTIBSP`.
2939pub trait AutibspEmitter {
2940    fn autibsp(&mut self);
2941}
2942
2943/// Emits the `AUTIBZ` instruction.
2944/// Assembly forms: `AUTIBZ`.
2945pub trait AutibzEmitter {
2946    fn autibz(&mut self);
2947}
2948
2949/// Emits the `AUTIZA` instruction.
2950/// Assembly forms: `AUTIZA XD`.
2951/// Operands: `rd`.
2952pub trait AutizaEmitter<T0> {
2953    fn autiza(&mut self, rd: T0);
2954}
2955
2956/// Emits the `AUTIZB` instruction.
2957/// Assembly forms: `AUTIZB XD`.
2958/// Operands: `rd`.
2959pub trait AutizbEmitter<T0> {
2960    fn autizb(&mut self, rd: T0);
2961}
2962
2963/// Emits the `GMI` instruction.
2964/// Assembly forms: `GMI XD, XN|SP, XM`.
2965/// Operands: `rd`, `rn`, `rm`.
2966pub trait GmiEmitter<T0, T1, T2> {
2967    fn gmi(&mut self, rd: T0, rn: T1, rm: T2);
2968}
2969
2970/// Emits the `CMPP` instruction.
2971/// Assembly forms: `CMPP XN|SP, XM|SP`.
2972/// Operands: `rn`, `rm`.
2973pub trait CmppEmitter<T0, T1> {
2974    fn cmpp(&mut self, rn: T0, rm: T1);
2975}
2976
2977/// Emits the `ADDG` instruction.
2978/// Assembly forms: `ADDG XD|SP, XN|SP, #IMM1, #IMM2`.
2979/// Operands: `rd`, `rn`, `imm1`, `imm2`.
2980pub trait AddgEmitter<T0, T1, T2, T3> {
2981    fn addg(&mut self, rd: T0, rn: T1, imm1: T2, imm2: T3);
2982}
2983
2984/// Emits the `LDG` instruction.
2985/// Assembly forms: `LDG XD, [XN|SP, #OFFS*16]`.
2986/// Operands: `rd`, `addr`.
2987pub trait LdgEmitter<T0, T1> {
2988    fn ldg(&mut self, rd: T0, addr: T1);
2989}
2990
2991/// Emits the `LDGM` instruction.
2992/// Assembly forms: `LDGM XD, [XN|SP]`.
2993/// Operands: `rd`, `addr`.
2994pub trait LdgmEmitter<T0, T1> {
2995    fn ldgm(&mut self, rd: T0, addr: T1);
2996}
2997
2998/// Emits the `LDRAA` instruction.
2999/// Assembly forms: `LDRAA XD, [XN|SP, #OFFS]{!}`.
3000/// Operands: `rd`, `addr`.
3001pub trait LdraaEmitter<T0, T1> {
3002    fn ldraa(&mut self, rd: T0, addr: T1);
3003}
3004
3005/// Emits the `LDRAB` instruction.
3006/// Assembly forms: `LDRAB XD, [XN|SP, #OFFS]{!}`.
3007/// Operands: `rd`, `addr`.
3008pub trait LdrabEmitter<T0, T1> {
3009    fn ldrab(&mut self, rd: T0, addr: T1);
3010}
3011
3012/// Emits the `PACDA` instruction.
3013/// Assembly forms: `PACDA XD, XN|SP`.
3014/// Operands: `rd`, `rn`.
3015pub trait PacdaEmitter<T0, T1> {
3016    fn pacda(&mut self, rd: T0, rn: T1);
3017}
3018
3019/// Emits the `PACDB` instruction.
3020/// Assembly forms: `PACDB XD, XN|SP`.
3021/// Operands: `rd`, `rn`.
3022pub trait PacdbEmitter<T0, T1> {
3023    fn pacdb(&mut self, rd: T0, rn: T1);
3024}
3025
3026/// Emits the `PACDZA` instruction.
3027/// Assembly forms: `PACDZA XD`.
3028/// Operands: `rd`.
3029pub trait PacdzaEmitter<T0> {
3030    fn pacdza(&mut self, rd: T0);
3031}
3032
3033/// Emits the `PACDZB` instruction.
3034/// Assembly forms: `PACDZB XD`.
3035/// Operands: `rd`.
3036pub trait PacdzbEmitter<T0> {
3037    fn pacdzb(&mut self, rd: T0);
3038}
3039
3040/// Emits the `PACGA` instruction.
3041/// Assembly forms: `PACGA XD, XN, XM|SP`.
3042/// Operands: `rd`, `rn`, `rm`.
3043pub trait PacgaEmitter<T0, T1, T2> {
3044    fn pacga(&mut self, rd: T0, rn: T1, rm: T2);
3045}
3046
3047/// Emits the `SUBP` instruction.
3048/// Assembly forms: `SUBP XD, XN|SP, XM|SP`.
3049/// Operands: `rd`, `rn`, `rm`.
3050pub trait SubpEmitter<T0, T1, T2> {
3051    fn subp(&mut self, rd: T0, rn: T1, rm: T2);
3052}
3053
3054/// Emits the `SUBPS` instruction.
3055/// Assembly forms: `SUBPS XD, XN|SP, XM|SP`.
3056/// Operands: `rd`, `rn`, `rm`.
3057pub trait SubpsEmitter<T0, T1, T2> {
3058    fn subps(&mut self, rd: T0, rn: T1, rm: T2);
3059}
3060
3061/// Emits the `SUBG` instruction.
3062/// Assembly forms: `SUBG XD|SP, XN|SP, #IMM1, #IMM2`.
3063/// Operands: `rd`, `rn`, `imm1`, `imm2`.
3064pub trait SubgEmitter<T0, T1, T2, T3> {
3065    fn subg(&mut self, rd: T0, rn: T1, imm1: T2, imm2: T3);
3066}
3067
3068/// Emits the `ST2G` instruction.
3069/// Assembly forms: `ST2G XS|SP, [XN|SP, #OFFS*16]{@}{!}`.
3070/// Operands: `rs`, `addr`.
3071pub trait St2gEmitter<T0, T1> {
3072    fn st2g(&mut self, rs: T0, addr: T1);
3073}
3074
3075/// Emits the `STG` instruction.
3076/// Assembly forms: `STG XS|SP, [XN|SP, #OFFS*16]{@}{!}`.
3077/// Operands: `rs`, `addr`.
3078pub trait StgEmitter<T0, T1> {
3079    fn stg(&mut self, rs: T0, addr: T1);
3080}
3081
3082/// Emits the `STGP` instruction.
3083/// Assembly forms: `STGP XS, XS2, [XN|SP, #OFFS*16]{@}{!}`.
3084/// Operands: `rs`, `rs2`, `addr`.
3085pub trait StgpEmitter<T0, T1, T2> {
3086    fn stgp(&mut self, rs: T0, rs2: T1, addr: T2);
3087}
3088
3089/// Emits the `STGM` instruction.
3090/// Assembly forms: `STGM XS, [XN|SP]`.
3091/// Operands: `rs`, `addr`.
3092pub trait StgmEmitter<T0, T1> {
3093    fn stgm(&mut self, rs: T0, addr: T1);
3094}
3095
3096/// Emits the `STZG` instruction.
3097/// Assembly forms: `STZG XS|SP, [XN|SP, #OFFS*16]{@}{!}`.
3098/// Operands: `rs`, `addr`.
3099pub trait StzgEmitter<T0, T1> {
3100    fn stzg(&mut self, rs: T0, addr: T1);
3101}
3102
3103/// Emits the `STZ2G` instruction.
3104/// Assembly forms: `STZ2G XS|SP, [XN|SP, #OFFS*16]{@}{!}`.
3105/// Operands: `rs`, `addr`.
3106pub trait Stz2gEmitter<T0, T1> {
3107    fn stz2g(&mut self, rs: T0, addr: T1);
3108}
3109
3110/// Emits the `STZGM` instruction.
3111/// Assembly forms: `STZGM XS, [XN|SP]`.
3112/// Operands: `rs`, `addr`.
3113pub trait StzgmEmitter<T0, T1> {
3114    fn stzgm(&mut self, rs: T0, addr: T1);
3115}
3116
3117/// Emits the `XPACD` instruction.
3118/// Assembly forms: `XPACD XD`.
3119/// Operands: `rd`.
3120pub trait XpacdEmitter<T0> {
3121    fn xpacd(&mut self, rd: T0);
3122}
3123
3124/// Emits the `XPACI` instruction.
3125/// Assembly forms: `XPACI XD`.
3126/// Operands: `rd`.
3127pub trait XpaciEmitter<T0> {
3128    fn xpaci(&mut self, rd: T0);
3129}
3130
3131/// Emits the `XPACLRI` instruction.
3132/// Assembly forms: `XPACLRI XD`.
3133pub trait XpaclriEmitter {
3134    fn xpaclri(&mut self);
3135}
3136
3137/// Emits the `HINT` instruction.
3138/// Assembly forms: `HINT #IMM`.
3139/// Operands: `imm`.
3140pub trait HintEmitter<T0> {
3141    fn hint(&mut self, imm: T0);
3142}
3143
3144/// Emits the `NOP` instruction.
3145/// Assembly forms: `NOP`.
3146pub trait NopEmitter {
3147    fn nop(&mut self);
3148}
3149
3150/// Emits the `SEV` instruction.
3151/// Assembly forms: `SEV`.
3152pub trait SevEmitter {
3153    fn sev(&mut self);
3154}
3155
3156/// Emits the `SEVL` instruction.
3157/// Assembly forms: `SEVL`.
3158pub trait SevlEmitter {
3159    fn sevl(&mut self);
3160}
3161
3162/// Emits the `WFE` instruction.
3163/// Assembly forms: `WFE`.
3164pub trait WfeEmitter {
3165    fn wfe(&mut self);
3166}
3167
3168/// Emits the `WFI` instruction.
3169/// Assembly forms: `WFI`.
3170pub trait WfiEmitter {
3171    fn wfi(&mut self);
3172}
3173
3174/// Emits the `YIELD` instruction.
3175/// Assembly forms: `YIELD`.
3176pub trait YieldEmitter {
3177    fn r#yield(&mut self);
3178}
3179
3180/// Emits the `ADDHN` instruction.
3181/// Assembly forms: `ADDHN VD.TA, VN.TB, VM.TB`.
3182/// Operands: `rd`, `rn`, `rm`.
3183pub trait AddhnEmitter<T0, T1, T2> {
3184    fn addhn(&mut self, rd: T0, rn: T1, rm: T2);
3185}
3186
3187/// Emits the `ADDHN2` instruction.
3188/// Assembly forms: `ADDHN2 VX.TA, VN.TB, VM.TB`.
3189/// Operands: `operand_1`, `rn`, `rm`.
3190pub trait Addhn2Emitter<T0, T1, T2> {
3191    fn addhn2(&mut self, operand_1: T0, rn: T1, rm: T2);
3192}
3193
3194/// Emits the `ADDP` instruction.
3195/// Assembly forms: `ADDP DD, VN.2D`; `ADDP VD.T, VN.T, VM.T`; `ADDP VD.T, VN.T, VM.T`.
3196/// Operands: `rd`, `rn`.
3197pub trait AddpEmitter<T0, T1> {
3198    fn addp(&mut self, rd: T0, rn: T1);
3199}
3200
3201/// Emits the `ADDP_3` instruction.
3202/// Assembly forms: `ADDP DD, VN.2D`; `ADDP VD.T, VN.T, VM.T`; `ADDP VD.T, VN.T, VM.T`.
3203/// Operands: `rd`, `rn`, `rm`.
3204pub trait Addp3Emitter<T0, T1, T2> {
3205    fn addp_3(&mut self, rd: T0, rn: T1, rm: T2);
3206}
3207
3208/// Emits the `ADDV` instruction.
3209/// Assembly forms: `ADDV BD, VN.8B`; `ADDV BD, VN.16B`; `ADDV HD, VN.4H`; `ADDV HD, VN.8H` (and related forms).
3210/// Operands: `rd`, `rn`.
3211pub trait AddvEmitter<T0, T1> {
3212    fn addv(&mut self, rd: T0, rn: T1);
3213}
3214
3215/// Emits the `BIC_2` instruction.
3216/// Assembly forms: `BIC WD, WN, WM, {SOP #N}`; `BIC XD, XN, XM, {SOP #N}`; `BIC VD.8B, VN.8B, VM.8B`; `BIC VD.16B, VN.16B, VM.16B` (and related forms).
3217/// Operands: `rd`, `rn_or_imm`.
3218pub trait Bic2Emitter<T0, T1> {
3219    fn bic_2(&mut self, rd: T0, rn_or_imm: T1);
3220}
3221
3222/// Emits the `BIF` instruction.
3223/// Assembly forms: `BIF DX.8B, VN.8B, VM.8B`; `BIF VX.16B, VN.16B, VM.16B`.
3224/// Operands: `operand_1`, `rn`, `rm`.
3225pub trait BifEmitter<T0, T1, T2> {
3226    fn bif(&mut self, operand_1: T0, rn: T1, rm: T2);
3227}
3228
3229/// Emits the `BIT` instruction.
3230/// Assembly forms: `BIT DX.8B, VN.8B, VM.8B`; `BIT VX.16B, VN.16B, VM.16B`.
3231/// Operands: `operand_1`, `rn`, `rm`.
3232pub trait BitEmitter<T0, T1, T2> {
3233    fn bit(&mut self, operand_1: T0, rn: T1, rm: T2);
3234}
3235
3236/// Emits the `BSL` instruction.
3237/// Assembly forms: `BSL DX.8B, VN.8B, VM.8B`; `BSL VX.16B, VN.16B, VM.16B`.
3238/// Operands: `operand_1`, `rn`, `rm`.
3239pub trait BslEmitter<T0, T1, T2> {
3240    fn bsl(&mut self, operand_1: T0, rn: T1, rm: T2);
3241}
3242
3243/// Emits the `CMEQ` instruction.
3244/// Assembly forms: `CMEQ DD, DN, DM`; `CMEQ DD, DN, #0`; `CMEQ VD.T, VN.T, VM.T`; `CMEQ VD.T, VN.T, #0` (and related forms).
3245/// Operands: `rd`, `rn`, `rm_or_operand_3`.
3246pub trait CmeqEmitter<T0, T1, T2> {
3247    fn cmeq(&mut self, rd: T0, rn: T1, rm_or_operand_3: T2);
3248}
3249
3250/// Emits the `CMGE` instruction.
3251/// Assembly forms: `CMGE DD, DN, DM`; `CMGE DD, DN, #0`; `CMGE VD.T, VN.T, VM.T`; `CMGE VD.T, VN.T, #0` (and related forms).
3252/// Operands: `rd`, `rn`, `rm_or_operand_3`.
3253pub trait CmgeEmitter<T0, T1, T2> {
3254    fn cmge(&mut self, rd: T0, rn: T1, rm_or_operand_3: T2);
3255}
3256
3257/// Emits the `CMGT` instruction.
3258/// Assembly forms: `CMGT DD, DN, DM`; `CMGT DD, DN, #0`; `CMGT VD.T, VN.T, VM.T`; `CMGT VD.T, VN.T, #0` (and related forms).
3259/// Operands: `rd`, `rn`, `rm_or_operand_3`.
3260pub trait CmgtEmitter<T0, T1, T2> {
3261    fn cmgt(&mut self, rd: T0, rn: T1, rm_or_operand_3: T2);
3262}
3263
3264/// Emits the `CMHI` instruction.
3265/// Assembly forms: `CMHI DD, DN, DM`; `CMHI VD.T, VN.T, VM.T`; `CMHI VD.T, VN.T, VM.T`.
3266/// Operands: `rd`, `rn`, `rm`.
3267pub trait CmhiEmitter<T0, T1, T2> {
3268    fn cmhi(&mut self, rd: T0, rn: T1, rm: T2);
3269}
3270
3271/// Emits the `CMHS` instruction.
3272/// Assembly forms: `CMHS DD, DN, DM`; `CMHS VD.T, VN.T, VM.T`; `CMHS VD.T, VN.T, VM.T`.
3273/// Operands: `rd`, `rn`, `rm`.
3274pub trait CmhsEmitter<T0, T1, T2> {
3275    fn cmhs(&mut self, rd: T0, rn: T1, rm: T2);
3276}
3277
3278/// Emits the `CMLE` instruction.
3279/// Assembly forms: `CMLE DD, DN, #0`; `CMLE VD.T, VN.T, #0`; `CMLE VD.T, VN.T, #0`.
3280/// Operands: `rd`, `rn`, `operand_3`.
3281pub trait CmleEmitter<T0, T1, T2> {
3282    fn cmle(&mut self, rd: T0, rn: T1, operand_3: T2);
3283}
3284
3285/// Emits the `CMLT` instruction.
3286/// Assembly forms: `CMLT DD, DN, #0`; `CMLT VD.T, VN.T, #0`; `CMLT VD.T, VN.T, #0`.
3287/// Operands: `rd`, `rn`, `operand_3`.
3288pub trait CmltEmitter<T0, T1, T2> {
3289    fn cmlt(&mut self, rd: T0, rn: T1, operand_3: T2);
3290}
3291
3292/// Emits the `CMTST` instruction.
3293/// Assembly forms: `CMTST DD, DN, DM`; `CMTST VD.T, VN.T, VM.T`; `CMTST VD.T, VN.T, VM.T`.
3294/// Operands: `rd`, `rn`, `rm`.
3295pub trait CmtstEmitter<T0, T1, T2> {
3296    fn cmtst(&mut self, rd: T0, rn: T1, rm: T2);
3297}
3298
3299/// Emits the `DUP` instruction.
3300/// Assembly forms: `DUP|MOV BD, VN.B[#IDX]`; `DUP|MOV HD, VN.H[#IDX]`; `DUP|MOV SD, VN.S[#IDX]`; `DUP|MOV DD, VN.D[#IDX]` (and related forms).
3301/// Operands: `rd`, `rn`.
3302pub trait DupEmitter<T0, T1> {
3303    fn dup(&mut self, rd: T0, rn: T1);
3304}
3305
3306/// Emits the `EXT` instruction.
3307/// Assembly forms: `EXT VD.8B, VN.8B, VM.8B, #IDX`; `EXT VD.16B, VN.16B, VM.16B, #IDX`.
3308/// Operands: `rd`, `rn`, `rm`, `idx`.
3309pub trait ExtEmitter<T0, T1, T2, T3> {
3310    fn ext(&mut self, rd: T0, rn: T1, rm: T2, idx: T3);
3311}
3312
3313/// Emits the `FABD` instruction.
3314/// Assembly forms: `FABD SD, SN, SM`; `FABD DD, DN, DM`; `FABD VD.2S, VN.2S, VM.2S`; `FABD VD.4S, VN.4S, VM.4S` (and related forms).
3315/// Operands: `rd`, `rn`, `rm`.
3316pub trait FabdEmitter<T0, T1, T2> {
3317    fn fabd(&mut self, rd: T0, rn: T1, rm: T2);
3318}
3319
3320/// Emits the `FABS` instruction.
3321/// Assembly forms: `FABS SD, SN`; `FABS DD, DN`; `FABS VD.2S, VN.2S`; `FABS VD.4S, VN.4S` (and related forms).
3322/// Operands: `rd`, `rn`.
3323pub trait FabsEmitter<T0, T1> {
3324    fn fabs(&mut self, rd: T0, rn: T1);
3325}
3326
3327/// Emits the `FACGE` instruction.
3328/// Assembly forms: `FACGE SD, SN, SM`; `FACGE DD, DN, DM`; `FACGE VD.2S, VN.2S, VM.2S`; `FACGE VD.4S, VN.4S, VM.4S` (and related forms).
3329/// Operands: `rd`, `rn`, `rm`.
3330pub trait FacgeEmitter<T0, T1, T2> {
3331    fn facge(&mut self, rd: T0, rn: T1, rm: T2);
3332}
3333
3334/// Emits the `FACGT` instruction.
3335/// Assembly forms: `FACGT SD, SN, SM`; `FACGT DD, DN, DM`; `FACGT VD.2S, VN.2S, VM.2S`; `FACGT VD.4S, VN.4S, VM.4S` (and related forms).
3336/// Operands: `rd`, `rn`, `rm`.
3337pub trait FacgtEmitter<T0, T1, T2> {
3338    fn facgt(&mut self, rd: T0, rn: T1, rm: T2);
3339}
3340
3341/// Emits the `FADD` instruction.
3342/// Assembly forms: `FADD SD, SN, SM`; `FADD DD, DN, DM`; `FADD VD.2S, VN.2S, VM.2S`; `FADD VD.4S, VN.4S, VM.4S` (and related forms).
3343/// Operands: `rd`, `rn`, `rm`.
3344pub trait FaddEmitter<T0, T1, T2> {
3345    fn fadd(&mut self, rd: T0, rn: T1, rm: T2);
3346}
3347
3348/// Emits the `FADDP` instruction.
3349/// Assembly forms: `FADDP SD, VN.2S`; `FADDP DD, VN.2D`; `FADDP VD.2S, VN.2S, VM.2S`; `FADDP VD.4S, VN.4S, VM.4S` (and related forms).
3350/// Operands: `rd`, `rn`.
3351pub trait FaddpEmitter<T0, T1> {
3352    fn faddp(&mut self, rd: T0, rn: T1);
3353}
3354
3355/// Emits the `FADDP_3` instruction.
3356/// Assembly forms: `FADDP SD, VN.2S`; `FADDP DD, VN.2D`; `FADDP VD.2S, VN.2S, VM.2S`; `FADDP VD.4S, VN.4S, VM.4S` (and related forms).
3357/// Operands: `rd`, `rn`, `rm`.
3358pub trait Faddp3Emitter<T0, T1, T2> {
3359    fn faddp_3(&mut self, rd: T0, rn: T1, rm: T2);
3360}
3361
3362/// Emits the `FCCMP` instruction.
3363/// Assembly forms: `FCCMP SN, SM, #NZCV, #COND`; `FCCMP DN, DM, #NZCV, #COND`; `FCCMP HN, HM, #NZCV, #COND`.
3364/// Operands: `rn`, `rm`, `flags`, `condition`.
3365pub trait FccmpEmitter<T0, T1, T2, T3> {
3366    fn fccmp(&mut self, rn: T0, rm: T1, flags: T2, condition: T3);
3367}
3368
3369/// Emits the `FCCMPE` instruction.
3370/// Assembly forms: `FCCMPE SN, SM, #NZCV, #COND`; `FCCMPE DN, DM, #NZCV, #COND`; `FCCMPE HN, HM, #NZCV, #COND`.
3371/// Operands: `rn`, `rm`, `flags`, `condition`.
3372pub trait FccmpeEmitter<T0, T1, T2, T3> {
3373    fn fccmpe(&mut self, rn: T0, rm: T1, flags: T2, condition: T3);
3374}
3375
3376/// Emits the `FCMEQ` instruction.
3377/// Assembly forms: `FCMEQ SD, SN, SM`; `FCMEQ SD, SN, #0`; `FCMEQ DD, DN, DM`; `FCMEQ DD, DN, #0` (and related forms).
3378/// Operands: `rd`, `rn`, `rm_or_operand_3`.
3379pub trait FcmeqEmitter<T0, T1, T2> {
3380    fn fcmeq(&mut self, rd: T0, rn: T1, rm_or_operand_3: T2);
3381}
3382
3383/// Emits the `FCMGE` instruction.
3384/// Assembly forms: `FCMGE SD, SN, SM`; `FCMGE SD, SN, #0`; `FCMGE DD, DN, DM`; `FCMGE DD, DN, #0` (and related forms).
3385/// Operands: `rd`, `rn`, `rm_or_operand_3`.
3386pub trait FcmgeEmitter<T0, T1, T2> {
3387    fn fcmge(&mut self, rd: T0, rn: T1, rm_or_operand_3: T2);
3388}
3389
3390/// Emits the `FCMGT` instruction.
3391/// Assembly forms: `FCMGT SD, SN, SM`; `FCMGT SD, SN, #0`; `FCMGT DD, DN, DM`; `FCMGT DD, DN, #0` (and related forms).
3392/// Operands: `rd`, `rn`, `rm_or_operand_3`.
3393pub trait FcmgtEmitter<T0, T1, T2> {
3394    fn fcmgt(&mut self, rd: T0, rn: T1, rm_or_operand_3: T2);
3395}
3396
3397/// Emits the `FCMLE` instruction.
3398/// Assembly forms: `FCMLE SD, SN, #0`; `FCMLE DD, DN, #0`; `FCMLE VD.2S, VN.2S, #0`; `FCMLE VD.4S, VN.4S, #0` (and related forms).
3399/// Operands: `rd`, `rn`, `operand_3`.
3400pub trait FcmleEmitter<T0, T1, T2> {
3401    fn fcmle(&mut self, rd: T0, rn: T1, operand_3: T2);
3402}
3403
3404/// Emits the `FCMLT` instruction.
3405/// Assembly forms: `FCMLT SD, SN, #0`; `FCMLT DD, DN, #0`; `FCMLT VD.2S, VN.2S, #0`; `FCMLT VD.4S, VN.4S, #0` (and related forms).
3406/// Operands: `rd`, `rn`, `operand_3`.
3407pub trait FcmltEmitter<T0, T1, T2> {
3408    fn fcmlt(&mut self, rd: T0, rn: T1, operand_3: T2);
3409}
3410
3411/// Emits the `FCMP` instruction.
3412/// Assembly forms: `FCMP SN, SM`; `FCMP SN, #0`; `FCMP DN, DM`; `FCMP DN, #0` (and related forms).
3413/// Operands: `rn`, `rm_or_operand_2`.
3414pub trait FcmpEmitter<T0, T1> {
3415    fn fcmp(&mut self, rn: T0, rm_or_operand_2: T1);
3416}
3417
3418/// Emits the `FCMPE` instruction.
3419/// Assembly forms: `FCMPE SN, SM`; `FCMPE SN, #0`; `FCMPE DN, DM`; `FCMPE DN, #0` (and related forms).
3420/// Operands: `rn`, `rm_or_operand_2`.
3421pub trait FcmpeEmitter<T0, T1> {
3422    fn fcmpe(&mut self, rn: T0, rm_or_operand_2: T1);
3423}
3424
3425/// Emits the `FCSEL` instruction.
3426/// Assembly forms: `FCSEL SD, SN, SM, #COND`; `FCSEL DD, DN, DM, #COND`; `FCSEL HD, HN, HM, #COND`.
3427/// Operands: `rd`, `rn`, `rm`, `condition`.
3428pub trait FcselEmitter<T0, T1, T2, T3> {
3429    fn fcsel(&mut self, rd: T0, rn: T1, rm: T2, condition: T3);
3430}
3431
3432/// Emits the `FCVT` instruction.
3433/// Assembly forms: `FCVT SD, HN`; `FCVT DD, HN`; `FCVT HD, SN`; `FCVT DD, SN` (and related forms).
3434/// Operands: `rd`, `rn`.
3435pub trait FcvtEmitter<T0, T1> {
3436    fn fcvt(&mut self, rd: T0, rn: T1);
3437}
3438
3439/// Emits the `FCVTAS` instruction.
3440/// Assembly forms: `FCVTAS WD, SN`; `FCVTAS XD, SN`; `FCVTAS WD, DN`; `FCVTAS XD, DN` (and related forms).
3441/// Operands: `rd`, `rn`.
3442pub trait FcvtasEmitter<T0, T1> {
3443    fn fcvtas(&mut self, rd: T0, rn: T1);
3444}
3445
3446/// Emits the `FCVTAU` instruction.
3447/// Assembly forms: `FCVTAU WD, SN`; `FCVTAU XD, SN`; `FCVTAU WD, DN`; `FCVTAU XD, DN` (and related forms).
3448/// Operands: `rd`, `rn`.
3449pub trait FcvtauEmitter<T0, T1> {
3450    fn fcvtau(&mut self, rd: T0, rn: T1);
3451}
3452
3453/// Emits the `FCVTL` instruction.
3454/// Assembly forms: `FCVTL VD.4S, VN.4H`; `FCVTL VD.2D, VN.2S`.
3455/// Operands: `rd`, `rn`.
3456pub trait FcvtlEmitter<T0, T1> {
3457    fn fcvtl(&mut self, rd: T0, rn: T1);
3458}
3459
3460/// Emits the `FCVTL2` instruction.
3461/// Assembly forms: `FCVTL2 VD.4S, VN.8H`; `FCVTL2 VD.2D, VN.4S`.
3462/// Operands: `rd`, `rn`.
3463pub trait Fcvtl2Emitter<T0, T1> {
3464    fn fcvtl2(&mut self, rd: T0, rn: T1);
3465}
3466
3467/// Emits the `FCVTMS` instruction.
3468/// Assembly forms: `FCVTMS WD, SN`; `FCVTMS XD, SN`; `FCVTMS WD, DN`; `FCVTMS XD, DN` (and related forms).
3469/// Operands: `rd`, `rn`.
3470pub trait FcvtmsEmitter<T0, T1> {
3471    fn fcvtms(&mut self, rd: T0, rn: T1);
3472}
3473
3474/// Emits the `FCVTMU` instruction.
3475/// Assembly forms: `FCVTMU WD, SN`; `FCVTMU XD, SN`; `FCVTMU WD, DN`; `FCVTMU XD, DN` (and related forms).
3476/// Operands: `rd`, `rn`.
3477pub trait FcvtmuEmitter<T0, T1> {
3478    fn fcvtmu(&mut self, rd: T0, rn: T1);
3479}
3480
3481/// Emits the `FCVTN` instruction.
3482/// Assembly forms: `FCVTN VD.4S, VN.4H`; `FCVTN VD.2D, VN.2S`; `FCVTN VD.8B, VN.4H, VM.4H`; `FCVTN VD.16B, VN.8H, VM.8H` (and related forms).
3483/// Operands: `rd`, `rn`.
3484pub trait FcvtnEmitter<T0, T1> {
3485    fn fcvtn(&mut self, rd: T0, rn: T1);
3486}
3487
3488/// Emits the `FCVTN2` instruction.
3489/// Assembly forms: `FCVTN2 VD.4S, VN.8H`; `FCVTN2 VD.2D, VN.4S`; `FCVTN2 VX.16B, VN.4S, VM.4S`.
3490/// Operands: `rd_or_operand_1`, `rn`.
3491pub trait Fcvtn2Emitter<T0, T1> {
3492    fn fcvtn2(&mut self, rd_or_operand_1: T0, rn: T1);
3493}
3494
3495/// Emits the `FCVTNS` instruction.
3496/// Assembly forms: `FCVTNS WD, SN`; `FCVTNS XD, SN`; `FCVTNS WD, DN`; `FCVTNS XD, DN` (and related forms).
3497/// Operands: `rd`, `rn`.
3498pub trait FcvtnsEmitter<T0, T1> {
3499    fn fcvtns(&mut self, rd: T0, rn: T1);
3500}
3501
3502/// Emits the `FCVTNU` instruction.
3503/// Assembly forms: `FCVTNU WD, SN`; `FCVTNU XD, SN`; `FCVTNU WD, DN`; `FCVTNU XD, DN` (and related forms).
3504/// Operands: `rd`, `rn`.
3505pub trait FcvtnuEmitter<T0, T1> {
3506    fn fcvtnu(&mut self, rd: T0, rn: T1);
3507}
3508
3509/// Emits the `FCVTPS` instruction.
3510/// Assembly forms: `FCVTPS WD, SN`; `FCVTPS XD, SN`; `FCVTPS WD, DN`; `FCVTPS XD, DN` (and related forms).
3511/// Operands: `rd`, `rn`.
3512pub trait FcvtpsEmitter<T0, T1> {
3513    fn fcvtps(&mut self, rd: T0, rn: T1);
3514}
3515
3516/// Emits the `FCVTPU` instruction.
3517/// Assembly forms: `FCVTPU WD, SN`; `FCVTPU XD, SN`; `FCVTPU WD, DN`; `FCVTPU XD, DN` (and related forms).
3518/// Operands: `rd`, `rn`.
3519pub trait FcvtpuEmitter<T0, T1> {
3520    fn fcvtpu(&mut self, rd: T0, rn: T1);
3521}
3522
3523/// Emits the `FCVTXN` instruction.
3524/// Operands: `rd`, `rn`.
3525pub trait FcvtxnEmitter<T0, T1> {
3526    fn fcvtxn(&mut self, rd: T0, rn: T1);
3527}
3528
3529/// Emits the `FCVTXN2` instruction.
3530/// Operands: `rd`, `rn`.
3531pub trait Fcvtxn2Emitter<T0, T1> {
3532    fn fcvtxn2(&mut self, rd: T0, rn: T1);
3533}
3534
3535/// Emits the `FCVTZS` instruction.
3536/// Assembly forms: `FCVTZS WD, SN`; `FCVTZS XD, SN`; `FCVTZS WD, DN`; `FCVTZS XD, DN` (and related forms).
3537/// Operands: `rd`, `rn`.
3538pub trait FcvtzsEmitter<T0, T1> {
3539    fn fcvtzs(&mut self, rd: T0, rn: T1);
3540}
3541
3542/// Emits the `FCVTZS_3` instruction.
3543/// Assembly forms: `FCVTZS WD, SN`; `FCVTZS XD, SN`; `FCVTZS WD, DN`; `FCVTZS XD, DN` (and related forms).
3544/// Operands: `rd`, `rn`, `fbits`.
3545pub trait Fcvtzs3Emitter<T0, T1, T2> {
3546    fn fcvtzs_3(&mut self, rd: T0, rn: T1, fbits: T2);
3547}
3548
3549/// Emits the `FCVTZU` instruction.
3550/// Assembly forms: `FCVTZU WD, SN`; `FCVTZU XD, SN`; `FCVTZU WD, DN`; `FCVTZU XD, DN` (and related forms).
3551/// Operands: `rd`, `rn`.
3552pub trait FcvtzuEmitter<T0, T1> {
3553    fn fcvtzu(&mut self, rd: T0, rn: T1);
3554}
3555
3556/// Emits the `FCVTZU_3` instruction.
3557/// Assembly forms: `FCVTZU WD, SN`; `FCVTZU XD, SN`; `FCVTZU WD, DN`; `FCVTZU XD, DN` (and related forms).
3558/// Operands: `rd`, `rn`, `fbits`.
3559pub trait Fcvtzu3Emitter<T0, T1, T2> {
3560    fn fcvtzu_3(&mut self, rd: T0, rn: T1, fbits: T2);
3561}
3562
3563/// Emits the `FDIV` instruction.
3564/// Assembly forms: `FDIV SD, SN, SM`; `FDIV DD, DN, DM`; `FDIV VD.2S, VN.2S, VM.2S`; `FDIV VD.4S, VN.4S, VM.4S` (and related forms).
3565/// Operands: `rd`, `rn`, `rm`.
3566pub trait FdivEmitter<T0, T1, T2> {
3567    fn fdiv(&mut self, rd: T0, rn: T1, rm: T2);
3568}
3569
3570/// Emits the `FMADD` instruction.
3571/// Assembly forms: `FMADD SD, SN, SM, SA`; `FMADD DD, DN, DM, DA`; `FMADD HD, HN, HM, HA`.
3572/// Operands: `rd`, `rn`, `rm`, `operand_4`.
3573pub trait FmaddEmitter<T0, T1, T2, T3> {
3574    fn fmadd(&mut self, rd: T0, rn: T1, rm: T2, operand_4: T3);
3575}
3576
3577/// Emits the `FMAX` instruction.
3578/// Assembly forms: `FMAX SD, SN, SM`; `FMAX DD, DN, DM`; `FMAX VD.2S, VN.2S, VM.2S`; `FMAX VD.4S, VN.4S, VM.4S` (and related forms).
3579/// Operands: `rd`, `rn`, `rm`.
3580pub trait FmaxEmitter<T0, T1, T2> {
3581    fn fmax(&mut self, rd: T0, rn: T1, rm: T2);
3582}
3583
3584/// Emits the `FMAXNM` instruction.
3585/// Assembly forms: `FMAXNM SD, SN, SM`; `FMAXNM DD, DN, DM`; `FMAXNM VD.2S, VN.2S, VM.2S`; `FMAXNM VD.2D, VN.2D, VM.2D` (and related forms).
3586/// Operands: `rd`, `rn`, `rm`.
3587pub trait FmaxnmEmitter<T0, T1, T2> {
3588    fn fmaxnm(&mut self, rd: T0, rn: T1, rm: T2);
3589}
3590
3591/// Emits the `FMAXNMP` instruction.
3592/// Assembly forms: `FMAXNMP SD, VN.2S`; `FMAXNMP DD, VN.2D`; `FMAXNMP VD.2S, VN.2S, VM.2S`; `FMAXNMP VD.4S, VN.4S, VM.4S` (and related forms).
3593/// Operands: `rd`, `rn`, `rm`.
3594pub trait FmaxnmpEmitter<T0, T1, T2> {
3595    fn fmaxnmp(&mut self, rd: T0, rn: T1, rm: T2);
3596}
3597
3598/// Emits the `FMAXNMP_2` instruction.
3599/// Assembly forms: `FMAXNMP SD, VN.2S`; `FMAXNMP DD, VN.2D`; `FMAXNMP VD.2S, VN.2S, VM.2S`; `FMAXNMP VD.4S, VN.4S, VM.4S` (and related forms).
3600/// Operands: `rd`, `rn`.
3601pub trait Fmaxnmp2Emitter<T0, T1> {
3602    fn fmaxnmp_2(&mut self, rd: T0, rn: T1);
3603}
3604
3605/// Emits the `FMAXNMV` instruction.
3606/// Assembly forms: `FMAXNMV SD, VN.4S`; `FMAXNMV HD, VN.4H`; `FMAXNMV HD, VN.8H`.
3607/// Operands: `rd`, `rn`.
3608pub trait FmaxnmvEmitter<T0, T1> {
3609    fn fmaxnmv(&mut self, rd: T0, rn: T1);
3610}
3611
3612/// Emits the `FMAXP` instruction.
3613/// Assembly forms: `FMAXP SD, VN.2S`; `FMAXP DD, VN.2D`; `FMAXP VD.2S, VN.2S, VM.2S`; `FMAXP VD.4S, VN.4S, VM.4S` (and related forms).
3614/// Operands: `rd`, `rn`, `rm`.
3615pub trait FmaxpEmitter<T0, T1, T2> {
3616    fn fmaxp(&mut self, rd: T0, rn: T1, rm: T2);
3617}
3618
3619/// Emits the `FMAXP_2` instruction.
3620/// Assembly forms: `FMAXP SD, VN.2S`; `FMAXP DD, VN.2D`; `FMAXP VD.2S, VN.2S, VM.2S`; `FMAXP VD.4S, VN.4S, VM.4S` (and related forms).
3621/// Operands: `rd`, `rn`.
3622pub trait Fmaxp2Emitter<T0, T1> {
3623    fn fmaxp_2(&mut self, rd: T0, rn: T1);
3624}
3625
3626/// Emits the `FMAXV` instruction.
3627/// Assembly forms: `FMAXV SD, VN.4S`; `FMAXV HD, VN.4H`; `FMAXV HD, VN.8H`.
3628/// Operands: `rd`, `rn`.
3629pub trait FmaxvEmitter<T0, T1> {
3630    fn fmaxv(&mut self, rd: T0, rn: T1);
3631}
3632
3633/// Emits the `FMIN` instruction.
3634/// Assembly forms: `FMIN SD, SN, SM`; `FMIN DD, DN, DM`; `FMIN VD.2S, VN.2S, VM.2S`; `FMIN VD.4S, VN.4S, VM.4S` (and related forms).
3635/// Operands: `rd`, `rn`, `rm`.
3636pub trait FminEmitter<T0, T1, T2> {
3637    fn fmin(&mut self, rd: T0, rn: T1, rm: T2);
3638}
3639
3640/// Emits the `FMINNM` instruction.
3641/// Assembly forms: `FMINNM SD, SN, SM`; `FMINNM DD, DN, DM`; `FMINNM VD.2S, VN.2S, VM.2S`; `FMINNM VD.2D, VN.2D, VM.2D` (and related forms).
3642/// Operands: `rd`, `rn`, `rm`.
3643pub trait FminnmEmitter<T0, T1, T2> {
3644    fn fminnm(&mut self, rd: T0, rn: T1, rm: T2);
3645}
3646
3647/// Emits the `FMINNMV` instruction.
3648/// Assembly forms: `FMINNMV SD, VN.4S`; `FMINNMV HD, VN.4H`; `FMINNMV HD, VN.8H`.
3649/// Operands: `rd`, `rn`.
3650pub trait FminnmvEmitter<T0, T1> {
3651    fn fminnmv(&mut self, rd: T0, rn: T1);
3652}
3653
3654/// Emits the `FMINNMP` instruction.
3655/// Assembly forms: `FMINNMP SD, VN.2S`; `FMINNMP DD, VN.2D`; `FMINNMP VD.2S, VN.2S, VM.2S`; `FMINNMP VD.4S, VN.4S, VM.4S` (and related forms).
3656/// Operands: `rd`, `rn`, `rm`.
3657pub trait FminnmpEmitter<T0, T1, T2> {
3658    fn fminnmp(&mut self, rd: T0, rn: T1, rm: T2);
3659}
3660
3661/// Emits the `FMINNMP_2` instruction.
3662/// Assembly forms: `FMINNMP SD, VN.2S`; `FMINNMP DD, VN.2D`; `FMINNMP VD.2S, VN.2S, VM.2S`; `FMINNMP VD.4S, VN.4S, VM.4S` (and related forms).
3663/// Operands: `rd`, `rn`.
3664pub trait Fminnmp2Emitter<T0, T1> {
3665    fn fminnmp_2(&mut self, rd: T0, rn: T1);
3666}
3667
3668/// Emits the `FMINP` instruction.
3669/// Assembly forms: `FMINP SD, VN.2S`; `FMINP DD, VN.2D`; `FMINP VD.2S, VN.2S, VM.2S`; `FMINP VD.4S, VN.4S, VM.4S` (and related forms).
3670/// Operands: `rd`, `rn`.
3671pub trait FminpEmitter<T0, T1> {
3672    fn fminp(&mut self, rd: T0, rn: T1);
3673}
3674
3675/// Emits the `FMINP_3` instruction.
3676/// Assembly forms: `FMINP SD, VN.2S`; `FMINP DD, VN.2D`; `FMINP VD.2S, VN.2S, VM.2S`; `FMINP VD.4S, VN.4S, VM.4S` (and related forms).
3677/// Operands: `rd`, `rn`, `rm`.
3678pub trait Fminp3Emitter<T0, T1, T2> {
3679    fn fminp_3(&mut self, rd: T0, rn: T1, rm: T2);
3680}
3681
3682/// Emits the `FMINV` instruction.
3683/// Assembly forms: `FMINV SD, VN.4S`; `FMINV HD, VN.4H`; `FMINV HD, VN.8H`.
3684/// Operands: `rd`, `rn`.
3685pub trait FminvEmitter<T0, T1> {
3686    fn fminv(&mut self, rd: T0, rn: T1);
3687}
3688
3689/// Emits the `FMLA` instruction.
3690/// Assembly forms: `FMLA SX, SN, VM.S[#IDX]`; `FMLA DX, DN, VM.D[#IDX]`; `FMLA VX.2S, VN.2S, VM.2S`; `FMLA VX.4S, VN.4S, VM.4S` (and related forms).
3691/// Operands: `operand_1`, `rn`, `rm`.
3692pub trait FmlaEmitter<T0, T1, T2> {
3693    fn fmla(&mut self, operand_1: T0, rn: T1, rm: T2);
3694}
3695
3696/// Emits the `FMLS` instruction.
3697/// Assembly forms: `FMLS SX, SN, VM.S[#IDX]`; `FMLS DX, DN, VM.D[#IDX]`; `FMLS VX.2S, VN.2S, VM.2S`; `FMLS VX.4S, VN.4S, VM.4S` (and related forms).
3698/// Operands: `operand_1`, `rn`, `rm`.
3699pub trait FmlsEmitter<T0, T1, T2> {
3700    fn fmls(&mut self, operand_1: T0, rn: T1, rm: T2);
3701}
3702
3703/// Emits the `FMOV` instruction.
3704/// Assembly forms: `FMOV WD, SN`; `FMOV XD, DN`; `FMOV XD, VN.D[#1]`; `FMOV SD, WN` (and related forms).
3705/// Operands: `rd`, `rn_or_fimm`.
3706pub trait FmovEmitter<T0, T1> {
3707    fn fmov(&mut self, rd: T0, rn_or_fimm: T1);
3708}
3709
3710/// Emits the `FMSUB` instruction.
3711/// Assembly forms: `FMSUB SD, SN, SM, SA`; `FMSUB DD, DN, DM, DA`; `FMSUB HD, HN, HM, HA`.
3712/// Operands: `rd`, `rn`, `rm`, `operand_4`.
3713pub trait FmsubEmitter<T0, T1, T2, T3> {
3714    fn fmsub(&mut self, rd: T0, rn: T1, rm: T2, operand_4: T3);
3715}
3716
3717/// Emits the `FMUL` instruction.
3718/// Assembly forms: `FMUL SD, SN, SM`; `FMUL DD, DN, DM`; `FMUL SD, SN, VM.S[#IDX]`; `FMUL DD, DN, VM.D[#IDX]` (and related forms).
3719/// Operands: `rd`, `rn`, `rm`.
3720pub trait FmulEmitter<T0, T1, T2> {
3721    fn fmul(&mut self, rd: T0, rn: T1, rm: T2);
3722}
3723
3724/// Emits the `FMULX` instruction.
3725/// Assembly forms: `FMULX SD, SN, SM`; `FMULX DD, DN, DM`; `FMULX SD, SN, VM.S[#IDX]`; `FMULX DD, DN, VM.D[#IDX]` (and related forms).
3726/// Operands: `rd`, `rn`, `rm`.
3727pub trait FmulxEmitter<T0, T1, T2> {
3728    fn fmulx(&mut self, rd: T0, rn: T1, rm: T2);
3729}
3730
3731/// Emits the `FNEG` instruction.
3732/// Assembly forms: `FNEG SD, SN`; `FNEG DD, DN`; `FNEG VD.2S, VN.2S`; `FNEG VD.4S, VN.4S` (and related forms).
3733/// Operands: `rd`, `rn`.
3734pub trait FnegEmitter<T0, T1> {
3735    fn fneg(&mut self, rd: T0, rn: T1);
3736}
3737
3738/// Emits the `FNMADD` instruction.
3739/// Assembly forms: `FNMADD SD, SN, SM, SA`; `FNMADD DD, DN, DM, DA`; `FNMADD HD, HN, HM, HA`.
3740/// Operands: `rd`, `rn`, `rm`, `operand_4`.
3741pub trait FnmaddEmitter<T0, T1, T2, T3> {
3742    fn fnmadd(&mut self, rd: T0, rn: T1, rm: T2, operand_4: T3);
3743}
3744
3745/// Emits the `FNMSUB` instruction.
3746/// Assembly forms: `FNMSUB SD, SN, SM, SA`; `FNMSUB DD, DN, DM, DA`; `FNMSUB HD, HN, HM, HA`.
3747/// Operands: `rd`, `rn`, `rm`, `operand_4`.
3748pub trait FnmsubEmitter<T0, T1, T2, T3> {
3749    fn fnmsub(&mut self, rd: T0, rn: T1, rm: T2, operand_4: T3);
3750}
3751
3752/// Emits the `FNMUL` instruction.
3753/// Assembly forms: `FNMUL SD, SN, SM`; `FNMUL DD, DN, DM`; `FNMUL HD, HN, HM`.
3754/// Operands: `rd`, `rn`, `rm`.
3755pub trait FnmulEmitter<T0, T1, T2> {
3756    fn fnmul(&mut self, rd: T0, rn: T1, rm: T2);
3757}
3758
3759/// Emits the `FRECPE` instruction.
3760/// Assembly forms: `FRECPE SD, SN`; `FRECPE DD, DN`; `FRECPE VD.2S, VN.2S`; `FRECPE VD.4S, VN.4S` (and related forms).
3761/// Operands: `rd`, `rn`.
3762pub trait FrecpeEmitter<T0, T1> {
3763    fn frecpe(&mut self, rd: T0, rn: T1);
3764}
3765
3766/// Emits the `FRECPS` instruction.
3767/// Assembly forms: `FRECPS SD, SN, SM`; `FRECPS DD, DN, DM`; `FRECPS VD.2S, VN.2S, VM.2S`; `FRECPS VD.4S, VN.4S, VM.4S` (and related forms).
3768/// Operands: `rd`, `rn`, `rm`.
3769pub trait FrecpsEmitter<T0, T1, T2> {
3770    fn frecps(&mut self, rd: T0, rn: T1, rm: T2);
3771}
3772
3773/// Emits the `FRECPX` instruction.
3774/// Assembly forms: `FRECPX SD, SN, SM`; `FRECPX DD, DN, DM`; `FRECPX HD, HN, HM`.
3775/// Operands: `rd`, `rn`.
3776pub trait FrecpxEmitter<T0, T1> {
3777    fn frecpx(&mut self, rd: T0, rn: T1);
3778}
3779
3780/// Emits the `FRINT32X` instruction.
3781/// Assembly forms: `FRINT32X SD, SN`; `FRINT32X DD, DN`; `FRINT32X VD.2S, VN.2S`; `FRINT32X VD.4S, VN.4S` (and related forms).
3782/// Operands: `rd`, `rn`.
3783pub trait Frint32xEmitter<T0, T1> {
3784    fn frint32x(&mut self, rd: T0, rn: T1);
3785}
3786
3787/// Emits the `FRINT32Z` instruction.
3788/// Assembly forms: `FRINT32Z SD, SN`; `FRINT32Z DD, DN`; `FRINT32Z VD.2S, VN.2S`; `FRINT32Z VD.4S, VN.4S` (and related forms).
3789/// Operands: `rd`, `rn`.
3790pub trait Frint32zEmitter<T0, T1> {
3791    fn frint32z(&mut self, rd: T0, rn: T1);
3792}
3793
3794/// Emits the `FRINT64X` instruction.
3795/// Assembly forms: `FRINT64X SD, SN`; `FRINT64X DD, DN`; `FRINT64X VD.2S, VN.2S`; `FRINT64X VD.4S, VN.4S` (and related forms).
3796/// Operands: `rd`, `rn`.
3797pub trait Frint64xEmitter<T0, T1> {
3798    fn frint64x(&mut self, rd: T0, rn: T1);
3799}
3800
3801/// Emits the `FRINT64Z` instruction.
3802/// Assembly forms: `FRINT64Z SD, SN`; `FRINT64Z DD, DN`; `FRINT64Z VD.2S, VN.2S`; `FRINT64Z VD.4S, VN.4S` (and related forms).
3803/// Operands: `rd`, `rn`.
3804pub trait Frint64zEmitter<T0, T1> {
3805    fn frint64z(&mut self, rd: T0, rn: T1);
3806}
3807
3808/// Emits the `FRINTA` instruction.
3809/// Assembly forms: `FRINTA SD, SN`; `FRINTA DD, DN`; `FRINTA VD.2S, VN.2S`; `FRINTA VD.4S, VN.4S` (and related forms).
3810/// Operands: `rd`, `rn`.
3811pub trait FrintaEmitter<T0, T1> {
3812    fn frinta(&mut self, rd: T0, rn: T1);
3813}
3814
3815/// Emits the `FRINTI` instruction.
3816/// Assembly forms: `FRINTI SD, SN`; `FRINTI DD, DN`; `FRINTI VD.2S, VN.2S`; `FRINTI VD.4S, VN.4S` (and related forms).
3817/// Operands: `rd`, `rn`.
3818pub trait FrintiEmitter<T0, T1> {
3819    fn frinti(&mut self, rd: T0, rn: T1);
3820}
3821
3822/// Emits the `FRINTM` instruction.
3823/// Assembly forms: `FRINTM SD, SN`; `FRINTM DD, DN`; `FRINTM VD.2S, VN.2S`; `FRINTM VD.4S, VN.4S` (and related forms).
3824/// Operands: `rd`, `rn`.
3825pub trait FrintmEmitter<T0, T1> {
3826    fn frintm(&mut self, rd: T0, rn: T1);
3827}
3828
3829/// Emits the `FRINTN` instruction.
3830/// Assembly forms: `FRINTN SD, SN`; `FRINTN DD, DN`; `FRINTN VD.2S, VN.2S`; `FRINTN VD.4S, VN.4S` (and related forms).
3831/// Operands: `rd`, `rn`.
3832pub trait FrintnEmitter<T0, T1> {
3833    fn frintn(&mut self, rd: T0, rn: T1);
3834}
3835
3836/// Emits the `FRINTP` instruction.
3837/// Assembly forms: `FRINTP SD, SN`; `FRINTP DD, DN`; `FRINTP VD.2S, VN.2S`; `FRINTP VD.4S, VN.4S` (and related forms).
3838/// Operands: `rd`, `rn`.
3839pub trait FrintpEmitter<T0, T1> {
3840    fn frintp(&mut self, rd: T0, rn: T1);
3841}
3842
3843/// Emits the `FRINTX` instruction.
3844/// Assembly forms: `FRINTX SD, SN`; `FRINTX DD, DN`; `FRINTX VD.2S, VN.2S`; `FRINTX VD.4S, VN.4S` (and related forms).
3845/// Operands: `rd`, `rn`.
3846pub trait FrintxEmitter<T0, T1> {
3847    fn frintx(&mut self, rd: T0, rn: T1);
3848}
3849
3850/// Emits the `FRINTZ` instruction.
3851/// Assembly forms: `FRINTZ SD, SN`; `FRINTZ DD, DN`; `FRINTZ VD.2S, VN.2S`; `FRINTZ VD.4S, VN.4S` (and related forms).
3852/// Operands: `rd`, `rn`.
3853pub trait FrintzEmitter<T0, T1> {
3854    fn frintz(&mut self, rd: T0, rn: T1);
3855}
3856
3857/// Emits the `FRSQRTE` instruction.
3858/// Assembly forms: `FRSQRTE SD, SN`; `FRSQRTE DD, DN`; `FRSQRTE VD.2S, VN.2S`; `FRSQRTE VD.4S, VN.4S` (and related forms).
3859/// Operands: `rd`, `rn`.
3860pub trait FrsqrteEmitter<T0, T1> {
3861    fn frsqrte(&mut self, rd: T0, rn: T1);
3862}
3863
3864/// Emits the `FRSQRTS` instruction.
3865/// Assembly forms: `FRSQRTS SD, SN, SM`; `FRSQRTS DD, DN, DM`; `FRSQRTS VD.2S, VN.2S, VM.2S`; `FRSQRTS VD.4S, VN.4S, VM.4S` (and related forms).
3866/// Operands: `rd`, `rn`, `rm`.
3867pub trait FrsqrtsEmitter<T0, T1, T2> {
3868    fn frsqrts(&mut self, rd: T0, rn: T1, rm: T2);
3869}
3870
3871/// Emits the `FSQRT` instruction.
3872/// Assembly forms: `FSQRT SD, SN`; `FSQRT DD, DN`; `FSQRT VD.2S, VN.2S`; `FSQRT VD.4S, VN.4S` (and related forms).
3873/// Operands: `rd`, `rn`.
3874pub trait FsqrtEmitter<T0, T1> {
3875    fn fsqrt(&mut self, rd: T0, rn: T1);
3876}
3877
3878/// Emits the `FSUB` instruction.
3879/// Assembly forms: `FSUB SD, SN, SM`; `FSUB DD, DN, DM`; `FSUB VD.2S, VN.2S, VM.2S`; `FSUB VD.4S, VN.4S, VM.4S` (and related forms).
3880/// Operands: `rd`, `rn`, `rm`.
3881pub trait FsubEmitter<T0, T1, T2> {
3882    fn fsub(&mut self, rd: T0, rn: T1, rm: T2);
3883}
3884
3885/// Emits the `INS` instruction.
3886/// Assembly forms: `INS|MOV VD.B[#IDX], WN`; `INS|MOV VD.H[#IDX], WN`; `INS|MOV VD.S[#IDX], WN`; `INS|MOV VD.D[#IDX], XN` (and related forms).
3887/// Operands: `rd`, `rn`.
3888pub trait InsEmitter<T0, T1> {
3889    fn ins(&mut self, rd: T0, rn: T1);
3890}
3891
3892/// Emits the `LD1` instruction.
3893/// Assembly forms: `LD1 VX.B[#IDX], [XN|SP]`; `LD1 VX.H[#IDX], [XN|SP]`; `LD1 VX.S[#IDX], [XN|SP]`; `LD1 VX.D[#IDX], [XN|SP]` (and related forms).
3894/// Operands: `idx_or_operand_1`, `addr`.
3895pub trait Ld1Emitter<T0, T1> {
3896    fn ld1(&mut self, idx_or_operand_1: T0, addr: T1);
3897}
3898
3899/// Emits the `LD1_3` instruction.
3900/// Assembly forms: `LD1 VX.B[#IDX], [XN|SP]`; `LD1 VX.H[#IDX], [XN|SP]`; `LD1 VX.S[#IDX], [XN|SP]`; `LD1 VX.D[#IDX], [XN|SP]` (and related forms).
3901/// Operands: `rd`, `rn`, `addr`.
3902pub trait Ld13Emitter<T0, T1, T2> {
3903    fn ld1_3(&mut self, rd: T0, rn: T1, addr: T2);
3904}
3905
3906/// Emits the `LD1_4` instruction.
3907/// Assembly forms: `LD1 VX.B[#IDX], [XN|SP]`; `LD1 VX.H[#IDX], [XN|SP]`; `LD1 VX.S[#IDX], [XN|SP]`; `LD1 VX.D[#IDX], [XN|SP]` (and related forms).
3908/// Operands: `rd`, `rn`, `rm1`, `addr`.
3909pub trait Ld14Emitter<T0, T1, T2, T3> {
3910    fn ld1_4(&mut self, rd: T0, rn: T1, rm1: T2, addr: T3);
3911}
3912
3913/// Emits the `LD1_5` instruction.
3914/// Assembly forms: `LD1 VX.B[#IDX], [XN|SP]`; `LD1 VX.H[#IDX], [XN|SP]`; `LD1 VX.S[#IDX], [XN|SP]`; `LD1 VX.D[#IDX], [XN|SP]` (and related forms).
3915/// Operands: `rd`, `rn`, `rm1`, `rm2`, `addr`.
3916pub trait Ld15Emitter<T0, T1, T2, T3, T4> {
3917    fn ld1_5(&mut self, rd: T0, rn: T1, rm1: T2, rm2: T3, addr: T4);
3918}
3919
3920/// Emits the `LD1R` instruction.
3921/// Assembly forms: `LD1R 1X{VD.T}, [XN|SP]`; `LD1R 1X{VD.T}, [XN|SP]`; `LD1R 1X{VD.T}, [XN|SP, XM]@`; `LD1R 1X{VD.T}, [XN|SP, XM]@` (and related forms).
3922/// Operands: `operand_1`, `addr`.
3923pub trait Ld1rEmitter<T0, T1> {
3924    fn ld1r(&mut self, operand_1: T0, addr: T1);
3925}
3926
3927/// Emits the `LD2` instruction.
3928/// Assembly forms: `LD2 2X{VX.B}[#IDX], [XN|SP]`; `LD2 2X{VX.H}[#IDX], [XN|SP]`; `LD2 2X{VX.S}[#IDX], [XN|SP]`; `LD2 2X{VX.D}[#IDX], [XN|SP]` (and related forms).
3929/// Operands: `rd`, `rn`, `addr`.
3930pub trait Ld2Emitter<T0, T1, T2> {
3931    fn ld2(&mut self, rd: T0, rn: T1, addr: T2);
3932}
3933
3934/// Emits the `LD2R` instruction.
3935/// Assembly forms: `LD2R 2X{VD.T}, [XN|SP]`; `LD2R 2X{VD.T}, [XN|SP]`; `LD2R 2X{VD.T}, [XN|SP, XM]@`; `LD2R 2X{VD.T}, [XN|SP, XM]@` (and related forms).
3936/// Operands: `rd`, `rn`, `addr`.
3937pub trait Ld2rEmitter<T0, T1, T2> {
3938    fn ld2r(&mut self, rd: T0, rn: T1, addr: T2);
3939}
3940
3941/// Emits the `LD3` instruction.
3942/// Assembly forms: `LD3 3X{VX.B}[#IDX], [XN|SP]`; `LD3 3X{VX.H}[#IDX], [XN|SP]`; `LD3 3X{VX.S}[#IDX], [XN|SP]`; `LD3 3X{VX.D}[#IDX], [XN|SP]` (and related forms).
3943/// Operands: `rd`, `rn`, `rm1`, `addr`.
3944pub trait Ld3Emitter<T0, T1, T2, T3> {
3945    fn ld3(&mut self, rd: T0, rn: T1, rm1: T2, addr: T3);
3946}
3947
3948/// Emits the `LD3R` instruction.
3949/// Assembly forms: `LD3R 3X{VD.T}, [XN|SP]`; `LD3R 3X{VD.T}, [XN|SP]`; `LD3R 3X{VD.T}, [XN|SP, XM]@`; `LD3R 3X{VD.T}, [XN|SP, XM]@` (and related forms).
3950/// Operands: `rd`, `rn`, `rm1`, `addr`.
3951pub trait Ld3rEmitter<T0, T1, T2, T3> {
3952    fn ld3r(&mut self, rd: T0, rn: T1, rm1: T2, addr: T3);
3953}
3954
3955/// Emits the `LD4` instruction.
3956/// Assembly forms: `LD4 4X{VX.B}[#IDX], [XN|SP]`; `LD4 4X{VX.H}[#IDX], [XN|SP]`; `LD4 4X{VX.S}[#IDX], [XN|SP]`; `LD4 4X{VX.D}[#IDX], [XN|SP]` (and related forms).
3957/// Operands: `rd`, `rn`, `rm1`, `rm2`, `addr`.
3958pub trait Ld4Emitter<T0, T1, T2, T3, T4> {
3959    fn ld4(&mut self, rd: T0, rn: T1, rm1: T2, rm2: T3, addr: T4);
3960}
3961
3962/// Emits the `LD4R` instruction.
3963/// Assembly forms: `LD4R 4X{VD.T}, [XN|SP]`; `LD4R 4X{VD.T}, [XN|SP]`; `LD4R 4X{VD.T}, [XN|SP, XM]@`; `LD4R 4X{VD.T}, [XN|SP, XM]@` (and related forms).
3964/// Operands: `rd`, `rn`, `rm1`, `rm2`, `addr`.
3965pub trait Ld4rEmitter<T0, T1, T2, T3, T4> {
3966    fn ld4r(&mut self, rd: T0, rn: T1, rm1: T2, rm2: T3, addr: T4);
3967}
3968
3969/// Emits the `MLA` instruction.
3970/// Assembly forms: `MLA VX.T, VN.T, VM.T`; `MLA VX.T, VN.T, VM.T`; `MLA VX.4H, VN.4H, VM.H[#IDX]`; `MLA VX.8H, VN.8H, VM.H[#IDX]` (and related forms).
3971/// Operands: `operand_1`, `rn`, `rm`.
3972pub trait MlaEmitter<T0, T1, T2> {
3973    fn mla(&mut self, operand_1: T0, rn: T1, rm: T2);
3974}
3975
3976/// Emits the `MLS` instruction.
3977/// Assembly forms: `MLS VX.T, VN.T, VM.T`; `MLS VX.T, VN.T, VM.T`; `MLS VX.4H, VN.4H, VM.H[#IDX]`; `MLS VX.8H, VN.8H, VM.H[#IDX]` (and related forms).
3978/// Operands: `operand_1`, `rn`, `rm`.
3979pub trait MlsEmitter<T0, T1, T2> {
3980    fn mls(&mut self, operand_1: T0, rn: T1, rm: T2);
3981}
3982
3983/// Emits the `MOVI` instruction.
3984/// Assembly forms: `MOVI DD, #IMM, {LSL #N}`; `MOVI VD.T, #IMM, {LSL #N}`; `MOVI VD.T, #IMM, {LSL #N}`.
3985/// Operands: `rd`, `imm`.
3986pub trait MoviEmitter<T0, T1> {
3987    fn movi(&mut self, rd: T0, imm: T1);
3988}
3989
3990/// Emits the `MOVI_3` instruction.
3991/// Assembly forms: `MOVI DD, #IMM, {LSL #N}`; `MOVI VD.T, #IMM, {LSL #N}`; `MOVI VD.T, #IMM, {LSL #N}`.
3992/// Operands: `rd`, `imm`, `shift`.
3993pub trait Movi3Emitter<T0, T1, T2> {
3994    fn movi_3(&mut self, rd: T0, imm: T1, shift: T2);
3995}
3996
3997/// Emits the `MVNI` instruction.
3998/// Assembly forms: `MVNI DD, #IMM, {LSL #N}`; `MVNI VD.T, #IMM, {LSL #N}`; `MVNI VD.T, #IMM, {LSL #N}`.
3999/// Operands: `rd`, `imm`.
4000pub trait MvniEmitter<T0, T1> {
4001    fn mvni(&mut self, rd: T0, imm: T1);
4002}
4003
4004/// Emits the `MVNI_3` instruction.
4005/// Assembly forms: `MVNI DD, #IMM, {LSL #N}`; `MVNI VD.T, #IMM, {LSL #N}`; `MVNI VD.T, #IMM, {LSL #N}`.
4006/// Operands: `rd`, `imm`, `shift`.
4007pub trait Mvni3Emitter<T0, T1, T2> {
4008    fn mvni_3(&mut self, rd: T0, imm: T1, shift: T2);
4009}
4010
4011/// Emits the `NOT_` instruction.
4012/// Assembly forms: `NOT|MVN VD.8B, VN.8B`; `NOT|MVN VD.16B, VN.16B`.
4013/// Operands: `rd`, `rn`.
4014pub trait NotEmitter<T0, T1> {
4015    fn not_(&mut self, rd: T0, rn: T1);
4016}
4017
4018/// Emits the `ORR_2` instruction.
4019/// Assembly forms: `ORR WD, WN, WM, {SOP #N}`; `ORR XD, XN, XM, {SOP #N}`; `ORR WD|WSP, WN, #LOG_IMM`; `ORR XD|SP, XN, #LOG_IMM` (and related forms).
4020/// Operands: `rd`, `rn_or_imm`.
4021pub trait Orr2Emitter<T0, T1> {
4022    fn orr_2(&mut self, rd: T0, rn_or_imm: T1);
4023}
4024
4025/// Emits the `PMUL` instruction.
4026/// Assembly forms: `PMUL VD.8B, VN.8B, VM.8B`; `PMUL VD.16B, VN.16B, VM.16B`.
4027/// Operands: `rd`, `rn`, `rm`.
4028pub trait PmulEmitter<T0, T1, T2> {
4029    fn pmul(&mut self, rd: T0, rn: T1, rm: T2);
4030}
4031
4032/// Emits the `PMULL` instruction.
4033/// Assembly forms: `PMULL VD.8H, VN.8B, VM.8B`; `PMULL VD.1Q, VN.1D, VM.1D`.
4034/// Operands: `rd`, `rn`, `rm`.
4035pub trait PmullEmitter<T0, T1, T2> {
4036    fn pmull(&mut self, rd: T0, rn: T1, rm: T2);
4037}
4038
4039/// Emits the `PMULL2` instruction.
4040/// Assembly forms: `PMULL2 VD.8H, VN.16B, VM.16B`; `PMULL2 VD.1Q, VN.2D, VM.2D`.
4041/// Operands: `rd`, `rn`, `rm`.
4042pub trait Pmull2Emitter<T0, T1, T2> {
4043    fn pmull2(&mut self, rd: T0, rn: T1, rm: T2);
4044}
4045
4046/// Emits the `RADDHN` instruction.
4047/// Assembly forms: `RADDHN VD.TA, VN.TB, VM.TB`.
4048/// Operands: `rd`, `rn`, `rm`.
4049pub trait RaddhnEmitter<T0, T1, T2> {
4050    fn raddhn(&mut self, rd: T0, rn: T1, rm: T2);
4051}
4052
4053/// Emits the `RADDHN2` instruction.
4054/// Assembly forms: `RADDHN2 VX.TA, VN.TB, VM.TB`.
4055/// Operands: `operand_1`, `rn`, `rm`.
4056pub trait Raddhn2Emitter<T0, T1, T2> {
4057    fn raddhn2(&mut self, operand_1: T0, rn: T1, rm: T2);
4058}
4059
4060/// Emits the `RSHRN` instruction.
4061/// Assembly forms: `RSHRN VD.TA, VN.TB, #N`.
4062/// Operands: `rd`, `rn`, `shift`.
4063pub trait RshrnEmitter<T0, T1, T2> {
4064    fn rshrn(&mut self, rd: T0, rn: T1, shift: T2);
4065}
4066
4067/// Emits the `RSHRN2` instruction.
4068/// Assembly forms: `RSHRN2 VX.TA, VN.TB, #N`.
4069/// Operands: `operand_1`, `rn`, `shift`.
4070pub trait Rshrn2Emitter<T0, T1, T2> {
4071    fn rshrn2(&mut self, operand_1: T0, rn: T1, shift: T2);
4072}
4073
4074/// Emits the `RSUBHN` instruction.
4075/// Assembly forms: `RSUBHN VD.TA, VN.TB, VM.TB`.
4076/// Operands: `rd`, `rn`, `rm`.
4077pub trait RsubhnEmitter<T0, T1, T2> {
4078    fn rsubhn(&mut self, rd: T0, rn: T1, rm: T2);
4079}
4080
4081/// Emits the `RSUBHN2` instruction.
4082/// Assembly forms: `RSUBHN2 VX.TA, VN.TB, VM.TB`.
4083/// Operands: `operand_1`, `rn`, `rm`.
4084pub trait Rsubhn2Emitter<T0, T1, T2> {
4085    fn rsubhn2(&mut self, operand_1: T0, rn: T1, rm: T2);
4086}
4087
4088/// Emits the `SABA` instruction.
4089/// Assembly forms: `SABA VX.T, VN.T, VM.T`; `SABA VX.T, VN.T, VM.T`.
4090/// Operands: `operand_1`, `rn`, `rm`.
4091pub trait SabaEmitter<T0, T1, T2> {
4092    fn saba(&mut self, operand_1: T0, rn: T1, rm: T2);
4093}
4094
4095/// Emits the `SABAL` instruction.
4096/// Assembly forms: `SABAL VX.TA, VN.TB, VM.TB`.
4097/// Operands: `operand_1`, `rn`, `rm`.
4098pub trait SabalEmitter<T0, T1, T2> {
4099    fn sabal(&mut self, operand_1: T0, rn: T1, rm: T2);
4100}
4101
4102/// Emits the `SABAL2` instruction.
4103/// Assembly forms: `SABAL2 VX.TA, VN.TB, VM.TB`.
4104/// Operands: `operand_1`, `rn`, `rm`.
4105pub trait Sabal2Emitter<T0, T1, T2> {
4106    fn sabal2(&mut self, operand_1: T0, rn: T1, rm: T2);
4107}
4108
4109/// Emits the `SABD` instruction.
4110/// Assembly forms: `SABD VD.T, VN.T, VM.T`; `SABD VD.T, VN.T, VM.T`.
4111/// Operands: `rd`, `rn`, `rm`.
4112pub trait SabdEmitter<T0, T1, T2> {
4113    fn sabd(&mut self, rd: T0, rn: T1, rm: T2);
4114}
4115
4116/// Emits the `SABDL` instruction.
4117/// Assembly forms: `SABDL VD.TA, VN.TB, VM.TB`.
4118/// Operands: `rd`, `rn`, `rm`.
4119pub trait SabdlEmitter<T0, T1, T2> {
4120    fn sabdl(&mut self, rd: T0, rn: T1, rm: T2);
4121}
4122
4123/// Emits the `SABDL2` instruction.
4124/// Assembly forms: `SABDL2 VD.TA, VN.TB, VM.TB`.
4125/// Operands: `rd`, `rn`, `rm`.
4126pub trait Sabdl2Emitter<T0, T1, T2> {
4127    fn sabdl2(&mut self, rd: T0, rn: T1, rm: T2);
4128}
4129
4130/// Emits the `SADALP` instruction.
4131/// Assembly forms: `SADALP VX.TA, VN.TB`; `SADALP VX.TA, VN.TB`.
4132/// Operands: `operand_1`, `rn`.
4133pub trait SadalpEmitter<T0, T1> {
4134    fn sadalp(&mut self, operand_1: T0, rn: T1);
4135}
4136
4137/// Emits the `SADDL` instruction.
4138/// Assembly forms: `SADDL VD.TA, VN.TB, VM.TB`.
4139/// Operands: `rd`, `rn`, `rm`.
4140pub trait SaddlEmitter<T0, T1, T2> {
4141    fn saddl(&mut self, rd: T0, rn: T1, rm: T2);
4142}
4143
4144/// Emits the `SADDL2` instruction.
4145/// Assembly forms: `SADDL2 VD.TA, VN.TB, VM.TB`.
4146/// Operands: `rd`, `rn`, `rm`.
4147pub trait Saddl2Emitter<T0, T1, T2> {
4148    fn saddl2(&mut self, rd: T0, rn: T1, rm: T2);
4149}
4150
4151/// Emits the `SADDLP` instruction.
4152/// Assembly forms: `SADDLP VD.TA, VN.TB`; `SADDLP VD.TA, VN.TB`.
4153/// Operands: `rd`, `rn`.
4154pub trait SaddlpEmitter<T0, T1> {
4155    fn saddlp(&mut self, rd: T0, rn: T1);
4156}
4157
4158/// Emits the `SADDLV` instruction.
4159/// Assembly forms: `SADDLV HD, VN.8B`; `SADDLV HD, VN.16B`; `SADDLV SD, VN.4H`; `SADDLV SD, VN.8H` (and related forms).
4160/// Operands: `rd`, `rn`.
4161pub trait SaddlvEmitter<T0, T1> {
4162    fn saddlv(&mut self, rd: T0, rn: T1);
4163}
4164
4165/// Emits the `SADDW` instruction.
4166/// Assembly forms: `SADDW VD.TA, VN.TA, VM.TB`.
4167/// Operands: `rd`, `rn`, `rm`.
4168pub trait SaddwEmitter<T0, T1, T2> {
4169    fn saddw(&mut self, rd: T0, rn: T1, rm: T2);
4170}
4171
4172/// Emits the `SADDW2` instruction.
4173/// Assembly forms: `SADDW2 VD.TA, VN.TA, VM.TB`.
4174/// Operands: `rd`, `rn`, `rm`.
4175pub trait Saddw2Emitter<T0, T1, T2> {
4176    fn saddw2(&mut self, rd: T0, rn: T1, rm: T2);
4177}
4178
4179/// Emits the `SCVTF` instruction.
4180/// Assembly forms: `SCVTF SD, WN`; `SCVTF SD, WN, #FBITS`; `SCVTF SD, XN`; `SCVTF SD, XN, #FBITS` (and related forms).
4181/// Operands: `rd`, `rn`.
4182pub trait ScvtfEmitter<T0, T1> {
4183    fn scvtf(&mut self, rd: T0, rn: T1);
4184}
4185
4186/// Emits the `SCVTF_3` instruction.
4187/// Assembly forms: `SCVTF SD, WN`; `SCVTF SD, WN, #FBITS`; `SCVTF SD, XN`; `SCVTF SD, XN, #FBITS` (and related forms).
4188/// Operands: `rd`, `rn`, `fbits_or_bits`.
4189pub trait Scvtf3Emitter<T0, T1, T2> {
4190    fn scvtf_3(&mut self, rd: T0, rn: T1, fbits_or_bits: T2);
4191}
4192
4193/// Emits the `SHADD` instruction.
4194/// Assembly forms: `SHADD VD.T, VN.T, VM.T`; `SHADD VD.T, VN.T, VM.T`.
4195/// Operands: `rd`, `rn`, `rm`.
4196pub trait ShaddEmitter<T0, T1, T2> {
4197    fn shadd(&mut self, rd: T0, rn: T1, rm: T2);
4198}
4199
4200/// Emits the `SHL` instruction.
4201/// Assembly forms: `SHL DD, DN, #N`; `SHL VD.T, VN.T, #N`; `SHL VD.T, VN.T, #N`.
4202/// Operands: `rd`, `rn`, `shift`.
4203pub trait ShlEmitter<T0, T1, T2> {
4204    fn shl(&mut self, rd: T0, rn: T1, shift: T2);
4205}
4206
4207/// Emits the `SHLL` instruction.
4208/// Assembly forms: `SHLL VD.8H, VN.8B, #8`; `SHLL VD.4S, VN.4H, #16`; `SHLL VD.2D, VN.2S, #32`.
4209/// Operands: `rd`, `rn`, `operand_3`.
4210pub trait ShllEmitter<T0, T1, T2> {
4211    fn shll(&mut self, rd: T0, rn: T1, operand_3: T2);
4212}
4213
4214/// Emits the `SHLL2` instruction.
4215/// Assembly forms: `SHLL2 VD.8H, VN.16B, #8`; `SHLL2 VD.4S, VN.8H, #16`; `SHLL2 VD.2D, VN.4S, #32`.
4216/// Operands: `rd`, `rn`, `operand_3`.
4217pub trait Shll2Emitter<T0, T1, T2> {
4218    fn shll2(&mut self, rd: T0, rn: T1, operand_3: T2);
4219}
4220
4221/// Emits the `SHRN` instruction.
4222/// Assembly forms: `SHRN VD.TA, VN.TB, #N`.
4223/// Operands: `rd`, `rn`, `shift`.
4224pub trait ShrnEmitter<T0, T1, T2> {
4225    fn shrn(&mut self, rd: T0, rn: T1, shift: T2);
4226}
4227
4228/// Emits the `SHRN2` instruction.
4229/// Assembly forms: `SHRN2 VX.TA, VN.TB, #N`.
4230/// Operands: `operand_1`, `rn`, `shift`.
4231pub trait Shrn2Emitter<T0, T1, T2> {
4232    fn shrn2(&mut self, operand_1: T0, rn: T1, shift: T2);
4233}
4234
4235/// Emits the `SHSUB` instruction.
4236/// Assembly forms: `SHSUB VD.T, VN.T, VM.T`; `SHSUB VD.T, VN.T, VM.T`.
4237/// Operands: `rd`, `rn`, `rm`.
4238pub trait ShsubEmitter<T0, T1, T2> {
4239    fn shsub(&mut self, rd: T0, rn: T1, rm: T2);
4240}
4241
4242/// Emits the `SLI` instruction.
4243/// Assembly forms: `SLI DX, DN, #N`; `SLI VX.T, VN.T, #N`; `SLI VX.T, VN.T, #N`.
4244/// Operands: `operand_1`, `rn`, `shift`.
4245pub trait SliEmitter<T0, T1, T2> {
4246    fn sli(&mut self, operand_1: T0, rn: T1, shift: T2);
4247}
4248
4249/// Emits the `SMAXP` instruction.
4250/// Assembly forms: `SMAXP VD.T, VN.T, VM.T`; `SMAXP VD.T, VN.T, VM.T`.
4251/// Operands: `rd`, `rn`, `rm`.
4252pub trait SmaxpEmitter<T0, T1, T2> {
4253    fn smaxp(&mut self, rd: T0, rn: T1, rm: T2);
4254}
4255
4256/// Emits the `SMAXV` instruction.
4257/// Assembly forms: `SMAXV BD, VN.8B`; `SMAXV BD, VN.16B`; `SMAXV HD, VN.4H`; `SMAXV HD, VN.8H` (and related forms).
4258/// Operands: `rd`, `rn`.
4259pub trait SmaxvEmitter<T0, T1> {
4260    fn smaxv(&mut self, rd: T0, rn: T1);
4261}
4262
4263/// Emits the `SMINP` instruction.
4264/// Assembly forms: `SMINP VD.T, VN.T, VM.T`; `SMINP VD.T, VN.T, VM.T`.
4265/// Operands: `rd`, `rn`, `rm`.
4266pub trait SminpEmitter<T0, T1, T2> {
4267    fn sminp(&mut self, rd: T0, rn: T1, rm: T2);
4268}
4269
4270/// Emits the `SMINV` instruction.
4271/// Assembly forms: `SMINV BD, VN.8B`; `SMINV BD, VN.16B`; `SMINV HD, VN.4H`; `SMINV HD, VN.8H` (and related forms).
4272/// Operands: `rd`, `rn`.
4273pub trait SminvEmitter<T0, T1> {
4274    fn sminv(&mut self, rd: T0, rn: T1);
4275}
4276
4277/// Emits the `SMLAL` instruction.
4278/// Assembly forms: `SMLAL VX.TA, VN.TB, VM.TB`; `SMLAL VX.4S, VN.4H, VM.H[#IDX]`; `SMLAL VX.2D, VN.2S, VM.S[#IDX]`.
4279/// Operands: `operand_1`, `rn`, `rm`.
4280pub trait SmlalEmitter<T0, T1, T2> {
4281    fn smlal(&mut self, operand_1: T0, rn: T1, rm: T2);
4282}
4283
4284/// Emits the `SMLAL2` instruction.
4285/// Assembly forms: `SMLAL2 VX.TA, VN.TB, VM.TB`; `SMLAL2 VX.4S, VN.8H, VM.H[#IDX]`; `SMLAL2 VX.2D, VN.4S, VM.S[#IDX]`.
4286/// Operands: `operand_1`, `rn`, `rm`.
4287pub trait Smlal2Emitter<T0, T1, T2> {
4288    fn smlal2(&mut self, operand_1: T0, rn: T1, rm: T2);
4289}
4290
4291/// Emits the `SMLSL` instruction.
4292/// Assembly forms: `SMLSL VX.TA, VN.TB, VM.TB`; `SMLSL VX.4S, VN.4H, VM.H[#IDX]`; `SMLSL VX.2D, VN.2S, VM.S[#IDX]`.
4293/// Operands: `operand_1`, `rn`, `rm`.
4294pub trait SmlslEmitter<T0, T1, T2> {
4295    fn smlsl(&mut self, operand_1: T0, rn: T1, rm: T2);
4296}
4297
4298/// Emits the `SMLSL2` instruction.
4299/// Assembly forms: `SMLSL2 VX.TA, VN.TB, VM.TB`; `SMLSL2 VX.4S, VN.8H, VM.H[#IDX]`; `SMLSL2 VX.2D, VN.4S, VM.S[#IDX]`.
4300/// Operands: `operand_1`, `rn`, `rm`.
4301pub trait Smlsl2Emitter<T0, T1, T2> {
4302    fn smlsl2(&mut self, operand_1: T0, rn: T1, rm: T2);
4303}
4304
4305/// Emits the `SMOV` instruction.
4306/// Assembly forms: `SMOV WD, VN.B[#IDX]`; `SMOV WD, VN.H[#IDX]`; `SMOV XD, VN.B[#IDX]`; `SMOV XD, VN.H[#IDX]` (and related forms).
4307/// Operands: `rd`, `rn`.
4308pub trait SmovEmitter<T0, T1> {
4309    fn smov(&mut self, rd: T0, rn: T1);
4310}
4311
4312/// Emits the `SMULL2` instruction.
4313/// Assembly forms: `SMULL2 VD.TA, VN.TB, VM.TB`; `SMULL2 VD.4S, VN.8H, VM.H[#IDX]`; `SMULL2 VD.2D, VN.4S, VM.S[#IDX]`.
4314/// Operands: `rd`, `rn`, `rm`.
4315pub trait Smull2Emitter<T0, T1, T2> {
4316    fn smull2(&mut self, rd: T0, rn: T1, rm: T2);
4317}
4318
4319/// Emits the `SQABS` instruction.
4320/// Assembly forms: `SQABS BD, BN`; `SQABS HD, HN`; `SQABS SD, SN`; `SQABS DD, DN` (and related forms).
4321/// Operands: `rd`, `rn`.
4322pub trait SqabsEmitter<T0, T1> {
4323    fn sqabs(&mut self, rd: T0, rn: T1);
4324}
4325
4326/// Emits the `SQADD` instruction.
4327/// Assembly forms: `SQADD BD, BN, BM`; `SQADD HD, HN, HM`; `SQADD SD, SN, SM`; `SQADD DD, DN, DM` (and related forms).
4328/// Operands: `rd`, `rn`, `rm`.
4329pub trait SqaddEmitter<T0, T1, T2> {
4330    fn sqadd(&mut self, rd: T0, rn: T1, rm: T2);
4331}
4332
4333/// Emits the `SQDMLAL` instruction.
4334/// Assembly forms: `SQDMLAL SX, HN, HM`; `SQDMLAL DX, SN, SM`; `SQDMLAL SX, HN, VM.H[#IDX]`; `SQDMLAL DX, SN, VM.S[#IDX]` (and related forms).
4335/// Operands: `operand_1`, `rn`, `rm`.
4336pub trait SqdmlalEmitter<T0, T1, T2> {
4337    fn sqdmlal(&mut self, operand_1: T0, rn: T1, rm: T2);
4338}
4339
4340/// Emits the `SQDMLAL2` instruction.
4341/// Assembly forms: `SQDMLAL2 VX.TA, VN.TB, VM.TB`; `SQDMLAL2 VX.4S, VN.8H, VM.H[#IDX]`; `SQDMLAL2 VX.2D, VN.4S, VM.S[#IDX]`.
4342/// Operands: `operand_1`, `rn`, `rm`.
4343pub trait Sqdmlal2Emitter<T0, T1, T2> {
4344    fn sqdmlal2(&mut self, operand_1: T0, rn: T1, rm: T2);
4345}
4346
4347/// Emits the `SQDMLSL` instruction.
4348/// Assembly forms: `SQDMLSL SX, HN, HM`; `SQDMLSL DX, SN, SM`; `SQDMLSL SX, HN, VM.H[#IDX]`; `SQDMLSL DX, SN, VM.S[#IDX]` (and related forms).
4349/// Operands: `operand_1`, `rn`, `rm`.
4350pub trait SqdmlslEmitter<T0, T1, T2> {
4351    fn sqdmlsl(&mut self, operand_1: T0, rn: T1, rm: T2);
4352}
4353
4354/// Emits the `SQDMLSL2` instruction.
4355/// Assembly forms: `SQDMLSL2 VX.TA, VN.TB, VM.TB`; `SQDMLSL2 VX.4S, VN.8H, VM.H[#IDX]`; `SQDMLSL2 VX.2D, VN.4S, VM.S[#IDX]`.
4356/// Operands: `operand_1`, `rn`, `rm`.
4357pub trait Sqdmlsl2Emitter<T0, T1, T2> {
4358    fn sqdmlsl2(&mut self, operand_1: T0, rn: T1, rm: T2);
4359}
4360
4361/// Emits the `SQDMULH` instruction.
4362/// Assembly forms: `SQDMULH HD, HN, HM`; `SQDMULH SD, SN, SM`; `SQDMULH HD, HN, VM.H[#IDX]`; `SQDMULH SD, SN, VM.S[#IDX]` (and related forms).
4363/// Operands: `rd`, `rn`, `rm`.
4364pub trait SqdmulhEmitter<T0, T1, T2> {
4365    fn sqdmulh(&mut self, rd: T0, rn: T1, rm: T2);
4366}
4367
4368/// Emits the `SQDMULL` instruction.
4369/// Assembly forms: `SQDMULL SD, HN, HM`; `SQDMULL DD, SN, SM`; `SQDMULL SD, HN, VM.H[#IDX]`; `SQDMULL DD, SN, VM.S[#IDX]` (and related forms).
4370/// Operands: `rd`, `rn`, `rm`.
4371pub trait SqdmullEmitter<T0, T1, T2> {
4372    fn sqdmull(&mut self, rd: T0, rn: T1, rm: T2);
4373}
4374
4375/// Emits the `SQDMULL2` instruction.
4376/// Assembly forms: `SQDMULL2 VD.TA, VN.TB, VM.TB`; `SQDMULL2 VD.4S, VN.8H, VM.H[#IDX]`; `SQDMULL2 VD.2D, VN.4S, VM.S[#IDX]`.
4377/// Operands: `rd`, `rn`, `rm`.
4378pub trait Sqdmull2Emitter<T0, T1, T2> {
4379    fn sqdmull2(&mut self, rd: T0, rn: T1, rm: T2);
4380}
4381
4382/// Emits the `SQNEG` instruction.
4383/// Assembly forms: `SQNEG BD, BN`; `SQNEG HD, HN`; `SQNEG SD, SN`; `SQNEG DD, DN` (and related forms).
4384/// Operands: `rd`, `rn`.
4385pub trait SqnegEmitter<T0, T1> {
4386    fn sqneg(&mut self, rd: T0, rn: T1);
4387}
4388
4389/// Emits the `SQRDMULH` instruction.
4390/// Assembly forms: `SQRDMULH HD, HN, HM`; `SQRDMULH SD, SN, SM`; `SQRDMULH HD, HN, VM.H[#IDX]`; `SQRDMULH SD, SN, VM.S[#IDX]` (and related forms).
4391/// Operands: `rd`, `rn`, `rm`.
4392pub trait SqrdmulhEmitter<T0, T1, T2> {
4393    fn sqrdmulh(&mut self, rd: T0, rn: T1, rm: T2);
4394}
4395
4396/// Emits the `SQRSHL` instruction.
4397/// Assembly forms: `SQRSHL BD, BN, BM`; `SQRSHL HD, HN, HM`; `SQRSHL SD, SN, SM`; `SQRSHL DD, DN, DM` (and related forms).
4398/// Operands: `rd`, `rn`, `rm`.
4399pub trait SqrshlEmitter<T0, T1, T2> {
4400    fn sqrshl(&mut self, rd: T0, rn: T1, rm: T2);
4401}
4402
4403/// Emits the `SQRSHRN` instruction.
4404/// Assembly forms: `SQRSHRN BD, HN, #N`; `SQRSHRN HD, SN, #N`; `SQRSHRN SD, DN, #N`; `SQRSHRN VD.8B, VN.8H, #N` (and related forms).
4405/// Operands: `rd`, `rn`, `shift`.
4406pub trait SqrshrnEmitter<T0, T1, T2> {
4407    fn sqrshrn(&mut self, rd: T0, rn: T1, shift: T2);
4408}
4409
4410/// Emits the `SQRSHRN2` instruction.
4411/// Assembly forms: `SQRSHRN2 VX.16B, VN.8H, #N`; `SQRSHRN2 VX.8H, VN.4S, #N`; `SQRSHRN2 VX.4S, VN.2D, #N`.
4412/// Operands: `operand_1`, `rn`, `shift`.
4413pub trait Sqrshrn2Emitter<T0, T1, T2> {
4414    fn sqrshrn2(&mut self, operand_1: T0, rn: T1, shift: T2);
4415}
4416
4417/// Emits the `SQRSHRUN` instruction.
4418/// Assembly forms: `SQRSHRUN BD, HN, #N`; `SQRSHRUN HD, SN, #N`; `SQRSHRUN SD, DN, #N`; `SQRSHRUN VD.8B, VN.8H, #N` (and related forms).
4419/// Operands: `rd`, `rn`, `shift`.
4420pub trait SqrshrunEmitter<T0, T1, T2> {
4421    fn sqrshrun(&mut self, rd: T0, rn: T1, shift: T2);
4422}
4423
4424/// Emits the `SQRSHRUN2` instruction.
4425/// Assembly forms: `SQRSHRUN2 VX.16B, VN.8H, #N`; `SQRSHRUN2 VX.8H, VN.4S, #N`; `SQRSHRUN2 VX.4S, VN.2D, #N`.
4426/// Operands: `operand_1`, `rn`, `shift`.
4427pub trait Sqrshrun2Emitter<T0, T1, T2> {
4428    fn sqrshrun2(&mut self, operand_1: T0, rn: T1, shift: T2);
4429}
4430
4431/// Emits the `SQSHL` instruction.
4432/// Assembly forms: `SQSHL BD, BN, BM`; `SQSHL HD, HN, HM`; `SQSHL SD, SN, SM`; `SQSHL DD, DN, DM` (and related forms).
4433/// Operands: `rd`, `rn`, `rm_or_shift`.
4434pub trait SqshlEmitter<T0, T1, T2> {
4435    fn sqshl(&mut self, rd: T0, rn: T1, rm_or_shift: T2);
4436}
4437
4438/// Emits the `SQSHLU` instruction.
4439/// Assembly forms: `SQSHLU BD, BN, #N`; `SQSHLU HD, HN, #N`; `SQSHLU SD, SN, #N`; `SQSHLU DD, DN, #N` (and related forms).
4440/// Operands: `rd`, `rn`, `shift`.
4441pub trait SqshluEmitter<T0, T1, T2> {
4442    fn sqshlu(&mut self, rd: T0, rn: T1, shift: T2);
4443}
4444
4445/// Emits the `SQSHRN` instruction.
4446/// Assembly forms: `SQSHRN BD, HN, #N`; `SQSHRN HD, SN, #N`; `SQSHRN SD, DN, #N`; `SQSHRN VD.TA, VN.TB, #N`.
4447/// Operands: `rd`, `rn`, `shift`.
4448pub trait SqshrnEmitter<T0, T1, T2> {
4449    fn sqshrn(&mut self, rd: T0, rn: T1, shift: T2);
4450}
4451
4452/// Emits the `SQSHRN2` instruction.
4453/// Assembly forms: `SQSHRN2 VX.TA, VN.TB, #N`.
4454/// Operands: `operand_1`, `rn`, `shift`.
4455pub trait Sqshrn2Emitter<T0, T1, T2> {
4456    fn sqshrn2(&mut self, operand_1: T0, rn: T1, shift: T2);
4457}
4458
4459/// Emits the `SQSHRUN` instruction.
4460/// Assembly forms: `SQSHRUN BD, HN, #N`; `SQSHRUN HD, SN, #N`; `SQSHRUN SD, DN, #N`; `SQSHRUN VD.8B, VN.8H, #N` (and related forms).
4461/// Operands: `rd`, `rn`, `shift`.
4462pub trait SqshrunEmitter<T0, T1, T2> {
4463    fn sqshrun(&mut self, rd: T0, rn: T1, shift: T2);
4464}
4465
4466/// Emits the `SQSHRUN2` instruction.
4467/// Assembly forms: `SQSHRUN2 VX.16B, VN.8H, #N`; `SQSHRUN2 VX.8H, VN.4S, #N`; `SQSHRUN2 VX.4S, VN.2D, #N`.
4468/// Operands: `operand_1`, `rn`, `shift`.
4469pub trait Sqshrun2Emitter<T0, T1, T2> {
4470    fn sqshrun2(&mut self, operand_1: T0, rn: T1, shift: T2);
4471}
4472
4473/// Emits the `SQSUB` instruction.
4474/// Assembly forms: `SQSUB BD, BN, BM`; `SQSUB HD, HN, HM`; `SQSUB SD, SN, SM`; `SQSUB DD, DN, DM` (and related forms).
4475/// Operands: `rd`, `rn`, `rm`.
4476pub trait SqsubEmitter<T0, T1, T2> {
4477    fn sqsub(&mut self, rd: T0, rn: T1, rm: T2);
4478}
4479
4480/// Emits the `SQXTN` instruction.
4481/// Assembly forms: `SQXTN BD, HN`; `SQXTN HD, SN`; `SQXTN SD, DN`; `SQXTN VD.TA, VN.TB`.
4482/// Operands: `rd`, `rn`.
4483pub trait SqxtnEmitter<T0, T1> {
4484    fn sqxtn(&mut self, rd: T0, rn: T1);
4485}
4486
4487/// Emits the `SQXTN2` instruction.
4488/// Assembly forms: `SQXTN2 VX.TA, VN.TB`.
4489/// Operands: `operand_1`, `rn`.
4490pub trait Sqxtn2Emitter<T0, T1> {
4491    fn sqxtn2(&mut self, operand_1: T0, rn: T1);
4492}
4493
4494/// Emits the `SQXTUN` instruction.
4495/// Assembly forms: `SQXTUN BD, HN`; `SQXTUN HD, SN`; `SQXTUN SD, DN`; `SQXTUN VD.TA, VN.TB`.
4496/// Operands: `rd`, `rn`.
4497pub trait SqxtunEmitter<T0, T1> {
4498    fn sqxtun(&mut self, rd: T0, rn: T1);
4499}
4500
4501/// Emits the `SQXTUN2` instruction.
4502/// Assembly forms: `SQXTUN2 VX.TA, VN.TB`.
4503/// Operands: `operand_1`, `rn`.
4504pub trait Sqxtun2Emitter<T0, T1> {
4505    fn sqxtun2(&mut self, operand_1: T0, rn: T1);
4506}
4507
4508/// Emits the `SRHADD` instruction.
4509/// Assembly forms: `SRHADD VD.T, VN.T, VM.T`; `SRHADD VD.T, VN.T, VM.T`.
4510/// Operands: `rd`, `rn`, `rm`.
4511pub trait SrhaddEmitter<T0, T1, T2> {
4512    fn srhadd(&mut self, rd: T0, rn: T1, rm: T2);
4513}
4514
4515/// Emits the `SRI` instruction.
4516/// Assembly forms: `SRI DX, DN, #N`; `SRI VX.T, VN.T, #N`; `SRI VX.T, VN.T, #N`.
4517/// Operands: `operand_1`, `rn`, `shift`.
4518pub trait SriEmitter<T0, T1, T2> {
4519    fn sri(&mut self, operand_1: T0, rn: T1, shift: T2);
4520}
4521
4522/// Emits the `SRSHL` instruction.
4523/// Assembly forms: `SRSHL DD, DN, DM`; `SRSHL VD.T, VN.T, VM.T`; `SRSHL VD.T, VN.T, VM.T`.
4524/// Operands: `rd`, `rn`, `rm`.
4525pub trait SrshlEmitter<T0, T1, T2> {
4526    fn srshl(&mut self, rd: T0, rn: T1, rm: T2);
4527}
4528
4529/// Emits the `SRSHR` instruction.
4530/// Assembly forms: `SRSHR DD, DN, #N`; `SRSHR VD.T, VN.T, #N`; `SRSHR VD.T, VN.T, #N`.
4531/// Operands: `rd`, `rn`, `shift`.
4532pub trait SrshrEmitter<T0, T1, T2> {
4533    fn srshr(&mut self, rd: T0, rn: T1, shift: T2);
4534}
4535
4536/// Emits the `SRSRA` instruction.
4537/// Assembly forms: `SRSRA DX, DN, #N`; `SRSRA VX.T, VN.T, #N`; `SRSRA VX.T, VN.T, #N`.
4538/// Operands: `operand_1`, `rn`, `shift`.
4539pub trait SrsraEmitter<T0, T1, T2> {
4540    fn srsra(&mut self, operand_1: T0, rn: T1, shift: T2);
4541}
4542
4543/// Emits the `SSHL` instruction.
4544/// Assembly forms: `SSHL DD, DN, DM`; `SSHL VD.T, VN.T, VM.T`; `SSHL VD.T, VN.T, VM.T`.
4545/// Operands: `rd`, `rn`, `rm`.
4546pub trait SshlEmitter<T0, T1, T2> {
4547    fn sshl(&mut self, rd: T0, rn: T1, rm: T2);
4548}
4549
4550/// Emits the `SSHLL` instruction.
4551/// Assembly forms: `SSHLL VD.TA, VN.TB, #N`.
4552/// Operands: `rd`, `rn`, `shift`.
4553pub trait SshllEmitter<T0, T1, T2> {
4554    fn sshll(&mut self, rd: T0, rn: T1, shift: T2);
4555}
4556
4557/// Emits the `SSHLL2` instruction.
4558/// Assembly forms: `SSHLL2 VD.TA, VN.TB, #N`.
4559/// Operands: `rd`, `rn`, `shift`.
4560pub trait Sshll2Emitter<T0, T1, T2> {
4561    fn sshll2(&mut self, rd: T0, rn: T1, shift: T2);
4562}
4563
4564/// Emits the `SSHR` instruction.
4565/// Assembly forms: `SSHR DD, DN, #N`; `SSHR VD.T, VN.T, #N`; `SSHR VD.T, VN.T, #N`.
4566/// Operands: `rd`, `rn`, `shift`.
4567pub trait SshrEmitter<T0, T1, T2> {
4568    fn sshr(&mut self, rd: T0, rn: T1, shift: T2);
4569}
4570
4571/// Emits the `SSRA` instruction.
4572/// Assembly forms: `SSRA DX, DN, #N`; `SSRA VX.T, VN.T, #N`; `SSRA VX.T, VN.T, #N`.
4573/// Operands: `operand_1`, `rn`, `shift`.
4574pub trait SsraEmitter<T0, T1, T2> {
4575    fn ssra(&mut self, operand_1: T0, rn: T1, shift: T2);
4576}
4577
4578/// Emits the `SSUBL` instruction.
4579/// Assembly forms: `SSUBL VD.TA, VN.TB, VM.TB`.
4580/// Operands: `rd`, `rn`, `rm`.
4581pub trait SsublEmitter<T0, T1, T2> {
4582    fn ssubl(&mut self, rd: T0, rn: T1, rm: T2);
4583}
4584
4585/// Emits the `SSUBL2` instruction.
4586/// Assembly forms: `SSUBL2 VD.TA, VN.TB, VM.TB`.
4587/// Operands: `rd`, `rn`, `rm`.
4588pub trait Ssubl2Emitter<T0, T1, T2> {
4589    fn ssubl2(&mut self, rd: T0, rn: T1, rm: T2);
4590}
4591
4592/// Emits the `SSUBW` instruction.
4593/// Assembly forms: `SSUBW VD.TA, VN.TA, VM.TB`.
4594/// Operands: `rd`, `rn`, `rm`.
4595pub trait SsubwEmitter<T0, T1, T2> {
4596    fn ssubw(&mut self, rd: T0, rn: T1, rm: T2);
4597}
4598
4599/// Emits the `SSUBW2` instruction.
4600/// Assembly forms: `SSUBW2 VD.TA, VN.TA, VM.TB`.
4601/// Operands: `rd`, `rn`, `rm`.
4602pub trait Ssubw2Emitter<T0, T1, T2> {
4603    fn ssubw2(&mut self, rd: T0, rn: T1, rm: T2);
4604}
4605
4606/// Emits the `ST1` instruction.
4607/// Assembly forms: `ST1 VS.B[#IDX], [XN|SP]`; `ST1 VS.H[#IDX], [XN|SP]`; `ST1 VS.S[#IDX], [XN|SP]`; `ST1 VS.D[#IDX], [XN|SP]` (and related forms).
4608/// Operands: `rs_or_operand_1`, `addr`.
4609pub trait St1Emitter<T0, T1> {
4610    fn st1(&mut self, rs_or_operand_1: T0, addr: T1);
4611}
4612
4613/// Emits the `ST1_3` instruction.
4614/// Assembly forms: `ST1 VS.B[#IDX], [XN|SP]`; `ST1 VS.H[#IDX], [XN|SP]`; `ST1 VS.S[#IDX], [XN|SP]`; `ST1 VS.D[#IDX], [XN|SP]` (and related forms).
4615/// Operands: `rd`, `rn`, `addr`.
4616pub trait St13Emitter<T0, T1, T2> {
4617    fn st1_3(&mut self, rd: T0, rn: T1, addr: T2);
4618}
4619
4620/// Emits the `ST1_4` instruction.
4621/// Assembly forms: `ST1 VS.B[#IDX], [XN|SP]`; `ST1 VS.H[#IDX], [XN|SP]`; `ST1 VS.S[#IDX], [XN|SP]`; `ST1 VS.D[#IDX], [XN|SP]` (and related forms).
4622/// Operands: `rd`, `rn`, `rm1`, `addr`.
4623pub trait St14Emitter<T0, T1, T2, T3> {
4624    fn st1_4(&mut self, rd: T0, rn: T1, rm1: T2, addr: T3);
4625}
4626
4627/// Emits the `ST1_5` instruction.
4628/// Assembly forms: `ST1 VS.B[#IDX], [XN|SP]`; `ST1 VS.H[#IDX], [XN|SP]`; `ST1 VS.S[#IDX], [XN|SP]`; `ST1 VS.D[#IDX], [XN|SP]` (and related forms).
4629/// Operands: `rd`, `rn`, `rm1`, `rm2`, `addr`.
4630pub trait St15Emitter<T0, T1, T2, T3, T4> {
4631    fn st1_5(&mut self, rd: T0, rn: T1, rm1: T2, rm2: T3, addr: T4);
4632}
4633
4634/// Emits the `ST2` instruction.
4635/// Assembly forms: `ST2 2X{VS.B}+[#IDX], [XN|SP]`; `ST2 2X{VS.H}+[#IDX], [XN|SP]`; `ST2 2X{VS.S}+[#IDX], [XN|SP]`; `ST2 2X{VS.D}+[#IDX], [XN|SP]` (and related forms).
4636/// Operands: `rd`, `rn`, `addr`.
4637pub trait St2Emitter<T0, T1, T2> {
4638    fn st2(&mut self, rd: T0, rn: T1, addr: T2);
4639}
4640
4641/// Emits the `ST3` instruction.
4642/// Assembly forms: `ST3 3X{VS.B}+[#IDX], [XN|SP]`; `ST3 3X{VS.H}+[#IDX], [XN|SP]`; `ST3 3X{VS.S}+[#IDX], [XN|SP]`; `ST3 3X{VS.D}+[#IDX], [XN|SP]` (and related forms).
4643/// Operands: `rd`, `rn`, `rm1`, `addr`.
4644pub trait St3Emitter<T0, T1, T2, T3> {
4645    fn st3(&mut self, rd: T0, rn: T1, rm1: T2, addr: T3);
4646}
4647
4648/// Emits the `ST4` instruction.
4649/// Assembly forms: `ST4 4X{VS.B}+[#IDX], [XN|SP]`; `ST4 4X{VS.H}+[#IDX], [XN|SP]`; `ST4 4X{VS.S}+[#IDX], [XN|SP]`; `ST4 4X{VS.D}+[#IDX], [XN|SP]` (and related forms).
4650/// Operands: `rd`, `rn`, `rm1`, `rm2`, `addr`.
4651pub trait St4Emitter<T0, T1, T2, T3, T4> {
4652    fn st4(&mut self, rd: T0, rn: T1, rm1: T2, rm2: T3, addr: T4);
4653}
4654
4655/// Emits the `SUBHN` instruction.
4656/// Assembly forms: `SUBHN VD.TA, VN.TB, VM.TB`.
4657/// Operands: `rd`, `rn`, `rm`.
4658pub trait SubhnEmitter<T0, T1, T2> {
4659    fn subhn(&mut self, rd: T0, rn: T1, rm: T2);
4660}
4661
4662/// Emits the `SUBHN2` instruction.
4663/// Assembly forms: `SUBHN2 VX.TA, VN.TB, VM.TB`.
4664/// Operands: `operand_1`, `rn`, `rm`.
4665pub trait Subhn2Emitter<T0, T1, T2> {
4666    fn subhn2(&mut self, operand_1: T0, rn: T1, rm: T2);
4667}
4668
4669/// Emits the `SUQADD` instruction.
4670/// Assembly forms: `SUQADD BX, BN`; `SUQADD HX, HN`; `SUQADD SX, SN`; `SUQADD DX, DN` (and related forms).
4671/// Operands: `operand_1`, `rn`.
4672pub trait SuqaddEmitter<T0, T1> {
4673    fn suqadd(&mut self, operand_1: T0, rn: T1);
4674}
4675
4676/// Emits the `SXTL` instruction.
4677/// Assembly forms: `SXTL VD.TA, VN.TB`.
4678/// Operands: `rd`, `rn`.
4679pub trait SxtlEmitter<T0, T1> {
4680    fn sxtl(&mut self, rd: T0, rn: T1);
4681}
4682
4683/// Emits the `SXTL2` instruction.
4684/// Assembly forms: `SXTL2 VD.TA, VN.TB`.
4685/// Operands: `rd`, `rn`.
4686pub trait Sxtl2Emitter<T0, T1> {
4687    fn sxtl2(&mut self, rd: T0, rn: T1);
4688}
4689
4690/// Emits the `TBL` instruction.
4691/// Assembly forms: `TBL VD.8B, VN.16B, VM.8B`; `TBL VD.16B, VN.16B, VM.16B`; `TBL VD.8B, 2X{VN.16B}+, VM.8B`; `TBL VD.16B, 2X{VN.16B}+, VM.16B` (and related forms).
4692/// Operands: `rd`, `rn_or_operand_2`, `rm`.
4693pub trait TblEmitter<T0, T1, T2> {
4694    fn tbl(&mut self, rd: T0, rn_or_operand_2: T1, rm: T2);
4695}
4696
4697/// Emits the `TBL_4` instruction.
4698/// Assembly forms: `TBL VD.8B, VN.16B, VM.8B`; `TBL VD.16B, VN.16B, VM.16B`; `TBL VD.8B, 2X{VN.16B}+, VM.8B`; `TBL VD.16B, 2X{VN.16B}+, VM.16B` (and related forms).
4699/// Operands: `rd`, `rn`, `rm1`, `rm2`.
4700pub trait Tbl4Emitter<T0, T1, T2, T3> {
4701    fn tbl_4(&mut self, rd: T0, rn: T1, rm1: T2, rm2: T3);
4702}
4703
4704/// Emits the `TBL_5` instruction.
4705/// Assembly forms: `TBL VD.8B, VN.16B, VM.8B`; `TBL VD.16B, VN.16B, VM.16B`; `TBL VD.8B, 2X{VN.16B}+, VM.8B`; `TBL VD.16B, 2X{VN.16B}+, VM.16B` (and related forms).
4706/// Operands: `rd`, `rn`, `rm1`, `rm2`, `rm3`.
4707pub trait Tbl5Emitter<T0, T1, T2, T3, T4> {
4708    fn tbl_5(&mut self, rd: T0, rn: T1, rm1: T2, rm2: T3, rm3: T4);
4709}
4710
4711/// Emits the `TBL_6` instruction.
4712/// Assembly forms: `TBL VD.8B, VN.16B, VM.8B`; `TBL VD.16B, VN.16B, VM.16B`; `TBL VD.8B, 2X{VN.16B}+, VM.8B`; `TBL VD.16B, 2X{VN.16B}+, VM.16B` (and related forms).
4713/// Operands: `rd`, `rn`, `rm1`, `rm2`, `rm3`, `rm4`.
4714pub trait Tbl6Emitter<T0, T1, T2, T3, T4, T5> {
4715    fn tbl_6(&mut self, rd: T0, rn: T1, rm1: T2, rm2: T3, rm3: T4, rm4: T5);
4716}
4717
4718/// Emits the `TBX` instruction.
4719/// Assembly forms: `TBX VX.8B, VN.16B, VM.8B`; `TBX VX.16B, VN.16B, VM.16B`; `TBX VX.8B, 2X{VN.16B}+, VM.8B`; `TBX VX.16B, 2X{VN.16B}+, VM.16B` (and related forms).
4720/// Operands: `operand_1`, `rn_or_operand_2`, `rm`.
4721pub trait TbxEmitter<T0, T1, T2> {
4722    fn tbx(&mut self, operand_1: T0, rn_or_operand_2: T1, rm: T2);
4723}
4724
4725/// Emits the `TBX_4` instruction.
4726/// Assembly forms: `TBX VX.8B, VN.16B, VM.8B`; `TBX VX.16B, VN.16B, VM.16B`; `TBX VX.8B, 2X{VN.16B}+, VM.8B`; `TBX VX.16B, 2X{VN.16B}+, VM.16B` (and related forms).
4727/// Operands: `rd`, `rn`, `rm1`, `rm2`.
4728pub trait Tbx4Emitter<T0, T1, T2, T3> {
4729    fn tbx_4(&mut self, rd: T0, rn: T1, rm1: T2, rm2: T3);
4730}
4731
4732/// Emits the `TBX_5` instruction.
4733/// Assembly forms: `TBX VX.8B, VN.16B, VM.8B`; `TBX VX.16B, VN.16B, VM.16B`; `TBX VX.8B, 2X{VN.16B}+, VM.8B`; `TBX VX.16B, 2X{VN.16B}+, VM.16B` (and related forms).
4734/// Operands: `rd`, `rn`, `rm1`, `rm2`, `rm3`.
4735pub trait Tbx5Emitter<T0, T1, T2, T3, T4> {
4736    fn tbx_5(&mut self, rd: T0, rn: T1, rm1: T2, rm2: T3, rm3: T4);
4737}
4738
4739/// Emits the `TBX_6` instruction.
4740/// Assembly forms: `TBX VX.8B, VN.16B, VM.8B`; `TBX VX.16B, VN.16B, VM.16B`; `TBX VX.8B, 2X{VN.16B}+, VM.8B`; `TBX VX.16B, 2X{VN.16B}+, VM.16B` (and related forms).
4741/// Operands: `rd`, `rn`, `rm1`, `rm2`, `rm3`, `rm4`.
4742pub trait Tbx6Emitter<T0, T1, T2, T3, T4, T5> {
4743    fn tbx_6(&mut self, rd: T0, rn: T1, rm1: T2, rm2: T3, rm3: T4, rm4: T5);
4744}
4745
4746/// Emits the `TRN1` instruction.
4747/// Assembly forms: `TRN1 VD.T, VN.T, VM.T`; `TRN1 VD.T, VN.T, VM.T`.
4748/// Operands: `rd`, `rn`, `rm`.
4749pub trait Trn1Emitter<T0, T1, T2> {
4750    fn trn1(&mut self, rd: T0, rn: T1, rm: T2);
4751}
4752
4753/// Emits the `TRN2` instruction.
4754/// Assembly forms: `TRN2 VD.T, VN.T, VM.T`; `TRN2 VD.T, VN.T, VM.T`.
4755/// Operands: `rd`, `rn`, `rm`.
4756pub trait Trn2Emitter<T0, T1, T2> {
4757    fn trn2(&mut self, rd: T0, rn: T1, rm: T2);
4758}
4759
4760/// Emits the `UABA` instruction.
4761/// Assembly forms: `UABA VX.T, VN.T, VM.T`; `UABA VX.T, VN.T, VM.T`.
4762/// Operands: `operand_1`, `rn`, `rm`.
4763pub trait UabaEmitter<T0, T1, T2> {
4764    fn uaba(&mut self, operand_1: T0, rn: T1, rm: T2);
4765}
4766
4767/// Emits the `UABAL` instruction.
4768/// Assembly forms: `UABAL VX.TA, VN.TB, VM.TB`.
4769/// Operands: `operand_1`, `rn`, `rm`.
4770pub trait UabalEmitter<T0, T1, T2> {
4771    fn uabal(&mut self, operand_1: T0, rn: T1, rm: T2);
4772}
4773
4774/// Emits the `UABAL2` instruction.
4775/// Assembly forms: `UABAL2 VX.TA, VN.TB, VM.TB`.
4776/// Operands: `operand_1`, `rn`, `rm`.
4777pub trait Uabal2Emitter<T0, T1, T2> {
4778    fn uabal2(&mut self, operand_1: T0, rn: T1, rm: T2);
4779}
4780
4781/// Emits the `UABD` instruction.
4782/// Assembly forms: `UABD VD.T, VN.T, VM.T`; `UABD VD.T, VN.T, VM.T`.
4783/// Operands: `rd`, `rn`, `rm`.
4784pub trait UabdEmitter<T0, T1, T2> {
4785    fn uabd(&mut self, rd: T0, rn: T1, rm: T2);
4786}
4787
4788/// Emits the `UABDL` instruction.
4789/// Assembly forms: `UABDL VD.TA, VN.TB, VM.TB`.
4790/// Operands: `rd`, `rn`, `rm`.
4791pub trait UabdlEmitter<T0, T1, T2> {
4792    fn uabdl(&mut self, rd: T0, rn: T1, rm: T2);
4793}
4794
4795/// Emits the `UABDL2` instruction.
4796/// Assembly forms: `UABDL2 VD.TA, VN.TB, VM.TB`.
4797/// Operands: `rd`, `rn`, `rm`.
4798pub trait Uabdl2Emitter<T0, T1, T2> {
4799    fn uabdl2(&mut self, rd: T0, rn: T1, rm: T2);
4800}
4801
4802/// Emits the `UADALP` instruction.
4803/// Assembly forms: `UADALP VX.TA, VN.TB`; `UADALP VX.TA, VN.TB`.
4804/// Operands: `operand_1`, `rn`.
4805pub trait UadalpEmitter<T0, T1> {
4806    fn uadalp(&mut self, operand_1: T0, rn: T1);
4807}
4808
4809/// Emits the `UADDL` instruction.
4810/// Assembly forms: `UADDL VD.TA, VN.TB, VM.TB`.
4811/// Operands: `rd`, `rn`, `rm`.
4812pub trait UaddlEmitter<T0, T1, T2> {
4813    fn uaddl(&mut self, rd: T0, rn: T1, rm: T2);
4814}
4815
4816/// Emits the `UADDL2` instruction.
4817/// Assembly forms: `UADDL2 VD.TA, VN.TB, VM.TB`.
4818/// Operands: `rd`, `rn`, `rm`.
4819pub trait Uaddl2Emitter<T0, T1, T2> {
4820    fn uaddl2(&mut self, rd: T0, rn: T1, rm: T2);
4821}
4822
4823/// Emits the `UADDLP` instruction.
4824/// Assembly forms: `UADDLP VD.TA, VN.TB`; `UADDLP VD.TA, VN.TB`.
4825/// Operands: `rd`, `rn`.
4826pub trait UaddlpEmitter<T0, T1> {
4827    fn uaddlp(&mut self, rd: T0, rn: T1);
4828}
4829
4830/// Emits the `UADDLV` instruction.
4831/// Assembly forms: `UADDLV HD, VN.8B`; `UADDLV HD, VN.16B`; `UADDLV SD, VN.4H`; `UADDLV SD, VN.8H` (and related forms).
4832/// Operands: `rd`, `rn`.
4833pub trait UaddlvEmitter<T0, T1> {
4834    fn uaddlv(&mut self, rd: T0, rn: T1);
4835}
4836
4837/// Emits the `UADDW` instruction.
4838/// Assembly forms: `UADDW VD.TA, VN.TA, VM.TB`.
4839/// Operands: `rd`, `rn`, `rm`.
4840pub trait UaddwEmitter<T0, T1, T2> {
4841    fn uaddw(&mut self, rd: T0, rn: T1, rm: T2);
4842}
4843
4844/// Emits the `UADDW2` instruction.
4845/// Assembly forms: `UADDW2 VD.TA, VN.TA, VM.TB`.
4846/// Operands: `rd`, `rn`, `rm`.
4847pub trait Uaddw2Emitter<T0, T1, T2> {
4848    fn uaddw2(&mut self, rd: T0, rn: T1, rm: T2);
4849}
4850
4851/// Emits the `UCVTF` instruction.
4852/// Assembly forms: `UCVTF SD, WN`; `UCVTF SD, WN, #FBITS`; `UCVTF SD, XN`; `UCVTF SD, XN, #FBITS` (and related forms).
4853/// Operands: `rd`, `rn`.
4854pub trait UcvtfEmitter<T0, T1> {
4855    fn ucvtf(&mut self, rd: T0, rn: T1);
4856}
4857
4858/// Emits the `UCVTF_3` instruction.
4859/// Assembly forms: `UCVTF SD, WN`; `UCVTF SD, WN, #FBITS`; `UCVTF SD, XN`; `UCVTF SD, XN, #FBITS` (and related forms).
4860/// Operands: `rd`, `rn`, `fbits_or_bits`.
4861pub trait Ucvtf3Emitter<T0, T1, T2> {
4862    fn ucvtf_3(&mut self, rd: T0, rn: T1, fbits_or_bits: T2);
4863}
4864
4865/// Emits the `UHADD` instruction.
4866/// Assembly forms: `UHADD VD.T, VN.T, VM.T`; `UHADD VD.T, VN.T, VM.T`.
4867/// Operands: `rd`, `rn`, `rm`.
4868pub trait UhaddEmitter<T0, T1, T2> {
4869    fn uhadd(&mut self, rd: T0, rn: T1, rm: T2);
4870}
4871
4872/// Emits the `UHSUB` instruction.
4873/// Assembly forms: `UHSUB VD.T, VN.T, VM.T`; `UHSUB VD.T, VN.T, VM.T`.
4874/// Operands: `rd`, `rn`, `rm`.
4875pub trait UhsubEmitter<T0, T1, T2> {
4876    fn uhsub(&mut self, rd: T0, rn: T1, rm: T2);
4877}
4878
4879/// Emits the `UMAXP` instruction.
4880/// Assembly forms: `UMAXP VD.T, VN.T, VM.T`; `UMAXP VD.T, VN.T, VM.T`.
4881/// Operands: `rd`, `rn`, `rm`.
4882pub trait UmaxpEmitter<T0, T1, T2> {
4883    fn umaxp(&mut self, rd: T0, rn: T1, rm: T2);
4884}
4885
4886/// Emits the `UMAXV` instruction.
4887/// Assembly forms: `UMAXV BD, VN.8B`; `UMAXV BD, VN.16B`; `UMAXV HD, VN.4H`; `UMAXV HD, VN.8H` (and related forms).
4888/// Operands: `rd`, `rn`.
4889pub trait UmaxvEmitter<T0, T1> {
4890    fn umaxv(&mut self, rd: T0, rn: T1);
4891}
4892
4893/// Emits the `UMINP` instruction.
4894/// Assembly forms: `UMINP VD.T, VN.T, VM.T`; `UMINP VD.T, VN.T, VM.T`.
4895/// Operands: `rd`, `rn`, `rm`.
4896pub trait UminpEmitter<T0, T1, T2> {
4897    fn uminp(&mut self, rd: T0, rn: T1, rm: T2);
4898}
4899
4900/// Emits the `UMINV` instruction.
4901/// Assembly forms: `UMINV BD, VN.8B`; `UMINV BD, VN.16B`; `UMINV HD, VN.4H`; `UMINV HD, VN.8H` (and related forms).
4902/// Operands: `rd`, `rn`.
4903pub trait UminvEmitter<T0, T1> {
4904    fn uminv(&mut self, rd: T0, rn: T1);
4905}
4906
4907/// Emits the `UMLAL` instruction.
4908/// Assembly forms: `UMLAL VD.TA, VN.TB, VM.TB`; `UMLAL VD.4S, VN.4H, VM.H[#IDX]`; `UMLAL VD.2D, VN.2S, VM.S[#IDX]`.
4909/// Operands: `rd`, `rn`, `rm`.
4910pub trait UmlalEmitter<T0, T1, T2> {
4911    fn umlal(&mut self, rd: T0, rn: T1, rm: T2);
4912}
4913
4914/// Emits the `UMLAL2` instruction.
4915/// Assembly forms: `UMLAL2 VD.TA, VN.TB, VM.TB`; `UMLAL2 VD.4S, VN.8H, VM.H[#IDX]`; `UMLAL2 VD.2D, VN.4S, VM.S[#IDX]`.
4916/// Operands: `rd`, `rn`, `rm`.
4917pub trait Umlal2Emitter<T0, T1, T2> {
4918    fn umlal2(&mut self, rd: T0, rn: T1, rm: T2);
4919}
4920
4921/// Emits the `UMLSL` instruction.
4922/// Assembly forms: `UMLSL VD.TA, VN.TB, VM.TB`; `UMLSL VD.4S, VN.4H, VM.H[#IDX]`; `UMLSL VD.2D, VN.2S, VM.S[#IDX]`.
4923/// Operands: `rd`, `rn`, `rm`.
4924pub trait UmlslEmitter<T0, T1, T2> {
4925    fn umlsl(&mut self, rd: T0, rn: T1, rm: T2);
4926}
4927
4928/// Emits the `UMLSL2` instruction.
4929/// Assembly forms: `UMLSL2 VD.TA, VN.TB, VM.TB`; `UMLSL2 VD.4S, VN.8H, VM.H[#IDX]`; `UMLSL2 VD.2D, VN.4S, VM.S[#IDX]`.
4930/// Operands: `rd`, `rn`, `rm`.
4931pub trait Umlsl2Emitter<T0, T1, T2> {
4932    fn umlsl2(&mut self, rd: T0, rn: T1, rm: T2);
4933}
4934
4935/// Emits the `UMOV` instruction.
4936/// Assembly forms: `UMOV WD, VN.B[#IDX]`; `UMOV WD, VN.H[#IDX]`; `UMOV|MOV WD, VN.S[#IDX]`; `UMOV|MOV XD, VN.D[#IDX]`.
4937/// Operands: `rd`, `rn`.
4938pub trait UmovEmitter<T0, T1> {
4939    fn umov(&mut self, rd: T0, rn: T1);
4940}
4941
4942/// Emits the `UMULL2` instruction.
4943/// Assembly forms: `UMULL2 VD.TA, VN.TB, VM.TB`; `UMULL2 VD.4S, VN.8H, VM.H[#IDX]`; `UMULL2 VD.2D, VN.4S, VM.S[#IDX]`.
4944/// Operands: `rd`, `rn`, `rm`.
4945pub trait Umull2Emitter<T0, T1, T2> {
4946    fn umull2(&mut self, rd: T0, rn: T1, rm: T2);
4947}
4948
4949/// Emits the `UQADD` instruction.
4950/// Assembly forms: `UQADD BD, BN, BM`; `UQADD HD, HN, HM`; `UQADD SD, SN, SM`; `UQADD DD, DN, DM` (and related forms).
4951/// Operands: `rd`, `rn`, `rm`.
4952pub trait UqaddEmitter<T0, T1, T2> {
4953    fn uqadd(&mut self, rd: T0, rn: T1, rm: T2);
4954}
4955
4956/// Emits the `UQRSHL` instruction.
4957/// Assembly forms: `UQRSHL BD, BN, BM`; `UQRSHL HD, HN, HM`; `UQRSHL SD, SN, SM`; `UQRSHL DD, DN, DM` (and related forms).
4958/// Operands: `rd`, `rn`, `rm`.
4959pub trait UqrshlEmitter<T0, T1, T2> {
4960    fn uqrshl(&mut self, rd: T0, rn: T1, rm: T2);
4961}
4962
4963/// Emits the `UQRSHRN` instruction.
4964/// Assembly forms: `UQRSHRN BD, HN, #N`; `UQRSHRN HD, SN, #N`; `UQRSHRN SD, DN, #N`; `UQRSHRN VD.8B, VN.8H, #N` (and related forms).
4965/// Operands: `rd`, `rn`, `shift`.
4966pub trait UqrshrnEmitter<T0, T1, T2> {
4967    fn uqrshrn(&mut self, rd: T0, rn: T1, shift: T2);
4968}
4969
4970/// Emits the `UQRSHRN2` instruction.
4971/// Assembly forms: `UQRSHRN2 VX.16B, VN.8H, #N`; `UQRSHRN2 VX.8H, VN.4S, #N`; `UQRSHRN2 VX.4S, VN.2D, #N`.
4972/// Operands: `operand_1`, `rn`, `shift`.
4973pub trait Uqrshrn2Emitter<T0, T1, T2> {
4974    fn uqrshrn2(&mut self, operand_1: T0, rn: T1, shift: T2);
4975}
4976
4977/// Emits the `UQSHL` instruction.
4978/// Assembly forms: `UQSHL BD, BN, BM`; `UQSHL HD, HN, HM`; `UQSHL SD, SN, SM`; `UQSHL DD, DN, DM` (and related forms).
4979/// Operands: `rd`, `rn`, `rm_or_shift`.
4980pub trait UqshlEmitter<T0, T1, T2> {
4981    fn uqshl(&mut self, rd: T0, rn: T1, rm_or_shift: T2);
4982}
4983
4984/// Emits the `UQSHRN` instruction.
4985/// Assembly forms: `UQSHRN BD, HN, #N`; `UQSHRN HD, SN, #N`; `UQSHRN SD, DN, #N`; `UQSHRN VD.TA, VN.TB, #N`.
4986/// Operands: `rd`, `rn`, `shift`.
4987pub trait UqshrnEmitter<T0, T1, T2> {
4988    fn uqshrn(&mut self, rd: T0, rn: T1, shift: T2);
4989}
4990
4991/// Emits the `UQSHRN2` instruction.
4992/// Assembly forms: `UQSHRN2 VX.TA, VN.TB, #N`.
4993/// Operands: `operand_1`, `rn`, `shift`.
4994pub trait Uqshrn2Emitter<T0, T1, T2> {
4995    fn uqshrn2(&mut self, operand_1: T0, rn: T1, shift: T2);
4996}
4997
4998/// Emits the `UQSUB` instruction.
4999/// Assembly forms: `UQSUB BD, BN, BM`; `UQSUB HD, HN, HM`; `UQSUB SD, SN, SM`; `UQSUB DD, DN, DM` (and related forms).
5000/// Operands: `rd`, `rn`, `rm`.
5001pub trait UqsubEmitter<T0, T1, T2> {
5002    fn uqsub(&mut self, rd: T0, rn: T1, rm: T2);
5003}
5004
5005/// Emits the `UQXTN` instruction.
5006/// Assembly forms: `UQXTN BD, HN`; `UQXTN HD, SN`; `UQXTN SD, DN`; `UQXTN VD.TA, VN.TB`.
5007/// Operands: `rd`, `rn`.
5008pub trait UqxtnEmitter<T0, T1> {
5009    fn uqxtn(&mut self, rd: T0, rn: T1);
5010}
5011
5012/// Emits the `UQXTN2` instruction.
5013/// Assembly forms: `UQXTN2 VX.TA, VN.TB`.
5014/// Operands: `operand_1`, `rn`.
5015pub trait Uqxtn2Emitter<T0, T1> {
5016    fn uqxtn2(&mut self, operand_1: T0, rn: T1);
5017}
5018
5019/// Emits the `URECPE` instruction.
5020/// Assembly forms: `URECPE VD.2S, VN.2S`; `URECPE VD.4S, VN.4S`.
5021/// Operands: `rd`, `rn`.
5022pub trait UrecpeEmitter<T0, T1> {
5023    fn urecpe(&mut self, rd: T0, rn: T1);
5024}
5025
5026/// Emits the `URHADD` instruction.
5027/// Assembly forms: `URHADD VD.T, VN.T, VM.T`; `URHADD VD.T, VN.T, VM.T`.
5028/// Operands: `rd`, `rn`, `rm`.
5029pub trait UrhaddEmitter<T0, T1, T2> {
5030    fn urhadd(&mut self, rd: T0, rn: T1, rm: T2);
5031}
5032
5033/// Emits the `URSHL` instruction.
5034/// Assembly forms: `URSHL DD, DN, DM`; `URSHL VD.T, VN.T, VM.T`; `URSHL VD.T, VN.T, VM.T`.
5035/// Operands: `rd`, `rn`, `rm`.
5036pub trait UrshlEmitter<T0, T1, T2> {
5037    fn urshl(&mut self, rd: T0, rn: T1, rm: T2);
5038}
5039
5040/// Emits the `URSHR` instruction.
5041/// Assembly forms: `URSHR DD, DN, #N`; `URSHR VD.T, VN.T, #N`; `URSHR VD.T, VN.T, #N`.
5042/// Operands: `rd`, `rn`, `shift`.
5043pub trait UrshrEmitter<T0, T1, T2> {
5044    fn urshr(&mut self, rd: T0, rn: T1, shift: T2);
5045}
5046
5047/// Emits the `URSQRTE` instruction.
5048/// Assembly forms: `URSQRTE VD.2S, VN.2S`; `URSQRTE VD.4S, VN.4S`.
5049/// Operands: `rd`, `rn`.
5050pub trait UrsqrteEmitter<T0, T1> {
5051    fn ursqrte(&mut self, rd: T0, rn: T1);
5052}
5053
5054/// Emits the `URSRA` instruction.
5055/// Assembly forms: `URSRA DX, DN, #N`; `URSRA VX.T, VN.T, #N`; `URSRA VX.T, VN.T, #N`.
5056/// Operands: `operand_1`, `rn`, `shift`.
5057pub trait UrsraEmitter<T0, T1, T2> {
5058    fn ursra(&mut self, operand_1: T0, rn: T1, shift: T2);
5059}
5060
5061/// Emits the `USHL` instruction.
5062/// Assembly forms: `USHL DD, DN, DM`; `USHL VD.T, VN.T, VM.T`; `USHL VD.T, VN.T, VM.T`.
5063/// Operands: `rd`, `rn`, `rm`.
5064pub trait UshlEmitter<T0, T1, T2> {
5065    fn ushl(&mut self, rd: T0, rn: T1, rm: T2);
5066}
5067
5068/// Emits the `USHLL` instruction.
5069/// Assembly forms: `USHLL VD.TA, VN.TB, #N`.
5070/// Operands: `rd`, `rn`, `shift`.
5071pub trait UshllEmitter<T0, T1, T2> {
5072    fn ushll(&mut self, rd: T0, rn: T1, shift: T2);
5073}
5074
5075/// Emits the `USHLL2` instruction.
5076/// Assembly forms: `USHLL2 VD.TA, VN.TB, #N`.
5077/// Operands: `rd`, `rn`, `shift`.
5078pub trait Ushll2Emitter<T0, T1, T2> {
5079    fn ushll2(&mut self, rd: T0, rn: T1, shift: T2);
5080}
5081
5082/// Emits the `USHR` instruction.
5083/// Assembly forms: `USHR DD, DN, #N`; `USHR VD.T, VN.T, #N`; `USHR VD.T, VN.T, #N`.
5084/// Operands: `rd`, `rn`, `shift`.
5085pub trait UshrEmitter<T0, T1, T2> {
5086    fn ushr(&mut self, rd: T0, rn: T1, shift: T2);
5087}
5088
5089/// Emits the `USQADD` instruction.
5090/// Assembly forms: `USQADD BX, BN`; `USQADD HX, HN`; `USQADD SX, SN`; `USQADD DX, DN` (and related forms).
5091/// Operands: `operand_1`, `rn`.
5092pub trait UsqaddEmitter<T0, T1> {
5093    fn usqadd(&mut self, operand_1: T0, rn: T1);
5094}
5095
5096/// Emits the `USRA` instruction.
5097/// Assembly forms: `USRA DX, DN, #N`; `USRA VX.T, VN.T, #N`; `USRA VX.T, VN.T, #N`.
5098/// Operands: `operand_1`, `rn`, `shift`.
5099pub trait UsraEmitter<T0, T1, T2> {
5100    fn usra(&mut self, operand_1: T0, rn: T1, shift: T2);
5101}
5102
5103/// Emits the `USUBL` instruction.
5104/// Assembly forms: `USUBL VD.TA, VN.TB, VM.TB`.
5105/// Operands: `rd`, `rn`, `rm`.
5106pub trait UsublEmitter<T0, T1, T2> {
5107    fn usubl(&mut self, rd: T0, rn: T1, rm: T2);
5108}
5109
5110/// Emits the `USUBL2` instruction.
5111/// Assembly forms: `USUBL2 VD.TA, VN.TB, VM.TB`.
5112/// Operands: `rd`, `rn`, `rm`.
5113pub trait Usubl2Emitter<T0, T1, T2> {
5114    fn usubl2(&mut self, rd: T0, rn: T1, rm: T2);
5115}
5116
5117/// Emits the `USUBW` instruction.
5118/// Assembly forms: `USUBW VD.TA, VN.TA, VM.TB`.
5119/// Operands: `rd`, `rn`, `rm`.
5120pub trait UsubwEmitter<T0, T1, T2> {
5121    fn usubw(&mut self, rd: T0, rn: T1, rm: T2);
5122}
5123
5124/// Emits the `USUBW2` instruction.
5125/// Assembly forms: `USUBW2 VD.TA, VN.TA, VM.TB`.
5126/// Operands: `rd`, `rn`, `rm`.
5127pub trait Usubw2Emitter<T0, T1, T2> {
5128    fn usubw2(&mut self, rd: T0, rn: T1, rm: T2);
5129}
5130
5131/// Emits the `UXTL` instruction.
5132/// Assembly forms: `UXTL VD.TA, VN.TB`.
5133/// Operands: `rd`, `rn`.
5134pub trait UxtlEmitter<T0, T1> {
5135    fn uxtl(&mut self, rd: T0, rn: T1);
5136}
5137
5138/// Emits the `UXTL2` instruction.
5139/// Assembly forms: `UXTL2 VD.TA, VN.TB`.
5140/// Operands: `rd`, `rn`.
5141pub trait Uxtl2Emitter<T0, T1> {
5142    fn uxtl2(&mut self, rd: T0, rn: T1);
5143}
5144
5145/// Emits the `UZP1` instruction.
5146/// Assembly forms: `UZP1 VD.T, VN.T, VM.T`; `UZP1 VD.T, VN.T, VM.T`.
5147/// Operands: `rd`, `rn`, `rm`.
5148pub trait Uzp1Emitter<T0, T1, T2> {
5149    fn uzp1(&mut self, rd: T0, rn: T1, rm: T2);
5150}
5151
5152/// Emits the `UZP2` instruction.
5153/// Assembly forms: `UZP2 VD.T, VN.T, VM.T`; `UZP2 VD.T, VN.T, VM.T`.
5154/// Operands: `rd`, `rn`, `rm`.
5155pub trait Uzp2Emitter<T0, T1, T2> {
5156    fn uzp2(&mut self, rd: T0, rn: T1, rm: T2);
5157}
5158
5159/// Emits the `XTN` instruction.
5160/// Assembly forms: `XTN VD.TA, VN.TB`.
5161/// Operands: `rd`, `rn`.
5162pub trait XtnEmitter<T0, T1> {
5163    fn xtn(&mut self, rd: T0, rn: T1);
5164}
5165
5166/// Emits the `XTN2` instruction.
5167/// Assembly forms: `XTN2 VX.TA, VN.TB`.
5168/// Operands: `operand_1`, `rn`.
5169pub trait Xtn2Emitter<T0, T1> {
5170    fn xtn2(&mut self, operand_1: T0, rn: T1);
5171}
5172
5173/// Emits the `ZIP1` instruction.
5174/// Assembly forms: `ZIP1 VD.T, VN.T, VM.T`; `ZIP1 VD.T, VN.T, VM.T`.
5175/// Operands: `rd`, `rn`, `rm`.
5176pub trait Zip1Emitter<T0, T1, T2> {
5177    fn zip1(&mut self, rd: T0, rn: T1, rm: T2);
5178}
5179
5180/// Emits the `ZIP2` instruction.
5181/// Assembly forms: `ZIP2 VD.T, VN.T, VM.T`; `ZIP2 VD.T, VN.T, VM.T`.
5182/// Operands: `rd`, `rn`, `rm`.
5183pub trait Zip2Emitter<T0, T1, T2> {
5184    fn zip2(&mut self, rd: T0, rn: T1, rm: T2);
5185}
5186
5187/// Emits the `AESD` instruction.
5188/// Assembly forms: `AESD VD.16B, VN.16B`.
5189/// Operands: `rd`, `rn`.
5190pub trait AesdEmitter<T0, T1> {
5191    fn aesd(&mut self, rd: T0, rn: T1);
5192}
5193
5194/// Emits the `AESE` instruction.
5195/// Assembly forms: `AESE VD.16B, VN.16B`.
5196/// Operands: `rd`, `rn`.
5197pub trait AeseEmitter<T0, T1> {
5198    fn aese(&mut self, rd: T0, rn: T1);
5199}
5200
5201/// Emits the `AESIMC` instruction.
5202/// Assembly forms: `AESIMC VD.16B, VN.16B`.
5203/// Operands: `rd`, `rn`.
5204pub trait AesimcEmitter<T0, T1> {
5205    fn aesimc(&mut self, rd: T0, rn: T1);
5206}
5207
5208/// Emits the `AESMC` instruction.
5209/// Assembly forms: `AESMC VD.16B, VN.16B`.
5210/// Operands: `rd`, `rn`.
5211pub trait AesmcEmitter<T0, T1> {
5212    fn aesmc(&mut self, rd: T0, rn: T1);
5213}
5214
5215/// Emits the `SHA1C` instruction.
5216/// Assembly forms: `SHA1C QX, SN, VM.4S`.
5217/// Operands: `operand_1`, `rn`, `rm`.
5218pub trait Sha1cEmitter<T0, T1, T2> {
5219    fn sha1c(&mut self, operand_1: T0, rn: T1, rm: T2);
5220}
5221
5222/// Emits the `SHA1H` instruction.
5223/// Assembly forms: `SHA1H SD, SN`.
5224/// Operands: `rd`, `rn`.
5225pub trait Sha1hEmitter<T0, T1> {
5226    fn sha1h(&mut self, rd: T0, rn: T1);
5227}
5228
5229/// Emits the `SHA1M` instruction.
5230/// Assembly forms: `SHA1M QX, SN, VM.4S`.
5231/// Operands: `operand_1`, `rn`, `rm`.
5232pub trait Sha1mEmitter<T0, T1, T2> {
5233    fn sha1m(&mut self, operand_1: T0, rn: T1, rm: T2);
5234}
5235
5236/// Emits the `SHA1P` instruction.
5237/// Assembly forms: `SHA1P QX, SN, VM.4S`.
5238/// Operands: `operand_1`, `rn`, `rm`.
5239pub trait Sha1pEmitter<T0, T1, T2> {
5240    fn sha1p(&mut self, operand_1: T0, rn: T1, rm: T2);
5241}
5242
5243/// Emits the `SHA1SU0` instruction.
5244/// Assembly forms: `SHA1SU0 VX.4S, VN.4S, VM.4S`.
5245/// Operands: `operand_1`, `rn`, `rm`.
5246pub trait Sha1su0Emitter<T0, T1, T2> {
5247    fn sha1su0(&mut self, operand_1: T0, rn: T1, rm: T2);
5248}
5249
5250/// Emits the `SHA1SU1` instruction.
5251/// Assembly forms: `SHA1SU1 VX.4S, VN.4S`.
5252/// Operands: `operand_1`, `rn`.
5253pub trait Sha1su1Emitter<T0, T1> {
5254    fn sha1su1(&mut self, operand_1: T0, rn: T1);
5255}
5256
5257/// Emits the `SHA256H` instruction.
5258/// Assembly forms: `SHA256H QX, QN, VM.4S`.
5259/// Operands: `operand_1`, `rn`, `rm`.
5260pub trait Sha256hEmitter<T0, T1, T2> {
5261    fn sha256h(&mut self, operand_1: T0, rn: T1, rm: T2);
5262}
5263
5264/// Emits the `SHA256H2` instruction.
5265/// Assembly forms: `SHA256H2 QX, QN, VM.4S`.
5266/// Operands: `operand_1`, `rn`, `rm`.
5267pub trait Sha256h2Emitter<T0, T1, T2> {
5268    fn sha256h2(&mut self, operand_1: T0, rn: T1, rm: T2);
5269}
5270
5271/// Emits the `SHA256SU0` instruction.
5272/// Assembly forms: `SHA256SU0 VX.4S, VN.4S`.
5273/// Operands: `operand_1`, `rn`.
5274pub trait Sha256su0Emitter<T0, T1> {
5275    fn sha256su0(&mut self, operand_1: T0, rn: T1);
5276}
5277
5278/// Emits the `SHA256SU1` instruction.
5279/// Assembly forms: `SHA256SU1 VX.4S, VN.4S, VM.4S`.
5280/// Operands: `operand_1`, `rn`, `rm`.
5281pub trait Sha256su1Emitter<T0, T1, T2> {
5282    fn sha256su1(&mut self, operand_1: T0, rn: T1, rm: T2);
5283}
5284
5285/// Emits the `SQRDMLAH` instruction.
5286/// Assembly forms: `SQRDMLAH HX, HN, HM`; `SQRDMLAH SX, SN, SM`; `SQRDMLAH HX, HN, VN.H[#IDX]`; `SQRDMLAH SX, SN, VN.S[#IDX]` (and related forms).
5287/// Operands: `operand_1`, `rn`, `rm_or_rn`.
5288pub trait SqrdmlahEmitter<T0, T1, T2> {
5289    fn sqrdmlah(&mut self, operand_1: T0, rn: T1, rm_or_rn: T2);
5290}
5291
5292/// Emits the `SQRDMLSH` instruction.
5293/// Assembly forms: `SQRDMLSH HX, HN, HM`; `SQRDMLSH SX, SN, SM`; `SQRDMLSH HX, HN, VN.H[#IDX]`; `SQRDMLSH SX, SN, VN.S[#IDX]` (and related forms).
5294/// Operands: `operand_1`, `rn`, `rm_or_rn`.
5295pub trait SqrdmlshEmitter<T0, T1, T2> {
5296    fn sqrdmlsh(&mut self, operand_1: T0, rn: T1, rm_or_rn: T2);
5297}
5298
5299/// Emits the `FCADD` instruction.
5300/// Assembly forms: `FCADD VD.T, VN.T, VM.T, #ROTATE`; `FCADD VD.T, VN.T, VM.T, #ROTATE`.
5301/// Operands: `rd`, `rn`, `rm`, `rotate`.
5302pub trait FcaddEmitter<T0, T1, T2, T3> {
5303    fn fcadd(&mut self, rd: T0, rn: T1, rm: T2, rotate: T3);
5304}
5305
5306/// Emits the `FCMLA` instruction.
5307/// Assembly forms: `FCMLA VD.T, VN.T, VM.T, #ROTATE`; `FCMLA VD.T, VN.T, VM.T, #ROTATE`; `FCMLA VD.4H, VN.4H, VM.H[#IDX], #ROTATE`; `FCMLA VD.8H, VN.8H, VM.H[#IDX], #ROTATE` (and related forms).
5308/// Operands: `rd`, `rn`, `rm`, `rotate`.
5309pub trait FcmlaEmitter<T0, T1, T2, T3> {
5310    fn fcmla(&mut self, rd: T0, rn: T1, rm: T2, rotate: T3);
5311}
5312
5313/// Emits the `FJCVTZS` instruction.
5314/// Assembly forms: `FJCVTZS WD, DN`.
5315/// Operands: `rd`, `rn`.
5316pub trait FjcvtzsEmitter<T0, T1> {
5317    fn fjcvtzs(&mut self, rd: T0, rn: T1);
5318}
5319
5320/// Emits the `FMLAL` instruction.
5321/// Assembly forms: `FMLAL VX.2S, VN.2H, VM.2H`; `FMLAL VX.4S, VN.4H, VM.4H`; `FMLAL VX.2S, VN.2H, VM.H[#IDX]`; `FMLAL VX.4S, VN.4H, VM.H[#IDX]`.
5322/// Operands: `operand_1`, `rn`, `rm`.
5323pub trait FmlalEmitter<T0, T1, T2> {
5324    fn fmlal(&mut self, operand_1: T0, rn: T1, rm: T2);
5325}
5326
5327/// Emits the `FMLAL2` instruction.
5328/// Assembly forms: `FMLAL2 VX.2S, VN.2H, VM.2H`; `FMLAL2 VX.4S, VN.4H, VM.4H`; `FMLAL2 VX.2S, VN.2H, VM.H[#IDX]`; `FMLAL2 VX.4S, VN.4H, VM.H[#IDX]`.
5329/// Operands: `operand_1`, `rn`, `rm`.
5330pub trait Fmlal2Emitter<T0, T1, T2> {
5331    fn fmlal2(&mut self, operand_1: T0, rn: T1, rm: T2);
5332}
5333
5334/// Emits the `FMLSL` instruction.
5335/// Assembly forms: `FMLSL VX.2S, VN.2H, VM.2H`; `FMLSL VX.4S, VN.4H, VM.4H`; `FMLSL VX.2S, VN.2H, VM.H[#IDX]`; `FMLSL VX.4S, VN.4H, VM.H[#IDX]`.
5336/// Operands: `operand_1`, `rn`, `rm`.
5337pub trait FmlslEmitter<T0, T1, T2> {
5338    fn fmlsl(&mut self, operand_1: T0, rn: T1, rm: T2);
5339}
5340
5341/// Emits the `FMLSL2` instruction.
5342/// Assembly forms: `FMLSL2 VX.2S, VN.2H, VM.2H`; `FMLSL2 VX.4S, VN.4H, VM.4H`; `FMLSL2 VX.2S, VN.2H, VM.H[#IDX]`; `FMLSL2 VX.4S, VN.4H, VM.H[#IDX]`.
5343/// Operands: `operand_1`, `rn`, `rm`.
5344pub trait Fmlsl2Emitter<T0, T1, T2> {
5345    fn fmlsl2(&mut self, operand_1: T0, rn: T1, rm: T2);
5346}
5347
5348/// Emits the `BCAX` instruction.
5349/// Assembly forms: `BCAX VD.16B, VN.16B, VM.16B, VA.16B`.
5350/// Operands: `rd`, `rn`, `rm`, `operand_4`.
5351pub trait BcaxEmitter<T0, T1, T2, T3> {
5352    fn bcax(&mut self, rd: T0, rn: T1, rm: T2, operand_4: T3);
5353}
5354
5355/// Emits the `EOR3` instruction.
5356/// Assembly forms: `EOR3 VD.16B, VN.16B, VM.16B, VA.16B`.
5357/// Operands: `rd`, `rn`, `rm`, `operand_4`.
5358pub trait Eor3Emitter<T0, T1, T2, T3> {
5359    fn eor3(&mut self, rd: T0, rn: T1, rm: T2, operand_4: T3);
5360}
5361
5362/// Emits the `RAX1` instruction.
5363/// Assembly forms: `RAX1 VD.2D, VN.2D, VM.2D`.
5364/// Operands: `rd`, `rn`, `rm`.
5365pub trait Rax1Emitter<T0, T1, T2> {
5366    fn rax1(&mut self, rd: T0, rn: T1, rm: T2);
5367}
5368
5369/// Emits the `XAR` instruction.
5370/// Assembly forms: `XAR VD.2D, VN.2D, VM.2D, #IMM`.
5371/// Operands: `rd`, `rn`, `rm`, `imm`.
5372pub trait XarEmitter<T0, T1, T2, T3> {
5373    fn xar(&mut self, rd: T0, rn: T1, rm: T2, imm: T3);
5374}
5375
5376/// Emits the `SHA512H` instruction.
5377/// Assembly forms: `SHA512H QX, QN, VM.2D`.
5378/// Operands: `operand_1`, `rn`, `rm`.
5379pub trait Sha512hEmitter<T0, T1, T2> {
5380    fn sha512h(&mut self, operand_1: T0, rn: T1, rm: T2);
5381}
5382
5383/// Emits the `SHA512H2` instruction.
5384/// Assembly forms: `SHA512H2 QX, QN, VM.2D`.
5385/// Operands: `operand_1`, `rn`, `rm`.
5386pub trait Sha512h2Emitter<T0, T1, T2> {
5387    fn sha512h2(&mut self, operand_1: T0, rn: T1, rm: T2);
5388}
5389
5390/// Emits the `SHA512SU0` instruction.
5391/// Assembly forms: `SHA512SU0 VX.2D, VN.2D`.
5392/// Operands: `operand_1`, `rn`.
5393pub trait Sha512su0Emitter<T0, T1> {
5394    fn sha512su0(&mut self, operand_1: T0, rn: T1);
5395}
5396
5397/// Emits the `SHA512SU1` instruction.
5398/// Assembly forms: `SHA512SU1 VX.2D, VN.2D, VM.2D`.
5399/// Operands: `operand_1`, `rn`, `rm`.
5400pub trait Sha512su1Emitter<T0, T1, T2> {
5401    fn sha512su1(&mut self, operand_1: T0, rn: T1, rm: T2);
5402}
5403
5404/// Emits the `SM3PARTW1` instruction.
5405/// Assembly forms: `SM3PARTW1 VX.4S, VN.4S, VM.4S`.
5406/// Operands: `operand_1`, `rn`, `rm`.
5407pub trait Sm3partw1Emitter<T0, T1, T2> {
5408    fn sm3partw1(&mut self, operand_1: T0, rn: T1, rm: T2);
5409}
5410
5411/// Emits the `SM3PARTW2` instruction.
5412/// Assembly forms: `SM3PARTW2 VX.4S, VN.4S, VM.4S`.
5413/// Operands: `operand_1`, `rn`, `rm`.
5414pub trait Sm3partw2Emitter<T0, T1, T2> {
5415    fn sm3partw2(&mut self, operand_1: T0, rn: T1, rm: T2);
5416}
5417
5418/// Emits the `SM3SS1` instruction.
5419/// Assembly forms: `SM3SS1 VD.4S, VN.4S, VM.4S, VA.4S`.
5420/// Operands: `rd`, `rn`, `rm`, `operand_4`.
5421pub trait Sm3ss1Emitter<T0, T1, T2, T3> {
5422    fn sm3ss1(&mut self, rd: T0, rn: T1, rm: T2, operand_4: T3);
5423}
5424
5425/// Emits the `SM3TT1A` instruction.
5426/// Assembly forms: `SM3TT1A VX.4S, VN.4S, VM.4[#IDX]`.
5427/// Operands: `operand_1`, `rn`, `rm`.
5428pub trait Sm3tt1aEmitter<T0, T1, T2> {
5429    fn sm3tt1a(&mut self, operand_1: T0, rn: T1, rm: T2);
5430}
5431
5432/// Emits the `SM3TT1B` instruction.
5433/// Assembly forms: `SM3TT1B VX.4S, VN.4S, VM.4[#IDX]`.
5434/// Operands: `operand_1`, `rn`, `rm`.
5435pub trait Sm3tt1bEmitter<T0, T1, T2> {
5436    fn sm3tt1b(&mut self, operand_1: T0, rn: T1, rm: T2);
5437}
5438
5439/// Emits the `SM3TT2A` instruction.
5440/// Assembly forms: `SM3TT2A VX.4S, VN.4S, VM.4[#IDX]`.
5441/// Operands: `operand_1`, `rn`, `rm`.
5442pub trait Sm3tt2aEmitter<T0, T1, T2> {
5443    fn sm3tt2a(&mut self, operand_1: T0, rn: T1, rm: T2);
5444}
5445
5446/// Emits the `SM3TT2B` instruction.
5447/// Assembly forms: `SM3TT2B VX.4S, VN.4S, VM.4[#IDX]`.
5448/// Operands: `operand_1`, `rn`, `rm`.
5449pub trait Sm3tt2bEmitter<T0, T1, T2> {
5450    fn sm3tt2b(&mut self, operand_1: T0, rn: T1, rm: T2);
5451}
5452
5453/// Emits the `SM4E` instruction.
5454/// Assembly forms: `SM4E VX.4S, VN.4S`.
5455/// Operands: `operand_1`, `rn`.
5456pub trait Sm4eEmitter<T0, T1> {
5457    fn sm4e(&mut self, operand_1: T0, rn: T1);
5458}
5459
5460/// Emits the `SM4EKEY` instruction.
5461/// Assembly forms: `SM4EKEY VD.4S, VN.4S, VM.4S`.
5462/// Operands: `rd`, `rn`, `rm`.
5463pub trait Sm4ekeyEmitter<T0, T1, T2> {
5464    fn sm4ekey(&mut self, rd: T0, rn: T1, rm: T2);
5465}
5466
5467/// Emits the `SDOT` instruction.
5468/// Assembly forms: `SDOT VX.2S, VN.8B, VM.8B`; `SDOT VX.4S, VN.16B, VM.16B`; `SDOT VX.2S, VN.8B, VM.4B[#IDX]`; `SDOT VX.4S, VN.16B, VM.4B[#IDX]`.
5469/// Operands: `operand_1`, `rn`, `rm`.
5470pub trait SdotEmitter<T0, T1, T2> {
5471    fn sdot(&mut self, operand_1: T0, rn: T1, rm: T2);
5472}
5473
5474/// Emits the `UDOT` instruction.
5475/// Assembly forms: `UDOT VX.2S, VN.8B, VM.8B`; `UDOT VX.4S, VN.16B, VM.16B`; `UDOT VX.2S, VN.8B, VM.4B[#IDX]`; `UDOT VX.4S, VN.16B, VM.4B[#IDX]`.
5476/// Operands: `operand_1`, `rn`, `rm`.
5477pub trait UdotEmitter<T0, T1, T2> {
5478    fn udot(&mut self, operand_1: T0, rn: T1, rm: T2);
5479}
5480
5481/// Emits the `BFCVT` instruction.
5482/// Assembly forms: `BFCVT HD, SN`.
5483/// Operands: `rd`, `rn`.
5484pub trait BfcvtEmitter<T0, T1> {
5485    fn bfcvt(&mut self, rd: T0, rn: T1);
5486}
5487
5488/// Emits the `BFCVTN` instruction.
5489/// Assembly forms: `BFCVTN VD.4H, VN.4S`.
5490/// Operands: `rd`, `rn`.
5491pub trait BfcvtnEmitter<T0, T1> {
5492    fn bfcvtn(&mut self, rd: T0, rn: T1);
5493}
5494
5495/// Emits the `BFCVTN2` instruction.
5496/// Assembly forms: `BFCVTN2 VD.8H, VN.4S`.
5497/// Operands: `rd`, `rn`.
5498pub trait Bfcvtn2Emitter<T0, T1> {
5499    fn bfcvtn2(&mut self, rd: T0, rn: T1);
5500}
5501
5502/// Emits the `BFMLALB` instruction.
5503/// Assembly forms: `BFMLALB VX.4S, VN.8H, VM.8H`; `BFMLALB VX.4S, VN.8H, VM.H[#IDX]`.
5504/// Operands: `operand_1`, `rn`, `rm`.
5505pub trait BfmlalbEmitter<T0, T1, T2> {
5506    fn bfmlalb(&mut self, operand_1: T0, rn: T1, rm: T2);
5507}
5508
5509/// Emits the `BFMLALT` instruction.
5510/// Assembly forms: `BFMLALT VX.4S, VN.8H, VM.8H`; `BFMLALT VX.4S, VN.8H, VM.H[#IDX]`.
5511/// Operands: `operand_1`, `rn`, `rm`.
5512pub trait BfmlaltEmitter<T0, T1, T2> {
5513    fn bfmlalt(&mut self, operand_1: T0, rn: T1, rm: T2);
5514}
5515
5516/// Emits the `BFMMLA` instruction.
5517/// Assembly forms: `BFMMLA VX.4S, VN.8H, VM.8H`.
5518/// Operands: `operand_1`, `rn`, `rm`.
5519pub trait BfmmlaEmitter<T0, T1, T2> {
5520    fn bfmmla(&mut self, operand_1: T0, rn: T1, rm: T2);
5521}
5522
5523/// Emits the `BFDOT` instruction.
5524/// Assembly forms: `BFDOT VX.2S, VN.4H, VM.4H`; `BFDOT VX.4S, VN.8H, VM.8H`; `BFDOT VX.2S, VN.4H, VM.2H[#IDX]`; `BFDOT VX.4S, VN.8H, VM.2H[#IDX]`.
5525/// Operands: `operand_1`, `rn`, `rm`.
5526pub trait BfdotEmitter<T0, T1, T2> {
5527    fn bfdot(&mut self, operand_1: T0, rn: T1, rm: T2);
5528}
5529
5530/// Emits the `SMMLA` instruction.
5531/// Assembly forms: `SMMLA VX.4S, VN.16B, VM.16B`.
5532/// Operands: `operand_1`, `rn`, `rm`.
5533pub trait SmmlaEmitter<T0, T1, T2> {
5534    fn smmla(&mut self, operand_1: T0, rn: T1, rm: T2);
5535}
5536
5537/// Emits the `SUDOT` instruction.
5538/// Assembly forms: `SUDOT VX.2S, VN.8B, VM.4B[#IDX]`; `SUDOT VX.4S, VN.16B, VM.4B[#IDX]`.
5539/// Operands: `operand_1`, `rn`, `rm`.
5540pub trait SudotEmitter<T0, T1, T2> {
5541    fn sudot(&mut self, operand_1: T0, rn: T1, rm: T2);
5542}
5543
5544/// Emits the `UMMLA` instruction.
5545/// Assembly forms: `UMMLA VX.4S, VN.16B, VM.16B`.
5546/// Operands: `operand_1`, `rn`, `rm`.
5547pub trait UmmlaEmitter<T0, T1, T2> {
5548    fn ummla(&mut self, operand_1: T0, rn: T1, rm: T2);
5549}
5550
5551/// Emits the `USDOT` instruction.
5552/// Assembly forms: `USDOT VX.2S, VN.8B, VM.TB`; `USDOT VX.4S, VN.16B, VM.TB`; `USDOT VX.2S, VN.8B, VM.4B[#IDX]`; `USDOT VX.4S, VN.16B, VM.4B[#IDX]`.
5553/// Operands: `operand_1`, `rn`, `rm`.
5554pub trait UsdotEmitter<T0, T1, T2> {
5555    fn usdot(&mut self, operand_1: T0, rn: T1, rm: T2);
5556}
5557
5558/// Emits the `USMMLA` instruction.
5559/// Assembly forms: `USMMLA VX.4S, VN.16B, VM.16B`.
5560/// Operands: `operand_1`, `rn`, `rm`.
5561pub trait UsmmlaEmitter<T0, T1, T2> {
5562    fn usmmla(&mut self, operand_1: T0, rn: T1, rm: T2);
5563}
5564
5565impl AdcEmitter<Gp, Gp, Gp> for Assembler<'_> {
5566    fn adc(&mut self, rd: Gp, rn: Gp, rm: Gp) {
5567        self.emit_n(
5568            InstId::Adc,
5569            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
5570        );
5571    }
5572}
5573
5574impl AdcsEmitter<Gp, Gp, Gp> for Assembler<'_> {
5575    fn adcs(&mut self, rd: Gp, rn: Gp, rm: Gp) {
5576        self.emit_n(
5577            InstId::Adcs,
5578            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
5579        );
5580    }
5581}
5582
5583impl AddEmitter<Gp, Gp, Gp> for Assembler<'_> {
5584    fn add(&mut self, rd: Gp, rn: Gp, rm_or_imm: Gp) {
5585        self.emit_n(
5586            InstId::Add,
5587            &[rd.as_operand(), rn.as_operand(), rm_or_imm.as_operand()],
5588        );
5589    }
5590}
5591
5592impl AddEmitter<Gp, Gp, Imm> for Assembler<'_> {
5593    fn add(&mut self, rd: Gp, rn: Gp, rm_or_imm: Imm) {
5594        self.emit_n(
5595            InstId::Add,
5596            &[rd.as_operand(), rn.as_operand(), rm_or_imm.as_operand()],
5597        );
5598    }
5599}
5600
5601impl AddEmitter<Vec, Vec, Vec> for Assembler<'_> {
5602    fn add(&mut self, rd: Vec, rn: Vec, rm_or_imm: Vec) {
5603        self.emit_n(
5604            InstId::Add_v,
5605            &[rd.as_operand(), rn.as_operand(), rm_or_imm.as_operand()],
5606        );
5607    }
5608}
5609
5610impl Add4Emitter<Gp, Gp, Gp, Imm> for Assembler<'_> {
5611    fn add_4(&mut self, rd: Gp, rn: Gp, rm_or_imm: Gp, shift: Imm) {
5612        self.emit_n(
5613            InstId::Add,
5614            &[
5615                rd.as_operand(),
5616                rn.as_operand(),
5617                rm_or_imm.as_operand(),
5618                shift.as_operand(),
5619            ],
5620        );
5621    }
5622}
5623
5624impl Add4Emitter<Gp, Gp, Imm, Imm> for Assembler<'_> {
5625    fn add_4(&mut self, rd: Gp, rn: Gp, rm_or_imm: Imm, shift: Imm) {
5626        self.emit_n(
5627            InstId::Add,
5628            &[
5629                rd.as_operand(),
5630                rn.as_operand(),
5631                rm_or_imm.as_operand(),
5632                shift.as_operand(),
5633            ],
5634        );
5635    }
5636}
5637
5638impl AddsEmitter<Gp, Gp, Gp> for Assembler<'_> {
5639    fn adds(&mut self, rd: Gp, rn: Gp, rm_or_imm: Gp) {
5640        self.emit_n(
5641            InstId::Adds,
5642            &[rd.as_operand(), rn.as_operand(), rm_or_imm.as_operand()],
5643        );
5644    }
5645}
5646
5647impl AddsEmitter<Gp, Gp, Imm> for Assembler<'_> {
5648    fn adds(&mut self, rd: Gp, rn: Gp, rm_or_imm: Imm) {
5649        self.emit_n(
5650            InstId::Adds,
5651            &[rd.as_operand(), rn.as_operand(), rm_or_imm.as_operand()],
5652        );
5653    }
5654}
5655
5656impl Adds4Emitter<Gp, Gp, Gp, Imm> for Assembler<'_> {
5657    fn adds_4(&mut self, rd: Gp, rn: Gp, rm_or_imm: Gp, shift: Imm) {
5658        self.emit_n(
5659            InstId::Adds,
5660            &[
5661                rd.as_operand(),
5662                rn.as_operand(),
5663                rm_or_imm.as_operand(),
5664                shift.as_operand(),
5665            ],
5666        );
5667    }
5668}
5669
5670impl Adds4Emitter<Gp, Gp, Imm, Imm> for Assembler<'_> {
5671    fn adds_4(&mut self, rd: Gp, rn: Gp, rm_or_imm: Imm, shift: Imm) {
5672        self.emit_n(
5673            InstId::Adds,
5674            &[
5675                rd.as_operand(),
5676                rn.as_operand(),
5677                rm_or_imm.as_operand(),
5678                shift.as_operand(),
5679            ],
5680        );
5681    }
5682}
5683
5684impl AdrEmitter<Gp, Imm> for Assembler<'_> {
5685    fn adr(&mut self, rd: Gp, target: Imm) {
5686        self.emit_n(InstId::Adr, &[rd.as_operand(), target.as_operand()]);
5687    }
5688}
5689
5690impl AdrEmitter<Gp, Label> for Assembler<'_> {
5691    fn adr(&mut self, rd: Gp, target: Label) {
5692        self.emit_n(InstId::Adr, &[rd.as_operand(), target.as_operand()]);
5693    }
5694}
5695
5696impl AdrEmitter<Gp, Sym> for Assembler<'_> {
5697    fn adr(&mut self, rd: Gp, target: Sym) {
5698        self.emit_n(InstId::Adr, &[rd.as_operand(), target.as_operand()]);
5699    }
5700}
5701
5702impl AdrpEmitter<Gp, Imm> for Assembler<'_> {
5703    fn adrp(&mut self, rd: Gp, target: Imm) {
5704        self.emit_n(InstId::Adrp, &[rd.as_operand(), target.as_operand()]);
5705    }
5706}
5707
5708impl AdrpEmitter<Gp, Label> for Assembler<'_> {
5709    fn adrp(&mut self, rd: Gp, target: Label) {
5710        self.emit_n(InstId::Adrp, &[rd.as_operand(), target.as_operand()]);
5711    }
5712}
5713
5714impl AdrpEmitter<Gp, Sym> for Assembler<'_> {
5715    fn adrp(&mut self, rd: Gp, target: Sym) {
5716        self.emit_n(InstId::Adrp, &[rd.as_operand(), target.as_operand()]);
5717    }
5718}
5719
5720impl AndEmitter<Gp, Gp, Imm> for Assembler<'_> {
5721    fn and_(&mut self, rd: Gp, rn: Gp, rm_or_imm: Imm) {
5722        self.emit_n(
5723            InstId::And,
5724            &[rd.as_operand(), rn.as_operand(), rm_or_imm.as_operand()],
5725        );
5726    }
5727}
5728
5729impl AndEmitter<Gp, Gp, Gp> for Assembler<'_> {
5730    fn and_(&mut self, rd: Gp, rn: Gp, rm_or_imm: Gp) {
5731        self.emit_n(
5732            InstId::And,
5733            &[rd.as_operand(), rn.as_operand(), rm_or_imm.as_operand()],
5734        );
5735    }
5736}
5737
5738impl AndEmitter<Vec, Vec, Vec> for Assembler<'_> {
5739    fn and_(&mut self, rd: Vec, rn: Vec, rm_or_imm: Vec) {
5740        self.emit_n(
5741            InstId::And_v,
5742            &[rd.as_operand(), rn.as_operand(), rm_or_imm.as_operand()],
5743        );
5744    }
5745}
5746
5747impl And4Emitter<Gp, Gp, Gp, Imm> for Assembler<'_> {
5748    fn and__4(&mut self, rd: Gp, rn: Gp, rm: Gp, shift: Imm) {
5749        self.emit_n(
5750            InstId::And,
5751            &[
5752                rd.as_operand(),
5753                rn.as_operand(),
5754                rm.as_operand(),
5755                shift.as_operand(),
5756            ],
5757        );
5758    }
5759}
5760
5761impl AndsEmitter<Gp, Gp, Imm> for Assembler<'_> {
5762    fn ands(&mut self, rd: Gp, rn: Gp, rm_or_imm: Imm) {
5763        self.emit_n(
5764            InstId::Ands,
5765            &[rd.as_operand(), rn.as_operand(), rm_or_imm.as_operand()],
5766        );
5767    }
5768}
5769
5770impl AndsEmitter<Gp, Gp, Gp> for Assembler<'_> {
5771    fn ands(&mut self, rd: Gp, rn: Gp, rm_or_imm: Gp) {
5772        self.emit_n(
5773            InstId::Ands,
5774            &[rd.as_operand(), rn.as_operand(), rm_or_imm.as_operand()],
5775        );
5776    }
5777}
5778
5779impl Ands4Emitter<Gp, Gp, Gp, Imm> for Assembler<'_> {
5780    fn ands_4(&mut self, rd: Gp, rn: Gp, rm: Gp, shift: Imm) {
5781        self.emit_n(
5782            InstId::Ands,
5783            &[
5784                rd.as_operand(),
5785                rn.as_operand(),
5786                rm.as_operand(),
5787                shift.as_operand(),
5788            ],
5789        );
5790    }
5791}
5792
5793impl AsrEmitter<Gp, Gp, Imm> for Assembler<'_> {
5794    fn asr(&mut self, rd: Gp, rn: Gp, rm_or_shift: Imm) {
5795        self.emit_n(
5796            InstId::Asr,
5797            &[rd.as_operand(), rn.as_operand(), rm_or_shift.as_operand()],
5798        );
5799    }
5800}
5801
5802impl AsrEmitter<Gp, Gp, Gp> for Assembler<'_> {
5803    fn asr(&mut self, rd: Gp, rn: Gp, rm_or_shift: Gp) {
5804        self.emit_n(
5805            InstId::Asr,
5806            &[rd.as_operand(), rn.as_operand(), rm_or_shift.as_operand()],
5807        );
5808    }
5809}
5810
5811impl AsrvEmitter<Gp, Gp, Gp> for Assembler<'_> {
5812    fn asrv(&mut self, rd: Gp, rn: Gp, rm: Gp) {
5813        self.emit_n(
5814            InstId::Asrv,
5815            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
5816        );
5817    }
5818}
5819
5820impl AtEmitter<Imm, Gp> for Assembler<'_> {
5821    fn at(&mut self, at_op: Imm, rt: Gp) {
5822        self.emit_n(InstId::At, &[at_op.as_operand(), rt.as_operand()]);
5823    }
5824}
5825
5826impl BfcEmitter<Gp, Imm, Imm> for Assembler<'_> {
5827    fn bfc(&mut self, rd: Gp, lsb: Imm, width: Imm) {
5828        self.emit_n(
5829            InstId::Bfc,
5830            &[rd.as_operand(), lsb.as_operand(), width.as_operand()],
5831        );
5832    }
5833}
5834
5835impl BfiEmitter<Gp, Gp, Imm, Imm> for Assembler<'_> {
5836    fn bfi(&mut self, rd: Gp, rn: Gp, lsb: Imm, width: Imm) {
5837        self.emit_n(
5838            InstId::Bfi,
5839            &[
5840                rd.as_operand(),
5841                rn.as_operand(),
5842                lsb.as_operand(),
5843                width.as_operand(),
5844            ],
5845        );
5846    }
5847}
5848
5849impl BfmEmitter<Gp, Gp, Imm, Imm> for Assembler<'_> {
5850    fn bfm(&mut self, rd: Gp, rn: Gp, imm: Imm, imm_2: Imm) {
5851        self.emit_n(
5852            InstId::Bfm,
5853            &[
5854                rd.as_operand(),
5855                rn.as_operand(),
5856                imm.as_operand(),
5857                imm_2.as_operand(),
5858            ],
5859        );
5860    }
5861}
5862
5863impl BfxilEmitter<Gp, Gp, Imm, Imm> for Assembler<'_> {
5864    fn bfxil(&mut self, rd: Gp, rn: Gp, lsb: Imm, width: Imm) {
5865        self.emit_n(
5866            InstId::Bfxil,
5867            &[
5868                rd.as_operand(),
5869                rn.as_operand(),
5870                lsb.as_operand(),
5871                width.as_operand(),
5872            ],
5873        );
5874    }
5875}
5876
5877impl BicEmitter<Gp, Gp, Imm> for Assembler<'_> {
5878    fn bic(&mut self, rd: Gp, rn_or_imm: Gp, rm_or_shift: Imm) {
5879        self.emit_n(
5880            InstId::Bic,
5881            &[
5882                rd.as_operand(),
5883                rn_or_imm.as_operand(),
5884                rm_or_shift.as_operand(),
5885            ],
5886        );
5887    }
5888}
5889
5890impl BicEmitter<Gp, Gp, Gp> for Assembler<'_> {
5891    fn bic(&mut self, rd: Gp, rn_or_imm: Gp, rm_or_shift: Gp) {
5892        self.emit_n(
5893            InstId::Bic,
5894            &[
5895                rd.as_operand(),
5896                rn_or_imm.as_operand(),
5897                rm_or_shift.as_operand(),
5898            ],
5899        );
5900    }
5901}
5902
5903impl BicEmitter<Vec, Vec, Vec> for Assembler<'_> {
5904    fn bic(&mut self, rd: Vec, rn_or_imm: Vec, rm_or_shift: Vec) {
5905        self.emit_n(
5906            InstId::Bic_v,
5907            &[
5908                rd.as_operand(),
5909                rn_or_imm.as_operand(),
5910                rm_or_shift.as_operand(),
5911            ],
5912        );
5913    }
5914}
5915
5916impl BicEmitter<Vec, Imm, Imm> for Assembler<'_> {
5917    fn bic(&mut self, rd: Vec, rn_or_imm: Imm, rm_or_shift: Imm) {
5918        self.emit_n(
5919            InstId::Bic_v,
5920            &[
5921                rd.as_operand(),
5922                rn_or_imm.as_operand(),
5923                rm_or_shift.as_operand(),
5924            ],
5925        );
5926    }
5927}
5928
5929impl Bic4Emitter<Gp, Gp, Gp, Imm> for Assembler<'_> {
5930    fn bic_4(&mut self, rd: Gp, rn: Gp, rm: Gp, shift: Imm) {
5931        self.emit_n(
5932            InstId::Bic,
5933            &[
5934                rd.as_operand(),
5935                rn.as_operand(),
5936                rm.as_operand(),
5937                shift.as_operand(),
5938            ],
5939        );
5940    }
5941}
5942
5943impl BicsEmitter<Gp, Gp, Imm> for Assembler<'_> {
5944    fn bics(&mut self, rd: Gp, rn: Gp, rm: Imm) {
5945        self.emit_n(
5946            InstId::Bics,
5947            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
5948        );
5949    }
5950}
5951
5952impl BicsEmitter<Gp, Gp, Gp> for Assembler<'_> {
5953    fn bics(&mut self, rd: Gp, rn: Gp, rm: Gp) {
5954        self.emit_n(
5955            InstId::Bics,
5956            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
5957        );
5958    }
5959}
5960
5961impl Bics4Emitter<Gp, Gp, Gp, Imm> for Assembler<'_> {
5962    fn bics_4(&mut self, rd: Gp, rn: Gp, rm: Gp, shift: Imm) {
5963        self.emit_n(
5964            InstId::Bics,
5965            &[
5966                rd.as_operand(),
5967                rn.as_operand(),
5968                rm.as_operand(),
5969                shift.as_operand(),
5970            ],
5971        );
5972    }
5973}
5974
5975impl BrkEmitter<Imm> for Assembler<'_> {
5976    fn brk(&mut self, imm: Imm) {
5977        self.emit_n(InstId::Brk, &[imm.as_operand()]);
5978    }
5979}
5980
5981impl CcmnEmitter<Gp, Gp, Imm, Imm> for Assembler<'_> {
5982    fn ccmn(&mut self, rn: Gp, rm_or_imm: Gp, flags: Imm, condition: Imm) {
5983        self.emit_n(
5984            InstId::Ccmn,
5985            &[
5986                rn.as_operand(),
5987                rm_or_imm.as_operand(),
5988                flags.as_operand(),
5989                condition.as_operand(),
5990            ],
5991        );
5992    }
5993}
5994
5995impl CcmnEmitter<Gp, Imm, Imm, Imm> for Assembler<'_> {
5996    fn ccmn(&mut self, rn: Gp, rm_or_imm: Imm, flags: Imm, condition: Imm) {
5997        self.emit_n(
5998            InstId::Ccmn,
5999            &[
6000                rn.as_operand(),
6001                rm_or_imm.as_operand(),
6002                flags.as_operand(),
6003                condition.as_operand(),
6004            ],
6005        );
6006    }
6007}
6008
6009impl CcmpEmitter<Gp, Gp, Imm, Imm> for Assembler<'_> {
6010    fn ccmp(&mut self, rn: Gp, rm_or_imm: Gp, flags: Imm, condition: Imm) {
6011        self.emit_n(
6012            InstId::Ccmp,
6013            &[
6014                rn.as_operand(),
6015                rm_or_imm.as_operand(),
6016                flags.as_operand(),
6017                condition.as_operand(),
6018            ],
6019        );
6020    }
6021}
6022
6023impl CcmpEmitter<Gp, Imm, Imm, Imm> for Assembler<'_> {
6024    fn ccmp(&mut self, rn: Gp, rm_or_imm: Imm, flags: Imm, condition: Imm) {
6025        self.emit_n(
6026            InstId::Ccmp,
6027            &[
6028                rn.as_operand(),
6029                rm_or_imm.as_operand(),
6030                flags.as_operand(),
6031                condition.as_operand(),
6032            ],
6033        );
6034    }
6035}
6036
6037impl CincEmitter<Gp, Gp, Imm> for Assembler<'_> {
6038    fn cinc(&mut self, rd: Gp, rn: Gp, condition: Imm) {
6039        self.emit_n(
6040            InstId::Cinc,
6041            &[rd.as_operand(), rn.as_operand(), condition.as_operand()],
6042        );
6043    }
6044}
6045
6046impl CinvEmitter<Gp, Gp, Imm> for Assembler<'_> {
6047    fn cinv(&mut self, rd: Gp, rn: Gp, condition: Imm) {
6048        self.emit_n(
6049            InstId::Cinv,
6050            &[rd.as_operand(), rn.as_operand(), condition.as_operand()],
6051        );
6052    }
6053}
6054
6055impl ClrexEmitter<Imm> for Assembler<'_> {
6056    fn clrex(&mut self, imm: Imm) {
6057        self.emit_n(InstId::Clrex, &[imm.as_operand()]);
6058    }
6059}
6060
6061impl ClsEmitter<Gp, Gp> for Assembler<'_> {
6062    fn cls(&mut self, rd: Gp, rn: Gp) {
6063        self.emit_n(InstId::Cls, &[rd.as_operand(), rn.as_operand()]);
6064    }
6065}
6066
6067impl ClsEmitter<Vec, Vec> for Assembler<'_> {
6068    fn cls(&mut self, rd: Vec, rn: Vec) {
6069        self.emit_n(InstId::Cls_v, &[rd.as_operand(), rn.as_operand()]);
6070    }
6071}
6072
6073impl ClzEmitter<Gp, Gp> for Assembler<'_> {
6074    fn clz(&mut self, rd: Gp, rn: Gp) {
6075        self.emit_n(InstId::Clz, &[rd.as_operand(), rn.as_operand()]);
6076    }
6077}
6078
6079impl ClzEmitter<Vec, Vec> for Assembler<'_> {
6080    fn clz(&mut self, rd: Vec, rn: Vec) {
6081        self.emit_n(InstId::Clz_v, &[rd.as_operand(), rn.as_operand()]);
6082    }
6083}
6084
6085impl CmnEmitter<Gp, Gp> for Assembler<'_> {
6086    fn cmn(&mut self, rn: Gp, imm_or_rm: Gp) {
6087        self.emit_n(InstId::Cmn, &[rn.as_operand(), imm_or_rm.as_operand()]);
6088    }
6089}
6090
6091impl CmnEmitter<Gp, Imm> for Assembler<'_> {
6092    fn cmn(&mut self, rn: Gp, imm_or_rm: Imm) {
6093        self.emit_n(InstId::Cmn, &[rn.as_operand(), imm_or_rm.as_operand()]);
6094    }
6095}
6096
6097impl Cmn3Emitter<Gp, Gp, Imm> for Assembler<'_> {
6098    fn cmn_3(&mut self, rn: Gp, imm_or_rm: Gp, shift: Imm) {
6099        self.emit_n(
6100            InstId::Cmn,
6101            &[rn.as_operand(), imm_or_rm.as_operand(), shift.as_operand()],
6102        );
6103    }
6104}
6105
6106impl Cmn3Emitter<Gp, Imm, Imm> for Assembler<'_> {
6107    fn cmn_3(&mut self, rn: Gp, imm_or_rm: Imm, shift: Imm) {
6108        self.emit_n(
6109            InstId::Cmn,
6110            &[rn.as_operand(), imm_or_rm.as_operand(), shift.as_operand()],
6111        );
6112    }
6113}
6114
6115impl CmpEmitter<Gp, Gp> for Assembler<'_> {
6116    fn cmp(&mut self, rn: Gp, rm_or_imm: Gp) {
6117        self.emit_n(InstId::Cmp, &[rn.as_operand(), rm_or_imm.as_operand()]);
6118    }
6119}
6120
6121impl CmpEmitter<Gp, Imm> for Assembler<'_> {
6122    fn cmp(&mut self, rn: Gp, rm_or_imm: Imm) {
6123        self.emit_n(InstId::Cmp, &[rn.as_operand(), rm_or_imm.as_operand()]);
6124    }
6125}
6126
6127impl Cmp3Emitter<Gp, Gp, Imm> for Assembler<'_> {
6128    fn cmp_3(&mut self, rn: Gp, rm_or_imm: Gp, shift: Imm) {
6129        self.emit_n(
6130            InstId::Cmp,
6131            &[rn.as_operand(), rm_or_imm.as_operand(), shift.as_operand()],
6132        );
6133    }
6134}
6135
6136impl Cmp3Emitter<Gp, Imm, Imm> for Assembler<'_> {
6137    fn cmp_3(&mut self, rn: Gp, rm_or_imm: Imm, shift: Imm) {
6138        self.emit_n(
6139            InstId::Cmp,
6140            &[rn.as_operand(), rm_or_imm.as_operand(), shift.as_operand()],
6141        );
6142    }
6143}
6144
6145impl CnegEmitter<Gp, Gp, Imm> for Assembler<'_> {
6146    fn cneg(&mut self, rd: Gp, rn: Gp, condition: Imm) {
6147        self.emit_n(
6148            InstId::Cneg,
6149            &[rd.as_operand(), rn.as_operand(), condition.as_operand()],
6150        );
6151    }
6152}
6153
6154impl CselEmitter<Gp, Gp, Gp, Imm> for Assembler<'_> {
6155    fn csel(&mut self, rd: Gp, rn: Gp, rm: Gp, condition: Imm) {
6156        self.emit_n(
6157            InstId::Csel,
6158            &[
6159                rd.as_operand(),
6160                rn.as_operand(),
6161                rm.as_operand(),
6162                condition.as_operand(),
6163            ],
6164        );
6165    }
6166}
6167
6168impl CsetEmitter<Gp, Imm> for Assembler<'_> {
6169    fn cset(&mut self, rd: Gp, condition: Imm) {
6170        self.emit_n(InstId::Cset, &[rd.as_operand(), condition.as_operand()]);
6171    }
6172}
6173
6174impl CsetmEmitter<Gp, Imm> for Assembler<'_> {
6175    fn csetm(&mut self, rd: Gp, condition: Imm) {
6176        self.emit_n(InstId::Csetm, &[rd.as_operand(), condition.as_operand()]);
6177    }
6178}
6179
6180impl CsincEmitter<Gp, Gp, Gp, Imm> for Assembler<'_> {
6181    fn csinc(&mut self, rd: Gp, rn: Gp, rm: Gp, condition: Imm) {
6182        self.emit_n(
6183            InstId::Csinc,
6184            &[
6185                rd.as_operand(),
6186                rn.as_operand(),
6187                rm.as_operand(),
6188                condition.as_operand(),
6189            ],
6190        );
6191    }
6192}
6193
6194impl CsinvEmitter<Gp, Gp, Gp, Imm> for Assembler<'_> {
6195    fn csinv(&mut self, rd: Gp, rn: Gp, rm: Gp, condition: Imm) {
6196        self.emit_n(
6197            InstId::Csinv,
6198            &[
6199                rd.as_operand(),
6200                rn.as_operand(),
6201                rm.as_operand(),
6202                condition.as_operand(),
6203            ],
6204        );
6205    }
6206}
6207
6208impl CsnegEmitter<Gp, Gp, Gp, Imm> for Assembler<'_> {
6209    fn csneg(&mut self, rd: Gp, rn: Gp, rm: Gp, condition: Imm) {
6210        self.emit_n(
6211            InstId::Csneg,
6212            &[
6213                rd.as_operand(),
6214                rn.as_operand(),
6215                rm.as_operand(),
6216                condition.as_operand(),
6217            ],
6218        );
6219    }
6220}
6221
6222impl DcEmitter<Imm, Gp> for Assembler<'_> {
6223    fn dc(&mut self, dc_op: Imm, rt: Gp) {
6224        self.emit_n(InstId::Dc, &[dc_op.as_operand(), rt.as_operand()]);
6225    }
6226}
6227
6228impl DmbEmitter<Imm> for Assembler<'_> {
6229    fn dmb(&mut self, barrier_op: Imm) {
6230        self.emit_n(InstId::Dmb, &[barrier_op.as_operand()]);
6231    }
6232}
6233
6234impl DsbEmitter<Imm> for Assembler<'_> {
6235    fn dsb(&mut self, barrier_op: Imm) {
6236        self.emit_n(InstId::Dsb, &[barrier_op.as_operand()]);
6237    }
6238}
6239
6240impl DrpsEmitter for Assembler<'_> {
6241    fn drps(&mut self) {
6242        self.emit_n(InstId::Drps, &[]);
6243    }
6244}
6245
6246impl EonEmitter<Gp, Gp, Gp> for Assembler<'_> {
6247    fn eon(&mut self, rd: Gp, rn: Gp, rm: Gp) {
6248        self.emit_n(
6249            InstId::Eon,
6250            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
6251        );
6252    }
6253}
6254
6255impl Eon4Emitter<Gp, Gp, Gp, Imm> for Assembler<'_> {
6256    fn eon_4(&mut self, rd: Gp, rn: Gp, rm: Gp, shift: Imm) {
6257        self.emit_n(
6258            InstId::Eon,
6259            &[
6260                rd.as_operand(),
6261                rn.as_operand(),
6262                rm.as_operand(),
6263                shift.as_operand(),
6264            ],
6265        );
6266    }
6267}
6268
6269impl EorEmitter<Gp, Gp, Imm> for Assembler<'_> {
6270    fn eor(&mut self, rd: Gp, rn: Gp, rm_or_imm: Imm) {
6271        self.emit_n(
6272            InstId::Eor,
6273            &[rd.as_operand(), rn.as_operand(), rm_or_imm.as_operand()],
6274        );
6275    }
6276}
6277
6278impl EorEmitter<Gp, Gp, Gp> for Assembler<'_> {
6279    fn eor(&mut self, rd: Gp, rn: Gp, rm_or_imm: Gp) {
6280        self.emit_n(
6281            InstId::Eor,
6282            &[rd.as_operand(), rn.as_operand(), rm_or_imm.as_operand()],
6283        );
6284    }
6285}
6286
6287impl EorEmitter<Vec, Vec, Vec> for Assembler<'_> {
6288    fn eor(&mut self, rd: Vec, rn: Vec, rm_or_imm: Vec) {
6289        self.emit_n(
6290            InstId::Eor_v,
6291            &[rd.as_operand(), rn.as_operand(), rm_or_imm.as_operand()],
6292        );
6293    }
6294}
6295
6296impl Eor4Emitter<Gp, Gp, Gp, Imm> for Assembler<'_> {
6297    fn eor_4(&mut self, rd: Gp, rn: Gp, rm: Gp, shift: Imm) {
6298        self.emit_n(
6299            InstId::Eor,
6300            &[
6301                rd.as_operand(),
6302                rn.as_operand(),
6303                rm.as_operand(),
6304                shift.as_operand(),
6305            ],
6306        );
6307    }
6308}
6309
6310impl EretEmitter for Assembler<'_> {
6311    fn eret(&mut self) {
6312        self.emit_n(InstId::Eret, &[]);
6313    }
6314}
6315
6316impl EsbEmitter for Assembler<'_> {
6317    fn esb(&mut self) {
6318        self.emit_n(InstId::Esb, &[]);
6319    }
6320}
6321
6322impl ExtrEmitter<Gp, Gp, Gp, Imm> for Assembler<'_> {
6323    fn extr(&mut self, rd: Gp, rn: Gp, rm: Gp, imm: Imm) {
6324        self.emit_n(
6325            InstId::Extr,
6326            &[
6327                rd.as_operand(),
6328                rn.as_operand(),
6329                rm.as_operand(),
6330                imm.as_operand(),
6331            ],
6332        );
6333    }
6334}
6335
6336impl HltEmitter<Imm> for Assembler<'_> {
6337    fn hlt(&mut self, imm: Imm) {
6338        self.emit_n(InstId::Hlt, &[imm.as_operand()]);
6339    }
6340}
6341
6342impl HvcEmitter<Imm> for Assembler<'_> {
6343    fn hvc(&mut self, imm: Imm) {
6344        self.emit_n(InstId::Hvc, &[imm.as_operand()]);
6345    }
6346}
6347
6348impl IcEmitter<Imm, Gp> for Assembler<'_> {
6349    fn ic(&mut self, ic_op: Imm, rt: Gp) {
6350        self.emit_n(InstId::Ic, &[ic_op.as_operand(), rt.as_operand()]);
6351    }
6352}
6353
6354impl IsbEmitter<Imm> for Assembler<'_> {
6355    fn isb(&mut self, isb_op: Imm) {
6356        self.emit_n(InstId::Isb, &[isb_op.as_operand()]);
6357    }
6358}
6359
6360impl LslEmitter<Gp, Gp, Imm> for Assembler<'_> {
6361    fn lsl(&mut self, rd: Gp, rn: Gp, rm_or_shift: Imm) {
6362        self.emit_n(
6363            InstId::Lsl,
6364            &[rd.as_operand(), rn.as_operand(), rm_or_shift.as_operand()],
6365        );
6366    }
6367}
6368
6369impl LslEmitter<Gp, Gp, Gp> for Assembler<'_> {
6370    fn lsl(&mut self, rd: Gp, rn: Gp, rm_or_shift: Gp) {
6371        self.emit_n(
6372            InstId::Lsl,
6373            &[rd.as_operand(), rn.as_operand(), rm_or_shift.as_operand()],
6374        );
6375    }
6376}
6377
6378impl LslvEmitter<Gp, Gp, Gp> for Assembler<'_> {
6379    fn lslv(&mut self, rd: Gp, rn: Gp, rm: Gp) {
6380        self.emit_n(
6381            InstId::Lslv,
6382            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
6383        );
6384    }
6385}
6386
6387impl LsrEmitter<Gp, Gp, Imm> for Assembler<'_> {
6388    fn lsr(&mut self, rd: Gp, rn: Gp, rm_or_shift: Imm) {
6389        self.emit_n(
6390            InstId::Lsr,
6391            &[rd.as_operand(), rn.as_operand(), rm_or_shift.as_operand()],
6392        );
6393    }
6394}
6395
6396impl LsrEmitter<Gp, Gp, Gp> for Assembler<'_> {
6397    fn lsr(&mut self, rd: Gp, rn: Gp, rm_or_shift: Gp) {
6398        self.emit_n(
6399            InstId::Lsr,
6400            &[rd.as_operand(), rn.as_operand(), rm_or_shift.as_operand()],
6401        );
6402    }
6403}
6404
6405impl LsrvEmitter<Gp, Gp, Gp> for Assembler<'_> {
6406    fn lsrv(&mut self, rd: Gp, rn: Gp, rm: Gp) {
6407        self.emit_n(
6408            InstId::Lsrv,
6409            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
6410        );
6411    }
6412}
6413
6414impl MaddEmitter<Gp, Gp, Gp, Gp> for Assembler<'_> {
6415    fn madd(&mut self, rd: Gp, rn: Gp, rm: Gp, operand_4: Gp) {
6416        self.emit_n(
6417            InstId::Madd,
6418            &[
6419                rd.as_operand(),
6420                rn.as_operand(),
6421                rm.as_operand(),
6422                operand_4.as_operand(),
6423            ],
6424        );
6425    }
6426}
6427
6428impl MnegEmitter<Gp, Gp, Gp> for Assembler<'_> {
6429    fn mneg(&mut self, rd: Gp, rn: Gp, rm: Gp) {
6430        self.emit_n(
6431            InstId::Mneg,
6432            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
6433        );
6434    }
6435}
6436
6437impl MovEmitter<Gp, Gp> for Assembler<'_> {
6438    fn mov(&mut self, rd: Gp, rm_or_rn_or_imm_or_log_imm: Gp) {
6439        self.emit_n(
6440            InstId::Mov,
6441            &[rd.as_operand(), rm_or_rn_or_imm_or_log_imm.as_operand()],
6442        );
6443    }
6444}
6445
6446impl MovEmitter<Gp, Imm> for Assembler<'_> {
6447    fn mov(&mut self, rd: Gp, rm_or_rn_or_imm_or_log_imm: Imm) {
6448        self.emit_n(
6449            InstId::Mov,
6450            &[rd.as_operand(), rm_or_rn_or_imm_or_log_imm.as_operand()],
6451        );
6452    }
6453}
6454
6455impl MovEmitter<Vec, Vec> for Assembler<'_> {
6456    fn mov(&mut self, rd: Vec, rm_or_rn_or_imm_or_log_imm: Vec) {
6457        self.emit_n(
6458            InstId::Mov_v,
6459            &[rd.as_operand(), rm_or_rn_or_imm_or_log_imm.as_operand()],
6460        );
6461    }
6462}
6463
6464impl MovEmitter<Gp, Vec> for Assembler<'_> {
6465    fn mov(&mut self, rd: Gp, rm_or_rn_or_imm_or_log_imm: Vec) {
6466        self.emit_n(
6467            InstId::Mov_v,
6468            &[rd.as_operand(), rm_or_rn_or_imm_or_log_imm.as_operand()],
6469        );
6470    }
6471}
6472
6473impl MovEmitter<Vec, Gp> for Assembler<'_> {
6474    fn mov(&mut self, rd: Vec, rm_or_rn_or_imm_or_log_imm: Gp) {
6475        self.emit_n(
6476            InstId::Mov_v,
6477            &[rd.as_operand(), rm_or_rn_or_imm_or_log_imm.as_operand()],
6478        );
6479    }
6480}
6481
6482impl MovkEmitter<Gp, Imm> for Assembler<'_> {
6483    fn movk(&mut self, rd: Gp, imm: Imm) {
6484        self.emit_n(InstId::Movk, &[rd.as_operand(), imm.as_operand()]);
6485    }
6486}
6487
6488impl Movk3Emitter<Gp, Imm, Imm> for Assembler<'_> {
6489    fn movk_3(&mut self, rd: Gp, imm: Imm, shift: Imm) {
6490        self.emit_n(
6491            InstId::Movk,
6492            &[rd.as_operand(), imm.as_operand(), shift.as_operand()],
6493        );
6494    }
6495}
6496
6497impl MovnEmitter<Gp, Imm> for Assembler<'_> {
6498    fn movn(&mut self, rd: Gp, imm: Imm) {
6499        self.emit_n(InstId::Movn, &[rd.as_operand(), imm.as_operand()]);
6500    }
6501}
6502
6503impl Movn3Emitter<Gp, Imm, Imm> for Assembler<'_> {
6504    fn movn_3(&mut self, rd: Gp, imm: Imm, shift: Imm) {
6505        self.emit_n(
6506            InstId::Movn,
6507            &[rd.as_operand(), imm.as_operand(), shift.as_operand()],
6508        );
6509    }
6510}
6511
6512impl MovzEmitter<Gp, Imm> for Assembler<'_> {
6513    fn movz(&mut self, rd: Gp, imm: Imm) {
6514        self.emit_n(InstId::Movz, &[rd.as_operand(), imm.as_operand()]);
6515    }
6516}
6517
6518impl Movz3Emitter<Gp, Imm, Imm> for Assembler<'_> {
6519    fn movz_3(&mut self, rd: Gp, imm: Imm, shift: Imm) {
6520        self.emit_n(
6521            InstId::Movz,
6522            &[rd.as_operand(), imm.as_operand(), shift.as_operand()],
6523        );
6524    }
6525}
6526
6527impl MrsEmitter<Gp, Imm> for Assembler<'_> {
6528    fn mrs(&mut self, rd: Gp, sysreg: Imm) {
6529        self.emit_n(InstId::Mrs, &[rd.as_operand(), sysreg.as_operand()]);
6530    }
6531}
6532
6533impl MsrEmitter<Imm, Gp> for Assembler<'_> {
6534    fn msr(&mut self, sysreg_or_pstatefield: Imm, rs_or_imm: Gp) {
6535        self.emit_n(
6536            InstId::Msr,
6537            &[sysreg_or_pstatefield.as_operand(), rs_or_imm.as_operand()],
6538        );
6539    }
6540}
6541
6542impl MsrEmitter<Imm, Imm> for Assembler<'_> {
6543    fn msr(&mut self, sysreg_or_pstatefield: Imm, rs_or_imm: Imm) {
6544        self.emit_n(
6545            InstId::Msr,
6546            &[sysreg_or_pstatefield.as_operand(), rs_or_imm.as_operand()],
6547        );
6548    }
6549}
6550
6551impl MsubEmitter<Gp, Gp, Gp, Gp> for Assembler<'_> {
6552    fn msub(&mut self, rd: Gp, rn: Gp, rm: Gp, operand_4: Gp) {
6553        self.emit_n(
6554            InstId::Msub,
6555            &[
6556                rd.as_operand(),
6557                rn.as_operand(),
6558                rm.as_operand(),
6559                operand_4.as_operand(),
6560            ],
6561        );
6562    }
6563}
6564
6565impl MulEmitter<Gp, Gp, Gp> for Assembler<'_> {
6566    fn mul(&mut self, rd: Gp, rn: Gp, rm: Gp) {
6567        self.emit_n(
6568            InstId::Mul,
6569            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
6570        );
6571    }
6572}
6573
6574impl MulEmitter<Vec, Vec, Vec> for Assembler<'_> {
6575    fn mul(&mut self, rd: Vec, rn: Vec, rm: Vec) {
6576        self.emit_n(
6577            InstId::Mul_v,
6578            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
6579        );
6580    }
6581}
6582
6583impl MvnEmitter<Gp, Gp> for Assembler<'_> {
6584    fn mvn(&mut self, rd: Gp, rn: Gp) {
6585        self.emit_n(InstId::Mvn, &[rd.as_operand(), rn.as_operand()]);
6586    }
6587}
6588
6589impl MvnEmitter<Vec, Vec> for Assembler<'_> {
6590    fn mvn(&mut self, rd: Vec, rn: Vec) {
6591        self.emit_n(InstId::Mvn_v, &[rd.as_operand(), rn.as_operand()]);
6592    }
6593}
6594
6595impl Mvn3Emitter<Gp, Gp, Imm> for Assembler<'_> {
6596    fn mvn_3(&mut self, rd: Gp, rn: Gp, shift: Imm) {
6597        self.emit_n(
6598            InstId::Mvn,
6599            &[rd.as_operand(), rn.as_operand(), shift.as_operand()],
6600        );
6601    }
6602}
6603
6604impl Mvn_Emitter<Gp, Gp> for Assembler<'_> {
6605    fn mvn_(&mut self, rd: Gp, rn: Gp) {
6606        self.emit_n(InstId::Mvn, &[rd.as_operand(), rn.as_operand()]);
6607    }
6608}
6609
6610impl Mvn_Emitter<Vec, Vec> for Assembler<'_> {
6611    fn mvn_(&mut self, rd: Vec, rn: Vec) {
6612        self.emit_n(InstId::Mvn_v, &[rd.as_operand(), rn.as_operand()]);
6613    }
6614}
6615
6616impl Mvn_3Emitter<Gp, Gp, Imm> for Assembler<'_> {
6617    fn mvn__3(&mut self, rd: Gp, rn: Gp, shift: Imm) {
6618        self.emit_n(
6619            InstId::Mvn,
6620            &[rd.as_operand(), rn.as_operand(), shift.as_operand()],
6621        );
6622    }
6623}
6624
6625impl NegEmitter<Gp, Gp> for Assembler<'_> {
6626    fn neg(&mut self, rd: Gp, rm_or_rn: Gp) {
6627        self.emit_n(InstId::Neg, &[rd.as_operand(), rm_or_rn.as_operand()]);
6628    }
6629}
6630
6631impl NegEmitter<Vec, Vec> for Assembler<'_> {
6632    fn neg(&mut self, rd: Vec, rm_or_rn: Vec) {
6633        self.emit_n(InstId::Neg_v, &[rd.as_operand(), rm_or_rn.as_operand()]);
6634    }
6635}
6636
6637impl Neg3Emitter<Gp, Gp, Imm> for Assembler<'_> {
6638    fn neg_3(&mut self, rd: Gp, rm: Gp, shift: Imm) {
6639        self.emit_n(
6640            InstId::Neg,
6641            &[rd.as_operand(), rm.as_operand(), shift.as_operand()],
6642        );
6643    }
6644}
6645
6646impl NegsEmitter<Gp, Gp> for Assembler<'_> {
6647    fn negs(&mut self, rd: Gp, rm: Gp) {
6648        self.emit_n(InstId::Negs, &[rd.as_operand(), rm.as_operand()]);
6649    }
6650}
6651
6652impl Negs3Emitter<Gp, Gp, Imm> for Assembler<'_> {
6653    fn negs_3(&mut self, rd: Gp, rm: Gp, shift: Imm) {
6654        self.emit_n(
6655            InstId::Negs,
6656            &[rd.as_operand(), rm.as_operand(), shift.as_operand()],
6657        );
6658    }
6659}
6660
6661impl NgcEmitter<Gp, Gp> for Assembler<'_> {
6662    fn ngc(&mut self, rd: Gp, rm: Gp) {
6663        self.emit_n(InstId::Ngc, &[rd.as_operand(), rm.as_operand()]);
6664    }
6665}
6666
6667impl NgcsEmitter<Gp, Gp> for Assembler<'_> {
6668    fn ngcs(&mut self, rd: Gp, rm: Gp) {
6669        self.emit_n(InstId::Ngcs, &[rd.as_operand(), rm.as_operand()]);
6670    }
6671}
6672
6673impl OrnEmitter<Gp, Gp, Gp> for Assembler<'_> {
6674    fn orn(&mut self, rd: Gp, rn: Gp, rm: Gp) {
6675        self.emit_n(
6676            InstId::Orn,
6677            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
6678        );
6679    }
6680}
6681
6682impl OrnEmitter<Vec, Vec, Vec> for Assembler<'_> {
6683    fn orn(&mut self, rd: Vec, rn: Vec, rm: Vec) {
6684        self.emit_n(
6685            InstId::Orn_v,
6686            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
6687        );
6688    }
6689}
6690
6691impl Orn4Emitter<Gp, Gp, Gp, Imm> for Assembler<'_> {
6692    fn orn_4(&mut self, rd: Gp, rn: Gp, rm: Gp, shift: Imm) {
6693        self.emit_n(
6694            InstId::Orn,
6695            &[
6696                rd.as_operand(),
6697                rn.as_operand(),
6698                rm.as_operand(),
6699                shift.as_operand(),
6700            ],
6701        );
6702    }
6703}
6704
6705impl OrrEmitter<Gp, Gp, Imm> for Assembler<'_> {
6706    fn orr(&mut self, rd: Gp, rn_or_imm: Gp, rm_or_log_imm_or_shift: Imm) {
6707        self.emit_n(
6708            InstId::Orr,
6709            &[
6710                rd.as_operand(),
6711                rn_or_imm.as_operand(),
6712                rm_or_log_imm_or_shift.as_operand(),
6713            ],
6714        );
6715    }
6716}
6717
6718impl OrrEmitter<Gp, Gp, Gp> for Assembler<'_> {
6719    fn orr(&mut self, rd: Gp, rn_or_imm: Gp, rm_or_log_imm_or_shift: Gp) {
6720        self.emit_n(
6721            InstId::Orr,
6722            &[
6723                rd.as_operand(),
6724                rn_or_imm.as_operand(),
6725                rm_or_log_imm_or_shift.as_operand(),
6726            ],
6727        );
6728    }
6729}
6730
6731impl OrrEmitter<Vec, Vec, Vec> for Assembler<'_> {
6732    fn orr(&mut self, rd: Vec, rn_or_imm: Vec, rm_or_log_imm_or_shift: Vec) {
6733        self.emit_n(
6734            InstId::Orr_v,
6735            &[
6736                rd.as_operand(),
6737                rn_or_imm.as_operand(),
6738                rm_or_log_imm_or_shift.as_operand(),
6739            ],
6740        );
6741    }
6742}
6743
6744impl OrrEmitter<Vec, Imm, Imm> for Assembler<'_> {
6745    fn orr(&mut self, rd: Vec, rn_or_imm: Imm, rm_or_log_imm_or_shift: Imm) {
6746        self.emit_n(
6747            InstId::Orr_v,
6748            &[
6749                rd.as_operand(),
6750                rn_or_imm.as_operand(),
6751                rm_or_log_imm_or_shift.as_operand(),
6752            ],
6753        );
6754    }
6755}
6756
6757impl Orr4Emitter<Gp, Gp, Gp, Imm> for Assembler<'_> {
6758    fn orr_4(&mut self, rd: Gp, rn: Gp, rm: Gp, shift: Imm) {
6759        self.emit_n(
6760            InstId::Orr,
6761            &[
6762                rd.as_operand(),
6763                rn.as_operand(),
6764                rm.as_operand(),
6765                shift.as_operand(),
6766            ],
6767        );
6768    }
6769}
6770
6771impl RbitEmitter<Gp, Gp> for Assembler<'_> {
6772    fn rbit(&mut self, rd: Gp, rn: Gp) {
6773        self.emit_n(InstId::Rbit, &[rd.as_operand(), rn.as_operand()]);
6774    }
6775}
6776
6777impl RbitEmitter<Vec, Vec> for Assembler<'_> {
6778    fn rbit(&mut self, rd: Vec, rn: Vec) {
6779        self.emit_n(InstId::Rbit_v, &[rd.as_operand(), rn.as_operand()]);
6780    }
6781}
6782
6783impl RetEmitter<Gp> for Assembler<'_> {
6784    fn ret(&mut self, rn: Gp) {
6785        self.emit_n(InstId::Ret, &[rn.as_operand()]);
6786    }
6787}
6788
6789impl RevEmitter<Gp, Gp> for Assembler<'_> {
6790    fn rev(&mut self, rd: Gp, rn: Gp) {
6791        self.emit_n(InstId::Rev, &[rd.as_operand(), rn.as_operand()]);
6792    }
6793}
6794
6795impl Rev16Emitter<Gp, Gp> for Assembler<'_> {
6796    fn rev16(&mut self, rd: Gp, rn: Gp) {
6797        self.emit_n(InstId::Rev16, &[rd.as_operand(), rn.as_operand()]);
6798    }
6799}
6800
6801impl Rev16Emitter<Vec, Vec> for Assembler<'_> {
6802    fn rev16(&mut self, rd: Vec, rn: Vec) {
6803        self.emit_n(InstId::Rev16_v, &[rd.as_operand(), rn.as_operand()]);
6804    }
6805}
6806
6807impl Rev32Emitter<Gp, Gp> for Assembler<'_> {
6808    fn rev32(&mut self, rd: Gp, rn: Gp) {
6809        self.emit_n(InstId::Rev32, &[rd.as_operand(), rn.as_operand()]);
6810    }
6811}
6812
6813impl Rev32Emitter<Vec, Vec> for Assembler<'_> {
6814    fn rev32(&mut self, rd: Vec, rn: Vec) {
6815        self.emit_n(InstId::Rev32_v, &[rd.as_operand(), rn.as_operand()]);
6816    }
6817}
6818
6819impl Rev64Emitter<Gp, Gp> for Assembler<'_> {
6820    fn rev64(&mut self, rd: Gp, rn: Gp) {
6821        self.emit_n(InstId::Rev64, &[rd.as_operand(), rn.as_operand()]);
6822    }
6823}
6824
6825impl Rev64Emitter<Vec, Vec> for Assembler<'_> {
6826    fn rev64(&mut self, rd: Vec, rn: Vec) {
6827        self.emit_n(InstId::Rev64_v, &[rd.as_operand(), rn.as_operand()]);
6828    }
6829}
6830
6831impl RorEmitter<Gp, Gp, Imm> for Assembler<'_> {
6832    fn ror(&mut self, rd: Gp, rn: Gp, rm_or_shift: Imm) {
6833        self.emit_n(
6834            InstId::Ror,
6835            &[rd.as_operand(), rn.as_operand(), rm_or_shift.as_operand()],
6836        );
6837    }
6838}
6839
6840impl RorEmitter<Gp, Gp, Gp> for Assembler<'_> {
6841    fn ror(&mut self, rd: Gp, rn: Gp, rm_or_shift: Gp) {
6842        self.emit_n(
6843            InstId::Ror,
6844            &[rd.as_operand(), rn.as_operand(), rm_or_shift.as_operand()],
6845        );
6846    }
6847}
6848
6849impl RorvEmitter<Gp, Gp, Gp> for Assembler<'_> {
6850    fn rorv(&mut self, rd: Gp, rn: Gp, rm: Gp) {
6851        self.emit_n(
6852            InstId::Rorv,
6853            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
6854        );
6855    }
6856}
6857
6858impl SbcEmitter<Gp, Gp, Gp> for Assembler<'_> {
6859    fn sbc(&mut self, rd: Gp, rn: Gp, rm: Gp) {
6860        self.emit_n(
6861            InstId::Sbc,
6862            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
6863        );
6864    }
6865}
6866
6867impl SbcsEmitter<Gp, Gp, Gp> for Assembler<'_> {
6868    fn sbcs(&mut self, rd: Gp, rn: Gp, rm: Gp) {
6869        self.emit_n(
6870            InstId::Sbcs,
6871            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
6872        );
6873    }
6874}
6875
6876impl SbfizEmitter<Gp, Gp, Imm, Imm> for Assembler<'_> {
6877    fn sbfiz(&mut self, rd: Gp, rn: Gp, lsb: Imm, width: Imm) {
6878        self.emit_n(
6879            InstId::Sbfiz,
6880            &[
6881                rd.as_operand(),
6882                rn.as_operand(),
6883                lsb.as_operand(),
6884                width.as_operand(),
6885            ],
6886        );
6887    }
6888}
6889
6890impl SbfmEmitter<Gp, Gp, Imm, Imm> for Assembler<'_> {
6891    fn sbfm(&mut self, rd: Gp, rn: Gp, imm: Imm, imm_2: Imm) {
6892        self.emit_n(
6893            InstId::Sbfm,
6894            &[
6895                rd.as_operand(),
6896                rn.as_operand(),
6897                imm.as_operand(),
6898                imm_2.as_operand(),
6899            ],
6900        );
6901    }
6902}
6903
6904impl SbfxEmitter<Gp, Gp, Imm, Imm> for Assembler<'_> {
6905    fn sbfx(&mut self, rd: Gp, rn: Gp, lsb: Imm, width: Imm) {
6906        self.emit_n(
6907            InstId::Sbfx,
6908            &[
6909                rd.as_operand(),
6910                rn.as_operand(),
6911                lsb.as_operand(),
6912                width.as_operand(),
6913            ],
6914        );
6915    }
6916}
6917
6918impl SdivEmitter<Gp, Gp, Gp> for Assembler<'_> {
6919    fn sdiv(&mut self, rd: Gp, rn: Gp, rm: Gp) {
6920        self.emit_n(
6921            InstId::Sdiv,
6922            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
6923        );
6924    }
6925}
6926
6927impl SmaddlEmitter<Gp, Gp, Gp, Gp> for Assembler<'_> {
6928    fn smaddl(&mut self, rd: Gp, rn: Gp, rm: Gp, operand_4: Gp) {
6929        self.emit_n(
6930            InstId::Smaddl,
6931            &[
6932                rd.as_operand(),
6933                rn.as_operand(),
6934                rm.as_operand(),
6935                operand_4.as_operand(),
6936            ],
6937        );
6938    }
6939}
6940
6941impl SmcEmitter<Imm> for Assembler<'_> {
6942    fn smc(&mut self, imm: Imm) {
6943        self.emit_n(InstId::Smc, &[imm.as_operand()]);
6944    }
6945}
6946
6947impl SmneglEmitter<Gp, Gp, Gp> for Assembler<'_> {
6948    fn smnegl(&mut self, rd: Gp, rn: Gp, rm: Gp) {
6949        self.emit_n(
6950            InstId::Smnegl,
6951            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
6952        );
6953    }
6954}
6955
6956impl SmsublEmitter<Gp, Gp, Gp, Gp> for Assembler<'_> {
6957    fn smsubl(&mut self, rd: Gp, rn: Gp, rm: Gp, operand_4: Gp) {
6958        self.emit_n(
6959            InstId::Smsubl,
6960            &[
6961                rd.as_operand(),
6962                rn.as_operand(),
6963                rm.as_operand(),
6964                operand_4.as_operand(),
6965            ],
6966        );
6967    }
6968}
6969
6970impl SmulhEmitter<Gp, Gp, Gp> for Assembler<'_> {
6971    fn smulh(&mut self, rd: Gp, rn: Gp, rm: Gp) {
6972        self.emit_n(
6973            InstId::Smulh,
6974            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
6975        );
6976    }
6977}
6978
6979impl SmullEmitter<Gp, Gp, Gp> for Assembler<'_> {
6980    fn smull(&mut self, rd: Gp, rn: Gp, rm: Gp) {
6981        self.emit_n(
6982            InstId::Smull,
6983            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
6984        );
6985    }
6986}
6987
6988impl SmullEmitter<Vec, Vec, Vec> for Assembler<'_> {
6989    fn smull(&mut self, rd: Vec, rn: Vec, rm: Vec) {
6990        self.emit_n(
6991            InstId::Smull_v,
6992            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
6993        );
6994    }
6995}
6996
6997impl SubEmitter<Gp, Gp, Gp> for Assembler<'_> {
6998    fn sub(&mut self, rd: Gp, rn: Gp, rm_or_imm: Gp) {
6999        self.emit_n(
7000            InstId::Sub,
7001            &[rd.as_operand(), rn.as_operand(), rm_or_imm.as_operand()],
7002        );
7003    }
7004}
7005
7006impl SubEmitter<Gp, Gp, Imm> for Assembler<'_> {
7007    fn sub(&mut self, rd: Gp, rn: Gp, rm_or_imm: Imm) {
7008        self.emit_n(
7009            InstId::Sub,
7010            &[rd.as_operand(), rn.as_operand(), rm_or_imm.as_operand()],
7011        );
7012    }
7013}
7014
7015impl SubEmitter<Vec, Vec, Vec> for Assembler<'_> {
7016    fn sub(&mut self, rd: Vec, rn: Vec, rm_or_imm: Vec) {
7017        self.emit_n(
7018            InstId::Sub_v,
7019            &[rd.as_operand(), rn.as_operand(), rm_or_imm.as_operand()],
7020        );
7021    }
7022}
7023
7024impl Sub4Emitter<Gp, Gp, Gp, Imm> for Assembler<'_> {
7025    fn sub_4(&mut self, rd: Gp, rn: Gp, rm_or_imm: Gp, shift: Imm) {
7026        self.emit_n(
7027            InstId::Sub,
7028            &[
7029                rd.as_operand(),
7030                rn.as_operand(),
7031                rm_or_imm.as_operand(),
7032                shift.as_operand(),
7033            ],
7034        );
7035    }
7036}
7037
7038impl Sub4Emitter<Gp, Gp, Imm, Imm> for Assembler<'_> {
7039    fn sub_4(&mut self, rd: Gp, rn: Gp, rm_or_imm: Imm, shift: Imm) {
7040        self.emit_n(
7041            InstId::Sub,
7042            &[
7043                rd.as_operand(),
7044                rn.as_operand(),
7045                rm_or_imm.as_operand(),
7046                shift.as_operand(),
7047            ],
7048        );
7049    }
7050}
7051
7052impl SubsEmitter<Gp, Gp, Gp> for Assembler<'_> {
7053    fn subs(&mut self, rd: Gp, rn: Gp, rm_or_imm: Gp) {
7054        self.emit_n(
7055            InstId::Subs,
7056            &[rd.as_operand(), rn.as_operand(), rm_or_imm.as_operand()],
7057        );
7058    }
7059}
7060
7061impl SubsEmitter<Gp, Gp, Imm> for Assembler<'_> {
7062    fn subs(&mut self, rd: Gp, rn: Gp, rm_or_imm: Imm) {
7063        self.emit_n(
7064            InstId::Subs,
7065            &[rd.as_operand(), rn.as_operand(), rm_or_imm.as_operand()],
7066        );
7067    }
7068}
7069
7070impl Subs4Emitter<Gp, Gp, Gp, Imm> for Assembler<'_> {
7071    fn subs_4(&mut self, rd: Gp, rn: Gp, rm_or_imm: Gp, shift: Imm) {
7072        self.emit_n(
7073            InstId::Subs,
7074            &[
7075                rd.as_operand(),
7076                rn.as_operand(),
7077                rm_or_imm.as_operand(),
7078                shift.as_operand(),
7079            ],
7080        );
7081    }
7082}
7083
7084impl Subs4Emitter<Gp, Gp, Imm, Imm> for Assembler<'_> {
7085    fn subs_4(&mut self, rd: Gp, rn: Gp, rm_or_imm: Imm, shift: Imm) {
7086        self.emit_n(
7087            InstId::Subs,
7088            &[
7089                rd.as_operand(),
7090                rn.as_operand(),
7091                rm_or_imm.as_operand(),
7092                shift.as_operand(),
7093            ],
7094        );
7095    }
7096}
7097
7098impl SvcEmitter<Imm> for Assembler<'_> {
7099    fn svc(&mut self, imm: Imm) {
7100        self.emit_n(InstId::Svc, &[imm.as_operand()]);
7101    }
7102}
7103
7104impl SxtbEmitter<Gp, Gp> for Assembler<'_> {
7105    fn sxtb(&mut self, rd: Gp, rn: Gp) {
7106        self.emit_n(InstId::Sxtb, &[rd.as_operand(), rn.as_operand()]);
7107    }
7108}
7109
7110impl SxthEmitter<Gp, Gp> for Assembler<'_> {
7111    fn sxth(&mut self, rd: Gp, rn: Gp) {
7112        self.emit_n(InstId::Sxth, &[rd.as_operand(), rn.as_operand()]);
7113    }
7114}
7115
7116impl SxtwEmitter<Gp, Gp> for Assembler<'_> {
7117    fn sxtw(&mut self, rd: Gp, rn: Gp) {
7118        self.emit_n(InstId::Sxtw, &[rd.as_operand(), rn.as_operand()]);
7119    }
7120}
7121
7122impl SysEmitter<Imm, Imm, Imm, Imm> for Assembler<'_> {
7123    fn sys(&mut self, system_op1: Imm, cn: Imm, cm: Imm, system_op2: Imm) {
7124        self.emit_n(
7125            InstId::Sys,
7126            &[
7127                system_op1.as_operand(),
7128                cn.as_operand(),
7129                cm.as_operand(),
7130                system_op2.as_operand(),
7131            ],
7132        );
7133    }
7134}
7135
7136impl Sys5Emitter<Imm, Imm, Imm, Imm, Gp> for Assembler<'_> {
7137    fn sys_5(&mut self, system_op1: Imm, cn: Imm, cm: Imm, system_op2: Imm, rt: Gp) {
7138        self.emit_n(
7139            InstId::Sys,
7140            &[
7141                system_op1.as_operand(),
7142                cn.as_operand(),
7143                cm.as_operand(),
7144                system_op2.as_operand(),
7145                rt.as_operand(),
7146            ],
7147        );
7148    }
7149}
7150
7151impl TlbiEmitter<Imm, Gp> for Assembler<'_> {
7152    fn tlbi(&mut self, tlbi_op: Imm, rt: Gp) {
7153        self.emit_n(InstId::Tlbi, &[tlbi_op.as_operand(), rt.as_operand()]);
7154    }
7155}
7156
7157impl TstEmitter<Gp, Imm> for Assembler<'_> {
7158    fn tst(&mut self, rn: Gp, rm_or_imm: Imm) {
7159        self.emit_n(InstId::Tst, &[rn.as_operand(), rm_or_imm.as_operand()]);
7160    }
7161}
7162
7163impl TstEmitter<Gp, Gp> for Assembler<'_> {
7164    fn tst(&mut self, rn: Gp, rm_or_imm: Gp) {
7165        self.emit_n(InstId::Tst, &[rn.as_operand(), rm_or_imm.as_operand()]);
7166    }
7167}
7168
7169impl Tst3Emitter<Gp, Gp, Imm> for Assembler<'_> {
7170    fn tst_3(&mut self, rn: Gp, rm: Gp, shift: Imm) {
7171        self.emit_n(
7172            InstId::Tst,
7173            &[rn.as_operand(), rm.as_operand(), shift.as_operand()],
7174        );
7175    }
7176}
7177
7178impl UdivEmitter<Gp, Gp, Gp> for Assembler<'_> {
7179    fn udiv(&mut self, rd: Gp, rn: Gp, rm: Gp) {
7180        self.emit_n(
7181            InstId::Udiv,
7182            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
7183        );
7184    }
7185}
7186
7187impl UbfizEmitter<Gp, Gp, Imm, Imm> for Assembler<'_> {
7188    fn ubfiz(&mut self, rd: Gp, rn: Gp, lsb: Imm, width: Imm) {
7189        self.emit_n(
7190            InstId::Ubfiz,
7191            &[
7192                rd.as_operand(),
7193                rn.as_operand(),
7194                lsb.as_operand(),
7195                width.as_operand(),
7196            ],
7197        );
7198    }
7199}
7200
7201impl UbfmEmitter<Gp, Gp, Imm, Imm> for Assembler<'_> {
7202    fn ubfm(&mut self, rd: Gp, rn: Gp, imm: Imm, imm_2: Imm) {
7203        self.emit_n(
7204            InstId::Ubfm,
7205            &[
7206                rd.as_operand(),
7207                rn.as_operand(),
7208                imm.as_operand(),
7209                imm_2.as_operand(),
7210            ],
7211        );
7212    }
7213}
7214
7215impl UbfxEmitter<Gp, Gp, Imm, Imm> for Assembler<'_> {
7216    fn ubfx(&mut self, rd: Gp, rn: Gp, lsb: Imm, width: Imm) {
7217        self.emit_n(
7218            InstId::Ubfx,
7219            &[
7220                rd.as_operand(),
7221                rn.as_operand(),
7222                lsb.as_operand(),
7223                width.as_operand(),
7224            ],
7225        );
7226    }
7227}
7228
7229impl UmaddlEmitter<Gp, Gp, Gp, Gp> for Assembler<'_> {
7230    fn umaddl(&mut self, rd: Gp, rn: Gp, rm: Gp, operand_4: Gp) {
7231        self.emit_n(
7232            InstId::Umaddl,
7233            &[
7234                rd.as_operand(),
7235                rn.as_operand(),
7236                rm.as_operand(),
7237                operand_4.as_operand(),
7238            ],
7239        );
7240    }
7241}
7242
7243impl UmneglEmitter<Gp, Gp, Gp> for Assembler<'_> {
7244    fn umnegl(&mut self, rd: Gp, rn: Gp, rm: Gp) {
7245        self.emit_n(
7246            InstId::Umnegl,
7247            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
7248        );
7249    }
7250}
7251
7252impl UmsublEmitter<Gp, Gp, Gp, Gp> for Assembler<'_> {
7253    fn umsubl(&mut self, rd: Gp, rn: Gp, rm: Gp, operand_4: Gp) {
7254        self.emit_n(
7255            InstId::Umsubl,
7256            &[
7257                rd.as_operand(),
7258                rn.as_operand(),
7259                rm.as_operand(),
7260                operand_4.as_operand(),
7261            ],
7262        );
7263    }
7264}
7265
7266impl UmullEmitter<Gp, Gp, Gp> for Assembler<'_> {
7267    fn umull(&mut self, rd: Gp, rn: Gp, rm: Gp) {
7268        self.emit_n(
7269            InstId::Umull,
7270            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
7271        );
7272    }
7273}
7274
7275impl UmullEmitter<Vec, Vec, Vec> for Assembler<'_> {
7276    fn umull(&mut self, rd: Vec, rn: Vec, rm: Vec) {
7277        self.emit_n(
7278            InstId::Umull_v,
7279            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
7280        );
7281    }
7282}
7283
7284impl UmulhEmitter<Gp, Gp, Gp> for Assembler<'_> {
7285    fn umulh(&mut self, rd: Gp, rn: Gp, rm: Gp) {
7286        self.emit_n(
7287            InstId::Umulh,
7288            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
7289        );
7290    }
7291}
7292
7293impl UxtbEmitter<Gp, Gp> for Assembler<'_> {
7294    fn uxtb(&mut self, rd: Gp, rn: Gp) {
7295        self.emit_n(InstId::Uxtb, &[rd.as_operand(), rn.as_operand()]);
7296    }
7297}
7298
7299impl UxthEmitter<Gp, Gp> for Assembler<'_> {
7300    fn uxth(&mut self, rd: Gp, rn: Gp) {
7301        self.emit_n(InstId::Uxth, &[rd.as_operand(), rn.as_operand()]);
7302    }
7303}
7304
7305impl CsdbEmitter for Assembler<'_> {
7306    fn csdb(&mut self) {
7307        self.emit_n(InstId::Csdb, &[]);
7308    }
7309}
7310
7311impl Dcps1Emitter<Imm> for Assembler<'_> {
7312    fn dcps1(&mut self, imm: Imm) {
7313        self.emit_n(InstId::Dcps1, &[imm.as_operand()]);
7314    }
7315}
7316
7317impl Dcps2Emitter<Imm> for Assembler<'_> {
7318    fn dcps2(&mut self, imm: Imm) {
7319        self.emit_n(InstId::Dcps2, &[imm.as_operand()]);
7320    }
7321}
7322
7323impl Dcps3Emitter<Imm> for Assembler<'_> {
7324    fn dcps3(&mut self, imm: Imm) {
7325        self.emit_n(InstId::Dcps3, &[imm.as_operand()]);
7326    }
7327}
7328
7329impl PssbbEmitter for Assembler<'_> {
7330    fn pssbb(&mut self) {
7331        self.emit_n(InstId::Pssbb, &[]);
7332    }
7333}
7334
7335impl SsbbEmitter for Assembler<'_> {
7336    fn ssbb(&mut self) {
7337        self.emit_n(InstId::Ssbb, &[]);
7338    }
7339}
7340
7341impl UdfEmitter<Imm> for Assembler<'_> {
7342    fn udf(&mut self, imm: Imm) {
7343        self.emit_n(InstId::Udf, &[imm.as_operand()]);
7344    }
7345}
7346
7347impl BEmitter<Imm> for Assembler<'_> {
7348    fn b(&mut self, target: Imm) {
7349        self.emit_n(InstId::B, &[target.as_operand()]);
7350    }
7351    fn b_eq(&mut self, target: Imm) {
7352        self.emit_n(InstId::B.with_cc(CondCode::EQ), &[target.as_operand()]);
7353    }
7354    fn b_ne(&mut self, target: Imm) {
7355        self.emit_n(InstId::B.with_cc(CondCode::NE), &[target.as_operand()]);
7356    }
7357    fn b_cs(&mut self, target: Imm) {
7358        self.emit_n(InstId::B.with_cc(CondCode::CS), &[target.as_operand()]);
7359    }
7360    fn b_hs(&mut self, target: Imm) {
7361        self.emit_n(InstId::B.with_cc(CondCode::HS), &[target.as_operand()]);
7362    }
7363    fn b_cc(&mut self, target: Imm) {
7364        self.emit_n(InstId::B.with_cc(CondCode::CC), &[target.as_operand()]);
7365    }
7366    fn b_lo(&mut self, target: Imm) {
7367        self.emit_n(InstId::B.with_cc(CondCode::LO), &[target.as_operand()]);
7368    }
7369    fn b_mi(&mut self, target: Imm) {
7370        self.emit_n(InstId::B.with_cc(CondCode::MI), &[target.as_operand()]);
7371    }
7372    fn b_pl(&mut self, target: Imm) {
7373        self.emit_n(InstId::B.with_cc(CondCode::PL), &[target.as_operand()]);
7374    }
7375    fn b_vs(&mut self, target: Imm) {
7376        self.emit_n(InstId::B.with_cc(CondCode::VS), &[target.as_operand()]);
7377    }
7378    fn b_vc(&mut self, target: Imm) {
7379        self.emit_n(InstId::B.with_cc(CondCode::VC), &[target.as_operand()]);
7380    }
7381    fn b_hi(&mut self, target: Imm) {
7382        self.emit_n(InstId::B.with_cc(CondCode::HI), &[target.as_operand()]);
7383    }
7384    fn b_ls(&mut self, target: Imm) {
7385        self.emit_n(InstId::B.with_cc(CondCode::LS), &[target.as_operand()]);
7386    }
7387    fn b_ge(&mut self, target: Imm) {
7388        self.emit_n(InstId::B.with_cc(CondCode::GE), &[target.as_operand()]);
7389    }
7390    fn b_lt(&mut self, target: Imm) {
7391        self.emit_n(InstId::B.with_cc(CondCode::LT), &[target.as_operand()]);
7392    }
7393    fn b_gt(&mut self, target: Imm) {
7394        self.emit_n(InstId::B.with_cc(CondCode::GT), &[target.as_operand()]);
7395    }
7396    fn b_le(&mut self, target: Imm) {
7397        self.emit_n(InstId::B.with_cc(CondCode::LE), &[target.as_operand()]);
7398    }
7399    fn b_al(&mut self, target: Imm) {
7400        self.emit_n(InstId::B.with_cc(CondCode::AL), &[target.as_operand()]);
7401    }
7402}
7403
7404impl BEmitter<Label> for Assembler<'_> {
7405    fn b(&mut self, target: Label) {
7406        self.emit_n(InstId::B, &[target.as_operand()]);
7407    }
7408    fn b_eq(&mut self, target: Label) {
7409        self.emit_n(InstId::B.with_cc(CondCode::EQ), &[target.as_operand()]);
7410    }
7411    fn b_ne(&mut self, target: Label) {
7412        self.emit_n(InstId::B.with_cc(CondCode::NE), &[target.as_operand()]);
7413    }
7414    fn b_cs(&mut self, target: Label) {
7415        self.emit_n(InstId::B.with_cc(CondCode::CS), &[target.as_operand()]);
7416    }
7417    fn b_hs(&mut self, target: Label) {
7418        self.emit_n(InstId::B.with_cc(CondCode::HS), &[target.as_operand()]);
7419    }
7420    fn b_cc(&mut self, target: Label) {
7421        self.emit_n(InstId::B.with_cc(CondCode::CC), &[target.as_operand()]);
7422    }
7423    fn b_lo(&mut self, target: Label) {
7424        self.emit_n(InstId::B.with_cc(CondCode::LO), &[target.as_operand()]);
7425    }
7426    fn b_mi(&mut self, target: Label) {
7427        self.emit_n(InstId::B.with_cc(CondCode::MI), &[target.as_operand()]);
7428    }
7429    fn b_pl(&mut self, target: Label) {
7430        self.emit_n(InstId::B.with_cc(CondCode::PL), &[target.as_operand()]);
7431    }
7432    fn b_vs(&mut self, target: Label) {
7433        self.emit_n(InstId::B.with_cc(CondCode::VS), &[target.as_operand()]);
7434    }
7435    fn b_vc(&mut self, target: Label) {
7436        self.emit_n(InstId::B.with_cc(CondCode::VC), &[target.as_operand()]);
7437    }
7438    fn b_hi(&mut self, target: Label) {
7439        self.emit_n(InstId::B.with_cc(CondCode::HI), &[target.as_operand()]);
7440    }
7441    fn b_ls(&mut self, target: Label) {
7442        self.emit_n(InstId::B.with_cc(CondCode::LS), &[target.as_operand()]);
7443    }
7444    fn b_ge(&mut self, target: Label) {
7445        self.emit_n(InstId::B.with_cc(CondCode::GE), &[target.as_operand()]);
7446    }
7447    fn b_lt(&mut self, target: Label) {
7448        self.emit_n(InstId::B.with_cc(CondCode::LT), &[target.as_operand()]);
7449    }
7450    fn b_gt(&mut self, target: Label) {
7451        self.emit_n(InstId::B.with_cc(CondCode::GT), &[target.as_operand()]);
7452    }
7453    fn b_le(&mut self, target: Label) {
7454        self.emit_n(InstId::B.with_cc(CondCode::LE), &[target.as_operand()]);
7455    }
7456    fn b_al(&mut self, target: Label) {
7457        self.emit_n(InstId::B.with_cc(CondCode::AL), &[target.as_operand()]);
7458    }
7459}
7460
7461impl BlEmitter<Imm> for Assembler<'_> {
7462    fn bl(&mut self, target: Imm) {
7463        self.emit_n(InstId::Bl, &[target.as_operand()]);
7464    }
7465}
7466
7467impl BlEmitter<Label> for Assembler<'_> {
7468    fn bl(&mut self, target: Label) {
7469        self.emit_n(InstId::Bl, &[target.as_operand()]);
7470    }
7471}
7472
7473impl BlEmitter<Sym> for Assembler<'_> {
7474    fn bl(&mut self, target: Sym) {
7475        self.emit_n(InstId::Bl, &[target.as_operand()]);
7476    }
7477}
7478
7479impl BlrEmitter<Gp> for Assembler<'_> {
7480    fn blr(&mut self, rn: Gp) {
7481        self.emit_n(InstId::Blr, &[rn.as_operand()]);
7482    }
7483}
7484
7485impl BrEmitter<Gp> for Assembler<'_> {
7486    fn br(&mut self, rn: Gp) {
7487        self.emit_n(InstId::Br, &[rn.as_operand()]);
7488    }
7489}
7490
7491impl CbzEmitter<Gp, Imm> for Assembler<'_> {
7492    fn cbz(&mut self, rn: Gp, target: Imm) {
7493        self.emit_n(InstId::Cbz, &[rn.as_operand(), target.as_operand()]);
7494    }
7495}
7496
7497impl CbzEmitter<Gp, Label> for Assembler<'_> {
7498    fn cbz(&mut self, rn: Gp, target: Label) {
7499        self.emit_n(InstId::Cbz, &[rn.as_operand(), target.as_operand()]);
7500    }
7501}
7502
7503impl CbzEmitter<Gp, Sym> for Assembler<'_> {
7504    fn cbz(&mut self, rn: Gp, target: Sym) {
7505        self.emit_n(InstId::Cbz, &[rn.as_operand(), target.as_operand()]);
7506    }
7507}
7508
7509impl CbnzEmitter<Gp, Imm> for Assembler<'_> {
7510    fn cbnz(&mut self, rn: Gp, target: Imm) {
7511        self.emit_n(InstId::Cbnz, &[rn.as_operand(), target.as_operand()]);
7512    }
7513}
7514
7515impl CbnzEmitter<Gp, Label> for Assembler<'_> {
7516    fn cbnz(&mut self, rn: Gp, target: Label) {
7517        self.emit_n(InstId::Cbnz, &[rn.as_operand(), target.as_operand()]);
7518    }
7519}
7520
7521impl CbnzEmitter<Gp, Sym> for Assembler<'_> {
7522    fn cbnz(&mut self, rn: Gp, target: Sym) {
7523        self.emit_n(InstId::Cbnz, &[rn.as_operand(), target.as_operand()]);
7524    }
7525}
7526
7527impl TbnzEmitter<Gp, Imm, Imm> for Assembler<'_> {
7528    fn tbnz(&mut self, rt: Gp, imm: Imm, target: Imm) {
7529        self.emit_n(
7530            InstId::Tbnz,
7531            &[rt.as_operand(), imm.as_operand(), target.as_operand()],
7532        );
7533    }
7534}
7535
7536impl TbnzEmitter<Gp, Imm, Label> for Assembler<'_> {
7537    fn tbnz(&mut self, rt: Gp, imm: Imm, target: Label) {
7538        self.emit_n(
7539            InstId::Tbnz,
7540            &[rt.as_operand(), imm.as_operand(), target.as_operand()],
7541        );
7542    }
7543}
7544
7545impl TbnzEmitter<Gp, Imm, Sym> for Assembler<'_> {
7546    fn tbnz(&mut self, rt: Gp, imm: Imm, target: Sym) {
7547        self.emit_n(
7548            InstId::Tbnz,
7549            &[rt.as_operand(), imm.as_operand(), target.as_operand()],
7550        );
7551    }
7552}
7553
7554impl TbzEmitter<Gp, Imm, Imm> for Assembler<'_> {
7555    fn tbz(&mut self, rt: Gp, imm: Imm, target: Imm) {
7556        self.emit_n(
7557            InstId::Tbz,
7558            &[rt.as_operand(), imm.as_operand(), target.as_operand()],
7559        );
7560    }
7561}
7562
7563impl TbzEmitter<Gp, Imm, Label> for Assembler<'_> {
7564    fn tbz(&mut self, rt: Gp, imm: Imm, target: Label) {
7565        self.emit_n(
7566            InstId::Tbz,
7567            &[rt.as_operand(), imm.as_operand(), target.as_operand()],
7568        );
7569    }
7570}
7571
7572impl TbzEmitter<Gp, Imm, Sym> for Assembler<'_> {
7573    fn tbz(&mut self, rt: Gp, imm: Imm, target: Sym) {
7574        self.emit_n(
7575            InstId::Tbz,
7576            &[rt.as_operand(), imm.as_operand(), target.as_operand()],
7577        );
7578    }
7579}
7580
7581impl CasEmitter<Gp, Gp, Mem> for Assembler<'_> {
7582    fn cas(&mut self, rs: Gp, rd: Gp, addr: Mem) {
7583        self.emit_n(
7584            InstId::Cas,
7585            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
7586        );
7587    }
7588}
7589
7590impl CasaEmitter<Gp, Gp, Mem> for Assembler<'_> {
7591    fn casa(&mut self, rs: Gp, rd: Gp, addr: Mem) {
7592        self.emit_n(
7593            InstId::Casa,
7594            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
7595        );
7596    }
7597}
7598
7599impl CasabEmitter<Gp, Gp, Mem> for Assembler<'_> {
7600    fn casab(&mut self, rs: Gp, rd: Gp, addr: Mem) {
7601        self.emit_n(
7602            InstId::Casab,
7603            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
7604        );
7605    }
7606}
7607
7608impl CasahEmitter<Gp, Gp, Mem> for Assembler<'_> {
7609    fn casah(&mut self, rs: Gp, rd: Gp, addr: Mem) {
7610        self.emit_n(
7611            InstId::Casah,
7612            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
7613        );
7614    }
7615}
7616
7617impl CasalEmitter<Gp, Gp, Mem> for Assembler<'_> {
7618    fn casal(&mut self, rs: Gp, rd: Gp, addr: Mem) {
7619        self.emit_n(
7620            InstId::Casal,
7621            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
7622        );
7623    }
7624}
7625
7626impl CasalbEmitter<Gp, Gp, Mem> for Assembler<'_> {
7627    fn casalb(&mut self, rs: Gp, rd: Gp, addr: Mem) {
7628        self.emit_n(
7629            InstId::Casalb,
7630            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
7631        );
7632    }
7633}
7634
7635impl CasalhEmitter<Gp, Gp, Mem> for Assembler<'_> {
7636    fn casalh(&mut self, rs: Gp, rd: Gp, addr: Mem) {
7637        self.emit_n(
7638            InstId::Casalh,
7639            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
7640        );
7641    }
7642}
7643
7644impl CasbEmitter<Gp, Gp, Mem> for Assembler<'_> {
7645    fn casb(&mut self, rs: Gp, rd: Gp, addr: Mem) {
7646        self.emit_n(
7647            InstId::Casb,
7648            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
7649        );
7650    }
7651}
7652
7653impl CashEmitter<Gp, Gp, Mem> for Assembler<'_> {
7654    fn cash(&mut self, rs: Gp, rd: Gp, addr: Mem) {
7655        self.emit_n(
7656            InstId::Cash,
7657            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
7658        );
7659    }
7660}
7661
7662impl CaslEmitter<Gp, Gp, Mem> for Assembler<'_> {
7663    fn casl(&mut self, rs: Gp, rd: Gp, addr: Mem) {
7664        self.emit_n(
7665            InstId::Casl,
7666            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
7667        );
7668    }
7669}
7670
7671impl CaslbEmitter<Gp, Gp, Mem> for Assembler<'_> {
7672    fn caslb(&mut self, rs: Gp, rd: Gp, addr: Mem) {
7673        self.emit_n(
7674            InstId::Caslb,
7675            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
7676        );
7677    }
7678}
7679
7680impl CaslhEmitter<Gp, Gp, Mem> for Assembler<'_> {
7681    fn caslh(&mut self, rs: Gp, rd: Gp, addr: Mem) {
7682        self.emit_n(
7683            InstId::Caslh,
7684            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
7685        );
7686    }
7687}
7688
7689impl CaspEmitter<Gp, Gp, Gp, Gp, Mem> for Assembler<'_> {
7690    fn casp(&mut self, rd: Gp, rn: Gp, rm1: Gp, rm2: Gp, addr: Mem) {
7691        self.emit_n(
7692            InstId::Casp,
7693            &[
7694                rd.as_operand(),
7695                rn.as_operand(),
7696                rm1.as_operand(),
7697                rm2.as_operand(),
7698                addr.as_operand(),
7699            ],
7700        );
7701    }
7702}
7703
7704impl CaspaEmitter<Gp, Gp, Gp, Gp, Mem> for Assembler<'_> {
7705    fn caspa(&mut self, rd: Gp, rn: Gp, rm1: Gp, rm2: Gp, addr: Mem) {
7706        self.emit_n(
7707            InstId::Caspa,
7708            &[
7709                rd.as_operand(),
7710                rn.as_operand(),
7711                rm1.as_operand(),
7712                rm2.as_operand(),
7713                addr.as_operand(),
7714            ],
7715        );
7716    }
7717}
7718
7719impl CaspalEmitter<Gp, Gp, Gp, Gp, Mem> for Assembler<'_> {
7720    fn caspal(&mut self, rd: Gp, rn: Gp, rm1: Gp, rm2: Gp, addr: Mem) {
7721        self.emit_n(
7722            InstId::Caspal,
7723            &[
7724                rd.as_operand(),
7725                rn.as_operand(),
7726                rm1.as_operand(),
7727                rm2.as_operand(),
7728                addr.as_operand(),
7729            ],
7730        );
7731    }
7732}
7733
7734impl CasplEmitter<Gp, Gp, Gp, Gp, Mem> for Assembler<'_> {
7735    fn caspl(&mut self, rd: Gp, rn: Gp, rm1: Gp, rm2: Gp, addr: Mem) {
7736        self.emit_n(
7737            InstId::Caspl,
7738            &[
7739                rd.as_operand(),
7740                rn.as_operand(),
7741                rm1.as_operand(),
7742                rm2.as_operand(),
7743                addr.as_operand(),
7744            ],
7745        );
7746    }
7747}
7748
7749impl LdaddEmitter<Gp, Gp, Mem> for Assembler<'_> {
7750    fn ldadd(&mut self, rs: Gp, rd: Gp, addr: Mem) {
7751        self.emit_n(
7752            InstId::Ldadd,
7753            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
7754        );
7755    }
7756}
7757
7758impl LdaddaEmitter<Gp, Gp, Mem> for Assembler<'_> {
7759    fn ldadda(&mut self, rs: Gp, rd: Gp, addr: Mem) {
7760        self.emit_n(
7761            InstId::Ldadda,
7762            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
7763        );
7764    }
7765}
7766
7767impl LdaddabEmitter<Gp, Gp, Mem> for Assembler<'_> {
7768    fn ldaddab(&mut self, rs: Gp, rd: Gp, addr: Mem) {
7769        self.emit_n(
7770            InstId::Ldaddab,
7771            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
7772        );
7773    }
7774}
7775
7776impl LdaddahEmitter<Gp, Gp, Mem> for Assembler<'_> {
7777    fn ldaddah(&mut self, rs: Gp, rd: Gp, addr: Mem) {
7778        self.emit_n(
7779            InstId::Ldaddah,
7780            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
7781        );
7782    }
7783}
7784
7785impl LdaddalEmitter<Gp, Gp, Mem> for Assembler<'_> {
7786    fn ldaddal(&mut self, rs: Gp, rd: Gp, addr: Mem) {
7787        self.emit_n(
7788            InstId::Ldaddal,
7789            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
7790        );
7791    }
7792}
7793
7794impl LdaddalbEmitter<Gp, Gp, Mem> for Assembler<'_> {
7795    fn ldaddalb(&mut self, rs: Gp, rd: Gp, addr: Mem) {
7796        self.emit_n(
7797            InstId::Ldaddalb,
7798            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
7799        );
7800    }
7801}
7802
7803impl LdaddalhEmitter<Gp, Gp, Mem> for Assembler<'_> {
7804    fn ldaddalh(&mut self, rs: Gp, rd: Gp, addr: Mem) {
7805        self.emit_n(
7806            InstId::Ldaddalh,
7807            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
7808        );
7809    }
7810}
7811
7812impl LdaddbEmitter<Gp, Gp, Mem> for Assembler<'_> {
7813    fn ldaddb(&mut self, rs: Gp, rd: Gp, addr: Mem) {
7814        self.emit_n(
7815            InstId::Ldaddb,
7816            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
7817        );
7818    }
7819}
7820
7821impl LdaddhEmitter<Gp, Gp, Mem> for Assembler<'_> {
7822    fn ldaddh(&mut self, rs: Gp, rd: Gp, addr: Mem) {
7823        self.emit_n(
7824            InstId::Ldaddh,
7825            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
7826        );
7827    }
7828}
7829
7830impl LdaddlEmitter<Gp, Gp, Mem> for Assembler<'_> {
7831    fn ldaddl(&mut self, rs: Gp, rd: Gp, addr: Mem) {
7832        self.emit_n(
7833            InstId::Ldaddl,
7834            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
7835        );
7836    }
7837}
7838
7839impl LdaddlbEmitter<Gp, Gp, Mem> for Assembler<'_> {
7840    fn ldaddlb(&mut self, rs: Gp, rd: Gp, addr: Mem) {
7841        self.emit_n(
7842            InstId::Ldaddlb,
7843            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
7844        );
7845    }
7846}
7847
7848impl LdaddlhEmitter<Gp, Gp, Mem> for Assembler<'_> {
7849    fn ldaddlh(&mut self, rs: Gp, rd: Gp, addr: Mem) {
7850        self.emit_n(
7851            InstId::Ldaddlh,
7852            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
7853        );
7854    }
7855}
7856
7857impl LdarEmitter<Gp, Mem> for Assembler<'_> {
7858    fn ldar(&mut self, rd: Gp, addr: Mem) {
7859        self.emit_n(InstId::Ldar, &[rd.as_operand(), addr.as_operand()]);
7860    }
7861}
7862
7863impl LdarbEmitter<Gp, Mem> for Assembler<'_> {
7864    fn ldarb(&mut self, rd: Gp, addr: Mem) {
7865        self.emit_n(InstId::Ldarb, &[rd.as_operand(), addr.as_operand()]);
7866    }
7867}
7868
7869impl LdarhEmitter<Gp, Mem> for Assembler<'_> {
7870    fn ldarh(&mut self, rd: Gp, addr: Mem) {
7871        self.emit_n(InstId::Ldarh, &[rd.as_operand(), addr.as_operand()]);
7872    }
7873}
7874
7875impl LdaxrEmitter<Gp, Mem> for Assembler<'_> {
7876    fn ldaxr(&mut self, rd: Gp, addr: Mem) {
7877        self.emit_n(InstId::Ldaxr, &[rd.as_operand(), addr.as_operand()]);
7878    }
7879}
7880
7881impl LdaxrbEmitter<Gp, Mem> for Assembler<'_> {
7882    fn ldaxrb(&mut self, rd: Gp, addr: Mem) {
7883        self.emit_n(InstId::Ldaxrb, &[rd.as_operand(), addr.as_operand()]);
7884    }
7885}
7886
7887impl LdaxrhEmitter<Gp, Mem> for Assembler<'_> {
7888    fn ldaxrh(&mut self, rd: Gp, addr: Mem) {
7889        self.emit_n(InstId::Ldaxrh, &[rd.as_operand(), addr.as_operand()]);
7890    }
7891}
7892
7893impl LdclrEmitter<Gp, Gp, Mem> for Assembler<'_> {
7894    fn ldclr(&mut self, rs: Gp, rd: Gp, addr: Mem) {
7895        self.emit_n(
7896            InstId::Ldclr,
7897            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
7898        );
7899    }
7900}
7901
7902impl LdclraEmitter<Gp, Gp, Mem> for Assembler<'_> {
7903    fn ldclra(&mut self, rs: Gp, rd: Gp, addr: Mem) {
7904        self.emit_n(
7905            InstId::Ldclra,
7906            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
7907        );
7908    }
7909}
7910
7911impl LdclrabEmitter<Gp, Gp, Mem> for Assembler<'_> {
7912    fn ldclrab(&mut self, rs: Gp, rd: Gp, addr: Mem) {
7913        self.emit_n(
7914            InstId::Ldclrab,
7915            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
7916        );
7917    }
7918}
7919
7920impl LdclrahEmitter<Gp, Gp, Mem> for Assembler<'_> {
7921    fn ldclrah(&mut self, rs: Gp, rd: Gp, addr: Mem) {
7922        self.emit_n(
7923            InstId::Ldclrah,
7924            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
7925        );
7926    }
7927}
7928
7929impl LdclralEmitter<Gp, Gp, Mem> for Assembler<'_> {
7930    fn ldclral(&mut self, rs: Gp, rd: Gp, addr: Mem) {
7931        self.emit_n(
7932            InstId::Ldclral,
7933            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
7934        );
7935    }
7936}
7937
7938impl LdclralbEmitter<Gp, Gp, Mem> for Assembler<'_> {
7939    fn ldclralb(&mut self, rs: Gp, rd: Gp, addr: Mem) {
7940        self.emit_n(
7941            InstId::Ldclralb,
7942            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
7943        );
7944    }
7945}
7946
7947impl LdclralhEmitter<Gp, Gp, Mem> for Assembler<'_> {
7948    fn ldclralh(&mut self, rs: Gp, rd: Gp, addr: Mem) {
7949        self.emit_n(
7950            InstId::Ldclralh,
7951            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
7952        );
7953    }
7954}
7955
7956impl LdclrbEmitter<Gp, Gp, Mem> for Assembler<'_> {
7957    fn ldclrb(&mut self, rs: Gp, rd: Gp, addr: Mem) {
7958        self.emit_n(
7959            InstId::Ldclrb,
7960            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
7961        );
7962    }
7963}
7964
7965impl LdclrhEmitter<Gp, Gp, Mem> for Assembler<'_> {
7966    fn ldclrh(&mut self, rs: Gp, rd: Gp, addr: Mem) {
7967        self.emit_n(
7968            InstId::Ldclrh,
7969            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
7970        );
7971    }
7972}
7973
7974impl LdclrlEmitter<Gp, Gp, Mem> for Assembler<'_> {
7975    fn ldclrl(&mut self, rs: Gp, rd: Gp, addr: Mem) {
7976        self.emit_n(
7977            InstId::Ldclrl,
7978            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
7979        );
7980    }
7981}
7982
7983impl LdclrlbEmitter<Gp, Gp, Mem> for Assembler<'_> {
7984    fn ldclrlb(&mut self, rs: Gp, rd: Gp, addr: Mem) {
7985        self.emit_n(
7986            InstId::Ldclrlb,
7987            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
7988        );
7989    }
7990}
7991
7992impl LdclrlhEmitter<Gp, Gp, Mem> for Assembler<'_> {
7993    fn ldclrlh(&mut self, rs: Gp, rd: Gp, addr: Mem) {
7994        self.emit_n(
7995            InstId::Ldclrlh,
7996            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
7997        );
7998    }
7999}
8000
8001impl LdeorEmitter<Gp, Gp, Mem> for Assembler<'_> {
8002    fn ldeor(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8003        self.emit_n(
8004            InstId::Ldeor,
8005            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8006        );
8007    }
8008}
8009
8010impl LdeoraEmitter<Gp, Gp, Mem> for Assembler<'_> {
8011    fn ldeora(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8012        self.emit_n(
8013            InstId::Ldeora,
8014            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8015        );
8016    }
8017}
8018
8019impl LdeorabEmitter<Gp, Gp, Mem> for Assembler<'_> {
8020    fn ldeorab(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8021        self.emit_n(
8022            InstId::Ldeorab,
8023            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8024        );
8025    }
8026}
8027
8028impl LdeorahEmitter<Gp, Gp, Mem> for Assembler<'_> {
8029    fn ldeorah(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8030        self.emit_n(
8031            InstId::Ldeorah,
8032            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8033        );
8034    }
8035}
8036
8037impl LdeoralEmitter<Gp, Gp, Mem> for Assembler<'_> {
8038    fn ldeoral(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8039        self.emit_n(
8040            InstId::Ldeoral,
8041            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8042        );
8043    }
8044}
8045
8046impl LdeoralbEmitter<Gp, Gp, Mem> for Assembler<'_> {
8047    fn ldeoralb(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8048        self.emit_n(
8049            InstId::Ldeoralb,
8050            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8051        );
8052    }
8053}
8054
8055impl LdeoralhEmitter<Gp, Gp, Mem> for Assembler<'_> {
8056    fn ldeoralh(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8057        self.emit_n(
8058            InstId::Ldeoralh,
8059            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8060        );
8061    }
8062}
8063
8064impl LdeorbEmitter<Gp, Gp, Mem> for Assembler<'_> {
8065    fn ldeorb(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8066        self.emit_n(
8067            InstId::Ldeorb,
8068            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8069        );
8070    }
8071}
8072
8073impl LdeorhEmitter<Gp, Gp, Mem> for Assembler<'_> {
8074    fn ldeorh(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8075        self.emit_n(
8076            InstId::Ldeorh,
8077            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8078        );
8079    }
8080}
8081
8082impl LdeorlEmitter<Gp, Gp, Mem> for Assembler<'_> {
8083    fn ldeorl(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8084        self.emit_n(
8085            InstId::Ldeorl,
8086            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8087        );
8088    }
8089}
8090
8091impl LdeorlbEmitter<Gp, Gp, Mem> for Assembler<'_> {
8092    fn ldeorlb(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8093        self.emit_n(
8094            InstId::Ldeorlb,
8095            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8096        );
8097    }
8098}
8099
8100impl LdeorlhEmitter<Gp, Gp, Mem> for Assembler<'_> {
8101    fn ldeorlh(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8102        self.emit_n(
8103            InstId::Ldeorlh,
8104            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8105        );
8106    }
8107}
8108
8109impl LdlarEmitter<Gp, Mem> for Assembler<'_> {
8110    fn ldlar(&mut self, rd: Gp, addr: Mem) {
8111        self.emit_n(InstId::Ldlar, &[rd.as_operand(), addr.as_operand()]);
8112    }
8113}
8114
8115impl LdlarbEmitter<Gp, Mem> for Assembler<'_> {
8116    fn ldlarb(&mut self, rd: Gp, addr: Mem) {
8117        self.emit_n(InstId::Ldlarb, &[rd.as_operand(), addr.as_operand()]);
8118    }
8119}
8120
8121impl LdlarhEmitter<Gp, Mem> for Assembler<'_> {
8122    fn ldlarh(&mut self, rd: Gp, addr: Mem) {
8123        self.emit_n(InstId::Ldlarh, &[rd.as_operand(), addr.as_operand()]);
8124    }
8125}
8126
8127impl LdnpEmitter<Gp, Gp, Mem> for Assembler<'_> {
8128    fn ldnp(&mut self, rd: Gp, rd2: Gp, addr: Mem) {
8129        self.emit_n(
8130            InstId::Ldnp,
8131            &[rd.as_operand(), rd2.as_operand(), addr.as_operand()],
8132        );
8133    }
8134}
8135
8136impl LdnpEmitter<Vec, Vec, Mem> for Assembler<'_> {
8137    fn ldnp(&mut self, rd: Vec, rd2: Vec, addr: Mem) {
8138        self.emit_n(
8139            InstId::Ldnp_v,
8140            &[rd.as_operand(), rd2.as_operand(), addr.as_operand()],
8141        );
8142    }
8143}
8144
8145impl LdpEmitter<Gp, Gp, Mem> for Assembler<'_> {
8146    fn ldp(&mut self, rd: Gp, rd2: Gp, addr: Mem) {
8147        self.emit_n(
8148            InstId::Ldp,
8149            &[rd.as_operand(), rd2.as_operand(), addr.as_operand()],
8150        );
8151    }
8152}
8153
8154impl LdpEmitter<Vec, Vec, Mem> for Assembler<'_> {
8155    fn ldp(&mut self, rd: Vec, rd2: Vec, addr: Mem) {
8156        self.emit_n(
8157            InstId::Ldp_v,
8158            &[rd.as_operand(), rd2.as_operand(), addr.as_operand()],
8159        );
8160    }
8161}
8162
8163impl LdpswEmitter<Gp, Gp, Mem> for Assembler<'_> {
8164    fn ldpsw(&mut self, rd: Gp, rd2: Gp, addr: Mem) {
8165        self.emit_n(
8166            InstId::Ldpsw,
8167            &[rd.as_operand(), rd2.as_operand(), addr.as_operand()],
8168        );
8169    }
8170}
8171
8172impl LdrEmitter<Gp, Mem> for Assembler<'_> {
8173    fn ldr(&mut self, rd: Gp, addr: Mem) {
8174        self.emit_n(InstId::Ldr, &[rd.as_operand(), addr.as_operand()]);
8175    }
8176}
8177
8178impl LdrEmitter<Vec, Mem> for Assembler<'_> {
8179    fn ldr(&mut self, rd: Vec, addr: Mem) {
8180        self.emit_n(InstId::Ldr_v, &[rd.as_operand(), addr.as_operand()]);
8181    }
8182}
8183
8184impl LdrbEmitter<Gp, Mem> for Assembler<'_> {
8185    fn ldrb(&mut self, rd: Gp, addr: Mem) {
8186        self.emit_n(InstId::Ldrb, &[rd.as_operand(), addr.as_operand()]);
8187    }
8188}
8189
8190impl LdrhEmitter<Gp, Mem> for Assembler<'_> {
8191    fn ldrh(&mut self, rd: Gp, addr: Mem) {
8192        self.emit_n(InstId::Ldrh, &[rd.as_operand(), addr.as_operand()]);
8193    }
8194}
8195
8196impl LdrsbEmitter<Gp, Mem> for Assembler<'_> {
8197    fn ldrsb(&mut self, rd: Gp, addr: Mem) {
8198        self.emit_n(InstId::Ldrsb, &[rd.as_operand(), addr.as_operand()]);
8199    }
8200}
8201
8202impl LdrshEmitter<Gp, Mem> for Assembler<'_> {
8203    fn ldrsh(&mut self, rd: Gp, addr: Mem) {
8204        self.emit_n(InstId::Ldrsh, &[rd.as_operand(), addr.as_operand()]);
8205    }
8206}
8207
8208impl LdrswEmitter<Gp, Mem> for Assembler<'_> {
8209    fn ldrsw(&mut self, rd: Gp, addr: Mem) {
8210        self.emit_n(InstId::Ldrsw, &[rd.as_operand(), addr.as_operand()]);
8211    }
8212}
8213
8214impl LdsetEmitter<Gp, Gp, Mem> for Assembler<'_> {
8215    fn ldset(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8216        self.emit_n(
8217            InstId::Ldset,
8218            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8219        );
8220    }
8221}
8222
8223impl LdsetaEmitter<Gp, Gp, Mem> for Assembler<'_> {
8224    fn ldseta(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8225        self.emit_n(
8226            InstId::Ldseta,
8227            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8228        );
8229    }
8230}
8231
8232impl LdsetabEmitter<Gp, Gp, Mem> for Assembler<'_> {
8233    fn ldsetab(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8234        self.emit_n(
8235            InstId::Ldsetab,
8236            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8237        );
8238    }
8239}
8240
8241impl LdsetahEmitter<Gp, Gp, Mem> for Assembler<'_> {
8242    fn ldsetah(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8243        self.emit_n(
8244            InstId::Ldsetah,
8245            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8246        );
8247    }
8248}
8249
8250impl LdsetalEmitter<Gp, Gp, Mem> for Assembler<'_> {
8251    fn ldsetal(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8252        self.emit_n(
8253            InstId::Ldsetal,
8254            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8255        );
8256    }
8257}
8258
8259impl LdsetalbEmitter<Gp, Gp, Mem> for Assembler<'_> {
8260    fn ldsetalb(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8261        self.emit_n(
8262            InstId::Ldsetalb,
8263            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8264        );
8265    }
8266}
8267
8268impl LdsetalhEmitter<Gp, Gp, Mem> for Assembler<'_> {
8269    fn ldsetalh(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8270        self.emit_n(
8271            InstId::Ldsetalh,
8272            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8273        );
8274    }
8275}
8276
8277impl LdsetbEmitter<Gp, Gp, Mem> for Assembler<'_> {
8278    fn ldsetb(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8279        self.emit_n(
8280            InstId::Ldsetb,
8281            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8282        );
8283    }
8284}
8285
8286impl LdsethEmitter<Gp, Gp, Mem> for Assembler<'_> {
8287    fn ldseth(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8288        self.emit_n(
8289            InstId::Ldseth,
8290            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8291        );
8292    }
8293}
8294
8295impl LdsetlEmitter<Gp, Gp, Mem> for Assembler<'_> {
8296    fn ldsetl(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8297        self.emit_n(
8298            InstId::Ldsetl,
8299            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8300        );
8301    }
8302}
8303
8304impl LdsetlbEmitter<Gp, Gp, Mem> for Assembler<'_> {
8305    fn ldsetlb(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8306        self.emit_n(
8307            InstId::Ldsetlb,
8308            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8309        );
8310    }
8311}
8312
8313impl LdsetlhEmitter<Gp, Gp, Mem> for Assembler<'_> {
8314    fn ldsetlh(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8315        self.emit_n(
8316            InstId::Ldsetlh,
8317            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8318        );
8319    }
8320}
8321
8322impl LdsmaxEmitter<Gp, Gp, Mem> for Assembler<'_> {
8323    fn ldsmax(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8324        self.emit_n(
8325            InstId::Ldsmax,
8326            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8327        );
8328    }
8329}
8330
8331impl LdsmaxaEmitter<Gp, Gp, Mem> for Assembler<'_> {
8332    fn ldsmaxa(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8333        self.emit_n(
8334            InstId::Ldsmaxa,
8335            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8336        );
8337    }
8338}
8339
8340impl LdsmaxabEmitter<Gp, Gp, Mem> for Assembler<'_> {
8341    fn ldsmaxab(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8342        self.emit_n(
8343            InstId::Ldsmaxab,
8344            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8345        );
8346    }
8347}
8348
8349impl LdsmaxahEmitter<Gp, Gp, Mem> for Assembler<'_> {
8350    fn ldsmaxah(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8351        self.emit_n(
8352            InstId::Ldsmaxah,
8353            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8354        );
8355    }
8356}
8357
8358impl LdsmaxalEmitter<Gp, Gp, Mem> for Assembler<'_> {
8359    fn ldsmaxal(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8360        self.emit_n(
8361            InstId::Ldsmaxal,
8362            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8363        );
8364    }
8365}
8366
8367impl LdsmaxalbEmitter<Gp, Gp, Mem> for Assembler<'_> {
8368    fn ldsmaxalb(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8369        self.emit_n(
8370            InstId::Ldsmaxalb,
8371            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8372        );
8373    }
8374}
8375
8376impl LdsmaxalhEmitter<Gp, Gp, Mem> for Assembler<'_> {
8377    fn ldsmaxalh(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8378        self.emit_n(
8379            InstId::Ldsmaxalh,
8380            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8381        );
8382    }
8383}
8384
8385impl LdsmaxbEmitter<Gp, Gp, Mem> for Assembler<'_> {
8386    fn ldsmaxb(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8387        self.emit_n(
8388            InstId::Ldsmaxb,
8389            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8390        );
8391    }
8392}
8393
8394impl LdsmaxhEmitter<Gp, Gp, Mem> for Assembler<'_> {
8395    fn ldsmaxh(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8396        self.emit_n(
8397            InstId::Ldsmaxh,
8398            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8399        );
8400    }
8401}
8402
8403impl LdsmaxlEmitter<Gp, Gp, Mem> for Assembler<'_> {
8404    fn ldsmaxl(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8405        self.emit_n(
8406            InstId::Ldsmaxl,
8407            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8408        );
8409    }
8410}
8411
8412impl LdsmaxlbEmitter<Gp, Gp, Mem> for Assembler<'_> {
8413    fn ldsmaxlb(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8414        self.emit_n(
8415            InstId::Ldsmaxlb,
8416            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8417        );
8418    }
8419}
8420
8421impl LdsmaxlhEmitter<Gp, Gp, Mem> for Assembler<'_> {
8422    fn ldsmaxlh(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8423        self.emit_n(
8424            InstId::Ldsmaxlh,
8425            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8426        );
8427    }
8428}
8429
8430impl LdsminEmitter<Gp, Gp, Mem> for Assembler<'_> {
8431    fn ldsmin(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8432        self.emit_n(
8433            InstId::Ldsmin,
8434            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8435        );
8436    }
8437}
8438
8439impl LdsminaEmitter<Gp, Gp, Mem> for Assembler<'_> {
8440    fn ldsmina(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8441        self.emit_n(
8442            InstId::Ldsmina,
8443            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8444        );
8445    }
8446}
8447
8448impl LdsminabEmitter<Gp, Gp, Mem> for Assembler<'_> {
8449    fn ldsminab(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8450        self.emit_n(
8451            InstId::Ldsminab,
8452            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8453        );
8454    }
8455}
8456
8457impl LdsminahEmitter<Gp, Gp, Mem> for Assembler<'_> {
8458    fn ldsminah(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8459        self.emit_n(
8460            InstId::Ldsminah,
8461            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8462        );
8463    }
8464}
8465
8466impl LdsminalEmitter<Gp, Gp, Mem> for Assembler<'_> {
8467    fn ldsminal(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8468        self.emit_n(
8469            InstId::Ldsminal,
8470            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8471        );
8472    }
8473}
8474
8475impl LdsminalbEmitter<Gp, Gp, Mem> for Assembler<'_> {
8476    fn ldsminalb(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8477        self.emit_n(
8478            InstId::Ldsminalb,
8479            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8480        );
8481    }
8482}
8483
8484impl LdsminalhEmitter<Gp, Gp, Mem> for Assembler<'_> {
8485    fn ldsminalh(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8486        self.emit_n(
8487            InstId::Ldsminalh,
8488            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8489        );
8490    }
8491}
8492
8493impl LdsminbEmitter<Gp, Gp, Mem> for Assembler<'_> {
8494    fn ldsminb(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8495        self.emit_n(
8496            InstId::Ldsminb,
8497            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8498        );
8499    }
8500}
8501
8502impl LdsminhEmitter<Gp, Gp, Mem> for Assembler<'_> {
8503    fn ldsminh(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8504        self.emit_n(
8505            InstId::Ldsminh,
8506            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8507        );
8508    }
8509}
8510
8511impl LdsminlEmitter<Gp, Gp, Mem> for Assembler<'_> {
8512    fn ldsminl(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8513        self.emit_n(
8514            InstId::Ldsminl,
8515            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8516        );
8517    }
8518}
8519
8520impl LdsminlbEmitter<Gp, Gp, Mem> for Assembler<'_> {
8521    fn ldsminlb(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8522        self.emit_n(
8523            InstId::Ldsminlb,
8524            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8525        );
8526    }
8527}
8528
8529impl LdsminlhEmitter<Gp, Gp, Mem> for Assembler<'_> {
8530    fn ldsminlh(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8531        self.emit_n(
8532            InstId::Ldsminlh,
8533            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8534        );
8535    }
8536}
8537
8538impl LdtrEmitter<Gp, Mem> for Assembler<'_> {
8539    fn ldtr(&mut self, rd: Gp, addr: Mem) {
8540        self.emit_n(InstId::Ldtr, &[rd.as_operand(), addr.as_operand()]);
8541    }
8542}
8543
8544impl LdtrbEmitter<Gp, Mem> for Assembler<'_> {
8545    fn ldtrb(&mut self, rd: Gp, addr: Mem) {
8546        self.emit_n(InstId::Ldtrb, &[rd.as_operand(), addr.as_operand()]);
8547    }
8548}
8549
8550impl LdtrhEmitter<Gp, Mem> for Assembler<'_> {
8551    fn ldtrh(&mut self, rd: Gp, addr: Mem) {
8552        self.emit_n(InstId::Ldtrh, &[rd.as_operand(), addr.as_operand()]);
8553    }
8554}
8555
8556impl LdtrsbEmitter<Gp, Mem> for Assembler<'_> {
8557    fn ldtrsb(&mut self, rd: Gp, addr: Mem) {
8558        self.emit_n(InstId::Ldtrsb, &[rd.as_operand(), addr.as_operand()]);
8559    }
8560}
8561
8562impl LdtrshEmitter<Gp, Mem> for Assembler<'_> {
8563    fn ldtrsh(&mut self, rd: Gp, addr: Mem) {
8564        self.emit_n(InstId::Ldtrsh, &[rd.as_operand(), addr.as_operand()]);
8565    }
8566}
8567
8568impl LdtrswEmitter<Gp, Mem> for Assembler<'_> {
8569    fn ldtrsw(&mut self, rd: Gp, addr: Mem) {
8570        self.emit_n(InstId::Ldtrsw, &[rd.as_operand(), addr.as_operand()]);
8571    }
8572}
8573
8574impl LdumaxEmitter<Gp, Gp, Mem> for Assembler<'_> {
8575    fn ldumax(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8576        self.emit_n(
8577            InstId::Ldumax,
8578            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8579        );
8580    }
8581}
8582
8583impl LdumaxaEmitter<Gp, Gp, Mem> for Assembler<'_> {
8584    fn ldumaxa(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8585        self.emit_n(
8586            InstId::Ldumaxa,
8587            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8588        );
8589    }
8590}
8591
8592impl LdumaxabEmitter<Gp, Gp, Mem> for Assembler<'_> {
8593    fn ldumaxab(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8594        self.emit_n(
8595            InstId::Ldumaxab,
8596            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8597        );
8598    }
8599}
8600
8601impl LdumaxahEmitter<Gp, Gp, Mem> for Assembler<'_> {
8602    fn ldumaxah(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8603        self.emit_n(
8604            InstId::Ldumaxah,
8605            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8606        );
8607    }
8608}
8609
8610impl LdumaxalEmitter<Gp, Gp, Mem> for Assembler<'_> {
8611    fn ldumaxal(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8612        self.emit_n(
8613            InstId::Ldumaxal,
8614            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8615        );
8616    }
8617}
8618
8619impl LdumaxalbEmitter<Gp, Gp, Mem> for Assembler<'_> {
8620    fn ldumaxalb(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8621        self.emit_n(
8622            InstId::Ldumaxalb,
8623            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8624        );
8625    }
8626}
8627
8628impl LdumaxalhEmitter<Gp, Gp, Mem> for Assembler<'_> {
8629    fn ldumaxalh(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8630        self.emit_n(
8631            InstId::Ldumaxalh,
8632            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8633        );
8634    }
8635}
8636
8637impl LdumaxbEmitter<Gp, Gp, Mem> for Assembler<'_> {
8638    fn ldumaxb(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8639        self.emit_n(
8640            InstId::Ldumaxb,
8641            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8642        );
8643    }
8644}
8645
8646impl LdumaxhEmitter<Gp, Gp, Mem> for Assembler<'_> {
8647    fn ldumaxh(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8648        self.emit_n(
8649            InstId::Ldumaxh,
8650            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8651        );
8652    }
8653}
8654
8655impl LdumaxlEmitter<Gp, Gp, Mem> for Assembler<'_> {
8656    fn ldumaxl(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8657        self.emit_n(
8658            InstId::Ldumaxl,
8659            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8660        );
8661    }
8662}
8663
8664impl LdumaxlbEmitter<Gp, Gp, Mem> for Assembler<'_> {
8665    fn ldumaxlb(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8666        self.emit_n(
8667            InstId::Ldumaxlb,
8668            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8669        );
8670    }
8671}
8672
8673impl LdumaxlhEmitter<Gp, Gp, Mem> for Assembler<'_> {
8674    fn ldumaxlh(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8675        self.emit_n(
8676            InstId::Ldumaxlh,
8677            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8678        );
8679    }
8680}
8681
8682impl LduminEmitter<Gp, Gp, Mem> for Assembler<'_> {
8683    fn ldumin(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8684        self.emit_n(
8685            InstId::Ldumin,
8686            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8687        );
8688    }
8689}
8690
8691impl LduminaEmitter<Gp, Gp, Mem> for Assembler<'_> {
8692    fn ldumina(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8693        self.emit_n(
8694            InstId::Ldumina,
8695            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8696        );
8697    }
8698}
8699
8700impl LduminabEmitter<Gp, Gp, Mem> for Assembler<'_> {
8701    fn lduminab(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8702        self.emit_n(
8703            InstId::Lduminab,
8704            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8705        );
8706    }
8707}
8708
8709impl LduminahEmitter<Gp, Gp, Mem> for Assembler<'_> {
8710    fn lduminah(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8711        self.emit_n(
8712            InstId::Lduminah,
8713            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8714        );
8715    }
8716}
8717
8718impl LduminalEmitter<Gp, Gp, Mem> for Assembler<'_> {
8719    fn lduminal(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8720        self.emit_n(
8721            InstId::Lduminal,
8722            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8723        );
8724    }
8725}
8726
8727impl LduminalbEmitter<Gp, Gp, Mem> for Assembler<'_> {
8728    fn lduminalb(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8729        self.emit_n(
8730            InstId::Lduminalb,
8731            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8732        );
8733    }
8734}
8735
8736impl LduminalhEmitter<Gp, Gp, Mem> for Assembler<'_> {
8737    fn lduminalh(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8738        self.emit_n(
8739            InstId::Lduminalh,
8740            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8741        );
8742    }
8743}
8744
8745impl LduminbEmitter<Gp, Gp, Mem> for Assembler<'_> {
8746    fn lduminb(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8747        self.emit_n(
8748            InstId::Lduminb,
8749            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8750        );
8751    }
8752}
8753
8754impl LduminhEmitter<Gp, Gp, Mem> for Assembler<'_> {
8755    fn lduminh(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8756        self.emit_n(
8757            InstId::Lduminh,
8758            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8759        );
8760    }
8761}
8762
8763impl LduminlEmitter<Gp, Gp, Mem> for Assembler<'_> {
8764    fn lduminl(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8765        self.emit_n(
8766            InstId::Lduminl,
8767            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8768        );
8769    }
8770}
8771
8772impl LduminlbEmitter<Gp, Gp, Mem> for Assembler<'_> {
8773    fn lduminlb(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8774        self.emit_n(
8775            InstId::Lduminlb,
8776            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8777        );
8778    }
8779}
8780
8781impl LduminlhEmitter<Gp, Gp, Mem> for Assembler<'_> {
8782    fn lduminlh(&mut self, rs: Gp, rd: Gp, addr: Mem) {
8783        self.emit_n(
8784            InstId::Lduminlh,
8785            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
8786        );
8787    }
8788}
8789
8790impl LdurEmitter<Gp, Mem> for Assembler<'_> {
8791    fn ldur(&mut self, rd: Gp, addr: Mem) {
8792        self.emit_n(InstId::Ldur, &[rd.as_operand(), addr.as_operand()]);
8793    }
8794}
8795
8796impl LdurEmitter<Vec, Mem> for Assembler<'_> {
8797    fn ldur(&mut self, rd: Vec, addr: Mem) {
8798        self.emit_n(InstId::Ldur_v, &[rd.as_operand(), addr.as_operand()]);
8799    }
8800}
8801
8802impl LdurbEmitter<Gp, Mem> for Assembler<'_> {
8803    fn ldurb(&mut self, rd: Gp, addr: Mem) {
8804        self.emit_n(InstId::Ldurb, &[rd.as_operand(), addr.as_operand()]);
8805    }
8806}
8807
8808impl LdurhEmitter<Gp, Mem> for Assembler<'_> {
8809    fn ldurh(&mut self, rd: Gp, addr: Mem) {
8810        self.emit_n(InstId::Ldurh, &[rd.as_operand(), addr.as_operand()]);
8811    }
8812}
8813
8814impl LdursbEmitter<Gp, Mem> for Assembler<'_> {
8815    fn ldursb(&mut self, rd: Gp, addr: Mem) {
8816        self.emit_n(InstId::Ldursb, &[rd.as_operand(), addr.as_operand()]);
8817    }
8818}
8819
8820impl LdurshEmitter<Gp, Mem> for Assembler<'_> {
8821    fn ldursh(&mut self, rd: Gp, addr: Mem) {
8822        self.emit_n(InstId::Ldursh, &[rd.as_operand(), addr.as_operand()]);
8823    }
8824}
8825
8826impl LdurswEmitter<Gp, Mem> for Assembler<'_> {
8827    fn ldursw(&mut self, rd: Gp, addr: Mem) {
8828        self.emit_n(InstId::Ldursw, &[rd.as_operand(), addr.as_operand()]);
8829    }
8830}
8831
8832impl LdxpEmitter<Gp, Gp, Mem> for Assembler<'_> {
8833    fn ldxp(&mut self, rd: Gp, rd2: Gp, addr: Mem) {
8834        self.emit_n(
8835            InstId::Ldxp,
8836            &[rd.as_operand(), rd2.as_operand(), addr.as_operand()],
8837        );
8838    }
8839}
8840
8841impl LdaxpEmitter<Gp, Gp, Mem> for Assembler<'_> {
8842    fn ldaxp(&mut self, rd: Gp, rd2: Gp, addr: Mem) {
8843        self.emit_n(
8844            InstId::Ldaxp,
8845            &[rd.as_operand(), rd2.as_operand(), addr.as_operand()],
8846        );
8847    }
8848}
8849
8850impl LdxrEmitter<Gp, Mem> for Assembler<'_> {
8851    fn ldxr(&mut self, rd: Gp, addr: Mem) {
8852        self.emit_n(InstId::Ldxr, &[rd.as_operand(), addr.as_operand()]);
8853    }
8854}
8855
8856impl LdxrbEmitter<Gp, Mem> for Assembler<'_> {
8857    fn ldxrb(&mut self, rd: Gp, addr: Mem) {
8858        self.emit_n(InstId::Ldxrb, &[rd.as_operand(), addr.as_operand()]);
8859    }
8860}
8861
8862impl LdxrhEmitter<Gp, Mem> for Assembler<'_> {
8863    fn ldxrh(&mut self, rd: Gp, addr: Mem) {
8864        self.emit_n(InstId::Ldxrh, &[rd.as_operand(), addr.as_operand()]);
8865    }
8866}
8867
8868impl PrfmEmitter<Imm, Mem> for Assembler<'_> {
8869    fn prfm(&mut self, prf_op: Imm, addr: Mem) {
8870        self.emit_n(InstId::Prfm, &[prf_op.as_operand(), addr.as_operand()]);
8871    }
8872}
8873
8874impl StaddEmitter<Gp, Mem> for Assembler<'_> {
8875    fn stadd(&mut self, rs: Gp, addr: Mem) {
8876        self.emit_n(InstId::Stadd, &[rs.as_operand(), addr.as_operand()]);
8877    }
8878}
8879
8880impl StaddbEmitter<Gp, Mem> for Assembler<'_> {
8881    fn staddb(&mut self, rs: Gp, addr: Mem) {
8882        self.emit_n(InstId::Staddb, &[rs.as_operand(), addr.as_operand()]);
8883    }
8884}
8885
8886impl StaddhEmitter<Gp, Mem> for Assembler<'_> {
8887    fn staddh(&mut self, rs: Gp, addr: Mem) {
8888        self.emit_n(InstId::Staddh, &[rs.as_operand(), addr.as_operand()]);
8889    }
8890}
8891
8892impl StaddlEmitter<Gp, Mem> for Assembler<'_> {
8893    fn staddl(&mut self, rs: Gp, addr: Mem) {
8894        self.emit_n(InstId::Staddl, &[rs.as_operand(), addr.as_operand()]);
8895    }
8896}
8897
8898impl StaddlbEmitter<Gp, Mem> for Assembler<'_> {
8899    fn staddlb(&mut self, rs: Gp, addr: Mem) {
8900        self.emit_n(InstId::Staddlb, &[rs.as_operand(), addr.as_operand()]);
8901    }
8902}
8903
8904impl StaddlhEmitter<Gp, Mem> for Assembler<'_> {
8905    fn staddlh(&mut self, rs: Gp, addr: Mem) {
8906        self.emit_n(InstId::Staddlh, &[rs.as_operand(), addr.as_operand()]);
8907    }
8908}
8909
8910impl StclrEmitter<Gp, Mem> for Assembler<'_> {
8911    fn stclr(&mut self, rs: Gp, addr: Mem) {
8912        self.emit_n(InstId::Stclr, &[rs.as_operand(), addr.as_operand()]);
8913    }
8914}
8915
8916impl StclrbEmitter<Gp, Mem> for Assembler<'_> {
8917    fn stclrb(&mut self, rs: Gp, addr: Mem) {
8918        self.emit_n(InstId::Stclrb, &[rs.as_operand(), addr.as_operand()]);
8919    }
8920}
8921
8922impl StclrhEmitter<Gp, Mem> for Assembler<'_> {
8923    fn stclrh(&mut self, rs: Gp, addr: Mem) {
8924        self.emit_n(InstId::Stclrh, &[rs.as_operand(), addr.as_operand()]);
8925    }
8926}
8927
8928impl StclrlEmitter<Gp, Mem> for Assembler<'_> {
8929    fn stclrl(&mut self, rs: Gp, addr: Mem) {
8930        self.emit_n(InstId::Stclrl, &[rs.as_operand(), addr.as_operand()]);
8931    }
8932}
8933
8934impl StclrlbEmitter<Gp, Mem> for Assembler<'_> {
8935    fn stclrlb(&mut self, rs: Gp, addr: Mem) {
8936        self.emit_n(InstId::Stclrlb, &[rs.as_operand(), addr.as_operand()]);
8937    }
8938}
8939
8940impl StclrlhEmitter<Gp, Mem> for Assembler<'_> {
8941    fn stclrlh(&mut self, rs: Gp, addr: Mem) {
8942        self.emit_n(InstId::Stclrlh, &[rs.as_operand(), addr.as_operand()]);
8943    }
8944}
8945
8946impl SteorEmitter<Gp, Mem> for Assembler<'_> {
8947    fn steor(&mut self, rs: Gp, addr: Mem) {
8948        self.emit_n(InstId::Steor, &[rs.as_operand(), addr.as_operand()]);
8949    }
8950}
8951
8952impl SteorbEmitter<Gp, Mem> for Assembler<'_> {
8953    fn steorb(&mut self, rs: Gp, addr: Mem) {
8954        self.emit_n(InstId::Steorb, &[rs.as_operand(), addr.as_operand()]);
8955    }
8956}
8957
8958impl SteorhEmitter<Gp, Mem> for Assembler<'_> {
8959    fn steorh(&mut self, rs: Gp, addr: Mem) {
8960        self.emit_n(InstId::Steorh, &[rs.as_operand(), addr.as_operand()]);
8961    }
8962}
8963
8964impl SteorlEmitter<Gp, Mem> for Assembler<'_> {
8965    fn steorl(&mut self, rs: Gp, addr: Mem) {
8966        self.emit_n(InstId::Steorl, &[rs.as_operand(), addr.as_operand()]);
8967    }
8968}
8969
8970impl SteorlbEmitter<Gp, Mem> for Assembler<'_> {
8971    fn steorlb(&mut self, rs: Gp, addr: Mem) {
8972        self.emit_n(InstId::Steorlb, &[rs.as_operand(), addr.as_operand()]);
8973    }
8974}
8975
8976impl SteorlhEmitter<Gp, Mem> for Assembler<'_> {
8977    fn steorlh(&mut self, rs: Gp, addr: Mem) {
8978        self.emit_n(InstId::Steorlh, &[rs.as_operand(), addr.as_operand()]);
8979    }
8980}
8981
8982impl StllrEmitter<Gp, Mem> for Assembler<'_> {
8983    fn stllr(&mut self, rs: Gp, addr: Mem) {
8984        self.emit_n(InstId::Stllr, &[rs.as_operand(), addr.as_operand()]);
8985    }
8986}
8987
8988impl StllrbEmitter<Gp, Mem> for Assembler<'_> {
8989    fn stllrb(&mut self, rs: Gp, addr: Mem) {
8990        self.emit_n(InstId::Stllrb, &[rs.as_operand(), addr.as_operand()]);
8991    }
8992}
8993
8994impl StllrhEmitter<Gp, Mem> for Assembler<'_> {
8995    fn stllrh(&mut self, rs: Gp, addr: Mem) {
8996        self.emit_n(InstId::Stllrh, &[rs.as_operand(), addr.as_operand()]);
8997    }
8998}
8999
9000impl StlrEmitter<Gp, Mem> for Assembler<'_> {
9001    fn stlr(&mut self, rs: Gp, addr: Mem) {
9002        self.emit_n(InstId::Stllr, &[rs.as_operand(), addr.as_operand()]);
9003    }
9004}
9005
9006impl StlrbEmitter<Gp, Mem> for Assembler<'_> {
9007    fn stlrb(&mut self, rs: Gp, addr: Mem) {
9008        self.emit_n(InstId::Stllrb, &[rs.as_operand(), addr.as_operand()]);
9009    }
9010}
9011
9012impl StlrhEmitter<Gp, Mem> for Assembler<'_> {
9013    fn stlrh(&mut self, rs: Gp, addr: Mem) {
9014        self.emit_n(InstId::Stllrh, &[rs.as_operand(), addr.as_operand()]);
9015    }
9016}
9017
9018impl StlxrEmitter<Gp, Gp, Mem> for Assembler<'_> {
9019    fn stlxr(&mut self, rd: Gp, rs: Gp, addr: Mem) {
9020        self.emit_n(
9021            InstId::Stlxr,
9022            &[rd.as_operand(), rs.as_operand(), addr.as_operand()],
9023        );
9024    }
9025}
9026
9027impl StlxrbEmitter<Gp, Gp, Mem> for Assembler<'_> {
9028    fn stlxrb(&mut self, rd: Gp, rs: Gp, addr: Mem) {
9029        self.emit_n(
9030            InstId::Stlxrb,
9031            &[rd.as_operand(), rs.as_operand(), addr.as_operand()],
9032        );
9033    }
9034}
9035
9036impl StlxrhEmitter<Gp, Gp, Mem> for Assembler<'_> {
9037    fn stlxrh(&mut self, rd: Gp, rs: Gp, addr: Mem) {
9038        self.emit_n(
9039            InstId::Stlxrh,
9040            &[rd.as_operand(), rs.as_operand(), addr.as_operand()],
9041        );
9042    }
9043}
9044
9045impl StnpEmitter<Gp, Gp, Mem> for Assembler<'_> {
9046    fn stnp(&mut self, rs_or_rd: Gp, rs2_or_rd2: Gp, addr: Mem) {
9047        self.emit_n(
9048            InstId::Stnp,
9049            &[
9050                rs_or_rd.as_operand(),
9051                rs2_or_rd2.as_operand(),
9052                addr.as_operand(),
9053            ],
9054        );
9055    }
9056}
9057
9058impl StnpEmitter<Vec, Vec, Mem> for Assembler<'_> {
9059    fn stnp(&mut self, rs_or_rd: Vec, rs2_or_rd2: Vec, addr: Mem) {
9060        self.emit_n(
9061            InstId::Stnp_v,
9062            &[
9063                rs_or_rd.as_operand(),
9064                rs2_or_rd2.as_operand(),
9065                addr.as_operand(),
9066            ],
9067        );
9068    }
9069}
9070
9071impl StpEmitter<Gp, Gp, Mem> for Assembler<'_> {
9072    fn stp(&mut self, rs_or_rd: Gp, rs2_or_rd2: Gp, addr: Mem) {
9073        self.emit_n(
9074            InstId::Stp,
9075            &[
9076                rs_or_rd.as_operand(),
9077                rs2_or_rd2.as_operand(),
9078                addr.as_operand(),
9079            ],
9080        );
9081    }
9082}
9083
9084impl StpEmitter<Vec, Vec, Mem> for Assembler<'_> {
9085    fn stp(&mut self, rs_or_rd: Vec, rs2_or_rd2: Vec, addr: Mem) {
9086        self.emit_n(
9087            InstId::Stp_v,
9088            &[
9089                rs_or_rd.as_operand(),
9090                rs2_or_rd2.as_operand(),
9091                addr.as_operand(),
9092            ],
9093        );
9094    }
9095}
9096
9097impl StrEmitter<Gp, Mem> for Assembler<'_> {
9098    fn str(&mut self, rs_or_rd: Gp, addr: Mem) {
9099        self.emit_n(InstId::Str, &[rs_or_rd.as_operand(), addr.as_operand()]);
9100    }
9101}
9102
9103impl StrEmitter<Vec, Mem> for Assembler<'_> {
9104    fn str(&mut self, rs_or_rd: Vec, addr: Mem) {
9105        self.emit_n(InstId::Str_v, &[rs_or_rd.as_operand(), addr.as_operand()]);
9106    }
9107}
9108
9109impl StrbEmitter<Gp, Mem> for Assembler<'_> {
9110    fn strb(&mut self, rs: Gp, addr: Mem) {
9111        self.emit_n(InstId::Strb, &[rs.as_operand(), addr.as_operand()]);
9112    }
9113}
9114
9115impl StrhEmitter<Gp, Mem> for Assembler<'_> {
9116    fn strh(&mut self, rs: Gp, addr: Mem) {
9117        self.emit_n(InstId::Strh, &[rs.as_operand(), addr.as_operand()]);
9118    }
9119}
9120
9121impl StsetEmitter<Gp, Mem> for Assembler<'_> {
9122    fn stset(&mut self, rs: Gp, addr: Mem) {
9123        self.emit_n(InstId::Stset, &[rs.as_operand(), addr.as_operand()]);
9124    }
9125}
9126
9127impl StsetbEmitter<Gp, Mem> for Assembler<'_> {
9128    fn stsetb(&mut self, rs: Gp, addr: Mem) {
9129        self.emit_n(InstId::Stsetb, &[rs.as_operand(), addr.as_operand()]);
9130    }
9131}
9132
9133impl StsethEmitter<Gp, Mem> for Assembler<'_> {
9134    fn stseth(&mut self, rs: Gp, addr: Mem) {
9135        self.emit_n(InstId::Stseth, &[rs.as_operand(), addr.as_operand()]);
9136    }
9137}
9138
9139impl StsetlEmitter<Gp, Mem> for Assembler<'_> {
9140    fn stsetl(&mut self, rs: Gp, addr: Mem) {
9141        self.emit_n(InstId::Stsetl, &[rs.as_operand(), addr.as_operand()]);
9142    }
9143}
9144
9145impl StsetlbEmitter<Gp, Mem> for Assembler<'_> {
9146    fn stsetlb(&mut self, rs: Gp, addr: Mem) {
9147        self.emit_n(InstId::Stsetlb, &[rs.as_operand(), addr.as_operand()]);
9148    }
9149}
9150
9151impl StsetlhEmitter<Gp, Mem> for Assembler<'_> {
9152    fn stsetlh(&mut self, rs: Gp, addr: Mem) {
9153        self.emit_n(InstId::Stsetlh, &[rs.as_operand(), addr.as_operand()]);
9154    }
9155}
9156
9157impl StsmaxEmitter<Gp, Mem> for Assembler<'_> {
9158    fn stsmax(&mut self, rs: Gp, addr: Mem) {
9159        self.emit_n(InstId::Stsmax, &[rs.as_operand(), addr.as_operand()]);
9160    }
9161}
9162
9163impl StsmaxbEmitter<Gp, Mem> for Assembler<'_> {
9164    fn stsmaxb(&mut self, rs: Gp, addr: Mem) {
9165        self.emit_n(InstId::Stsmaxb, &[rs.as_operand(), addr.as_operand()]);
9166    }
9167}
9168
9169impl StsmaxhEmitter<Gp, Mem> for Assembler<'_> {
9170    fn stsmaxh(&mut self, rs: Gp, addr: Mem) {
9171        self.emit_n(InstId::Stsmaxh, &[rs.as_operand(), addr.as_operand()]);
9172    }
9173}
9174
9175impl StsmaxlEmitter<Gp, Mem> for Assembler<'_> {
9176    fn stsmaxl(&mut self, rs: Gp, addr: Mem) {
9177        self.emit_n(InstId::Stsmaxl, &[rs.as_operand(), addr.as_operand()]);
9178    }
9179}
9180
9181impl StsmaxlbEmitter<Gp, Mem> for Assembler<'_> {
9182    fn stsmaxlb(&mut self, rs: Gp, addr: Mem) {
9183        self.emit_n(InstId::Stsmaxlb, &[rs.as_operand(), addr.as_operand()]);
9184    }
9185}
9186
9187impl StsmaxlhEmitter<Gp, Mem> for Assembler<'_> {
9188    fn stsmaxlh(&mut self, rs: Gp, addr: Mem) {
9189        self.emit_n(InstId::Stsmaxlh, &[rs.as_operand(), addr.as_operand()]);
9190    }
9191}
9192
9193impl StsminEmitter<Gp, Mem> for Assembler<'_> {
9194    fn stsmin(&mut self, rs: Gp, addr: Mem) {
9195        self.emit_n(InstId::Stsmin, &[rs.as_operand(), addr.as_operand()]);
9196    }
9197}
9198
9199impl StsminbEmitter<Gp, Mem> for Assembler<'_> {
9200    fn stsminb(&mut self, rs: Gp, addr: Mem) {
9201        self.emit_n(InstId::Stsminb, &[rs.as_operand(), addr.as_operand()]);
9202    }
9203}
9204
9205impl StsminhEmitter<Gp, Mem> for Assembler<'_> {
9206    fn stsminh(&mut self, rs: Gp, addr: Mem) {
9207        self.emit_n(InstId::Stsminh, &[rs.as_operand(), addr.as_operand()]);
9208    }
9209}
9210
9211impl StsminlEmitter<Gp, Mem> for Assembler<'_> {
9212    fn stsminl(&mut self, rs: Gp, addr: Mem) {
9213        self.emit_n(InstId::Stsminl, &[rs.as_operand(), addr.as_operand()]);
9214    }
9215}
9216
9217impl StsminlbEmitter<Gp, Mem> for Assembler<'_> {
9218    fn stsminlb(&mut self, rs: Gp, addr: Mem) {
9219        self.emit_n(InstId::Stsminlb, &[rs.as_operand(), addr.as_operand()]);
9220    }
9221}
9222
9223impl StsminlhEmitter<Gp, Mem> for Assembler<'_> {
9224    fn stsminlh(&mut self, rs: Gp, addr: Mem) {
9225        self.emit_n(InstId::Stsminlh, &[rs.as_operand(), addr.as_operand()]);
9226    }
9227}
9228
9229impl SttrEmitter<Gp, Mem> for Assembler<'_> {
9230    fn sttr(&mut self, rs: Gp, addr: Mem) {
9231        self.emit_n(InstId::Sttr, &[rs.as_operand(), addr.as_operand()]);
9232    }
9233}
9234
9235impl SttrbEmitter<Gp, Mem> for Assembler<'_> {
9236    fn sttrb(&mut self, rs: Gp, addr: Mem) {
9237        self.emit_n(InstId::Sttrb, &[rs.as_operand(), addr.as_operand()]);
9238    }
9239}
9240
9241impl SttrhEmitter<Gp, Mem> for Assembler<'_> {
9242    fn sttrh(&mut self, rs: Gp, addr: Mem) {
9243        self.emit_n(InstId::Sttrh, &[rs.as_operand(), addr.as_operand()]);
9244    }
9245}
9246
9247impl StumaxEmitter<Gp, Mem> for Assembler<'_> {
9248    fn stumax(&mut self, rs: Gp, addr: Mem) {
9249        self.emit_n(InstId::Stumax, &[rs.as_operand(), addr.as_operand()]);
9250    }
9251}
9252
9253impl StumaxbEmitter<Gp, Mem> for Assembler<'_> {
9254    fn stumaxb(&mut self, rs: Gp, addr: Mem) {
9255        self.emit_n(InstId::Stumaxb, &[rs.as_operand(), addr.as_operand()]);
9256    }
9257}
9258
9259impl StumaxhEmitter<Gp, Mem> for Assembler<'_> {
9260    fn stumaxh(&mut self, rs: Gp, addr: Mem) {
9261        self.emit_n(InstId::Stumaxh, &[rs.as_operand(), addr.as_operand()]);
9262    }
9263}
9264
9265impl StumaxlEmitter<Gp, Mem> for Assembler<'_> {
9266    fn stumaxl(&mut self, rs: Gp, addr: Mem) {
9267        self.emit_n(InstId::Stumaxl, &[rs.as_operand(), addr.as_operand()]);
9268    }
9269}
9270
9271impl StumaxlbEmitter<Gp, Mem> for Assembler<'_> {
9272    fn stumaxlb(&mut self, rs: Gp, addr: Mem) {
9273        self.emit_n(InstId::Stumaxlb, &[rs.as_operand(), addr.as_operand()]);
9274    }
9275}
9276
9277impl StumaxlhEmitter<Gp, Mem> for Assembler<'_> {
9278    fn stumaxlh(&mut self, rs: Gp, addr: Mem) {
9279        self.emit_n(InstId::Stumaxlh, &[rs.as_operand(), addr.as_operand()]);
9280    }
9281}
9282
9283impl StuminEmitter<Gp, Mem> for Assembler<'_> {
9284    fn stumin(&mut self, rs: Gp, addr: Mem) {
9285        self.emit_n(InstId::Stumin, &[rs.as_operand(), addr.as_operand()]);
9286    }
9287}
9288
9289impl StuminbEmitter<Gp, Mem> for Assembler<'_> {
9290    fn stuminb(&mut self, rs: Gp, addr: Mem) {
9291        self.emit_n(InstId::Stuminb, &[rs.as_operand(), addr.as_operand()]);
9292    }
9293}
9294
9295impl StuminhEmitter<Gp, Mem> for Assembler<'_> {
9296    fn stuminh(&mut self, rs: Gp, addr: Mem) {
9297        self.emit_n(InstId::Stuminh, &[rs.as_operand(), addr.as_operand()]);
9298    }
9299}
9300
9301impl StuminlEmitter<Gp, Mem> for Assembler<'_> {
9302    fn stuminl(&mut self, rs: Gp, addr: Mem) {
9303        self.emit_n(InstId::Stuminl, &[rs.as_operand(), addr.as_operand()]);
9304    }
9305}
9306
9307impl StuminlbEmitter<Gp, Mem> for Assembler<'_> {
9308    fn stuminlb(&mut self, rs: Gp, addr: Mem) {
9309        self.emit_n(InstId::Stuminlb, &[rs.as_operand(), addr.as_operand()]);
9310    }
9311}
9312
9313impl StuminlhEmitter<Gp, Mem> for Assembler<'_> {
9314    fn stuminlh(&mut self, rs: Gp, addr: Mem) {
9315        self.emit_n(InstId::Stuminlh, &[rs.as_operand(), addr.as_operand()]);
9316    }
9317}
9318
9319impl SturEmitter<Gp, Mem> for Assembler<'_> {
9320    fn stur(&mut self, rs_or_rd: Gp, addr: Mem) {
9321        self.emit_n(InstId::Stur, &[rs_or_rd.as_operand(), addr.as_operand()]);
9322    }
9323}
9324
9325impl SturEmitter<Vec, Mem> for Assembler<'_> {
9326    fn stur(&mut self, rs_or_rd: Vec, addr: Mem) {
9327        self.emit_n(InstId::Stur_v, &[rs_or_rd.as_operand(), addr.as_operand()]);
9328    }
9329}
9330
9331impl SturbEmitter<Gp, Mem> for Assembler<'_> {
9332    fn sturb(&mut self, rs: Gp, addr: Mem) {
9333        self.emit_n(InstId::Sturb, &[rs.as_operand(), addr.as_operand()]);
9334    }
9335}
9336
9337impl SturhEmitter<Gp, Mem> for Assembler<'_> {
9338    fn sturh(&mut self, rs: Gp, addr: Mem) {
9339        self.emit_n(InstId::Sturh, &[rs.as_operand(), addr.as_operand()]);
9340    }
9341}
9342
9343impl StxpEmitter<Gp, Gp, Gp, Mem> for Assembler<'_> {
9344    fn stxp(&mut self, rd: Gp, rs: Gp, rs2: Gp, addr: Mem) {
9345        self.emit_n(
9346            InstId::Stxp,
9347            &[
9348                rd.as_operand(),
9349                rs.as_operand(),
9350                rs2.as_operand(),
9351                addr.as_operand(),
9352            ],
9353        );
9354    }
9355}
9356
9357impl StlxpEmitter<Gp, Gp, Gp, Mem> for Assembler<'_> {
9358    fn stlxp(&mut self, rd: Gp, rs: Gp, rs2: Gp, addr: Mem) {
9359        self.emit_n(
9360            InstId::Stlxp,
9361            &[
9362                rd.as_operand(),
9363                rs.as_operand(),
9364                rs2.as_operand(),
9365                addr.as_operand(),
9366            ],
9367        );
9368    }
9369}
9370
9371impl StxrEmitter<Gp, Gp, Mem> for Assembler<'_> {
9372    fn stxr(&mut self, rd: Gp, rs: Gp, addr: Mem) {
9373        self.emit_n(
9374            InstId::Stxr,
9375            &[rd.as_operand(), rs.as_operand(), addr.as_operand()],
9376        );
9377    }
9378}
9379
9380impl StxrbEmitter<Gp, Gp, Mem> for Assembler<'_> {
9381    fn stxrb(&mut self, rd: Gp, rs: Gp, addr: Mem) {
9382        self.emit_n(
9383            InstId::Stxrb,
9384            &[rd.as_operand(), rs.as_operand(), addr.as_operand()],
9385        );
9386    }
9387}
9388
9389impl StxrhEmitter<Gp, Gp, Mem> for Assembler<'_> {
9390    fn stxrh(&mut self, rd: Gp, rs: Gp, addr: Mem) {
9391        self.emit_n(
9392            InstId::Stxrh,
9393            &[rd.as_operand(), rs.as_operand(), addr.as_operand()],
9394        );
9395    }
9396}
9397
9398impl SwpEmitter<Gp, Gp, Mem> for Assembler<'_> {
9399    fn swp(&mut self, rs: Gp, rd: Gp, addr: Mem) {
9400        self.emit_n(
9401            InstId::Swp,
9402            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
9403        );
9404    }
9405}
9406
9407impl SwpaEmitter<Gp, Gp, Mem> for Assembler<'_> {
9408    fn swpa(&mut self, rs: Gp, rd: Gp, addr: Mem) {
9409        self.emit_n(
9410            InstId::Swpa,
9411            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
9412        );
9413    }
9414}
9415
9416impl SwpabEmitter<Gp, Gp, Mem> for Assembler<'_> {
9417    fn swpab(&mut self, rs: Gp, rd: Gp, addr: Mem) {
9418        self.emit_n(
9419            InstId::Swpab,
9420            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
9421        );
9422    }
9423}
9424
9425impl SwpahEmitter<Gp, Gp, Mem> for Assembler<'_> {
9426    fn swpah(&mut self, rs: Gp, rd: Gp, addr: Mem) {
9427        self.emit_n(
9428            InstId::Swpah,
9429            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
9430        );
9431    }
9432}
9433
9434impl SwpalEmitter<Gp, Gp, Mem> for Assembler<'_> {
9435    fn swpal(&mut self, rs: Gp, rd: Gp, addr: Mem) {
9436        self.emit_n(
9437            InstId::Swpal,
9438            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
9439        );
9440    }
9441}
9442
9443impl SwpalbEmitter<Gp, Gp, Mem> for Assembler<'_> {
9444    fn swpalb(&mut self, rs: Gp, rd: Gp, addr: Mem) {
9445        self.emit_n(
9446            InstId::Swpalb,
9447            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
9448        );
9449    }
9450}
9451
9452impl SwpalhEmitter<Gp, Gp, Mem> for Assembler<'_> {
9453    fn swpalh(&mut self, rs: Gp, rd: Gp, addr: Mem) {
9454        self.emit_n(
9455            InstId::Swpalh,
9456            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
9457        );
9458    }
9459}
9460
9461impl SwpbEmitter<Gp, Gp, Mem> for Assembler<'_> {
9462    fn swpb(&mut self, rs: Gp, rd: Gp, addr: Mem) {
9463        self.emit_n(
9464            InstId::Swpb,
9465            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
9466        );
9467    }
9468}
9469
9470impl SwphEmitter<Gp, Gp, Mem> for Assembler<'_> {
9471    fn swph(&mut self, rs: Gp, rd: Gp, addr: Mem) {
9472        self.emit_n(
9473            InstId::Swph,
9474            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
9475        );
9476    }
9477}
9478
9479impl SwplEmitter<Gp, Gp, Mem> for Assembler<'_> {
9480    fn swpl(&mut self, rs: Gp, rd: Gp, addr: Mem) {
9481        self.emit_n(
9482            InstId::Swpl,
9483            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
9484        );
9485    }
9486}
9487
9488impl SwplbEmitter<Gp, Gp, Mem> for Assembler<'_> {
9489    fn swplb(&mut self, rs: Gp, rd: Gp, addr: Mem) {
9490        self.emit_n(
9491            InstId::Swplb,
9492            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
9493        );
9494    }
9495}
9496
9497impl SwplhEmitter<Gp, Gp, Mem> for Assembler<'_> {
9498    fn swplh(&mut self, rs: Gp, rd: Gp, addr: Mem) {
9499        self.emit_n(
9500            InstId::Swplh,
9501            &[rs.as_operand(), rd.as_operand(), addr.as_operand()],
9502        );
9503    }
9504}
9505
9506impl BtiEmitter<Imm> for Assembler<'_> {
9507    fn bti(&mut self, targets: Imm) {
9508        self.emit_n(InstId::Bti, &[targets.as_operand()]);
9509    }
9510}
9511
9512impl ChkfeatEmitter<Gp> for Assembler<'_> {
9513    fn chkfeat(&mut self, rd: Gp) {
9514        self.emit_n(InstId::Chkfeat, &[rd.as_operand()]);
9515    }
9516}
9517
9518impl ClrbhbEmitter for Assembler<'_> {
9519    fn clrbhb(&mut self) {
9520        self.emit_n(InstId::Clrbhb, &[]);
9521    }
9522}
9523
9524impl Crc32bEmitter<Gp, Gp, Gp> for Assembler<'_> {
9525    fn crc32b(&mut self, rd: Gp, rn: Gp, rm: Gp) {
9526        self.emit_n(
9527            InstId::Crc32b,
9528            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
9529        );
9530    }
9531}
9532
9533impl Crc32hEmitter<Gp, Gp, Gp> for Assembler<'_> {
9534    fn crc32h(&mut self, rd: Gp, rn: Gp, rm: Gp) {
9535        self.emit_n(
9536            InstId::Crc32h,
9537            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
9538        );
9539    }
9540}
9541
9542impl Crc32wEmitter<Gp, Gp, Gp> for Assembler<'_> {
9543    fn crc32w(&mut self, rd: Gp, rn: Gp, rm: Gp) {
9544        self.emit_n(
9545            InstId::Crc32w,
9546            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
9547        );
9548    }
9549}
9550
9551impl Crc32xEmitter<Gp, Gp, Gp> for Assembler<'_> {
9552    fn crc32x(&mut self, rd: Gp, rn: Gp, rm: Gp) {
9553        self.emit_n(
9554            InstId::Crc32x,
9555            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
9556        );
9557    }
9558}
9559
9560impl Crc32cbEmitter<Gp, Gp, Gp> for Assembler<'_> {
9561    fn crc32cb(&mut self, rd: Gp, rn: Gp, rm: Gp) {
9562        self.emit_n(
9563            InstId::Crc32cb,
9564            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
9565        );
9566    }
9567}
9568
9569impl Crc32chEmitter<Gp, Gp, Gp> for Assembler<'_> {
9570    fn crc32ch(&mut self, rd: Gp, rn: Gp, rm: Gp) {
9571        self.emit_n(
9572            InstId::Crc32ch,
9573            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
9574        );
9575    }
9576}
9577
9578impl Crc32cwEmitter<Gp, Gp, Gp> for Assembler<'_> {
9579    fn crc32cw(&mut self, rd: Gp, rn: Gp, rm: Gp) {
9580        self.emit_n(
9581            InstId::Crc32cw,
9582            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
9583        );
9584    }
9585}
9586
9587impl Crc32cxEmitter<Gp, Gp, Gp> for Assembler<'_> {
9588    fn crc32cx(&mut self, rd: Gp, rn: Gp, rm: Gp) {
9589        self.emit_n(
9590            InstId::Crc32cx,
9591            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
9592        );
9593    }
9594}
9595
9596impl AbsEmitter<Gp, Gp> for Assembler<'_> {
9597    fn abs(&mut self, rd: Gp, rn: Gp) {
9598        self.emit_n(InstId::Abs, &[rd.as_operand(), rn.as_operand()]);
9599    }
9600}
9601
9602impl AbsEmitter<Vec, Vec> for Assembler<'_> {
9603    fn abs(&mut self, rd: Vec, rn: Vec) {
9604        self.emit_n(InstId::Abs_v, &[rd.as_operand(), rn.as_operand()]);
9605    }
9606}
9607
9608impl CntEmitter<Gp, Gp> for Assembler<'_> {
9609    fn cnt(&mut self, rd: Gp, rn: Gp) {
9610        self.emit_n(InstId::Cnt, &[rd.as_operand(), rn.as_operand()]);
9611    }
9612}
9613
9614impl CntEmitter<Vec, Vec> for Assembler<'_> {
9615    fn cnt(&mut self, rd: Vec, rn: Vec) {
9616        self.emit_n(InstId::Cnt_v, &[rd.as_operand(), rn.as_operand()]);
9617    }
9618}
9619
9620impl CtzEmitter<Gp, Gp> for Assembler<'_> {
9621    fn ctz(&mut self, rd: Gp, rn: Gp) {
9622        self.emit_n(InstId::Ctz, &[rd.as_operand(), rn.as_operand()]);
9623    }
9624}
9625
9626impl SmaxEmitter<Gp, Gp, Gp> for Assembler<'_> {
9627    fn smax(&mut self, rd: Gp, rn: Gp, rm_or_imm: Gp) {
9628        self.emit_n(
9629            InstId::Smax,
9630            &[rd.as_operand(), rn.as_operand(), rm_or_imm.as_operand()],
9631        );
9632    }
9633}
9634
9635impl SmaxEmitter<Gp, Gp, Imm> for Assembler<'_> {
9636    fn smax(&mut self, rd: Gp, rn: Gp, rm_or_imm: Imm) {
9637        self.emit_n(
9638            InstId::Smax,
9639            &[rd.as_operand(), rn.as_operand(), rm_or_imm.as_operand()],
9640        );
9641    }
9642}
9643
9644impl SmaxEmitter<Vec, Vec, Vec> for Assembler<'_> {
9645    fn smax(&mut self, rd: Vec, rn: Vec, rm_or_imm: Vec) {
9646        self.emit_n(
9647            InstId::Smax_v,
9648            &[rd.as_operand(), rn.as_operand(), rm_or_imm.as_operand()],
9649        );
9650    }
9651}
9652
9653impl SminEmitter<Gp, Gp, Gp> for Assembler<'_> {
9654    fn smin(&mut self, rd: Gp, rn: Gp, rm_or_imm: Gp) {
9655        self.emit_n(
9656            InstId::Smin,
9657            &[rd.as_operand(), rn.as_operand(), rm_or_imm.as_operand()],
9658        );
9659    }
9660}
9661
9662impl SminEmitter<Gp, Gp, Imm> for Assembler<'_> {
9663    fn smin(&mut self, rd: Gp, rn: Gp, rm_or_imm: Imm) {
9664        self.emit_n(
9665            InstId::Smin,
9666            &[rd.as_operand(), rn.as_operand(), rm_or_imm.as_operand()],
9667        );
9668    }
9669}
9670
9671impl SminEmitter<Vec, Vec, Vec> for Assembler<'_> {
9672    fn smin(&mut self, rd: Vec, rn: Vec, rm_or_imm: Vec) {
9673        self.emit_n(
9674            InstId::Smin_v,
9675            &[rd.as_operand(), rn.as_operand(), rm_or_imm.as_operand()],
9676        );
9677    }
9678}
9679
9680impl UmaxEmitter<Gp, Gp, Gp> for Assembler<'_> {
9681    fn umax(&mut self, rd: Gp, rn: Gp, rm_or_imm: Gp) {
9682        self.emit_n(
9683            InstId::Umax,
9684            &[rd.as_operand(), rn.as_operand(), rm_or_imm.as_operand()],
9685        );
9686    }
9687}
9688
9689impl UmaxEmitter<Gp, Gp, Imm> for Assembler<'_> {
9690    fn umax(&mut self, rd: Gp, rn: Gp, rm_or_imm: Imm) {
9691        self.emit_n(
9692            InstId::Umax,
9693            &[rd.as_operand(), rn.as_operand(), rm_or_imm.as_operand()],
9694        );
9695    }
9696}
9697
9698impl UmaxEmitter<Vec, Vec, Vec> for Assembler<'_> {
9699    fn umax(&mut self, rd: Vec, rn: Vec, rm_or_imm: Vec) {
9700        self.emit_n(
9701            InstId::Umax_v,
9702            &[rd.as_operand(), rn.as_operand(), rm_or_imm.as_operand()],
9703        );
9704    }
9705}
9706
9707impl UminEmitter<Gp, Gp, Gp> for Assembler<'_> {
9708    fn umin(&mut self, rd: Gp, rn: Gp, rm_or_imm: Gp) {
9709        self.emit_n(
9710            InstId::Umin,
9711            &[rd.as_operand(), rn.as_operand(), rm_or_imm.as_operand()],
9712        );
9713    }
9714}
9715
9716impl UminEmitter<Gp, Gp, Imm> for Assembler<'_> {
9717    fn umin(&mut self, rd: Gp, rn: Gp, rm_or_imm: Imm) {
9718        self.emit_n(
9719            InstId::Umin,
9720            &[rd.as_operand(), rn.as_operand(), rm_or_imm.as_operand()],
9721        );
9722    }
9723}
9724
9725impl UminEmitter<Vec, Vec, Vec> for Assembler<'_> {
9726    fn umin(&mut self, rd: Vec, rn: Vec, rm_or_imm: Vec) {
9727        self.emit_n(
9728            InstId::Umin_v,
9729            &[rd.as_operand(), rn.as_operand(), rm_or_imm.as_operand()],
9730        );
9731    }
9732}
9733
9734impl DghEmitter for Assembler<'_> {
9735    fn dgh(&mut self) {
9736        self.emit_n(InstId::Dgh, &[]);
9737    }
9738}
9739
9740impl CfinvEmitter for Assembler<'_> {
9741    fn cfinv(&mut self) {
9742        self.emit_n(InstId::Cfinv, &[]);
9743    }
9744}
9745
9746impl Setf8Emitter<Gp> for Assembler<'_> {
9747    fn setf8(&mut self, rn: Gp) {
9748        self.emit_n(InstId::Setf8, &[rn.as_operand()]);
9749    }
9750}
9751
9752impl Setf16Emitter<Gp> for Assembler<'_> {
9753    fn setf16(&mut self, rn: Gp) {
9754        self.emit_n(InstId::Setf16, &[rn.as_operand()]);
9755    }
9756}
9757
9758impl AxflagEmitter for Assembler<'_> {
9759    fn axflag(&mut self) {
9760        self.emit_n(InstId::Axflag, &[]);
9761    }
9762}
9763
9764impl XaflagEmitter for Assembler<'_> {
9765    fn xaflag(&mut self) {
9766        self.emit_n(InstId::Xaflag, &[]);
9767    }
9768}
9769
9770impl BcEmitter<Imm> for Assembler<'_> {
9771    fn bc(&mut self, target: Imm) {
9772        self.emit_n(InstId::Bc, &[target.as_operand()]);
9773    }
9774    fn bc_eq(&mut self, target: Imm) {
9775        self.emit_n(InstId::Bc.with_cc(CondCode::EQ), &[target.as_operand()]);
9776    }
9777    fn bc_ne(&mut self, target: Imm) {
9778        self.emit_n(InstId::Bc.with_cc(CondCode::NE), &[target.as_operand()]);
9779    }
9780    fn bc_cs(&mut self, target: Imm) {
9781        self.emit_n(InstId::Bc.with_cc(CondCode::CS), &[target.as_operand()]);
9782    }
9783    fn bc_hs(&mut self, target: Imm) {
9784        self.emit_n(InstId::Bc.with_cc(CondCode::HS), &[target.as_operand()]);
9785    }
9786    fn bc_cc(&mut self, target: Imm) {
9787        self.emit_n(InstId::Bc.with_cc(CondCode::CC), &[target.as_operand()]);
9788    }
9789    fn bc_lo(&mut self, target: Imm) {
9790        self.emit_n(InstId::Bc.with_cc(CondCode::LO), &[target.as_operand()]);
9791    }
9792    fn bc_mi(&mut self, target: Imm) {
9793        self.emit_n(InstId::Bc.with_cc(CondCode::MI), &[target.as_operand()]);
9794    }
9795    fn bc_pl(&mut self, target: Imm) {
9796        self.emit_n(InstId::Bc.with_cc(CondCode::PL), &[target.as_operand()]);
9797    }
9798    fn bc_vs(&mut self, target: Imm) {
9799        self.emit_n(InstId::Bc.with_cc(CondCode::VS), &[target.as_operand()]);
9800    }
9801    fn bc_vc(&mut self, target: Imm) {
9802        self.emit_n(InstId::Bc.with_cc(CondCode::VC), &[target.as_operand()]);
9803    }
9804    fn bc_hi(&mut self, target: Imm) {
9805        self.emit_n(InstId::Bc.with_cc(CondCode::HI), &[target.as_operand()]);
9806    }
9807    fn bc_ls(&mut self, target: Imm) {
9808        self.emit_n(InstId::Bc.with_cc(CondCode::LS), &[target.as_operand()]);
9809    }
9810    fn bc_ge(&mut self, target: Imm) {
9811        self.emit_n(InstId::Bc.with_cc(CondCode::GE), &[target.as_operand()]);
9812    }
9813    fn bc_lt(&mut self, target: Imm) {
9814        self.emit_n(InstId::Bc.with_cc(CondCode::LT), &[target.as_operand()]);
9815    }
9816    fn bc_gt(&mut self, target: Imm) {
9817        self.emit_n(InstId::Bc.with_cc(CondCode::GT), &[target.as_operand()]);
9818    }
9819    fn bc_le(&mut self, target: Imm) {
9820        self.emit_n(InstId::Bc.with_cc(CondCode::LE), &[target.as_operand()]);
9821    }
9822    fn bc_al(&mut self, target: Imm) {
9823        self.emit_n(InstId::Bc.with_cc(CondCode::AL), &[target.as_operand()]);
9824    }
9825}
9826
9827impl BcEmitter<Label> for Assembler<'_> {
9828    fn bc(&mut self, target: Label) {
9829        self.emit_n(InstId::Bc, &[target.as_operand()]);
9830    }
9831    fn bc_eq(&mut self, target: Label) {
9832        self.emit_n(InstId::Bc.with_cc(CondCode::EQ), &[target.as_operand()]);
9833    }
9834    fn bc_ne(&mut self, target: Label) {
9835        self.emit_n(InstId::Bc.with_cc(CondCode::NE), &[target.as_operand()]);
9836    }
9837    fn bc_cs(&mut self, target: Label) {
9838        self.emit_n(InstId::Bc.with_cc(CondCode::CS), &[target.as_operand()]);
9839    }
9840    fn bc_hs(&mut self, target: Label) {
9841        self.emit_n(InstId::Bc.with_cc(CondCode::HS), &[target.as_operand()]);
9842    }
9843    fn bc_cc(&mut self, target: Label) {
9844        self.emit_n(InstId::Bc.with_cc(CondCode::CC), &[target.as_operand()]);
9845    }
9846    fn bc_lo(&mut self, target: Label) {
9847        self.emit_n(InstId::Bc.with_cc(CondCode::LO), &[target.as_operand()]);
9848    }
9849    fn bc_mi(&mut self, target: Label) {
9850        self.emit_n(InstId::Bc.with_cc(CondCode::MI), &[target.as_operand()]);
9851    }
9852    fn bc_pl(&mut self, target: Label) {
9853        self.emit_n(InstId::Bc.with_cc(CondCode::PL), &[target.as_operand()]);
9854    }
9855    fn bc_vs(&mut self, target: Label) {
9856        self.emit_n(InstId::Bc.with_cc(CondCode::VS), &[target.as_operand()]);
9857    }
9858    fn bc_vc(&mut self, target: Label) {
9859        self.emit_n(InstId::Bc.with_cc(CondCode::VC), &[target.as_operand()]);
9860    }
9861    fn bc_hi(&mut self, target: Label) {
9862        self.emit_n(InstId::Bc.with_cc(CondCode::HI), &[target.as_operand()]);
9863    }
9864    fn bc_ls(&mut self, target: Label) {
9865        self.emit_n(InstId::Bc.with_cc(CondCode::LS), &[target.as_operand()]);
9866    }
9867    fn bc_ge(&mut self, target: Label) {
9868        self.emit_n(InstId::Bc.with_cc(CondCode::GE), &[target.as_operand()]);
9869    }
9870    fn bc_lt(&mut self, target: Label) {
9871        self.emit_n(InstId::Bc.with_cc(CondCode::LT), &[target.as_operand()]);
9872    }
9873    fn bc_gt(&mut self, target: Label) {
9874        self.emit_n(InstId::Bc.with_cc(CondCode::GT), &[target.as_operand()]);
9875    }
9876    fn bc_le(&mut self, target: Label) {
9877        self.emit_n(InstId::Bc.with_cc(CondCode::LE), &[target.as_operand()]);
9878    }
9879    fn bc_al(&mut self, target: Label) {
9880        self.emit_n(InstId::Bc.with_cc(CondCode::AL), &[target.as_operand()]);
9881    }
9882}
9883
9884impl BcEmitter<Sym> for Assembler<'_> {
9885    fn bc(&mut self, target: Sym) {
9886        self.emit_n(InstId::Bc, &[target.as_operand()]);
9887    }
9888    fn bc_eq(&mut self, target: Sym) {
9889        self.emit_n(InstId::Bc.with_cc(CondCode::EQ), &[target.as_operand()]);
9890    }
9891    fn bc_ne(&mut self, target: Sym) {
9892        self.emit_n(InstId::Bc.with_cc(CondCode::NE), &[target.as_operand()]);
9893    }
9894    fn bc_cs(&mut self, target: Sym) {
9895        self.emit_n(InstId::Bc.with_cc(CondCode::CS), &[target.as_operand()]);
9896    }
9897    fn bc_hs(&mut self, target: Sym) {
9898        self.emit_n(InstId::Bc.with_cc(CondCode::HS), &[target.as_operand()]);
9899    }
9900    fn bc_cc(&mut self, target: Sym) {
9901        self.emit_n(InstId::Bc.with_cc(CondCode::CC), &[target.as_operand()]);
9902    }
9903    fn bc_lo(&mut self, target: Sym) {
9904        self.emit_n(InstId::Bc.with_cc(CondCode::LO), &[target.as_operand()]);
9905    }
9906    fn bc_mi(&mut self, target: Sym) {
9907        self.emit_n(InstId::Bc.with_cc(CondCode::MI), &[target.as_operand()]);
9908    }
9909    fn bc_pl(&mut self, target: Sym) {
9910        self.emit_n(InstId::Bc.with_cc(CondCode::PL), &[target.as_operand()]);
9911    }
9912    fn bc_vs(&mut self, target: Sym) {
9913        self.emit_n(InstId::Bc.with_cc(CondCode::VS), &[target.as_operand()]);
9914    }
9915    fn bc_vc(&mut self, target: Sym) {
9916        self.emit_n(InstId::Bc.with_cc(CondCode::VC), &[target.as_operand()]);
9917    }
9918    fn bc_hi(&mut self, target: Sym) {
9919        self.emit_n(InstId::Bc.with_cc(CondCode::HI), &[target.as_operand()]);
9920    }
9921    fn bc_ls(&mut self, target: Sym) {
9922        self.emit_n(InstId::Bc.with_cc(CondCode::LS), &[target.as_operand()]);
9923    }
9924    fn bc_ge(&mut self, target: Sym) {
9925        self.emit_n(InstId::Bc.with_cc(CondCode::GE), &[target.as_operand()]);
9926    }
9927    fn bc_lt(&mut self, target: Sym) {
9928        self.emit_n(InstId::Bc.with_cc(CondCode::LT), &[target.as_operand()]);
9929    }
9930    fn bc_gt(&mut self, target: Sym) {
9931        self.emit_n(InstId::Bc.with_cc(CondCode::GT), &[target.as_operand()]);
9932    }
9933    fn bc_le(&mut self, target: Sym) {
9934        self.emit_n(InstId::Bc.with_cc(CondCode::LE), &[target.as_operand()]);
9935    }
9936    fn bc_al(&mut self, target: Sym) {
9937        self.emit_n(InstId::Bc.with_cc(CondCode::AL), &[target.as_operand()]);
9938    }
9939}
9940
9941impl AutdaEmitter<Gp, Gp> for Assembler<'_> {
9942    fn autda(&mut self, rd: Gp, rn: Gp) {
9943        self.emit_n(InstId::Autda, &[rd.as_operand(), rn.as_operand()]);
9944    }
9945}
9946
9947impl AutdbEmitter<Gp, Gp> for Assembler<'_> {
9948    fn autdb(&mut self, rd: Gp, rn: Gp) {
9949        self.emit_n(InstId::Autdb, &[rd.as_operand(), rn.as_operand()]);
9950    }
9951}
9952
9953impl AutdzaEmitter<Gp> for Assembler<'_> {
9954    fn autdza(&mut self, rd: Gp) {
9955        self.emit_n(InstId::Autdza, &[rd.as_operand()]);
9956    }
9957}
9958
9959impl AutdzbEmitter<Gp> for Assembler<'_> {
9960    fn autdzb(&mut self, rd: Gp) {
9961        self.emit_n(InstId::Autdzb, &[rd.as_operand()]);
9962    }
9963}
9964
9965impl AutiaEmitter<Gp, Gp> for Assembler<'_> {
9966    fn autia(&mut self, rd: Gp, rn: Gp) {
9967        self.emit_n(InstId::Autia, &[rd.as_operand(), rn.as_operand()]);
9968    }
9969}
9970
9971impl Autia1716Emitter for Assembler<'_> {
9972    fn autia1716(&mut self) {
9973        self.emit_n(InstId::Autia1716, &[]);
9974    }
9975}
9976
9977impl AutiaspEmitter for Assembler<'_> {
9978    fn autiasp(&mut self) {
9979        self.emit_n(InstId::Autiasp, &[]);
9980    }
9981}
9982
9983impl AutiazEmitter for Assembler<'_> {
9984    fn autiaz(&mut self) {
9985        self.emit_n(InstId::Autiaz, &[]);
9986    }
9987}
9988
9989impl AutibEmitter<Gp, Gp> for Assembler<'_> {
9990    fn autib(&mut self, rd: Gp, rn: Gp) {
9991        self.emit_n(InstId::Autib, &[rd.as_operand(), rn.as_operand()]);
9992    }
9993}
9994
9995impl Autib1716Emitter for Assembler<'_> {
9996    fn autib1716(&mut self) {
9997        self.emit_n(InstId::Autib1716, &[]);
9998    }
9999}
10000
10001impl AutibspEmitter for Assembler<'_> {
10002    fn autibsp(&mut self) {
10003        self.emit_n(InstId::Autibsp, &[]);
10004    }
10005}
10006
10007impl AutibzEmitter for Assembler<'_> {
10008    fn autibz(&mut self) {
10009        self.emit_n(InstId::Autibz, &[]);
10010    }
10011}
10012
10013impl AutizaEmitter<Gp> for Assembler<'_> {
10014    fn autiza(&mut self, rd: Gp) {
10015        self.emit_n(InstId::Autiza, &[rd.as_operand()]);
10016    }
10017}
10018
10019impl AutizbEmitter<Gp> for Assembler<'_> {
10020    fn autizb(&mut self, rd: Gp) {
10021        self.emit_n(InstId::Autizb, &[rd.as_operand()]);
10022    }
10023}
10024
10025impl GmiEmitter<Gp, Gp, Gp> for Assembler<'_> {
10026    fn gmi(&mut self, rd: Gp, rn: Gp, rm: Gp) {
10027        self.emit_n(
10028            InstId::Gmi,
10029            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
10030        );
10031    }
10032}
10033
10034impl CmppEmitter<Gp, Gp> for Assembler<'_> {
10035    fn cmpp(&mut self, rn: Gp, rm: Gp) {
10036        self.emit_n(InstId::Cmpp, &[rn.as_operand(), rm.as_operand()]);
10037    }
10038}
10039
10040impl AddgEmitter<Gp, Gp, Imm, Imm> for Assembler<'_> {
10041    fn addg(&mut self, rd: Gp, rn: Gp, imm1: Imm, imm2: Imm) {
10042        self.emit_n(
10043            InstId::Addg,
10044            &[
10045                rd.as_operand(),
10046                rn.as_operand(),
10047                imm1.as_operand(),
10048                imm2.as_operand(),
10049            ],
10050        );
10051    }
10052}
10053
10054impl LdgEmitter<Gp, Mem> for Assembler<'_> {
10055    fn ldg(&mut self, rd: Gp, addr: Mem) {
10056        self.emit_n(InstId::Ldg, &[rd.as_operand(), addr.as_operand()]);
10057    }
10058}
10059
10060impl LdgmEmitter<Gp, Mem> for Assembler<'_> {
10061    fn ldgm(&mut self, rd: Gp, addr: Mem) {
10062        self.emit_n(InstId::Ldgm, &[rd.as_operand(), addr.as_operand()]);
10063    }
10064}
10065
10066impl LdraaEmitter<Gp, Mem> for Assembler<'_> {
10067    fn ldraa(&mut self, rd: Gp, addr: Mem) {
10068        self.emit_n(InstId::Ldraa, &[rd.as_operand(), addr.as_operand()]);
10069    }
10070}
10071
10072impl LdrabEmitter<Gp, Mem> for Assembler<'_> {
10073    fn ldrab(&mut self, rd: Gp, addr: Mem) {
10074        self.emit_n(InstId::Ldrab, &[rd.as_operand(), addr.as_operand()]);
10075    }
10076}
10077
10078impl PacdaEmitter<Gp, Gp> for Assembler<'_> {
10079    fn pacda(&mut self, rd: Gp, rn: Gp) {
10080        self.emit_n(InstId::Pacda, &[rd.as_operand(), rn.as_operand()]);
10081    }
10082}
10083
10084impl PacdbEmitter<Gp, Gp> for Assembler<'_> {
10085    fn pacdb(&mut self, rd: Gp, rn: Gp) {
10086        self.emit_n(InstId::Pacdb, &[rd.as_operand(), rn.as_operand()]);
10087    }
10088}
10089
10090impl PacdzaEmitter<Gp> for Assembler<'_> {
10091    fn pacdza(&mut self, rd: Gp) {
10092        self.emit_n(InstId::Pacdza, &[rd.as_operand()]);
10093    }
10094}
10095
10096impl PacdzbEmitter<Gp> for Assembler<'_> {
10097    fn pacdzb(&mut self, rd: Gp) {
10098        self.emit_n(InstId::Pacdzb, &[rd.as_operand()]);
10099    }
10100}
10101
10102impl PacgaEmitter<Gp, Gp, Gp> for Assembler<'_> {
10103    fn pacga(&mut self, rd: Gp, rn: Gp, rm: Gp) {
10104        self.emit_n(
10105            InstId::Pacga,
10106            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
10107        );
10108    }
10109}
10110
10111impl SubpEmitter<Gp, Gp, Gp> for Assembler<'_> {
10112    fn subp(&mut self, rd: Gp, rn: Gp, rm: Gp) {
10113        self.emit_n(
10114            InstId::Subp,
10115            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
10116        );
10117    }
10118}
10119
10120impl SubpsEmitter<Gp, Gp, Gp> for Assembler<'_> {
10121    fn subps(&mut self, rd: Gp, rn: Gp, rm: Gp) {
10122        self.emit_n(
10123            InstId::Subps,
10124            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
10125        );
10126    }
10127}
10128
10129impl SubgEmitter<Gp, Gp, Imm, Imm> for Assembler<'_> {
10130    fn subg(&mut self, rd: Gp, rn: Gp, imm1: Imm, imm2: Imm) {
10131        self.emit_n(
10132            InstId::Subg,
10133            &[
10134                rd.as_operand(),
10135                rn.as_operand(),
10136                imm1.as_operand(),
10137                imm2.as_operand(),
10138            ],
10139        );
10140    }
10141}
10142
10143impl St2gEmitter<Gp, Mem> for Assembler<'_> {
10144    fn st2g(&mut self, rs: Gp, addr: Mem) {
10145        self.emit_n(InstId::St2g, &[rs.as_operand(), addr.as_operand()]);
10146    }
10147}
10148
10149impl StgEmitter<Gp, Mem> for Assembler<'_> {
10150    fn stg(&mut self, rs: Gp, addr: Mem) {
10151        self.emit_n(InstId::Stg, &[rs.as_operand(), addr.as_operand()]);
10152    }
10153}
10154
10155impl StgpEmitter<Gp, Gp, Mem> for Assembler<'_> {
10156    fn stgp(&mut self, rs: Gp, rs2: Gp, addr: Mem) {
10157        self.emit_n(
10158            InstId::Stgp,
10159            &[rs.as_operand(), rs2.as_operand(), addr.as_operand()],
10160        );
10161    }
10162}
10163
10164impl StgmEmitter<Gp, Mem> for Assembler<'_> {
10165    fn stgm(&mut self, rs: Gp, addr: Mem) {
10166        self.emit_n(InstId::Stgm, &[rs.as_operand(), addr.as_operand()]);
10167    }
10168}
10169
10170impl StzgEmitter<Gp, Mem> for Assembler<'_> {
10171    fn stzg(&mut self, rs: Gp, addr: Mem) {
10172        self.emit_n(InstId::Stzg, &[rs.as_operand(), addr.as_operand()]);
10173    }
10174}
10175
10176impl Stz2gEmitter<Gp, Mem> for Assembler<'_> {
10177    fn stz2g(&mut self, rs: Gp, addr: Mem) {
10178        self.emit_n(InstId::Stz2g, &[rs.as_operand(), addr.as_operand()]);
10179    }
10180}
10181
10182impl StzgmEmitter<Gp, Mem> for Assembler<'_> {
10183    fn stzgm(&mut self, rs: Gp, addr: Mem) {
10184        self.emit_n(InstId::Stzgm, &[rs.as_operand(), addr.as_operand()]);
10185    }
10186}
10187
10188impl XpacdEmitter<Gp> for Assembler<'_> {
10189    fn xpacd(&mut self, rd: Gp) {
10190        self.emit_n(InstId::Xpacd, &[rd.as_operand()]);
10191    }
10192}
10193
10194impl XpaciEmitter<Gp> for Assembler<'_> {
10195    fn xpaci(&mut self, rd: Gp) {
10196        self.emit_n(InstId::Xpaci, &[rd.as_operand()]);
10197    }
10198}
10199
10200impl XpaclriEmitter for Assembler<'_> {
10201    fn xpaclri(&mut self) {
10202        self.emit_n(InstId::Xpaclri, &[]);
10203    }
10204}
10205
10206impl HintEmitter<Imm> for Assembler<'_> {
10207    fn hint(&mut self, imm: Imm) {
10208        self.emit_n(InstId::Hint, &[imm.as_operand()]);
10209    }
10210}
10211
10212impl NopEmitter for Assembler<'_> {
10213    fn nop(&mut self) {
10214        self.emit_n(InstId::Nop, &[]);
10215    }
10216}
10217
10218impl SevEmitter for Assembler<'_> {
10219    fn sev(&mut self) {
10220        self.emit_n(InstId::Sev, &[]);
10221    }
10222}
10223
10224impl SevlEmitter for Assembler<'_> {
10225    fn sevl(&mut self) {
10226        self.emit_n(InstId::Sevl, &[]);
10227    }
10228}
10229
10230impl WfeEmitter for Assembler<'_> {
10231    fn wfe(&mut self) {
10232        self.emit_n(InstId::Wfe, &[]);
10233    }
10234}
10235
10236impl WfiEmitter for Assembler<'_> {
10237    fn wfi(&mut self) {
10238        self.emit_n(InstId::Wfi, &[]);
10239    }
10240}
10241
10242impl YieldEmitter for Assembler<'_> {
10243    fn r#yield(&mut self) {
10244        self.emit_n(InstId::Yield, &[]);
10245    }
10246}
10247
10248impl AddhnEmitter<Vec, Vec, Vec> for Assembler<'_> {
10249    fn addhn(&mut self, rd: Vec, rn: Vec, rm: Vec) {
10250        self.emit_n(
10251            InstId::Addhn_v,
10252            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
10253        );
10254    }
10255}
10256
10257impl Addhn2Emitter<Vec, Vec, Vec> for Assembler<'_> {
10258    fn addhn2(&mut self, operand_1: Vec, rn: Vec, rm: Vec) {
10259        self.emit_n(
10260            InstId::Addhn2_v,
10261            &[operand_1.as_operand(), rn.as_operand(), rm.as_operand()],
10262        );
10263    }
10264}
10265
10266impl AddpEmitter<Vec, Vec> for Assembler<'_> {
10267    fn addp(&mut self, rd: Vec, rn: Vec) {
10268        self.emit_n(InstId::Addp_v, &[rd.as_operand(), rn.as_operand()]);
10269    }
10270}
10271
10272impl Addp3Emitter<Vec, Vec, Vec> for Assembler<'_> {
10273    fn addp_3(&mut self, rd: Vec, rn: Vec, rm: Vec) {
10274        self.emit_n(
10275            InstId::Addp_v,
10276            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
10277        );
10278    }
10279}
10280
10281impl AddvEmitter<Vec, Vec> for Assembler<'_> {
10282    fn addv(&mut self, rd: Vec, rn: Vec) {
10283        self.emit_n(InstId::Addv_v, &[rd.as_operand(), rn.as_operand()]);
10284    }
10285}
10286
10287impl Bic2Emitter<Vec, Imm> for Assembler<'_> {
10288    fn bic_2(&mut self, rd: Vec, rn_or_imm: Imm) {
10289        self.emit_n(InstId::Bic_v, &[rd.as_operand(), rn_or_imm.as_operand()]);
10290    }
10291}
10292
10293impl BifEmitter<Vec, Vec, Vec> for Assembler<'_> {
10294    fn bif(&mut self, operand_1: Vec, rn: Vec, rm: Vec) {
10295        self.emit_n(
10296            InstId::Bif_v,
10297            &[operand_1.as_operand(), rn.as_operand(), rm.as_operand()],
10298        );
10299    }
10300}
10301
10302impl BitEmitter<Vec, Vec, Vec> for Assembler<'_> {
10303    fn bit(&mut self, operand_1: Vec, rn: Vec, rm: Vec) {
10304        self.emit_n(
10305            InstId::Bit_v,
10306            &[operand_1.as_operand(), rn.as_operand(), rm.as_operand()],
10307        );
10308    }
10309}
10310
10311impl BslEmitter<Vec, Vec, Vec> for Assembler<'_> {
10312    fn bsl(&mut self, operand_1: Vec, rn: Vec, rm: Vec) {
10313        self.emit_n(
10314            InstId::Bsl_v,
10315            &[operand_1.as_operand(), rn.as_operand(), rm.as_operand()],
10316        );
10317    }
10318}
10319
10320impl CmeqEmitter<Vec, Vec, Vec> for Assembler<'_> {
10321    fn cmeq(&mut self, rd: Vec, rn: Vec, rm_or_operand_3: Vec) {
10322        self.emit_n(
10323            InstId::Cmeq_v,
10324            &[
10325                rd.as_operand(),
10326                rn.as_operand(),
10327                rm_or_operand_3.as_operand(),
10328            ],
10329        );
10330    }
10331}
10332
10333impl CmeqEmitter<Vec, Vec, Imm> for Assembler<'_> {
10334    fn cmeq(&mut self, rd: Vec, rn: Vec, rm_or_operand_3: Imm) {
10335        self.emit_n(
10336            InstId::Cmeq_v,
10337            &[
10338                rd.as_operand(),
10339                rn.as_operand(),
10340                rm_or_operand_3.as_operand(),
10341            ],
10342        );
10343    }
10344}
10345
10346impl CmgeEmitter<Vec, Vec, Vec> for Assembler<'_> {
10347    fn cmge(&mut self, rd: Vec, rn: Vec, rm_or_operand_3: Vec) {
10348        self.emit_n(
10349            InstId::Cmge_v,
10350            &[
10351                rd.as_operand(),
10352                rn.as_operand(),
10353                rm_or_operand_3.as_operand(),
10354            ],
10355        );
10356    }
10357}
10358
10359impl CmgeEmitter<Vec, Vec, Imm> for Assembler<'_> {
10360    fn cmge(&mut self, rd: Vec, rn: Vec, rm_or_operand_3: Imm) {
10361        self.emit_n(
10362            InstId::Cmge_v,
10363            &[
10364                rd.as_operand(),
10365                rn.as_operand(),
10366                rm_or_operand_3.as_operand(),
10367            ],
10368        );
10369    }
10370}
10371
10372impl CmgtEmitter<Vec, Vec, Vec> for Assembler<'_> {
10373    fn cmgt(&mut self, rd: Vec, rn: Vec, rm_or_operand_3: Vec) {
10374        self.emit_n(
10375            InstId::Cmgt_v,
10376            &[
10377                rd.as_operand(),
10378                rn.as_operand(),
10379                rm_or_operand_3.as_operand(),
10380            ],
10381        );
10382    }
10383}
10384
10385impl CmgtEmitter<Vec, Vec, Imm> for Assembler<'_> {
10386    fn cmgt(&mut self, rd: Vec, rn: Vec, rm_or_operand_3: Imm) {
10387        self.emit_n(
10388            InstId::Cmgt_v,
10389            &[
10390                rd.as_operand(),
10391                rn.as_operand(),
10392                rm_or_operand_3.as_operand(),
10393            ],
10394        );
10395    }
10396}
10397
10398impl CmhiEmitter<Vec, Vec, Vec> for Assembler<'_> {
10399    fn cmhi(&mut self, rd: Vec, rn: Vec, rm: Vec) {
10400        self.emit_n(
10401            InstId::Cmhi_v,
10402            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
10403        );
10404    }
10405}
10406
10407impl CmhsEmitter<Vec, Vec, Vec> for Assembler<'_> {
10408    fn cmhs(&mut self, rd: Vec, rn: Vec, rm: Vec) {
10409        self.emit_n(
10410            InstId::Cmhs_v,
10411            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
10412        );
10413    }
10414}
10415
10416impl CmleEmitter<Vec, Vec, Imm> for Assembler<'_> {
10417    fn cmle(&mut self, rd: Vec, rn: Vec, operand_3: Imm) {
10418        self.emit_n(
10419            InstId::Cmle_v,
10420            &[rd.as_operand(), rn.as_operand(), operand_3.as_operand()],
10421        );
10422    }
10423}
10424
10425impl CmltEmitter<Vec, Vec, Imm> for Assembler<'_> {
10426    fn cmlt(&mut self, rd: Vec, rn: Vec, operand_3: Imm) {
10427        self.emit_n(
10428            InstId::Cmlt_v,
10429            &[rd.as_operand(), rn.as_operand(), operand_3.as_operand()],
10430        );
10431    }
10432}
10433
10434impl CmtstEmitter<Vec, Vec, Vec> for Assembler<'_> {
10435    fn cmtst(&mut self, rd: Vec, rn: Vec, rm: Vec) {
10436        self.emit_n(
10437            InstId::Cmtst_v,
10438            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
10439        );
10440    }
10441}
10442
10443impl DupEmitter<Vec, Gp> for Assembler<'_> {
10444    fn dup(&mut self, rd: Vec, rn: Gp) {
10445        self.emit_n(InstId::Dup_v, &[rd.as_operand(), rn.as_operand()]);
10446    }
10447}
10448
10449impl DupEmitter<Vec, Vec> for Assembler<'_> {
10450    fn dup(&mut self, rd: Vec, rn: Vec) {
10451        self.emit_n(InstId::Dup_v, &[rd.as_operand(), rn.as_operand()]);
10452    }
10453}
10454
10455impl ExtEmitter<Vec, Vec, Vec, Imm> for Assembler<'_> {
10456    fn ext(&mut self, rd: Vec, rn: Vec, rm: Vec, idx: Imm) {
10457        self.emit_n(
10458            InstId::Ext_v,
10459            &[
10460                rd.as_operand(),
10461                rn.as_operand(),
10462                rm.as_operand(),
10463                idx.as_operand(),
10464            ],
10465        );
10466    }
10467}
10468
10469impl FabdEmitter<Vec, Vec, Vec> for Assembler<'_> {
10470    fn fabd(&mut self, rd: Vec, rn: Vec, rm: Vec) {
10471        self.emit_n(
10472            InstId::Fabd_v,
10473            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
10474        );
10475    }
10476}
10477
10478impl FabsEmitter<Vec, Vec> for Assembler<'_> {
10479    fn fabs(&mut self, rd: Vec, rn: Vec) {
10480        self.emit_n(InstId::Fabs_v, &[rd.as_operand(), rn.as_operand()]);
10481    }
10482}
10483
10484impl FacgeEmitter<Vec, Vec, Vec> for Assembler<'_> {
10485    fn facge(&mut self, rd: Vec, rn: Vec, rm: Vec) {
10486        self.emit_n(
10487            InstId::Facge_v,
10488            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
10489        );
10490    }
10491}
10492
10493impl FacgtEmitter<Vec, Vec, Vec> for Assembler<'_> {
10494    fn facgt(&mut self, rd: Vec, rn: Vec, rm: Vec) {
10495        self.emit_n(
10496            InstId::Facgt_v,
10497            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
10498        );
10499    }
10500}
10501
10502impl FaddEmitter<Vec, Vec, Vec> for Assembler<'_> {
10503    fn fadd(&mut self, rd: Vec, rn: Vec, rm: Vec) {
10504        self.emit_n(
10505            InstId::Fadd_v,
10506            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
10507        );
10508    }
10509}
10510
10511impl FaddpEmitter<Vec, Vec> for Assembler<'_> {
10512    fn faddp(&mut self, rd: Vec, rn: Vec) {
10513        self.emit_n(InstId::Faddp_v, &[rd.as_operand(), rn.as_operand()]);
10514    }
10515}
10516
10517impl Faddp3Emitter<Vec, Vec, Vec> for Assembler<'_> {
10518    fn faddp_3(&mut self, rd: Vec, rn: Vec, rm: Vec) {
10519        self.emit_n(
10520            InstId::Faddp_v,
10521            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
10522        );
10523    }
10524}
10525
10526impl FccmpEmitter<Vec, Vec, Imm, Imm> for Assembler<'_> {
10527    fn fccmp(&mut self, rn: Vec, rm: Vec, flags: Imm, condition: Imm) {
10528        self.emit_n(
10529            InstId::Fccmp_v,
10530            &[
10531                rn.as_operand(),
10532                rm.as_operand(),
10533                flags.as_operand(),
10534                condition.as_operand(),
10535            ],
10536        );
10537    }
10538}
10539
10540impl FccmpeEmitter<Vec, Vec, Imm, Imm> for Assembler<'_> {
10541    fn fccmpe(&mut self, rn: Vec, rm: Vec, flags: Imm, condition: Imm) {
10542        self.emit_n(
10543            InstId::Fccmpe_v,
10544            &[
10545                rn.as_operand(),
10546                rm.as_operand(),
10547                flags.as_operand(),
10548                condition.as_operand(),
10549            ],
10550        );
10551    }
10552}
10553
10554impl FcmeqEmitter<Vec, Vec, Vec> for Assembler<'_> {
10555    fn fcmeq(&mut self, rd: Vec, rn: Vec, rm_or_operand_3: Vec) {
10556        self.emit_n(
10557            InstId::Fcmeq_v,
10558            &[
10559                rd.as_operand(),
10560                rn.as_operand(),
10561                rm_or_operand_3.as_operand(),
10562            ],
10563        );
10564    }
10565}
10566
10567impl FcmeqEmitter<Vec, Vec, Imm> for Assembler<'_> {
10568    fn fcmeq(&mut self, rd: Vec, rn: Vec, rm_or_operand_3: Imm) {
10569        self.emit_n(
10570            InstId::Fcmeq_v,
10571            &[
10572                rd.as_operand(),
10573                rn.as_operand(),
10574                rm_or_operand_3.as_operand(),
10575            ],
10576        );
10577    }
10578}
10579
10580impl FcmgeEmitter<Vec, Vec, Vec> for Assembler<'_> {
10581    fn fcmge(&mut self, rd: Vec, rn: Vec, rm_or_operand_3: Vec) {
10582        self.emit_n(
10583            InstId::Fcmge_v,
10584            &[
10585                rd.as_operand(),
10586                rn.as_operand(),
10587                rm_or_operand_3.as_operand(),
10588            ],
10589        );
10590    }
10591}
10592
10593impl FcmgeEmitter<Vec, Vec, Imm> for Assembler<'_> {
10594    fn fcmge(&mut self, rd: Vec, rn: Vec, rm_or_operand_3: Imm) {
10595        self.emit_n(
10596            InstId::Fcmge_v,
10597            &[
10598                rd.as_operand(),
10599                rn.as_operand(),
10600                rm_or_operand_3.as_operand(),
10601            ],
10602        );
10603    }
10604}
10605
10606impl FcmgtEmitter<Vec, Vec, Vec> for Assembler<'_> {
10607    fn fcmgt(&mut self, rd: Vec, rn: Vec, rm_or_operand_3: Vec) {
10608        self.emit_n(
10609            InstId::Fcmgt_v,
10610            &[
10611                rd.as_operand(),
10612                rn.as_operand(),
10613                rm_or_operand_3.as_operand(),
10614            ],
10615        );
10616    }
10617}
10618
10619impl FcmgtEmitter<Vec, Vec, Imm> for Assembler<'_> {
10620    fn fcmgt(&mut self, rd: Vec, rn: Vec, rm_or_operand_3: Imm) {
10621        self.emit_n(
10622            InstId::Fcmgt_v,
10623            &[
10624                rd.as_operand(),
10625                rn.as_operand(),
10626                rm_or_operand_3.as_operand(),
10627            ],
10628        );
10629    }
10630}
10631
10632impl FcmleEmitter<Vec, Vec, Imm> for Assembler<'_> {
10633    fn fcmle(&mut self, rd: Vec, rn: Vec, operand_3: Imm) {
10634        self.emit_n(
10635            InstId::Fcmle_v,
10636            &[rd.as_operand(), rn.as_operand(), operand_3.as_operand()],
10637        );
10638    }
10639}
10640
10641impl FcmltEmitter<Vec, Vec, Imm> for Assembler<'_> {
10642    fn fcmlt(&mut self, rd: Vec, rn: Vec, operand_3: Imm) {
10643        self.emit_n(
10644            InstId::Fcmlt_v,
10645            &[rd.as_operand(), rn.as_operand(), operand_3.as_operand()],
10646        );
10647    }
10648}
10649
10650impl FcmpEmitter<Vec, Vec> for Assembler<'_> {
10651    fn fcmp(&mut self, rn: Vec, rm_or_operand_2: Vec) {
10652        self.emit_n(
10653            InstId::Fcmp_v,
10654            &[rn.as_operand(), rm_or_operand_2.as_operand()],
10655        );
10656    }
10657}
10658
10659impl FcmpEmitter<Vec, Imm> for Assembler<'_> {
10660    fn fcmp(&mut self, rn: Vec, rm_or_operand_2: Imm) {
10661        self.emit_n(
10662            InstId::Fcmp_v,
10663            &[rn.as_operand(), rm_or_operand_2.as_operand()],
10664        );
10665    }
10666}
10667
10668impl FcmpeEmitter<Vec, Vec> for Assembler<'_> {
10669    fn fcmpe(&mut self, rn: Vec, rm_or_operand_2: Vec) {
10670        self.emit_n(
10671            InstId::Fcmpe_v,
10672            &[rn.as_operand(), rm_or_operand_2.as_operand()],
10673        );
10674    }
10675}
10676
10677impl FcmpeEmitter<Vec, Imm> for Assembler<'_> {
10678    fn fcmpe(&mut self, rn: Vec, rm_or_operand_2: Imm) {
10679        self.emit_n(
10680            InstId::Fcmpe_v,
10681            &[rn.as_operand(), rm_or_operand_2.as_operand()],
10682        );
10683    }
10684}
10685
10686impl FcselEmitter<Vec, Vec, Vec, Imm> for Assembler<'_> {
10687    fn fcsel(&mut self, rd: Vec, rn: Vec, rm: Vec, condition: Imm) {
10688        self.emit_n(
10689            InstId::Fcsel_v,
10690            &[
10691                rd.as_operand(),
10692                rn.as_operand(),
10693                rm.as_operand(),
10694                condition.as_operand(),
10695            ],
10696        );
10697    }
10698}
10699
10700impl FcvtEmitter<Vec, Vec> for Assembler<'_> {
10701    fn fcvt(&mut self, rd: Vec, rn: Vec) {
10702        self.emit_n(InstId::Fcvt_v, &[rd.as_operand(), rn.as_operand()]);
10703    }
10704}
10705
10706impl FcvtasEmitter<Gp, Vec> for Assembler<'_> {
10707    fn fcvtas(&mut self, rd: Gp, rn: Vec) {
10708        self.emit_n(InstId::Fcvtas_v, &[rd.as_operand(), rn.as_operand()]);
10709    }
10710}
10711
10712impl FcvtasEmitter<Vec, Vec> for Assembler<'_> {
10713    fn fcvtas(&mut self, rd: Vec, rn: Vec) {
10714        self.emit_n(InstId::Fcvtas_v, &[rd.as_operand(), rn.as_operand()]);
10715    }
10716}
10717
10718impl FcvtauEmitter<Gp, Vec> for Assembler<'_> {
10719    fn fcvtau(&mut self, rd: Gp, rn: Vec) {
10720        self.emit_n(InstId::Fcvtau_v, &[rd.as_operand(), rn.as_operand()]);
10721    }
10722}
10723
10724impl FcvtauEmitter<Vec, Vec> for Assembler<'_> {
10725    fn fcvtau(&mut self, rd: Vec, rn: Vec) {
10726        self.emit_n(InstId::Fcvtau_v, &[rd.as_operand(), rn.as_operand()]);
10727    }
10728}
10729
10730impl FcvtlEmitter<Vec, Vec> for Assembler<'_> {
10731    fn fcvtl(&mut self, rd: Vec, rn: Vec) {
10732        self.emit_n(InstId::Fcvtl_v, &[rd.as_operand(), rn.as_operand()]);
10733    }
10734}
10735
10736impl Fcvtl2Emitter<Vec, Vec> for Assembler<'_> {
10737    fn fcvtl2(&mut self, rd: Vec, rn: Vec) {
10738        self.emit_n(InstId::Fcvtl2_v, &[rd.as_operand(), rn.as_operand()]);
10739    }
10740}
10741
10742impl FcvtmsEmitter<Gp, Vec> for Assembler<'_> {
10743    fn fcvtms(&mut self, rd: Gp, rn: Vec) {
10744        self.emit_n(InstId::Fcvtms_v, &[rd.as_operand(), rn.as_operand()]);
10745    }
10746}
10747
10748impl FcvtmsEmitter<Vec, Vec> for Assembler<'_> {
10749    fn fcvtms(&mut self, rd: Vec, rn: Vec) {
10750        self.emit_n(InstId::Fcvtms_v, &[rd.as_operand(), rn.as_operand()]);
10751    }
10752}
10753
10754impl FcvtmuEmitter<Gp, Vec> for Assembler<'_> {
10755    fn fcvtmu(&mut self, rd: Gp, rn: Vec) {
10756        self.emit_n(InstId::Fcvtmu_v, &[rd.as_operand(), rn.as_operand()]);
10757    }
10758}
10759
10760impl FcvtmuEmitter<Vec, Vec> for Assembler<'_> {
10761    fn fcvtmu(&mut self, rd: Vec, rn: Vec) {
10762        self.emit_n(InstId::Fcvtmu_v, &[rd.as_operand(), rn.as_operand()]);
10763    }
10764}
10765
10766impl FcvtnEmitter<Vec, Vec> for Assembler<'_> {
10767    fn fcvtn(&mut self, rd: Vec, rn: Vec) {
10768        self.emit_n(InstId::Fcvtn_v, &[rd.as_operand(), rn.as_operand()]);
10769    }
10770}
10771
10772impl Fcvtn2Emitter<Vec, Vec> for Assembler<'_> {
10773    fn fcvtn2(&mut self, rd_or_operand_1: Vec, rn: Vec) {
10774        self.emit_n(
10775            InstId::Fcvtn2_v,
10776            &[rd_or_operand_1.as_operand(), rn.as_operand()],
10777        );
10778    }
10779}
10780
10781impl FcvtnsEmitter<Gp, Vec> for Assembler<'_> {
10782    fn fcvtns(&mut self, rd: Gp, rn: Vec) {
10783        self.emit_n(InstId::Fcvtns_v, &[rd.as_operand(), rn.as_operand()]);
10784    }
10785}
10786
10787impl FcvtnsEmitter<Vec, Vec> for Assembler<'_> {
10788    fn fcvtns(&mut self, rd: Vec, rn: Vec) {
10789        self.emit_n(InstId::Fcvtns_v, &[rd.as_operand(), rn.as_operand()]);
10790    }
10791}
10792
10793impl FcvtnuEmitter<Gp, Vec> for Assembler<'_> {
10794    fn fcvtnu(&mut self, rd: Gp, rn: Vec) {
10795        self.emit_n(InstId::Fcvtnu_v, &[rd.as_operand(), rn.as_operand()]);
10796    }
10797}
10798
10799impl FcvtnuEmitter<Vec, Vec> for Assembler<'_> {
10800    fn fcvtnu(&mut self, rd: Vec, rn: Vec) {
10801        self.emit_n(InstId::Fcvtnu_v, &[rd.as_operand(), rn.as_operand()]);
10802    }
10803}
10804
10805impl FcvtpsEmitter<Gp, Vec> for Assembler<'_> {
10806    fn fcvtps(&mut self, rd: Gp, rn: Vec) {
10807        self.emit_n(InstId::Fcvtps_v, &[rd.as_operand(), rn.as_operand()]);
10808    }
10809}
10810
10811impl FcvtpsEmitter<Vec, Vec> for Assembler<'_> {
10812    fn fcvtps(&mut self, rd: Vec, rn: Vec) {
10813        self.emit_n(InstId::Fcvtps_v, &[rd.as_operand(), rn.as_operand()]);
10814    }
10815}
10816
10817impl FcvtpuEmitter<Gp, Vec> for Assembler<'_> {
10818    fn fcvtpu(&mut self, rd: Gp, rn: Vec) {
10819        self.emit_n(InstId::Fcvtpu_v, &[rd.as_operand(), rn.as_operand()]);
10820    }
10821}
10822
10823impl FcvtpuEmitter<Vec, Vec> for Assembler<'_> {
10824    fn fcvtpu(&mut self, rd: Vec, rn: Vec) {
10825        self.emit_n(InstId::Fcvtpu_v, &[rd.as_operand(), rn.as_operand()]);
10826    }
10827}
10828
10829impl FcvtxnEmitter<Vec, Vec> for Assembler<'_> {
10830    fn fcvtxn(&mut self, rd: Vec, rn: Vec) {
10831        self.emit_n(InstId::Fcvtxn_v, &[rd.as_operand(), rn.as_operand()]);
10832    }
10833}
10834
10835impl Fcvtxn2Emitter<Vec, Vec> for Assembler<'_> {
10836    fn fcvtxn2(&mut self, rd: Vec, rn: Vec) {
10837        self.emit_n(InstId::Fcvtxn2_v, &[rd.as_operand(), rn.as_operand()]);
10838    }
10839}
10840
10841impl FcvtzsEmitter<Gp, Vec> for Assembler<'_> {
10842    fn fcvtzs(&mut self, rd: Gp, rn: Vec) {
10843        self.emit_n(InstId::Fcvtzs_v, &[rd.as_operand(), rn.as_operand()]);
10844    }
10845}
10846
10847impl FcvtzsEmitter<Vec, Vec> for Assembler<'_> {
10848    fn fcvtzs(&mut self, rd: Vec, rn: Vec) {
10849        self.emit_n(InstId::Fcvtzs_v, &[rd.as_operand(), rn.as_operand()]);
10850    }
10851}
10852
10853impl Fcvtzs3Emitter<Gp, Vec, Imm> for Assembler<'_> {
10854    fn fcvtzs_3(&mut self, rd: Gp, rn: Vec, fbits: Imm) {
10855        self.emit_n(
10856            InstId::Fcvtzs_v,
10857            &[rd.as_operand(), rn.as_operand(), fbits.as_operand()],
10858        );
10859    }
10860}
10861
10862impl Fcvtzs3Emitter<Vec, Vec, Imm> for Assembler<'_> {
10863    fn fcvtzs_3(&mut self, rd: Vec, rn: Vec, fbits: Imm) {
10864        self.emit_n(
10865            InstId::Fcvtzs_v,
10866            &[rd.as_operand(), rn.as_operand(), fbits.as_operand()],
10867        );
10868    }
10869}
10870
10871impl FcvtzuEmitter<Gp, Vec> for Assembler<'_> {
10872    fn fcvtzu(&mut self, rd: Gp, rn: Vec) {
10873        self.emit_n(InstId::Fcvtzu_v, &[rd.as_operand(), rn.as_operand()]);
10874    }
10875}
10876
10877impl FcvtzuEmitter<Vec, Vec> for Assembler<'_> {
10878    fn fcvtzu(&mut self, rd: Vec, rn: Vec) {
10879        self.emit_n(InstId::Fcvtzu_v, &[rd.as_operand(), rn.as_operand()]);
10880    }
10881}
10882
10883impl Fcvtzu3Emitter<Gp, Vec, Imm> for Assembler<'_> {
10884    fn fcvtzu_3(&mut self, rd: Gp, rn: Vec, fbits: Imm) {
10885        self.emit_n(
10886            InstId::Fcvtzu_v,
10887            &[rd.as_operand(), rn.as_operand(), fbits.as_operand()],
10888        );
10889    }
10890}
10891
10892impl Fcvtzu3Emitter<Vec, Vec, Imm> for Assembler<'_> {
10893    fn fcvtzu_3(&mut self, rd: Vec, rn: Vec, fbits: Imm) {
10894        self.emit_n(
10895            InstId::Fcvtzu_v,
10896            &[rd.as_operand(), rn.as_operand(), fbits.as_operand()],
10897        );
10898    }
10899}
10900
10901impl FdivEmitter<Vec, Vec, Vec> for Assembler<'_> {
10902    fn fdiv(&mut self, rd: Vec, rn: Vec, rm: Vec) {
10903        self.emit_n(
10904            InstId::Fdiv_v,
10905            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
10906        );
10907    }
10908}
10909
10910impl FmaddEmitter<Vec, Vec, Vec, Vec> for Assembler<'_> {
10911    fn fmadd(&mut self, rd: Vec, rn: Vec, rm: Vec, operand_4: Vec) {
10912        self.emit_n(
10913            InstId::Fmadd_v,
10914            &[
10915                rd.as_operand(),
10916                rn.as_operand(),
10917                rm.as_operand(),
10918                operand_4.as_operand(),
10919            ],
10920        );
10921    }
10922}
10923
10924impl FmaxEmitter<Vec, Vec, Vec> for Assembler<'_> {
10925    fn fmax(&mut self, rd: Vec, rn: Vec, rm: Vec) {
10926        self.emit_n(
10927            InstId::Fmax_v,
10928            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
10929        );
10930    }
10931}
10932
10933impl FmaxnmEmitter<Vec, Vec, Vec> for Assembler<'_> {
10934    fn fmaxnm(&mut self, rd: Vec, rn: Vec, rm: Vec) {
10935        self.emit_n(
10936            InstId::Fmaxnm_v,
10937            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
10938        );
10939    }
10940}
10941
10942impl FmaxnmpEmitter<Vec, Vec, Vec> for Assembler<'_> {
10943    fn fmaxnmp(&mut self, rd: Vec, rn: Vec, rm: Vec) {
10944        self.emit_n(
10945            InstId::Fmaxnmp_v,
10946            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
10947        );
10948    }
10949}
10950
10951impl Fmaxnmp2Emitter<Vec, Vec> for Assembler<'_> {
10952    fn fmaxnmp_2(&mut self, rd: Vec, rn: Vec) {
10953        self.emit_n(InstId::Fmaxnmp_v, &[rd.as_operand(), rn.as_operand()]);
10954    }
10955}
10956
10957impl FmaxnmvEmitter<Vec, Vec> for Assembler<'_> {
10958    fn fmaxnmv(&mut self, rd: Vec, rn: Vec) {
10959        self.emit_n(InstId::Fmaxnmv_v, &[rd.as_operand(), rn.as_operand()]);
10960    }
10961}
10962
10963impl FmaxpEmitter<Vec, Vec, Vec> for Assembler<'_> {
10964    fn fmaxp(&mut self, rd: Vec, rn: Vec, rm: Vec) {
10965        self.emit_n(
10966            InstId::Fmaxp_v,
10967            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
10968        );
10969    }
10970}
10971
10972impl Fmaxp2Emitter<Vec, Vec> for Assembler<'_> {
10973    fn fmaxp_2(&mut self, rd: Vec, rn: Vec) {
10974        self.emit_n(InstId::Fmaxp_v, &[rd.as_operand(), rn.as_operand()]);
10975    }
10976}
10977
10978impl FmaxvEmitter<Vec, Vec> for Assembler<'_> {
10979    fn fmaxv(&mut self, rd: Vec, rn: Vec) {
10980        self.emit_n(InstId::Fmaxv_v, &[rd.as_operand(), rn.as_operand()]);
10981    }
10982}
10983
10984impl FminEmitter<Vec, Vec, Vec> for Assembler<'_> {
10985    fn fmin(&mut self, rd: Vec, rn: Vec, rm: Vec) {
10986        self.emit_n(
10987            InstId::Fmin_v,
10988            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
10989        );
10990    }
10991}
10992
10993impl FminnmEmitter<Vec, Vec, Vec> for Assembler<'_> {
10994    fn fminnm(&mut self, rd: Vec, rn: Vec, rm: Vec) {
10995        self.emit_n(
10996            InstId::Fminnm_v,
10997            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
10998        );
10999    }
11000}
11001
11002impl FminnmvEmitter<Vec, Vec> for Assembler<'_> {
11003    fn fminnmv(&mut self, rd: Vec, rn: Vec) {
11004        self.emit_n(InstId::Fminnmv_v, &[rd.as_operand(), rn.as_operand()]);
11005    }
11006}
11007
11008impl FminnmpEmitter<Vec, Vec, Vec> for Assembler<'_> {
11009    fn fminnmp(&mut self, rd: Vec, rn: Vec, rm: Vec) {
11010        self.emit_n(
11011            InstId::Fminnmp_v,
11012            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
11013        );
11014    }
11015}
11016
11017impl Fminnmp2Emitter<Vec, Vec> for Assembler<'_> {
11018    fn fminnmp_2(&mut self, rd: Vec, rn: Vec) {
11019        self.emit_n(InstId::Fminnmp_v, &[rd.as_operand(), rn.as_operand()]);
11020    }
11021}
11022
11023impl FminpEmitter<Vec, Vec> for Assembler<'_> {
11024    fn fminp(&mut self, rd: Vec, rn: Vec) {
11025        self.emit_n(InstId::Fminp_v, &[rd.as_operand(), rn.as_operand()]);
11026    }
11027}
11028
11029impl Fminp3Emitter<Vec, Vec, Vec> for Assembler<'_> {
11030    fn fminp_3(&mut self, rd: Vec, rn: Vec, rm: Vec) {
11031        self.emit_n(
11032            InstId::Fminp_v,
11033            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
11034        );
11035    }
11036}
11037
11038impl FminvEmitter<Vec, Vec> for Assembler<'_> {
11039    fn fminv(&mut self, rd: Vec, rn: Vec) {
11040        self.emit_n(InstId::Fminv_v, &[rd.as_operand(), rn.as_operand()]);
11041    }
11042}
11043
11044impl FmlaEmitter<Vec, Vec, Vec> for Assembler<'_> {
11045    fn fmla(&mut self, operand_1: Vec, rn: Vec, rm: Vec) {
11046        self.emit_n(
11047            InstId::Fmla_v,
11048            &[operand_1.as_operand(), rn.as_operand(), rm.as_operand()],
11049        );
11050    }
11051}
11052
11053impl FmlsEmitter<Vec, Vec, Vec> for Assembler<'_> {
11054    fn fmls(&mut self, operand_1: Vec, rn: Vec, rm: Vec) {
11055        self.emit_n(
11056            InstId::Fmls_v,
11057            &[operand_1.as_operand(), rn.as_operand(), rm.as_operand()],
11058        );
11059    }
11060}
11061
11062impl FmovEmitter<Gp, Vec> for Assembler<'_> {
11063    fn fmov(&mut self, rd: Gp, rn_or_fimm: Vec) {
11064        self.emit_n(InstId::Fmov_v, &[rd.as_operand(), rn_or_fimm.as_operand()]);
11065    }
11066}
11067
11068impl FmovEmitter<Vec, Gp> for Assembler<'_> {
11069    fn fmov(&mut self, rd: Vec, rn_or_fimm: Gp) {
11070        self.emit_n(InstId::Fmov_v, &[rd.as_operand(), rn_or_fimm.as_operand()]);
11071    }
11072}
11073
11074impl FmovEmitter<Vec, Vec> for Assembler<'_> {
11075    fn fmov(&mut self, rd: Vec, rn_or_fimm: Vec) {
11076        self.emit_n(InstId::Fmov_v, &[rd.as_operand(), rn_or_fimm.as_operand()]);
11077    }
11078}
11079
11080impl FmovEmitter<Vec, Imm> for Assembler<'_> {
11081    fn fmov(&mut self, rd: Vec, rn_or_fimm: Imm) {
11082        self.emit_n(InstId::Fmov_v, &[rd.as_operand(), rn_or_fimm.as_operand()]);
11083    }
11084}
11085
11086impl FmsubEmitter<Vec, Vec, Vec, Vec> for Assembler<'_> {
11087    fn fmsub(&mut self, rd: Vec, rn: Vec, rm: Vec, operand_4: Vec) {
11088        self.emit_n(
11089            InstId::Fmsub_v,
11090            &[
11091                rd.as_operand(),
11092                rn.as_operand(),
11093                rm.as_operand(),
11094                operand_4.as_operand(),
11095            ],
11096        );
11097    }
11098}
11099
11100impl FmulEmitter<Vec, Vec, Vec> for Assembler<'_> {
11101    fn fmul(&mut self, rd: Vec, rn: Vec, rm: Vec) {
11102        self.emit_n(
11103            InstId::Fmul_v,
11104            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
11105        );
11106    }
11107}
11108
11109impl FmulxEmitter<Vec, Vec, Vec> for Assembler<'_> {
11110    fn fmulx(&mut self, rd: Vec, rn: Vec, rm: Vec) {
11111        self.emit_n(
11112            InstId::Fmulx_v,
11113            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
11114        );
11115    }
11116}
11117
11118impl FnegEmitter<Vec, Vec> for Assembler<'_> {
11119    fn fneg(&mut self, rd: Vec, rn: Vec) {
11120        self.emit_n(InstId::Fneg_v, &[rd.as_operand(), rn.as_operand()]);
11121    }
11122}
11123
11124impl FnmaddEmitter<Vec, Vec, Vec, Vec> for Assembler<'_> {
11125    fn fnmadd(&mut self, rd: Vec, rn: Vec, rm: Vec, operand_4: Vec) {
11126        self.emit_n(
11127            InstId::Fnmadd_v,
11128            &[
11129                rd.as_operand(),
11130                rn.as_operand(),
11131                rm.as_operand(),
11132                operand_4.as_operand(),
11133            ],
11134        );
11135    }
11136}
11137
11138impl FnmsubEmitter<Vec, Vec, Vec, Vec> for Assembler<'_> {
11139    fn fnmsub(&mut self, rd: Vec, rn: Vec, rm: Vec, operand_4: Vec) {
11140        self.emit_n(
11141            InstId::Fnmsub_v,
11142            &[
11143                rd.as_operand(),
11144                rn.as_operand(),
11145                rm.as_operand(),
11146                operand_4.as_operand(),
11147            ],
11148        );
11149    }
11150}
11151
11152impl FnmulEmitter<Vec, Vec, Vec> for Assembler<'_> {
11153    fn fnmul(&mut self, rd: Vec, rn: Vec, rm: Vec) {
11154        self.emit_n(
11155            InstId::Fnmul_v,
11156            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
11157        );
11158    }
11159}
11160
11161impl FrecpeEmitter<Vec, Vec> for Assembler<'_> {
11162    fn frecpe(&mut self, rd: Vec, rn: Vec) {
11163        self.emit_n(InstId::Frecpe_v, &[rd.as_operand(), rn.as_operand()]);
11164    }
11165}
11166
11167impl FrecpsEmitter<Vec, Vec, Vec> for Assembler<'_> {
11168    fn frecps(&mut self, rd: Vec, rn: Vec, rm: Vec) {
11169        self.emit_n(
11170            InstId::Frecps_v,
11171            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
11172        );
11173    }
11174}
11175
11176impl FrecpxEmitter<Vec, Vec> for Assembler<'_> {
11177    fn frecpx(&mut self, rd: Vec, rn: Vec) {
11178        self.emit_n(InstId::Frecpx_v, &[rd.as_operand(), rn.as_operand()]);
11179    }
11180}
11181
11182impl Frint32xEmitter<Vec, Vec> for Assembler<'_> {
11183    fn frint32x(&mut self, rd: Vec, rn: Vec) {
11184        self.emit_n(InstId::Frint32x_v, &[rd.as_operand(), rn.as_operand()]);
11185    }
11186}
11187
11188impl Frint32zEmitter<Vec, Vec> for Assembler<'_> {
11189    fn frint32z(&mut self, rd: Vec, rn: Vec) {
11190        self.emit_n(InstId::Frint32z_v, &[rd.as_operand(), rn.as_operand()]);
11191    }
11192}
11193
11194impl Frint64xEmitter<Vec, Vec> for Assembler<'_> {
11195    fn frint64x(&mut self, rd: Vec, rn: Vec) {
11196        self.emit_n(InstId::Frint64x_v, &[rd.as_operand(), rn.as_operand()]);
11197    }
11198}
11199
11200impl Frint64zEmitter<Vec, Vec> for Assembler<'_> {
11201    fn frint64z(&mut self, rd: Vec, rn: Vec) {
11202        self.emit_n(InstId::Frint64z_v, &[rd.as_operand(), rn.as_operand()]);
11203    }
11204}
11205
11206impl FrintaEmitter<Vec, Vec> for Assembler<'_> {
11207    fn frinta(&mut self, rd: Vec, rn: Vec) {
11208        self.emit_n(InstId::Frinta_v, &[rd.as_operand(), rn.as_operand()]);
11209    }
11210}
11211
11212impl FrintiEmitter<Vec, Vec> for Assembler<'_> {
11213    fn frinti(&mut self, rd: Vec, rn: Vec) {
11214        self.emit_n(InstId::Frinti_v, &[rd.as_operand(), rn.as_operand()]);
11215    }
11216}
11217
11218impl FrintmEmitter<Vec, Vec> for Assembler<'_> {
11219    fn frintm(&mut self, rd: Vec, rn: Vec) {
11220        self.emit_n(InstId::Frintm_v, &[rd.as_operand(), rn.as_operand()]);
11221    }
11222}
11223
11224impl FrintnEmitter<Vec, Vec> for Assembler<'_> {
11225    fn frintn(&mut self, rd: Vec, rn: Vec) {
11226        self.emit_n(InstId::Frintn_v, &[rd.as_operand(), rn.as_operand()]);
11227    }
11228}
11229
11230impl FrintpEmitter<Vec, Vec> for Assembler<'_> {
11231    fn frintp(&mut self, rd: Vec, rn: Vec) {
11232        self.emit_n(InstId::Frintp_v, &[rd.as_operand(), rn.as_operand()]);
11233    }
11234}
11235
11236impl FrintxEmitter<Vec, Vec> for Assembler<'_> {
11237    fn frintx(&mut self, rd: Vec, rn: Vec) {
11238        self.emit_n(InstId::Frintx_v, &[rd.as_operand(), rn.as_operand()]);
11239    }
11240}
11241
11242impl FrintzEmitter<Vec, Vec> for Assembler<'_> {
11243    fn frintz(&mut self, rd: Vec, rn: Vec) {
11244        self.emit_n(InstId::Frintz_v, &[rd.as_operand(), rn.as_operand()]);
11245    }
11246}
11247
11248impl FrsqrteEmitter<Vec, Vec> for Assembler<'_> {
11249    fn frsqrte(&mut self, rd: Vec, rn: Vec) {
11250        self.emit_n(InstId::Frsqrte_v, &[rd.as_operand(), rn.as_operand()]);
11251    }
11252}
11253
11254impl FrsqrtsEmitter<Vec, Vec, Vec> for Assembler<'_> {
11255    fn frsqrts(&mut self, rd: Vec, rn: Vec, rm: Vec) {
11256        self.emit_n(
11257            InstId::Frsqrts_v,
11258            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
11259        );
11260    }
11261}
11262
11263impl FsqrtEmitter<Vec, Vec> for Assembler<'_> {
11264    fn fsqrt(&mut self, rd: Vec, rn: Vec) {
11265        self.emit_n(InstId::Fsqrt_v, &[rd.as_operand(), rn.as_operand()]);
11266    }
11267}
11268
11269impl FsubEmitter<Vec, Vec, Vec> for Assembler<'_> {
11270    fn fsub(&mut self, rd: Vec, rn: Vec, rm: Vec) {
11271        self.emit_n(
11272            InstId::Fsub_v,
11273            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
11274        );
11275    }
11276}
11277
11278impl InsEmitter<Vec, Gp> for Assembler<'_> {
11279    fn ins(&mut self, rd: Vec, rn: Gp) {
11280        self.emit_n(InstId::Ins_v, &[rd.as_operand(), rn.as_operand()]);
11281    }
11282}
11283
11284impl InsEmitter<Vec, Vec> for Assembler<'_> {
11285    fn ins(&mut self, rd: Vec, rn: Vec) {
11286        self.emit_n(InstId::Ins_v, &[rd.as_operand(), rn.as_operand()]);
11287    }
11288}
11289
11290impl Ld1Emitter<Vec, Mem> for Assembler<'_> {
11291    fn ld1(&mut self, idx_or_operand_1: Vec, addr: Mem) {
11292        self.emit_n(
11293            InstId::Ld1_v,
11294            &[idx_or_operand_1.as_operand(), addr.as_operand()],
11295        );
11296    }
11297}
11298
11299impl Ld13Emitter<Vec, Vec, Mem> for Assembler<'_> {
11300    fn ld1_3(&mut self, rd: Vec, rn: Vec, addr: Mem) {
11301        self.emit_n(
11302            InstId::Ld1_v,
11303            &[rd.as_operand(), rn.as_operand(), addr.as_operand()],
11304        );
11305    }
11306}
11307
11308impl Ld14Emitter<Vec, Vec, Vec, Mem> for Assembler<'_> {
11309    fn ld1_4(&mut self, rd: Vec, rn: Vec, rm1: Vec, addr: Mem) {
11310        self.emit_n(
11311            InstId::Ld1_v,
11312            &[
11313                rd.as_operand(),
11314                rn.as_operand(),
11315                rm1.as_operand(),
11316                addr.as_operand(),
11317            ],
11318        );
11319    }
11320}
11321
11322impl Ld15Emitter<Vec, Vec, Vec, Vec, Mem> for Assembler<'_> {
11323    fn ld1_5(&mut self, rd: Vec, rn: Vec, rm1: Vec, rm2: Vec, addr: Mem) {
11324        self.emit_n(
11325            InstId::Ld1_v,
11326            &[
11327                rd.as_operand(),
11328                rn.as_operand(),
11329                rm1.as_operand(),
11330                rm2.as_operand(),
11331                addr.as_operand(),
11332            ],
11333        );
11334    }
11335}
11336
11337impl Ld1rEmitter<Vec, Mem> for Assembler<'_> {
11338    fn ld1r(&mut self, operand_1: Vec, addr: Mem) {
11339        self.emit_n(InstId::Ld1r_v, &[operand_1.as_operand(), addr.as_operand()]);
11340    }
11341}
11342
11343impl Ld2Emitter<Vec, Vec, Mem> for Assembler<'_> {
11344    fn ld2(&mut self, rd: Vec, rn: Vec, addr: Mem) {
11345        self.emit_n(
11346            InstId::Ld2_v,
11347            &[rd.as_operand(), rn.as_operand(), addr.as_operand()],
11348        );
11349    }
11350}
11351
11352impl Ld2rEmitter<Vec, Vec, Mem> for Assembler<'_> {
11353    fn ld2r(&mut self, rd: Vec, rn: Vec, addr: Mem) {
11354        self.emit_n(
11355            InstId::Ld2r_v,
11356            &[rd.as_operand(), rn.as_operand(), addr.as_operand()],
11357        );
11358    }
11359}
11360
11361impl Ld3Emitter<Vec, Vec, Vec, Mem> for Assembler<'_> {
11362    fn ld3(&mut self, rd: Vec, rn: Vec, rm1: Vec, addr: Mem) {
11363        self.emit_n(
11364            InstId::Ld3_v,
11365            &[
11366                rd.as_operand(),
11367                rn.as_operand(),
11368                rm1.as_operand(),
11369                addr.as_operand(),
11370            ],
11371        );
11372    }
11373}
11374
11375impl Ld3rEmitter<Vec, Vec, Vec, Mem> for Assembler<'_> {
11376    fn ld3r(&mut self, rd: Vec, rn: Vec, rm1: Vec, addr: Mem) {
11377        self.emit_n(
11378            InstId::Ld3r_v,
11379            &[
11380                rd.as_operand(),
11381                rn.as_operand(),
11382                rm1.as_operand(),
11383                addr.as_operand(),
11384            ],
11385        );
11386    }
11387}
11388
11389impl Ld4Emitter<Vec, Vec, Vec, Vec, Mem> for Assembler<'_> {
11390    fn ld4(&mut self, rd: Vec, rn: Vec, rm1: Vec, rm2: Vec, addr: Mem) {
11391        self.emit_n(
11392            InstId::Ld4_v,
11393            &[
11394                rd.as_operand(),
11395                rn.as_operand(),
11396                rm1.as_operand(),
11397                rm2.as_operand(),
11398                addr.as_operand(),
11399            ],
11400        );
11401    }
11402}
11403
11404impl Ld4rEmitter<Vec, Vec, Vec, Vec, Mem> for Assembler<'_> {
11405    fn ld4r(&mut self, rd: Vec, rn: Vec, rm1: Vec, rm2: Vec, addr: Mem) {
11406        self.emit_n(
11407            InstId::Ld4r_v,
11408            &[
11409                rd.as_operand(),
11410                rn.as_operand(),
11411                rm1.as_operand(),
11412                rm2.as_operand(),
11413                addr.as_operand(),
11414            ],
11415        );
11416    }
11417}
11418
11419impl MlaEmitter<Vec, Vec, Vec> for Assembler<'_> {
11420    fn mla(&mut self, operand_1: Vec, rn: Vec, rm: Vec) {
11421        self.emit_n(
11422            InstId::Mla_v,
11423            &[operand_1.as_operand(), rn.as_operand(), rm.as_operand()],
11424        );
11425    }
11426}
11427
11428impl MlsEmitter<Vec, Vec, Vec> for Assembler<'_> {
11429    fn mls(&mut self, operand_1: Vec, rn: Vec, rm: Vec) {
11430        self.emit_n(
11431            InstId::Mls_v,
11432            &[operand_1.as_operand(), rn.as_operand(), rm.as_operand()],
11433        );
11434    }
11435}
11436
11437impl MoviEmitter<Vec, Imm> for Assembler<'_> {
11438    fn movi(&mut self, rd: Vec, imm: Imm) {
11439        self.emit_n(InstId::Movi_v, &[rd.as_operand(), imm.as_operand()]);
11440    }
11441}
11442
11443impl Movi3Emitter<Vec, Imm, Imm> for Assembler<'_> {
11444    fn movi_3(&mut self, rd: Vec, imm: Imm, shift: Imm) {
11445        self.emit_n(
11446            InstId::Movi_v,
11447            &[rd.as_operand(), imm.as_operand(), shift.as_operand()],
11448        );
11449    }
11450}
11451
11452impl MvniEmitter<Vec, Imm> for Assembler<'_> {
11453    fn mvni(&mut self, rd: Vec, imm: Imm) {
11454        self.emit_n(InstId::Mvni_v, &[rd.as_operand(), imm.as_operand()]);
11455    }
11456}
11457
11458impl Mvni3Emitter<Vec, Imm, Imm> for Assembler<'_> {
11459    fn mvni_3(&mut self, rd: Vec, imm: Imm, shift: Imm) {
11460        self.emit_n(
11461            InstId::Mvni_v,
11462            &[rd.as_operand(), imm.as_operand(), shift.as_operand()],
11463        );
11464    }
11465}
11466
11467impl NotEmitter<Vec, Vec> for Assembler<'_> {
11468    fn not_(&mut self, rd: Vec, rn: Vec) {
11469        self.emit_n(InstId::Not_v, &[rd.as_operand(), rn.as_operand()]);
11470    }
11471}
11472
11473impl Orr2Emitter<Vec, Imm> for Assembler<'_> {
11474    fn orr_2(&mut self, rd: Vec, rn_or_imm: Imm) {
11475        self.emit_n(InstId::Orr_v, &[rd.as_operand(), rn_or_imm.as_operand()]);
11476    }
11477}
11478
11479impl PmulEmitter<Vec, Vec, Vec> for Assembler<'_> {
11480    fn pmul(&mut self, rd: Vec, rn: Vec, rm: Vec) {
11481        self.emit_n(
11482            InstId::Pmul_v,
11483            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
11484        );
11485    }
11486}
11487
11488impl PmullEmitter<Vec, Vec, Vec> for Assembler<'_> {
11489    fn pmull(&mut self, rd: Vec, rn: Vec, rm: Vec) {
11490        self.emit_n(
11491            InstId::Pmull_v,
11492            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
11493        );
11494    }
11495}
11496
11497impl Pmull2Emitter<Vec, Vec, Vec> for Assembler<'_> {
11498    fn pmull2(&mut self, rd: Vec, rn: Vec, rm: Vec) {
11499        self.emit_n(
11500            InstId::Pmull2_v,
11501            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
11502        );
11503    }
11504}
11505
11506impl RaddhnEmitter<Vec, Vec, Vec> for Assembler<'_> {
11507    fn raddhn(&mut self, rd: Vec, rn: Vec, rm: Vec) {
11508        self.emit_n(
11509            InstId::Raddhn_v,
11510            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
11511        );
11512    }
11513}
11514
11515impl Raddhn2Emitter<Vec, Vec, Vec> for Assembler<'_> {
11516    fn raddhn2(&mut self, operand_1: Vec, rn: Vec, rm: Vec) {
11517        self.emit_n(
11518            InstId::Raddhn2_v,
11519            &[operand_1.as_operand(), rn.as_operand(), rm.as_operand()],
11520        );
11521    }
11522}
11523
11524impl RshrnEmitter<Vec, Vec, Imm> for Assembler<'_> {
11525    fn rshrn(&mut self, rd: Vec, rn: Vec, shift: Imm) {
11526        self.emit_n(
11527            InstId::Rshrn_v,
11528            &[rd.as_operand(), rn.as_operand(), shift.as_operand()],
11529        );
11530    }
11531}
11532
11533impl Rshrn2Emitter<Vec, Vec, Imm> for Assembler<'_> {
11534    fn rshrn2(&mut self, operand_1: Vec, rn: Vec, shift: Imm) {
11535        self.emit_n(
11536            InstId::Rshrn2_v,
11537            &[operand_1.as_operand(), rn.as_operand(), shift.as_operand()],
11538        );
11539    }
11540}
11541
11542impl RsubhnEmitter<Vec, Vec, Vec> for Assembler<'_> {
11543    fn rsubhn(&mut self, rd: Vec, rn: Vec, rm: Vec) {
11544        self.emit_n(
11545            InstId::Rsubhn_v,
11546            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
11547        );
11548    }
11549}
11550
11551impl Rsubhn2Emitter<Vec, Vec, Vec> for Assembler<'_> {
11552    fn rsubhn2(&mut self, operand_1: Vec, rn: Vec, rm: Vec) {
11553        self.emit_n(
11554            InstId::Rsubhn2_v,
11555            &[operand_1.as_operand(), rn.as_operand(), rm.as_operand()],
11556        );
11557    }
11558}
11559
11560impl SabaEmitter<Vec, Vec, Vec> for Assembler<'_> {
11561    fn saba(&mut self, operand_1: Vec, rn: Vec, rm: Vec) {
11562        self.emit_n(
11563            InstId::Saba_v,
11564            &[operand_1.as_operand(), rn.as_operand(), rm.as_operand()],
11565        );
11566    }
11567}
11568
11569impl SabalEmitter<Vec, Vec, Vec> for Assembler<'_> {
11570    fn sabal(&mut self, operand_1: Vec, rn: Vec, rm: Vec) {
11571        self.emit_n(
11572            InstId::Sabal_v,
11573            &[operand_1.as_operand(), rn.as_operand(), rm.as_operand()],
11574        );
11575    }
11576}
11577
11578impl Sabal2Emitter<Vec, Vec, Vec> for Assembler<'_> {
11579    fn sabal2(&mut self, operand_1: Vec, rn: Vec, rm: Vec) {
11580        self.emit_n(
11581            InstId::Sabal2_v,
11582            &[operand_1.as_operand(), rn.as_operand(), rm.as_operand()],
11583        );
11584    }
11585}
11586
11587impl SabdEmitter<Vec, Vec, Vec> for Assembler<'_> {
11588    fn sabd(&mut self, rd: Vec, rn: Vec, rm: Vec) {
11589        self.emit_n(
11590            InstId::Sabd_v,
11591            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
11592        );
11593    }
11594}
11595
11596impl SabdlEmitter<Vec, Vec, Vec> for Assembler<'_> {
11597    fn sabdl(&mut self, rd: Vec, rn: Vec, rm: Vec) {
11598        self.emit_n(
11599            InstId::Sabdl_v,
11600            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
11601        );
11602    }
11603}
11604
11605impl Sabdl2Emitter<Vec, Vec, Vec> for Assembler<'_> {
11606    fn sabdl2(&mut self, rd: Vec, rn: Vec, rm: Vec) {
11607        self.emit_n(
11608            InstId::Sabdl2_v,
11609            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
11610        );
11611    }
11612}
11613
11614impl SadalpEmitter<Vec, Vec> for Assembler<'_> {
11615    fn sadalp(&mut self, operand_1: Vec, rn: Vec) {
11616        self.emit_n(InstId::Sadalp_v, &[operand_1.as_operand(), rn.as_operand()]);
11617    }
11618}
11619
11620impl SaddlEmitter<Vec, Vec, Vec> for Assembler<'_> {
11621    fn saddl(&mut self, rd: Vec, rn: Vec, rm: Vec) {
11622        self.emit_n(
11623            InstId::Saddl_v,
11624            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
11625        );
11626    }
11627}
11628
11629impl Saddl2Emitter<Vec, Vec, Vec> for Assembler<'_> {
11630    fn saddl2(&mut self, rd: Vec, rn: Vec, rm: Vec) {
11631        self.emit_n(
11632            InstId::Saddl2_v,
11633            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
11634        );
11635    }
11636}
11637
11638impl SaddlpEmitter<Vec, Vec> for Assembler<'_> {
11639    fn saddlp(&mut self, rd: Vec, rn: Vec) {
11640        self.emit_n(InstId::Saddlp_v, &[rd.as_operand(), rn.as_operand()]);
11641    }
11642}
11643
11644impl SaddlvEmitter<Vec, Vec> for Assembler<'_> {
11645    fn saddlv(&mut self, rd: Vec, rn: Vec) {
11646        self.emit_n(InstId::Saddlv_v, &[rd.as_operand(), rn.as_operand()]);
11647    }
11648}
11649
11650impl SaddwEmitter<Vec, Vec, Vec> for Assembler<'_> {
11651    fn saddw(&mut self, rd: Vec, rn: Vec, rm: Vec) {
11652        self.emit_n(
11653            InstId::Saddw_v,
11654            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
11655        );
11656    }
11657}
11658
11659impl Saddw2Emitter<Vec, Vec, Vec> for Assembler<'_> {
11660    fn saddw2(&mut self, rd: Vec, rn: Vec, rm: Vec) {
11661        self.emit_n(
11662            InstId::Saddw2_v,
11663            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
11664        );
11665    }
11666}
11667
11668impl ScvtfEmitter<Vec, Gp> for Assembler<'_> {
11669    fn scvtf(&mut self, rd: Vec, rn: Gp) {
11670        self.emit_n(InstId::Scvtf_v, &[rd.as_operand(), rn.as_operand()]);
11671    }
11672}
11673
11674impl ScvtfEmitter<Vec, Vec> for Assembler<'_> {
11675    fn scvtf(&mut self, rd: Vec, rn: Vec) {
11676        self.emit_n(InstId::Scvtf_v, &[rd.as_operand(), rn.as_operand()]);
11677    }
11678}
11679
11680impl Scvtf3Emitter<Vec, Gp, Imm> for Assembler<'_> {
11681    fn scvtf_3(&mut self, rd: Vec, rn: Gp, fbits_or_bits: Imm) {
11682        self.emit_n(
11683            InstId::Scvtf_v,
11684            &[rd.as_operand(), rn.as_operand(), fbits_or_bits.as_operand()],
11685        );
11686    }
11687}
11688
11689impl Scvtf3Emitter<Vec, Vec, Imm> for Assembler<'_> {
11690    fn scvtf_3(&mut self, rd: Vec, rn: Vec, fbits_or_bits: Imm) {
11691        self.emit_n(
11692            InstId::Scvtf_v,
11693            &[rd.as_operand(), rn.as_operand(), fbits_or_bits.as_operand()],
11694        );
11695    }
11696}
11697
11698impl ShaddEmitter<Vec, Vec, Vec> for Assembler<'_> {
11699    fn shadd(&mut self, rd: Vec, rn: Vec, rm: Vec) {
11700        self.emit_n(
11701            InstId::Shadd_v,
11702            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
11703        );
11704    }
11705}
11706
11707impl ShlEmitter<Vec, Vec, Imm> for Assembler<'_> {
11708    fn shl(&mut self, rd: Vec, rn: Vec, shift: Imm) {
11709        self.emit_n(
11710            InstId::Shl_v,
11711            &[rd.as_operand(), rn.as_operand(), shift.as_operand()],
11712        );
11713    }
11714}
11715
11716impl ShllEmitter<Vec, Vec, Imm> for Assembler<'_> {
11717    fn shll(&mut self, rd: Vec, rn: Vec, operand_3: Imm) {
11718        self.emit_n(
11719            InstId::Shll_v,
11720            &[rd.as_operand(), rn.as_operand(), operand_3.as_operand()],
11721        );
11722    }
11723}
11724
11725impl Shll2Emitter<Vec, Vec, Imm> for Assembler<'_> {
11726    fn shll2(&mut self, rd: Vec, rn: Vec, operand_3: Imm) {
11727        self.emit_n(
11728            InstId::Shll2_v,
11729            &[rd.as_operand(), rn.as_operand(), operand_3.as_operand()],
11730        );
11731    }
11732}
11733
11734impl ShrnEmitter<Vec, Vec, Imm> for Assembler<'_> {
11735    fn shrn(&mut self, rd: Vec, rn: Vec, shift: Imm) {
11736        self.emit_n(
11737            InstId::Shrn_v,
11738            &[rd.as_operand(), rn.as_operand(), shift.as_operand()],
11739        );
11740    }
11741}
11742
11743impl Shrn2Emitter<Vec, Vec, Imm> for Assembler<'_> {
11744    fn shrn2(&mut self, operand_1: Vec, rn: Vec, shift: Imm) {
11745        self.emit_n(
11746            InstId::Shrn2_v,
11747            &[operand_1.as_operand(), rn.as_operand(), shift.as_operand()],
11748        );
11749    }
11750}
11751
11752impl ShsubEmitter<Vec, Vec, Vec> for Assembler<'_> {
11753    fn shsub(&mut self, rd: Vec, rn: Vec, rm: Vec) {
11754        self.emit_n(
11755            InstId::Shsub_v,
11756            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
11757        );
11758    }
11759}
11760
11761impl SliEmitter<Vec, Vec, Imm> for Assembler<'_> {
11762    fn sli(&mut self, operand_1: Vec, rn: Vec, shift: Imm) {
11763        self.emit_n(
11764            InstId::Sli_v,
11765            &[operand_1.as_operand(), rn.as_operand(), shift.as_operand()],
11766        );
11767    }
11768}
11769
11770impl SmaxpEmitter<Vec, Vec, Vec> for Assembler<'_> {
11771    fn smaxp(&mut self, rd: Vec, rn: Vec, rm: Vec) {
11772        self.emit_n(
11773            InstId::Smaxp_v,
11774            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
11775        );
11776    }
11777}
11778
11779impl SmaxvEmitter<Vec, Vec> for Assembler<'_> {
11780    fn smaxv(&mut self, rd: Vec, rn: Vec) {
11781        self.emit_n(InstId::Smaxv_v, &[rd.as_operand(), rn.as_operand()]);
11782    }
11783}
11784
11785impl SminpEmitter<Vec, Vec, Vec> for Assembler<'_> {
11786    fn sminp(&mut self, rd: Vec, rn: Vec, rm: Vec) {
11787        self.emit_n(
11788            InstId::Sminp_v,
11789            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
11790        );
11791    }
11792}
11793
11794impl SminvEmitter<Vec, Vec> for Assembler<'_> {
11795    fn sminv(&mut self, rd: Vec, rn: Vec) {
11796        self.emit_n(InstId::Sminv_v, &[rd.as_operand(), rn.as_operand()]);
11797    }
11798}
11799
11800impl SmlalEmitter<Vec, Vec, Vec> for Assembler<'_> {
11801    fn smlal(&mut self, operand_1: Vec, rn: Vec, rm: Vec) {
11802        self.emit_n(
11803            InstId::Smlal_v,
11804            &[operand_1.as_operand(), rn.as_operand(), rm.as_operand()],
11805        );
11806    }
11807}
11808
11809impl Smlal2Emitter<Vec, Vec, Vec> for Assembler<'_> {
11810    fn smlal2(&mut self, operand_1: Vec, rn: Vec, rm: Vec) {
11811        self.emit_n(
11812            InstId::Smlal2_v,
11813            &[operand_1.as_operand(), rn.as_operand(), rm.as_operand()],
11814        );
11815    }
11816}
11817
11818impl SmlslEmitter<Vec, Vec, Vec> for Assembler<'_> {
11819    fn smlsl(&mut self, operand_1: Vec, rn: Vec, rm: Vec) {
11820        self.emit_n(
11821            InstId::Smlsl_v,
11822            &[operand_1.as_operand(), rn.as_operand(), rm.as_operand()],
11823        );
11824    }
11825}
11826
11827impl Smlsl2Emitter<Vec, Vec, Vec> for Assembler<'_> {
11828    fn smlsl2(&mut self, operand_1: Vec, rn: Vec, rm: Vec) {
11829        self.emit_n(
11830            InstId::Smlsl2_v,
11831            &[operand_1.as_operand(), rn.as_operand(), rm.as_operand()],
11832        );
11833    }
11834}
11835
11836impl SmovEmitter<Gp, Vec> for Assembler<'_> {
11837    fn smov(&mut self, rd: Gp, rn: Vec) {
11838        self.emit_n(InstId::Smov_v, &[rd.as_operand(), rn.as_operand()]);
11839    }
11840}
11841
11842impl Smull2Emitter<Vec, Vec, Vec> for Assembler<'_> {
11843    fn smull2(&mut self, rd: Vec, rn: Vec, rm: Vec) {
11844        self.emit_n(
11845            InstId::Smull2_v,
11846            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
11847        );
11848    }
11849}
11850
11851impl SqabsEmitter<Vec, Vec> for Assembler<'_> {
11852    fn sqabs(&mut self, rd: Vec, rn: Vec) {
11853        self.emit_n(InstId::Sqabs_v, &[rd.as_operand(), rn.as_operand()]);
11854    }
11855}
11856
11857impl SqaddEmitter<Vec, Vec, Vec> for Assembler<'_> {
11858    fn sqadd(&mut self, rd: Vec, rn: Vec, rm: Vec) {
11859        self.emit_n(
11860            InstId::Sqadd_v,
11861            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
11862        );
11863    }
11864}
11865
11866impl SqdmlalEmitter<Vec, Vec, Vec> for Assembler<'_> {
11867    fn sqdmlal(&mut self, operand_1: Vec, rn: Vec, rm: Vec) {
11868        self.emit_n(
11869            InstId::Sqdmlal_v,
11870            &[operand_1.as_operand(), rn.as_operand(), rm.as_operand()],
11871        );
11872    }
11873}
11874
11875impl Sqdmlal2Emitter<Vec, Vec, Vec> for Assembler<'_> {
11876    fn sqdmlal2(&mut self, operand_1: Vec, rn: Vec, rm: Vec) {
11877        self.emit_n(
11878            InstId::Sqdmlal2_v,
11879            &[operand_1.as_operand(), rn.as_operand(), rm.as_operand()],
11880        );
11881    }
11882}
11883
11884impl SqdmlslEmitter<Vec, Vec, Vec> for Assembler<'_> {
11885    fn sqdmlsl(&mut self, operand_1: Vec, rn: Vec, rm: Vec) {
11886        self.emit_n(
11887            InstId::Sqdmlsl_v,
11888            &[operand_1.as_operand(), rn.as_operand(), rm.as_operand()],
11889        );
11890    }
11891}
11892
11893impl Sqdmlsl2Emitter<Vec, Vec, Vec> for Assembler<'_> {
11894    fn sqdmlsl2(&mut self, operand_1: Vec, rn: Vec, rm: Vec) {
11895        self.emit_n(
11896            InstId::Sqdmlsl2_v,
11897            &[operand_1.as_operand(), rn.as_operand(), rm.as_operand()],
11898        );
11899    }
11900}
11901
11902impl SqdmulhEmitter<Vec, Vec, Vec> for Assembler<'_> {
11903    fn sqdmulh(&mut self, rd: Vec, rn: Vec, rm: Vec) {
11904        self.emit_n(
11905            InstId::Sqdmulh_v,
11906            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
11907        );
11908    }
11909}
11910
11911impl SqdmullEmitter<Vec, Vec, Vec> for Assembler<'_> {
11912    fn sqdmull(&mut self, rd: Vec, rn: Vec, rm: Vec) {
11913        self.emit_n(
11914            InstId::Sqdmull_v,
11915            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
11916        );
11917    }
11918}
11919
11920impl Sqdmull2Emitter<Vec, Vec, Vec> for Assembler<'_> {
11921    fn sqdmull2(&mut self, rd: Vec, rn: Vec, rm: Vec) {
11922        self.emit_n(
11923            InstId::Sqdmull2_v,
11924            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
11925        );
11926    }
11927}
11928
11929impl SqnegEmitter<Vec, Vec> for Assembler<'_> {
11930    fn sqneg(&mut self, rd: Vec, rn: Vec) {
11931        self.emit_n(InstId::Sqneg_v, &[rd.as_operand(), rn.as_operand()]);
11932    }
11933}
11934
11935impl SqrdmulhEmitter<Vec, Vec, Vec> for Assembler<'_> {
11936    fn sqrdmulh(&mut self, rd: Vec, rn: Vec, rm: Vec) {
11937        self.emit_n(
11938            InstId::Sqrdmulh_v,
11939            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
11940        );
11941    }
11942}
11943
11944impl SqrshlEmitter<Vec, Vec, Vec> for Assembler<'_> {
11945    fn sqrshl(&mut self, rd: Vec, rn: Vec, rm: Vec) {
11946        self.emit_n(
11947            InstId::Sqrshl_v,
11948            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
11949        );
11950    }
11951}
11952
11953impl SqrshrnEmitter<Vec, Vec, Imm> for Assembler<'_> {
11954    fn sqrshrn(&mut self, rd: Vec, rn: Vec, shift: Imm) {
11955        self.emit_n(
11956            InstId::Sqrshrn_v,
11957            &[rd.as_operand(), rn.as_operand(), shift.as_operand()],
11958        );
11959    }
11960}
11961
11962impl Sqrshrn2Emitter<Vec, Vec, Imm> for Assembler<'_> {
11963    fn sqrshrn2(&mut self, operand_1: Vec, rn: Vec, shift: Imm) {
11964        self.emit_n(
11965            InstId::Sqrshrn2_v,
11966            &[operand_1.as_operand(), rn.as_operand(), shift.as_operand()],
11967        );
11968    }
11969}
11970
11971impl SqrshrunEmitter<Vec, Vec, Imm> for Assembler<'_> {
11972    fn sqrshrun(&mut self, rd: Vec, rn: Vec, shift: Imm) {
11973        self.emit_n(
11974            InstId::Sqrshrun_v,
11975            &[rd.as_operand(), rn.as_operand(), shift.as_operand()],
11976        );
11977    }
11978}
11979
11980impl Sqrshrun2Emitter<Vec, Vec, Imm> for Assembler<'_> {
11981    fn sqrshrun2(&mut self, operand_1: Vec, rn: Vec, shift: Imm) {
11982        self.emit_n(
11983            InstId::Sqrshrun2_v,
11984            &[operand_1.as_operand(), rn.as_operand(), shift.as_operand()],
11985        );
11986    }
11987}
11988
11989impl SqshlEmitter<Vec, Vec, Vec> for Assembler<'_> {
11990    fn sqshl(&mut self, rd: Vec, rn: Vec, rm_or_shift: Vec) {
11991        self.emit_n(
11992            InstId::Sqshl_v,
11993            &[rd.as_operand(), rn.as_operand(), rm_or_shift.as_operand()],
11994        );
11995    }
11996}
11997
11998impl SqshlEmitter<Vec, Vec, Imm> for Assembler<'_> {
11999    fn sqshl(&mut self, rd: Vec, rn: Vec, rm_or_shift: Imm) {
12000        self.emit_n(
12001            InstId::Sqshl_v,
12002            &[rd.as_operand(), rn.as_operand(), rm_or_shift.as_operand()],
12003        );
12004    }
12005}
12006
12007impl SqshluEmitter<Vec, Vec, Imm> for Assembler<'_> {
12008    fn sqshlu(&mut self, rd: Vec, rn: Vec, shift: Imm) {
12009        self.emit_n(
12010            InstId::Sqshlu_v,
12011            &[rd.as_operand(), rn.as_operand(), shift.as_operand()],
12012        );
12013    }
12014}
12015
12016impl SqshrnEmitter<Vec, Vec, Imm> for Assembler<'_> {
12017    fn sqshrn(&mut self, rd: Vec, rn: Vec, shift: Imm) {
12018        self.emit_n(
12019            InstId::Sqshrn_v,
12020            &[rd.as_operand(), rn.as_operand(), shift.as_operand()],
12021        );
12022    }
12023}
12024
12025impl Sqshrn2Emitter<Vec, Vec, Imm> for Assembler<'_> {
12026    fn sqshrn2(&mut self, operand_1: Vec, rn: Vec, shift: Imm) {
12027        self.emit_n(
12028            InstId::Sqshrn2_v,
12029            &[operand_1.as_operand(), rn.as_operand(), shift.as_operand()],
12030        );
12031    }
12032}
12033
12034impl SqshrunEmitter<Vec, Vec, Imm> for Assembler<'_> {
12035    fn sqshrun(&mut self, rd: Vec, rn: Vec, shift: Imm) {
12036        self.emit_n(
12037            InstId::Sqshrun_v,
12038            &[rd.as_operand(), rn.as_operand(), shift.as_operand()],
12039        );
12040    }
12041}
12042
12043impl Sqshrun2Emitter<Vec, Vec, Imm> for Assembler<'_> {
12044    fn sqshrun2(&mut self, operand_1: Vec, rn: Vec, shift: Imm) {
12045        self.emit_n(
12046            InstId::Sqshrun2_v,
12047            &[operand_1.as_operand(), rn.as_operand(), shift.as_operand()],
12048        );
12049    }
12050}
12051
12052impl SqsubEmitter<Vec, Vec, Vec> for Assembler<'_> {
12053    fn sqsub(&mut self, rd: Vec, rn: Vec, rm: Vec) {
12054        self.emit_n(
12055            InstId::Sqsub_v,
12056            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
12057        );
12058    }
12059}
12060
12061impl SqxtnEmitter<Vec, Vec> for Assembler<'_> {
12062    fn sqxtn(&mut self, rd: Vec, rn: Vec) {
12063        self.emit_n(InstId::Sqxtn_v, &[rd.as_operand(), rn.as_operand()]);
12064    }
12065}
12066
12067impl Sqxtn2Emitter<Vec, Vec> for Assembler<'_> {
12068    fn sqxtn2(&mut self, operand_1: Vec, rn: Vec) {
12069        self.emit_n(InstId::Sqxtn2_v, &[operand_1.as_operand(), rn.as_operand()]);
12070    }
12071}
12072
12073impl SqxtunEmitter<Vec, Vec> for Assembler<'_> {
12074    fn sqxtun(&mut self, rd: Vec, rn: Vec) {
12075        self.emit_n(InstId::Sqxtun_v, &[rd.as_operand(), rn.as_operand()]);
12076    }
12077}
12078
12079impl Sqxtun2Emitter<Vec, Vec> for Assembler<'_> {
12080    fn sqxtun2(&mut self, operand_1: Vec, rn: Vec) {
12081        self.emit_n(
12082            InstId::Sqxtun2_v,
12083            &[operand_1.as_operand(), rn.as_operand()],
12084        );
12085    }
12086}
12087
12088impl SrhaddEmitter<Vec, Vec, Vec> for Assembler<'_> {
12089    fn srhadd(&mut self, rd: Vec, rn: Vec, rm: Vec) {
12090        self.emit_n(
12091            InstId::Srhadd_v,
12092            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
12093        );
12094    }
12095}
12096
12097impl SriEmitter<Vec, Vec, Imm> for Assembler<'_> {
12098    fn sri(&mut self, operand_1: Vec, rn: Vec, shift: Imm) {
12099        self.emit_n(
12100            InstId::Sri_v,
12101            &[operand_1.as_operand(), rn.as_operand(), shift.as_operand()],
12102        );
12103    }
12104}
12105
12106impl SrshlEmitter<Vec, Vec, Vec> for Assembler<'_> {
12107    fn srshl(&mut self, rd: Vec, rn: Vec, rm: Vec) {
12108        self.emit_n(
12109            InstId::Srshl_v,
12110            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
12111        );
12112    }
12113}
12114
12115impl SrshrEmitter<Vec, Vec, Imm> for Assembler<'_> {
12116    fn srshr(&mut self, rd: Vec, rn: Vec, shift: Imm) {
12117        self.emit_n(
12118            InstId::Srshr_v,
12119            &[rd.as_operand(), rn.as_operand(), shift.as_operand()],
12120        );
12121    }
12122}
12123
12124impl SrsraEmitter<Vec, Vec, Imm> for Assembler<'_> {
12125    fn srsra(&mut self, operand_1: Vec, rn: Vec, shift: Imm) {
12126        self.emit_n(
12127            InstId::Srsra_v,
12128            &[operand_1.as_operand(), rn.as_operand(), shift.as_operand()],
12129        );
12130    }
12131}
12132
12133impl SshlEmitter<Vec, Vec, Vec> for Assembler<'_> {
12134    fn sshl(&mut self, rd: Vec, rn: Vec, rm: Vec) {
12135        self.emit_n(
12136            InstId::Sshl_v,
12137            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
12138        );
12139    }
12140}
12141
12142impl SshllEmitter<Vec, Vec, Imm> for Assembler<'_> {
12143    fn sshll(&mut self, rd: Vec, rn: Vec, shift: Imm) {
12144        self.emit_n(
12145            InstId::Sshll_v,
12146            &[rd.as_operand(), rn.as_operand(), shift.as_operand()],
12147        );
12148    }
12149}
12150
12151impl Sshll2Emitter<Vec, Vec, Imm> for Assembler<'_> {
12152    fn sshll2(&mut self, rd: Vec, rn: Vec, shift: Imm) {
12153        self.emit_n(
12154            InstId::Sshll2_v,
12155            &[rd.as_operand(), rn.as_operand(), shift.as_operand()],
12156        );
12157    }
12158}
12159
12160impl SshrEmitter<Vec, Vec, Imm> for Assembler<'_> {
12161    fn sshr(&mut self, rd: Vec, rn: Vec, shift: Imm) {
12162        self.emit_n(
12163            InstId::Sshr_v,
12164            &[rd.as_operand(), rn.as_operand(), shift.as_operand()],
12165        );
12166    }
12167}
12168
12169impl SsraEmitter<Vec, Vec, Imm> for Assembler<'_> {
12170    fn ssra(&mut self, operand_1: Vec, rn: Vec, shift: Imm) {
12171        self.emit_n(
12172            InstId::Ssra_v,
12173            &[operand_1.as_operand(), rn.as_operand(), shift.as_operand()],
12174        );
12175    }
12176}
12177
12178impl SsublEmitter<Vec, Vec, Vec> for Assembler<'_> {
12179    fn ssubl(&mut self, rd: Vec, rn: Vec, rm: Vec) {
12180        self.emit_n(
12181            InstId::Ssubl_v,
12182            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
12183        );
12184    }
12185}
12186
12187impl Ssubl2Emitter<Vec, Vec, Vec> for Assembler<'_> {
12188    fn ssubl2(&mut self, rd: Vec, rn: Vec, rm: Vec) {
12189        self.emit_n(
12190            InstId::Ssubl2_v,
12191            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
12192        );
12193    }
12194}
12195
12196impl SsubwEmitter<Vec, Vec, Vec> for Assembler<'_> {
12197    fn ssubw(&mut self, rd: Vec, rn: Vec, rm: Vec) {
12198        self.emit_n(
12199            InstId::Ssubw_v,
12200            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
12201        );
12202    }
12203}
12204
12205impl Ssubw2Emitter<Vec, Vec, Vec> for Assembler<'_> {
12206    fn ssubw2(&mut self, rd: Vec, rn: Vec, rm: Vec) {
12207        self.emit_n(
12208            InstId::Ssubw2_v,
12209            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
12210        );
12211    }
12212}
12213
12214impl St1Emitter<Vec, Mem> for Assembler<'_> {
12215    fn st1(&mut self, rs_or_operand_1: Vec, addr: Mem) {
12216        self.emit_n(
12217            InstId::St1_v,
12218            &[rs_or_operand_1.as_operand(), addr.as_operand()],
12219        );
12220    }
12221}
12222
12223impl St13Emitter<Vec, Vec, Mem> for Assembler<'_> {
12224    fn st1_3(&mut self, rd: Vec, rn: Vec, addr: Mem) {
12225        self.emit_n(
12226            InstId::St1_v,
12227            &[rd.as_operand(), rn.as_operand(), addr.as_operand()],
12228        );
12229    }
12230}
12231
12232impl St14Emitter<Vec, Vec, Vec, Mem> for Assembler<'_> {
12233    fn st1_4(&mut self, rd: Vec, rn: Vec, rm1: Vec, addr: Mem) {
12234        self.emit_n(
12235            InstId::St1_v,
12236            &[
12237                rd.as_operand(),
12238                rn.as_operand(),
12239                rm1.as_operand(),
12240                addr.as_operand(),
12241            ],
12242        );
12243    }
12244}
12245
12246impl St15Emitter<Vec, Vec, Vec, Vec, Mem> for Assembler<'_> {
12247    fn st1_5(&mut self, rd: Vec, rn: Vec, rm1: Vec, rm2: Vec, addr: Mem) {
12248        self.emit_n(
12249            InstId::St1_v,
12250            &[
12251                rd.as_operand(),
12252                rn.as_operand(),
12253                rm1.as_operand(),
12254                rm2.as_operand(),
12255                addr.as_operand(),
12256            ],
12257        );
12258    }
12259}
12260
12261impl St2Emitter<Vec, Vec, Mem> for Assembler<'_> {
12262    fn st2(&mut self, rd: Vec, rn: Vec, addr: Mem) {
12263        self.emit_n(
12264            InstId::St2_v,
12265            &[rd.as_operand(), rn.as_operand(), addr.as_operand()],
12266        );
12267    }
12268}
12269
12270impl St3Emitter<Vec, Vec, Vec, Mem> for Assembler<'_> {
12271    fn st3(&mut self, rd: Vec, rn: Vec, rm1: Vec, addr: Mem) {
12272        self.emit_n(
12273            InstId::St3_v,
12274            &[
12275                rd.as_operand(),
12276                rn.as_operand(),
12277                rm1.as_operand(),
12278                addr.as_operand(),
12279            ],
12280        );
12281    }
12282}
12283
12284impl St4Emitter<Vec, Vec, Vec, Vec, Mem> for Assembler<'_> {
12285    fn st4(&mut self, rd: Vec, rn: Vec, rm1: Vec, rm2: Vec, addr: Mem) {
12286        self.emit_n(
12287            InstId::St4_v,
12288            &[
12289                rd.as_operand(),
12290                rn.as_operand(),
12291                rm1.as_operand(),
12292                rm2.as_operand(),
12293                addr.as_operand(),
12294            ],
12295        );
12296    }
12297}
12298
12299impl SubhnEmitter<Vec, Vec, Vec> for Assembler<'_> {
12300    fn subhn(&mut self, rd: Vec, rn: Vec, rm: Vec) {
12301        self.emit_n(
12302            InstId::Subhn_v,
12303            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
12304        );
12305    }
12306}
12307
12308impl Subhn2Emitter<Vec, Vec, Vec> for Assembler<'_> {
12309    fn subhn2(&mut self, operand_1: Vec, rn: Vec, rm: Vec) {
12310        self.emit_n(
12311            InstId::Subhn2_v,
12312            &[operand_1.as_operand(), rn.as_operand(), rm.as_operand()],
12313        );
12314    }
12315}
12316
12317impl SuqaddEmitter<Vec, Vec> for Assembler<'_> {
12318    fn suqadd(&mut self, operand_1: Vec, rn: Vec) {
12319        self.emit_n(InstId::Suqadd_v, &[operand_1.as_operand(), rn.as_operand()]);
12320    }
12321}
12322
12323impl SxtlEmitter<Vec, Vec> for Assembler<'_> {
12324    fn sxtl(&mut self, rd: Vec, rn: Vec) {
12325        self.emit_n(InstId::Sxtl_v, &[rd.as_operand(), rn.as_operand()]);
12326    }
12327}
12328
12329impl Sxtl2Emitter<Vec, Vec> for Assembler<'_> {
12330    fn sxtl2(&mut self, rd: Vec, rn: Vec) {
12331        self.emit_n(InstId::Sxtl2_v, &[rd.as_operand(), rn.as_operand()]);
12332    }
12333}
12334
12335impl TblEmitter<Vec, Vec, Vec> for Assembler<'_> {
12336    fn tbl(&mut self, rd: Vec, rn_or_operand_2: Vec, rm: Vec) {
12337        self.emit_n(
12338            InstId::Tbl_v,
12339            &[
12340                rd.as_operand(),
12341                rn_or_operand_2.as_operand(),
12342                rm.as_operand(),
12343            ],
12344        );
12345    }
12346}
12347
12348impl Tbl4Emitter<Vec, Vec, Vec, Vec> for Assembler<'_> {
12349    fn tbl_4(&mut self, rd: Vec, rn: Vec, rm1: Vec, rm2: Vec) {
12350        self.emit_n(
12351            InstId::Tbl_v,
12352            &[
12353                rd.as_operand(),
12354                rn.as_operand(),
12355                rm1.as_operand(),
12356                rm2.as_operand(),
12357            ],
12358        );
12359    }
12360}
12361
12362impl Tbl5Emitter<Vec, Vec, Vec, Vec, Vec> for Assembler<'_> {
12363    fn tbl_5(&mut self, rd: Vec, rn: Vec, rm1: Vec, rm2: Vec, rm3: Vec) {
12364        self.emit_n(
12365            InstId::Tbl_v,
12366            &[
12367                rd.as_operand(),
12368                rn.as_operand(),
12369                rm1.as_operand(),
12370                rm2.as_operand(),
12371                rm3.as_operand(),
12372            ],
12373        );
12374    }
12375}
12376
12377impl Tbl6Emitter<Vec, Vec, Vec, Vec, Vec, Vec> for Assembler<'_> {
12378    fn tbl_6(&mut self, rd: Vec, rn: Vec, rm1: Vec, rm2: Vec, rm3: Vec, rm4: Vec) {
12379        self.emit_n(
12380            InstId::Tbl_v,
12381            &[
12382                rd.as_operand(),
12383                rn.as_operand(),
12384                rm1.as_operand(),
12385                rm2.as_operand(),
12386                rm3.as_operand(),
12387                rm4.as_operand(),
12388            ],
12389        );
12390    }
12391}
12392
12393impl TbxEmitter<Vec, Vec, Vec> for Assembler<'_> {
12394    fn tbx(&mut self, operand_1: Vec, rn_or_operand_2: Vec, rm: Vec) {
12395        self.emit_n(
12396            InstId::Tbx_v,
12397            &[
12398                operand_1.as_operand(),
12399                rn_or_operand_2.as_operand(),
12400                rm.as_operand(),
12401            ],
12402        );
12403    }
12404}
12405
12406impl Tbx4Emitter<Vec, Vec, Vec, Vec> for Assembler<'_> {
12407    fn tbx_4(&mut self, rd: Vec, rn: Vec, rm1: Vec, rm2: Vec) {
12408        self.emit_n(
12409            InstId::Tbx_v,
12410            &[
12411                rd.as_operand(),
12412                rn.as_operand(),
12413                rm1.as_operand(),
12414                rm2.as_operand(),
12415            ],
12416        );
12417    }
12418}
12419
12420impl Tbx5Emitter<Vec, Vec, Vec, Vec, Vec> for Assembler<'_> {
12421    fn tbx_5(&mut self, rd: Vec, rn: Vec, rm1: Vec, rm2: Vec, rm3: Vec) {
12422        self.emit_n(
12423            InstId::Tbx_v,
12424            &[
12425                rd.as_operand(),
12426                rn.as_operand(),
12427                rm1.as_operand(),
12428                rm2.as_operand(),
12429                rm3.as_operand(),
12430            ],
12431        );
12432    }
12433}
12434
12435impl Tbx6Emitter<Vec, Vec, Vec, Vec, Vec, Vec> for Assembler<'_> {
12436    fn tbx_6(&mut self, rd: Vec, rn: Vec, rm1: Vec, rm2: Vec, rm3: Vec, rm4: Vec) {
12437        self.emit_n(
12438            InstId::Tbx_v,
12439            &[
12440                rd.as_operand(),
12441                rn.as_operand(),
12442                rm1.as_operand(),
12443                rm2.as_operand(),
12444                rm3.as_operand(),
12445                rm4.as_operand(),
12446            ],
12447        );
12448    }
12449}
12450
12451impl Trn1Emitter<Vec, Vec, Vec> for Assembler<'_> {
12452    fn trn1(&mut self, rd: Vec, rn: Vec, rm: Vec) {
12453        self.emit_n(
12454            InstId::Trn1_v,
12455            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
12456        );
12457    }
12458}
12459
12460impl Trn2Emitter<Vec, Vec, Vec> for Assembler<'_> {
12461    fn trn2(&mut self, rd: Vec, rn: Vec, rm: Vec) {
12462        self.emit_n(
12463            InstId::Trn2_v,
12464            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
12465        );
12466    }
12467}
12468
12469impl UabaEmitter<Vec, Vec, Vec> for Assembler<'_> {
12470    fn uaba(&mut self, operand_1: Vec, rn: Vec, rm: Vec) {
12471        self.emit_n(
12472            InstId::Uaba_v,
12473            &[operand_1.as_operand(), rn.as_operand(), rm.as_operand()],
12474        );
12475    }
12476}
12477
12478impl UabalEmitter<Vec, Vec, Vec> for Assembler<'_> {
12479    fn uabal(&mut self, operand_1: Vec, rn: Vec, rm: Vec) {
12480        self.emit_n(
12481            InstId::Uabal_v,
12482            &[operand_1.as_operand(), rn.as_operand(), rm.as_operand()],
12483        );
12484    }
12485}
12486
12487impl Uabal2Emitter<Vec, Vec, Vec> for Assembler<'_> {
12488    fn uabal2(&mut self, operand_1: Vec, rn: Vec, rm: Vec) {
12489        self.emit_n(
12490            InstId::Uabal2_v,
12491            &[operand_1.as_operand(), rn.as_operand(), rm.as_operand()],
12492        );
12493    }
12494}
12495
12496impl UabdEmitter<Vec, Vec, Vec> for Assembler<'_> {
12497    fn uabd(&mut self, rd: Vec, rn: Vec, rm: Vec) {
12498        self.emit_n(
12499            InstId::Uabd_v,
12500            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
12501        );
12502    }
12503}
12504
12505impl UabdlEmitter<Vec, Vec, Vec> for Assembler<'_> {
12506    fn uabdl(&mut self, rd: Vec, rn: Vec, rm: Vec) {
12507        self.emit_n(
12508            InstId::Uabdl_v,
12509            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
12510        );
12511    }
12512}
12513
12514impl Uabdl2Emitter<Vec, Vec, Vec> for Assembler<'_> {
12515    fn uabdl2(&mut self, rd: Vec, rn: Vec, rm: Vec) {
12516        self.emit_n(
12517            InstId::Uabdl2_v,
12518            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
12519        );
12520    }
12521}
12522
12523impl UadalpEmitter<Vec, Vec> for Assembler<'_> {
12524    fn uadalp(&mut self, operand_1: Vec, rn: Vec) {
12525        self.emit_n(InstId::Uadalp_v, &[operand_1.as_operand(), rn.as_operand()]);
12526    }
12527}
12528
12529impl UaddlEmitter<Vec, Vec, Vec> for Assembler<'_> {
12530    fn uaddl(&mut self, rd: Vec, rn: Vec, rm: Vec) {
12531        self.emit_n(
12532            InstId::Uaddl_v,
12533            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
12534        );
12535    }
12536}
12537
12538impl Uaddl2Emitter<Vec, Vec, Vec> for Assembler<'_> {
12539    fn uaddl2(&mut self, rd: Vec, rn: Vec, rm: Vec) {
12540        self.emit_n(
12541            InstId::Uaddl2_v,
12542            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
12543        );
12544    }
12545}
12546
12547impl UaddlpEmitter<Vec, Vec> for Assembler<'_> {
12548    fn uaddlp(&mut self, rd: Vec, rn: Vec) {
12549        self.emit_n(InstId::Uaddlp_v, &[rd.as_operand(), rn.as_operand()]);
12550    }
12551}
12552
12553impl UaddlvEmitter<Vec, Vec> for Assembler<'_> {
12554    fn uaddlv(&mut self, rd: Vec, rn: Vec) {
12555        self.emit_n(InstId::Uaddlv_v, &[rd.as_operand(), rn.as_operand()]);
12556    }
12557}
12558
12559impl UaddwEmitter<Vec, Vec, Vec> for Assembler<'_> {
12560    fn uaddw(&mut self, rd: Vec, rn: Vec, rm: Vec) {
12561        self.emit_n(
12562            InstId::Uaddw_v,
12563            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
12564        );
12565    }
12566}
12567
12568impl Uaddw2Emitter<Vec, Vec, Vec> for Assembler<'_> {
12569    fn uaddw2(&mut self, rd: Vec, rn: Vec, rm: Vec) {
12570        self.emit_n(
12571            InstId::Uaddw2_v,
12572            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
12573        );
12574    }
12575}
12576
12577impl UcvtfEmitter<Vec, Gp> for Assembler<'_> {
12578    fn ucvtf(&mut self, rd: Vec, rn: Gp) {
12579        self.emit_n(InstId::Ucvtf_v, &[rd.as_operand(), rn.as_operand()]);
12580    }
12581}
12582
12583impl UcvtfEmitter<Vec, Vec> for Assembler<'_> {
12584    fn ucvtf(&mut self, rd: Vec, rn: Vec) {
12585        self.emit_n(InstId::Ucvtf_v, &[rd.as_operand(), rn.as_operand()]);
12586    }
12587}
12588
12589impl Ucvtf3Emitter<Vec, Gp, Imm> for Assembler<'_> {
12590    fn ucvtf_3(&mut self, rd: Vec, rn: Gp, fbits_or_bits: Imm) {
12591        self.emit_n(
12592            InstId::Ucvtf_v,
12593            &[rd.as_operand(), rn.as_operand(), fbits_or_bits.as_operand()],
12594        );
12595    }
12596}
12597
12598impl Ucvtf3Emitter<Vec, Vec, Imm> for Assembler<'_> {
12599    fn ucvtf_3(&mut self, rd: Vec, rn: Vec, fbits_or_bits: Imm) {
12600        self.emit_n(
12601            InstId::Ucvtf_v,
12602            &[rd.as_operand(), rn.as_operand(), fbits_or_bits.as_operand()],
12603        );
12604    }
12605}
12606
12607impl UhaddEmitter<Vec, Vec, Vec> for Assembler<'_> {
12608    fn uhadd(&mut self, rd: Vec, rn: Vec, rm: Vec) {
12609        self.emit_n(
12610            InstId::Uhadd_v,
12611            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
12612        );
12613    }
12614}
12615
12616impl UhsubEmitter<Vec, Vec, Vec> for Assembler<'_> {
12617    fn uhsub(&mut self, rd: Vec, rn: Vec, rm: Vec) {
12618        self.emit_n(
12619            InstId::Uhsub_v,
12620            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
12621        );
12622    }
12623}
12624
12625impl UmaxpEmitter<Vec, Vec, Vec> for Assembler<'_> {
12626    fn umaxp(&mut self, rd: Vec, rn: Vec, rm: Vec) {
12627        self.emit_n(
12628            InstId::Umaxp_v,
12629            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
12630        );
12631    }
12632}
12633
12634impl UmaxvEmitter<Vec, Vec> for Assembler<'_> {
12635    fn umaxv(&mut self, rd: Vec, rn: Vec) {
12636        self.emit_n(InstId::Umaxv_v, &[rd.as_operand(), rn.as_operand()]);
12637    }
12638}
12639
12640impl UminpEmitter<Vec, Vec, Vec> for Assembler<'_> {
12641    fn uminp(&mut self, rd: Vec, rn: Vec, rm: Vec) {
12642        self.emit_n(
12643            InstId::Uminp_v,
12644            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
12645        );
12646    }
12647}
12648
12649impl UminvEmitter<Vec, Vec> for Assembler<'_> {
12650    fn uminv(&mut self, rd: Vec, rn: Vec) {
12651        self.emit_n(InstId::Uminv_v, &[rd.as_operand(), rn.as_operand()]);
12652    }
12653}
12654
12655impl UmlalEmitter<Vec, Vec, Vec> for Assembler<'_> {
12656    fn umlal(&mut self, rd: Vec, rn: Vec, rm: Vec) {
12657        self.emit_n(
12658            InstId::Umlal_v,
12659            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
12660        );
12661    }
12662}
12663
12664impl Umlal2Emitter<Vec, Vec, Vec> for Assembler<'_> {
12665    fn umlal2(&mut self, rd: Vec, rn: Vec, rm: Vec) {
12666        self.emit_n(
12667            InstId::Umlal2_v,
12668            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
12669        );
12670    }
12671}
12672
12673impl UmlslEmitter<Vec, Vec, Vec> for Assembler<'_> {
12674    fn umlsl(&mut self, rd: Vec, rn: Vec, rm: Vec) {
12675        self.emit_n(
12676            InstId::Umlsl_v,
12677            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
12678        );
12679    }
12680}
12681
12682impl Umlsl2Emitter<Vec, Vec, Vec> for Assembler<'_> {
12683    fn umlsl2(&mut self, rd: Vec, rn: Vec, rm: Vec) {
12684        self.emit_n(
12685            InstId::Umlsl2_v,
12686            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
12687        );
12688    }
12689}
12690
12691impl UmovEmitter<Gp, Vec> for Assembler<'_> {
12692    fn umov(&mut self, rd: Gp, rn: Vec) {
12693        self.emit_n(InstId::Umov_v, &[rd.as_operand(), rn.as_operand()]);
12694    }
12695}
12696
12697impl Umull2Emitter<Vec, Vec, Vec> for Assembler<'_> {
12698    fn umull2(&mut self, rd: Vec, rn: Vec, rm: Vec) {
12699        self.emit_n(
12700            InstId::Umull2_v,
12701            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
12702        );
12703    }
12704}
12705
12706impl UqaddEmitter<Vec, Vec, Vec> for Assembler<'_> {
12707    fn uqadd(&mut self, rd: Vec, rn: Vec, rm: Vec) {
12708        self.emit_n(
12709            InstId::Uqadd_v,
12710            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
12711        );
12712    }
12713}
12714
12715impl UqrshlEmitter<Vec, Vec, Vec> for Assembler<'_> {
12716    fn uqrshl(&mut self, rd: Vec, rn: Vec, rm: Vec) {
12717        self.emit_n(
12718            InstId::Uqrshl_v,
12719            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
12720        );
12721    }
12722}
12723
12724impl UqrshlEmitter<Vec, Vec, Imm> for Assembler<'_> {
12725    fn uqrshl(&mut self, rd: Vec, rn: Vec, rm: Imm) {
12726        self.emit_n(
12727            InstId::Uqrshl_v,
12728            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
12729        );
12730    }
12731}
12732
12733impl UqrshrnEmitter<Vec, Vec, Imm> for Assembler<'_> {
12734    fn uqrshrn(&mut self, rd: Vec, rn: Vec, shift: Imm) {
12735        self.emit_n(
12736            InstId::Uqrshrn_v,
12737            &[rd.as_operand(), rn.as_operand(), shift.as_operand()],
12738        );
12739    }
12740}
12741
12742impl Uqrshrn2Emitter<Vec, Vec, Imm> for Assembler<'_> {
12743    fn uqrshrn2(&mut self, operand_1: Vec, rn: Vec, shift: Imm) {
12744        self.emit_n(
12745            InstId::Uqrshrn2_v,
12746            &[operand_1.as_operand(), rn.as_operand(), shift.as_operand()],
12747        );
12748    }
12749}
12750
12751impl UqshlEmitter<Vec, Vec, Vec> for Assembler<'_> {
12752    fn uqshl(&mut self, rd: Vec, rn: Vec, rm_or_shift: Vec) {
12753        self.emit_n(
12754            InstId::Uqshl_v,
12755            &[rd.as_operand(), rn.as_operand(), rm_or_shift.as_operand()],
12756        );
12757    }
12758}
12759
12760impl UqshlEmitter<Vec, Vec, Imm> for Assembler<'_> {
12761    fn uqshl(&mut self, rd: Vec, rn: Vec, rm_or_shift: Imm) {
12762        self.emit_n(
12763            InstId::Uqshl_v,
12764            &[rd.as_operand(), rn.as_operand(), rm_or_shift.as_operand()],
12765        );
12766    }
12767}
12768
12769impl UqshrnEmitter<Vec, Vec, Imm> for Assembler<'_> {
12770    fn uqshrn(&mut self, rd: Vec, rn: Vec, shift: Imm) {
12771        self.emit_n(
12772            InstId::Uqshrn_v,
12773            &[rd.as_operand(), rn.as_operand(), shift.as_operand()],
12774        );
12775    }
12776}
12777
12778impl Uqshrn2Emitter<Vec, Vec, Imm> for Assembler<'_> {
12779    fn uqshrn2(&mut self, operand_1: Vec, rn: Vec, shift: Imm) {
12780        self.emit_n(
12781            InstId::Uqshrn2_v,
12782            &[operand_1.as_operand(), rn.as_operand(), shift.as_operand()],
12783        );
12784    }
12785}
12786
12787impl UqsubEmitter<Vec, Vec, Vec> for Assembler<'_> {
12788    fn uqsub(&mut self, rd: Vec, rn: Vec, rm: Vec) {
12789        self.emit_n(
12790            InstId::Uqsub_v,
12791            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
12792        );
12793    }
12794}
12795
12796impl UqxtnEmitter<Vec, Vec> for Assembler<'_> {
12797    fn uqxtn(&mut self, rd: Vec, rn: Vec) {
12798        self.emit_n(InstId::Uqxtn_v, &[rd.as_operand(), rn.as_operand()]);
12799    }
12800}
12801
12802impl Uqxtn2Emitter<Vec, Vec> for Assembler<'_> {
12803    fn uqxtn2(&mut self, operand_1: Vec, rn: Vec) {
12804        self.emit_n(InstId::Uqxtn2_v, &[operand_1.as_operand(), rn.as_operand()]);
12805    }
12806}
12807
12808impl UrecpeEmitter<Vec, Vec> for Assembler<'_> {
12809    fn urecpe(&mut self, rd: Vec, rn: Vec) {
12810        self.emit_n(InstId::Urecpe_v, &[rd.as_operand(), rn.as_operand()]);
12811    }
12812}
12813
12814impl UrhaddEmitter<Vec, Vec, Vec> for Assembler<'_> {
12815    fn urhadd(&mut self, rd: Vec, rn: Vec, rm: Vec) {
12816        self.emit_n(
12817            InstId::Urhadd_v,
12818            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
12819        );
12820    }
12821}
12822
12823impl UrshlEmitter<Vec, Vec, Vec> for Assembler<'_> {
12824    fn urshl(&mut self, rd: Vec, rn: Vec, rm: Vec) {
12825        self.emit_n(
12826            InstId::Urshl_v,
12827            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
12828        );
12829    }
12830}
12831
12832impl UrshrEmitter<Vec, Vec, Imm> for Assembler<'_> {
12833    fn urshr(&mut self, rd: Vec, rn: Vec, shift: Imm) {
12834        self.emit_n(
12835            InstId::Urshr_v,
12836            &[rd.as_operand(), rn.as_operand(), shift.as_operand()],
12837        );
12838    }
12839}
12840
12841impl UrsqrteEmitter<Vec, Vec> for Assembler<'_> {
12842    fn ursqrte(&mut self, rd: Vec, rn: Vec) {
12843        self.emit_n(InstId::Ursqrte_v, &[rd.as_operand(), rn.as_operand()]);
12844    }
12845}
12846
12847impl UrsraEmitter<Vec, Vec, Imm> for Assembler<'_> {
12848    fn ursra(&mut self, operand_1: Vec, rn: Vec, shift: Imm) {
12849        self.emit_n(
12850            InstId::Ursra_v,
12851            &[operand_1.as_operand(), rn.as_operand(), shift.as_operand()],
12852        );
12853    }
12854}
12855
12856impl UshlEmitter<Vec, Vec, Vec> for Assembler<'_> {
12857    fn ushl(&mut self, rd: Vec, rn: Vec, rm: Vec) {
12858        self.emit_n(
12859            InstId::Ushl_v,
12860            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
12861        );
12862    }
12863}
12864
12865impl UshllEmitter<Vec, Vec, Imm> for Assembler<'_> {
12866    fn ushll(&mut self, rd: Vec, rn: Vec, shift: Imm) {
12867        self.emit_n(
12868            InstId::Ushll_v,
12869            &[rd.as_operand(), rn.as_operand(), shift.as_operand()],
12870        );
12871    }
12872}
12873
12874impl Ushll2Emitter<Vec, Vec, Imm> for Assembler<'_> {
12875    fn ushll2(&mut self, rd: Vec, rn: Vec, shift: Imm) {
12876        self.emit_n(
12877            InstId::Ushll2_v,
12878            &[rd.as_operand(), rn.as_operand(), shift.as_operand()],
12879        );
12880    }
12881}
12882
12883impl UshrEmitter<Vec, Vec, Imm> for Assembler<'_> {
12884    fn ushr(&mut self, rd: Vec, rn: Vec, shift: Imm) {
12885        self.emit_n(
12886            InstId::Ushr_v,
12887            &[rd.as_operand(), rn.as_operand(), shift.as_operand()],
12888        );
12889    }
12890}
12891
12892impl UsqaddEmitter<Vec, Vec> for Assembler<'_> {
12893    fn usqadd(&mut self, operand_1: Vec, rn: Vec) {
12894        self.emit_n(InstId::Usqadd_v, &[operand_1.as_operand(), rn.as_operand()]);
12895    }
12896}
12897
12898impl UsraEmitter<Vec, Vec, Imm> for Assembler<'_> {
12899    fn usra(&mut self, operand_1: Vec, rn: Vec, shift: Imm) {
12900        self.emit_n(
12901            InstId::Usra_v,
12902            &[operand_1.as_operand(), rn.as_operand(), shift.as_operand()],
12903        );
12904    }
12905}
12906
12907impl UsublEmitter<Vec, Vec, Vec> for Assembler<'_> {
12908    fn usubl(&mut self, rd: Vec, rn: Vec, rm: Vec) {
12909        self.emit_n(
12910            InstId::Usubl_v,
12911            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
12912        );
12913    }
12914}
12915
12916impl Usubl2Emitter<Vec, Vec, Vec> for Assembler<'_> {
12917    fn usubl2(&mut self, rd: Vec, rn: Vec, rm: Vec) {
12918        self.emit_n(
12919            InstId::Usubl2_v,
12920            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
12921        );
12922    }
12923}
12924
12925impl UsubwEmitter<Vec, Vec, Vec> for Assembler<'_> {
12926    fn usubw(&mut self, rd: Vec, rn: Vec, rm: Vec) {
12927        self.emit_n(
12928            InstId::Usubw_v,
12929            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
12930        );
12931    }
12932}
12933
12934impl Usubw2Emitter<Vec, Vec, Vec> for Assembler<'_> {
12935    fn usubw2(&mut self, rd: Vec, rn: Vec, rm: Vec) {
12936        self.emit_n(
12937            InstId::Usubw2_v,
12938            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
12939        );
12940    }
12941}
12942
12943impl UxtlEmitter<Vec, Vec> for Assembler<'_> {
12944    fn uxtl(&mut self, rd: Vec, rn: Vec) {
12945        self.emit_n(InstId::Uxtl_v, &[rd.as_operand(), rn.as_operand()]);
12946    }
12947}
12948
12949impl Uxtl2Emitter<Vec, Vec> for Assembler<'_> {
12950    fn uxtl2(&mut self, rd: Vec, rn: Vec) {
12951        self.emit_n(InstId::Uxtl2_v, &[rd.as_operand(), rn.as_operand()]);
12952    }
12953}
12954
12955impl Uzp1Emitter<Vec, Vec, Vec> for Assembler<'_> {
12956    fn uzp1(&mut self, rd: Vec, rn: Vec, rm: Vec) {
12957        self.emit_n(
12958            InstId::Uzp1_v,
12959            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
12960        );
12961    }
12962}
12963
12964impl Uzp2Emitter<Vec, Vec, Vec> for Assembler<'_> {
12965    fn uzp2(&mut self, rd: Vec, rn: Vec, rm: Vec) {
12966        self.emit_n(
12967            InstId::Uzp2_v,
12968            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
12969        );
12970    }
12971}
12972
12973impl XtnEmitter<Vec, Vec> for Assembler<'_> {
12974    fn xtn(&mut self, rd: Vec, rn: Vec) {
12975        self.emit_n(InstId::Xtn_v, &[rd.as_operand(), rn.as_operand()]);
12976    }
12977}
12978
12979impl Xtn2Emitter<Vec, Vec> for Assembler<'_> {
12980    fn xtn2(&mut self, operand_1: Vec, rn: Vec) {
12981        self.emit_n(InstId::Xtn2_v, &[operand_1.as_operand(), rn.as_operand()]);
12982    }
12983}
12984
12985impl Zip1Emitter<Vec, Vec, Vec> for Assembler<'_> {
12986    fn zip1(&mut self, rd: Vec, rn: Vec, rm: Vec) {
12987        self.emit_n(
12988            InstId::Zip1_v,
12989            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
12990        );
12991    }
12992}
12993
12994impl Zip2Emitter<Vec, Vec, Vec> for Assembler<'_> {
12995    fn zip2(&mut self, rd: Vec, rn: Vec, rm: Vec) {
12996        self.emit_n(
12997            InstId::Zip2_v,
12998            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
12999        );
13000    }
13001}
13002
13003impl AesdEmitter<Vec, Vec> for Assembler<'_> {
13004    fn aesd(&mut self, rd: Vec, rn: Vec) {
13005        self.emit_n(InstId::Aesd_v, &[rd.as_operand(), rn.as_operand()]);
13006    }
13007}
13008
13009impl AeseEmitter<Vec, Vec> for Assembler<'_> {
13010    fn aese(&mut self, rd: Vec, rn: Vec) {
13011        self.emit_n(InstId::Aese_v, &[rd.as_operand(), rn.as_operand()]);
13012    }
13013}
13014
13015impl AesimcEmitter<Vec, Vec> for Assembler<'_> {
13016    fn aesimc(&mut self, rd: Vec, rn: Vec) {
13017        self.emit_n(InstId::Aesimc_v, &[rd.as_operand(), rn.as_operand()]);
13018    }
13019}
13020
13021impl AesmcEmitter<Vec, Vec> for Assembler<'_> {
13022    fn aesmc(&mut self, rd: Vec, rn: Vec) {
13023        self.emit_n(InstId::Aesmc_v, &[rd.as_operand(), rn.as_operand()]);
13024    }
13025}
13026
13027impl Sha1cEmitter<Vec, Vec, Vec> for Assembler<'_> {
13028    fn sha1c(&mut self, operand_1: Vec, rn: Vec, rm: Vec) {
13029        self.emit_n(
13030            InstId::Sha1c_v,
13031            &[operand_1.as_operand(), rn.as_operand(), rm.as_operand()],
13032        );
13033    }
13034}
13035
13036impl Sha1hEmitter<Vec, Vec> for Assembler<'_> {
13037    fn sha1h(&mut self, rd: Vec, rn: Vec) {
13038        self.emit_n(InstId::Sha1h_v, &[rd.as_operand(), rn.as_operand()]);
13039    }
13040}
13041
13042impl Sha1mEmitter<Vec, Vec, Vec> for Assembler<'_> {
13043    fn sha1m(&mut self, operand_1: Vec, rn: Vec, rm: Vec) {
13044        self.emit_n(
13045            InstId::Sha1m_v,
13046            &[operand_1.as_operand(), rn.as_operand(), rm.as_operand()],
13047        );
13048    }
13049}
13050
13051impl Sha1pEmitter<Vec, Vec, Vec> for Assembler<'_> {
13052    fn sha1p(&mut self, operand_1: Vec, rn: Vec, rm: Vec) {
13053        self.emit_n(
13054            InstId::Sha1p_v,
13055            &[operand_1.as_operand(), rn.as_operand(), rm.as_operand()],
13056        );
13057    }
13058}
13059
13060impl Sha1su0Emitter<Vec, Vec, Vec> for Assembler<'_> {
13061    fn sha1su0(&mut self, operand_1: Vec, rn: Vec, rm: Vec) {
13062        self.emit_n(
13063            InstId::Sha1su0_v,
13064            &[operand_1.as_operand(), rn.as_operand(), rm.as_operand()],
13065        );
13066    }
13067}
13068
13069impl Sha1su1Emitter<Vec, Vec> for Assembler<'_> {
13070    fn sha1su1(&mut self, operand_1: Vec, rn: Vec) {
13071        self.emit_n(
13072            InstId::Sha1su1_v,
13073            &[operand_1.as_operand(), rn.as_operand()],
13074        );
13075    }
13076}
13077
13078impl Sha256hEmitter<Vec, Vec, Vec> for Assembler<'_> {
13079    fn sha256h(&mut self, operand_1: Vec, rn: Vec, rm: Vec) {
13080        self.emit_n(
13081            InstId::Sha256h_v,
13082            &[operand_1.as_operand(), rn.as_operand(), rm.as_operand()],
13083        );
13084    }
13085}
13086
13087impl Sha256h2Emitter<Vec, Vec, Vec> for Assembler<'_> {
13088    fn sha256h2(&mut self, operand_1: Vec, rn: Vec, rm: Vec) {
13089        self.emit_n(
13090            InstId::Sha256h2_v,
13091            &[operand_1.as_operand(), rn.as_operand(), rm.as_operand()],
13092        );
13093    }
13094}
13095
13096impl Sha256su0Emitter<Vec, Vec> for Assembler<'_> {
13097    fn sha256su0(&mut self, operand_1: Vec, rn: Vec) {
13098        self.emit_n(
13099            InstId::Sha256su0_v,
13100            &[operand_1.as_operand(), rn.as_operand()],
13101        );
13102    }
13103}
13104
13105impl Sha256su1Emitter<Vec, Vec, Vec> for Assembler<'_> {
13106    fn sha256su1(&mut self, operand_1: Vec, rn: Vec, rm: Vec) {
13107        self.emit_n(
13108            InstId::Sha256su1_v,
13109            &[operand_1.as_operand(), rn.as_operand(), rm.as_operand()],
13110        );
13111    }
13112}
13113
13114impl SqrdmlahEmitter<Vec, Vec, Vec> for Assembler<'_> {
13115    fn sqrdmlah(&mut self, operand_1: Vec, rn: Vec, rm_or_rn: Vec) {
13116        self.emit_n(
13117            InstId::Sqrdmlah_v,
13118            &[
13119                operand_1.as_operand(),
13120                rn.as_operand(),
13121                rm_or_rn.as_operand(),
13122            ],
13123        );
13124    }
13125}
13126
13127impl SqrdmlshEmitter<Vec, Vec, Vec> for Assembler<'_> {
13128    fn sqrdmlsh(&mut self, operand_1: Vec, rn: Vec, rm_or_rn: Vec) {
13129        self.emit_n(
13130            InstId::Sqrdmlsh_v,
13131            &[
13132                operand_1.as_operand(),
13133                rn.as_operand(),
13134                rm_or_rn.as_operand(),
13135            ],
13136        );
13137    }
13138}
13139
13140impl FcaddEmitter<Vec, Vec, Vec, Imm> for Assembler<'_> {
13141    fn fcadd(&mut self, rd: Vec, rn: Vec, rm: Vec, rotate: Imm) {
13142        self.emit_n(
13143            InstId::Fcadd_v,
13144            &[
13145                rd.as_operand(),
13146                rn.as_operand(),
13147                rm.as_operand(),
13148                rotate.as_operand(),
13149            ],
13150        );
13151    }
13152}
13153
13154impl FcmlaEmitter<Vec, Vec, Vec, Imm> for Assembler<'_> {
13155    fn fcmla(&mut self, rd: Vec, rn: Vec, rm: Vec, rotate: Imm) {
13156        self.emit_n(
13157            InstId::Fcmla_v,
13158            &[
13159                rd.as_operand(),
13160                rn.as_operand(),
13161                rm.as_operand(),
13162                rotate.as_operand(),
13163            ],
13164        );
13165    }
13166}
13167
13168impl FjcvtzsEmitter<Gp, Vec> for Assembler<'_> {
13169    fn fjcvtzs(&mut self, rd: Gp, rn: Vec) {
13170        self.emit_n(InstId::Fjcvtzs_v, &[rd.as_operand(), rn.as_operand()]);
13171    }
13172}
13173
13174impl FmlalEmitter<Vec, Vec, Vec> for Assembler<'_> {
13175    fn fmlal(&mut self, operand_1: Vec, rn: Vec, rm: Vec) {
13176        self.emit_n(
13177            InstId::Fmlal_v,
13178            &[operand_1.as_operand(), rn.as_operand(), rm.as_operand()],
13179        );
13180    }
13181}
13182
13183impl Fmlal2Emitter<Vec, Vec, Vec> for Assembler<'_> {
13184    fn fmlal2(&mut self, operand_1: Vec, rn: Vec, rm: Vec) {
13185        self.emit_n(
13186            InstId::Fmlal2_v,
13187            &[operand_1.as_operand(), rn.as_operand(), rm.as_operand()],
13188        );
13189    }
13190}
13191
13192impl FmlslEmitter<Vec, Vec, Vec> for Assembler<'_> {
13193    fn fmlsl(&mut self, operand_1: Vec, rn: Vec, rm: Vec) {
13194        self.emit_n(
13195            InstId::Fmlsl_v,
13196            &[operand_1.as_operand(), rn.as_operand(), rm.as_operand()],
13197        );
13198    }
13199}
13200
13201impl Fmlsl2Emitter<Vec, Vec, Vec> for Assembler<'_> {
13202    fn fmlsl2(&mut self, operand_1: Vec, rn: Vec, rm: Vec) {
13203        self.emit_n(
13204            InstId::Fmlsl2_v,
13205            &[operand_1.as_operand(), rn.as_operand(), rm.as_operand()],
13206        );
13207    }
13208}
13209
13210impl BcaxEmitter<Vec, Vec, Vec, Vec> for Assembler<'_> {
13211    fn bcax(&mut self, rd: Vec, rn: Vec, rm: Vec, operand_4: Vec) {
13212        self.emit_n(
13213            InstId::Bcax_v,
13214            &[
13215                rd.as_operand(),
13216                rn.as_operand(),
13217                rm.as_operand(),
13218                operand_4.as_operand(),
13219            ],
13220        );
13221    }
13222}
13223
13224impl Eor3Emitter<Vec, Vec, Vec, Vec> for Assembler<'_> {
13225    fn eor3(&mut self, rd: Vec, rn: Vec, rm: Vec, operand_4: Vec) {
13226        self.emit_n(
13227            InstId::Eor3_v,
13228            &[
13229                rd.as_operand(),
13230                rn.as_operand(),
13231                rm.as_operand(),
13232                operand_4.as_operand(),
13233            ],
13234        );
13235    }
13236}
13237
13238impl Rax1Emitter<Vec, Vec, Vec> for Assembler<'_> {
13239    fn rax1(&mut self, rd: Vec, rn: Vec, rm: Vec) {
13240        self.emit_n(
13241            InstId::Rax1_v,
13242            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
13243        );
13244    }
13245}
13246
13247impl XarEmitter<Vec, Vec, Vec, Imm> for Assembler<'_> {
13248    fn xar(&mut self, rd: Vec, rn: Vec, rm: Vec, imm: Imm) {
13249        self.emit_n(
13250            InstId::Xar_v,
13251            &[
13252                rd.as_operand(),
13253                rn.as_operand(),
13254                rm.as_operand(),
13255                imm.as_operand(),
13256            ],
13257        );
13258    }
13259}
13260
13261impl Sha512hEmitter<Vec, Vec, Vec> for Assembler<'_> {
13262    fn sha512h(&mut self, operand_1: Vec, rn: Vec, rm: Vec) {
13263        self.emit_n(
13264            InstId::Sha512h_v,
13265            &[operand_1.as_operand(), rn.as_operand(), rm.as_operand()],
13266        );
13267    }
13268}
13269
13270impl Sha512h2Emitter<Vec, Vec, Vec> for Assembler<'_> {
13271    fn sha512h2(&mut self, operand_1: Vec, rn: Vec, rm: Vec) {
13272        self.emit_n(
13273            InstId::Sha512h2_v,
13274            &[operand_1.as_operand(), rn.as_operand(), rm.as_operand()],
13275        );
13276    }
13277}
13278
13279impl Sha512su0Emitter<Vec, Vec> for Assembler<'_> {
13280    fn sha512su0(&mut self, operand_1: Vec, rn: Vec) {
13281        self.emit_n(
13282            InstId::Sha512su0_v,
13283            &[operand_1.as_operand(), rn.as_operand()],
13284        );
13285    }
13286}
13287
13288impl Sha512su1Emitter<Vec, Vec, Vec> for Assembler<'_> {
13289    fn sha512su1(&mut self, operand_1: Vec, rn: Vec, rm: Vec) {
13290        self.emit_n(
13291            InstId::Sha512su1_v,
13292            &[operand_1.as_operand(), rn.as_operand(), rm.as_operand()],
13293        );
13294    }
13295}
13296
13297impl Sm3partw1Emitter<Vec, Vec, Vec> for Assembler<'_> {
13298    fn sm3partw1(&mut self, operand_1: Vec, rn: Vec, rm: Vec) {
13299        self.emit_n(
13300            InstId::Sm3partw1_v,
13301            &[operand_1.as_operand(), rn.as_operand(), rm.as_operand()],
13302        );
13303    }
13304}
13305
13306impl Sm3partw2Emitter<Vec, Vec, Vec> for Assembler<'_> {
13307    fn sm3partw2(&mut self, operand_1: Vec, rn: Vec, rm: Vec) {
13308        self.emit_n(
13309            InstId::Sm3partw2_v,
13310            &[operand_1.as_operand(), rn.as_operand(), rm.as_operand()],
13311        );
13312    }
13313}
13314
13315impl Sm3ss1Emitter<Vec, Vec, Vec, Vec> for Assembler<'_> {
13316    fn sm3ss1(&mut self, rd: Vec, rn: Vec, rm: Vec, operand_4: Vec) {
13317        self.emit_n(
13318            InstId::Sm3ss1_v,
13319            &[
13320                rd.as_operand(),
13321                rn.as_operand(),
13322                rm.as_operand(),
13323                operand_4.as_operand(),
13324            ],
13325        );
13326    }
13327}
13328
13329impl Sm3tt1aEmitter<Vec, Vec, Vec> for Assembler<'_> {
13330    fn sm3tt1a(&mut self, operand_1: Vec, rn: Vec, rm: Vec) {
13331        self.emit_n(
13332            InstId::Sm3tt1a_v,
13333            &[operand_1.as_operand(), rn.as_operand(), rm.as_operand()],
13334        );
13335    }
13336}
13337
13338impl Sm3tt1bEmitter<Vec, Vec, Vec> for Assembler<'_> {
13339    fn sm3tt1b(&mut self, operand_1: Vec, rn: Vec, rm: Vec) {
13340        self.emit_n(
13341            InstId::Sm3tt1b_v,
13342            &[operand_1.as_operand(), rn.as_operand(), rm.as_operand()],
13343        );
13344    }
13345}
13346
13347impl Sm3tt2aEmitter<Vec, Vec, Vec> for Assembler<'_> {
13348    fn sm3tt2a(&mut self, operand_1: Vec, rn: Vec, rm: Vec) {
13349        self.emit_n(
13350            InstId::Sm3tt2a_v,
13351            &[operand_1.as_operand(), rn.as_operand(), rm.as_operand()],
13352        );
13353    }
13354}
13355
13356impl Sm3tt2bEmitter<Vec, Vec, Vec> for Assembler<'_> {
13357    fn sm3tt2b(&mut self, operand_1: Vec, rn: Vec, rm: Vec) {
13358        self.emit_n(
13359            InstId::Sm3tt2b_v,
13360            &[operand_1.as_operand(), rn.as_operand(), rm.as_operand()],
13361        );
13362    }
13363}
13364
13365impl Sm4eEmitter<Vec, Vec> for Assembler<'_> {
13366    fn sm4e(&mut self, operand_1: Vec, rn: Vec) {
13367        self.emit_n(InstId::Sm4e_v, &[operand_1.as_operand(), rn.as_operand()]);
13368    }
13369}
13370
13371impl Sm4ekeyEmitter<Vec, Vec, Vec> for Assembler<'_> {
13372    fn sm4ekey(&mut self, rd: Vec, rn: Vec, rm: Vec) {
13373        self.emit_n(
13374            InstId::Sm4ekey_v,
13375            &[rd.as_operand(), rn.as_operand(), rm.as_operand()],
13376        );
13377    }
13378}
13379
13380impl SdotEmitter<Vec, Vec, Vec> for Assembler<'_> {
13381    fn sdot(&mut self, operand_1: Vec, rn: Vec, rm: Vec) {
13382        self.emit_n(
13383            InstId::Sdot_v,
13384            &[operand_1.as_operand(), rn.as_operand(), rm.as_operand()],
13385        );
13386    }
13387}
13388
13389impl UdotEmitter<Vec, Vec, Vec> for Assembler<'_> {
13390    fn udot(&mut self, operand_1: Vec, rn: Vec, rm: Vec) {
13391        self.emit_n(
13392            InstId::Udot_v,
13393            &[operand_1.as_operand(), rn.as_operand(), rm.as_operand()],
13394        );
13395    }
13396}
13397
13398impl BfcvtEmitter<Vec, Vec> for Assembler<'_> {
13399    fn bfcvt(&mut self, rd: Vec, rn: Vec) {
13400        self.emit_n(InstId::Bfcvt_v, &[rd.as_operand(), rn.as_operand()]);
13401    }
13402}
13403
13404impl BfcvtnEmitter<Vec, Vec> for Assembler<'_> {
13405    fn bfcvtn(&mut self, rd: Vec, rn: Vec) {
13406        self.emit_n(InstId::Bfcvtn_v, &[rd.as_operand(), rn.as_operand()]);
13407    }
13408}
13409
13410impl Bfcvtn2Emitter<Vec, Vec> for Assembler<'_> {
13411    fn bfcvtn2(&mut self, rd: Vec, rn: Vec) {
13412        self.emit_n(InstId::Bfcvtn2_v, &[rd.as_operand(), rn.as_operand()]);
13413    }
13414}
13415
13416impl BfmlalbEmitter<Vec, Vec, Vec> for Assembler<'_> {
13417    fn bfmlalb(&mut self, operand_1: Vec, rn: Vec, rm: Vec) {
13418        self.emit_n(
13419            InstId::Bfmlalb_v,
13420            &[operand_1.as_operand(), rn.as_operand(), rm.as_operand()],
13421        );
13422    }
13423}
13424
13425impl BfmlaltEmitter<Vec, Vec, Vec> for Assembler<'_> {
13426    fn bfmlalt(&mut self, operand_1: Vec, rn: Vec, rm: Vec) {
13427        self.emit_n(
13428            InstId::Bfmlalt_v,
13429            &[operand_1.as_operand(), rn.as_operand(), rm.as_operand()],
13430        );
13431    }
13432}
13433
13434impl BfmmlaEmitter<Vec, Vec, Vec> for Assembler<'_> {
13435    fn bfmmla(&mut self, operand_1: Vec, rn: Vec, rm: Vec) {
13436        self.emit_n(
13437            InstId::Bfmmla_v,
13438            &[operand_1.as_operand(), rn.as_operand(), rm.as_operand()],
13439        );
13440    }
13441}
13442
13443impl BfdotEmitter<Vec, Vec, Vec> for Assembler<'_> {
13444    fn bfdot(&mut self, operand_1: Vec, rn: Vec, rm: Vec) {
13445        self.emit_n(
13446            InstId::Bfdot_v,
13447            &[operand_1.as_operand(), rn.as_operand(), rm.as_operand()],
13448        );
13449    }
13450}
13451
13452impl SmmlaEmitter<Vec, Vec, Vec> for Assembler<'_> {
13453    fn smmla(&mut self, operand_1: Vec, rn: Vec, rm: Vec) {
13454        self.emit_n(
13455            InstId::Smmla_v,
13456            &[operand_1.as_operand(), rn.as_operand(), rm.as_operand()],
13457        );
13458    }
13459}
13460
13461impl SudotEmitter<Vec, Vec, Vec> for Assembler<'_> {
13462    fn sudot(&mut self, operand_1: Vec, rn: Vec, rm: Vec) {
13463        self.emit_n(
13464            InstId::Sudot_v,
13465            &[operand_1.as_operand(), rn.as_operand(), rm.as_operand()],
13466        );
13467    }
13468}
13469
13470impl UmmlaEmitter<Vec, Vec, Vec> for Assembler<'_> {
13471    fn ummla(&mut self, operand_1: Vec, rn: Vec, rm: Vec) {
13472        self.emit_n(
13473            InstId::Ummla_v,
13474            &[operand_1.as_operand(), rn.as_operand(), rm.as_operand()],
13475        );
13476    }
13477}
13478
13479impl UsdotEmitter<Vec, Vec, Vec> for Assembler<'_> {
13480    fn usdot(&mut self, operand_1: Vec, rn: Vec, rm: Vec) {
13481        self.emit_n(
13482            InstId::Usdot_v,
13483            &[operand_1.as_operand(), rn.as_operand(), rm.as_operand()],
13484        );
13485    }
13486}
13487
13488impl UsmmlaEmitter<Vec, Vec, Vec> for Assembler<'_> {
13489    fn usmmla(&mut self, operand_1: Vec, rn: Vec, rm: Vec) {
13490        self.emit_n(
13491            InstId::Usmmla_v,
13492            &[operand_1.as_operand(), rn.as_operand(), rm.as_operand()],
13493        );
13494    }
13495}
13496
13497impl Assembler<'_> {
13498    /// Emits the `ADC` instruction.
13499    /// Assembly forms: `ADC WD, WN, WM`; `ADC XD, XN, XM`.
13500    /// Operands: `rd`, `rn`, `rm`.
13501    pub fn adc<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
13502    where
13503        Self: AdcEmitter<T0, T1, T2>,
13504    {
13505        <Self as AdcEmitter<T0, T1, T2>>::adc(self, rd, rn, rm);
13506    }
13507    /// Emits the `ADCS` instruction.
13508    /// Assembly forms: `ADCS WD, WN, WM`; `ADCS XD, XN, XM`.
13509    /// Operands: `rd`, `rn`, `rm`.
13510    pub fn adcs<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
13511    where
13512        Self: AdcsEmitter<T0, T1, T2>,
13513    {
13514        <Self as AdcsEmitter<T0, T1, T2>>::adcs(self, rd, rn, rm);
13515    }
13516    /// Emits the `ADD` instruction.
13517    /// Assembly forms: `ADD WD, WN, WM, {LSL|LSR|ASR #N}`; `ADD XD, XN, XM, {LSL|LSR|ASR #N}`; `ADD WD|WSP, WN|WSP, WM, {EXTEND #N}`; `ADD XD|SP, XN|SP, RM, {EXTEND #N}` (and related forms).
13518    /// Operands: `rd`, `rn`, `rm_or_imm`.
13519    pub fn add<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm_or_imm: T2)
13520    where
13521        Self: AddEmitter<T0, T1, T2>,
13522    {
13523        <Self as AddEmitter<T0, T1, T2>>::add(self, rd, rn, rm_or_imm);
13524    }
13525    /// Emits the `ADD_4` instruction.
13526    /// Assembly forms: `ADD WD, WN, WM, {LSL|LSR|ASR #N}`; `ADD XD, XN, XM, {LSL|LSR|ASR #N}`; `ADD WD|WSP, WN|WSP, WM, {EXTEND #N}`; `ADD XD|SP, XN|SP, RM, {EXTEND #N}` (and related forms).
13527    /// Operands: `rd`, `rn`, `rm_or_imm`, `shift`.
13528    pub fn add_4<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm_or_imm: T2, shift: T3)
13529    where
13530        Self: Add4Emitter<T0, T1, T2, T3>,
13531    {
13532        <Self as Add4Emitter<T0, T1, T2, T3>>::add_4(self, rd, rn, rm_or_imm, shift);
13533    }
13534    /// Emits the `ADDS` instruction.
13535    /// Assembly forms: `ADDS WD, WN, WM, {LSL|LSR|ASR #N}`; `ADDS XD, XN, XM, {LSL|LSR|ASR #N}`; `ADDS WD, WN|WSP, WM, {EXTEND #N}`; `ADDS XD, XN|SP, RM, {EXTEND #N}` (and related forms).
13536    /// Operands: `rd`, `rn`, `rm_or_imm`.
13537    pub fn adds<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm_or_imm: T2)
13538    where
13539        Self: AddsEmitter<T0, T1, T2>,
13540    {
13541        <Self as AddsEmitter<T0, T1, T2>>::adds(self, rd, rn, rm_or_imm);
13542    }
13543    /// Emits the `ADDS_4` instruction.
13544    /// Assembly forms: `ADDS WD, WN, WM, {LSL|LSR|ASR #N}`; `ADDS XD, XN, XM, {LSL|LSR|ASR #N}`; `ADDS WD, WN|WSP, WM, {EXTEND #N}`; `ADDS XD, XN|SP, RM, {EXTEND #N}` (and related forms).
13545    /// Operands: `rd`, `rn`, `rm_or_imm`, `shift`.
13546    pub fn adds_4<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm_or_imm: T2, shift: T3)
13547    where
13548        Self: Adds4Emitter<T0, T1, T2, T3>,
13549    {
13550        <Self as Adds4Emitter<T0, T1, T2, T3>>::adds_4(self, rd, rn, rm_or_imm, shift);
13551    }
13552    /// Emits the `ADR` instruction.
13553    /// Assembly forms: `ADR XD, #RELS`.
13554    /// Operands: `rd`, `target`.
13555    pub fn adr<T0, T1>(&mut self, rd: T0, target: T1)
13556    where
13557        Self: AdrEmitter<T0, T1>,
13558    {
13559        <Self as AdrEmitter<T0, T1>>::adr(self, rd, target);
13560    }
13561    /// Emits the `ADRP` instruction.
13562    /// Assembly forms: `ADRP XD, #RELS`.
13563    /// Operands: `rd`, `target`.
13564    pub fn adrp<T0, T1>(&mut self, rd: T0, target: T1)
13565    where
13566        Self: AdrpEmitter<T0, T1>,
13567    {
13568        <Self as AdrpEmitter<T0, T1>>::adrp(self, rd, target);
13569    }
13570    /// Emits the `AND_` instruction.
13571    /// Assembly forms: `AND WD|WSP, WN, WM, {SOP #N}`; `AND XD|SP, XN, XM, {SOP #N}`; `AND WD|WSP, WN, #IMM`; `AND XD|SP, XN, #IMM` (and related forms).
13572    /// Operands: `rd`, `rn`, `rm_or_imm`.
13573    pub fn and_<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm_or_imm: T2)
13574    where
13575        Self: AndEmitter<T0, T1, T2>,
13576    {
13577        <Self as AndEmitter<T0, T1, T2>>::and_(self, rd, rn, rm_or_imm);
13578    }
13579    /// Emits the `AND__4` instruction.
13580    /// Assembly forms: `AND WD|WSP, WN, WM, {SOP #N}`; `AND XD|SP, XN, XM, {SOP #N}`; `AND WD|WSP, WN, #IMM`; `AND XD|SP, XN, #IMM` (and related forms).
13581    /// Operands: `rd`, `rn`, `rm`, `shift`.
13582    pub fn and__4<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm: T2, shift: T3)
13583    where
13584        Self: And4Emitter<T0, T1, T2, T3>,
13585    {
13586        <Self as And4Emitter<T0, T1, T2, T3>>::and__4(self, rd, rn, rm, shift);
13587    }
13588    /// Emits the `ANDS` instruction.
13589    /// Assembly forms: `ANDS WD|WSP, WN, WM, {SOP #N}`; `ANDS XD|SP, XN, XM, {SOP #N}`; `ANDS WD|WSP, WN, #IMM`; `ANDS XD|SP, XN, #IMM`.
13590    /// Operands: `rd`, `rn`, `rm_or_imm`.
13591    pub fn ands<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm_or_imm: T2)
13592    where
13593        Self: AndsEmitter<T0, T1, T2>,
13594    {
13595        <Self as AndsEmitter<T0, T1, T2>>::ands(self, rd, rn, rm_or_imm);
13596    }
13597    /// Emits the `ANDS_4` instruction.
13598    /// Assembly forms: `ANDS WD|WSP, WN, WM, {SOP #N}`; `ANDS XD|SP, XN, XM, {SOP #N}`; `ANDS WD|WSP, WN, #IMM`; `ANDS XD|SP, XN, #IMM`.
13599    /// Operands: `rd`, `rn`, `rm`, `shift`.
13600    pub fn ands_4<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm: T2, shift: T3)
13601    where
13602        Self: Ands4Emitter<T0, T1, T2, T3>,
13603    {
13604        <Self as Ands4Emitter<T0, T1, T2, T3>>::ands_4(self, rd, rn, rm, shift);
13605    }
13606    /// Emits the `ASR` instruction.
13607    /// Assembly forms: `ASR|ASRV WD, WN, WM`; `ASR|ASRV XD, XN, XM`; `ASR WD, WN, #N`; `ASR XD, XN, #N`.
13608    /// Operands: `rd`, `rn`, `rm_or_shift`.
13609    pub fn asr<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm_or_shift: T2)
13610    where
13611        Self: AsrEmitter<T0, T1, T2>,
13612    {
13613        <Self as AsrEmitter<T0, T1, T2>>::asr(self, rd, rn, rm_or_shift);
13614    }
13615    /// Emits the `ASRV` instruction.
13616    /// Assembly forms: `ASR|ASRV WD, WN, WM`; `ASR|ASRV XD, XN, XM`.
13617    /// Operands: `rd`, `rn`, `rm`.
13618    pub fn asrv<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
13619    where
13620        Self: AsrvEmitter<T0, T1, T2>,
13621    {
13622        <Self as AsrvEmitter<T0, T1, T2>>::asrv(self, rd, rn, rm);
13623    }
13624    /// Emits the `AT` instruction.
13625    /// Assembly forms: `AT #AT_OP, XT`.
13626    /// Operands: `at_op`, `rt`.
13627    pub fn at<T0, T1>(&mut self, at_op: T0, rt: T1)
13628    where
13629        Self: AtEmitter<T0, T1>,
13630    {
13631        <Self as AtEmitter<T0, T1>>::at(self, at_op, rt);
13632    }
13633    /// Emits the `BFC` instruction.
13634    /// Assembly forms: `BFC WD, #LSB, #WIDTH`; `BFC XD, #LSB, #WIDTH`.
13635    /// Operands: `rd`, `lsb`, `width`.
13636    pub fn bfc<T0, T1, T2>(&mut self, rd: T0, lsb: T1, width: T2)
13637    where
13638        Self: BfcEmitter<T0, T1, T2>,
13639    {
13640        <Self as BfcEmitter<T0, T1, T2>>::bfc(self, rd, lsb, width);
13641    }
13642    /// Emits the `BFI` instruction.
13643    /// Assembly forms: `BFI WD, WN, #LSB, #WIDTH`; `BFI XD, XN, #LSB, #WIDTH`.
13644    /// Operands: `rd`, `rn`, `lsb`, `width`.
13645    pub fn bfi<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, lsb: T2, width: T3)
13646    where
13647        Self: BfiEmitter<T0, T1, T2, T3>,
13648    {
13649        <Self as BfiEmitter<T0, T1, T2, T3>>::bfi(self, rd, rn, lsb, width);
13650    }
13651    /// Emits the `BFM` instruction.
13652    /// Assembly forms: `BFM WD, WN, #IMMR, #IMMS`; `BFM XD, XN, #IMMR, #IMMS`.
13653    /// Operands: `rd`, `rn`, `imm`, `imm_2`.
13654    pub fn bfm<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, imm: T2, imm_2: T3)
13655    where
13656        Self: BfmEmitter<T0, T1, T2, T3>,
13657    {
13658        <Self as BfmEmitter<T0, T1, T2, T3>>::bfm(self, rd, rn, imm, imm_2);
13659    }
13660    /// Emits the `BFXIL` instruction.
13661    /// Assembly forms: `BFXIL WD, WN, #LSB, #WIDTH`; `BFXIL XD, XN, #LSB, #WIDTH`.
13662    /// Operands: `rd`, `rn`, `lsb`, `width`.
13663    pub fn bfxil<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, lsb: T2, width: T3)
13664    where
13665        Self: BfxilEmitter<T0, T1, T2, T3>,
13666    {
13667        <Self as BfxilEmitter<T0, T1, T2, T3>>::bfxil(self, rd, rn, lsb, width);
13668    }
13669    /// Emits the `BIC` instruction.
13670    /// Assembly forms: `BIC WD, WN, WM, {SOP #N}`; `BIC XD, XN, XM, {SOP #N}`; `BIC VD.8B, VN.8B, VM.8B`; `BIC VD.16B, VN.16B, VM.16B` (and related forms).
13671    /// Operands: `rd`, `rn_or_imm`, `rm_or_shift`.
13672    pub fn bic<T0, T1, T2>(&mut self, rd: T0, rn_or_imm: T1, rm_or_shift: T2)
13673    where
13674        Self: BicEmitter<T0, T1, T2>,
13675    {
13676        <Self as BicEmitter<T0, T1, T2>>::bic(self, rd, rn_or_imm, rm_or_shift);
13677    }
13678    /// Emits the `BIC_4` instruction.
13679    /// Assembly forms: `BIC WD, WN, WM, {SOP #N}`; `BIC XD, XN, XM, {SOP #N}`; `BIC VD.8B, VN.8B, VM.8B`; `BIC VD.16B, VN.16B, VM.16B` (and related forms).
13680    /// Operands: `rd`, `rn`, `rm`, `shift`.
13681    pub fn bic_4<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm: T2, shift: T3)
13682    where
13683        Self: Bic4Emitter<T0, T1, T2, T3>,
13684    {
13685        <Self as Bic4Emitter<T0, T1, T2, T3>>::bic_4(self, rd, rn, rm, shift);
13686    }
13687    /// Emits the `BICS` instruction.
13688    /// Assembly forms: `BICS WD, WN, WM, {SOP #N}`; `BICS XD, XN, XM, {SOP #N}`.
13689    /// Operands: `rd`, `rn`, `rm`.
13690    pub fn bics<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
13691    where
13692        Self: BicsEmitter<T0, T1, T2>,
13693    {
13694        <Self as BicsEmitter<T0, T1, T2>>::bics(self, rd, rn, rm);
13695    }
13696    /// Emits the `BICS_4` instruction.
13697    /// Assembly forms: `BICS WD, WN, WM, {SOP #N}`; `BICS XD, XN, XM, {SOP #N}`.
13698    /// Operands: `rd`, `rn`, `rm`, `shift`.
13699    pub fn bics_4<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm: T2, shift: T3)
13700    where
13701        Self: Bics4Emitter<T0, T1, T2, T3>,
13702    {
13703        <Self as Bics4Emitter<T0, T1, T2, T3>>::bics_4(self, rd, rn, rm, shift);
13704    }
13705    /// Emits the `BRK` instruction.
13706    /// Assembly forms: `BRK #IMM`.
13707    /// Operands: `imm`.
13708    pub fn brk<T0>(&mut self, imm: T0)
13709    where
13710        Self: BrkEmitter<T0>,
13711    {
13712        <Self as BrkEmitter<T0>>::brk(self, imm);
13713    }
13714    /// Emits the `CCMN` instruction.
13715    /// Assembly forms: `CCMN WN, WM, #NZCV, #COND`; `CCMN XN, XM, #NZCV, #COND`; `CCMN WN, #IMM, #NZCV, #COND`; `CCMN XN, #IMM, #NZCV, #COND`.
13716    /// Operands: `rn`, `rm_or_imm`, `flags`, `condition`.
13717    pub fn ccmn<T0, T1, T2, T3>(&mut self, rn: T0, rm_or_imm: T1, flags: T2, condition: T3)
13718    where
13719        Self: CcmnEmitter<T0, T1, T2, T3>,
13720    {
13721        <Self as CcmnEmitter<T0, T1, T2, T3>>::ccmn(self, rn, rm_or_imm, flags, condition);
13722    }
13723    /// Emits the `CCMP` instruction.
13724    /// Assembly forms: `CCMP WN, WM, #NZCV, #COND`; `CCMP XN, XM, #NZCV, #COND`; `CCMP WN, #IMM, #NZCV, #COND`; `CCMP XN, #IMM, #NZCV, #COND`.
13725    /// Operands: `rn`, `rm_or_imm`, `flags`, `condition`.
13726    pub fn ccmp<T0, T1, T2, T3>(&mut self, rn: T0, rm_or_imm: T1, flags: T2, condition: T3)
13727    where
13728        Self: CcmpEmitter<T0, T1, T2, T3>,
13729    {
13730        <Self as CcmpEmitter<T0, T1, T2, T3>>::ccmp(self, rn, rm_or_imm, flags, condition);
13731    }
13732    /// Emits the `CINC` instruction.
13733    /// Assembly forms: `CINC WD, WN, #COND`; `CINC XD, XN, #COND`.
13734    /// Operands: `rd`, `rn`, `condition`.
13735    pub fn cinc<T0, T1, T2>(&mut self, rd: T0, rn: T1, condition: T2)
13736    where
13737        Self: CincEmitter<T0, T1, T2>,
13738    {
13739        <Self as CincEmitter<T0, T1, T2>>::cinc(self, rd, rn, condition);
13740    }
13741    /// Emits the `CINV` instruction.
13742    /// Assembly forms: `CINV WD, WN, #COND`; `CINV XD, XN, #COND`.
13743    /// Operands: `rd`, `rn`, `condition`.
13744    pub fn cinv<T0, T1, T2>(&mut self, rd: T0, rn: T1, condition: T2)
13745    where
13746        Self: CinvEmitter<T0, T1, T2>,
13747    {
13748        <Self as CinvEmitter<T0, T1, T2>>::cinv(self, rd, rn, condition);
13749    }
13750    /// Emits the `CLREX` instruction.
13751    /// Assembly forms: `CLREX {#IMM=15}`.
13752    /// Operands: `imm`.
13753    pub fn clrex<T0>(&mut self, imm: T0)
13754    where
13755        Self: ClrexEmitter<T0>,
13756    {
13757        <Self as ClrexEmitter<T0>>::clrex(self, imm);
13758    }
13759    /// Emits the `CLS` instruction.
13760    /// Assembly forms: `CLS WD, WN`; `CLS XD, XN`; `CLS VD.T, VN.T`; `CLS VD.T, VN.T`.
13761    /// Operands: `rd`, `rn`.
13762    pub fn cls<T0, T1>(&mut self, rd: T0, rn: T1)
13763    where
13764        Self: ClsEmitter<T0, T1>,
13765    {
13766        <Self as ClsEmitter<T0, T1>>::cls(self, rd, rn);
13767    }
13768    /// Emits the `CLZ` instruction.
13769    /// Assembly forms: `CLZ WD, WN`; `CLZ XD, XN`; `CLZ VD.T, VN.T`; `CLZ VD.T, VN.T`.
13770    /// Operands: `rd`, `rn`.
13771    pub fn clz<T0, T1>(&mut self, rd: T0, rn: T1)
13772    where
13773        Self: ClzEmitter<T0, T1>,
13774    {
13775        <Self as ClzEmitter<T0, T1>>::clz(self, rd, rn);
13776    }
13777    /// Emits the `CMN` instruction.
13778    /// Assembly forms: `CMN WN|WSP, #IMM, {LSL #N=0|12}`; `CMN XN|SP, #IMM, {LSL #N=0|12}`; `CMN WN|WSP, WM, {EXTEND #N}`; `CMN XN|SP, RM, {EXTEND #N}` (and related forms).
13779    /// Operands: `rn`, `imm_or_rm`.
13780    pub fn cmn<T0, T1>(&mut self, rn: T0, imm_or_rm: T1)
13781    where
13782        Self: CmnEmitter<T0, T1>,
13783    {
13784        <Self as CmnEmitter<T0, T1>>::cmn(self, rn, imm_or_rm);
13785    }
13786    /// Emits the `CMN_3` instruction.
13787    /// Assembly forms: `CMN WN|WSP, #IMM, {LSL #N=0|12}`; `CMN XN|SP, #IMM, {LSL #N=0|12}`; `CMN WN|WSP, WM, {EXTEND #N}`; `CMN XN|SP, RM, {EXTEND #N}` (and related forms).
13788    /// Operands: `rn`, `imm_or_rm`, `shift`.
13789    pub fn cmn_3<T0, T1, T2>(&mut self, rn: T0, imm_or_rm: T1, shift: T2)
13790    where
13791        Self: Cmn3Emitter<T0, T1, T2>,
13792    {
13793        <Self as Cmn3Emitter<T0, T1, T2>>::cmn_3(self, rn, imm_or_rm, shift);
13794    }
13795    /// Emits the `CMP` instruction.
13796    /// Assembly forms: `CMP WN, WM, {LSL|LSR|ASR #N}`; `CMP XN, XM, {LSL|LSR|ASR #N}`; `CMP WN|WSP, WM, {EXTEND #N}`; `CMP XN|SP, RM, {EXTEND #N}` (and related forms).
13797    /// Operands: `rn`, `rm_or_imm`.
13798    pub fn cmp<T0, T1>(&mut self, rn: T0, rm_or_imm: T1)
13799    where
13800        Self: CmpEmitter<T0, T1>,
13801    {
13802        <Self as CmpEmitter<T0, T1>>::cmp(self, rn, rm_or_imm);
13803    }
13804    /// Emits the `CMP_3` instruction.
13805    /// Assembly forms: `CMP WN, WM, {LSL|LSR|ASR #N}`; `CMP XN, XM, {LSL|LSR|ASR #N}`; `CMP WN|WSP, WM, {EXTEND #N}`; `CMP XN|SP, RM, {EXTEND #N}` (and related forms).
13806    /// Operands: `rn`, `rm_or_imm`, `shift`.
13807    pub fn cmp_3<T0, T1, T2>(&mut self, rn: T0, rm_or_imm: T1, shift: T2)
13808    where
13809        Self: Cmp3Emitter<T0, T1, T2>,
13810    {
13811        <Self as Cmp3Emitter<T0, T1, T2>>::cmp_3(self, rn, rm_or_imm, shift);
13812    }
13813    /// Emits the `CNEG` instruction.
13814    /// Assembly forms: `CNEG WD, WN, #COND`; `CNEG XD, XN, #COND`.
13815    /// Operands: `rd`, `rn`, `condition`.
13816    pub fn cneg<T0, T1, T2>(&mut self, rd: T0, rn: T1, condition: T2)
13817    where
13818        Self: CnegEmitter<T0, T1, T2>,
13819    {
13820        <Self as CnegEmitter<T0, T1, T2>>::cneg(self, rd, rn, condition);
13821    }
13822    /// Emits the `CSEL` instruction.
13823    /// Assembly forms: `CSEL WD, WN, WM, #COND`; `CSEL XD, XN, XM, #COND`.
13824    /// Operands: `rd`, `rn`, `rm`, `condition`.
13825    pub fn csel<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm: T2, condition: T3)
13826    where
13827        Self: CselEmitter<T0, T1, T2, T3>,
13828    {
13829        <Self as CselEmitter<T0, T1, T2, T3>>::csel(self, rd, rn, rm, condition);
13830    }
13831    /// Emits the `CSET` instruction.
13832    /// Assembly forms: `CSET WD, #COND`; `CSET XD, #COND`.
13833    /// Operands: `rd`, `condition`.
13834    pub fn cset<T0, T1>(&mut self, rd: T0, condition: T1)
13835    where
13836        Self: CsetEmitter<T0, T1>,
13837    {
13838        <Self as CsetEmitter<T0, T1>>::cset(self, rd, condition);
13839    }
13840    /// Emits the `CSETM` instruction.
13841    /// Assembly forms: `CSETM WD, #COND`; `CSETM XD, #COND`.
13842    /// Operands: `rd`, `condition`.
13843    pub fn csetm<T0, T1>(&mut self, rd: T0, condition: T1)
13844    where
13845        Self: CsetmEmitter<T0, T1>,
13846    {
13847        <Self as CsetmEmitter<T0, T1>>::csetm(self, rd, condition);
13848    }
13849    /// Emits the `CSINC` instruction.
13850    /// Assembly forms: `CSINC WD, WN, WM, #COND`; `CSINC XD, XN, XM, #COND`.
13851    /// Operands: `rd`, `rn`, `rm`, `condition`.
13852    pub fn csinc<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm: T2, condition: T3)
13853    where
13854        Self: CsincEmitter<T0, T1, T2, T3>,
13855    {
13856        <Self as CsincEmitter<T0, T1, T2, T3>>::csinc(self, rd, rn, rm, condition);
13857    }
13858    /// Emits the `CSINV` instruction.
13859    /// Assembly forms: `CSINV WD, WN, WM, #COND`; `CSINV XD, XN, XM, #COND`.
13860    /// Operands: `rd`, `rn`, `rm`, `condition`.
13861    pub fn csinv<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm: T2, condition: T3)
13862    where
13863        Self: CsinvEmitter<T0, T1, T2, T3>,
13864    {
13865        <Self as CsinvEmitter<T0, T1, T2, T3>>::csinv(self, rd, rn, rm, condition);
13866    }
13867    /// Emits the `CSNEG` instruction.
13868    /// Assembly forms: `CSNEG WD, WN, WM, #COND`; `CSNEG XD, XN, XM, #COND`.
13869    /// Operands: `rd`, `rn`, `rm`, `condition`.
13870    pub fn csneg<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm: T2, condition: T3)
13871    where
13872        Self: CsnegEmitter<T0, T1, T2, T3>,
13873    {
13874        <Self as CsnegEmitter<T0, T1, T2, T3>>::csneg(self, rd, rn, rm, condition);
13875    }
13876    /// Emits the `DC` instruction.
13877    /// Assembly forms: `DC #DC_OP, XT`.
13878    /// Operands: `dc_op`, `rt`.
13879    pub fn dc<T0, T1>(&mut self, dc_op: T0, rt: T1)
13880    where
13881        Self: DcEmitter<T0, T1>,
13882    {
13883        <Self as DcEmitter<T0, T1>>::dc(self, dc_op, rt);
13884    }
13885    /// Emits the `DMB` instruction.
13886    /// Assembly forms: `DMB #BARRIER_OP`.
13887    /// Operands: `barrier_op`.
13888    pub fn dmb<T0>(&mut self, barrier_op: T0)
13889    where
13890        Self: DmbEmitter<T0>,
13891    {
13892        <Self as DmbEmitter<T0>>::dmb(self, barrier_op);
13893    }
13894    /// Emits the `DSB` instruction.
13895    /// Assembly forms: `DSB #BARRIER_OP`.
13896    /// Operands: `barrier_op`.
13897    pub fn dsb<T0>(&mut self, barrier_op: T0)
13898    where
13899        Self: DsbEmitter<T0>,
13900    {
13901        <Self as DsbEmitter<T0>>::dsb(self, barrier_op);
13902    }
13903    /// Emits the `DRPS` instruction.
13904    /// Assembly forms: `DRPS`.
13905    pub fn drps(&mut self)
13906    where
13907        Self: DrpsEmitter,
13908    {
13909        <Self as DrpsEmitter>::drps(self);
13910    }
13911    /// Emits the `EON` instruction.
13912    /// Assembly forms: `EON WD, WN, WM, {SOP #N}`; `EON XD, XN, XM, {SOP #N}`.
13913    /// Operands: `rd`, `rn`, `rm`.
13914    pub fn eon<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
13915    where
13916        Self: EonEmitter<T0, T1, T2>,
13917    {
13918        <Self as EonEmitter<T0, T1, T2>>::eon(self, rd, rn, rm);
13919    }
13920    /// Emits the `EON_4` instruction.
13921    /// Assembly forms: `EON WD, WN, WM, {SOP #N}`; `EON XD, XN, XM, {SOP #N}`.
13922    /// Operands: `rd`, `rn`, `rm`, `shift`.
13923    pub fn eon_4<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm: T2, shift: T3)
13924    where
13925        Self: Eon4Emitter<T0, T1, T2, T3>,
13926    {
13927        <Self as Eon4Emitter<T0, T1, T2, T3>>::eon_4(self, rd, rn, rm, shift);
13928    }
13929    /// Emits the `EOR` instruction.
13930    /// Assembly forms: `EOR WD, WN, WM, {SOP #N}`; `EOR XD, XN, XM, {SOP #N}`; `EOR WD|WSP, WN, #IMM`; `EOR XD|SP, XN, #IMM` (and related forms).
13931    /// Operands: `rd`, `rn`, `rm_or_imm`.
13932    pub fn eor<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm_or_imm: T2)
13933    where
13934        Self: EorEmitter<T0, T1, T2>,
13935    {
13936        <Self as EorEmitter<T0, T1, T2>>::eor(self, rd, rn, rm_or_imm);
13937    }
13938    /// Emits the `EOR_4` instruction.
13939    /// Assembly forms: `EOR WD, WN, WM, {SOP #N}`; `EOR XD, XN, XM, {SOP #N}`; `EOR WD|WSP, WN, #IMM`; `EOR XD|SP, XN, #IMM` (and related forms).
13940    /// Operands: `rd`, `rn`, `rm`, `shift`.
13941    pub fn eor_4<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm: T2, shift: T3)
13942    where
13943        Self: Eor4Emitter<T0, T1, T2, T3>,
13944    {
13945        <Self as Eor4Emitter<T0, T1, T2, T3>>::eor_4(self, rd, rn, rm, shift);
13946    }
13947    /// Emits the `ERET` instruction.
13948    /// Assembly forms: `ERET`.
13949    pub fn eret(&mut self)
13950    where
13951        Self: EretEmitter,
13952    {
13953        <Self as EretEmitter>::eret(self);
13954    }
13955    /// Emits the `ESB` instruction.
13956    /// Assembly forms: `ESB`.
13957    pub fn esb(&mut self)
13958    where
13959        Self: EsbEmitter,
13960    {
13961        <Self as EsbEmitter>::esb(self);
13962    }
13963    /// Emits the `EXTR` instruction.
13964    /// Assembly forms: `EXTR WD, WN, WM, #IMM`; `EXTR XD, XN, XM, #IMM`.
13965    /// Operands: `rd`, `rn`, `rm`, `imm`.
13966    pub fn extr<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm: T2, imm: T3)
13967    where
13968        Self: ExtrEmitter<T0, T1, T2, T3>,
13969    {
13970        <Self as ExtrEmitter<T0, T1, T2, T3>>::extr(self, rd, rn, rm, imm);
13971    }
13972    /// Emits the `HLT` instruction.
13973    /// Assembly forms: `HLT #IMM`.
13974    /// Operands: `imm`.
13975    pub fn hlt<T0>(&mut self, imm: T0)
13976    where
13977        Self: HltEmitter<T0>,
13978    {
13979        <Self as HltEmitter<T0>>::hlt(self, imm);
13980    }
13981    /// Emits the `HVC` instruction.
13982    /// Assembly forms: `HVC #IMM`.
13983    /// Operands: `imm`.
13984    pub fn hvc<T0>(&mut self, imm: T0)
13985    where
13986        Self: HvcEmitter<T0>,
13987    {
13988        <Self as HvcEmitter<T0>>::hvc(self, imm);
13989    }
13990    /// Emits the `IC` instruction.
13991    /// Assembly forms: `IC #IC_OP`; `IC #IC_OP, XT`.
13992    /// Operands: `ic_op`, `rt`.
13993    pub fn ic<T0, T1>(&mut self, ic_op: T0, rt: T1)
13994    where
13995        Self: IcEmitter<T0, T1>,
13996    {
13997        <Self as IcEmitter<T0, T1>>::ic(self, ic_op, rt);
13998    }
13999    /// Emits the `ISB` instruction.
14000    /// Assembly forms: `ISB {#ISB_OP=15}`.
14001    /// Operands: `isb_op`.
14002    pub fn isb<T0>(&mut self, isb_op: T0)
14003    where
14004        Self: IsbEmitter<T0>,
14005    {
14006        <Self as IsbEmitter<T0>>::isb(self, isb_op);
14007    }
14008    /// Emits the `LSL` instruction.
14009    /// Assembly forms: `LSL|LSLV WD, WN, WM`; `LSL|LSLV XD, XN, XM`; `LSL WD, WN, #N`; `LSL XD, XN, #N`.
14010    /// Operands: `rd`, `rn`, `rm_or_shift`.
14011    pub fn lsl<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm_or_shift: T2)
14012    where
14013        Self: LslEmitter<T0, T1, T2>,
14014    {
14015        <Self as LslEmitter<T0, T1, T2>>::lsl(self, rd, rn, rm_or_shift);
14016    }
14017    /// Emits the `LSLV` instruction.
14018    /// Assembly forms: `LSL|LSLV WD, WN, WM`; `LSL|LSLV XD, XN, XM`.
14019    /// Operands: `rd`, `rn`, `rm`.
14020    pub fn lslv<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
14021    where
14022        Self: LslvEmitter<T0, T1, T2>,
14023    {
14024        <Self as LslvEmitter<T0, T1, T2>>::lslv(self, rd, rn, rm);
14025    }
14026    /// Emits the `LSR` instruction.
14027    /// Assembly forms: `LSR|LSRV WD, WN, WM`; `LSR|LSRV XD, XN, XM`; `LSR WD, WN, #N`; `LSR XD, XN, #N`.
14028    /// Operands: `rd`, `rn`, `rm_or_shift`.
14029    pub fn lsr<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm_or_shift: T2)
14030    where
14031        Self: LsrEmitter<T0, T1, T2>,
14032    {
14033        <Self as LsrEmitter<T0, T1, T2>>::lsr(self, rd, rn, rm_or_shift);
14034    }
14035    /// Emits the `LSRV` instruction.
14036    /// Assembly forms: `LSR|LSRV WD, WN, WM`; `LSR|LSRV XD, XN, XM`.
14037    /// Operands: `rd`, `rn`, `rm`.
14038    pub fn lsrv<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
14039    where
14040        Self: LsrvEmitter<T0, T1, T2>,
14041    {
14042        <Self as LsrvEmitter<T0, T1, T2>>::lsrv(self, rd, rn, rm);
14043    }
14044    /// Emits the `MADD` instruction.
14045    /// Assembly forms: `MADD WD, WN, WM, WA`; `MADD XD, XN, XM, XA`.
14046    /// Operands: `rd`, `rn`, `rm`, `operand_4`.
14047    pub fn madd<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm: T2, operand_4: T3)
14048    where
14049        Self: MaddEmitter<T0, T1, T2, T3>,
14050    {
14051        <Self as MaddEmitter<T0, T1, T2, T3>>::madd(self, rd, rn, rm, operand_4);
14052    }
14053    /// Emits the `MNEG` instruction.
14054    /// Assembly forms: `MNEG WD, WN, WM`; `MNEG XD, XN, XM`.
14055    /// Operands: `rd`, `rn`, `rm`.
14056    pub fn mneg<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
14057    where
14058        Self: MnegEmitter<T0, T1, T2>,
14059    {
14060        <Self as MnegEmitter<T0, T1, T2>>::mneg(self, rd, rn, rm);
14061    }
14062    /// Emits the `MOV` instruction.
14063    /// Assembly forms: `MOV WD, WM`; `MOV XD, XM`; `MOV WD|WSP, WN|WSP`; `MOV XD|SP, XN|SP` (and related forms).
14064    /// Operands: `rd`, `rm_or_rn_or_imm_or_log_imm`.
14065    pub fn mov<T0, T1>(&mut self, rd: T0, rm_or_rn_or_imm_or_log_imm: T1)
14066    where
14067        Self: MovEmitter<T0, T1>,
14068    {
14069        <Self as MovEmitter<T0, T1>>::mov(self, rd, rm_or_rn_or_imm_or_log_imm);
14070    }
14071    /// Emits the `MOVK` instruction.
14072    /// Assembly forms: `MOVK WD, #IMM, {LSL #N}`; `MOVK XD, #IMM, {LSL #N}`.
14073    /// Operands: `rd`, `imm`.
14074    pub fn movk<T0, T1>(&mut self, rd: T0, imm: T1)
14075    where
14076        Self: MovkEmitter<T0, T1>,
14077    {
14078        <Self as MovkEmitter<T0, T1>>::movk(self, rd, imm);
14079    }
14080    /// Emits the `MOVK_3` instruction.
14081    /// Assembly forms: `MOVK WD, #IMM, {LSL #N}`; `MOVK XD, #IMM, {LSL #N}`.
14082    /// Operands: `rd`, `imm`, `shift`.
14083    pub fn movk_3<T0, T1, T2>(&mut self, rd: T0, imm: T1, shift: T2)
14084    where
14085        Self: Movk3Emitter<T0, T1, T2>,
14086    {
14087        <Self as Movk3Emitter<T0, T1, T2>>::movk_3(self, rd, imm, shift);
14088    }
14089    /// Emits the `MOVN` instruction.
14090    /// Assembly forms: `MOVN WD, #IMM, {LSL #N}`; `MOVN XD, #IMM, {LSL #N}`.
14091    /// Operands: `rd`, `imm`.
14092    pub fn movn<T0, T1>(&mut self, rd: T0, imm: T1)
14093    where
14094        Self: MovnEmitter<T0, T1>,
14095    {
14096        <Self as MovnEmitter<T0, T1>>::movn(self, rd, imm);
14097    }
14098    /// Emits the `MOVN_3` instruction.
14099    /// Assembly forms: `MOVN WD, #IMM, {LSL #N}`; `MOVN XD, #IMM, {LSL #N}`.
14100    /// Operands: `rd`, `imm`, `shift`.
14101    pub fn movn_3<T0, T1, T2>(&mut self, rd: T0, imm: T1, shift: T2)
14102    where
14103        Self: Movn3Emitter<T0, T1, T2>,
14104    {
14105        <Self as Movn3Emitter<T0, T1, T2>>::movn_3(self, rd, imm, shift);
14106    }
14107    /// Emits the `MOVZ` instruction.
14108    /// Assembly forms: `MOVZ WD, #IMM, {LSL #N}`; `MOVZ XD, #IMM, {LSL #N}`.
14109    /// Operands: `rd`, `imm`.
14110    pub fn movz<T0, T1>(&mut self, rd: T0, imm: T1)
14111    where
14112        Self: MovzEmitter<T0, T1>,
14113    {
14114        <Self as MovzEmitter<T0, T1>>::movz(self, rd, imm);
14115    }
14116    /// Emits the `MOVZ_3` instruction.
14117    /// Assembly forms: `MOVZ WD, #IMM, {LSL #N}`; `MOVZ XD, #IMM, {LSL #N}`.
14118    /// Operands: `rd`, `imm`, `shift`.
14119    pub fn movz_3<T0, T1, T2>(&mut self, rd: T0, imm: T1, shift: T2)
14120    where
14121        Self: Movz3Emitter<T0, T1, T2>,
14122    {
14123        <Self as Movz3Emitter<T0, T1, T2>>::movz_3(self, rd, imm, shift);
14124    }
14125    /// Emits the `MRS` instruction.
14126    /// Assembly forms: `MRS XD, #SYSREG`.
14127    /// Operands: `rd`, `sysreg`.
14128    pub fn mrs<T0, T1>(&mut self, rd: T0, sysreg: T1)
14129    where
14130        Self: MrsEmitter<T0, T1>,
14131    {
14132        <Self as MrsEmitter<T0, T1>>::mrs(self, rd, sysreg);
14133    }
14134    /// Emits the `MSR` instruction.
14135    /// Assembly forms: `MSR #SYSREG, XS`; `MSR #PSTATEFIELD, #IMM`.
14136    /// Operands: `sysreg_or_pstatefield`, `rs_or_imm`.
14137    pub fn msr<T0, T1>(&mut self, sysreg_or_pstatefield: T0, rs_or_imm: T1)
14138    where
14139        Self: MsrEmitter<T0, T1>,
14140    {
14141        <Self as MsrEmitter<T0, T1>>::msr(self, sysreg_or_pstatefield, rs_or_imm);
14142    }
14143    /// Emits the `MSUB` instruction.
14144    /// Assembly forms: `MSUB WD, WN, WM, WA`; `MSUB XD, XN, XM, XA`.
14145    /// Operands: `rd`, `rn`, `rm`, `operand_4`.
14146    pub fn msub<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm: T2, operand_4: T3)
14147    where
14148        Self: MsubEmitter<T0, T1, T2, T3>,
14149    {
14150        <Self as MsubEmitter<T0, T1, T2, T3>>::msub(self, rd, rn, rm, operand_4);
14151    }
14152    /// Emits the `MUL` instruction.
14153    /// Assembly forms: `MUL WD, WN, WM`; `MUL XD, XN, XM`; `MUL VD.T, VN.T, VM.T`; `MUL VD.T, VN.T, VM.T` (and related forms).
14154    /// Operands: `rd`, `rn`, `rm`.
14155    pub fn mul<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
14156    where
14157        Self: MulEmitter<T0, T1, T2>,
14158    {
14159        <Self as MulEmitter<T0, T1, T2>>::mul(self, rd, rn, rm);
14160    }
14161    /// Emits the `MVN` instruction.
14162    /// Assembly forms: `MVN WD, WN, {SOP #N}`; `MVN XD, XN, {SOP #N}`; `NOT|MVN VD.8B, VN.8B`; `NOT|MVN VD.16B, VN.16B`.
14163    /// Operands: `rd`, `rn`.
14164    pub fn mvn<T0, T1>(&mut self, rd: T0, rn: T1)
14165    where
14166        Self: MvnEmitter<T0, T1>,
14167    {
14168        <Self as MvnEmitter<T0, T1>>::mvn(self, rd, rn);
14169    }
14170    /// Emits the `MVN_3` instruction.
14171    /// Assembly forms: `MVN WD, WN, {SOP #N}`; `MVN XD, XN, {SOP #N}`; `NOT|MVN VD.8B, VN.8B`; `NOT|MVN VD.16B, VN.16B`.
14172    /// Operands: `rd`, `rn`, `shift`.
14173    pub fn mvn_3<T0, T1, T2>(&mut self, rd: T0, rn: T1, shift: T2)
14174    where
14175        Self: Mvn3Emitter<T0, T1, T2>,
14176    {
14177        <Self as Mvn3Emitter<T0, T1, T2>>::mvn_3(self, rd, rn, shift);
14178    }
14179    /// Emits the `MVN_` instruction.
14180    /// Assembly forms: `MVN WD, WN, {SOP #N}`; `MVN XD, XN, {SOP #N}`; `NOT|MVN VD.8B, VN.8B`; `NOT|MVN VD.16B, VN.16B`.
14181    /// Operands: `rd`, `rn`.
14182    pub fn mvn_<T0, T1>(&mut self, rd: T0, rn: T1)
14183    where
14184        Self: Mvn_Emitter<T0, T1>,
14185    {
14186        <Self as Mvn_Emitter<T0, T1>>::mvn_(self, rd, rn);
14187    }
14188    /// Emits the `MVN__3` instruction.
14189    /// Assembly forms: `MVN WD, WN, {SOP #N}`; `MVN XD, XN, {SOP #N}`; `NOT|MVN VD.8B, VN.8B`; `NOT|MVN VD.16B, VN.16B`.
14190    /// Operands: `rd`, `rn`, `shift`.
14191    pub fn mvn__3<T0, T1, T2>(&mut self, rd: T0, rn: T1, shift: T2)
14192    where
14193        Self: Mvn_3Emitter<T0, T1, T2>,
14194    {
14195        <Self as Mvn_3Emitter<T0, T1, T2>>::mvn__3(self, rd, rn, shift);
14196    }
14197    /// Emits the `NEG` instruction.
14198    /// Assembly forms: `NEG WD, WM, {LSL|LSR|ASR #N}`; `NEG XD, XM, {LSL|LSR|ASR #N}`; `NEG DD, DN`; `NEG VD.T, VN.T` (and related forms).
14199    /// Operands: `rd`, `rm_or_rn`.
14200    pub fn neg<T0, T1>(&mut self, rd: T0, rm_or_rn: T1)
14201    where
14202        Self: NegEmitter<T0, T1>,
14203    {
14204        <Self as NegEmitter<T0, T1>>::neg(self, rd, rm_or_rn);
14205    }
14206    /// Emits the `NEG_3` instruction.
14207    /// Assembly forms: `NEG WD, WM, {LSL|LSR|ASR #N}`; `NEG XD, XM, {LSL|LSR|ASR #N}`; `NEG DD, DN`; `NEG VD.T, VN.T` (and related forms).
14208    /// Operands: `rd`, `rm`, `shift`.
14209    pub fn neg_3<T0, T1, T2>(&mut self, rd: T0, rm: T1, shift: T2)
14210    where
14211        Self: Neg3Emitter<T0, T1, T2>,
14212    {
14213        <Self as Neg3Emitter<T0, T1, T2>>::neg_3(self, rd, rm, shift);
14214    }
14215    /// Emits the `NEGS` instruction.
14216    /// Assembly forms: `NEGS WD, WM, {LSL|LSR|ASR #N}`; `NEGS XD, XM, {LSL|LSR|ASR #N}`.
14217    /// Operands: `rd`, `rm`.
14218    pub fn negs<T0, T1>(&mut self, rd: T0, rm: T1)
14219    where
14220        Self: NegsEmitter<T0, T1>,
14221    {
14222        <Self as NegsEmitter<T0, T1>>::negs(self, rd, rm);
14223    }
14224    /// Emits the `NEGS_3` instruction.
14225    /// Assembly forms: `NEGS WD, WM, {LSL|LSR|ASR #N}`; `NEGS XD, XM, {LSL|LSR|ASR #N}`.
14226    /// Operands: `rd`, `rm`, `shift`.
14227    pub fn negs_3<T0, T1, T2>(&mut self, rd: T0, rm: T1, shift: T2)
14228    where
14229        Self: Negs3Emitter<T0, T1, T2>,
14230    {
14231        <Self as Negs3Emitter<T0, T1, T2>>::negs_3(self, rd, rm, shift);
14232    }
14233    /// Emits the `NGC` instruction.
14234    /// Assembly forms: `NGC WD, WM`; `NGC XD, XM`.
14235    /// Operands: `rd`, `rm`.
14236    pub fn ngc<T0, T1>(&mut self, rd: T0, rm: T1)
14237    where
14238        Self: NgcEmitter<T0, T1>,
14239    {
14240        <Self as NgcEmitter<T0, T1>>::ngc(self, rd, rm);
14241    }
14242    /// Emits the `NGCS` instruction.
14243    /// Assembly forms: `NGCS WD, WM`; `NGCS XD, XM`.
14244    /// Operands: `rd`, `rm`.
14245    pub fn ngcs<T0, T1>(&mut self, rd: T0, rm: T1)
14246    where
14247        Self: NgcsEmitter<T0, T1>,
14248    {
14249        <Self as NgcsEmitter<T0, T1>>::ngcs(self, rd, rm);
14250    }
14251    /// Emits the `ORN` instruction.
14252    /// Assembly forms: `ORN WD, WN, WM, {SOP #N}`; `ORN XD, XN, XM, {SOP #N}`; `ORN VD.8B, VN.8B, VM.8B`; `ORN VD.16B, VN.16B, VM.16B`.
14253    /// Operands: `rd`, `rn`, `rm`.
14254    pub fn orn<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
14255    where
14256        Self: OrnEmitter<T0, T1, T2>,
14257    {
14258        <Self as OrnEmitter<T0, T1, T2>>::orn(self, rd, rn, rm);
14259    }
14260    /// Emits the `ORN_4` instruction.
14261    /// Assembly forms: `ORN WD, WN, WM, {SOP #N}`; `ORN XD, XN, XM, {SOP #N}`; `ORN VD.8B, VN.8B, VM.8B`; `ORN VD.16B, VN.16B, VM.16B`.
14262    /// Operands: `rd`, `rn`, `rm`, `shift`.
14263    pub fn orn_4<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm: T2, shift: T3)
14264    where
14265        Self: Orn4Emitter<T0, T1, T2, T3>,
14266    {
14267        <Self as Orn4Emitter<T0, T1, T2, T3>>::orn_4(self, rd, rn, rm, shift);
14268    }
14269    /// Emits the `ORR` instruction.
14270    /// Assembly forms: `ORR WD, WN, WM, {SOP #N}`; `ORR XD, XN, XM, {SOP #N}`; `ORR WD|WSP, WN, #LOG_IMM`; `ORR XD|SP, XN, #LOG_IMM` (and related forms).
14271    /// Operands: `rd`, `rn_or_imm`, `rm_or_log_imm_or_shift`.
14272    pub fn orr<T0, T1, T2>(&mut self, rd: T0, rn_or_imm: T1, rm_or_log_imm_or_shift: T2)
14273    where
14274        Self: OrrEmitter<T0, T1, T2>,
14275    {
14276        <Self as OrrEmitter<T0, T1, T2>>::orr(self, rd, rn_or_imm, rm_or_log_imm_or_shift);
14277    }
14278    /// Emits the `ORR_4` instruction.
14279    /// Assembly forms: `ORR WD, WN, WM, {SOP #N}`; `ORR XD, XN, XM, {SOP #N}`; `ORR WD|WSP, WN, #LOG_IMM`; `ORR XD|SP, XN, #LOG_IMM` (and related forms).
14280    /// Operands: `rd`, `rn`, `rm`, `shift`.
14281    pub fn orr_4<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm: T2, shift: T3)
14282    where
14283        Self: Orr4Emitter<T0, T1, T2, T3>,
14284    {
14285        <Self as Orr4Emitter<T0, T1, T2, T3>>::orr_4(self, rd, rn, rm, shift);
14286    }
14287    /// Emits the `RBIT` instruction.
14288    /// Assembly forms: `RBIT WD, WN`; `RBIT XD, XN`; `RBIT VD.8B, VN.8B`; `RBIT VD.16B, VN.16B`.
14289    /// Operands: `rd`, `rn`.
14290    pub fn rbit<T0, T1>(&mut self, rd: T0, rn: T1)
14291    where
14292        Self: RbitEmitter<T0, T1>,
14293    {
14294        <Self as RbitEmitter<T0, T1>>::rbit(self, rd, rn);
14295    }
14296    /// Emits the `RET` instruction.
14297    /// Assembly forms: `RET XN`.
14298    /// Operands: `rn`.
14299    pub fn ret<T0>(&mut self, rn: T0)
14300    where
14301        Self: RetEmitter<T0>,
14302    {
14303        <Self as RetEmitter<T0>>::ret(self, rn);
14304    }
14305    /// Emits the `REV` instruction.
14306    /// Assembly forms: `REV WD, WN`; `REV|REV64 XD, XN`.
14307    /// Operands: `rd`, `rn`.
14308    pub fn rev<T0, T1>(&mut self, rd: T0, rn: T1)
14309    where
14310        Self: RevEmitter<T0, T1>,
14311    {
14312        <Self as RevEmitter<T0, T1>>::rev(self, rd, rn);
14313    }
14314    /// Emits the `REV16` instruction.
14315    /// Assembly forms: `REV16 WD, WN`; `REV16 XD, XN`; `REV16 VD.8B, VN.8B`; `REV16 VD.16B, VN.16B`.
14316    /// Operands: `rd`, `rn`.
14317    pub fn rev16<T0, T1>(&mut self, rd: T0, rn: T1)
14318    where
14319        Self: Rev16Emitter<T0, T1>,
14320    {
14321        <Self as Rev16Emitter<T0, T1>>::rev16(self, rd, rn);
14322    }
14323    /// Emits the `REV32` instruction.
14324    /// Assembly forms: `REV32 XD, XN`; `REV32 VD.T, VN.T`; `REV32 VD.T, VN.T`.
14325    /// Operands: `rd`, `rn`.
14326    pub fn rev32<T0, T1>(&mut self, rd: T0, rn: T1)
14327    where
14328        Self: Rev32Emitter<T0, T1>,
14329    {
14330        <Self as Rev32Emitter<T0, T1>>::rev32(self, rd, rn);
14331    }
14332    /// Emits the `REV64` instruction.
14333    /// Assembly forms: `REV|REV64 XD, XN`; `REV64 VD.T, VN.T`; `REV64 VD.T, VN.T`.
14334    /// Operands: `rd`, `rn`.
14335    pub fn rev64<T0, T1>(&mut self, rd: T0, rn: T1)
14336    where
14337        Self: Rev64Emitter<T0, T1>,
14338    {
14339        <Self as Rev64Emitter<T0, T1>>::rev64(self, rd, rn);
14340    }
14341    /// Emits the `ROR` instruction.
14342    /// Assembly forms: `ROR|RORV WD, WN, WM`; `ROR|RORV XD, XN, XM`; `ROR WD, WN, #N`; `ROR XD, XN, #N`.
14343    /// Operands: `rd`, `rn`, `rm_or_shift`.
14344    pub fn ror<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm_or_shift: T2)
14345    where
14346        Self: RorEmitter<T0, T1, T2>,
14347    {
14348        <Self as RorEmitter<T0, T1, T2>>::ror(self, rd, rn, rm_or_shift);
14349    }
14350    /// Emits the `RORV` instruction.
14351    /// Assembly forms: `ROR|RORV WD, WN, WM`; `ROR|RORV XD, XN, XM`.
14352    /// Operands: `rd`, `rn`, `rm`.
14353    pub fn rorv<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
14354    where
14355        Self: RorvEmitter<T0, T1, T2>,
14356    {
14357        <Self as RorvEmitter<T0, T1, T2>>::rorv(self, rd, rn, rm);
14358    }
14359    /// Emits the `SBC` instruction.
14360    /// Assembly forms: `SBC WD, WN, WM`; `SBC XD, XN, XM`.
14361    /// Operands: `rd`, `rn`, `rm`.
14362    pub fn sbc<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
14363    where
14364        Self: SbcEmitter<T0, T1, T2>,
14365    {
14366        <Self as SbcEmitter<T0, T1, T2>>::sbc(self, rd, rn, rm);
14367    }
14368    /// Emits the `SBCS` instruction.
14369    /// Assembly forms: `SBCS WD, WN, WM`; `SBCS XD, XN, XM`.
14370    /// Operands: `rd`, `rn`, `rm`.
14371    pub fn sbcs<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
14372    where
14373        Self: SbcsEmitter<T0, T1, T2>,
14374    {
14375        <Self as SbcsEmitter<T0, T1, T2>>::sbcs(self, rd, rn, rm);
14376    }
14377    /// Emits the `SBFIZ` instruction.
14378    /// Assembly forms: `SBFIZ WD, WN, #LSB, #WIDTH`; `SBFIZ XD, XN, #LSB, #WIDTH`.
14379    /// Operands: `rd`, `rn`, `lsb`, `width`.
14380    pub fn sbfiz<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, lsb: T2, width: T3)
14381    where
14382        Self: SbfizEmitter<T0, T1, T2, T3>,
14383    {
14384        <Self as SbfizEmitter<T0, T1, T2, T3>>::sbfiz(self, rd, rn, lsb, width);
14385    }
14386    /// Emits the `SBFM` instruction.
14387    /// Assembly forms: `SBFM WD, WN, #IMMR, #IMMS`; `SBFM XD, XN, #IMMR, #IMMS`.
14388    /// Operands: `rd`, `rn`, `imm`, `imm_2`.
14389    pub fn sbfm<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, imm: T2, imm_2: T3)
14390    where
14391        Self: SbfmEmitter<T0, T1, T2, T3>,
14392    {
14393        <Self as SbfmEmitter<T0, T1, T2, T3>>::sbfm(self, rd, rn, imm, imm_2);
14394    }
14395    /// Emits the `SBFX` instruction.
14396    /// Assembly forms: `SBFX WD, WN, #LSB, #WIDTH`; `SBFX XD, XN, #LSB, #WIDTH`.
14397    /// Operands: `rd`, `rn`, `lsb`, `width`.
14398    pub fn sbfx<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, lsb: T2, width: T3)
14399    where
14400        Self: SbfxEmitter<T0, T1, T2, T3>,
14401    {
14402        <Self as SbfxEmitter<T0, T1, T2, T3>>::sbfx(self, rd, rn, lsb, width);
14403    }
14404    /// Emits the `SDIV` instruction.
14405    /// Assembly forms: `SDIV WD, WN, WM`; `SDIV XD, XN, XM`.
14406    /// Operands: `rd`, `rn`, `rm`.
14407    pub fn sdiv<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
14408    where
14409        Self: SdivEmitter<T0, T1, T2>,
14410    {
14411        <Self as SdivEmitter<T0, T1, T2>>::sdiv(self, rd, rn, rm);
14412    }
14413    /// Emits the `SMADDL` instruction.
14414    /// Assembly forms: `SMADDL XD, WN, WM, XA`.
14415    /// Operands: `rd`, `rn`, `rm`, `operand_4`.
14416    pub fn smaddl<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm: T2, operand_4: T3)
14417    where
14418        Self: SmaddlEmitter<T0, T1, T2, T3>,
14419    {
14420        <Self as SmaddlEmitter<T0, T1, T2, T3>>::smaddl(self, rd, rn, rm, operand_4);
14421    }
14422    /// Emits the `SMC` instruction.
14423    /// Assembly forms: `SMC #IMMZ`.
14424    /// Operands: `imm`.
14425    pub fn smc<T0>(&mut self, imm: T0)
14426    where
14427        Self: SmcEmitter<T0>,
14428    {
14429        <Self as SmcEmitter<T0>>::smc(self, imm);
14430    }
14431    /// Emits the `SMNEGL` instruction.
14432    /// Assembly forms: `SMNEGL XD, WN, WM`.
14433    /// Operands: `rd`, `rn`, `rm`.
14434    pub fn smnegl<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
14435    where
14436        Self: SmneglEmitter<T0, T1, T2>,
14437    {
14438        <Self as SmneglEmitter<T0, T1, T2>>::smnegl(self, rd, rn, rm);
14439    }
14440    /// Emits the `SMSUBL` instruction.
14441    /// Assembly forms: `SMSUBL XD, WN, WM, XA`.
14442    /// Operands: `rd`, `rn`, `rm`, `operand_4`.
14443    pub fn smsubl<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm: T2, operand_4: T3)
14444    where
14445        Self: SmsublEmitter<T0, T1, T2, T3>,
14446    {
14447        <Self as SmsublEmitter<T0, T1, T2, T3>>::smsubl(self, rd, rn, rm, operand_4);
14448    }
14449    /// Emits the `SMULH` instruction.
14450    /// Assembly forms: `SMULH XD, XN, XM`.
14451    /// Operands: `rd`, `rn`, `rm`.
14452    pub fn smulh<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
14453    where
14454        Self: SmulhEmitter<T0, T1, T2>,
14455    {
14456        <Self as SmulhEmitter<T0, T1, T2>>::smulh(self, rd, rn, rm);
14457    }
14458    /// Emits the `SMULL` instruction.
14459    /// Assembly forms: `SMULL XD, WN, WM`; `SMULL VD.TA, VN.TB, VM.TB`; `SMULL VD.4S, VN.4H, VM.H[#IDX]`; `SMULL VD.2D, VN.2S, VM.S[#IDX]`.
14460    /// Operands: `rd`, `rn`, `rm`.
14461    pub fn smull<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
14462    where
14463        Self: SmullEmitter<T0, T1, T2>,
14464    {
14465        <Self as SmullEmitter<T0, T1, T2>>::smull(self, rd, rn, rm);
14466    }
14467    /// Emits the `SUB` instruction.
14468    /// Assembly forms: `SUB WD, WN, WM, {LSL|LSR|ASR #N}`; `SUB XD, XN, XM, {LSL|LSR|ASR #N}`; `SUB WD|WSP, WN|WSP, WM, {EXTEND #N}`; `SUB XD|SP, XN|SP, RM, {EXTEND #N}` (and related forms).
14469    /// Operands: `rd`, `rn`, `rm_or_imm`.
14470    pub fn sub<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm_or_imm: T2)
14471    where
14472        Self: SubEmitter<T0, T1, T2>,
14473    {
14474        <Self as SubEmitter<T0, T1, T2>>::sub(self, rd, rn, rm_or_imm);
14475    }
14476    /// Emits the `SUB_4` instruction.
14477    /// Assembly forms: `SUB WD, WN, WM, {LSL|LSR|ASR #N}`; `SUB XD, XN, XM, {LSL|LSR|ASR #N}`; `SUB WD|WSP, WN|WSP, WM, {EXTEND #N}`; `SUB XD|SP, XN|SP, RM, {EXTEND #N}` (and related forms).
14478    /// Operands: `rd`, `rn`, `rm_or_imm`, `shift`.
14479    pub fn sub_4<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm_or_imm: T2, shift: T3)
14480    where
14481        Self: Sub4Emitter<T0, T1, T2, T3>,
14482    {
14483        <Self as Sub4Emitter<T0, T1, T2, T3>>::sub_4(self, rd, rn, rm_or_imm, shift);
14484    }
14485    /// Emits the `SUBS` instruction.
14486    /// Assembly forms: `SUBS WD, WN, WM, {LSL|LSR|ASR #N}`; `SUBS XD, XN, XM, {LSL|LSR|ASR #N}`; `SUBS WD, WN|WSP, WM, {EXTEND #N}`; `SUBS XD, XN|SP, RM, {EXTEND #N}` (and related forms).
14487    /// Operands: `rd`, `rn`, `rm_or_imm`.
14488    pub fn subs<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm_or_imm: T2)
14489    where
14490        Self: SubsEmitter<T0, T1, T2>,
14491    {
14492        <Self as SubsEmitter<T0, T1, T2>>::subs(self, rd, rn, rm_or_imm);
14493    }
14494    /// Emits the `SUBS_4` instruction.
14495    /// Assembly forms: `SUBS WD, WN, WM, {LSL|LSR|ASR #N}`; `SUBS XD, XN, XM, {LSL|LSR|ASR #N}`; `SUBS WD, WN|WSP, WM, {EXTEND #N}`; `SUBS XD, XN|SP, RM, {EXTEND #N}` (and related forms).
14496    /// Operands: `rd`, `rn`, `rm_or_imm`, `shift`.
14497    pub fn subs_4<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm_or_imm: T2, shift: T3)
14498    where
14499        Self: Subs4Emitter<T0, T1, T2, T3>,
14500    {
14501        <Self as Subs4Emitter<T0, T1, T2, T3>>::subs_4(self, rd, rn, rm_or_imm, shift);
14502    }
14503    /// Emits the `SVC` instruction.
14504    /// Assembly forms: `SVC #IMMZ`.
14505    /// Operands: `imm`.
14506    pub fn svc<T0>(&mut self, imm: T0)
14507    where
14508        Self: SvcEmitter<T0>,
14509    {
14510        <Self as SvcEmitter<T0>>::svc(self, imm);
14511    }
14512    /// Emits the `SXTB` instruction.
14513    /// Assembly forms: `SXTB WD, WN`; `SXTB XD, WN`.
14514    /// Operands: `rd`, `rn`.
14515    pub fn sxtb<T0, T1>(&mut self, rd: T0, rn: T1)
14516    where
14517        Self: SxtbEmitter<T0, T1>,
14518    {
14519        <Self as SxtbEmitter<T0, T1>>::sxtb(self, rd, rn);
14520    }
14521    /// Emits the `SXTH` instruction.
14522    /// Assembly forms: `SXTH WD, WN`; `SXTH XD, WN`.
14523    /// Operands: `rd`, `rn`.
14524    pub fn sxth<T0, T1>(&mut self, rd: T0, rn: T1)
14525    where
14526        Self: SxthEmitter<T0, T1>,
14527    {
14528        <Self as SxthEmitter<T0, T1>>::sxth(self, rd, rn);
14529    }
14530    /// Emits the `SXTW` instruction.
14531    /// Assembly forms: `SXTW XD, WN`.
14532    /// Operands: `rd`, `rn`.
14533    pub fn sxtw<T0, T1>(&mut self, rd: T0, rn: T1)
14534    where
14535        Self: SxtwEmitter<T0, T1>,
14536    {
14537        <Self as SxtwEmitter<T0, T1>>::sxtw(self, rd, rn);
14538    }
14539    /// Emits the `SYS` instruction.
14540    /// Assembly forms: `SYS #OP1, #CN, #CM, #OP2`; `SYS #OP1, #CN, #CM, #OP2, XT`.
14541    /// Operands: `system_op1`, `cn`, `cm`, `system_op2`.
14542    pub fn sys<T0, T1, T2, T3>(&mut self, system_op1: T0, cn: T1, cm: T2, system_op2: T3)
14543    where
14544        Self: SysEmitter<T0, T1, T2, T3>,
14545    {
14546        <Self as SysEmitter<T0, T1, T2, T3>>::sys(self, system_op1, cn, cm, system_op2);
14547    }
14548    /// Emits the `SYS_5` instruction.
14549    /// Assembly forms: `SYS #OP1, #CN, #CM, #OP2`; `SYS #OP1, #CN, #CM, #OP2, XT`.
14550    /// Operands: `system_op1`, `cn`, `cm`, `system_op2`, `rt`.
14551    pub fn sys_5<T0, T1, T2, T3, T4>(
14552        &mut self,
14553        system_op1: T0,
14554        cn: T1,
14555        cm: T2,
14556        system_op2: T3,
14557        rt: T4,
14558    ) where
14559        Self: Sys5Emitter<T0, T1, T2, T3, T4>,
14560    {
14561        <Self as Sys5Emitter<T0, T1, T2, T3, T4>>::sys_5(self, system_op1, cn, cm, system_op2, rt);
14562    }
14563    /// Emits the `TLBI` instruction.
14564    /// Assembly forms: `TLBI #TLBI_OP`; `TLBI #TLBI_OP, XT`.
14565    /// Operands: `tlbi_op`, `rt`.
14566    pub fn tlbi<T0, T1>(&mut self, tlbi_op: T0, rt: T1)
14567    where
14568        Self: TlbiEmitter<T0, T1>,
14569    {
14570        <Self as TlbiEmitter<T0, T1>>::tlbi(self, tlbi_op, rt);
14571    }
14572    /// Emits the `TST` instruction.
14573    /// Assembly forms: `TST WN, WM, {SOP #N}`; `TST XN, XM, {SOP #N}`; `TST WN, #IMM`; `TST XN, #IMM`.
14574    /// Operands: `rn`, `rm_or_imm`.
14575    pub fn tst<T0, T1>(&mut self, rn: T0, rm_or_imm: T1)
14576    where
14577        Self: TstEmitter<T0, T1>,
14578    {
14579        <Self as TstEmitter<T0, T1>>::tst(self, rn, rm_or_imm);
14580    }
14581    /// Emits the `TST_3` instruction.
14582    /// Assembly forms: `TST WN, WM, {SOP #N}`; `TST XN, XM, {SOP #N}`; `TST WN, #IMM`; `TST XN, #IMM`.
14583    /// Operands: `rn`, `rm`, `shift`.
14584    pub fn tst_3<T0, T1, T2>(&mut self, rn: T0, rm: T1, shift: T2)
14585    where
14586        Self: Tst3Emitter<T0, T1, T2>,
14587    {
14588        <Self as Tst3Emitter<T0, T1, T2>>::tst_3(self, rn, rm, shift);
14589    }
14590    /// Emits the `UDIV` instruction.
14591    /// Assembly forms: `UDIV WD, WN, WM`; `UDIV XD, XN, XM`.
14592    /// Operands: `rd`, `rn`, `rm`.
14593    pub fn udiv<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
14594    where
14595        Self: UdivEmitter<T0, T1, T2>,
14596    {
14597        <Self as UdivEmitter<T0, T1, T2>>::udiv(self, rd, rn, rm);
14598    }
14599    /// Emits the `UBFIZ` instruction.
14600    /// Assembly forms: `UBFIZ WD, WN, #LSB, #WIDTH`; `UBFIZ XD, XN, #LSB, #WIDTH`.
14601    /// Operands: `rd`, `rn`, `lsb`, `width`.
14602    pub fn ubfiz<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, lsb: T2, width: T3)
14603    where
14604        Self: UbfizEmitter<T0, T1, T2, T3>,
14605    {
14606        <Self as UbfizEmitter<T0, T1, T2, T3>>::ubfiz(self, rd, rn, lsb, width);
14607    }
14608    /// Emits the `UBFM` instruction.
14609    /// Assembly forms: `UBFM WD, WN, #IMMR, #IMMS`; `UBFM XD, XN, #IMMR, #IMMS`.
14610    /// Operands: `rd`, `rn`, `imm`, `imm_2`.
14611    pub fn ubfm<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, imm: T2, imm_2: T3)
14612    where
14613        Self: UbfmEmitter<T0, T1, T2, T3>,
14614    {
14615        <Self as UbfmEmitter<T0, T1, T2, T3>>::ubfm(self, rd, rn, imm, imm_2);
14616    }
14617    /// Emits the `UBFX` instruction.
14618    /// Assembly forms: `UBFX WD, WN, #LSB, #WIDTH`; `UBFX XD, XN, #LSB, #WIDTH`.
14619    /// Operands: `rd`, `rn`, `lsb`, `width`.
14620    pub fn ubfx<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, lsb: T2, width: T3)
14621    where
14622        Self: UbfxEmitter<T0, T1, T2, T3>,
14623    {
14624        <Self as UbfxEmitter<T0, T1, T2, T3>>::ubfx(self, rd, rn, lsb, width);
14625    }
14626    /// Emits the `UMADDL` instruction.
14627    /// Assembly forms: `UMADDL XD, WN, WM, XA`.
14628    /// Operands: `rd`, `rn`, `rm`, `operand_4`.
14629    pub fn umaddl<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm: T2, operand_4: T3)
14630    where
14631        Self: UmaddlEmitter<T0, T1, T2, T3>,
14632    {
14633        <Self as UmaddlEmitter<T0, T1, T2, T3>>::umaddl(self, rd, rn, rm, operand_4);
14634    }
14635    /// Emits the `UMNEGL` instruction.
14636    /// Assembly forms: `UMNEGL XD, WN, WM`.
14637    /// Operands: `rd`, `rn`, `rm`.
14638    pub fn umnegl<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
14639    where
14640        Self: UmneglEmitter<T0, T1, T2>,
14641    {
14642        <Self as UmneglEmitter<T0, T1, T2>>::umnegl(self, rd, rn, rm);
14643    }
14644    /// Emits the `UMSUBL` instruction.
14645    /// Assembly forms: `UMSUBL XD, WN, WM, XA`.
14646    /// Operands: `rd`, `rn`, `rm`, `operand_4`.
14647    pub fn umsubl<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm: T2, operand_4: T3)
14648    where
14649        Self: UmsublEmitter<T0, T1, T2, T3>,
14650    {
14651        <Self as UmsublEmitter<T0, T1, T2, T3>>::umsubl(self, rd, rn, rm, operand_4);
14652    }
14653    /// Emits the `UMULL` instruction.
14654    /// Assembly forms: `UMULL XD, WN, WM`; `UMULL VD.TA, VN.TB, VM.TB`; `UMULL VD.4S, VN.4H, VM.H[#IDX]`; `UMULL VD.2D, VN.2S, VM.S[#IDX]`.
14655    /// Operands: `rd`, `rn`, `rm`.
14656    pub fn umull<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
14657    where
14658        Self: UmullEmitter<T0, T1, T2>,
14659    {
14660        <Self as UmullEmitter<T0, T1, T2>>::umull(self, rd, rn, rm);
14661    }
14662    /// Emits the `UMULH` instruction.
14663    /// Assembly forms: `UMULH XD, XN, XM`.
14664    /// Operands: `rd`, `rn`, `rm`.
14665    pub fn umulh<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
14666    where
14667        Self: UmulhEmitter<T0, T1, T2>,
14668    {
14669        <Self as UmulhEmitter<T0, T1, T2>>::umulh(self, rd, rn, rm);
14670    }
14671    /// Emits the `UXTB` instruction.
14672    /// Assembly forms: `UXTB WD, WN`.
14673    /// Operands: `rd`, `rn`.
14674    pub fn uxtb<T0, T1>(&mut self, rd: T0, rn: T1)
14675    where
14676        Self: UxtbEmitter<T0, T1>,
14677    {
14678        <Self as UxtbEmitter<T0, T1>>::uxtb(self, rd, rn);
14679    }
14680    /// Emits the `UXTH` instruction.
14681    /// Assembly forms: `UXTH WD, WN`.
14682    /// Operands: `rd`, `rn`.
14683    pub fn uxth<T0, T1>(&mut self, rd: T0, rn: T1)
14684    where
14685        Self: UxthEmitter<T0, T1>,
14686    {
14687        <Self as UxthEmitter<T0, T1>>::uxth(self, rd, rn);
14688    }
14689    /// Emits the `CSDB` instruction.
14690    /// Assembly forms: `CSDB`.
14691    pub fn csdb(&mut self)
14692    where
14693        Self: CsdbEmitter,
14694    {
14695        <Self as CsdbEmitter>::csdb(self);
14696    }
14697    /// Emits the `DCPS1` instruction.
14698    /// Assembly forms: `DCPS1 {#IMM}`.
14699    /// Operands: `imm`.
14700    pub fn dcps1<T0>(&mut self, imm: T0)
14701    where
14702        Self: Dcps1Emitter<T0>,
14703    {
14704        <Self as Dcps1Emitter<T0>>::dcps1(self, imm);
14705    }
14706    /// Emits the `DCPS2` instruction.
14707    /// Assembly forms: `DCPS2 {#IMM}`.
14708    /// Operands: `imm`.
14709    pub fn dcps2<T0>(&mut self, imm: T0)
14710    where
14711        Self: Dcps2Emitter<T0>,
14712    {
14713        <Self as Dcps2Emitter<T0>>::dcps2(self, imm);
14714    }
14715    /// Emits the `DCPS3` instruction.
14716    /// Assembly forms: `DCPS3 {#IMM}`.
14717    /// Operands: `imm`.
14718    pub fn dcps3<T0>(&mut self, imm: T0)
14719    where
14720        Self: Dcps3Emitter<T0>,
14721    {
14722        <Self as Dcps3Emitter<T0>>::dcps3(self, imm);
14723    }
14724    /// Emits the `PSSBB` instruction.
14725    /// Assembly forms: `PSSBB`.
14726    pub fn pssbb(&mut self)
14727    where
14728        Self: PssbbEmitter,
14729    {
14730        <Self as PssbbEmitter>::pssbb(self);
14731    }
14732    /// Emits the `SSBB` instruction.
14733    /// Assembly forms: `SSBB`.
14734    pub fn ssbb(&mut self)
14735    where
14736        Self: SsbbEmitter,
14737    {
14738        <Self as SsbbEmitter>::ssbb(self);
14739    }
14740    /// Emits the `UDF` instruction.
14741    /// Assembly forms: `UDF #IMM`.
14742    /// Operands: `imm`.
14743    pub fn udf<T0>(&mut self, imm: T0)
14744    where
14745        Self: UdfEmitter<T0>,
14746    {
14747        <Self as UdfEmitter<T0>>::udf(self, imm);
14748    }
14749    /// Emits the `B` instruction.
14750    /// Assembly forms: `B #RELS*4`; `B.<COND> #RELS*4`.
14751    /// Operands: `target`.
14752    pub fn b<T0>(&mut self, target: T0)
14753    where
14754        Self: BEmitter<T0>,
14755    {
14756        <Self as BEmitter<T0>>::b(self, target);
14757    }
14758    /// Emits the `B` instruction.
14759    /// Assembly forms: `B #RELS*4`; `B.<COND> #RELS*4`.
14760    /// Operands: `target`.
14761    pub fn b_eq<T0>(&mut self, target: T0)
14762    where
14763        Self: BEmitter<T0>,
14764    {
14765        <Self as BEmitter<T0>>::b_eq(self, target);
14766    }
14767    /// Emits the `B` instruction.
14768    /// Assembly forms: `B #RELS*4`; `B.<COND> #RELS*4`.
14769    /// Operands: `target`.
14770    pub fn b_ne<T0>(&mut self, target: T0)
14771    where
14772        Self: BEmitter<T0>,
14773    {
14774        <Self as BEmitter<T0>>::b_ne(self, target);
14775    }
14776    /// Emits the `B` instruction.
14777    /// Assembly forms: `B #RELS*4`; `B.<COND> #RELS*4`.
14778    /// Operands: `target`.
14779    pub fn b_cs<T0>(&mut self, target: T0)
14780    where
14781        Self: BEmitter<T0>,
14782    {
14783        <Self as BEmitter<T0>>::b_cs(self, target);
14784    }
14785    /// Emits the `B` instruction.
14786    /// Assembly forms: `B #RELS*4`; `B.<COND> #RELS*4`.
14787    /// Operands: `target`.
14788    pub fn b_hs<T0>(&mut self, target: T0)
14789    where
14790        Self: BEmitter<T0>,
14791    {
14792        <Self as BEmitter<T0>>::b_hs(self, target);
14793    }
14794    /// Emits the `B` instruction.
14795    /// Assembly forms: `B #RELS*4`; `B.<COND> #RELS*4`.
14796    /// Operands: `target`.
14797    pub fn b_cc<T0>(&mut self, target: T0)
14798    where
14799        Self: BEmitter<T0>,
14800    {
14801        <Self as BEmitter<T0>>::b_cc(self, target);
14802    }
14803    /// Emits the `B` instruction.
14804    /// Assembly forms: `B #RELS*4`; `B.<COND> #RELS*4`.
14805    /// Operands: `target`.
14806    pub fn b_lo<T0>(&mut self, target: T0)
14807    where
14808        Self: BEmitter<T0>,
14809    {
14810        <Self as BEmitter<T0>>::b_lo(self, target);
14811    }
14812    /// Emits the `B` instruction.
14813    /// Assembly forms: `B #RELS*4`; `B.<COND> #RELS*4`.
14814    /// Operands: `target`.
14815    pub fn b_mi<T0>(&mut self, target: T0)
14816    where
14817        Self: BEmitter<T0>,
14818    {
14819        <Self as BEmitter<T0>>::b_mi(self, target);
14820    }
14821    /// Emits the `B` instruction.
14822    /// Assembly forms: `B #RELS*4`; `B.<COND> #RELS*4`.
14823    /// Operands: `target`.
14824    pub fn b_pl<T0>(&mut self, target: T0)
14825    where
14826        Self: BEmitter<T0>,
14827    {
14828        <Self as BEmitter<T0>>::b_pl(self, target);
14829    }
14830    /// Emits the `B` instruction.
14831    /// Assembly forms: `B #RELS*4`; `B.<COND> #RELS*4`.
14832    /// Operands: `target`.
14833    pub fn b_vs<T0>(&mut self, target: T0)
14834    where
14835        Self: BEmitter<T0>,
14836    {
14837        <Self as BEmitter<T0>>::b_vs(self, target);
14838    }
14839    /// Emits the `B` instruction.
14840    /// Assembly forms: `B #RELS*4`; `B.<COND> #RELS*4`.
14841    /// Operands: `target`.
14842    pub fn b_vc<T0>(&mut self, target: T0)
14843    where
14844        Self: BEmitter<T0>,
14845    {
14846        <Self as BEmitter<T0>>::b_vc(self, target);
14847    }
14848    /// Emits the `B` instruction.
14849    /// Assembly forms: `B #RELS*4`; `B.<COND> #RELS*4`.
14850    /// Operands: `target`.
14851    pub fn b_hi<T0>(&mut self, target: T0)
14852    where
14853        Self: BEmitter<T0>,
14854    {
14855        <Self as BEmitter<T0>>::b_hi(self, target);
14856    }
14857    /// Emits the `B` instruction.
14858    /// Assembly forms: `B #RELS*4`; `B.<COND> #RELS*4`.
14859    /// Operands: `target`.
14860    pub fn b_ls<T0>(&mut self, target: T0)
14861    where
14862        Self: BEmitter<T0>,
14863    {
14864        <Self as BEmitter<T0>>::b_ls(self, target);
14865    }
14866    /// Emits the `B` instruction.
14867    /// Assembly forms: `B #RELS*4`; `B.<COND> #RELS*4`.
14868    /// Operands: `target`.
14869    pub fn b_ge<T0>(&mut self, target: T0)
14870    where
14871        Self: BEmitter<T0>,
14872    {
14873        <Self as BEmitter<T0>>::b_ge(self, target);
14874    }
14875    /// Emits the `B` instruction.
14876    /// Assembly forms: `B #RELS*4`; `B.<COND> #RELS*4`.
14877    /// Operands: `target`.
14878    pub fn b_lt<T0>(&mut self, target: T0)
14879    where
14880        Self: BEmitter<T0>,
14881    {
14882        <Self as BEmitter<T0>>::b_lt(self, target);
14883    }
14884    /// Emits the `B` instruction.
14885    /// Assembly forms: `B #RELS*4`; `B.<COND> #RELS*4`.
14886    /// Operands: `target`.
14887    pub fn b_gt<T0>(&mut self, target: T0)
14888    where
14889        Self: BEmitter<T0>,
14890    {
14891        <Self as BEmitter<T0>>::b_gt(self, target);
14892    }
14893    /// Emits the `B` instruction.
14894    /// Assembly forms: `B #RELS*4`; `B.<COND> #RELS*4`.
14895    /// Operands: `target`.
14896    pub fn b_le<T0>(&mut self, target: T0)
14897    where
14898        Self: BEmitter<T0>,
14899    {
14900        <Self as BEmitter<T0>>::b_le(self, target);
14901    }
14902    /// Emits the `B` instruction.
14903    /// Assembly forms: `B #RELS*4`; `B.<COND> #RELS*4`.
14904    /// Operands: `target`.
14905    pub fn b_al<T0>(&mut self, target: T0)
14906    where
14907        Self: BEmitter<T0>,
14908    {
14909        <Self as BEmitter<T0>>::b_al(self, target);
14910    }
14911    /// Emits the `BL` instruction.
14912    /// Assembly forms: `BL #RELS*4`.
14913    /// Operands: `target`.
14914    pub fn bl<T0>(&mut self, target: T0)
14915    where
14916        Self: BlEmitter<T0>,
14917    {
14918        <Self as BlEmitter<T0>>::bl(self, target);
14919    }
14920    /// Emits the `BLR` instruction.
14921    /// Assembly forms: `BLR XN`.
14922    /// Operands: `rn`.
14923    pub fn blr<T0>(&mut self, rn: T0)
14924    where
14925        Self: BlrEmitter<T0>,
14926    {
14927        <Self as BlrEmitter<T0>>::blr(self, rn);
14928    }
14929    /// Emits the `BR` instruction.
14930    /// Assembly forms: `BR XN`.
14931    /// Operands: `rn`.
14932    pub fn br<T0>(&mut self, rn: T0)
14933    where
14934        Self: BrEmitter<T0>,
14935    {
14936        <Self as BrEmitter<T0>>::br(self, rn);
14937    }
14938    /// Emits the `CBZ` instruction.
14939    /// Assembly forms: `CBZ WN, #RELS*4`; `CBZ XN, #RELS*4`.
14940    /// Operands: `rn`, `target`.
14941    pub fn cbz<T0, T1>(&mut self, rn: T0, target: T1)
14942    where
14943        Self: CbzEmitter<T0, T1>,
14944    {
14945        <Self as CbzEmitter<T0, T1>>::cbz(self, rn, target);
14946    }
14947    /// Emits the `CBNZ` instruction.
14948    /// Assembly forms: `CBNZ WN, #RELS*4`; `CBNZ XN, #RELS*4`.
14949    /// Operands: `rn`, `target`.
14950    pub fn cbnz<T0, T1>(&mut self, rn: T0, target: T1)
14951    where
14952        Self: CbnzEmitter<T0, T1>,
14953    {
14954        <Self as CbnzEmitter<T0, T1>>::cbnz(self, rn, target);
14955    }
14956    /// Emits the `TBNZ` instruction.
14957    /// Assembly forms: `TBNZ WT, #IMM, #RELS*4`; `TBNZ XT, #IMM, #RELS*4`.
14958    /// Operands: `rt`, `imm`, `target`.
14959    pub fn tbnz<T0, T1, T2>(&mut self, rt: T0, imm: T1, target: T2)
14960    where
14961        Self: TbnzEmitter<T0, T1, T2>,
14962    {
14963        <Self as TbnzEmitter<T0, T1, T2>>::tbnz(self, rt, imm, target);
14964    }
14965    /// Emits the `TBZ` instruction.
14966    /// Assembly forms: `TBZ WT, #IMM, #RELS*4`; `TBZ XT, #IMM, #RELS*4`.
14967    /// Operands: `rt`, `imm`, `target`.
14968    pub fn tbz<T0, T1, T2>(&mut self, rt: T0, imm: T1, target: T2)
14969    where
14970        Self: TbzEmitter<T0, T1, T2>,
14971    {
14972        <Self as TbzEmitter<T0, T1, T2>>::tbz(self, rt, imm, target);
14973    }
14974    /// Emits the `CAS` instruction.
14975    /// Assembly forms: `CAS WS, WD, [XN|SP]`; `CAS XS, XD, [XN|SP]`.
14976    /// Operands: `rs`, `rd`, `addr`.
14977    pub fn cas<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
14978    where
14979        Self: CasEmitter<T0, T1, T2>,
14980    {
14981        <Self as CasEmitter<T0, T1, T2>>::cas(self, rs, rd, addr);
14982    }
14983    /// Emits the `CASA` instruction.
14984    /// Assembly forms: `CASA WS, WD, [XN|SP]`; `CASA XS, XD, [XN|SP]`.
14985    /// Operands: `rs`, `rd`, `addr`.
14986    pub fn casa<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
14987    where
14988        Self: CasaEmitter<T0, T1, T2>,
14989    {
14990        <Self as CasaEmitter<T0, T1, T2>>::casa(self, rs, rd, addr);
14991    }
14992    /// Emits the `CASAB` instruction.
14993    /// Assembly forms: `CASAB WS, WD, [XN|SP]`.
14994    /// Operands: `rs`, `rd`, `addr`.
14995    pub fn casab<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
14996    where
14997        Self: CasabEmitter<T0, T1, T2>,
14998    {
14999        <Self as CasabEmitter<T0, T1, T2>>::casab(self, rs, rd, addr);
15000    }
15001    /// Emits the `CASAH` instruction.
15002    /// Assembly forms: `CASAH WS, WD, [XN|SP]`.
15003    /// Operands: `rs`, `rd`, `addr`.
15004    pub fn casah<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15005    where
15006        Self: CasahEmitter<T0, T1, T2>,
15007    {
15008        <Self as CasahEmitter<T0, T1, T2>>::casah(self, rs, rd, addr);
15009    }
15010    /// Emits the `CASAL` instruction.
15011    /// Assembly forms: `CASAL WS, WD, [XN|SP]`; `CASAL XS, XD, [XN|SP]`.
15012    /// Operands: `rs`, `rd`, `addr`.
15013    pub fn casal<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15014    where
15015        Self: CasalEmitter<T0, T1, T2>,
15016    {
15017        <Self as CasalEmitter<T0, T1, T2>>::casal(self, rs, rd, addr);
15018    }
15019    /// Emits the `CASALB` instruction.
15020    /// Assembly forms: `CASALB WS, WD, [XN|SP]`.
15021    /// Operands: `rs`, `rd`, `addr`.
15022    pub fn casalb<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15023    where
15024        Self: CasalbEmitter<T0, T1, T2>,
15025    {
15026        <Self as CasalbEmitter<T0, T1, T2>>::casalb(self, rs, rd, addr);
15027    }
15028    /// Emits the `CASALH` instruction.
15029    /// Assembly forms: `CASALH WS, WD, [XN|SP]`.
15030    /// Operands: `rs`, `rd`, `addr`.
15031    pub fn casalh<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15032    where
15033        Self: CasalhEmitter<T0, T1, T2>,
15034    {
15035        <Self as CasalhEmitter<T0, T1, T2>>::casalh(self, rs, rd, addr);
15036    }
15037    /// Emits the `CASB` instruction.
15038    /// Assembly forms: `CASB WS, WD, [XN|SP]`.
15039    /// Operands: `rs`, `rd`, `addr`.
15040    pub fn casb<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15041    where
15042        Self: CasbEmitter<T0, T1, T2>,
15043    {
15044        <Self as CasbEmitter<T0, T1, T2>>::casb(self, rs, rd, addr);
15045    }
15046    /// Emits the `CASH` instruction.
15047    /// Assembly forms: `CASH WS, WD, [XN|SP]`.
15048    /// Operands: `rs`, `rd`, `addr`.
15049    pub fn cash<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15050    where
15051        Self: CashEmitter<T0, T1, T2>,
15052    {
15053        <Self as CashEmitter<T0, T1, T2>>::cash(self, rs, rd, addr);
15054    }
15055    /// Emits the `CASL` instruction.
15056    /// Assembly forms: `CASL WS, WD, [XN|SP]`; `CASL XS, XD, [XN|SP]`.
15057    /// Operands: `rs`, `rd`, `addr`.
15058    pub fn casl<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15059    where
15060        Self: CaslEmitter<T0, T1, T2>,
15061    {
15062        <Self as CaslEmitter<T0, T1, T2>>::casl(self, rs, rd, addr);
15063    }
15064    /// Emits the `CASLB` instruction.
15065    /// Assembly forms: `CASLB WS, WD, [XN|SP]`.
15066    /// Operands: `rs`, `rd`, `addr`.
15067    pub fn caslb<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15068    where
15069        Self: CaslbEmitter<T0, T1, T2>,
15070    {
15071        <Self as CaslbEmitter<T0, T1, T2>>::caslb(self, rs, rd, addr);
15072    }
15073    /// Emits the `CASLH` instruction.
15074    /// Assembly forms: `CASLH WS, WD, [XN|SP]`.
15075    /// Operands: `rs`, `rd`, `addr`.
15076    pub fn caslh<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15077    where
15078        Self: CaslhEmitter<T0, T1, T2>,
15079    {
15080        <Self as CaslhEmitter<T0, T1, T2>>::caslh(self, rs, rd, addr);
15081    }
15082    /// Emits the `CASP` instruction.
15083    /// Assembly forms: `CASP 2X{WS}+, 2X{WD}+, [XN|SP]`; `CASP 2X{XS}+, 2X{XD}+, [XN|SP]`.
15084    /// Operands: `rd`, `rn`, `rm1`, `rm2`, `addr`.
15085    pub fn casp<T0, T1, T2, T3, T4>(&mut self, rd: T0, rn: T1, rm1: T2, rm2: T3, addr: T4)
15086    where
15087        Self: CaspEmitter<T0, T1, T2, T3, T4>,
15088    {
15089        <Self as CaspEmitter<T0, T1, T2, T3, T4>>::casp(self, rd, rn, rm1, rm2, addr);
15090    }
15091    /// Emits the `CASPA` instruction.
15092    /// Assembly forms: `CASPA 2X{WS}+, 2X{WD}+, [XN|SP]`; `CASPA 2X{XS}+, 2X{XD}+, [XN|SP]`.
15093    /// Operands: `rd`, `rn`, `rm1`, `rm2`, `addr`.
15094    pub fn caspa<T0, T1, T2, T3, T4>(&mut self, rd: T0, rn: T1, rm1: T2, rm2: T3, addr: T4)
15095    where
15096        Self: CaspaEmitter<T0, T1, T2, T3, T4>,
15097    {
15098        <Self as CaspaEmitter<T0, T1, T2, T3, T4>>::caspa(self, rd, rn, rm1, rm2, addr);
15099    }
15100    /// Emits the `CASPAL` instruction.
15101    /// Assembly forms: `CASPAL 2X{WS}+, 2X{WD}+, [XN|SP]`; `CASPAL 2X{XS}+, 2X{XD}+, [XN|SP]`.
15102    /// Operands: `rd`, `rn`, `rm1`, `rm2`, `addr`.
15103    pub fn caspal<T0, T1, T2, T3, T4>(&mut self, rd: T0, rn: T1, rm1: T2, rm2: T3, addr: T4)
15104    where
15105        Self: CaspalEmitter<T0, T1, T2, T3, T4>,
15106    {
15107        <Self as CaspalEmitter<T0, T1, T2, T3, T4>>::caspal(self, rd, rn, rm1, rm2, addr);
15108    }
15109    /// Emits the `CASPL` instruction.
15110    /// Assembly forms: `CASPL 2X{WS}+, 2X{WD}+, [XN|SP]`; `CASPL 2X{XS}+, 2X{XD}+, [XN|SP]`.
15111    /// Operands: `rd`, `rn`, `rm1`, `rm2`, `addr`.
15112    pub fn caspl<T0, T1, T2, T3, T4>(&mut self, rd: T0, rn: T1, rm1: T2, rm2: T3, addr: T4)
15113    where
15114        Self: CasplEmitter<T0, T1, T2, T3, T4>,
15115    {
15116        <Self as CasplEmitter<T0, T1, T2, T3, T4>>::caspl(self, rd, rn, rm1, rm2, addr);
15117    }
15118    /// Emits the `LDADD` instruction.
15119    /// Assembly forms: `LDADD WS, WD, [XN|SP]`; `LDADD XS, XD, [XN|SP]`.
15120    /// Operands: `rs`, `rd`, `addr`.
15121    pub fn ldadd<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15122    where
15123        Self: LdaddEmitter<T0, T1, T2>,
15124    {
15125        <Self as LdaddEmitter<T0, T1, T2>>::ldadd(self, rs, rd, addr);
15126    }
15127    /// Emits the `LDADDA` instruction.
15128    /// Assembly forms: `LDADDA WS, WD, [XN|SP]`; `LDADDA XS, XD, [XN|SP]`.
15129    /// Operands: `rs`, `rd`, `addr`.
15130    pub fn ldadda<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15131    where
15132        Self: LdaddaEmitter<T0, T1, T2>,
15133    {
15134        <Self as LdaddaEmitter<T0, T1, T2>>::ldadda(self, rs, rd, addr);
15135    }
15136    /// Emits the `LDADDAB` instruction.
15137    /// Assembly forms: `LDADDAB WS, WD, [XN|SP]`.
15138    /// Operands: `rs`, `rd`, `addr`.
15139    pub fn ldaddab<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15140    where
15141        Self: LdaddabEmitter<T0, T1, T2>,
15142    {
15143        <Self as LdaddabEmitter<T0, T1, T2>>::ldaddab(self, rs, rd, addr);
15144    }
15145    /// Emits the `LDADDAH` instruction.
15146    /// Assembly forms: `LDADDAH WS, WD, [XN|SP]`.
15147    /// Operands: `rs`, `rd`, `addr`.
15148    pub fn ldaddah<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15149    where
15150        Self: LdaddahEmitter<T0, T1, T2>,
15151    {
15152        <Self as LdaddahEmitter<T0, T1, T2>>::ldaddah(self, rs, rd, addr);
15153    }
15154    /// Emits the `LDADDAL` instruction.
15155    /// Assembly forms: `LDADDAL WS, WD, [XN|SP]`; `LDADDAL XS, XD, [XN|SP]`.
15156    /// Operands: `rs`, `rd`, `addr`.
15157    pub fn ldaddal<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15158    where
15159        Self: LdaddalEmitter<T0, T1, T2>,
15160    {
15161        <Self as LdaddalEmitter<T0, T1, T2>>::ldaddal(self, rs, rd, addr);
15162    }
15163    /// Emits the `LDADDALB` instruction.
15164    /// Assembly forms: `LDADDALB WS, WD, [XN|SP]`.
15165    /// Operands: `rs`, `rd`, `addr`.
15166    pub fn ldaddalb<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15167    where
15168        Self: LdaddalbEmitter<T0, T1, T2>,
15169    {
15170        <Self as LdaddalbEmitter<T0, T1, T2>>::ldaddalb(self, rs, rd, addr);
15171    }
15172    /// Emits the `LDADDALH` instruction.
15173    /// Assembly forms: `LDADDALH WS, WD, [XN|SP]`.
15174    /// Operands: `rs`, `rd`, `addr`.
15175    pub fn ldaddalh<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15176    where
15177        Self: LdaddalhEmitter<T0, T1, T2>,
15178    {
15179        <Self as LdaddalhEmitter<T0, T1, T2>>::ldaddalh(self, rs, rd, addr);
15180    }
15181    /// Emits the `LDADDB` instruction.
15182    /// Assembly forms: `LDADDB WS, WD, [XN|SP]`.
15183    /// Operands: `rs`, `rd`, `addr`.
15184    pub fn ldaddb<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15185    where
15186        Self: LdaddbEmitter<T0, T1, T2>,
15187    {
15188        <Self as LdaddbEmitter<T0, T1, T2>>::ldaddb(self, rs, rd, addr);
15189    }
15190    /// Emits the `LDADDH` instruction.
15191    /// Assembly forms: `LDADDH WS, WD, [XN|SP]`.
15192    /// Operands: `rs`, `rd`, `addr`.
15193    pub fn ldaddh<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15194    where
15195        Self: LdaddhEmitter<T0, T1, T2>,
15196    {
15197        <Self as LdaddhEmitter<T0, T1, T2>>::ldaddh(self, rs, rd, addr);
15198    }
15199    /// Emits the `LDADDL` instruction.
15200    /// Assembly forms: `LDADDL WS, WD, [XN|SP]`; `LDADDL XS, XD, [XN|SP]`.
15201    /// Operands: `rs`, `rd`, `addr`.
15202    pub fn ldaddl<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15203    where
15204        Self: LdaddlEmitter<T0, T1, T2>,
15205    {
15206        <Self as LdaddlEmitter<T0, T1, T2>>::ldaddl(self, rs, rd, addr);
15207    }
15208    /// Emits the `LDADDLB` instruction.
15209    /// Assembly forms: `LDADDLB WS, WD, [XN|SP]`.
15210    /// Operands: `rs`, `rd`, `addr`.
15211    pub fn ldaddlb<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15212    where
15213        Self: LdaddlbEmitter<T0, T1, T2>,
15214    {
15215        <Self as LdaddlbEmitter<T0, T1, T2>>::ldaddlb(self, rs, rd, addr);
15216    }
15217    /// Emits the `LDADDLH` instruction.
15218    /// Assembly forms: `LDADDLH WS, WD, [XN|SP]`.
15219    /// Operands: `rs`, `rd`, `addr`.
15220    pub fn ldaddlh<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15221    where
15222        Self: LdaddlhEmitter<T0, T1, T2>,
15223    {
15224        <Self as LdaddlhEmitter<T0, T1, T2>>::ldaddlh(self, rs, rd, addr);
15225    }
15226    /// Emits the `LDAR` instruction.
15227    /// Assembly forms: `LDAR WD, [XN|SP]`; `LDAR XD, [XN|SP]`.
15228    /// Operands: `rd`, `addr`.
15229    pub fn ldar<T0, T1>(&mut self, rd: T0, addr: T1)
15230    where
15231        Self: LdarEmitter<T0, T1>,
15232    {
15233        <Self as LdarEmitter<T0, T1>>::ldar(self, rd, addr);
15234    }
15235    /// Emits the `LDARB` instruction.
15236    /// Assembly forms: `LDARB WD, [XN|SP]`.
15237    /// Operands: `rd`, `addr`.
15238    pub fn ldarb<T0, T1>(&mut self, rd: T0, addr: T1)
15239    where
15240        Self: LdarbEmitter<T0, T1>,
15241    {
15242        <Self as LdarbEmitter<T0, T1>>::ldarb(self, rd, addr);
15243    }
15244    /// Emits the `LDARH` instruction.
15245    /// Assembly forms: `LDARH WD, [XN|SP]`.
15246    /// Operands: `rd`, `addr`.
15247    pub fn ldarh<T0, T1>(&mut self, rd: T0, addr: T1)
15248    where
15249        Self: LdarhEmitter<T0, T1>,
15250    {
15251        <Self as LdarhEmitter<T0, T1>>::ldarh(self, rd, addr);
15252    }
15253    /// Emits the `LDAXR` instruction.
15254    /// Assembly forms: `LDAXR WD, [XN|SP]`; `LDAXR XD, [XN|SP]`.
15255    /// Operands: `rd`, `addr`.
15256    pub fn ldaxr<T0, T1>(&mut self, rd: T0, addr: T1)
15257    where
15258        Self: LdaxrEmitter<T0, T1>,
15259    {
15260        <Self as LdaxrEmitter<T0, T1>>::ldaxr(self, rd, addr);
15261    }
15262    /// Emits the `LDAXRB` instruction.
15263    /// Assembly forms: `LDAXRB WD, [XN|SP]`.
15264    /// Operands: `rd`, `addr`.
15265    pub fn ldaxrb<T0, T1>(&mut self, rd: T0, addr: T1)
15266    where
15267        Self: LdaxrbEmitter<T0, T1>,
15268    {
15269        <Self as LdaxrbEmitter<T0, T1>>::ldaxrb(self, rd, addr);
15270    }
15271    /// Emits the `LDAXRH` instruction.
15272    /// Assembly forms: `LDAXRH XD, [XN|SP]`.
15273    /// Operands: `rd`, `addr`.
15274    pub fn ldaxrh<T0, T1>(&mut self, rd: T0, addr: T1)
15275    where
15276        Self: LdaxrhEmitter<T0, T1>,
15277    {
15278        <Self as LdaxrhEmitter<T0, T1>>::ldaxrh(self, rd, addr);
15279    }
15280    /// Emits the `LDCLR` instruction.
15281    /// Assembly forms: `LDCLR WS, WD, [XN|SP]`; `LDCLR XS, XD, [XN|SP]`.
15282    /// Operands: `rs`, `rd`, `addr`.
15283    pub fn ldclr<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15284    where
15285        Self: LdclrEmitter<T0, T1, T2>,
15286    {
15287        <Self as LdclrEmitter<T0, T1, T2>>::ldclr(self, rs, rd, addr);
15288    }
15289    /// Emits the `LDCLRA` instruction.
15290    /// Assembly forms: `LDCLRA WS, WD, [XN|SP]`; `LDCLRA XS, XD, [XN|SP]`.
15291    /// Operands: `rs`, `rd`, `addr`.
15292    pub fn ldclra<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15293    where
15294        Self: LdclraEmitter<T0, T1, T2>,
15295    {
15296        <Self as LdclraEmitter<T0, T1, T2>>::ldclra(self, rs, rd, addr);
15297    }
15298    /// Emits the `LDCLRAB` instruction.
15299    /// Assembly forms: `LDCLRAB WS, WD, [XN|SP]`.
15300    /// Operands: `rs`, `rd`, `addr`.
15301    pub fn ldclrab<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15302    where
15303        Self: LdclrabEmitter<T0, T1, T2>,
15304    {
15305        <Self as LdclrabEmitter<T0, T1, T2>>::ldclrab(self, rs, rd, addr);
15306    }
15307    /// Emits the `LDCLRAH` instruction.
15308    /// Assembly forms: `LDCLRAH WS, WD, [XN|SP]`.
15309    /// Operands: `rs`, `rd`, `addr`.
15310    pub fn ldclrah<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15311    where
15312        Self: LdclrahEmitter<T0, T1, T2>,
15313    {
15314        <Self as LdclrahEmitter<T0, T1, T2>>::ldclrah(self, rs, rd, addr);
15315    }
15316    /// Emits the `LDCLRAL` instruction.
15317    /// Assembly forms: `LDCLRAL WS, WD, [XN|SP]`; `LDCLRAL XS, XD, [XN|SP]`.
15318    /// Operands: `rs`, `rd`, `addr`.
15319    pub fn ldclral<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15320    where
15321        Self: LdclralEmitter<T0, T1, T2>,
15322    {
15323        <Self as LdclralEmitter<T0, T1, T2>>::ldclral(self, rs, rd, addr);
15324    }
15325    /// Emits the `LDCLRALB` instruction.
15326    /// Assembly forms: `LDCLRALB WS, WD, [XN|SP]`.
15327    /// Operands: `rs`, `rd`, `addr`.
15328    pub fn ldclralb<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15329    where
15330        Self: LdclralbEmitter<T0, T1, T2>,
15331    {
15332        <Self as LdclralbEmitter<T0, T1, T2>>::ldclralb(self, rs, rd, addr);
15333    }
15334    /// Emits the `LDCLRALH` instruction.
15335    /// Assembly forms: `LDCLRALH WS, WD, [XN|SP]`.
15336    /// Operands: `rs`, `rd`, `addr`.
15337    pub fn ldclralh<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15338    where
15339        Self: LdclralhEmitter<T0, T1, T2>,
15340    {
15341        <Self as LdclralhEmitter<T0, T1, T2>>::ldclralh(self, rs, rd, addr);
15342    }
15343    /// Emits the `LDCLRB` instruction.
15344    /// Assembly forms: `LDCLRB WS, WD, [XN|SP]`.
15345    /// Operands: `rs`, `rd`, `addr`.
15346    pub fn ldclrb<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15347    where
15348        Self: LdclrbEmitter<T0, T1, T2>,
15349    {
15350        <Self as LdclrbEmitter<T0, T1, T2>>::ldclrb(self, rs, rd, addr);
15351    }
15352    /// Emits the `LDCLRH` instruction.
15353    /// Assembly forms: `LDCLRH WS, WD, [XN|SP]`.
15354    /// Operands: `rs`, `rd`, `addr`.
15355    pub fn ldclrh<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15356    where
15357        Self: LdclrhEmitter<T0, T1, T2>,
15358    {
15359        <Self as LdclrhEmitter<T0, T1, T2>>::ldclrh(self, rs, rd, addr);
15360    }
15361    /// Emits the `LDCLRL` instruction.
15362    /// Assembly forms: `LDCLRL WS, WD, [XN|SP]`; `LDCLRL XS, XD, [XN|SP]`.
15363    /// Operands: `rs`, `rd`, `addr`.
15364    pub fn ldclrl<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15365    where
15366        Self: LdclrlEmitter<T0, T1, T2>,
15367    {
15368        <Self as LdclrlEmitter<T0, T1, T2>>::ldclrl(self, rs, rd, addr);
15369    }
15370    /// Emits the `LDCLRLB` instruction.
15371    /// Assembly forms: `LDCLRLB WS, WD, [XN|SP]`.
15372    /// Operands: `rs`, `rd`, `addr`.
15373    pub fn ldclrlb<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15374    where
15375        Self: LdclrlbEmitter<T0, T1, T2>,
15376    {
15377        <Self as LdclrlbEmitter<T0, T1, T2>>::ldclrlb(self, rs, rd, addr);
15378    }
15379    /// Emits the `LDCLRLH` instruction.
15380    /// Assembly forms: `LDCLRLH WS, WD, [XN|SP]`.
15381    /// Operands: `rs`, `rd`, `addr`.
15382    pub fn ldclrlh<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15383    where
15384        Self: LdclrlhEmitter<T0, T1, T2>,
15385    {
15386        <Self as LdclrlhEmitter<T0, T1, T2>>::ldclrlh(self, rs, rd, addr);
15387    }
15388    /// Emits the `LDEOR` instruction.
15389    /// Assembly forms: `LDEOR WS, WD, [XN|SP]`; `LDEOR XS, XD, [XN|SP]`.
15390    /// Operands: `rs`, `rd`, `addr`.
15391    pub fn ldeor<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15392    where
15393        Self: LdeorEmitter<T0, T1, T2>,
15394    {
15395        <Self as LdeorEmitter<T0, T1, T2>>::ldeor(self, rs, rd, addr);
15396    }
15397    /// Emits the `LDEORA` instruction.
15398    /// Assembly forms: `LDEORA WS, WD, [XN|SP]`; `LDEORA XS, XD, [XN|SP]`.
15399    /// Operands: `rs`, `rd`, `addr`.
15400    pub fn ldeora<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15401    where
15402        Self: LdeoraEmitter<T0, T1, T2>,
15403    {
15404        <Self as LdeoraEmitter<T0, T1, T2>>::ldeora(self, rs, rd, addr);
15405    }
15406    /// Emits the `LDEORAB` instruction.
15407    /// Assembly forms: `LDEORAB WS, WD, [XN|SP]`.
15408    /// Operands: `rs`, `rd`, `addr`.
15409    pub fn ldeorab<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15410    where
15411        Self: LdeorabEmitter<T0, T1, T2>,
15412    {
15413        <Self as LdeorabEmitter<T0, T1, T2>>::ldeorab(self, rs, rd, addr);
15414    }
15415    /// Emits the `LDEORAH` instruction.
15416    /// Assembly forms: `LDEORAH WS, WD, [XN|SP]`.
15417    /// Operands: `rs`, `rd`, `addr`.
15418    pub fn ldeorah<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15419    where
15420        Self: LdeorahEmitter<T0, T1, T2>,
15421    {
15422        <Self as LdeorahEmitter<T0, T1, T2>>::ldeorah(self, rs, rd, addr);
15423    }
15424    /// Emits the `LDEORAL` instruction.
15425    /// Assembly forms: `LDEORAL WS, WD, [XN|SP]`; `LDEORAL XS, XD, [XN|SP]`.
15426    /// Operands: `rs`, `rd`, `addr`.
15427    pub fn ldeoral<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15428    where
15429        Self: LdeoralEmitter<T0, T1, T2>,
15430    {
15431        <Self as LdeoralEmitter<T0, T1, T2>>::ldeoral(self, rs, rd, addr);
15432    }
15433    /// Emits the `LDEORALB` instruction.
15434    /// Assembly forms: `LDEORALB WS, WD, [XN|SP]`.
15435    /// Operands: `rs`, `rd`, `addr`.
15436    pub fn ldeoralb<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15437    where
15438        Self: LdeoralbEmitter<T0, T1, T2>,
15439    {
15440        <Self as LdeoralbEmitter<T0, T1, T2>>::ldeoralb(self, rs, rd, addr);
15441    }
15442    /// Emits the `LDEORALH` instruction.
15443    /// Assembly forms: `LDEORALH WS, WD, [XN|SP]`.
15444    /// Operands: `rs`, `rd`, `addr`.
15445    pub fn ldeoralh<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15446    where
15447        Self: LdeoralhEmitter<T0, T1, T2>,
15448    {
15449        <Self as LdeoralhEmitter<T0, T1, T2>>::ldeoralh(self, rs, rd, addr);
15450    }
15451    /// Emits the `LDEORB` instruction.
15452    /// Assembly forms: `LDEORB WS, WD, [XN|SP]`.
15453    /// Operands: `rs`, `rd`, `addr`.
15454    pub fn ldeorb<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15455    where
15456        Self: LdeorbEmitter<T0, T1, T2>,
15457    {
15458        <Self as LdeorbEmitter<T0, T1, T2>>::ldeorb(self, rs, rd, addr);
15459    }
15460    /// Emits the `LDEORH` instruction.
15461    /// Assembly forms: `LDEORH WS, WD, [XN|SP]`.
15462    /// Operands: `rs`, `rd`, `addr`.
15463    pub fn ldeorh<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15464    where
15465        Self: LdeorhEmitter<T0, T1, T2>,
15466    {
15467        <Self as LdeorhEmitter<T0, T1, T2>>::ldeorh(self, rs, rd, addr);
15468    }
15469    /// Emits the `LDEORL` instruction.
15470    /// Assembly forms: `LDEORL WS, WD, [XN|SP]`; `LDEORL XS, XD, [XN|SP]`.
15471    /// Operands: `rs`, `rd`, `addr`.
15472    pub fn ldeorl<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15473    where
15474        Self: LdeorlEmitter<T0, T1, T2>,
15475    {
15476        <Self as LdeorlEmitter<T0, T1, T2>>::ldeorl(self, rs, rd, addr);
15477    }
15478    /// Emits the `LDEORLB` instruction.
15479    /// Assembly forms: `LDEORLB WS, WD, [XN|SP]`.
15480    /// Operands: `rs`, `rd`, `addr`.
15481    pub fn ldeorlb<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15482    where
15483        Self: LdeorlbEmitter<T0, T1, T2>,
15484    {
15485        <Self as LdeorlbEmitter<T0, T1, T2>>::ldeorlb(self, rs, rd, addr);
15486    }
15487    /// Emits the `LDEORLH` instruction.
15488    /// Assembly forms: `LDEORLH WS, WD, [XN|SP]`.
15489    /// Operands: `rs`, `rd`, `addr`.
15490    pub fn ldeorlh<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15491    where
15492        Self: LdeorlhEmitter<T0, T1, T2>,
15493    {
15494        <Self as LdeorlhEmitter<T0, T1, T2>>::ldeorlh(self, rs, rd, addr);
15495    }
15496    /// Emits the `LDLAR` instruction.
15497    /// Assembly forms: `LDLAR WD, [XN|SP]`; `LDLAR XD, [XN|SP]`.
15498    /// Operands: `rd`, `addr`.
15499    pub fn ldlar<T0, T1>(&mut self, rd: T0, addr: T1)
15500    where
15501        Self: LdlarEmitter<T0, T1>,
15502    {
15503        <Self as LdlarEmitter<T0, T1>>::ldlar(self, rd, addr);
15504    }
15505    /// Emits the `LDLARB` instruction.
15506    /// Assembly forms: `LDLARB WD, [XN|SP]`.
15507    /// Operands: `rd`, `addr`.
15508    pub fn ldlarb<T0, T1>(&mut self, rd: T0, addr: T1)
15509    where
15510        Self: LdlarbEmitter<T0, T1>,
15511    {
15512        <Self as LdlarbEmitter<T0, T1>>::ldlarb(self, rd, addr);
15513    }
15514    /// Emits the `LDLARH` instruction.
15515    /// Assembly forms: `LDLARH WD, [XN|SP]`.
15516    /// Operands: `rd`, `addr`.
15517    pub fn ldlarh<T0, T1>(&mut self, rd: T0, addr: T1)
15518    where
15519        Self: LdlarhEmitter<T0, T1>,
15520    {
15521        <Self as LdlarhEmitter<T0, T1>>::ldlarh(self, rd, addr);
15522    }
15523    /// Emits the `LDNP` instruction.
15524    /// Assembly forms: `LDNP WD, WD2, [XN|SP, #OFFS*4]`; `LDNP XD, XD2, [XN|SP, #OFFS*8]`; `LDNP SD, SD2, [XN|SP, #OFFS*4]`; `LDNP DD, DD2, [XN|SP, #OFFS*8]` (and related forms).
15525    /// Operands: `rd`, `rd2`, `addr`.
15526    pub fn ldnp<T0, T1, T2>(&mut self, rd: T0, rd2: T1, addr: T2)
15527    where
15528        Self: LdnpEmitter<T0, T1, T2>,
15529    {
15530        <Self as LdnpEmitter<T0, T1, T2>>::ldnp(self, rd, rd2, addr);
15531    }
15532    /// Emits the `LDP` instruction.
15533    /// Assembly forms: `LDP WD, WD2, [XN|SP, #OFFS*4]{@}{!}`; `LDP XD, XD2, [XN|SP, #OFFS*8]{@}{!}`; `LDP SD, SD2, [XN|SP, #OFFS*4]{@}{!}`; `LDP DD, DD2, [XN|SP, #OFFS*8]{@}{!}` (and related forms).
15534    /// Operands: `rd`, `rd2`, `addr`.
15535    pub fn ldp<T0, T1, T2>(&mut self, rd: T0, rd2: T1, addr: T2)
15536    where
15537        Self: LdpEmitter<T0, T1, T2>,
15538    {
15539        <Self as LdpEmitter<T0, T1, T2>>::ldp(self, rd, rd2, addr);
15540    }
15541    /// Emits the `LDPSW` instruction.
15542    /// Assembly forms: `LDPSW XD, XD2, [XN|SP, #OFFS*4]{@}{!}`.
15543    /// Operands: `rd`, `rd2`, `addr`.
15544    pub fn ldpsw<T0, T1, T2>(&mut self, rd: T0, rd2: T1, addr: T2)
15545    where
15546        Self: LdpswEmitter<T0, T1, T2>,
15547    {
15548        <Self as LdpswEmitter<T0, T1, T2>>::ldpsw(self, rd, rd2, addr);
15549    }
15550    /// Emits the `LDR` instruction.
15551    /// Assembly forms: `LDR WD, [XN|SP, #OFFZ*4]`; `LDR XD, [XN|SP, #OFFZ*8]`; `LDR WD, [XN|SP, #OFFS*4]@`; `LDR XD, [XN|SP, #OFFS*8]@` (and related forms).
15552    /// Operands: `rd`, `addr`.
15553    pub fn ldr<T0, T1>(&mut self, rd: T0, addr: T1)
15554    where
15555        Self: LdrEmitter<T0, T1>,
15556    {
15557        <Self as LdrEmitter<T0, T1>>::ldr(self, rd, addr);
15558    }
15559    /// Emits the `LDRB` instruction.
15560    /// Assembly forms: `LDRB WD, [XN|SP, #OFFZ]`; `LDRB WD, [XN|SP, #OFFS]@`; `LDRB WD, [XN|SP, #OFFS]!`; `LDRB WD, [XN|SP, RM, {UXTW|LSL|SXTW|SXTX #N}]`.
15561    /// Operands: `rd`, `addr`.
15562    pub fn ldrb<T0, T1>(&mut self, rd: T0, addr: T1)
15563    where
15564        Self: LdrbEmitter<T0, T1>,
15565    {
15566        <Self as LdrbEmitter<T0, T1>>::ldrb(self, rd, addr);
15567    }
15568    /// Emits the `LDRH` instruction.
15569    /// Assembly forms: `LDRH WD, [XN|SP, #OFFZ*2]`; `LDRH WD, [XN|SP, #OFFS*2]@`; `LDRH WD, [XN|SP, #OFFS*2]!`; `LDRH WD, [XN|SP, RM, {UXTW|LSL|SXTW|SXTX #N}]`.
15570    /// Operands: `rd`, `addr`.
15571    pub fn ldrh<T0, T1>(&mut self, rd: T0, addr: T1)
15572    where
15573        Self: LdrhEmitter<T0, T1>,
15574    {
15575        <Self as LdrhEmitter<T0, T1>>::ldrh(self, rd, addr);
15576    }
15577    /// Emits the `LDRSB` instruction.
15578    /// Assembly forms: `LDRSB WD, [XN|SP, #OFFZ]`; `LDRSB XD, [XN|SP, #OFFZ]`; `LDRSB WD, [XN|SP, #OFFS]@`; `LDRSB XD, [XN|SP, #OFFS]@` (and related forms).
15579    /// Operands: `rd`, `addr`.
15580    pub fn ldrsb<T0, T1>(&mut self, rd: T0, addr: T1)
15581    where
15582        Self: LdrsbEmitter<T0, T1>,
15583    {
15584        <Self as LdrsbEmitter<T0, T1>>::ldrsb(self, rd, addr);
15585    }
15586    /// Emits the `LDRSH` instruction.
15587    /// Assembly forms: `LDRSH WD, [XN|SP, #OFFZ*2]`; `LDRSH XD, [XN|SP, #OFFZ*2]`; `LDRSH WD, [XN|SP, #OFFS*2]@`; `LDRSH XD, [XN|SP, #OFFS*2]@` (and related forms).
15588    /// Operands: `rd`, `addr`.
15589    pub fn ldrsh<T0, T1>(&mut self, rd: T0, addr: T1)
15590    where
15591        Self: LdrshEmitter<T0, T1>,
15592    {
15593        <Self as LdrshEmitter<T0, T1>>::ldrsh(self, rd, addr);
15594    }
15595    /// Emits the `LDRSW` instruction.
15596    /// Assembly forms: `LDRSW XD, [XN|SP, #OFFZ*4]`; `LDRSW XD, [XN|SP, #OFFS*4]@`; `LDRSW XD, [XN|SP, #OFFS*4]!`; `LDRSW XD, [PC, #OFFS*4]` (and related forms).
15597    /// Operands: `rd`, `addr`.
15598    pub fn ldrsw<T0, T1>(&mut self, rd: T0, addr: T1)
15599    where
15600        Self: LdrswEmitter<T0, T1>,
15601    {
15602        <Self as LdrswEmitter<T0, T1>>::ldrsw(self, rd, addr);
15603    }
15604    /// Emits the `LDSET` instruction.
15605    /// Assembly forms: `LDSET WS, WD, [XN|SP]`; `LDSET XS, WD, [XN|SP]`.
15606    /// Operands: `rs`, `rd`, `addr`.
15607    pub fn ldset<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15608    where
15609        Self: LdsetEmitter<T0, T1, T2>,
15610    {
15611        <Self as LdsetEmitter<T0, T1, T2>>::ldset(self, rs, rd, addr);
15612    }
15613    /// Emits the `LDSETA` instruction.
15614    /// Assembly forms: `LDSETA WS, WD, [XN|SP]`; `LDSETA XS, WD, [XN|SP]`.
15615    /// Operands: `rs`, `rd`, `addr`.
15616    pub fn ldseta<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15617    where
15618        Self: LdsetaEmitter<T0, T1, T2>,
15619    {
15620        <Self as LdsetaEmitter<T0, T1, T2>>::ldseta(self, rs, rd, addr);
15621    }
15622    /// Emits the `LDSETAB` instruction.
15623    /// Assembly forms: `LDSETAB WS, WD, [XN|SP]`.
15624    /// Operands: `rs`, `rd`, `addr`.
15625    pub fn ldsetab<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15626    where
15627        Self: LdsetabEmitter<T0, T1, T2>,
15628    {
15629        <Self as LdsetabEmitter<T0, T1, T2>>::ldsetab(self, rs, rd, addr);
15630    }
15631    /// Emits the `LDSETAH` instruction.
15632    /// Assembly forms: `LDSETAH WS, WD, [XN|SP]`.
15633    /// Operands: `rs`, `rd`, `addr`.
15634    pub fn ldsetah<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15635    where
15636        Self: LdsetahEmitter<T0, T1, T2>,
15637    {
15638        <Self as LdsetahEmitter<T0, T1, T2>>::ldsetah(self, rs, rd, addr);
15639    }
15640    /// Emits the `LDSETAL` instruction.
15641    /// Assembly forms: `LDSETAL WS, WD, [XN|SP]`; `LDSETAL XS, WD, [XN|SP]`.
15642    /// Operands: `rs`, `rd`, `addr`.
15643    pub fn ldsetal<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15644    where
15645        Self: LdsetalEmitter<T0, T1, T2>,
15646    {
15647        <Self as LdsetalEmitter<T0, T1, T2>>::ldsetal(self, rs, rd, addr);
15648    }
15649    /// Emits the `LDSETALB` instruction.
15650    /// Assembly forms: `LDSETALB WS, WD, [XN|SP]`.
15651    /// Operands: `rs`, `rd`, `addr`.
15652    pub fn ldsetalb<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15653    where
15654        Self: LdsetalbEmitter<T0, T1, T2>,
15655    {
15656        <Self as LdsetalbEmitter<T0, T1, T2>>::ldsetalb(self, rs, rd, addr);
15657    }
15658    /// Emits the `LDSETALH` instruction.
15659    /// Assembly forms: `LDSETALH WS, WD, [XN|SP]`.
15660    /// Operands: `rs`, `rd`, `addr`.
15661    pub fn ldsetalh<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15662    where
15663        Self: LdsetalhEmitter<T0, T1, T2>,
15664    {
15665        <Self as LdsetalhEmitter<T0, T1, T2>>::ldsetalh(self, rs, rd, addr);
15666    }
15667    /// Emits the `LDSETB` instruction.
15668    /// Assembly forms: `LDSETB WS, WD, [XN|SP]`.
15669    /// Operands: `rs`, `rd`, `addr`.
15670    pub fn ldsetb<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15671    where
15672        Self: LdsetbEmitter<T0, T1, T2>,
15673    {
15674        <Self as LdsetbEmitter<T0, T1, T2>>::ldsetb(self, rs, rd, addr);
15675    }
15676    /// Emits the `LDSETH` instruction.
15677    /// Assembly forms: `LDSETH WS, WD, [XN|SP]`.
15678    /// Operands: `rs`, `rd`, `addr`.
15679    pub fn ldseth<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15680    where
15681        Self: LdsethEmitter<T0, T1, T2>,
15682    {
15683        <Self as LdsethEmitter<T0, T1, T2>>::ldseth(self, rs, rd, addr);
15684    }
15685    /// Emits the `LDSETL` instruction.
15686    /// Assembly forms: `LDSETL WS, WD, [XN|SP]`; `LDSETL XS, WD, [XN|SP]`.
15687    /// Operands: `rs`, `rd`, `addr`.
15688    pub fn ldsetl<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15689    where
15690        Self: LdsetlEmitter<T0, T1, T2>,
15691    {
15692        <Self as LdsetlEmitter<T0, T1, T2>>::ldsetl(self, rs, rd, addr);
15693    }
15694    /// Emits the `LDSETLB` instruction.
15695    /// Assembly forms: `LDSETLB WS, WD, [XN|SP]`.
15696    /// Operands: `rs`, `rd`, `addr`.
15697    pub fn ldsetlb<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15698    where
15699        Self: LdsetlbEmitter<T0, T1, T2>,
15700    {
15701        <Self as LdsetlbEmitter<T0, T1, T2>>::ldsetlb(self, rs, rd, addr);
15702    }
15703    /// Emits the `LDSETLH` instruction.
15704    /// Assembly forms: `LDSETLH WS, WD, [XN|SP]`.
15705    /// Operands: `rs`, `rd`, `addr`.
15706    pub fn ldsetlh<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15707    where
15708        Self: LdsetlhEmitter<T0, T1, T2>,
15709    {
15710        <Self as LdsetlhEmitter<T0, T1, T2>>::ldsetlh(self, rs, rd, addr);
15711    }
15712    /// Emits the `LDSMAX` instruction.
15713    /// Assembly forms: `LDSMAX WS, WD, [XN|SP]`; `LDSMAX XS, XD, [XN|SP]`.
15714    /// Operands: `rs`, `rd`, `addr`.
15715    pub fn ldsmax<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15716    where
15717        Self: LdsmaxEmitter<T0, T1, T2>,
15718    {
15719        <Self as LdsmaxEmitter<T0, T1, T2>>::ldsmax(self, rs, rd, addr);
15720    }
15721    /// Emits the `LDSMAXA` instruction.
15722    /// Assembly forms: `LDSMAXA WS, WD, [XN|SP]`; `LDSMAXA XS, XD, [XN|SP]`.
15723    /// Operands: `rs`, `rd`, `addr`.
15724    pub fn ldsmaxa<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15725    where
15726        Self: LdsmaxaEmitter<T0, T1, T2>,
15727    {
15728        <Self as LdsmaxaEmitter<T0, T1, T2>>::ldsmaxa(self, rs, rd, addr);
15729    }
15730    /// Emits the `LDSMAXAB` instruction.
15731    /// Assembly forms: `LDSMAXAB WS, WD, [XN|SP]`.
15732    /// Operands: `rs`, `rd`, `addr`.
15733    pub fn ldsmaxab<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15734    where
15735        Self: LdsmaxabEmitter<T0, T1, T2>,
15736    {
15737        <Self as LdsmaxabEmitter<T0, T1, T2>>::ldsmaxab(self, rs, rd, addr);
15738    }
15739    /// Emits the `LDSMAXAH` instruction.
15740    /// Assembly forms: `LDSMAXAH WS, WD, [XN|SP]`.
15741    /// Operands: `rs`, `rd`, `addr`.
15742    pub fn ldsmaxah<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15743    where
15744        Self: LdsmaxahEmitter<T0, T1, T2>,
15745    {
15746        <Self as LdsmaxahEmitter<T0, T1, T2>>::ldsmaxah(self, rs, rd, addr);
15747    }
15748    /// Emits the `LDSMAXAL` instruction.
15749    /// Assembly forms: `LDSMAXAL WS, WD, [XN|SP]`; `LDSMAXAL XS, XD, [XN|SP]`.
15750    /// Operands: `rs`, `rd`, `addr`.
15751    pub fn ldsmaxal<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15752    where
15753        Self: LdsmaxalEmitter<T0, T1, T2>,
15754    {
15755        <Self as LdsmaxalEmitter<T0, T1, T2>>::ldsmaxal(self, rs, rd, addr);
15756    }
15757    /// Emits the `LDSMAXALB` instruction.
15758    /// Assembly forms: `LDSMAXALB WS, WD, [XN|SP]`.
15759    /// Operands: `rs`, `rd`, `addr`.
15760    pub fn ldsmaxalb<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15761    where
15762        Self: LdsmaxalbEmitter<T0, T1, T2>,
15763    {
15764        <Self as LdsmaxalbEmitter<T0, T1, T2>>::ldsmaxalb(self, rs, rd, addr);
15765    }
15766    /// Emits the `LDSMAXALH` instruction.
15767    /// Assembly forms: `LDSMAXALH WS, WD, [XN|SP]`.
15768    /// Operands: `rs`, `rd`, `addr`.
15769    pub fn ldsmaxalh<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15770    where
15771        Self: LdsmaxalhEmitter<T0, T1, T2>,
15772    {
15773        <Self as LdsmaxalhEmitter<T0, T1, T2>>::ldsmaxalh(self, rs, rd, addr);
15774    }
15775    /// Emits the `LDSMAXB` instruction.
15776    /// Assembly forms: `LDSMAXB WS, WD, [XN|SP]`.
15777    /// Operands: `rs`, `rd`, `addr`.
15778    pub fn ldsmaxb<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15779    where
15780        Self: LdsmaxbEmitter<T0, T1, T2>,
15781    {
15782        <Self as LdsmaxbEmitter<T0, T1, T2>>::ldsmaxb(self, rs, rd, addr);
15783    }
15784    /// Emits the `LDSMAXH` instruction.
15785    /// Assembly forms: `LDSMAXH WS, WD, [XN|SP]`.
15786    /// Operands: `rs`, `rd`, `addr`.
15787    pub fn ldsmaxh<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15788    where
15789        Self: LdsmaxhEmitter<T0, T1, T2>,
15790    {
15791        <Self as LdsmaxhEmitter<T0, T1, T2>>::ldsmaxh(self, rs, rd, addr);
15792    }
15793    /// Emits the `LDSMAXL` instruction.
15794    /// Assembly forms: `LDSMAXL WS, WD, [XN|SP]`; `LDSMAXL XS, XD, [XN|SP]`.
15795    /// Operands: `rs`, `rd`, `addr`.
15796    pub fn ldsmaxl<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15797    where
15798        Self: LdsmaxlEmitter<T0, T1, T2>,
15799    {
15800        <Self as LdsmaxlEmitter<T0, T1, T2>>::ldsmaxl(self, rs, rd, addr);
15801    }
15802    /// Emits the `LDSMAXLB` instruction.
15803    /// Assembly forms: `LDSMAXLB WS, WD, [XN|SP]`.
15804    /// Operands: `rs`, `rd`, `addr`.
15805    pub fn ldsmaxlb<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15806    where
15807        Self: LdsmaxlbEmitter<T0, T1, T2>,
15808    {
15809        <Self as LdsmaxlbEmitter<T0, T1, T2>>::ldsmaxlb(self, rs, rd, addr);
15810    }
15811    /// Emits the `LDSMAXLH` instruction.
15812    /// Assembly forms: `LDSMAXLH WS, WD, [XN|SP]`.
15813    /// Operands: `rs`, `rd`, `addr`.
15814    pub fn ldsmaxlh<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15815    where
15816        Self: LdsmaxlhEmitter<T0, T1, T2>,
15817    {
15818        <Self as LdsmaxlhEmitter<T0, T1, T2>>::ldsmaxlh(self, rs, rd, addr);
15819    }
15820    /// Emits the `LDSMIN` instruction.
15821    /// Assembly forms: `LDSMIN WS, WD, [XN|SP]`; `LDSMIN XS, XD, [XN|SP]`.
15822    /// Operands: `rs`, `rd`, `addr`.
15823    pub fn ldsmin<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15824    where
15825        Self: LdsminEmitter<T0, T1, T2>,
15826    {
15827        <Self as LdsminEmitter<T0, T1, T2>>::ldsmin(self, rs, rd, addr);
15828    }
15829    /// Emits the `LDSMINA` instruction.
15830    /// Assembly forms: `LDSMINA WS, WD, [XN|SP]`; `LDSMINA XS, XD, [XN|SP]`.
15831    /// Operands: `rs`, `rd`, `addr`.
15832    pub fn ldsmina<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15833    where
15834        Self: LdsminaEmitter<T0, T1, T2>,
15835    {
15836        <Self as LdsminaEmitter<T0, T1, T2>>::ldsmina(self, rs, rd, addr);
15837    }
15838    /// Emits the `LDSMINAB` instruction.
15839    /// Assembly forms: `LDSMINAB WS, WD, [XN|SP]`.
15840    /// Operands: `rs`, `rd`, `addr`.
15841    pub fn ldsminab<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15842    where
15843        Self: LdsminabEmitter<T0, T1, T2>,
15844    {
15845        <Self as LdsminabEmitter<T0, T1, T2>>::ldsminab(self, rs, rd, addr);
15846    }
15847    /// Emits the `LDSMINAH` instruction.
15848    /// Assembly forms: `LDSMINAH WS, WD, [XN|SP]`.
15849    /// Operands: `rs`, `rd`, `addr`.
15850    pub fn ldsminah<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15851    where
15852        Self: LdsminahEmitter<T0, T1, T2>,
15853    {
15854        <Self as LdsminahEmitter<T0, T1, T2>>::ldsminah(self, rs, rd, addr);
15855    }
15856    /// Emits the `LDSMINAL` instruction.
15857    /// Assembly forms: `LDSMINAL WS, WD, [XN|SP]`; `LDSMINAL XS, XD, [XN|SP]`.
15858    /// Operands: `rs`, `rd`, `addr`.
15859    pub fn ldsminal<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15860    where
15861        Self: LdsminalEmitter<T0, T1, T2>,
15862    {
15863        <Self as LdsminalEmitter<T0, T1, T2>>::ldsminal(self, rs, rd, addr);
15864    }
15865    /// Emits the `LDSMINALB` instruction.
15866    /// Assembly forms: `LDSMINALB WS, WD, [XN|SP]`.
15867    /// Operands: `rs`, `rd`, `addr`.
15868    pub fn ldsminalb<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15869    where
15870        Self: LdsminalbEmitter<T0, T1, T2>,
15871    {
15872        <Self as LdsminalbEmitter<T0, T1, T2>>::ldsminalb(self, rs, rd, addr);
15873    }
15874    /// Emits the `LDSMINALH` instruction.
15875    /// Assembly forms: `LDSMINALH WS, WD, [XN|SP]`.
15876    /// Operands: `rs`, `rd`, `addr`.
15877    pub fn ldsminalh<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15878    where
15879        Self: LdsminalhEmitter<T0, T1, T2>,
15880    {
15881        <Self as LdsminalhEmitter<T0, T1, T2>>::ldsminalh(self, rs, rd, addr);
15882    }
15883    /// Emits the `LDSMINB` instruction.
15884    /// Assembly forms: `LDSMINB WS, WD, [XN|SP]`.
15885    /// Operands: `rs`, `rd`, `addr`.
15886    pub fn ldsminb<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15887    where
15888        Self: LdsminbEmitter<T0, T1, T2>,
15889    {
15890        <Self as LdsminbEmitter<T0, T1, T2>>::ldsminb(self, rs, rd, addr);
15891    }
15892    /// Emits the `LDSMINH` instruction.
15893    /// Assembly forms: `LDSMINH WS, WD, [XN|SP]`.
15894    /// Operands: `rs`, `rd`, `addr`.
15895    pub fn ldsminh<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15896    where
15897        Self: LdsminhEmitter<T0, T1, T2>,
15898    {
15899        <Self as LdsminhEmitter<T0, T1, T2>>::ldsminh(self, rs, rd, addr);
15900    }
15901    /// Emits the `LDSMINL` instruction.
15902    /// Assembly forms: `LDSMINL WS, WD, [XN|SP]`; `LDSMINL XS, XD, [XN|SP]`.
15903    /// Operands: `rs`, `rd`, `addr`.
15904    pub fn ldsminl<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15905    where
15906        Self: LdsminlEmitter<T0, T1, T2>,
15907    {
15908        <Self as LdsminlEmitter<T0, T1, T2>>::ldsminl(self, rs, rd, addr);
15909    }
15910    /// Emits the `LDSMINLB` instruction.
15911    /// Assembly forms: `LDSMINLB WS, WD, [XN|SP]`.
15912    /// Operands: `rs`, `rd`, `addr`.
15913    pub fn ldsminlb<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15914    where
15915        Self: LdsminlbEmitter<T0, T1, T2>,
15916    {
15917        <Self as LdsminlbEmitter<T0, T1, T2>>::ldsminlb(self, rs, rd, addr);
15918    }
15919    /// Emits the `LDSMINLH` instruction.
15920    /// Assembly forms: `LDSMINLH WS, WD, [XN|SP]`.
15921    /// Operands: `rs`, `rd`, `addr`.
15922    pub fn ldsminlh<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15923    where
15924        Self: LdsminlhEmitter<T0, T1, T2>,
15925    {
15926        <Self as LdsminlhEmitter<T0, T1, T2>>::ldsminlh(self, rs, rd, addr);
15927    }
15928    /// Emits the `LDTR` instruction.
15929    /// Assembly forms: `LDTR WD, [XN|SP, #OFFS]`; `LDTR XD, [XN|SP, #OFFS]`.
15930    /// Operands: `rd`, `addr`.
15931    pub fn ldtr<T0, T1>(&mut self, rd: T0, addr: T1)
15932    where
15933        Self: LdtrEmitter<T0, T1>,
15934    {
15935        <Self as LdtrEmitter<T0, T1>>::ldtr(self, rd, addr);
15936    }
15937    /// Emits the `LDTRB` instruction.
15938    /// Assembly forms: `LDTRB WD, [XN|SP, #OFFS]`.
15939    /// Operands: `rd`, `addr`.
15940    pub fn ldtrb<T0, T1>(&mut self, rd: T0, addr: T1)
15941    where
15942        Self: LdtrbEmitter<T0, T1>,
15943    {
15944        <Self as LdtrbEmitter<T0, T1>>::ldtrb(self, rd, addr);
15945    }
15946    /// Emits the `LDTRH` instruction.
15947    /// Assembly forms: `LDTRH WD, [XN|SP, #OFFS]`.
15948    /// Operands: `rd`, `addr`.
15949    pub fn ldtrh<T0, T1>(&mut self, rd: T0, addr: T1)
15950    where
15951        Self: LdtrhEmitter<T0, T1>,
15952    {
15953        <Self as LdtrhEmitter<T0, T1>>::ldtrh(self, rd, addr);
15954    }
15955    /// Emits the `LDTRSB` instruction.
15956    /// Assembly forms: `LDTRSB WD, [XN|SP, #OFFS]`; `LDTRSB XD, [XN|SP, #OFFS]`.
15957    /// Operands: `rd`, `addr`.
15958    pub fn ldtrsb<T0, T1>(&mut self, rd: T0, addr: T1)
15959    where
15960        Self: LdtrsbEmitter<T0, T1>,
15961    {
15962        <Self as LdtrsbEmitter<T0, T1>>::ldtrsb(self, rd, addr);
15963    }
15964    /// Emits the `LDTRSH` instruction.
15965    /// Assembly forms: `LDTRSH WD, [XN|SP, #OFFS]`; `LDTRSH XD, [XN|SP, #OFFS]`.
15966    /// Operands: `rd`, `addr`.
15967    pub fn ldtrsh<T0, T1>(&mut self, rd: T0, addr: T1)
15968    where
15969        Self: LdtrshEmitter<T0, T1>,
15970    {
15971        <Self as LdtrshEmitter<T0, T1>>::ldtrsh(self, rd, addr);
15972    }
15973    /// Emits the `LDTRSW` instruction.
15974    /// Assembly forms: `LDTRSW XD, [XN|SP, #OFFS]`.
15975    /// Operands: `rd`, `addr`.
15976    pub fn ldtrsw<T0, T1>(&mut self, rd: T0, addr: T1)
15977    where
15978        Self: LdtrswEmitter<T0, T1>,
15979    {
15980        <Self as LdtrswEmitter<T0, T1>>::ldtrsw(self, rd, addr);
15981    }
15982    /// Emits the `LDUMAX` instruction.
15983    /// Assembly forms: `LDUMAX WS, WD, [XN|SP]`; `LDUMAX XS, XD, [XN|SP]`.
15984    /// Operands: `rs`, `rd`, `addr`.
15985    pub fn ldumax<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15986    where
15987        Self: LdumaxEmitter<T0, T1, T2>,
15988    {
15989        <Self as LdumaxEmitter<T0, T1, T2>>::ldumax(self, rs, rd, addr);
15990    }
15991    /// Emits the `LDUMAXA` instruction.
15992    /// Assembly forms: `LDUMAXA WS, WD, [XN|SP]`; `LDUMAXA XS, XD, [XN|SP]`.
15993    /// Operands: `rs`, `rd`, `addr`.
15994    pub fn ldumaxa<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
15995    where
15996        Self: LdumaxaEmitter<T0, T1, T2>,
15997    {
15998        <Self as LdumaxaEmitter<T0, T1, T2>>::ldumaxa(self, rs, rd, addr);
15999    }
16000    /// Emits the `LDUMAXAB` instruction.
16001    /// Assembly forms: `LDUMAXAB WS, WD, [XN|SP]`.
16002    /// Operands: `rs`, `rd`, `addr`.
16003    pub fn ldumaxab<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
16004    where
16005        Self: LdumaxabEmitter<T0, T1, T2>,
16006    {
16007        <Self as LdumaxabEmitter<T0, T1, T2>>::ldumaxab(self, rs, rd, addr);
16008    }
16009    /// Emits the `LDUMAXAH` instruction.
16010    /// Assembly forms: `LDUMAXAH WS, WD, [XN|SP]`.
16011    /// Operands: `rs`, `rd`, `addr`.
16012    pub fn ldumaxah<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
16013    where
16014        Self: LdumaxahEmitter<T0, T1, T2>,
16015    {
16016        <Self as LdumaxahEmitter<T0, T1, T2>>::ldumaxah(self, rs, rd, addr);
16017    }
16018    /// Emits the `LDUMAXAL` instruction.
16019    /// Assembly forms: `LDUMAXAL WS, WD, [XN|SP]`; `LDUMAXAL XS, XD, [XN|SP]`.
16020    /// Operands: `rs`, `rd`, `addr`.
16021    pub fn ldumaxal<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
16022    where
16023        Self: LdumaxalEmitter<T0, T1, T2>,
16024    {
16025        <Self as LdumaxalEmitter<T0, T1, T2>>::ldumaxal(self, rs, rd, addr);
16026    }
16027    /// Emits the `LDUMAXALB` instruction.
16028    /// Assembly forms: `LDUMAXALB WS, WD, [XN|SP]`.
16029    /// Operands: `rs`, `rd`, `addr`.
16030    pub fn ldumaxalb<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
16031    where
16032        Self: LdumaxalbEmitter<T0, T1, T2>,
16033    {
16034        <Self as LdumaxalbEmitter<T0, T1, T2>>::ldumaxalb(self, rs, rd, addr);
16035    }
16036    /// Emits the `LDUMAXALH` instruction.
16037    /// Assembly forms: `LDUMAXALH WS, WD, [XN|SP]`.
16038    /// Operands: `rs`, `rd`, `addr`.
16039    pub fn ldumaxalh<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
16040    where
16041        Self: LdumaxalhEmitter<T0, T1, T2>,
16042    {
16043        <Self as LdumaxalhEmitter<T0, T1, T2>>::ldumaxalh(self, rs, rd, addr);
16044    }
16045    /// Emits the `LDUMAXB` instruction.
16046    /// Assembly forms: `LDUMAXB WS, WD, [XN|SP]`.
16047    /// Operands: `rs`, `rd`, `addr`.
16048    pub fn ldumaxb<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
16049    where
16050        Self: LdumaxbEmitter<T0, T1, T2>,
16051    {
16052        <Self as LdumaxbEmitter<T0, T1, T2>>::ldumaxb(self, rs, rd, addr);
16053    }
16054    /// Emits the `LDUMAXH` instruction.
16055    /// Assembly forms: `LDUMAXH WS, WD, [XN|SP]`.
16056    /// Operands: `rs`, `rd`, `addr`.
16057    pub fn ldumaxh<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
16058    where
16059        Self: LdumaxhEmitter<T0, T1, T2>,
16060    {
16061        <Self as LdumaxhEmitter<T0, T1, T2>>::ldumaxh(self, rs, rd, addr);
16062    }
16063    /// Emits the `LDUMAXL` instruction.
16064    /// Assembly forms: `LDUMAXL WS, WD, [XN|SP]`; `LDUMAXL XS, XD, [XN|SP]`.
16065    /// Operands: `rs`, `rd`, `addr`.
16066    pub fn ldumaxl<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
16067    where
16068        Self: LdumaxlEmitter<T0, T1, T2>,
16069    {
16070        <Self as LdumaxlEmitter<T0, T1, T2>>::ldumaxl(self, rs, rd, addr);
16071    }
16072    /// Emits the `LDUMAXLB` instruction.
16073    /// Assembly forms: `LDUMAXLB WS, WD, [XN|SP]`.
16074    /// Operands: `rs`, `rd`, `addr`.
16075    pub fn ldumaxlb<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
16076    where
16077        Self: LdumaxlbEmitter<T0, T1, T2>,
16078    {
16079        <Self as LdumaxlbEmitter<T0, T1, T2>>::ldumaxlb(self, rs, rd, addr);
16080    }
16081    /// Emits the `LDUMAXLH` instruction.
16082    /// Assembly forms: `LDUMAXLH WS, WD, [XN|SP]`.
16083    /// Operands: `rs`, `rd`, `addr`.
16084    pub fn ldumaxlh<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
16085    where
16086        Self: LdumaxlhEmitter<T0, T1, T2>,
16087    {
16088        <Self as LdumaxlhEmitter<T0, T1, T2>>::ldumaxlh(self, rs, rd, addr);
16089    }
16090    /// Emits the `LDUMIN` instruction.
16091    /// Assembly forms: `LDUMIN WS, WD, [XN|SP]`; `LDUMIN XS, XD, [XN|SP]`.
16092    /// Operands: `rs`, `rd`, `addr`.
16093    pub fn ldumin<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
16094    where
16095        Self: LduminEmitter<T0, T1, T2>,
16096    {
16097        <Self as LduminEmitter<T0, T1, T2>>::ldumin(self, rs, rd, addr);
16098    }
16099    /// Emits the `LDUMINA` instruction.
16100    /// Assembly forms: `LDUMINA WS, WD, [XN|SP]`; `LDUMINA XS, XD, [XN|SP]`.
16101    /// Operands: `rs`, `rd`, `addr`.
16102    pub fn ldumina<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
16103    where
16104        Self: LduminaEmitter<T0, T1, T2>,
16105    {
16106        <Self as LduminaEmitter<T0, T1, T2>>::ldumina(self, rs, rd, addr);
16107    }
16108    /// Emits the `LDUMINAB` instruction.
16109    /// Assembly forms: `LDUMINAB WS, WD, [XN|SP]`.
16110    /// Operands: `rs`, `rd`, `addr`.
16111    pub fn lduminab<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
16112    where
16113        Self: LduminabEmitter<T0, T1, T2>,
16114    {
16115        <Self as LduminabEmitter<T0, T1, T2>>::lduminab(self, rs, rd, addr);
16116    }
16117    /// Emits the `LDUMINAH` instruction.
16118    /// Assembly forms: `LDUMINAH WS, WD, [XN|SP]`.
16119    /// Operands: `rs`, `rd`, `addr`.
16120    pub fn lduminah<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
16121    where
16122        Self: LduminahEmitter<T0, T1, T2>,
16123    {
16124        <Self as LduminahEmitter<T0, T1, T2>>::lduminah(self, rs, rd, addr);
16125    }
16126    /// Emits the `LDUMINAL` instruction.
16127    /// Assembly forms: `LDUMINAL WS, WD, [XN|SP]`; `LDUMINAL XS, XD, [XN|SP]`.
16128    /// Operands: `rs`, `rd`, `addr`.
16129    pub fn lduminal<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
16130    where
16131        Self: LduminalEmitter<T0, T1, T2>,
16132    {
16133        <Self as LduminalEmitter<T0, T1, T2>>::lduminal(self, rs, rd, addr);
16134    }
16135    /// Emits the `LDUMINALB` instruction.
16136    /// Assembly forms: `LDUMINALB WS, WD, [XN|SP]`.
16137    /// Operands: `rs`, `rd`, `addr`.
16138    pub fn lduminalb<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
16139    where
16140        Self: LduminalbEmitter<T0, T1, T2>,
16141    {
16142        <Self as LduminalbEmitter<T0, T1, T2>>::lduminalb(self, rs, rd, addr);
16143    }
16144    /// Emits the `LDUMINALH` instruction.
16145    /// Assembly forms: `LDUMINALH WS, WD, [XN|SP]`.
16146    /// Operands: `rs`, `rd`, `addr`.
16147    pub fn lduminalh<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
16148    where
16149        Self: LduminalhEmitter<T0, T1, T2>,
16150    {
16151        <Self as LduminalhEmitter<T0, T1, T2>>::lduminalh(self, rs, rd, addr);
16152    }
16153    /// Emits the `LDUMINB` instruction.
16154    /// Assembly forms: `LDUMINB WS, WD, [XN|SP]`.
16155    /// Operands: `rs`, `rd`, `addr`.
16156    pub fn lduminb<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
16157    where
16158        Self: LduminbEmitter<T0, T1, T2>,
16159    {
16160        <Self as LduminbEmitter<T0, T1, T2>>::lduminb(self, rs, rd, addr);
16161    }
16162    /// Emits the `LDUMINH` instruction.
16163    /// Assembly forms: `LDUMINH WS, WD, [XN|SP]`.
16164    /// Operands: `rs`, `rd`, `addr`.
16165    pub fn lduminh<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
16166    where
16167        Self: LduminhEmitter<T0, T1, T2>,
16168    {
16169        <Self as LduminhEmitter<T0, T1, T2>>::lduminh(self, rs, rd, addr);
16170    }
16171    /// Emits the `LDUMINL` instruction.
16172    /// Assembly forms: `LDUMINL WS, WD, [XN|SP]`; `LDUMINL XS, XD, [XN|SP]`.
16173    /// Operands: `rs`, `rd`, `addr`.
16174    pub fn lduminl<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
16175    where
16176        Self: LduminlEmitter<T0, T1, T2>,
16177    {
16178        <Self as LduminlEmitter<T0, T1, T2>>::lduminl(self, rs, rd, addr);
16179    }
16180    /// Emits the `LDUMINLB` instruction.
16181    /// Assembly forms: `LDUMINLB WS, WD, [XN|SP]`.
16182    /// Operands: `rs`, `rd`, `addr`.
16183    pub fn lduminlb<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
16184    where
16185        Self: LduminlbEmitter<T0, T1, T2>,
16186    {
16187        <Self as LduminlbEmitter<T0, T1, T2>>::lduminlb(self, rs, rd, addr);
16188    }
16189    /// Emits the `LDUMINLH` instruction.
16190    /// Assembly forms: `LDUMINLH WS, WD, [XN|SP]`.
16191    /// Operands: `rs`, `rd`, `addr`.
16192    pub fn lduminlh<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
16193    where
16194        Self: LduminlhEmitter<T0, T1, T2>,
16195    {
16196        <Self as LduminlhEmitter<T0, T1, T2>>::lduminlh(self, rs, rd, addr);
16197    }
16198    /// Emits the `LDUR` instruction.
16199    /// Assembly forms: `LDUR WD, [XN|SP, #OFFS]`; `LDUR XD, [XN|SP, #OFFS]`; `LDUR BD, [XN|SP, #OFFS]`; `LDUR HD, [XN|SP, #OFFS]` (and related forms).
16200    /// Operands: `rd`, `addr`.
16201    pub fn ldur<T0, T1>(&mut self, rd: T0, addr: T1)
16202    where
16203        Self: LdurEmitter<T0, T1>,
16204    {
16205        <Self as LdurEmitter<T0, T1>>::ldur(self, rd, addr);
16206    }
16207    /// Emits the `LDURB` instruction.
16208    /// Assembly forms: `LDURB WD, [XN|SP, #OFFS]`.
16209    /// Operands: `rd`, `addr`.
16210    pub fn ldurb<T0, T1>(&mut self, rd: T0, addr: T1)
16211    where
16212        Self: LdurbEmitter<T0, T1>,
16213    {
16214        <Self as LdurbEmitter<T0, T1>>::ldurb(self, rd, addr);
16215    }
16216    /// Emits the `LDURH` instruction.
16217    /// Assembly forms: `LDURH WD, [XN|SP, #OFFS]`.
16218    /// Operands: `rd`, `addr`.
16219    pub fn ldurh<T0, T1>(&mut self, rd: T0, addr: T1)
16220    where
16221        Self: LdurhEmitter<T0, T1>,
16222    {
16223        <Self as LdurhEmitter<T0, T1>>::ldurh(self, rd, addr);
16224    }
16225    /// Emits the `LDURSB` instruction.
16226    /// Assembly forms: `LDURSB WD, [XN|SP, #OFFS]`; `LDURSB XD, [XN|SP, #OFFS]`.
16227    /// Operands: `rd`, `addr`.
16228    pub fn ldursb<T0, T1>(&mut self, rd: T0, addr: T1)
16229    where
16230        Self: LdursbEmitter<T0, T1>,
16231    {
16232        <Self as LdursbEmitter<T0, T1>>::ldursb(self, rd, addr);
16233    }
16234    /// Emits the `LDURSH` instruction.
16235    /// Assembly forms: `LDURSH WD, [XN|SP, #OFFS]`; `LDURSH XD, [XN|SP, #OFFS]`.
16236    /// Operands: `rd`, `addr`.
16237    pub fn ldursh<T0, T1>(&mut self, rd: T0, addr: T1)
16238    where
16239        Self: LdurshEmitter<T0, T1>,
16240    {
16241        <Self as LdurshEmitter<T0, T1>>::ldursh(self, rd, addr);
16242    }
16243    /// Emits the `LDURSW` instruction.
16244    /// Assembly forms: `LDURSW XD, [XN|SP, #OFFS]`.
16245    /// Operands: `rd`, `addr`.
16246    pub fn ldursw<T0, T1>(&mut self, rd: T0, addr: T1)
16247    where
16248        Self: LdurswEmitter<T0, T1>,
16249    {
16250        <Self as LdurswEmitter<T0, T1>>::ldursw(self, rd, addr);
16251    }
16252    /// Emits the `LDXP` instruction.
16253    /// Assembly forms: `LDXP WD, WD2, [XN|SP, #OFFS*4]`; `LDXP XD, XD2, [XN|SP, #OFFS*8]`.
16254    /// Operands: `rd`, `rd2`, `addr`.
16255    pub fn ldxp<T0, T1, T2>(&mut self, rd: T0, rd2: T1, addr: T2)
16256    where
16257        Self: LdxpEmitter<T0, T1, T2>,
16258    {
16259        <Self as LdxpEmitter<T0, T1, T2>>::ldxp(self, rd, rd2, addr);
16260    }
16261    /// Emits the `LDAXP` instruction.
16262    /// Assembly forms: `LDAXP WD, WD2, [XN|SP]`; `LDAXP XD, XD2, [XN|SP]`.
16263    /// Operands: `rd`, `rd2`, `addr`.
16264    pub fn ldaxp<T0, T1, T2>(&mut self, rd: T0, rd2: T1, addr: T2)
16265    where
16266        Self: LdaxpEmitter<T0, T1, T2>,
16267    {
16268        <Self as LdaxpEmitter<T0, T1, T2>>::ldaxp(self, rd, rd2, addr);
16269    }
16270    /// Emits the `LDXR` instruction.
16271    /// Assembly forms: `LDXR WD, [XN|SP]`; `LDXR XD, [XN|SP]`.
16272    /// Operands: `rd`, `addr`.
16273    pub fn ldxr<T0, T1>(&mut self, rd: T0, addr: T1)
16274    where
16275        Self: LdxrEmitter<T0, T1>,
16276    {
16277        <Self as LdxrEmitter<T0, T1>>::ldxr(self, rd, addr);
16278    }
16279    /// Emits the `LDXRB` instruction.
16280    /// Assembly forms: `LDXRB WD, [XN|SP]`.
16281    /// Operands: `rd`, `addr`.
16282    pub fn ldxrb<T0, T1>(&mut self, rd: T0, addr: T1)
16283    where
16284        Self: LdxrbEmitter<T0, T1>,
16285    {
16286        <Self as LdxrbEmitter<T0, T1>>::ldxrb(self, rd, addr);
16287    }
16288    /// Emits the `LDXRH` instruction.
16289    /// Assembly forms: `LDXRH WD, [XN|SP]`.
16290    /// Operands: `rd`, `addr`.
16291    pub fn ldxrh<T0, T1>(&mut self, rd: T0, addr: T1)
16292    where
16293        Self: LdxrhEmitter<T0, T1>,
16294    {
16295        <Self as LdxrhEmitter<T0, T1>>::ldxrh(self, rd, addr);
16296    }
16297    /// Emits the `PRFM` instruction.
16298    /// Assembly forms: `PRFM #PRF_OP, [XN|SP, RM, {UXTW|LSL|SXTW|SXTX #N*8}]`; `PRFM #PRF_OP, [XN|SP, #OFFZ]`; `PRFM #PRF_OP, [PC, #OFFS*4]`.
16299    /// Operands: `prf_op`, `addr`.
16300    pub fn prfm<T0, T1>(&mut self, prf_op: T0, addr: T1)
16301    where
16302        Self: PrfmEmitter<T0, T1>,
16303    {
16304        <Self as PrfmEmitter<T0, T1>>::prfm(self, prf_op, addr);
16305    }
16306    /// Emits the `STADD` instruction.
16307    /// Assembly forms: `STADD WS, [XN|SP]`; `STADD XS, [XN|SP]`.
16308    /// Operands: `rs`, `addr`.
16309    pub fn stadd<T0, T1>(&mut self, rs: T0, addr: T1)
16310    where
16311        Self: StaddEmitter<T0, T1>,
16312    {
16313        <Self as StaddEmitter<T0, T1>>::stadd(self, rs, addr);
16314    }
16315    /// Emits the `STADDB` instruction.
16316    /// Assembly forms: `STADDB WS, [XN|SP]`.
16317    /// Operands: `rs`, `addr`.
16318    pub fn staddb<T0, T1>(&mut self, rs: T0, addr: T1)
16319    where
16320        Self: StaddbEmitter<T0, T1>,
16321    {
16322        <Self as StaddbEmitter<T0, T1>>::staddb(self, rs, addr);
16323    }
16324    /// Emits the `STADDH` instruction.
16325    /// Assembly forms: `STADDH WS, [XN|SP]`.
16326    /// Operands: `rs`, `addr`.
16327    pub fn staddh<T0, T1>(&mut self, rs: T0, addr: T1)
16328    where
16329        Self: StaddhEmitter<T0, T1>,
16330    {
16331        <Self as StaddhEmitter<T0, T1>>::staddh(self, rs, addr);
16332    }
16333    /// Emits the `STADDL` instruction.
16334    /// Assembly forms: `STADDL WS, [XN|SP]`; `STADDL XS, [XN|SP]`.
16335    /// Operands: `rs`, `addr`.
16336    pub fn staddl<T0, T1>(&mut self, rs: T0, addr: T1)
16337    where
16338        Self: StaddlEmitter<T0, T1>,
16339    {
16340        <Self as StaddlEmitter<T0, T1>>::staddl(self, rs, addr);
16341    }
16342    /// Emits the `STADDLB` instruction.
16343    /// Assembly forms: `STADDLB WS, [XN|SP]`.
16344    /// Operands: `rs`, `addr`.
16345    pub fn staddlb<T0, T1>(&mut self, rs: T0, addr: T1)
16346    where
16347        Self: StaddlbEmitter<T0, T1>,
16348    {
16349        <Self as StaddlbEmitter<T0, T1>>::staddlb(self, rs, addr);
16350    }
16351    /// Emits the `STADDLH` instruction.
16352    /// Assembly forms: `STADDLH WS, [XN|SP]`.
16353    /// Operands: `rs`, `addr`.
16354    pub fn staddlh<T0, T1>(&mut self, rs: T0, addr: T1)
16355    where
16356        Self: StaddlhEmitter<T0, T1>,
16357    {
16358        <Self as StaddlhEmitter<T0, T1>>::staddlh(self, rs, addr);
16359    }
16360    /// Emits the `STCLR` instruction.
16361    /// Assembly forms: `STCLR WS, [XN|SP]`; `STCLR XS, [XN|SP]`.
16362    /// Operands: `rs`, `addr`.
16363    pub fn stclr<T0, T1>(&mut self, rs: T0, addr: T1)
16364    where
16365        Self: StclrEmitter<T0, T1>,
16366    {
16367        <Self as StclrEmitter<T0, T1>>::stclr(self, rs, addr);
16368    }
16369    /// Emits the `STCLRB` instruction.
16370    /// Assembly forms: `STCLRB WS, [XN|SP]`.
16371    /// Operands: `rs`, `addr`.
16372    pub fn stclrb<T0, T1>(&mut self, rs: T0, addr: T1)
16373    where
16374        Self: StclrbEmitter<T0, T1>,
16375    {
16376        <Self as StclrbEmitter<T0, T1>>::stclrb(self, rs, addr);
16377    }
16378    /// Emits the `STCLRH` instruction.
16379    /// Assembly forms: `STCLRH WS, [XN|SP]`.
16380    /// Operands: `rs`, `addr`.
16381    pub fn stclrh<T0, T1>(&mut self, rs: T0, addr: T1)
16382    where
16383        Self: StclrhEmitter<T0, T1>,
16384    {
16385        <Self as StclrhEmitter<T0, T1>>::stclrh(self, rs, addr);
16386    }
16387    /// Emits the `STCLRL` instruction.
16388    /// Assembly forms: `STCLRL WS, [XN|SP]`; `STCLRL XS, [XN|SP]`.
16389    /// Operands: `rs`, `addr`.
16390    pub fn stclrl<T0, T1>(&mut self, rs: T0, addr: T1)
16391    where
16392        Self: StclrlEmitter<T0, T1>,
16393    {
16394        <Self as StclrlEmitter<T0, T1>>::stclrl(self, rs, addr);
16395    }
16396    /// Emits the `STCLRLB` instruction.
16397    /// Assembly forms: `STCLRLB WS, [XN|SP]`.
16398    /// Operands: `rs`, `addr`.
16399    pub fn stclrlb<T0, T1>(&mut self, rs: T0, addr: T1)
16400    where
16401        Self: StclrlbEmitter<T0, T1>,
16402    {
16403        <Self as StclrlbEmitter<T0, T1>>::stclrlb(self, rs, addr);
16404    }
16405    /// Emits the `STCLRLH` instruction.
16406    /// Assembly forms: `STCLRLH WS, [XN|SP]`.
16407    /// Operands: `rs`, `addr`.
16408    pub fn stclrlh<T0, T1>(&mut self, rs: T0, addr: T1)
16409    where
16410        Self: StclrlhEmitter<T0, T1>,
16411    {
16412        <Self as StclrlhEmitter<T0, T1>>::stclrlh(self, rs, addr);
16413    }
16414    /// Emits the `STEOR` instruction.
16415    /// Assembly forms: `STEOR WS, [XN|SP]`; `STEOR XS, [XN|SP]`.
16416    /// Operands: `rs`, `addr`.
16417    pub fn steor<T0, T1>(&mut self, rs: T0, addr: T1)
16418    where
16419        Self: SteorEmitter<T0, T1>,
16420    {
16421        <Self as SteorEmitter<T0, T1>>::steor(self, rs, addr);
16422    }
16423    /// Emits the `STEORB` instruction.
16424    /// Assembly forms: `STEORB WS, [XN|SP]`.
16425    /// Operands: `rs`, `addr`.
16426    pub fn steorb<T0, T1>(&mut self, rs: T0, addr: T1)
16427    where
16428        Self: SteorbEmitter<T0, T1>,
16429    {
16430        <Self as SteorbEmitter<T0, T1>>::steorb(self, rs, addr);
16431    }
16432    /// Emits the `STEORH` instruction.
16433    /// Assembly forms: `STEORH WS, [XN|SP]`.
16434    /// Operands: `rs`, `addr`.
16435    pub fn steorh<T0, T1>(&mut self, rs: T0, addr: T1)
16436    where
16437        Self: SteorhEmitter<T0, T1>,
16438    {
16439        <Self as SteorhEmitter<T0, T1>>::steorh(self, rs, addr);
16440    }
16441    /// Emits the `STEORL` instruction.
16442    /// Assembly forms: `STEORL WS, [XN|SP]`; `STEORL XS, [XN|SP]`.
16443    /// Operands: `rs`, `addr`.
16444    pub fn steorl<T0, T1>(&mut self, rs: T0, addr: T1)
16445    where
16446        Self: SteorlEmitter<T0, T1>,
16447    {
16448        <Self as SteorlEmitter<T0, T1>>::steorl(self, rs, addr);
16449    }
16450    /// Emits the `STEORLB` instruction.
16451    /// Assembly forms: `STEORLB WS, [XN|SP]`.
16452    /// Operands: `rs`, `addr`.
16453    pub fn steorlb<T0, T1>(&mut self, rs: T0, addr: T1)
16454    where
16455        Self: SteorlbEmitter<T0, T1>,
16456    {
16457        <Self as SteorlbEmitter<T0, T1>>::steorlb(self, rs, addr);
16458    }
16459    /// Emits the `STEORLH` instruction.
16460    /// Assembly forms: `STEORLH WS, [XN|SP]`.
16461    /// Operands: `rs`, `addr`.
16462    pub fn steorlh<T0, T1>(&mut self, rs: T0, addr: T1)
16463    where
16464        Self: SteorlhEmitter<T0, T1>,
16465    {
16466        <Self as SteorlhEmitter<T0, T1>>::steorlh(self, rs, addr);
16467    }
16468    /// Emits the `STLLR` instruction.
16469    /// Assembly forms: `STLLR WS, [XN|SP]`; `STLLR XS, [XN|SP]`.
16470    /// Operands: `rs`, `addr`.
16471    pub fn stllr<T0, T1>(&mut self, rs: T0, addr: T1)
16472    where
16473        Self: StllrEmitter<T0, T1>,
16474    {
16475        <Self as StllrEmitter<T0, T1>>::stllr(self, rs, addr);
16476    }
16477    /// Emits the `STLLRB` instruction.
16478    /// Assembly forms: `STLLRB WS, [XN|SP]`.
16479    /// Operands: `rs`, `addr`.
16480    pub fn stllrb<T0, T1>(&mut self, rs: T0, addr: T1)
16481    where
16482        Self: StllrbEmitter<T0, T1>,
16483    {
16484        <Self as StllrbEmitter<T0, T1>>::stllrb(self, rs, addr);
16485    }
16486    /// Emits the `STLLRH` instruction.
16487    /// Assembly forms: `STLLRH WS, [XN|SP]`.
16488    /// Operands: `rs`, `addr`.
16489    pub fn stllrh<T0, T1>(&mut self, rs: T0, addr: T1)
16490    where
16491        Self: StllrhEmitter<T0, T1>,
16492    {
16493        <Self as StllrhEmitter<T0, T1>>::stllrh(self, rs, addr);
16494    }
16495    /// Emits the `STLR` instruction.
16496    /// Assembly forms: `STLR WS, [XN|SP]`; `STLR XS, [XN|SP]`.
16497    /// Operands: `rs`, `addr`.
16498    pub fn stlr<T0, T1>(&mut self, rs: T0, addr: T1)
16499    where
16500        Self: StlrEmitter<T0, T1>,
16501    {
16502        <Self as StlrEmitter<T0, T1>>::stlr(self, rs, addr);
16503    }
16504    /// Emits the `STLRB` instruction.
16505    /// Assembly forms: `STLRB WS, [XN|SP]`.
16506    /// Operands: `rs`, `addr`.
16507    pub fn stlrb<T0, T1>(&mut self, rs: T0, addr: T1)
16508    where
16509        Self: StlrbEmitter<T0, T1>,
16510    {
16511        <Self as StlrbEmitter<T0, T1>>::stlrb(self, rs, addr);
16512    }
16513    /// Emits the `STLRH` instruction.
16514    /// Assembly forms: `STLRH WS, [XN|SP]`.
16515    /// Operands: `rs`, `addr`.
16516    pub fn stlrh<T0, T1>(&mut self, rs: T0, addr: T1)
16517    where
16518        Self: StlrhEmitter<T0, T1>,
16519    {
16520        <Self as StlrhEmitter<T0, T1>>::stlrh(self, rs, addr);
16521    }
16522    /// Emits the `STLXR` instruction.
16523    /// Assembly forms: `STLXR WD, WS, [XN|SP]`; `STLXR WD, XS, [XN|SP]`.
16524    /// Operands: `rd`, `rs`, `addr`.
16525    pub fn stlxr<T0, T1, T2>(&mut self, rd: T0, rs: T1, addr: T2)
16526    where
16527        Self: StlxrEmitter<T0, T1, T2>,
16528    {
16529        <Self as StlxrEmitter<T0, T1, T2>>::stlxr(self, rd, rs, addr);
16530    }
16531    /// Emits the `STLXRB` instruction.
16532    /// Assembly forms: `STLXRB WD, WS, [XN|SP]`.
16533    /// Operands: `rd`, `rs`, `addr`.
16534    pub fn stlxrb<T0, T1, T2>(&mut self, rd: T0, rs: T1, addr: T2)
16535    where
16536        Self: StlxrbEmitter<T0, T1, T2>,
16537    {
16538        <Self as StlxrbEmitter<T0, T1, T2>>::stlxrb(self, rd, rs, addr);
16539    }
16540    /// Emits the `STLXRH` instruction.
16541    /// Assembly forms: `STLXRH WD, XS, [XN|SP]`.
16542    /// Operands: `rd`, `rs`, `addr`.
16543    pub fn stlxrh<T0, T1, T2>(&mut self, rd: T0, rs: T1, addr: T2)
16544    where
16545        Self: StlxrhEmitter<T0, T1, T2>,
16546    {
16547        <Self as StlxrhEmitter<T0, T1, T2>>::stlxrh(self, rd, rs, addr);
16548    }
16549    /// Emits the `STNP` instruction.
16550    /// Assembly forms: `STNP WS, WS2, [XN|SP, #OFFS*4]`; `STNP XS, XS2, [XN|SP, #OFFS*8]`; `STNP SD, SD2, [XN|SP, #OFFS*4]`; `STNP DD, DD2, [XN|SP, #OFFS*8]` (and related forms).
16551    /// Operands: `rs_or_rd`, `rs2_or_rd2`, `addr`.
16552    pub fn stnp<T0, T1, T2>(&mut self, rs_or_rd: T0, rs2_or_rd2: T1, addr: T2)
16553    where
16554        Self: StnpEmitter<T0, T1, T2>,
16555    {
16556        <Self as StnpEmitter<T0, T1, T2>>::stnp(self, rs_or_rd, rs2_or_rd2, addr);
16557    }
16558    /// Emits the `STP` instruction.
16559    /// Assembly forms: `STP WS, WS2, [XN|SP, #OFFS*4]{@}{!}`; `STP XS, XS2, [XN|SP, #OFFS*8]{@}{!}`; `STP SD, SD2, [XN|SP, #OFFS*4]{@}{!}`; `STP DD, DD2, [XN|SP, #OFFS*8]{@}{!}` (and related forms).
16560    /// Operands: `rs_or_rd`, `rs2_or_rd2`, `addr`.
16561    pub fn stp<T0, T1, T2>(&mut self, rs_or_rd: T0, rs2_or_rd2: T1, addr: T2)
16562    where
16563        Self: StpEmitter<T0, T1, T2>,
16564    {
16565        <Self as StpEmitter<T0, T1, T2>>::stp(self, rs_or_rd, rs2_or_rd2, addr);
16566    }
16567    /// Emits the `STR` instruction.
16568    /// Assembly forms: `STR WS, [XN|SP, #OFFZ*4]`; `STR XS, [XN|SP, #OFFZ*8]`; `STR WS, [XN|SP, #OFFS*4]@`; `STR XS, [XN|SP, #OFFS*8]@` (and related forms).
16569    /// Operands: `rs_or_rd`, `addr`.
16570    pub fn str<T0, T1>(&mut self, rs_or_rd: T0, addr: T1)
16571    where
16572        Self: StrEmitter<T0, T1>,
16573    {
16574        <Self as StrEmitter<T0, T1>>::str(self, rs_or_rd, addr);
16575    }
16576    /// Emits the `STRB` instruction.
16577    /// Assembly forms: `STRB WS, [XN|SP, #OFFZ]`; `STRB WS, [XN|SP, #OFFS]@`; `STRB WS, [XN|SP, #OFFS]!`; `STRB WS, [XN|SP, RM, {UXTW|LSL|SXTW|SXTX #N}]`.
16578    /// Operands: `rs`, `addr`.
16579    pub fn strb<T0, T1>(&mut self, rs: T0, addr: T1)
16580    where
16581        Self: StrbEmitter<T0, T1>,
16582    {
16583        <Self as StrbEmitter<T0, T1>>::strb(self, rs, addr);
16584    }
16585    /// Emits the `STRH` instruction.
16586    /// Assembly forms: `STRH WS, [XN|SP, #OFFZ*2]`; `STRH WS, [XN|SP, #OFFS*2]@`; `STRH WS, [XN|SP, #OFFS*2]!`; `STRH WS, [XN|SP, RM, {UXTW|LSL|SXTW|SXTX #N}]`.
16587    /// Operands: `rs`, `addr`.
16588    pub fn strh<T0, T1>(&mut self, rs: T0, addr: T1)
16589    where
16590        Self: StrhEmitter<T0, T1>,
16591    {
16592        <Self as StrhEmitter<T0, T1>>::strh(self, rs, addr);
16593    }
16594    /// Emits the `STSET` instruction.
16595    /// Assembly forms: `STSET WS, [XN|SP]`; `STSET XS, [XN|SP]`.
16596    /// Operands: `rs`, `addr`.
16597    pub fn stset<T0, T1>(&mut self, rs: T0, addr: T1)
16598    where
16599        Self: StsetEmitter<T0, T1>,
16600    {
16601        <Self as StsetEmitter<T0, T1>>::stset(self, rs, addr);
16602    }
16603    /// Emits the `STSETB` instruction.
16604    /// Assembly forms: `STSETB WS, [XN|SP]`.
16605    /// Operands: `rs`, `addr`.
16606    pub fn stsetb<T0, T1>(&mut self, rs: T0, addr: T1)
16607    where
16608        Self: StsetbEmitter<T0, T1>,
16609    {
16610        <Self as StsetbEmitter<T0, T1>>::stsetb(self, rs, addr);
16611    }
16612    /// Emits the `STSETH` instruction.
16613    /// Assembly forms: `STSETH WS, [XN|SP]`.
16614    /// Operands: `rs`, `addr`.
16615    pub fn stseth<T0, T1>(&mut self, rs: T0, addr: T1)
16616    where
16617        Self: StsethEmitter<T0, T1>,
16618    {
16619        <Self as StsethEmitter<T0, T1>>::stseth(self, rs, addr);
16620    }
16621    /// Emits the `STSETL` instruction.
16622    /// Assembly forms: `STSETL WS, [XN|SP]`; `STSETL XS, [XN|SP]`.
16623    /// Operands: `rs`, `addr`.
16624    pub fn stsetl<T0, T1>(&mut self, rs: T0, addr: T1)
16625    where
16626        Self: StsetlEmitter<T0, T1>,
16627    {
16628        <Self as StsetlEmitter<T0, T1>>::stsetl(self, rs, addr);
16629    }
16630    /// Emits the `STSETLB` instruction.
16631    /// Assembly forms: `STSETLB WS, [XN|SP]`.
16632    /// Operands: `rs`, `addr`.
16633    pub fn stsetlb<T0, T1>(&mut self, rs: T0, addr: T1)
16634    where
16635        Self: StsetlbEmitter<T0, T1>,
16636    {
16637        <Self as StsetlbEmitter<T0, T1>>::stsetlb(self, rs, addr);
16638    }
16639    /// Emits the `STSETLH` instruction.
16640    /// Assembly forms: `STSETLH WS, [XN|SP]`.
16641    /// Operands: `rs`, `addr`.
16642    pub fn stsetlh<T0, T1>(&mut self, rs: T0, addr: T1)
16643    where
16644        Self: StsetlhEmitter<T0, T1>,
16645    {
16646        <Self as StsetlhEmitter<T0, T1>>::stsetlh(self, rs, addr);
16647    }
16648    /// Emits the `STSMAX` instruction.
16649    /// Assembly forms: `STSMAX WS, [XN|SP]`; `STSMAX XS, [XN|SP]`.
16650    /// Operands: `rs`, `addr`.
16651    pub fn stsmax<T0, T1>(&mut self, rs: T0, addr: T1)
16652    where
16653        Self: StsmaxEmitter<T0, T1>,
16654    {
16655        <Self as StsmaxEmitter<T0, T1>>::stsmax(self, rs, addr);
16656    }
16657    /// Emits the `STSMAXB` instruction.
16658    /// Assembly forms: `STSMAXB WS, [XN|SP]`.
16659    /// Operands: `rs`, `addr`.
16660    pub fn stsmaxb<T0, T1>(&mut self, rs: T0, addr: T1)
16661    where
16662        Self: StsmaxbEmitter<T0, T1>,
16663    {
16664        <Self as StsmaxbEmitter<T0, T1>>::stsmaxb(self, rs, addr);
16665    }
16666    /// Emits the `STSMAXH` instruction.
16667    /// Assembly forms: `STSMAXH WS, [XN|SP]`.
16668    /// Operands: `rs`, `addr`.
16669    pub fn stsmaxh<T0, T1>(&mut self, rs: T0, addr: T1)
16670    where
16671        Self: StsmaxhEmitter<T0, T1>,
16672    {
16673        <Self as StsmaxhEmitter<T0, T1>>::stsmaxh(self, rs, addr);
16674    }
16675    /// Emits the `STSMAXL` instruction.
16676    /// Assembly forms: `STSMAXL WS, [XN|SP]`; `STSMAXL XS, [XN|SP]`.
16677    /// Operands: `rs`, `addr`.
16678    pub fn stsmaxl<T0, T1>(&mut self, rs: T0, addr: T1)
16679    where
16680        Self: StsmaxlEmitter<T0, T1>,
16681    {
16682        <Self as StsmaxlEmitter<T0, T1>>::stsmaxl(self, rs, addr);
16683    }
16684    /// Emits the `STSMAXLB` instruction.
16685    /// Assembly forms: `STSMAXLB WS, [XN|SP]`.
16686    /// Operands: `rs`, `addr`.
16687    pub fn stsmaxlb<T0, T1>(&mut self, rs: T0, addr: T1)
16688    where
16689        Self: StsmaxlbEmitter<T0, T1>,
16690    {
16691        <Self as StsmaxlbEmitter<T0, T1>>::stsmaxlb(self, rs, addr);
16692    }
16693    /// Emits the `STSMAXLH` instruction.
16694    /// Assembly forms: `STSMAXLH WS, [XN|SP]`.
16695    /// Operands: `rs`, `addr`.
16696    pub fn stsmaxlh<T0, T1>(&mut self, rs: T0, addr: T1)
16697    where
16698        Self: StsmaxlhEmitter<T0, T1>,
16699    {
16700        <Self as StsmaxlhEmitter<T0, T1>>::stsmaxlh(self, rs, addr);
16701    }
16702    /// Emits the `STSMIN` instruction.
16703    /// Assembly forms: `STSMIN WS, [XN|SP]`; `STSMIN XS, [XN|SP]`.
16704    /// Operands: `rs`, `addr`.
16705    pub fn stsmin<T0, T1>(&mut self, rs: T0, addr: T1)
16706    where
16707        Self: StsminEmitter<T0, T1>,
16708    {
16709        <Self as StsminEmitter<T0, T1>>::stsmin(self, rs, addr);
16710    }
16711    /// Emits the `STSMINB` instruction.
16712    /// Assembly forms: `STSMINB WS, [XN|SP]`.
16713    /// Operands: `rs`, `addr`.
16714    pub fn stsminb<T0, T1>(&mut self, rs: T0, addr: T1)
16715    where
16716        Self: StsminbEmitter<T0, T1>,
16717    {
16718        <Self as StsminbEmitter<T0, T1>>::stsminb(self, rs, addr);
16719    }
16720    /// Emits the `STSMINH` instruction.
16721    /// Assembly forms: `STSMINH WS, [XN|SP]`.
16722    /// Operands: `rs`, `addr`.
16723    pub fn stsminh<T0, T1>(&mut self, rs: T0, addr: T1)
16724    where
16725        Self: StsminhEmitter<T0, T1>,
16726    {
16727        <Self as StsminhEmitter<T0, T1>>::stsminh(self, rs, addr);
16728    }
16729    /// Emits the `STSMINL` instruction.
16730    /// Assembly forms: `STSMINL WS, [XN|SP]`; `STSMINL XS, [XN|SP]`.
16731    /// Operands: `rs`, `addr`.
16732    pub fn stsminl<T0, T1>(&mut self, rs: T0, addr: T1)
16733    where
16734        Self: StsminlEmitter<T0, T1>,
16735    {
16736        <Self as StsminlEmitter<T0, T1>>::stsminl(self, rs, addr);
16737    }
16738    /// Emits the `STSMINLB` instruction.
16739    /// Assembly forms: `STSMINLB WS, [XN|SP]`.
16740    /// Operands: `rs`, `addr`.
16741    pub fn stsminlb<T0, T1>(&mut self, rs: T0, addr: T1)
16742    where
16743        Self: StsminlbEmitter<T0, T1>,
16744    {
16745        <Self as StsminlbEmitter<T0, T1>>::stsminlb(self, rs, addr);
16746    }
16747    /// Emits the `STSMINLH` instruction.
16748    /// Assembly forms: `STSMINLH WS, [XN|SP]`.
16749    /// Operands: `rs`, `addr`.
16750    pub fn stsminlh<T0, T1>(&mut self, rs: T0, addr: T1)
16751    where
16752        Self: StsminlhEmitter<T0, T1>,
16753    {
16754        <Self as StsminlhEmitter<T0, T1>>::stsminlh(self, rs, addr);
16755    }
16756    /// Emits the `STTR` instruction.
16757    /// Assembly forms: `STTR WS, [XN|SP, #OFFS]`; `STTR XS, [XN|SP, #OFFS]`.
16758    /// Operands: `rs`, `addr`.
16759    pub fn sttr<T0, T1>(&mut self, rs: T0, addr: T1)
16760    where
16761        Self: SttrEmitter<T0, T1>,
16762    {
16763        <Self as SttrEmitter<T0, T1>>::sttr(self, rs, addr);
16764    }
16765    /// Emits the `STTRB` instruction.
16766    /// Assembly forms: `STTRB WS, [XN|SP, #OFFS]`.
16767    /// Operands: `rs`, `addr`.
16768    pub fn sttrb<T0, T1>(&mut self, rs: T0, addr: T1)
16769    where
16770        Self: SttrbEmitter<T0, T1>,
16771    {
16772        <Self as SttrbEmitter<T0, T1>>::sttrb(self, rs, addr);
16773    }
16774    /// Emits the `STTRH` instruction.
16775    /// Assembly forms: `STTRH WS, [XN|SP, #OFFS]`.
16776    /// Operands: `rs`, `addr`.
16777    pub fn sttrh<T0, T1>(&mut self, rs: T0, addr: T1)
16778    where
16779        Self: SttrhEmitter<T0, T1>,
16780    {
16781        <Self as SttrhEmitter<T0, T1>>::sttrh(self, rs, addr);
16782    }
16783    /// Emits the `STUMAX` instruction.
16784    /// Assembly forms: `STUMAX WS, [XN|SP]`; `STUMAX XS, [XN|SP]`.
16785    /// Operands: `rs`, `addr`.
16786    pub fn stumax<T0, T1>(&mut self, rs: T0, addr: T1)
16787    where
16788        Self: StumaxEmitter<T0, T1>,
16789    {
16790        <Self as StumaxEmitter<T0, T1>>::stumax(self, rs, addr);
16791    }
16792    /// Emits the `STUMAXB` instruction.
16793    /// Assembly forms: `STUMAXB WS, [XN|SP]`.
16794    /// Operands: `rs`, `addr`.
16795    pub fn stumaxb<T0, T1>(&mut self, rs: T0, addr: T1)
16796    where
16797        Self: StumaxbEmitter<T0, T1>,
16798    {
16799        <Self as StumaxbEmitter<T0, T1>>::stumaxb(self, rs, addr);
16800    }
16801    /// Emits the `STUMAXH` instruction.
16802    /// Assembly forms: `STUMAXH WS, [XN|SP]`.
16803    /// Operands: `rs`, `addr`.
16804    pub fn stumaxh<T0, T1>(&mut self, rs: T0, addr: T1)
16805    where
16806        Self: StumaxhEmitter<T0, T1>,
16807    {
16808        <Self as StumaxhEmitter<T0, T1>>::stumaxh(self, rs, addr);
16809    }
16810    /// Emits the `STUMAXL` instruction.
16811    /// Assembly forms: `STUMAXL WS, [XN|SP]`; `STUMAXL XS, [XN|SP]`.
16812    /// Operands: `rs`, `addr`.
16813    pub fn stumaxl<T0, T1>(&mut self, rs: T0, addr: T1)
16814    where
16815        Self: StumaxlEmitter<T0, T1>,
16816    {
16817        <Self as StumaxlEmitter<T0, T1>>::stumaxl(self, rs, addr);
16818    }
16819    /// Emits the `STUMAXLB` instruction.
16820    /// Assembly forms: `STUMAXLB WS, [XN|SP]`.
16821    /// Operands: `rs`, `addr`.
16822    pub fn stumaxlb<T0, T1>(&mut self, rs: T0, addr: T1)
16823    where
16824        Self: StumaxlbEmitter<T0, T1>,
16825    {
16826        <Self as StumaxlbEmitter<T0, T1>>::stumaxlb(self, rs, addr);
16827    }
16828    /// Emits the `STUMAXLH` instruction.
16829    /// Assembly forms: `STUMAXLH WS, [XN|SP]`.
16830    /// Operands: `rs`, `addr`.
16831    pub fn stumaxlh<T0, T1>(&mut self, rs: T0, addr: T1)
16832    where
16833        Self: StumaxlhEmitter<T0, T1>,
16834    {
16835        <Self as StumaxlhEmitter<T0, T1>>::stumaxlh(self, rs, addr);
16836    }
16837    /// Emits the `STUMIN` instruction.
16838    /// Assembly forms: `STUMIN WS, [XN|SP]`; `STUMIN XS, [XN|SP]`.
16839    /// Operands: `rs`, `addr`.
16840    pub fn stumin<T0, T1>(&mut self, rs: T0, addr: T1)
16841    where
16842        Self: StuminEmitter<T0, T1>,
16843    {
16844        <Self as StuminEmitter<T0, T1>>::stumin(self, rs, addr);
16845    }
16846    /// Emits the `STUMINB` instruction.
16847    /// Assembly forms: `STUMINB WS, [XN|SP]`.
16848    /// Operands: `rs`, `addr`.
16849    pub fn stuminb<T0, T1>(&mut self, rs: T0, addr: T1)
16850    where
16851        Self: StuminbEmitter<T0, T1>,
16852    {
16853        <Self as StuminbEmitter<T0, T1>>::stuminb(self, rs, addr);
16854    }
16855    /// Emits the `STUMINH` instruction.
16856    /// Assembly forms: `STUMINH WS, [XN|SP]`.
16857    /// Operands: `rs`, `addr`.
16858    pub fn stuminh<T0, T1>(&mut self, rs: T0, addr: T1)
16859    where
16860        Self: StuminhEmitter<T0, T1>,
16861    {
16862        <Self as StuminhEmitter<T0, T1>>::stuminh(self, rs, addr);
16863    }
16864    /// Emits the `STUMINL` instruction.
16865    /// Assembly forms: `STUMINL WS, [XN|SP]`; `STUMINL XS, [XN|SP]`.
16866    /// Operands: `rs`, `addr`.
16867    pub fn stuminl<T0, T1>(&mut self, rs: T0, addr: T1)
16868    where
16869        Self: StuminlEmitter<T0, T1>,
16870    {
16871        <Self as StuminlEmitter<T0, T1>>::stuminl(self, rs, addr);
16872    }
16873    /// Emits the `STUMINLB` instruction.
16874    /// Assembly forms: `STUMINLB WS, [XN|SP]`.
16875    /// Operands: `rs`, `addr`.
16876    pub fn stuminlb<T0, T1>(&mut self, rs: T0, addr: T1)
16877    where
16878        Self: StuminlbEmitter<T0, T1>,
16879    {
16880        <Self as StuminlbEmitter<T0, T1>>::stuminlb(self, rs, addr);
16881    }
16882    /// Emits the `STUMINLH` instruction.
16883    /// Assembly forms: `STUMINLH WS, [XN|SP]`.
16884    /// Operands: `rs`, `addr`.
16885    pub fn stuminlh<T0, T1>(&mut self, rs: T0, addr: T1)
16886    where
16887        Self: StuminlhEmitter<T0, T1>,
16888    {
16889        <Self as StuminlhEmitter<T0, T1>>::stuminlh(self, rs, addr);
16890    }
16891    /// Emits the `STUR` instruction.
16892    /// Assembly forms: `STUR WS, [XN|SP, #OFFS]`; `STUR XS, [XN|SP, #OFFS]`; `STUR BD, [XN|SP, #OFFS]`; `STUR HD, [XN|SP, #OFFS]` (and related forms).
16893    /// Operands: `rs_or_rd`, `addr`.
16894    pub fn stur<T0, T1>(&mut self, rs_or_rd: T0, addr: T1)
16895    where
16896        Self: SturEmitter<T0, T1>,
16897    {
16898        <Self as SturEmitter<T0, T1>>::stur(self, rs_or_rd, addr);
16899    }
16900    /// Emits the `STURB` instruction.
16901    /// Assembly forms: `STURB WS, [XN|SP, #OFFS]`.
16902    /// Operands: `rs`, `addr`.
16903    pub fn sturb<T0, T1>(&mut self, rs: T0, addr: T1)
16904    where
16905        Self: SturbEmitter<T0, T1>,
16906    {
16907        <Self as SturbEmitter<T0, T1>>::sturb(self, rs, addr);
16908    }
16909    /// Emits the `STURH` instruction.
16910    /// Assembly forms: `STURH WS, [XN|SP, #OFFS]`.
16911    /// Operands: `rs`, `addr`.
16912    pub fn sturh<T0, T1>(&mut self, rs: T0, addr: T1)
16913    where
16914        Self: SturhEmitter<T0, T1>,
16915    {
16916        <Self as SturhEmitter<T0, T1>>::sturh(self, rs, addr);
16917    }
16918    /// Emits the `STXP` instruction.
16919    /// Assembly forms: `STXP WD, WS, WS2, [XN|SP]`; `STXP WD, XS, XS2, [XN|SP]`.
16920    /// Operands: `rd`, `rs`, `rs2`, `addr`.
16921    pub fn stxp<T0, T1, T2, T3>(&mut self, rd: T0, rs: T1, rs2: T2, addr: T3)
16922    where
16923        Self: StxpEmitter<T0, T1, T2, T3>,
16924    {
16925        <Self as StxpEmitter<T0, T1, T2, T3>>::stxp(self, rd, rs, rs2, addr);
16926    }
16927    /// Emits the `STLXP` instruction.
16928    /// Assembly forms: `STLXP WD, WS, WS2, [XN|SP]`; `STLXP WD, XS, XS2, [XN|SP]`.
16929    /// Operands: `rd`, `rs`, `rs2`, `addr`.
16930    pub fn stlxp<T0, T1, T2, T3>(&mut self, rd: T0, rs: T1, rs2: T2, addr: T3)
16931    where
16932        Self: StlxpEmitter<T0, T1, T2, T3>,
16933    {
16934        <Self as StlxpEmitter<T0, T1, T2, T3>>::stlxp(self, rd, rs, rs2, addr);
16935    }
16936    /// Emits the `STXR` instruction.
16937    /// Assembly forms: `STXR WD, WS, [XN|SP]`; `STXR WD, XS, [XN|SP]`.
16938    /// Operands: `rd`, `rs`, `addr`.
16939    pub fn stxr<T0, T1, T2>(&mut self, rd: T0, rs: T1, addr: T2)
16940    where
16941        Self: StxrEmitter<T0, T1, T2>,
16942    {
16943        <Self as StxrEmitter<T0, T1, T2>>::stxr(self, rd, rs, addr);
16944    }
16945    /// Emits the `STXRB` instruction.
16946    /// Assembly forms: `STXRB WD, WS, [XN|SP]`.
16947    /// Operands: `rd`, `rs`, `addr`.
16948    pub fn stxrb<T0, T1, T2>(&mut self, rd: T0, rs: T1, addr: T2)
16949    where
16950        Self: StxrbEmitter<T0, T1, T2>,
16951    {
16952        <Self as StxrbEmitter<T0, T1, T2>>::stxrb(self, rd, rs, addr);
16953    }
16954    /// Emits the `STXRH` instruction.
16955    /// Assembly forms: `STXRH WD, XS, [XN|SP]`.
16956    /// Operands: `rd`, `rs`, `addr`.
16957    pub fn stxrh<T0, T1, T2>(&mut self, rd: T0, rs: T1, addr: T2)
16958    where
16959        Self: StxrhEmitter<T0, T1, T2>,
16960    {
16961        <Self as StxrhEmitter<T0, T1, T2>>::stxrh(self, rd, rs, addr);
16962    }
16963    /// Emits the `SWP` instruction.
16964    /// Assembly forms: `SWP WS, WD, [XN|SP]`; `SWP XS, XD, [XN|SP]`.
16965    /// Operands: `rs`, `rd`, `addr`.
16966    pub fn swp<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
16967    where
16968        Self: SwpEmitter<T0, T1, T2>,
16969    {
16970        <Self as SwpEmitter<T0, T1, T2>>::swp(self, rs, rd, addr);
16971    }
16972    /// Emits the `SWPA` instruction.
16973    /// Assembly forms: `SWPA WS, WD, [XN|SP]`; `SWPA XS, XD, [XN|SP]`.
16974    /// Operands: `rs`, `rd`, `addr`.
16975    pub fn swpa<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
16976    where
16977        Self: SwpaEmitter<T0, T1, T2>,
16978    {
16979        <Self as SwpaEmitter<T0, T1, T2>>::swpa(self, rs, rd, addr);
16980    }
16981    /// Emits the `SWPAB` instruction.
16982    /// Assembly forms: `SWPAB WS, WD, [XN|SP]`.
16983    /// Operands: `rs`, `rd`, `addr`.
16984    pub fn swpab<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
16985    where
16986        Self: SwpabEmitter<T0, T1, T2>,
16987    {
16988        <Self as SwpabEmitter<T0, T1, T2>>::swpab(self, rs, rd, addr);
16989    }
16990    /// Emits the `SWPAH` instruction.
16991    /// Assembly forms: `SWPAH WS, WD, [XN|SP]`.
16992    /// Operands: `rs`, `rd`, `addr`.
16993    pub fn swpah<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
16994    where
16995        Self: SwpahEmitter<T0, T1, T2>,
16996    {
16997        <Self as SwpahEmitter<T0, T1, T2>>::swpah(self, rs, rd, addr);
16998    }
16999    /// Emits the `SWPAL` instruction.
17000    /// Assembly forms: `SWPAL WS, WD, [XN|SP]`; `SWPAL XS, XD, [XN|SP]`.
17001    /// Operands: `rs`, `rd`, `addr`.
17002    pub fn swpal<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
17003    where
17004        Self: SwpalEmitter<T0, T1, T2>,
17005    {
17006        <Self as SwpalEmitter<T0, T1, T2>>::swpal(self, rs, rd, addr);
17007    }
17008    /// Emits the `SWPALB` instruction.
17009    /// Assembly forms: `SWPALB WS, WD, [XN|SP]`.
17010    /// Operands: `rs`, `rd`, `addr`.
17011    pub fn swpalb<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
17012    where
17013        Self: SwpalbEmitter<T0, T1, T2>,
17014    {
17015        <Self as SwpalbEmitter<T0, T1, T2>>::swpalb(self, rs, rd, addr);
17016    }
17017    /// Emits the `SWPALH` instruction.
17018    /// Assembly forms: `SWPALH WS, WD, [XN|SP]`.
17019    /// Operands: `rs`, `rd`, `addr`.
17020    pub fn swpalh<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
17021    where
17022        Self: SwpalhEmitter<T0, T1, T2>,
17023    {
17024        <Self as SwpalhEmitter<T0, T1, T2>>::swpalh(self, rs, rd, addr);
17025    }
17026    /// Emits the `SWPB` instruction.
17027    /// Assembly forms: `SWPB WS, WD, [XN|SP]`.
17028    /// Operands: `rs`, `rd`, `addr`.
17029    pub fn swpb<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
17030    where
17031        Self: SwpbEmitter<T0, T1, T2>,
17032    {
17033        <Self as SwpbEmitter<T0, T1, T2>>::swpb(self, rs, rd, addr);
17034    }
17035    /// Emits the `SWPH` instruction.
17036    /// Assembly forms: `SWPH WS, WD, [XN|SP]`.
17037    /// Operands: `rs`, `rd`, `addr`.
17038    pub fn swph<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
17039    where
17040        Self: SwphEmitter<T0, T1, T2>,
17041    {
17042        <Self as SwphEmitter<T0, T1, T2>>::swph(self, rs, rd, addr);
17043    }
17044    /// Emits the `SWPL` instruction.
17045    /// Assembly forms: `SWPL WS, WD, [XN|SP]`; `SWPL XS, XD, [XN|SP]`.
17046    /// Operands: `rs`, `rd`, `addr`.
17047    pub fn swpl<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
17048    where
17049        Self: SwplEmitter<T0, T1, T2>,
17050    {
17051        <Self as SwplEmitter<T0, T1, T2>>::swpl(self, rs, rd, addr);
17052    }
17053    /// Emits the `SWPLB` instruction.
17054    /// Assembly forms: `SWPLB WS, WD, [XN|SP]`.
17055    /// Operands: `rs`, `rd`, `addr`.
17056    pub fn swplb<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
17057    where
17058        Self: SwplbEmitter<T0, T1, T2>,
17059    {
17060        <Self as SwplbEmitter<T0, T1, T2>>::swplb(self, rs, rd, addr);
17061    }
17062    /// Emits the `SWPLH` instruction.
17063    /// Assembly forms: `SWPLH WS, WD, [XN|SP]`.
17064    /// Operands: `rs`, `rd`, `addr`.
17065    pub fn swplh<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)
17066    where
17067        Self: SwplhEmitter<T0, T1, T2>,
17068    {
17069        <Self as SwplhEmitter<T0, T1, T2>>::swplh(self, rs, rd, addr);
17070    }
17071    /// Emits the `BTI` instruction.
17072    /// Assembly forms: `BTI {#TARGETS}`.
17073    /// Operands: `targets`.
17074    pub fn bti<T0>(&mut self, targets: T0)
17075    where
17076        Self: BtiEmitter<T0>,
17077    {
17078        <Self as BtiEmitter<T0>>::bti(self, targets);
17079    }
17080    /// Emits the `CHKFEAT` instruction.
17081    /// Assembly forms: `CHKFEAT`.
17082    /// Operands: `rd`.
17083    pub fn chkfeat<T0>(&mut self, rd: T0)
17084    where
17085        Self: ChkfeatEmitter<T0>,
17086    {
17087        <Self as ChkfeatEmitter<T0>>::chkfeat(self, rd);
17088    }
17089    /// Emits the `CLRBHB` instruction.
17090    /// Assembly forms: `CLRBHB`.
17091    pub fn clrbhb(&mut self)
17092    where
17093        Self: ClrbhbEmitter,
17094    {
17095        <Self as ClrbhbEmitter>::clrbhb(self);
17096    }
17097    /// Emits the `CRC32B` instruction.
17098    /// Assembly forms: `CRC32B WD, WN, WM`.
17099    /// Operands: `rd`, `rn`, `rm`.
17100    pub fn crc32b<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
17101    where
17102        Self: Crc32bEmitter<T0, T1, T2>,
17103    {
17104        <Self as Crc32bEmitter<T0, T1, T2>>::crc32b(self, rd, rn, rm);
17105    }
17106    /// Emits the `CRC32H` instruction.
17107    /// Assembly forms: `CRC32H WD, WN, WM`.
17108    /// Operands: `rd`, `rn`, `rm`.
17109    pub fn crc32h<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
17110    where
17111        Self: Crc32hEmitter<T0, T1, T2>,
17112    {
17113        <Self as Crc32hEmitter<T0, T1, T2>>::crc32h(self, rd, rn, rm);
17114    }
17115    /// Emits the `CRC32W` instruction.
17116    /// Assembly forms: `CRC32W WD, WN, WM`.
17117    /// Operands: `rd`, `rn`, `rm`.
17118    pub fn crc32w<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
17119    where
17120        Self: Crc32wEmitter<T0, T1, T2>,
17121    {
17122        <Self as Crc32wEmitter<T0, T1, T2>>::crc32w(self, rd, rn, rm);
17123    }
17124    /// Emits the `CRC32X` instruction.
17125    /// Assembly forms: `CRC32X XD, XN, XM`.
17126    /// Operands: `rd`, `rn`, `rm`.
17127    pub fn crc32x<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
17128    where
17129        Self: Crc32xEmitter<T0, T1, T2>,
17130    {
17131        <Self as Crc32xEmitter<T0, T1, T2>>::crc32x(self, rd, rn, rm);
17132    }
17133    /// Emits the `CRC32CB` instruction.
17134    /// Assembly forms: `CRC32CB WD, WN, WM`.
17135    /// Operands: `rd`, `rn`, `rm`.
17136    pub fn crc32cb<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
17137    where
17138        Self: Crc32cbEmitter<T0, T1, T2>,
17139    {
17140        <Self as Crc32cbEmitter<T0, T1, T2>>::crc32cb(self, rd, rn, rm);
17141    }
17142    /// Emits the `CRC32CH` instruction.
17143    /// Assembly forms: `CRC32CH WD, WN, WM`.
17144    /// Operands: `rd`, `rn`, `rm`.
17145    pub fn crc32ch<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
17146    where
17147        Self: Crc32chEmitter<T0, T1, T2>,
17148    {
17149        <Self as Crc32chEmitter<T0, T1, T2>>::crc32ch(self, rd, rn, rm);
17150    }
17151    /// Emits the `CRC32CW` instruction.
17152    /// Assembly forms: `CRC32CW WD, WN, WM`.
17153    /// Operands: `rd`, `rn`, `rm`.
17154    pub fn crc32cw<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
17155    where
17156        Self: Crc32cwEmitter<T0, T1, T2>,
17157    {
17158        <Self as Crc32cwEmitter<T0, T1, T2>>::crc32cw(self, rd, rn, rm);
17159    }
17160    /// Emits the `CRC32CX` instruction.
17161    /// Assembly forms: `CRC32CX XD, XN, XM`.
17162    /// Operands: `rd`, `rn`, `rm`.
17163    pub fn crc32cx<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
17164    where
17165        Self: Crc32cxEmitter<T0, T1, T2>,
17166    {
17167        <Self as Crc32cxEmitter<T0, T1, T2>>::crc32cx(self, rd, rn, rm);
17168    }
17169    /// Emits the `ABS` instruction.
17170    /// Assembly forms: `ABS WD, WN`; `ABS XD, XN`; `ABS DD, DN`; `ABS VD.T, VN.T` (and related forms).
17171    /// Operands: `rd`, `rn`.
17172    pub fn abs<T0, T1>(&mut self, rd: T0, rn: T1)
17173    where
17174        Self: AbsEmitter<T0, T1>,
17175    {
17176        <Self as AbsEmitter<T0, T1>>::abs(self, rd, rn);
17177    }
17178    /// Emits the `CNT` instruction.
17179    /// Assembly forms: `CNT WD, WN`; `CNT XD, XN`; `CNT VD.8B, VN.8B`; `CNT VD.16B, VN.16B`.
17180    /// Operands: `rd`, `rn`.
17181    pub fn cnt<T0, T1>(&mut self, rd: T0, rn: T1)
17182    where
17183        Self: CntEmitter<T0, T1>,
17184    {
17185        <Self as CntEmitter<T0, T1>>::cnt(self, rd, rn);
17186    }
17187    /// Emits the `CTZ` instruction.
17188    /// Assembly forms: `CTZ WD, WN`; `CTZ XD, XN`.
17189    /// Operands: `rd`, `rn`.
17190    pub fn ctz<T0, T1>(&mut self, rd: T0, rn: T1)
17191    where
17192        Self: CtzEmitter<T0, T1>,
17193    {
17194        <Self as CtzEmitter<T0, T1>>::ctz(self, rd, rn);
17195    }
17196    /// Emits the `SMAX` instruction.
17197    /// Assembly forms: `SMAX WD, WN, WM`; `SMAX XD, XN, XM`; `SMAX WD, WN, #IMMS`; `SMAX XD, XN, #IMMS` (and related forms).
17198    /// Operands: `rd`, `rn`, `rm_or_imm`.
17199    pub fn smax<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm_or_imm: T2)
17200    where
17201        Self: SmaxEmitter<T0, T1, T2>,
17202    {
17203        <Self as SmaxEmitter<T0, T1, T2>>::smax(self, rd, rn, rm_or_imm);
17204    }
17205    /// Emits the `SMIN` instruction.
17206    /// Assembly forms: `SMIN WD, WN, WM`; `SMIN XD, XN, XM`; `SMIN WD, WN, #IMMS`; `SMIN XD, XN, #IMMS` (and related forms).
17207    /// Operands: `rd`, `rn`, `rm_or_imm`.
17208    pub fn smin<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm_or_imm: T2)
17209    where
17210        Self: SminEmitter<T0, T1, T2>,
17211    {
17212        <Self as SminEmitter<T0, T1, T2>>::smin(self, rd, rn, rm_or_imm);
17213    }
17214    /// Emits the `UMAX` instruction.
17215    /// Assembly forms: `UMAX WD, WN, WM`; `UMAX XD, XN, XM`; `UMAX WD, WN, #IMMZ`; `UMAX XD, XN, #IMMZ` (and related forms).
17216    /// Operands: `rd`, `rn`, `rm_or_imm`.
17217    pub fn umax<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm_or_imm: T2)
17218    where
17219        Self: UmaxEmitter<T0, T1, T2>,
17220    {
17221        <Self as UmaxEmitter<T0, T1, T2>>::umax(self, rd, rn, rm_or_imm);
17222    }
17223    /// Emits the `UMIN` instruction.
17224    /// Assembly forms: `UMIN WD, WN, WM`; `UMIN XD, XN, XM`; `UMIN WD, WN, #IMMZ`; `UMIN XD, XN, #IMMZ` (and related forms).
17225    /// Operands: `rd`, `rn`, `rm_or_imm`.
17226    pub fn umin<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm_or_imm: T2)
17227    where
17228        Self: UminEmitter<T0, T1, T2>,
17229    {
17230        <Self as UminEmitter<T0, T1, T2>>::umin(self, rd, rn, rm_or_imm);
17231    }
17232    /// Emits the `DGH` instruction.
17233    /// Assembly forms: `DGH`.
17234    pub fn dgh(&mut self)
17235    where
17236        Self: DghEmitter,
17237    {
17238        <Self as DghEmitter>::dgh(self);
17239    }
17240    /// Emits the `CFINV` instruction.
17241    /// Assembly forms: `CFINV`.
17242    pub fn cfinv(&mut self)
17243    where
17244        Self: CfinvEmitter,
17245    {
17246        <Self as CfinvEmitter>::cfinv(self);
17247    }
17248    /// Emits the `SETF8` instruction.
17249    /// Assembly forms: `SETF8 WN`.
17250    /// Operands: `rn`.
17251    pub fn setf8<T0>(&mut self, rn: T0)
17252    where
17253        Self: Setf8Emitter<T0>,
17254    {
17255        <Self as Setf8Emitter<T0>>::setf8(self, rn);
17256    }
17257    /// Emits the `SETF16` instruction.
17258    /// Assembly forms: `SETF16 WN`.
17259    /// Operands: `rn`.
17260    pub fn setf16<T0>(&mut self, rn: T0)
17261    where
17262        Self: Setf16Emitter<T0>,
17263    {
17264        <Self as Setf16Emitter<T0>>::setf16(self, rn);
17265    }
17266    /// Emits the `AXFLAG` instruction.
17267    /// Assembly forms: `AXFLAG`.
17268    pub fn axflag(&mut self)
17269    where
17270        Self: AxflagEmitter,
17271    {
17272        <Self as AxflagEmitter>::axflag(self);
17273    }
17274    /// Emits the `XAFLAG` instruction.
17275    /// Assembly forms: `XAFLAG`.
17276    pub fn xaflag(&mut self)
17277    where
17278        Self: XaflagEmitter,
17279    {
17280        <Self as XaflagEmitter>::xaflag(self);
17281    }
17282    /// Emits the `BC` instruction.
17283    /// Assembly forms: `BC.<COND> #RELS*4`.
17284    /// Operands: `target`.
17285    pub fn bc<T0>(&mut self, target: T0)
17286    where
17287        Self: BcEmitter<T0>,
17288    {
17289        <Self as BcEmitter<T0>>::bc(self, target);
17290    }
17291    /// Emits the `BC` instruction.
17292    /// Assembly forms: `BC.<COND> #RELS*4`.
17293    /// Operands: `target`.
17294    pub fn bc_eq<T0>(&mut self, target: T0)
17295    where
17296        Self: BcEmitter<T0>,
17297    {
17298        <Self as BcEmitter<T0>>::bc_eq(self, target);
17299    }
17300    /// Emits the `BC` instruction.
17301    /// Assembly forms: `BC.<COND> #RELS*4`.
17302    /// Operands: `target`.
17303    pub fn bc_ne<T0>(&mut self, target: T0)
17304    where
17305        Self: BcEmitter<T0>,
17306    {
17307        <Self as BcEmitter<T0>>::bc_ne(self, target);
17308    }
17309    /// Emits the `BC` instruction.
17310    /// Assembly forms: `BC.<COND> #RELS*4`.
17311    /// Operands: `target`.
17312    pub fn bc_cs<T0>(&mut self, target: T0)
17313    where
17314        Self: BcEmitter<T0>,
17315    {
17316        <Self as BcEmitter<T0>>::bc_cs(self, target);
17317    }
17318    /// Emits the `BC` instruction.
17319    /// Assembly forms: `BC.<COND> #RELS*4`.
17320    /// Operands: `target`.
17321    pub fn bc_hs<T0>(&mut self, target: T0)
17322    where
17323        Self: BcEmitter<T0>,
17324    {
17325        <Self as BcEmitter<T0>>::bc_hs(self, target);
17326    }
17327    /// Emits the `BC` instruction.
17328    /// Assembly forms: `BC.<COND> #RELS*4`.
17329    /// Operands: `target`.
17330    pub fn bc_cc<T0>(&mut self, target: T0)
17331    where
17332        Self: BcEmitter<T0>,
17333    {
17334        <Self as BcEmitter<T0>>::bc_cc(self, target);
17335    }
17336    /// Emits the `BC` instruction.
17337    /// Assembly forms: `BC.<COND> #RELS*4`.
17338    /// Operands: `target`.
17339    pub fn bc_lo<T0>(&mut self, target: T0)
17340    where
17341        Self: BcEmitter<T0>,
17342    {
17343        <Self as BcEmitter<T0>>::bc_lo(self, target);
17344    }
17345    /// Emits the `BC` instruction.
17346    /// Assembly forms: `BC.<COND> #RELS*4`.
17347    /// Operands: `target`.
17348    pub fn bc_mi<T0>(&mut self, target: T0)
17349    where
17350        Self: BcEmitter<T0>,
17351    {
17352        <Self as BcEmitter<T0>>::bc_mi(self, target);
17353    }
17354    /// Emits the `BC` instruction.
17355    /// Assembly forms: `BC.<COND> #RELS*4`.
17356    /// Operands: `target`.
17357    pub fn bc_pl<T0>(&mut self, target: T0)
17358    where
17359        Self: BcEmitter<T0>,
17360    {
17361        <Self as BcEmitter<T0>>::bc_pl(self, target);
17362    }
17363    /// Emits the `BC` instruction.
17364    /// Assembly forms: `BC.<COND> #RELS*4`.
17365    /// Operands: `target`.
17366    pub fn bc_vs<T0>(&mut self, target: T0)
17367    where
17368        Self: BcEmitter<T0>,
17369    {
17370        <Self as BcEmitter<T0>>::bc_vs(self, target);
17371    }
17372    /// Emits the `BC` instruction.
17373    /// Assembly forms: `BC.<COND> #RELS*4`.
17374    /// Operands: `target`.
17375    pub fn bc_vc<T0>(&mut self, target: T0)
17376    where
17377        Self: BcEmitter<T0>,
17378    {
17379        <Self as BcEmitter<T0>>::bc_vc(self, target);
17380    }
17381    /// Emits the `BC` instruction.
17382    /// Assembly forms: `BC.<COND> #RELS*4`.
17383    /// Operands: `target`.
17384    pub fn bc_hi<T0>(&mut self, target: T0)
17385    where
17386        Self: BcEmitter<T0>,
17387    {
17388        <Self as BcEmitter<T0>>::bc_hi(self, target);
17389    }
17390    /// Emits the `BC` instruction.
17391    /// Assembly forms: `BC.<COND> #RELS*4`.
17392    /// Operands: `target`.
17393    pub fn bc_ls<T0>(&mut self, target: T0)
17394    where
17395        Self: BcEmitter<T0>,
17396    {
17397        <Self as BcEmitter<T0>>::bc_ls(self, target);
17398    }
17399    /// Emits the `BC` instruction.
17400    /// Assembly forms: `BC.<COND> #RELS*4`.
17401    /// Operands: `target`.
17402    pub fn bc_ge<T0>(&mut self, target: T0)
17403    where
17404        Self: BcEmitter<T0>,
17405    {
17406        <Self as BcEmitter<T0>>::bc_ge(self, target);
17407    }
17408    /// Emits the `BC` instruction.
17409    /// Assembly forms: `BC.<COND> #RELS*4`.
17410    /// Operands: `target`.
17411    pub fn bc_lt<T0>(&mut self, target: T0)
17412    where
17413        Self: BcEmitter<T0>,
17414    {
17415        <Self as BcEmitter<T0>>::bc_lt(self, target);
17416    }
17417    /// Emits the `BC` instruction.
17418    /// Assembly forms: `BC.<COND> #RELS*4`.
17419    /// Operands: `target`.
17420    pub fn bc_gt<T0>(&mut self, target: T0)
17421    where
17422        Self: BcEmitter<T0>,
17423    {
17424        <Self as BcEmitter<T0>>::bc_gt(self, target);
17425    }
17426    /// Emits the `BC` instruction.
17427    /// Assembly forms: `BC.<COND> #RELS*4`.
17428    /// Operands: `target`.
17429    pub fn bc_le<T0>(&mut self, target: T0)
17430    where
17431        Self: BcEmitter<T0>,
17432    {
17433        <Self as BcEmitter<T0>>::bc_le(self, target);
17434    }
17435    /// Emits the `BC` instruction.
17436    /// Assembly forms: `BC.<COND> #RELS*4`.
17437    /// Operands: `target`.
17438    pub fn bc_al<T0>(&mut self, target: T0)
17439    where
17440        Self: BcEmitter<T0>,
17441    {
17442        <Self as BcEmitter<T0>>::bc_al(self, target);
17443    }
17444    /// Emits the `AUTDA` instruction.
17445    /// Assembly forms: `AUTDA XD, XN|SP`.
17446    /// Operands: `rd`, `rn`.
17447    pub fn autda<T0, T1>(&mut self, rd: T0, rn: T1)
17448    where
17449        Self: AutdaEmitter<T0, T1>,
17450    {
17451        <Self as AutdaEmitter<T0, T1>>::autda(self, rd, rn);
17452    }
17453    /// Emits the `AUTDB` instruction.
17454    /// Assembly forms: `AUTDB XD, XN|SP`.
17455    /// Operands: `rd`, `rn`.
17456    pub fn autdb<T0, T1>(&mut self, rd: T0, rn: T1)
17457    where
17458        Self: AutdbEmitter<T0, T1>,
17459    {
17460        <Self as AutdbEmitter<T0, T1>>::autdb(self, rd, rn);
17461    }
17462    /// Emits the `AUTDZA` instruction.
17463    /// Assembly forms: `AUTDZA XD`.
17464    /// Operands: `rd`.
17465    pub fn autdza<T0>(&mut self, rd: T0)
17466    where
17467        Self: AutdzaEmitter<T0>,
17468    {
17469        <Self as AutdzaEmitter<T0>>::autdza(self, rd);
17470    }
17471    /// Emits the `AUTDZB` instruction.
17472    /// Assembly forms: `AUTDZB XD`.
17473    /// Operands: `rd`.
17474    pub fn autdzb<T0>(&mut self, rd: T0)
17475    where
17476        Self: AutdzbEmitter<T0>,
17477    {
17478        <Self as AutdzbEmitter<T0>>::autdzb(self, rd);
17479    }
17480    /// Emits the `AUTIA` instruction.
17481    /// Assembly forms: `AUTIA XD, XN|SP`.
17482    /// Operands: `rd`, `rn`.
17483    pub fn autia<T0, T1>(&mut self, rd: T0, rn: T1)
17484    where
17485        Self: AutiaEmitter<T0, T1>,
17486    {
17487        <Self as AutiaEmitter<T0, T1>>::autia(self, rd, rn);
17488    }
17489    /// Emits the `AUTIA1716` instruction.
17490    /// Assembly forms: `AUTIA1716`.
17491    pub fn autia1716(&mut self)
17492    where
17493        Self: Autia1716Emitter,
17494    {
17495        <Self as Autia1716Emitter>::autia1716(self);
17496    }
17497    /// Emits the `AUTIASP` instruction.
17498    /// Assembly forms: `AUTIASP`.
17499    pub fn autiasp(&mut self)
17500    where
17501        Self: AutiaspEmitter,
17502    {
17503        <Self as AutiaspEmitter>::autiasp(self);
17504    }
17505    /// Emits the `AUTIAZ` instruction.
17506    /// Assembly forms: `AUTIAZ`.
17507    pub fn autiaz(&mut self)
17508    where
17509        Self: AutiazEmitter,
17510    {
17511        <Self as AutiazEmitter>::autiaz(self);
17512    }
17513    /// Emits the `AUTIB` instruction.
17514    /// Assembly forms: `AUTIB XD, XN|SP`.
17515    /// Operands: `rd`, `rn`.
17516    pub fn autib<T0, T1>(&mut self, rd: T0, rn: T1)
17517    where
17518        Self: AutibEmitter<T0, T1>,
17519    {
17520        <Self as AutibEmitter<T0, T1>>::autib(self, rd, rn);
17521    }
17522    /// Emits the `AUTIB1716` instruction.
17523    /// Assembly forms: `AUTIB1716`.
17524    pub fn autib1716(&mut self)
17525    where
17526        Self: Autib1716Emitter,
17527    {
17528        <Self as Autib1716Emitter>::autib1716(self);
17529    }
17530    /// Emits the `AUTIBSP` instruction.
17531    /// Assembly forms: `AUTIBSP`.
17532    pub fn autibsp(&mut self)
17533    where
17534        Self: AutibspEmitter,
17535    {
17536        <Self as AutibspEmitter>::autibsp(self);
17537    }
17538    /// Emits the `AUTIBZ` instruction.
17539    /// Assembly forms: `AUTIBZ`.
17540    pub fn autibz(&mut self)
17541    where
17542        Self: AutibzEmitter,
17543    {
17544        <Self as AutibzEmitter>::autibz(self);
17545    }
17546    /// Emits the `AUTIZA` instruction.
17547    /// Assembly forms: `AUTIZA XD`.
17548    /// Operands: `rd`.
17549    pub fn autiza<T0>(&mut self, rd: T0)
17550    where
17551        Self: AutizaEmitter<T0>,
17552    {
17553        <Self as AutizaEmitter<T0>>::autiza(self, rd);
17554    }
17555    /// Emits the `AUTIZB` instruction.
17556    /// Assembly forms: `AUTIZB XD`.
17557    /// Operands: `rd`.
17558    pub fn autizb<T0>(&mut self, rd: T0)
17559    where
17560        Self: AutizbEmitter<T0>,
17561    {
17562        <Self as AutizbEmitter<T0>>::autizb(self, rd);
17563    }
17564    /// Emits the `GMI` instruction.
17565    /// Assembly forms: `GMI XD, XN|SP, XM`.
17566    /// Operands: `rd`, `rn`, `rm`.
17567    pub fn gmi<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
17568    where
17569        Self: GmiEmitter<T0, T1, T2>,
17570    {
17571        <Self as GmiEmitter<T0, T1, T2>>::gmi(self, rd, rn, rm);
17572    }
17573    /// Emits the `CMPP` instruction.
17574    /// Assembly forms: `CMPP XN|SP, XM|SP`.
17575    /// Operands: `rn`, `rm`.
17576    pub fn cmpp<T0, T1>(&mut self, rn: T0, rm: T1)
17577    where
17578        Self: CmppEmitter<T0, T1>,
17579    {
17580        <Self as CmppEmitter<T0, T1>>::cmpp(self, rn, rm);
17581    }
17582    /// Emits the `ADDG` instruction.
17583    /// Assembly forms: `ADDG XD|SP, XN|SP, #IMM1, #IMM2`.
17584    /// Operands: `rd`, `rn`, `imm1`, `imm2`.
17585    pub fn addg<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, imm1: T2, imm2: T3)
17586    where
17587        Self: AddgEmitter<T0, T1, T2, T3>,
17588    {
17589        <Self as AddgEmitter<T0, T1, T2, T3>>::addg(self, rd, rn, imm1, imm2);
17590    }
17591    /// Emits the `LDG` instruction.
17592    /// Assembly forms: `LDG XD, [XN|SP, #OFFS*16]`.
17593    /// Operands: `rd`, `addr`.
17594    pub fn ldg<T0, T1>(&mut self, rd: T0, addr: T1)
17595    where
17596        Self: LdgEmitter<T0, T1>,
17597    {
17598        <Self as LdgEmitter<T0, T1>>::ldg(self, rd, addr);
17599    }
17600    /// Emits the `LDGM` instruction.
17601    /// Assembly forms: `LDGM XD, [XN|SP]`.
17602    /// Operands: `rd`, `addr`.
17603    pub fn ldgm<T0, T1>(&mut self, rd: T0, addr: T1)
17604    where
17605        Self: LdgmEmitter<T0, T1>,
17606    {
17607        <Self as LdgmEmitter<T0, T1>>::ldgm(self, rd, addr);
17608    }
17609    /// Emits the `LDRAA` instruction.
17610    /// Assembly forms: `LDRAA XD, [XN|SP, #OFFS]{!}`.
17611    /// Operands: `rd`, `addr`.
17612    pub fn ldraa<T0, T1>(&mut self, rd: T0, addr: T1)
17613    where
17614        Self: LdraaEmitter<T0, T1>,
17615    {
17616        <Self as LdraaEmitter<T0, T1>>::ldraa(self, rd, addr);
17617    }
17618    /// Emits the `LDRAB` instruction.
17619    /// Assembly forms: `LDRAB XD, [XN|SP, #OFFS]{!}`.
17620    /// Operands: `rd`, `addr`.
17621    pub fn ldrab<T0, T1>(&mut self, rd: T0, addr: T1)
17622    where
17623        Self: LdrabEmitter<T0, T1>,
17624    {
17625        <Self as LdrabEmitter<T0, T1>>::ldrab(self, rd, addr);
17626    }
17627    /// Emits the `PACDA` instruction.
17628    /// Assembly forms: `PACDA XD, XN|SP`.
17629    /// Operands: `rd`, `rn`.
17630    pub fn pacda<T0, T1>(&mut self, rd: T0, rn: T1)
17631    where
17632        Self: PacdaEmitter<T0, T1>,
17633    {
17634        <Self as PacdaEmitter<T0, T1>>::pacda(self, rd, rn);
17635    }
17636    /// Emits the `PACDB` instruction.
17637    /// Assembly forms: `PACDB XD, XN|SP`.
17638    /// Operands: `rd`, `rn`.
17639    pub fn pacdb<T0, T1>(&mut self, rd: T0, rn: T1)
17640    where
17641        Self: PacdbEmitter<T0, T1>,
17642    {
17643        <Self as PacdbEmitter<T0, T1>>::pacdb(self, rd, rn);
17644    }
17645    /// Emits the `PACDZA` instruction.
17646    /// Assembly forms: `PACDZA XD`.
17647    /// Operands: `rd`.
17648    pub fn pacdza<T0>(&mut self, rd: T0)
17649    where
17650        Self: PacdzaEmitter<T0>,
17651    {
17652        <Self as PacdzaEmitter<T0>>::pacdza(self, rd);
17653    }
17654    /// Emits the `PACDZB` instruction.
17655    /// Assembly forms: `PACDZB XD`.
17656    /// Operands: `rd`.
17657    pub fn pacdzb<T0>(&mut self, rd: T0)
17658    where
17659        Self: PacdzbEmitter<T0>,
17660    {
17661        <Self as PacdzbEmitter<T0>>::pacdzb(self, rd);
17662    }
17663    /// Emits the `PACGA` instruction.
17664    /// Assembly forms: `PACGA XD, XN, XM|SP`.
17665    /// Operands: `rd`, `rn`, `rm`.
17666    pub fn pacga<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
17667    where
17668        Self: PacgaEmitter<T0, T1, T2>,
17669    {
17670        <Self as PacgaEmitter<T0, T1, T2>>::pacga(self, rd, rn, rm);
17671    }
17672    /// Emits the `SUBP` instruction.
17673    /// Assembly forms: `SUBP XD, XN|SP, XM|SP`.
17674    /// Operands: `rd`, `rn`, `rm`.
17675    pub fn subp<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
17676    where
17677        Self: SubpEmitter<T0, T1, T2>,
17678    {
17679        <Self as SubpEmitter<T0, T1, T2>>::subp(self, rd, rn, rm);
17680    }
17681    /// Emits the `SUBPS` instruction.
17682    /// Assembly forms: `SUBPS XD, XN|SP, XM|SP`.
17683    /// Operands: `rd`, `rn`, `rm`.
17684    pub fn subps<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
17685    where
17686        Self: SubpsEmitter<T0, T1, T2>,
17687    {
17688        <Self as SubpsEmitter<T0, T1, T2>>::subps(self, rd, rn, rm);
17689    }
17690    /// Emits the `SUBG` instruction.
17691    /// Assembly forms: `SUBG XD|SP, XN|SP, #IMM1, #IMM2`.
17692    /// Operands: `rd`, `rn`, `imm1`, `imm2`.
17693    pub fn subg<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, imm1: T2, imm2: T3)
17694    where
17695        Self: SubgEmitter<T0, T1, T2, T3>,
17696    {
17697        <Self as SubgEmitter<T0, T1, T2, T3>>::subg(self, rd, rn, imm1, imm2);
17698    }
17699    /// Emits the `ST2G` instruction.
17700    /// Assembly forms: `ST2G XS|SP, [XN|SP, #OFFS*16]{@}{!}`.
17701    /// Operands: `rs`, `addr`.
17702    pub fn st2g<T0, T1>(&mut self, rs: T0, addr: T1)
17703    where
17704        Self: St2gEmitter<T0, T1>,
17705    {
17706        <Self as St2gEmitter<T0, T1>>::st2g(self, rs, addr);
17707    }
17708    /// Emits the `STG` instruction.
17709    /// Assembly forms: `STG XS|SP, [XN|SP, #OFFS*16]{@}{!}`.
17710    /// Operands: `rs`, `addr`.
17711    pub fn stg<T0, T1>(&mut self, rs: T0, addr: T1)
17712    where
17713        Self: StgEmitter<T0, T1>,
17714    {
17715        <Self as StgEmitter<T0, T1>>::stg(self, rs, addr);
17716    }
17717    /// Emits the `STGP` instruction.
17718    /// Assembly forms: `STGP XS, XS2, [XN|SP, #OFFS*16]{@}{!}`.
17719    /// Operands: `rs`, `rs2`, `addr`.
17720    pub fn stgp<T0, T1, T2>(&mut self, rs: T0, rs2: T1, addr: T2)
17721    where
17722        Self: StgpEmitter<T0, T1, T2>,
17723    {
17724        <Self as StgpEmitter<T0, T1, T2>>::stgp(self, rs, rs2, addr);
17725    }
17726    /// Emits the `STGM` instruction.
17727    /// Assembly forms: `STGM XS, [XN|SP]`.
17728    /// Operands: `rs`, `addr`.
17729    pub fn stgm<T0, T1>(&mut self, rs: T0, addr: T1)
17730    where
17731        Self: StgmEmitter<T0, T1>,
17732    {
17733        <Self as StgmEmitter<T0, T1>>::stgm(self, rs, addr);
17734    }
17735    /// Emits the `STZG` instruction.
17736    /// Assembly forms: `STZG XS|SP, [XN|SP, #OFFS*16]{@}{!}`.
17737    /// Operands: `rs`, `addr`.
17738    pub fn stzg<T0, T1>(&mut self, rs: T0, addr: T1)
17739    where
17740        Self: StzgEmitter<T0, T1>,
17741    {
17742        <Self as StzgEmitter<T0, T1>>::stzg(self, rs, addr);
17743    }
17744    /// Emits the `STZ2G` instruction.
17745    /// Assembly forms: `STZ2G XS|SP, [XN|SP, #OFFS*16]{@}{!}`.
17746    /// Operands: `rs`, `addr`.
17747    pub fn stz2g<T0, T1>(&mut self, rs: T0, addr: T1)
17748    where
17749        Self: Stz2gEmitter<T0, T1>,
17750    {
17751        <Self as Stz2gEmitter<T0, T1>>::stz2g(self, rs, addr);
17752    }
17753    /// Emits the `STZGM` instruction.
17754    /// Assembly forms: `STZGM XS, [XN|SP]`.
17755    /// Operands: `rs`, `addr`.
17756    pub fn stzgm<T0, T1>(&mut self, rs: T0, addr: T1)
17757    where
17758        Self: StzgmEmitter<T0, T1>,
17759    {
17760        <Self as StzgmEmitter<T0, T1>>::stzgm(self, rs, addr);
17761    }
17762    /// Emits the `XPACD` instruction.
17763    /// Assembly forms: `XPACD XD`.
17764    /// Operands: `rd`.
17765    pub fn xpacd<T0>(&mut self, rd: T0)
17766    where
17767        Self: XpacdEmitter<T0>,
17768    {
17769        <Self as XpacdEmitter<T0>>::xpacd(self, rd);
17770    }
17771    /// Emits the `XPACI` instruction.
17772    /// Assembly forms: `XPACI XD`.
17773    /// Operands: `rd`.
17774    pub fn xpaci<T0>(&mut self, rd: T0)
17775    where
17776        Self: XpaciEmitter<T0>,
17777    {
17778        <Self as XpaciEmitter<T0>>::xpaci(self, rd);
17779    }
17780    /// Emits the `XPACLRI` instruction.
17781    /// Assembly forms: `XPACLRI XD`.
17782    pub fn xpaclri(&mut self)
17783    where
17784        Self: XpaclriEmitter,
17785    {
17786        <Self as XpaclriEmitter>::xpaclri(self);
17787    }
17788    /// Emits the `HINT` instruction.
17789    /// Assembly forms: `HINT #IMM`.
17790    /// Operands: `imm`.
17791    pub fn hint<T0>(&mut self, imm: T0)
17792    where
17793        Self: HintEmitter<T0>,
17794    {
17795        <Self as HintEmitter<T0>>::hint(self, imm);
17796    }
17797    /// Emits the `NOP` instruction.
17798    /// Assembly forms: `NOP`.
17799    pub fn nop(&mut self)
17800    where
17801        Self: NopEmitter,
17802    {
17803        <Self as NopEmitter>::nop(self);
17804    }
17805    /// Emits the `SEV` instruction.
17806    /// Assembly forms: `SEV`.
17807    pub fn sev(&mut self)
17808    where
17809        Self: SevEmitter,
17810    {
17811        <Self as SevEmitter>::sev(self);
17812    }
17813    /// Emits the `SEVL` instruction.
17814    /// Assembly forms: `SEVL`.
17815    pub fn sevl(&mut self)
17816    where
17817        Self: SevlEmitter,
17818    {
17819        <Self as SevlEmitter>::sevl(self);
17820    }
17821    /// Emits the `WFE` instruction.
17822    /// Assembly forms: `WFE`.
17823    pub fn wfe(&mut self)
17824    where
17825        Self: WfeEmitter,
17826    {
17827        <Self as WfeEmitter>::wfe(self);
17828    }
17829    /// Emits the `WFI` instruction.
17830    /// Assembly forms: `WFI`.
17831    pub fn wfi(&mut self)
17832    where
17833        Self: WfiEmitter,
17834    {
17835        <Self as WfiEmitter>::wfi(self);
17836    }
17837    /// Emits the `YIELD` instruction.
17838    /// Assembly forms: `YIELD`.
17839    pub fn r#yield(&mut self)
17840    where
17841        Self: YieldEmitter,
17842    {
17843        <Self as YieldEmitter>::r#yield(self);
17844    }
17845    /// Emits the `ADDHN` instruction.
17846    /// Assembly forms: `ADDHN VD.TA, VN.TB, VM.TB`.
17847    /// Operands: `rd`, `rn`, `rm`.
17848    pub fn addhn<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
17849    where
17850        Self: AddhnEmitter<T0, T1, T2>,
17851    {
17852        <Self as AddhnEmitter<T0, T1, T2>>::addhn(self, rd, rn, rm);
17853    }
17854    /// Emits the `ADDHN2` instruction.
17855    /// Assembly forms: `ADDHN2 VX.TA, VN.TB, VM.TB`.
17856    /// Operands: `operand_1`, `rn`, `rm`.
17857    pub fn addhn2<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)
17858    where
17859        Self: Addhn2Emitter<T0, T1, T2>,
17860    {
17861        <Self as Addhn2Emitter<T0, T1, T2>>::addhn2(self, operand_1, rn, rm);
17862    }
17863    /// Emits the `ADDP` instruction.
17864    /// Assembly forms: `ADDP DD, VN.2D`; `ADDP VD.T, VN.T, VM.T`; `ADDP VD.T, VN.T, VM.T`.
17865    /// Operands: `rd`, `rn`.
17866    pub fn addp<T0, T1>(&mut self, rd: T0, rn: T1)
17867    where
17868        Self: AddpEmitter<T0, T1>,
17869    {
17870        <Self as AddpEmitter<T0, T1>>::addp(self, rd, rn);
17871    }
17872    /// Emits the `ADDP_3` instruction.
17873    /// Assembly forms: `ADDP DD, VN.2D`; `ADDP VD.T, VN.T, VM.T`; `ADDP VD.T, VN.T, VM.T`.
17874    /// Operands: `rd`, `rn`, `rm`.
17875    pub fn addp_3<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
17876    where
17877        Self: Addp3Emitter<T0, T1, T2>,
17878    {
17879        <Self as Addp3Emitter<T0, T1, T2>>::addp_3(self, rd, rn, rm);
17880    }
17881    /// Emits the `ADDV` instruction.
17882    /// Assembly forms: `ADDV BD, VN.8B`; `ADDV BD, VN.16B`; `ADDV HD, VN.4H`; `ADDV HD, VN.8H` (and related forms).
17883    /// Operands: `rd`, `rn`.
17884    pub fn addv<T0, T1>(&mut self, rd: T0, rn: T1)
17885    where
17886        Self: AddvEmitter<T0, T1>,
17887    {
17888        <Self as AddvEmitter<T0, T1>>::addv(self, rd, rn);
17889    }
17890    /// Emits the `BIC_2` instruction.
17891    /// Assembly forms: `BIC WD, WN, WM, {SOP #N}`; `BIC XD, XN, XM, {SOP #N}`; `BIC VD.8B, VN.8B, VM.8B`; `BIC VD.16B, VN.16B, VM.16B` (and related forms).
17892    /// Operands: `rd`, `rn_or_imm`.
17893    pub fn bic_2<T0, T1>(&mut self, rd: T0, rn_or_imm: T1)
17894    where
17895        Self: Bic2Emitter<T0, T1>,
17896    {
17897        <Self as Bic2Emitter<T0, T1>>::bic_2(self, rd, rn_or_imm);
17898    }
17899    /// Emits the `BIF` instruction.
17900    /// Assembly forms: `BIF DX.8B, VN.8B, VM.8B`; `BIF VX.16B, VN.16B, VM.16B`.
17901    /// Operands: `operand_1`, `rn`, `rm`.
17902    pub fn bif<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)
17903    where
17904        Self: BifEmitter<T0, T1, T2>,
17905    {
17906        <Self as BifEmitter<T0, T1, T2>>::bif(self, operand_1, rn, rm);
17907    }
17908    /// Emits the `BIT` instruction.
17909    /// Assembly forms: `BIT DX.8B, VN.8B, VM.8B`; `BIT VX.16B, VN.16B, VM.16B`.
17910    /// Operands: `operand_1`, `rn`, `rm`.
17911    pub fn bit<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)
17912    where
17913        Self: BitEmitter<T0, T1, T2>,
17914    {
17915        <Self as BitEmitter<T0, T1, T2>>::bit(self, operand_1, rn, rm);
17916    }
17917    /// Emits the `BSL` instruction.
17918    /// Assembly forms: `BSL DX.8B, VN.8B, VM.8B`; `BSL VX.16B, VN.16B, VM.16B`.
17919    /// Operands: `operand_1`, `rn`, `rm`.
17920    pub fn bsl<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)
17921    where
17922        Self: BslEmitter<T0, T1, T2>,
17923    {
17924        <Self as BslEmitter<T0, T1, T2>>::bsl(self, operand_1, rn, rm);
17925    }
17926    /// Emits the `CMEQ` instruction.
17927    /// Assembly forms: `CMEQ DD, DN, DM`; `CMEQ DD, DN, #0`; `CMEQ VD.T, VN.T, VM.T`; `CMEQ VD.T, VN.T, #0` (and related forms).
17928    /// Operands: `rd`, `rn`, `rm_or_operand_3`.
17929    pub fn cmeq<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm_or_operand_3: T2)
17930    where
17931        Self: CmeqEmitter<T0, T1, T2>,
17932    {
17933        <Self as CmeqEmitter<T0, T1, T2>>::cmeq(self, rd, rn, rm_or_operand_3);
17934    }
17935    /// Emits the `CMGE` instruction.
17936    /// Assembly forms: `CMGE DD, DN, DM`; `CMGE DD, DN, #0`; `CMGE VD.T, VN.T, VM.T`; `CMGE VD.T, VN.T, #0` (and related forms).
17937    /// Operands: `rd`, `rn`, `rm_or_operand_3`.
17938    pub fn cmge<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm_or_operand_3: T2)
17939    where
17940        Self: CmgeEmitter<T0, T1, T2>,
17941    {
17942        <Self as CmgeEmitter<T0, T1, T2>>::cmge(self, rd, rn, rm_or_operand_3);
17943    }
17944    /// Emits the `CMGT` instruction.
17945    /// Assembly forms: `CMGT DD, DN, DM`; `CMGT DD, DN, #0`; `CMGT VD.T, VN.T, VM.T`; `CMGT VD.T, VN.T, #0` (and related forms).
17946    /// Operands: `rd`, `rn`, `rm_or_operand_3`.
17947    pub fn cmgt<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm_or_operand_3: T2)
17948    where
17949        Self: CmgtEmitter<T0, T1, T2>,
17950    {
17951        <Self as CmgtEmitter<T0, T1, T2>>::cmgt(self, rd, rn, rm_or_operand_3);
17952    }
17953    /// Emits the `CMHI` instruction.
17954    /// Assembly forms: `CMHI DD, DN, DM`; `CMHI VD.T, VN.T, VM.T`; `CMHI VD.T, VN.T, VM.T`.
17955    /// Operands: `rd`, `rn`, `rm`.
17956    pub fn cmhi<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
17957    where
17958        Self: CmhiEmitter<T0, T1, T2>,
17959    {
17960        <Self as CmhiEmitter<T0, T1, T2>>::cmhi(self, rd, rn, rm);
17961    }
17962    /// Emits the `CMHS` instruction.
17963    /// Assembly forms: `CMHS DD, DN, DM`; `CMHS VD.T, VN.T, VM.T`; `CMHS VD.T, VN.T, VM.T`.
17964    /// Operands: `rd`, `rn`, `rm`.
17965    pub fn cmhs<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
17966    where
17967        Self: CmhsEmitter<T0, T1, T2>,
17968    {
17969        <Self as CmhsEmitter<T0, T1, T2>>::cmhs(self, rd, rn, rm);
17970    }
17971    /// Emits the `CMLE` instruction.
17972    /// Assembly forms: `CMLE DD, DN, #0`; `CMLE VD.T, VN.T, #0`; `CMLE VD.T, VN.T, #0`.
17973    /// Operands: `rd`, `rn`, `operand_3`.
17974    pub fn cmle<T0, T1, T2>(&mut self, rd: T0, rn: T1, operand_3: T2)
17975    where
17976        Self: CmleEmitter<T0, T1, T2>,
17977    {
17978        <Self as CmleEmitter<T0, T1, T2>>::cmle(self, rd, rn, operand_3);
17979    }
17980    /// Emits the `CMLT` instruction.
17981    /// Assembly forms: `CMLT DD, DN, #0`; `CMLT VD.T, VN.T, #0`; `CMLT VD.T, VN.T, #0`.
17982    /// Operands: `rd`, `rn`, `operand_3`.
17983    pub fn cmlt<T0, T1, T2>(&mut self, rd: T0, rn: T1, operand_3: T2)
17984    where
17985        Self: CmltEmitter<T0, T1, T2>,
17986    {
17987        <Self as CmltEmitter<T0, T1, T2>>::cmlt(self, rd, rn, operand_3);
17988    }
17989    /// Emits the `CMTST` instruction.
17990    /// Assembly forms: `CMTST DD, DN, DM`; `CMTST VD.T, VN.T, VM.T`; `CMTST VD.T, VN.T, VM.T`.
17991    /// Operands: `rd`, `rn`, `rm`.
17992    pub fn cmtst<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
17993    where
17994        Self: CmtstEmitter<T0, T1, T2>,
17995    {
17996        <Self as CmtstEmitter<T0, T1, T2>>::cmtst(self, rd, rn, rm);
17997    }
17998    /// Emits the `DUP` instruction.
17999    /// Assembly forms: `DUP|MOV BD, VN.B[#IDX]`; `DUP|MOV HD, VN.H[#IDX]`; `DUP|MOV SD, VN.S[#IDX]`; `DUP|MOV DD, VN.D[#IDX]` (and related forms).
18000    /// Operands: `rd`, `rn`.
18001    pub fn dup<T0, T1>(&mut self, rd: T0, rn: T1)
18002    where
18003        Self: DupEmitter<T0, T1>,
18004    {
18005        <Self as DupEmitter<T0, T1>>::dup(self, rd, rn);
18006    }
18007    /// Emits the `EXT` instruction.
18008    /// Assembly forms: `EXT VD.8B, VN.8B, VM.8B, #IDX`; `EXT VD.16B, VN.16B, VM.16B, #IDX`.
18009    /// Operands: `rd`, `rn`, `rm`, `idx`.
18010    pub fn ext<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm: T2, idx: T3)
18011    where
18012        Self: ExtEmitter<T0, T1, T2, T3>,
18013    {
18014        <Self as ExtEmitter<T0, T1, T2, T3>>::ext(self, rd, rn, rm, idx);
18015    }
18016    /// Emits the `FABD` instruction.
18017    /// Assembly forms: `FABD SD, SN, SM`; `FABD DD, DN, DM`; `FABD VD.2S, VN.2S, VM.2S`; `FABD VD.4S, VN.4S, VM.4S` (and related forms).
18018    /// Operands: `rd`, `rn`, `rm`.
18019    pub fn fabd<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
18020    where
18021        Self: FabdEmitter<T0, T1, T2>,
18022    {
18023        <Self as FabdEmitter<T0, T1, T2>>::fabd(self, rd, rn, rm);
18024    }
18025    /// Emits the `FABS` instruction.
18026    /// Assembly forms: `FABS SD, SN`; `FABS DD, DN`; `FABS VD.2S, VN.2S`; `FABS VD.4S, VN.4S` (and related forms).
18027    /// Operands: `rd`, `rn`.
18028    pub fn fabs<T0, T1>(&mut self, rd: T0, rn: T1)
18029    where
18030        Self: FabsEmitter<T0, T1>,
18031    {
18032        <Self as FabsEmitter<T0, T1>>::fabs(self, rd, rn);
18033    }
18034    /// Emits the `FACGE` instruction.
18035    /// Assembly forms: `FACGE SD, SN, SM`; `FACGE DD, DN, DM`; `FACGE VD.2S, VN.2S, VM.2S`; `FACGE VD.4S, VN.4S, VM.4S` (and related forms).
18036    /// Operands: `rd`, `rn`, `rm`.
18037    pub fn facge<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
18038    where
18039        Self: FacgeEmitter<T0, T1, T2>,
18040    {
18041        <Self as FacgeEmitter<T0, T1, T2>>::facge(self, rd, rn, rm);
18042    }
18043    /// Emits the `FACGT` instruction.
18044    /// Assembly forms: `FACGT SD, SN, SM`; `FACGT DD, DN, DM`; `FACGT VD.2S, VN.2S, VM.2S`; `FACGT VD.4S, VN.4S, VM.4S` (and related forms).
18045    /// Operands: `rd`, `rn`, `rm`.
18046    pub fn facgt<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
18047    where
18048        Self: FacgtEmitter<T0, T1, T2>,
18049    {
18050        <Self as FacgtEmitter<T0, T1, T2>>::facgt(self, rd, rn, rm);
18051    }
18052    /// Emits the `FADD` instruction.
18053    /// Assembly forms: `FADD SD, SN, SM`; `FADD DD, DN, DM`; `FADD VD.2S, VN.2S, VM.2S`; `FADD VD.4S, VN.4S, VM.4S` (and related forms).
18054    /// Operands: `rd`, `rn`, `rm`.
18055    pub fn fadd<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
18056    where
18057        Self: FaddEmitter<T0, T1, T2>,
18058    {
18059        <Self as FaddEmitter<T0, T1, T2>>::fadd(self, rd, rn, rm);
18060    }
18061    /// Emits the `FADDP` instruction.
18062    /// Assembly forms: `FADDP SD, VN.2S`; `FADDP DD, VN.2D`; `FADDP VD.2S, VN.2S, VM.2S`; `FADDP VD.4S, VN.4S, VM.4S` (and related forms).
18063    /// Operands: `rd`, `rn`.
18064    pub fn faddp<T0, T1>(&mut self, rd: T0, rn: T1)
18065    where
18066        Self: FaddpEmitter<T0, T1>,
18067    {
18068        <Self as FaddpEmitter<T0, T1>>::faddp(self, rd, rn);
18069    }
18070    /// Emits the `FADDP_3` instruction.
18071    /// Assembly forms: `FADDP SD, VN.2S`; `FADDP DD, VN.2D`; `FADDP VD.2S, VN.2S, VM.2S`; `FADDP VD.4S, VN.4S, VM.4S` (and related forms).
18072    /// Operands: `rd`, `rn`, `rm`.
18073    pub fn faddp_3<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
18074    where
18075        Self: Faddp3Emitter<T0, T1, T2>,
18076    {
18077        <Self as Faddp3Emitter<T0, T1, T2>>::faddp_3(self, rd, rn, rm);
18078    }
18079    /// Emits the `FCCMP` instruction.
18080    /// Assembly forms: `FCCMP SN, SM, #NZCV, #COND`; `FCCMP DN, DM, #NZCV, #COND`; `FCCMP HN, HM, #NZCV, #COND`.
18081    /// Operands: `rn`, `rm`, `flags`, `condition`.
18082    pub fn fccmp<T0, T1, T2, T3>(&mut self, rn: T0, rm: T1, flags: T2, condition: T3)
18083    where
18084        Self: FccmpEmitter<T0, T1, T2, T3>,
18085    {
18086        <Self as FccmpEmitter<T0, T1, T2, T3>>::fccmp(self, rn, rm, flags, condition);
18087    }
18088    /// Emits the `FCCMPE` instruction.
18089    /// Assembly forms: `FCCMPE SN, SM, #NZCV, #COND`; `FCCMPE DN, DM, #NZCV, #COND`; `FCCMPE HN, HM, #NZCV, #COND`.
18090    /// Operands: `rn`, `rm`, `flags`, `condition`.
18091    pub fn fccmpe<T0, T1, T2, T3>(&mut self, rn: T0, rm: T1, flags: T2, condition: T3)
18092    where
18093        Self: FccmpeEmitter<T0, T1, T2, T3>,
18094    {
18095        <Self as FccmpeEmitter<T0, T1, T2, T3>>::fccmpe(self, rn, rm, flags, condition);
18096    }
18097    /// Emits the `FCMEQ` instruction.
18098    /// Assembly forms: `FCMEQ SD, SN, SM`; `FCMEQ SD, SN, #0`; `FCMEQ DD, DN, DM`; `FCMEQ DD, DN, #0` (and related forms).
18099    /// Operands: `rd`, `rn`, `rm_or_operand_3`.
18100    pub fn fcmeq<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm_or_operand_3: T2)
18101    where
18102        Self: FcmeqEmitter<T0, T1, T2>,
18103    {
18104        <Self as FcmeqEmitter<T0, T1, T2>>::fcmeq(self, rd, rn, rm_or_operand_3);
18105    }
18106    /// Emits the `FCMGE` instruction.
18107    /// Assembly forms: `FCMGE SD, SN, SM`; `FCMGE SD, SN, #0`; `FCMGE DD, DN, DM`; `FCMGE DD, DN, #0` (and related forms).
18108    /// Operands: `rd`, `rn`, `rm_or_operand_3`.
18109    pub fn fcmge<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm_or_operand_3: T2)
18110    where
18111        Self: FcmgeEmitter<T0, T1, T2>,
18112    {
18113        <Self as FcmgeEmitter<T0, T1, T2>>::fcmge(self, rd, rn, rm_or_operand_3);
18114    }
18115    /// Emits the `FCMGT` instruction.
18116    /// Assembly forms: `FCMGT SD, SN, SM`; `FCMGT SD, SN, #0`; `FCMGT DD, DN, DM`; `FCMGT DD, DN, #0` (and related forms).
18117    /// Operands: `rd`, `rn`, `rm_or_operand_3`.
18118    pub fn fcmgt<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm_or_operand_3: T2)
18119    where
18120        Self: FcmgtEmitter<T0, T1, T2>,
18121    {
18122        <Self as FcmgtEmitter<T0, T1, T2>>::fcmgt(self, rd, rn, rm_or_operand_3);
18123    }
18124    /// Emits the `FCMLE` instruction.
18125    /// Assembly forms: `FCMLE SD, SN, #0`; `FCMLE DD, DN, #0`; `FCMLE VD.2S, VN.2S, #0`; `FCMLE VD.4S, VN.4S, #0` (and related forms).
18126    /// Operands: `rd`, `rn`, `operand_3`.
18127    pub fn fcmle<T0, T1, T2>(&mut self, rd: T0, rn: T1, operand_3: T2)
18128    where
18129        Self: FcmleEmitter<T0, T1, T2>,
18130    {
18131        <Self as FcmleEmitter<T0, T1, T2>>::fcmle(self, rd, rn, operand_3);
18132    }
18133    /// Emits the `FCMLT` instruction.
18134    /// Assembly forms: `FCMLT SD, SN, #0`; `FCMLT DD, DN, #0`; `FCMLT VD.2S, VN.2S, #0`; `FCMLT VD.4S, VN.4S, #0` (and related forms).
18135    /// Operands: `rd`, `rn`, `operand_3`.
18136    pub fn fcmlt<T0, T1, T2>(&mut self, rd: T0, rn: T1, operand_3: T2)
18137    where
18138        Self: FcmltEmitter<T0, T1, T2>,
18139    {
18140        <Self as FcmltEmitter<T0, T1, T2>>::fcmlt(self, rd, rn, operand_3);
18141    }
18142    /// Emits the `FCMP` instruction.
18143    /// Assembly forms: `FCMP SN, SM`; `FCMP SN, #0`; `FCMP DN, DM`; `FCMP DN, #0` (and related forms).
18144    /// Operands: `rn`, `rm_or_operand_2`.
18145    pub fn fcmp<T0, T1>(&mut self, rn: T0, rm_or_operand_2: T1)
18146    where
18147        Self: FcmpEmitter<T0, T1>,
18148    {
18149        <Self as FcmpEmitter<T0, T1>>::fcmp(self, rn, rm_or_operand_2);
18150    }
18151    /// Emits the `FCMPE` instruction.
18152    /// Assembly forms: `FCMPE SN, SM`; `FCMPE SN, #0`; `FCMPE DN, DM`; `FCMPE DN, #0` (and related forms).
18153    /// Operands: `rn`, `rm_or_operand_2`.
18154    pub fn fcmpe<T0, T1>(&mut self, rn: T0, rm_or_operand_2: T1)
18155    where
18156        Self: FcmpeEmitter<T0, T1>,
18157    {
18158        <Self as FcmpeEmitter<T0, T1>>::fcmpe(self, rn, rm_or_operand_2);
18159    }
18160    /// Emits the `FCSEL` instruction.
18161    /// Assembly forms: `FCSEL SD, SN, SM, #COND`; `FCSEL DD, DN, DM, #COND`; `FCSEL HD, HN, HM, #COND`.
18162    /// Operands: `rd`, `rn`, `rm`, `condition`.
18163    pub fn fcsel<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm: T2, condition: T3)
18164    where
18165        Self: FcselEmitter<T0, T1, T2, T3>,
18166    {
18167        <Self as FcselEmitter<T0, T1, T2, T3>>::fcsel(self, rd, rn, rm, condition);
18168    }
18169    /// Emits the `FCVT` instruction.
18170    /// Assembly forms: `FCVT SD, HN`; `FCVT DD, HN`; `FCVT HD, SN`; `FCVT DD, SN` (and related forms).
18171    /// Operands: `rd`, `rn`.
18172    pub fn fcvt<T0, T1>(&mut self, rd: T0, rn: T1)
18173    where
18174        Self: FcvtEmitter<T0, T1>,
18175    {
18176        <Self as FcvtEmitter<T0, T1>>::fcvt(self, rd, rn);
18177    }
18178    /// Emits the `FCVTAS` instruction.
18179    /// Assembly forms: `FCVTAS WD, SN`; `FCVTAS XD, SN`; `FCVTAS WD, DN`; `FCVTAS XD, DN` (and related forms).
18180    /// Operands: `rd`, `rn`.
18181    pub fn fcvtas<T0, T1>(&mut self, rd: T0, rn: T1)
18182    where
18183        Self: FcvtasEmitter<T0, T1>,
18184    {
18185        <Self as FcvtasEmitter<T0, T1>>::fcvtas(self, rd, rn);
18186    }
18187    /// Emits the `FCVTAU` instruction.
18188    /// Assembly forms: `FCVTAU WD, SN`; `FCVTAU XD, SN`; `FCVTAU WD, DN`; `FCVTAU XD, DN` (and related forms).
18189    /// Operands: `rd`, `rn`.
18190    pub fn fcvtau<T0, T1>(&mut self, rd: T0, rn: T1)
18191    where
18192        Self: FcvtauEmitter<T0, T1>,
18193    {
18194        <Self as FcvtauEmitter<T0, T1>>::fcvtau(self, rd, rn);
18195    }
18196    /// Emits the `FCVTL` instruction.
18197    /// Assembly forms: `FCVTL VD.4S, VN.4H`; `FCVTL VD.2D, VN.2S`.
18198    /// Operands: `rd`, `rn`.
18199    pub fn fcvtl<T0, T1>(&mut self, rd: T0, rn: T1)
18200    where
18201        Self: FcvtlEmitter<T0, T1>,
18202    {
18203        <Self as FcvtlEmitter<T0, T1>>::fcvtl(self, rd, rn);
18204    }
18205    /// Emits the `FCVTL2` instruction.
18206    /// Assembly forms: `FCVTL2 VD.4S, VN.8H`; `FCVTL2 VD.2D, VN.4S`.
18207    /// Operands: `rd`, `rn`.
18208    pub fn fcvtl2<T0, T1>(&mut self, rd: T0, rn: T1)
18209    where
18210        Self: Fcvtl2Emitter<T0, T1>,
18211    {
18212        <Self as Fcvtl2Emitter<T0, T1>>::fcvtl2(self, rd, rn);
18213    }
18214    /// Emits the `FCVTMS` instruction.
18215    /// Assembly forms: `FCVTMS WD, SN`; `FCVTMS XD, SN`; `FCVTMS WD, DN`; `FCVTMS XD, DN` (and related forms).
18216    /// Operands: `rd`, `rn`.
18217    pub fn fcvtms<T0, T1>(&mut self, rd: T0, rn: T1)
18218    where
18219        Self: FcvtmsEmitter<T0, T1>,
18220    {
18221        <Self as FcvtmsEmitter<T0, T1>>::fcvtms(self, rd, rn);
18222    }
18223    /// Emits the `FCVTMU` instruction.
18224    /// Assembly forms: `FCVTMU WD, SN`; `FCVTMU XD, SN`; `FCVTMU WD, DN`; `FCVTMU XD, DN` (and related forms).
18225    /// Operands: `rd`, `rn`.
18226    pub fn fcvtmu<T0, T1>(&mut self, rd: T0, rn: T1)
18227    where
18228        Self: FcvtmuEmitter<T0, T1>,
18229    {
18230        <Self as FcvtmuEmitter<T0, T1>>::fcvtmu(self, rd, rn);
18231    }
18232    /// Emits the `FCVTN` instruction.
18233    /// Assembly forms: `FCVTN VD.4S, VN.4H`; `FCVTN VD.2D, VN.2S`; `FCVTN VD.8B, VN.4H, VM.4H`; `FCVTN VD.16B, VN.8H, VM.8H` (and related forms).
18234    /// Operands: `rd`, `rn`.
18235    pub fn fcvtn<T0, T1>(&mut self, rd: T0, rn: T1)
18236    where
18237        Self: FcvtnEmitter<T0, T1>,
18238    {
18239        <Self as FcvtnEmitter<T0, T1>>::fcvtn(self, rd, rn);
18240    }
18241    /// Emits the `FCVTN2` instruction.
18242    /// Assembly forms: `FCVTN2 VD.4S, VN.8H`; `FCVTN2 VD.2D, VN.4S`; `FCVTN2 VX.16B, VN.4S, VM.4S`.
18243    /// Operands: `rd_or_operand_1`, `rn`.
18244    pub fn fcvtn2<T0, T1>(&mut self, rd_or_operand_1: T0, rn: T1)
18245    where
18246        Self: Fcvtn2Emitter<T0, T1>,
18247    {
18248        <Self as Fcvtn2Emitter<T0, T1>>::fcvtn2(self, rd_or_operand_1, rn);
18249    }
18250    /// Emits the `FCVTNS` instruction.
18251    /// Assembly forms: `FCVTNS WD, SN`; `FCVTNS XD, SN`; `FCVTNS WD, DN`; `FCVTNS XD, DN` (and related forms).
18252    /// Operands: `rd`, `rn`.
18253    pub fn fcvtns<T0, T1>(&mut self, rd: T0, rn: T1)
18254    where
18255        Self: FcvtnsEmitter<T0, T1>,
18256    {
18257        <Self as FcvtnsEmitter<T0, T1>>::fcvtns(self, rd, rn);
18258    }
18259    /// Emits the `FCVTNU` instruction.
18260    /// Assembly forms: `FCVTNU WD, SN`; `FCVTNU XD, SN`; `FCVTNU WD, DN`; `FCVTNU XD, DN` (and related forms).
18261    /// Operands: `rd`, `rn`.
18262    pub fn fcvtnu<T0, T1>(&mut self, rd: T0, rn: T1)
18263    where
18264        Self: FcvtnuEmitter<T0, T1>,
18265    {
18266        <Self as FcvtnuEmitter<T0, T1>>::fcvtnu(self, rd, rn);
18267    }
18268    /// Emits the `FCVTPS` instruction.
18269    /// Assembly forms: `FCVTPS WD, SN`; `FCVTPS XD, SN`; `FCVTPS WD, DN`; `FCVTPS XD, DN` (and related forms).
18270    /// Operands: `rd`, `rn`.
18271    pub fn fcvtps<T0, T1>(&mut self, rd: T0, rn: T1)
18272    where
18273        Self: FcvtpsEmitter<T0, T1>,
18274    {
18275        <Self as FcvtpsEmitter<T0, T1>>::fcvtps(self, rd, rn);
18276    }
18277    /// Emits the `FCVTPU` instruction.
18278    /// Assembly forms: `FCVTPU WD, SN`; `FCVTPU XD, SN`; `FCVTPU WD, DN`; `FCVTPU XD, DN` (and related forms).
18279    /// Operands: `rd`, `rn`.
18280    pub fn fcvtpu<T0, T1>(&mut self, rd: T0, rn: T1)
18281    where
18282        Self: FcvtpuEmitter<T0, T1>,
18283    {
18284        <Self as FcvtpuEmitter<T0, T1>>::fcvtpu(self, rd, rn);
18285    }
18286    /// Emits the `FCVTXN` instruction.
18287    /// Operands: `rd`, `rn`.
18288    pub fn fcvtxn<T0, T1>(&mut self, rd: T0, rn: T1)
18289    where
18290        Self: FcvtxnEmitter<T0, T1>,
18291    {
18292        <Self as FcvtxnEmitter<T0, T1>>::fcvtxn(self, rd, rn);
18293    }
18294    /// Emits the `FCVTXN2` instruction.
18295    /// Operands: `rd`, `rn`.
18296    pub fn fcvtxn2<T0, T1>(&mut self, rd: T0, rn: T1)
18297    where
18298        Self: Fcvtxn2Emitter<T0, T1>,
18299    {
18300        <Self as Fcvtxn2Emitter<T0, T1>>::fcvtxn2(self, rd, rn);
18301    }
18302    /// Emits the `FCVTZS` instruction.
18303    /// Assembly forms: `FCVTZS WD, SN`; `FCVTZS XD, SN`; `FCVTZS WD, DN`; `FCVTZS XD, DN` (and related forms).
18304    /// Operands: `rd`, `rn`.
18305    pub fn fcvtzs<T0, T1>(&mut self, rd: T0, rn: T1)
18306    where
18307        Self: FcvtzsEmitter<T0, T1>,
18308    {
18309        <Self as FcvtzsEmitter<T0, T1>>::fcvtzs(self, rd, rn);
18310    }
18311    /// Emits the `FCVTZS_3` instruction.
18312    /// Assembly forms: `FCVTZS WD, SN`; `FCVTZS XD, SN`; `FCVTZS WD, DN`; `FCVTZS XD, DN` (and related forms).
18313    /// Operands: `rd`, `rn`, `fbits`.
18314    pub fn fcvtzs_3<T0, T1, T2>(&mut self, rd: T0, rn: T1, fbits: T2)
18315    where
18316        Self: Fcvtzs3Emitter<T0, T1, T2>,
18317    {
18318        <Self as Fcvtzs3Emitter<T0, T1, T2>>::fcvtzs_3(self, rd, rn, fbits);
18319    }
18320    /// Emits the `FCVTZU` instruction.
18321    /// Assembly forms: `FCVTZU WD, SN`; `FCVTZU XD, SN`; `FCVTZU WD, DN`; `FCVTZU XD, DN` (and related forms).
18322    /// Operands: `rd`, `rn`.
18323    pub fn fcvtzu<T0, T1>(&mut self, rd: T0, rn: T1)
18324    where
18325        Self: FcvtzuEmitter<T0, T1>,
18326    {
18327        <Self as FcvtzuEmitter<T0, T1>>::fcvtzu(self, rd, rn);
18328    }
18329    /// Emits the `FCVTZU_3` instruction.
18330    /// Assembly forms: `FCVTZU WD, SN`; `FCVTZU XD, SN`; `FCVTZU WD, DN`; `FCVTZU XD, DN` (and related forms).
18331    /// Operands: `rd`, `rn`, `fbits`.
18332    pub fn fcvtzu_3<T0, T1, T2>(&mut self, rd: T0, rn: T1, fbits: T2)
18333    where
18334        Self: Fcvtzu3Emitter<T0, T1, T2>,
18335    {
18336        <Self as Fcvtzu3Emitter<T0, T1, T2>>::fcvtzu_3(self, rd, rn, fbits);
18337    }
18338    /// Emits the `FDIV` instruction.
18339    /// Assembly forms: `FDIV SD, SN, SM`; `FDIV DD, DN, DM`; `FDIV VD.2S, VN.2S, VM.2S`; `FDIV VD.4S, VN.4S, VM.4S` (and related forms).
18340    /// Operands: `rd`, `rn`, `rm`.
18341    pub fn fdiv<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
18342    where
18343        Self: FdivEmitter<T0, T1, T2>,
18344    {
18345        <Self as FdivEmitter<T0, T1, T2>>::fdiv(self, rd, rn, rm);
18346    }
18347    /// Emits the `FMADD` instruction.
18348    /// Assembly forms: `FMADD SD, SN, SM, SA`; `FMADD DD, DN, DM, DA`; `FMADD HD, HN, HM, HA`.
18349    /// Operands: `rd`, `rn`, `rm`, `operand_4`.
18350    pub fn fmadd<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm: T2, operand_4: T3)
18351    where
18352        Self: FmaddEmitter<T0, T1, T2, T3>,
18353    {
18354        <Self as FmaddEmitter<T0, T1, T2, T3>>::fmadd(self, rd, rn, rm, operand_4);
18355    }
18356    /// Emits the `FMAX` instruction.
18357    /// Assembly forms: `FMAX SD, SN, SM`; `FMAX DD, DN, DM`; `FMAX VD.2S, VN.2S, VM.2S`; `FMAX VD.4S, VN.4S, VM.4S` (and related forms).
18358    /// Operands: `rd`, `rn`, `rm`.
18359    pub fn fmax<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
18360    where
18361        Self: FmaxEmitter<T0, T1, T2>,
18362    {
18363        <Self as FmaxEmitter<T0, T1, T2>>::fmax(self, rd, rn, rm);
18364    }
18365    /// Emits the `FMAXNM` instruction.
18366    /// Assembly forms: `FMAXNM SD, SN, SM`; `FMAXNM DD, DN, DM`; `FMAXNM VD.2S, VN.2S, VM.2S`; `FMAXNM VD.2D, VN.2D, VM.2D` (and related forms).
18367    /// Operands: `rd`, `rn`, `rm`.
18368    pub fn fmaxnm<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
18369    where
18370        Self: FmaxnmEmitter<T0, T1, T2>,
18371    {
18372        <Self as FmaxnmEmitter<T0, T1, T2>>::fmaxnm(self, rd, rn, rm);
18373    }
18374    /// Emits the `FMAXNMP` instruction.
18375    /// Assembly forms: `FMAXNMP SD, VN.2S`; `FMAXNMP DD, VN.2D`; `FMAXNMP VD.2S, VN.2S, VM.2S`; `FMAXNMP VD.4S, VN.4S, VM.4S` (and related forms).
18376    /// Operands: `rd`, `rn`, `rm`.
18377    pub fn fmaxnmp<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
18378    where
18379        Self: FmaxnmpEmitter<T0, T1, T2>,
18380    {
18381        <Self as FmaxnmpEmitter<T0, T1, T2>>::fmaxnmp(self, rd, rn, rm);
18382    }
18383    /// Emits the `FMAXNMP_2` instruction.
18384    /// Assembly forms: `FMAXNMP SD, VN.2S`; `FMAXNMP DD, VN.2D`; `FMAXNMP VD.2S, VN.2S, VM.2S`; `FMAXNMP VD.4S, VN.4S, VM.4S` (and related forms).
18385    /// Operands: `rd`, `rn`.
18386    pub fn fmaxnmp_2<T0, T1>(&mut self, rd: T0, rn: T1)
18387    where
18388        Self: Fmaxnmp2Emitter<T0, T1>,
18389    {
18390        <Self as Fmaxnmp2Emitter<T0, T1>>::fmaxnmp_2(self, rd, rn);
18391    }
18392    /// Emits the `FMAXNMV` instruction.
18393    /// Assembly forms: `FMAXNMV SD, VN.4S`; `FMAXNMV HD, VN.4H`; `FMAXNMV HD, VN.8H`.
18394    /// Operands: `rd`, `rn`.
18395    pub fn fmaxnmv<T0, T1>(&mut self, rd: T0, rn: T1)
18396    where
18397        Self: FmaxnmvEmitter<T0, T1>,
18398    {
18399        <Self as FmaxnmvEmitter<T0, T1>>::fmaxnmv(self, rd, rn);
18400    }
18401    /// Emits the `FMAXP` instruction.
18402    /// Assembly forms: `FMAXP SD, VN.2S`; `FMAXP DD, VN.2D`; `FMAXP VD.2S, VN.2S, VM.2S`; `FMAXP VD.4S, VN.4S, VM.4S` (and related forms).
18403    /// Operands: `rd`, `rn`, `rm`.
18404    pub fn fmaxp<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
18405    where
18406        Self: FmaxpEmitter<T0, T1, T2>,
18407    {
18408        <Self as FmaxpEmitter<T0, T1, T2>>::fmaxp(self, rd, rn, rm);
18409    }
18410    /// Emits the `FMAXP_2` instruction.
18411    /// Assembly forms: `FMAXP SD, VN.2S`; `FMAXP DD, VN.2D`; `FMAXP VD.2S, VN.2S, VM.2S`; `FMAXP VD.4S, VN.4S, VM.4S` (and related forms).
18412    /// Operands: `rd`, `rn`.
18413    pub fn fmaxp_2<T0, T1>(&mut self, rd: T0, rn: T1)
18414    where
18415        Self: Fmaxp2Emitter<T0, T1>,
18416    {
18417        <Self as Fmaxp2Emitter<T0, T1>>::fmaxp_2(self, rd, rn);
18418    }
18419    /// Emits the `FMAXV` instruction.
18420    /// Assembly forms: `FMAXV SD, VN.4S`; `FMAXV HD, VN.4H`; `FMAXV HD, VN.8H`.
18421    /// Operands: `rd`, `rn`.
18422    pub fn fmaxv<T0, T1>(&mut self, rd: T0, rn: T1)
18423    where
18424        Self: FmaxvEmitter<T0, T1>,
18425    {
18426        <Self as FmaxvEmitter<T0, T1>>::fmaxv(self, rd, rn);
18427    }
18428    /// Emits the `FMIN` instruction.
18429    /// Assembly forms: `FMIN SD, SN, SM`; `FMIN DD, DN, DM`; `FMIN VD.2S, VN.2S, VM.2S`; `FMIN VD.4S, VN.4S, VM.4S` (and related forms).
18430    /// Operands: `rd`, `rn`, `rm`.
18431    pub fn fmin<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
18432    where
18433        Self: FminEmitter<T0, T1, T2>,
18434    {
18435        <Self as FminEmitter<T0, T1, T2>>::fmin(self, rd, rn, rm);
18436    }
18437    /// Emits the `FMINNM` instruction.
18438    /// Assembly forms: `FMINNM SD, SN, SM`; `FMINNM DD, DN, DM`; `FMINNM VD.2S, VN.2S, VM.2S`; `FMINNM VD.2D, VN.2D, VM.2D` (and related forms).
18439    /// Operands: `rd`, `rn`, `rm`.
18440    pub fn fminnm<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
18441    where
18442        Self: FminnmEmitter<T0, T1, T2>,
18443    {
18444        <Self as FminnmEmitter<T0, T1, T2>>::fminnm(self, rd, rn, rm);
18445    }
18446    /// Emits the `FMINNMV` instruction.
18447    /// Assembly forms: `FMINNMV SD, VN.4S`; `FMINNMV HD, VN.4H`; `FMINNMV HD, VN.8H`.
18448    /// Operands: `rd`, `rn`.
18449    pub fn fminnmv<T0, T1>(&mut self, rd: T0, rn: T1)
18450    where
18451        Self: FminnmvEmitter<T0, T1>,
18452    {
18453        <Self as FminnmvEmitter<T0, T1>>::fminnmv(self, rd, rn);
18454    }
18455    /// Emits the `FMINNMP` instruction.
18456    /// Assembly forms: `FMINNMP SD, VN.2S`; `FMINNMP DD, VN.2D`; `FMINNMP VD.2S, VN.2S, VM.2S`; `FMINNMP VD.4S, VN.4S, VM.4S` (and related forms).
18457    /// Operands: `rd`, `rn`, `rm`.
18458    pub fn fminnmp<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
18459    where
18460        Self: FminnmpEmitter<T0, T1, T2>,
18461    {
18462        <Self as FminnmpEmitter<T0, T1, T2>>::fminnmp(self, rd, rn, rm);
18463    }
18464    /// Emits the `FMINNMP_2` instruction.
18465    /// Assembly forms: `FMINNMP SD, VN.2S`; `FMINNMP DD, VN.2D`; `FMINNMP VD.2S, VN.2S, VM.2S`; `FMINNMP VD.4S, VN.4S, VM.4S` (and related forms).
18466    /// Operands: `rd`, `rn`.
18467    pub fn fminnmp_2<T0, T1>(&mut self, rd: T0, rn: T1)
18468    where
18469        Self: Fminnmp2Emitter<T0, T1>,
18470    {
18471        <Self as Fminnmp2Emitter<T0, T1>>::fminnmp_2(self, rd, rn);
18472    }
18473    /// Emits the `FMINP` instruction.
18474    /// Assembly forms: `FMINP SD, VN.2S`; `FMINP DD, VN.2D`; `FMINP VD.2S, VN.2S, VM.2S`; `FMINP VD.4S, VN.4S, VM.4S` (and related forms).
18475    /// Operands: `rd`, `rn`.
18476    pub fn fminp<T0, T1>(&mut self, rd: T0, rn: T1)
18477    where
18478        Self: FminpEmitter<T0, T1>,
18479    {
18480        <Self as FminpEmitter<T0, T1>>::fminp(self, rd, rn);
18481    }
18482    /// Emits the `FMINP_3` instruction.
18483    /// Assembly forms: `FMINP SD, VN.2S`; `FMINP DD, VN.2D`; `FMINP VD.2S, VN.2S, VM.2S`; `FMINP VD.4S, VN.4S, VM.4S` (and related forms).
18484    /// Operands: `rd`, `rn`, `rm`.
18485    pub fn fminp_3<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
18486    where
18487        Self: Fminp3Emitter<T0, T1, T2>,
18488    {
18489        <Self as Fminp3Emitter<T0, T1, T2>>::fminp_3(self, rd, rn, rm);
18490    }
18491    /// Emits the `FMINV` instruction.
18492    /// Assembly forms: `FMINV SD, VN.4S`; `FMINV HD, VN.4H`; `FMINV HD, VN.8H`.
18493    /// Operands: `rd`, `rn`.
18494    pub fn fminv<T0, T1>(&mut self, rd: T0, rn: T1)
18495    where
18496        Self: FminvEmitter<T0, T1>,
18497    {
18498        <Self as FminvEmitter<T0, T1>>::fminv(self, rd, rn);
18499    }
18500    /// Emits the `FMLA` instruction.
18501    /// Assembly forms: `FMLA SX, SN, VM.S[#IDX]`; `FMLA DX, DN, VM.D[#IDX]`; `FMLA VX.2S, VN.2S, VM.2S`; `FMLA VX.4S, VN.4S, VM.4S` (and related forms).
18502    /// Operands: `operand_1`, `rn`, `rm`.
18503    pub fn fmla<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)
18504    where
18505        Self: FmlaEmitter<T0, T1, T2>,
18506    {
18507        <Self as FmlaEmitter<T0, T1, T2>>::fmla(self, operand_1, rn, rm);
18508    }
18509    /// Emits the `FMLS` instruction.
18510    /// Assembly forms: `FMLS SX, SN, VM.S[#IDX]`; `FMLS DX, DN, VM.D[#IDX]`; `FMLS VX.2S, VN.2S, VM.2S`; `FMLS VX.4S, VN.4S, VM.4S` (and related forms).
18511    /// Operands: `operand_1`, `rn`, `rm`.
18512    pub fn fmls<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)
18513    where
18514        Self: FmlsEmitter<T0, T1, T2>,
18515    {
18516        <Self as FmlsEmitter<T0, T1, T2>>::fmls(self, operand_1, rn, rm);
18517    }
18518    /// Emits the `FMOV` instruction.
18519    /// Assembly forms: `FMOV WD, SN`; `FMOV XD, DN`; `FMOV XD, VN.D[#1]`; `FMOV SD, WN` (and related forms).
18520    /// Operands: `rd`, `rn_or_fimm`.
18521    pub fn fmov<T0, T1>(&mut self, rd: T0, rn_or_fimm: T1)
18522    where
18523        Self: FmovEmitter<T0, T1>,
18524    {
18525        <Self as FmovEmitter<T0, T1>>::fmov(self, rd, rn_or_fimm);
18526    }
18527    /// Emits the `FMSUB` instruction.
18528    /// Assembly forms: `FMSUB SD, SN, SM, SA`; `FMSUB DD, DN, DM, DA`; `FMSUB HD, HN, HM, HA`.
18529    /// Operands: `rd`, `rn`, `rm`, `operand_4`.
18530    pub fn fmsub<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm: T2, operand_4: T3)
18531    where
18532        Self: FmsubEmitter<T0, T1, T2, T3>,
18533    {
18534        <Self as FmsubEmitter<T0, T1, T2, T3>>::fmsub(self, rd, rn, rm, operand_4);
18535    }
18536    /// Emits the `FMUL` instruction.
18537    /// Assembly forms: `FMUL SD, SN, SM`; `FMUL DD, DN, DM`; `FMUL SD, SN, VM.S[#IDX]`; `FMUL DD, DN, VM.D[#IDX]` (and related forms).
18538    /// Operands: `rd`, `rn`, `rm`.
18539    pub fn fmul<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
18540    where
18541        Self: FmulEmitter<T0, T1, T2>,
18542    {
18543        <Self as FmulEmitter<T0, T1, T2>>::fmul(self, rd, rn, rm);
18544    }
18545    /// Emits the `FMULX` instruction.
18546    /// Assembly forms: `FMULX SD, SN, SM`; `FMULX DD, DN, DM`; `FMULX SD, SN, VM.S[#IDX]`; `FMULX DD, DN, VM.D[#IDX]` (and related forms).
18547    /// Operands: `rd`, `rn`, `rm`.
18548    pub fn fmulx<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
18549    where
18550        Self: FmulxEmitter<T0, T1, T2>,
18551    {
18552        <Self as FmulxEmitter<T0, T1, T2>>::fmulx(self, rd, rn, rm);
18553    }
18554    /// Emits the `FNEG` instruction.
18555    /// Assembly forms: `FNEG SD, SN`; `FNEG DD, DN`; `FNEG VD.2S, VN.2S`; `FNEG VD.4S, VN.4S` (and related forms).
18556    /// Operands: `rd`, `rn`.
18557    pub fn fneg<T0, T1>(&mut self, rd: T0, rn: T1)
18558    where
18559        Self: FnegEmitter<T0, T1>,
18560    {
18561        <Self as FnegEmitter<T0, T1>>::fneg(self, rd, rn);
18562    }
18563    /// Emits the `FNMADD` instruction.
18564    /// Assembly forms: `FNMADD SD, SN, SM, SA`; `FNMADD DD, DN, DM, DA`; `FNMADD HD, HN, HM, HA`.
18565    /// Operands: `rd`, `rn`, `rm`, `operand_4`.
18566    pub fn fnmadd<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm: T2, operand_4: T3)
18567    where
18568        Self: FnmaddEmitter<T0, T1, T2, T3>,
18569    {
18570        <Self as FnmaddEmitter<T0, T1, T2, T3>>::fnmadd(self, rd, rn, rm, operand_4);
18571    }
18572    /// Emits the `FNMSUB` instruction.
18573    /// Assembly forms: `FNMSUB SD, SN, SM, SA`; `FNMSUB DD, DN, DM, DA`; `FNMSUB HD, HN, HM, HA`.
18574    /// Operands: `rd`, `rn`, `rm`, `operand_4`.
18575    pub fn fnmsub<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm: T2, operand_4: T3)
18576    where
18577        Self: FnmsubEmitter<T0, T1, T2, T3>,
18578    {
18579        <Self as FnmsubEmitter<T0, T1, T2, T3>>::fnmsub(self, rd, rn, rm, operand_4);
18580    }
18581    /// Emits the `FNMUL` instruction.
18582    /// Assembly forms: `FNMUL SD, SN, SM`; `FNMUL DD, DN, DM`; `FNMUL HD, HN, HM`.
18583    /// Operands: `rd`, `rn`, `rm`.
18584    pub fn fnmul<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
18585    where
18586        Self: FnmulEmitter<T0, T1, T2>,
18587    {
18588        <Self as FnmulEmitter<T0, T1, T2>>::fnmul(self, rd, rn, rm);
18589    }
18590    /// Emits the `FRECPE` instruction.
18591    /// Assembly forms: `FRECPE SD, SN`; `FRECPE DD, DN`; `FRECPE VD.2S, VN.2S`; `FRECPE VD.4S, VN.4S` (and related forms).
18592    /// Operands: `rd`, `rn`.
18593    pub fn frecpe<T0, T1>(&mut self, rd: T0, rn: T1)
18594    where
18595        Self: FrecpeEmitter<T0, T1>,
18596    {
18597        <Self as FrecpeEmitter<T0, T1>>::frecpe(self, rd, rn);
18598    }
18599    /// Emits the `FRECPS` instruction.
18600    /// Assembly forms: `FRECPS SD, SN, SM`; `FRECPS DD, DN, DM`; `FRECPS VD.2S, VN.2S, VM.2S`; `FRECPS VD.4S, VN.4S, VM.4S` (and related forms).
18601    /// Operands: `rd`, `rn`, `rm`.
18602    pub fn frecps<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
18603    where
18604        Self: FrecpsEmitter<T0, T1, T2>,
18605    {
18606        <Self as FrecpsEmitter<T0, T1, T2>>::frecps(self, rd, rn, rm);
18607    }
18608    /// Emits the `FRECPX` instruction.
18609    /// Assembly forms: `FRECPX SD, SN, SM`; `FRECPX DD, DN, DM`; `FRECPX HD, HN, HM`.
18610    /// Operands: `rd`, `rn`.
18611    pub fn frecpx<T0, T1>(&mut self, rd: T0, rn: T1)
18612    where
18613        Self: FrecpxEmitter<T0, T1>,
18614    {
18615        <Self as FrecpxEmitter<T0, T1>>::frecpx(self, rd, rn);
18616    }
18617    /// Emits the `FRINT32X` instruction.
18618    /// Assembly forms: `FRINT32X SD, SN`; `FRINT32X DD, DN`; `FRINT32X VD.2S, VN.2S`; `FRINT32X VD.4S, VN.4S` (and related forms).
18619    /// Operands: `rd`, `rn`.
18620    pub fn frint32x<T0, T1>(&mut self, rd: T0, rn: T1)
18621    where
18622        Self: Frint32xEmitter<T0, T1>,
18623    {
18624        <Self as Frint32xEmitter<T0, T1>>::frint32x(self, rd, rn);
18625    }
18626    /// Emits the `FRINT32Z` instruction.
18627    /// Assembly forms: `FRINT32Z SD, SN`; `FRINT32Z DD, DN`; `FRINT32Z VD.2S, VN.2S`; `FRINT32Z VD.4S, VN.4S` (and related forms).
18628    /// Operands: `rd`, `rn`.
18629    pub fn frint32z<T0, T1>(&mut self, rd: T0, rn: T1)
18630    where
18631        Self: Frint32zEmitter<T0, T1>,
18632    {
18633        <Self as Frint32zEmitter<T0, T1>>::frint32z(self, rd, rn);
18634    }
18635    /// Emits the `FRINT64X` instruction.
18636    /// Assembly forms: `FRINT64X SD, SN`; `FRINT64X DD, DN`; `FRINT64X VD.2S, VN.2S`; `FRINT64X VD.4S, VN.4S` (and related forms).
18637    /// Operands: `rd`, `rn`.
18638    pub fn frint64x<T0, T1>(&mut self, rd: T0, rn: T1)
18639    where
18640        Self: Frint64xEmitter<T0, T1>,
18641    {
18642        <Self as Frint64xEmitter<T0, T1>>::frint64x(self, rd, rn);
18643    }
18644    /// Emits the `FRINT64Z` instruction.
18645    /// Assembly forms: `FRINT64Z SD, SN`; `FRINT64Z DD, DN`; `FRINT64Z VD.2S, VN.2S`; `FRINT64Z VD.4S, VN.4S` (and related forms).
18646    /// Operands: `rd`, `rn`.
18647    pub fn frint64z<T0, T1>(&mut self, rd: T0, rn: T1)
18648    where
18649        Self: Frint64zEmitter<T0, T1>,
18650    {
18651        <Self as Frint64zEmitter<T0, T1>>::frint64z(self, rd, rn);
18652    }
18653    /// Emits the `FRINTA` instruction.
18654    /// Assembly forms: `FRINTA SD, SN`; `FRINTA DD, DN`; `FRINTA VD.2S, VN.2S`; `FRINTA VD.4S, VN.4S` (and related forms).
18655    /// Operands: `rd`, `rn`.
18656    pub fn frinta<T0, T1>(&mut self, rd: T0, rn: T1)
18657    where
18658        Self: FrintaEmitter<T0, T1>,
18659    {
18660        <Self as FrintaEmitter<T0, T1>>::frinta(self, rd, rn);
18661    }
18662    /// Emits the `FRINTI` instruction.
18663    /// Assembly forms: `FRINTI SD, SN`; `FRINTI DD, DN`; `FRINTI VD.2S, VN.2S`; `FRINTI VD.4S, VN.4S` (and related forms).
18664    /// Operands: `rd`, `rn`.
18665    pub fn frinti<T0, T1>(&mut self, rd: T0, rn: T1)
18666    where
18667        Self: FrintiEmitter<T0, T1>,
18668    {
18669        <Self as FrintiEmitter<T0, T1>>::frinti(self, rd, rn);
18670    }
18671    /// Emits the `FRINTM` instruction.
18672    /// Assembly forms: `FRINTM SD, SN`; `FRINTM DD, DN`; `FRINTM VD.2S, VN.2S`; `FRINTM VD.4S, VN.4S` (and related forms).
18673    /// Operands: `rd`, `rn`.
18674    pub fn frintm<T0, T1>(&mut self, rd: T0, rn: T1)
18675    where
18676        Self: FrintmEmitter<T0, T1>,
18677    {
18678        <Self as FrintmEmitter<T0, T1>>::frintm(self, rd, rn);
18679    }
18680    /// Emits the `FRINTN` instruction.
18681    /// Assembly forms: `FRINTN SD, SN`; `FRINTN DD, DN`; `FRINTN VD.2S, VN.2S`; `FRINTN VD.4S, VN.4S` (and related forms).
18682    /// Operands: `rd`, `rn`.
18683    pub fn frintn<T0, T1>(&mut self, rd: T0, rn: T1)
18684    where
18685        Self: FrintnEmitter<T0, T1>,
18686    {
18687        <Self as FrintnEmitter<T0, T1>>::frintn(self, rd, rn);
18688    }
18689    /// Emits the `FRINTP` instruction.
18690    /// Assembly forms: `FRINTP SD, SN`; `FRINTP DD, DN`; `FRINTP VD.2S, VN.2S`; `FRINTP VD.4S, VN.4S` (and related forms).
18691    /// Operands: `rd`, `rn`.
18692    pub fn frintp<T0, T1>(&mut self, rd: T0, rn: T1)
18693    where
18694        Self: FrintpEmitter<T0, T1>,
18695    {
18696        <Self as FrintpEmitter<T0, T1>>::frintp(self, rd, rn);
18697    }
18698    /// Emits the `FRINTX` instruction.
18699    /// Assembly forms: `FRINTX SD, SN`; `FRINTX DD, DN`; `FRINTX VD.2S, VN.2S`; `FRINTX VD.4S, VN.4S` (and related forms).
18700    /// Operands: `rd`, `rn`.
18701    pub fn frintx<T0, T1>(&mut self, rd: T0, rn: T1)
18702    where
18703        Self: FrintxEmitter<T0, T1>,
18704    {
18705        <Self as FrintxEmitter<T0, T1>>::frintx(self, rd, rn);
18706    }
18707    /// Emits the `FRINTZ` instruction.
18708    /// Assembly forms: `FRINTZ SD, SN`; `FRINTZ DD, DN`; `FRINTZ VD.2S, VN.2S`; `FRINTZ VD.4S, VN.4S` (and related forms).
18709    /// Operands: `rd`, `rn`.
18710    pub fn frintz<T0, T1>(&mut self, rd: T0, rn: T1)
18711    where
18712        Self: FrintzEmitter<T0, T1>,
18713    {
18714        <Self as FrintzEmitter<T0, T1>>::frintz(self, rd, rn);
18715    }
18716    /// Emits the `FRSQRTE` instruction.
18717    /// Assembly forms: `FRSQRTE SD, SN`; `FRSQRTE DD, DN`; `FRSQRTE VD.2S, VN.2S`; `FRSQRTE VD.4S, VN.4S` (and related forms).
18718    /// Operands: `rd`, `rn`.
18719    pub fn frsqrte<T0, T1>(&mut self, rd: T0, rn: T1)
18720    where
18721        Self: FrsqrteEmitter<T0, T1>,
18722    {
18723        <Self as FrsqrteEmitter<T0, T1>>::frsqrte(self, rd, rn);
18724    }
18725    /// Emits the `FRSQRTS` instruction.
18726    /// Assembly forms: `FRSQRTS SD, SN, SM`; `FRSQRTS DD, DN, DM`; `FRSQRTS VD.2S, VN.2S, VM.2S`; `FRSQRTS VD.4S, VN.4S, VM.4S` (and related forms).
18727    /// Operands: `rd`, `rn`, `rm`.
18728    pub fn frsqrts<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
18729    where
18730        Self: FrsqrtsEmitter<T0, T1, T2>,
18731    {
18732        <Self as FrsqrtsEmitter<T0, T1, T2>>::frsqrts(self, rd, rn, rm);
18733    }
18734    /// Emits the `FSQRT` instruction.
18735    /// Assembly forms: `FSQRT SD, SN`; `FSQRT DD, DN`; `FSQRT VD.2S, VN.2S`; `FSQRT VD.4S, VN.4S` (and related forms).
18736    /// Operands: `rd`, `rn`.
18737    pub fn fsqrt<T0, T1>(&mut self, rd: T0, rn: T1)
18738    where
18739        Self: FsqrtEmitter<T0, T1>,
18740    {
18741        <Self as FsqrtEmitter<T0, T1>>::fsqrt(self, rd, rn);
18742    }
18743    /// Emits the `FSUB` instruction.
18744    /// Assembly forms: `FSUB SD, SN, SM`; `FSUB DD, DN, DM`; `FSUB VD.2S, VN.2S, VM.2S`; `FSUB VD.4S, VN.4S, VM.4S` (and related forms).
18745    /// Operands: `rd`, `rn`, `rm`.
18746    pub fn fsub<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
18747    where
18748        Self: FsubEmitter<T0, T1, T2>,
18749    {
18750        <Self as FsubEmitter<T0, T1, T2>>::fsub(self, rd, rn, rm);
18751    }
18752    /// Emits the `INS` instruction.
18753    /// Assembly forms: `INS|MOV VD.B[#IDX], WN`; `INS|MOV VD.H[#IDX], WN`; `INS|MOV VD.S[#IDX], WN`; `INS|MOV VD.D[#IDX], XN` (and related forms).
18754    /// Operands: `rd`, `rn`.
18755    pub fn ins<T0, T1>(&mut self, rd: T0, rn: T1)
18756    where
18757        Self: InsEmitter<T0, T1>,
18758    {
18759        <Self as InsEmitter<T0, T1>>::ins(self, rd, rn);
18760    }
18761    /// Emits the `LD1` instruction.
18762    /// Assembly forms: `LD1 VX.B[#IDX], [XN|SP]`; `LD1 VX.H[#IDX], [XN|SP]`; `LD1 VX.S[#IDX], [XN|SP]`; `LD1 VX.D[#IDX], [XN|SP]` (and related forms).
18763    /// Operands: `idx_or_operand_1`, `addr`.
18764    pub fn ld1<T0, T1>(&mut self, idx_or_operand_1: T0, addr: T1)
18765    where
18766        Self: Ld1Emitter<T0, T1>,
18767    {
18768        <Self as Ld1Emitter<T0, T1>>::ld1(self, idx_or_operand_1, addr);
18769    }
18770    /// Emits the `LD1_3` instruction.
18771    /// Assembly forms: `LD1 VX.B[#IDX], [XN|SP]`; `LD1 VX.H[#IDX], [XN|SP]`; `LD1 VX.S[#IDX], [XN|SP]`; `LD1 VX.D[#IDX], [XN|SP]` (and related forms).
18772    /// Operands: `rd`, `rn`, `addr`.
18773    pub fn ld1_3<T0, T1, T2>(&mut self, rd: T0, rn: T1, addr: T2)
18774    where
18775        Self: Ld13Emitter<T0, T1, T2>,
18776    {
18777        <Self as Ld13Emitter<T0, T1, T2>>::ld1_3(self, rd, rn, addr);
18778    }
18779    /// Emits the `LD1_4` instruction.
18780    /// Assembly forms: `LD1 VX.B[#IDX], [XN|SP]`; `LD1 VX.H[#IDX], [XN|SP]`; `LD1 VX.S[#IDX], [XN|SP]`; `LD1 VX.D[#IDX], [XN|SP]` (and related forms).
18781    /// Operands: `rd`, `rn`, `rm1`, `addr`.
18782    pub fn ld1_4<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm1: T2, addr: T3)
18783    where
18784        Self: Ld14Emitter<T0, T1, T2, T3>,
18785    {
18786        <Self as Ld14Emitter<T0, T1, T2, T3>>::ld1_4(self, rd, rn, rm1, addr);
18787    }
18788    /// Emits the `LD1_5` instruction.
18789    /// Assembly forms: `LD1 VX.B[#IDX], [XN|SP]`; `LD1 VX.H[#IDX], [XN|SP]`; `LD1 VX.S[#IDX], [XN|SP]`; `LD1 VX.D[#IDX], [XN|SP]` (and related forms).
18790    /// Operands: `rd`, `rn`, `rm1`, `rm2`, `addr`.
18791    pub fn ld1_5<T0, T1, T2, T3, T4>(&mut self, rd: T0, rn: T1, rm1: T2, rm2: T3, addr: T4)
18792    where
18793        Self: Ld15Emitter<T0, T1, T2, T3, T4>,
18794    {
18795        <Self as Ld15Emitter<T0, T1, T2, T3, T4>>::ld1_5(self, rd, rn, rm1, rm2, addr);
18796    }
18797    /// Emits the `LD1R` instruction.
18798    /// Assembly forms: `LD1R 1X{VD.T}, [XN|SP]`; `LD1R 1X{VD.T}, [XN|SP]`; `LD1R 1X{VD.T}, [XN|SP, XM]@`; `LD1R 1X{VD.T}, [XN|SP, XM]@` (and related forms).
18799    /// Operands: `operand_1`, `addr`.
18800    pub fn ld1r<T0, T1>(&mut self, operand_1: T0, addr: T1)
18801    where
18802        Self: Ld1rEmitter<T0, T1>,
18803    {
18804        <Self as Ld1rEmitter<T0, T1>>::ld1r(self, operand_1, addr);
18805    }
18806    /// Emits the `LD2` instruction.
18807    /// Assembly forms: `LD2 2X{VX.B}[#IDX], [XN|SP]`; `LD2 2X{VX.H}[#IDX], [XN|SP]`; `LD2 2X{VX.S}[#IDX], [XN|SP]`; `LD2 2X{VX.D}[#IDX], [XN|SP]` (and related forms).
18808    /// Operands: `rd`, `rn`, `addr`.
18809    pub fn ld2<T0, T1, T2>(&mut self, rd: T0, rn: T1, addr: T2)
18810    where
18811        Self: Ld2Emitter<T0, T1, T2>,
18812    {
18813        <Self as Ld2Emitter<T0, T1, T2>>::ld2(self, rd, rn, addr);
18814    }
18815    /// Emits the `LD2R` instruction.
18816    /// Assembly forms: `LD2R 2X{VD.T}, [XN|SP]`; `LD2R 2X{VD.T}, [XN|SP]`; `LD2R 2X{VD.T}, [XN|SP, XM]@`; `LD2R 2X{VD.T}, [XN|SP, XM]@` (and related forms).
18817    /// Operands: `rd`, `rn`, `addr`.
18818    pub fn ld2r<T0, T1, T2>(&mut self, rd: T0, rn: T1, addr: T2)
18819    where
18820        Self: Ld2rEmitter<T0, T1, T2>,
18821    {
18822        <Self as Ld2rEmitter<T0, T1, T2>>::ld2r(self, rd, rn, addr);
18823    }
18824    /// Emits the `LD3` instruction.
18825    /// Assembly forms: `LD3 3X{VX.B}[#IDX], [XN|SP]`; `LD3 3X{VX.H}[#IDX], [XN|SP]`; `LD3 3X{VX.S}[#IDX], [XN|SP]`; `LD3 3X{VX.D}[#IDX], [XN|SP]` (and related forms).
18826    /// Operands: `rd`, `rn`, `rm1`, `addr`.
18827    pub fn ld3<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm1: T2, addr: T3)
18828    where
18829        Self: Ld3Emitter<T0, T1, T2, T3>,
18830    {
18831        <Self as Ld3Emitter<T0, T1, T2, T3>>::ld3(self, rd, rn, rm1, addr);
18832    }
18833    /// Emits the `LD3R` instruction.
18834    /// Assembly forms: `LD3R 3X{VD.T}, [XN|SP]`; `LD3R 3X{VD.T}, [XN|SP]`; `LD3R 3X{VD.T}, [XN|SP, XM]@`; `LD3R 3X{VD.T}, [XN|SP, XM]@` (and related forms).
18835    /// Operands: `rd`, `rn`, `rm1`, `addr`.
18836    pub fn ld3r<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm1: T2, addr: T3)
18837    where
18838        Self: Ld3rEmitter<T0, T1, T2, T3>,
18839    {
18840        <Self as Ld3rEmitter<T0, T1, T2, T3>>::ld3r(self, rd, rn, rm1, addr);
18841    }
18842    /// Emits the `LD4` instruction.
18843    /// Assembly forms: `LD4 4X{VX.B}[#IDX], [XN|SP]`; `LD4 4X{VX.H}[#IDX], [XN|SP]`; `LD4 4X{VX.S}[#IDX], [XN|SP]`; `LD4 4X{VX.D}[#IDX], [XN|SP]` (and related forms).
18844    /// Operands: `rd`, `rn`, `rm1`, `rm2`, `addr`.
18845    pub fn ld4<T0, T1, T2, T3, T4>(&mut self, rd: T0, rn: T1, rm1: T2, rm2: T3, addr: T4)
18846    where
18847        Self: Ld4Emitter<T0, T1, T2, T3, T4>,
18848    {
18849        <Self as Ld4Emitter<T0, T1, T2, T3, T4>>::ld4(self, rd, rn, rm1, rm2, addr);
18850    }
18851    /// Emits the `LD4R` instruction.
18852    /// Assembly forms: `LD4R 4X{VD.T}, [XN|SP]`; `LD4R 4X{VD.T}, [XN|SP]`; `LD4R 4X{VD.T}, [XN|SP, XM]@`; `LD4R 4X{VD.T}, [XN|SP, XM]@` (and related forms).
18853    /// Operands: `rd`, `rn`, `rm1`, `rm2`, `addr`.
18854    pub fn ld4r<T0, T1, T2, T3, T4>(&mut self, rd: T0, rn: T1, rm1: T2, rm2: T3, addr: T4)
18855    where
18856        Self: Ld4rEmitter<T0, T1, T2, T3, T4>,
18857    {
18858        <Self as Ld4rEmitter<T0, T1, T2, T3, T4>>::ld4r(self, rd, rn, rm1, rm2, addr);
18859    }
18860    /// Emits the `MLA` instruction.
18861    /// Assembly forms: `MLA VX.T, VN.T, VM.T`; `MLA VX.T, VN.T, VM.T`; `MLA VX.4H, VN.4H, VM.H[#IDX]`; `MLA VX.8H, VN.8H, VM.H[#IDX]` (and related forms).
18862    /// Operands: `operand_1`, `rn`, `rm`.
18863    pub fn mla<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)
18864    where
18865        Self: MlaEmitter<T0, T1, T2>,
18866    {
18867        <Self as MlaEmitter<T0, T1, T2>>::mla(self, operand_1, rn, rm);
18868    }
18869    /// Emits the `MLS` instruction.
18870    /// Assembly forms: `MLS VX.T, VN.T, VM.T`; `MLS VX.T, VN.T, VM.T`; `MLS VX.4H, VN.4H, VM.H[#IDX]`; `MLS VX.8H, VN.8H, VM.H[#IDX]` (and related forms).
18871    /// Operands: `operand_1`, `rn`, `rm`.
18872    pub fn mls<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)
18873    where
18874        Self: MlsEmitter<T0, T1, T2>,
18875    {
18876        <Self as MlsEmitter<T0, T1, T2>>::mls(self, operand_1, rn, rm);
18877    }
18878    /// Emits the `MOVI` instruction.
18879    /// Assembly forms: `MOVI DD, #IMM, {LSL #N}`; `MOVI VD.T, #IMM, {LSL #N}`; `MOVI VD.T, #IMM, {LSL #N}`.
18880    /// Operands: `rd`, `imm`.
18881    pub fn movi<T0, T1>(&mut self, rd: T0, imm: T1)
18882    where
18883        Self: MoviEmitter<T0, T1>,
18884    {
18885        <Self as MoviEmitter<T0, T1>>::movi(self, rd, imm);
18886    }
18887    /// Emits the `MOVI_3` instruction.
18888    /// Assembly forms: `MOVI DD, #IMM, {LSL #N}`; `MOVI VD.T, #IMM, {LSL #N}`; `MOVI VD.T, #IMM, {LSL #N}`.
18889    /// Operands: `rd`, `imm`, `shift`.
18890    pub fn movi_3<T0, T1, T2>(&mut self, rd: T0, imm: T1, shift: T2)
18891    where
18892        Self: Movi3Emitter<T0, T1, T2>,
18893    {
18894        <Self as Movi3Emitter<T0, T1, T2>>::movi_3(self, rd, imm, shift);
18895    }
18896    /// Emits the `MVNI` instruction.
18897    /// Assembly forms: `MVNI DD, #IMM, {LSL #N}`; `MVNI VD.T, #IMM, {LSL #N}`; `MVNI VD.T, #IMM, {LSL #N}`.
18898    /// Operands: `rd`, `imm`.
18899    pub fn mvni<T0, T1>(&mut self, rd: T0, imm: T1)
18900    where
18901        Self: MvniEmitter<T0, T1>,
18902    {
18903        <Self as MvniEmitter<T0, T1>>::mvni(self, rd, imm);
18904    }
18905    /// Emits the `MVNI_3` instruction.
18906    /// Assembly forms: `MVNI DD, #IMM, {LSL #N}`; `MVNI VD.T, #IMM, {LSL #N}`; `MVNI VD.T, #IMM, {LSL #N}`.
18907    /// Operands: `rd`, `imm`, `shift`.
18908    pub fn mvni_3<T0, T1, T2>(&mut self, rd: T0, imm: T1, shift: T2)
18909    where
18910        Self: Mvni3Emitter<T0, T1, T2>,
18911    {
18912        <Self as Mvni3Emitter<T0, T1, T2>>::mvni_3(self, rd, imm, shift);
18913    }
18914    /// Emits the `NOT_` instruction.
18915    /// Assembly forms: `NOT|MVN VD.8B, VN.8B`; `NOT|MVN VD.16B, VN.16B`.
18916    /// Operands: `rd`, `rn`.
18917    pub fn not_<T0, T1>(&mut self, rd: T0, rn: T1)
18918    where
18919        Self: NotEmitter<T0, T1>,
18920    {
18921        <Self as NotEmitter<T0, T1>>::not_(self, rd, rn);
18922    }
18923    /// Emits the `ORR_2` instruction.
18924    /// Assembly forms: `ORR WD, WN, WM, {SOP #N}`; `ORR XD, XN, XM, {SOP #N}`; `ORR WD|WSP, WN, #LOG_IMM`; `ORR XD|SP, XN, #LOG_IMM` (and related forms).
18925    /// Operands: `rd`, `rn_or_imm`.
18926    pub fn orr_2<T0, T1>(&mut self, rd: T0, rn_or_imm: T1)
18927    where
18928        Self: Orr2Emitter<T0, T1>,
18929    {
18930        <Self as Orr2Emitter<T0, T1>>::orr_2(self, rd, rn_or_imm);
18931    }
18932    /// Emits the `PMUL` instruction.
18933    /// Assembly forms: `PMUL VD.8B, VN.8B, VM.8B`; `PMUL VD.16B, VN.16B, VM.16B`.
18934    /// Operands: `rd`, `rn`, `rm`.
18935    pub fn pmul<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
18936    where
18937        Self: PmulEmitter<T0, T1, T2>,
18938    {
18939        <Self as PmulEmitter<T0, T1, T2>>::pmul(self, rd, rn, rm);
18940    }
18941    /// Emits the `PMULL` instruction.
18942    /// Assembly forms: `PMULL VD.8H, VN.8B, VM.8B`; `PMULL VD.1Q, VN.1D, VM.1D`.
18943    /// Operands: `rd`, `rn`, `rm`.
18944    pub fn pmull<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
18945    where
18946        Self: PmullEmitter<T0, T1, T2>,
18947    {
18948        <Self as PmullEmitter<T0, T1, T2>>::pmull(self, rd, rn, rm);
18949    }
18950    /// Emits the `PMULL2` instruction.
18951    /// Assembly forms: `PMULL2 VD.8H, VN.16B, VM.16B`; `PMULL2 VD.1Q, VN.2D, VM.2D`.
18952    /// Operands: `rd`, `rn`, `rm`.
18953    pub fn pmull2<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
18954    where
18955        Self: Pmull2Emitter<T0, T1, T2>,
18956    {
18957        <Self as Pmull2Emitter<T0, T1, T2>>::pmull2(self, rd, rn, rm);
18958    }
18959    /// Emits the `RADDHN` instruction.
18960    /// Assembly forms: `RADDHN VD.TA, VN.TB, VM.TB`.
18961    /// Operands: `rd`, `rn`, `rm`.
18962    pub fn raddhn<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
18963    where
18964        Self: RaddhnEmitter<T0, T1, T2>,
18965    {
18966        <Self as RaddhnEmitter<T0, T1, T2>>::raddhn(self, rd, rn, rm);
18967    }
18968    /// Emits the `RADDHN2` instruction.
18969    /// Assembly forms: `RADDHN2 VX.TA, VN.TB, VM.TB`.
18970    /// Operands: `operand_1`, `rn`, `rm`.
18971    pub fn raddhn2<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)
18972    where
18973        Self: Raddhn2Emitter<T0, T1, T2>,
18974    {
18975        <Self as Raddhn2Emitter<T0, T1, T2>>::raddhn2(self, operand_1, rn, rm);
18976    }
18977    /// Emits the `RSHRN` instruction.
18978    /// Assembly forms: `RSHRN VD.TA, VN.TB, #N`.
18979    /// Operands: `rd`, `rn`, `shift`.
18980    pub fn rshrn<T0, T1, T2>(&mut self, rd: T0, rn: T1, shift: T2)
18981    where
18982        Self: RshrnEmitter<T0, T1, T2>,
18983    {
18984        <Self as RshrnEmitter<T0, T1, T2>>::rshrn(self, rd, rn, shift);
18985    }
18986    /// Emits the `RSHRN2` instruction.
18987    /// Assembly forms: `RSHRN2 VX.TA, VN.TB, #N`.
18988    /// Operands: `operand_1`, `rn`, `shift`.
18989    pub fn rshrn2<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, shift: T2)
18990    where
18991        Self: Rshrn2Emitter<T0, T1, T2>,
18992    {
18993        <Self as Rshrn2Emitter<T0, T1, T2>>::rshrn2(self, operand_1, rn, shift);
18994    }
18995    /// Emits the `RSUBHN` instruction.
18996    /// Assembly forms: `RSUBHN VD.TA, VN.TB, VM.TB`.
18997    /// Operands: `rd`, `rn`, `rm`.
18998    pub fn rsubhn<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
18999    where
19000        Self: RsubhnEmitter<T0, T1, T2>,
19001    {
19002        <Self as RsubhnEmitter<T0, T1, T2>>::rsubhn(self, rd, rn, rm);
19003    }
19004    /// Emits the `RSUBHN2` instruction.
19005    /// Assembly forms: `RSUBHN2 VX.TA, VN.TB, VM.TB`.
19006    /// Operands: `operand_1`, `rn`, `rm`.
19007    pub fn rsubhn2<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)
19008    where
19009        Self: Rsubhn2Emitter<T0, T1, T2>,
19010    {
19011        <Self as Rsubhn2Emitter<T0, T1, T2>>::rsubhn2(self, operand_1, rn, rm);
19012    }
19013    /// Emits the `SABA` instruction.
19014    /// Assembly forms: `SABA VX.T, VN.T, VM.T`; `SABA VX.T, VN.T, VM.T`.
19015    /// Operands: `operand_1`, `rn`, `rm`.
19016    pub fn saba<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)
19017    where
19018        Self: SabaEmitter<T0, T1, T2>,
19019    {
19020        <Self as SabaEmitter<T0, T1, T2>>::saba(self, operand_1, rn, rm);
19021    }
19022    /// Emits the `SABAL` instruction.
19023    /// Assembly forms: `SABAL VX.TA, VN.TB, VM.TB`.
19024    /// Operands: `operand_1`, `rn`, `rm`.
19025    pub fn sabal<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)
19026    where
19027        Self: SabalEmitter<T0, T1, T2>,
19028    {
19029        <Self as SabalEmitter<T0, T1, T2>>::sabal(self, operand_1, rn, rm);
19030    }
19031    /// Emits the `SABAL2` instruction.
19032    /// Assembly forms: `SABAL2 VX.TA, VN.TB, VM.TB`.
19033    /// Operands: `operand_1`, `rn`, `rm`.
19034    pub fn sabal2<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)
19035    where
19036        Self: Sabal2Emitter<T0, T1, T2>,
19037    {
19038        <Self as Sabal2Emitter<T0, T1, T2>>::sabal2(self, operand_1, rn, rm);
19039    }
19040    /// Emits the `SABD` instruction.
19041    /// Assembly forms: `SABD VD.T, VN.T, VM.T`; `SABD VD.T, VN.T, VM.T`.
19042    /// Operands: `rd`, `rn`, `rm`.
19043    pub fn sabd<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
19044    where
19045        Self: SabdEmitter<T0, T1, T2>,
19046    {
19047        <Self as SabdEmitter<T0, T1, T2>>::sabd(self, rd, rn, rm);
19048    }
19049    /// Emits the `SABDL` instruction.
19050    /// Assembly forms: `SABDL VD.TA, VN.TB, VM.TB`.
19051    /// Operands: `rd`, `rn`, `rm`.
19052    pub fn sabdl<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
19053    where
19054        Self: SabdlEmitter<T0, T1, T2>,
19055    {
19056        <Self as SabdlEmitter<T0, T1, T2>>::sabdl(self, rd, rn, rm);
19057    }
19058    /// Emits the `SABDL2` instruction.
19059    /// Assembly forms: `SABDL2 VD.TA, VN.TB, VM.TB`.
19060    /// Operands: `rd`, `rn`, `rm`.
19061    pub fn sabdl2<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
19062    where
19063        Self: Sabdl2Emitter<T0, T1, T2>,
19064    {
19065        <Self as Sabdl2Emitter<T0, T1, T2>>::sabdl2(self, rd, rn, rm);
19066    }
19067    /// Emits the `SADALP` instruction.
19068    /// Assembly forms: `SADALP VX.TA, VN.TB`; `SADALP VX.TA, VN.TB`.
19069    /// Operands: `operand_1`, `rn`.
19070    pub fn sadalp<T0, T1>(&mut self, operand_1: T0, rn: T1)
19071    where
19072        Self: SadalpEmitter<T0, T1>,
19073    {
19074        <Self as SadalpEmitter<T0, T1>>::sadalp(self, operand_1, rn);
19075    }
19076    /// Emits the `SADDL` instruction.
19077    /// Assembly forms: `SADDL VD.TA, VN.TB, VM.TB`.
19078    /// Operands: `rd`, `rn`, `rm`.
19079    pub fn saddl<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
19080    where
19081        Self: SaddlEmitter<T0, T1, T2>,
19082    {
19083        <Self as SaddlEmitter<T0, T1, T2>>::saddl(self, rd, rn, rm);
19084    }
19085    /// Emits the `SADDL2` instruction.
19086    /// Assembly forms: `SADDL2 VD.TA, VN.TB, VM.TB`.
19087    /// Operands: `rd`, `rn`, `rm`.
19088    pub fn saddl2<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
19089    where
19090        Self: Saddl2Emitter<T0, T1, T2>,
19091    {
19092        <Self as Saddl2Emitter<T0, T1, T2>>::saddl2(self, rd, rn, rm);
19093    }
19094    /// Emits the `SADDLP` instruction.
19095    /// Assembly forms: `SADDLP VD.TA, VN.TB`; `SADDLP VD.TA, VN.TB`.
19096    /// Operands: `rd`, `rn`.
19097    pub fn saddlp<T0, T1>(&mut self, rd: T0, rn: T1)
19098    where
19099        Self: SaddlpEmitter<T0, T1>,
19100    {
19101        <Self as SaddlpEmitter<T0, T1>>::saddlp(self, rd, rn);
19102    }
19103    /// Emits the `SADDLV` instruction.
19104    /// Assembly forms: `SADDLV HD, VN.8B`; `SADDLV HD, VN.16B`; `SADDLV SD, VN.4H`; `SADDLV SD, VN.8H` (and related forms).
19105    /// Operands: `rd`, `rn`.
19106    pub fn saddlv<T0, T1>(&mut self, rd: T0, rn: T1)
19107    where
19108        Self: SaddlvEmitter<T0, T1>,
19109    {
19110        <Self as SaddlvEmitter<T0, T1>>::saddlv(self, rd, rn);
19111    }
19112    /// Emits the `SADDW` instruction.
19113    /// Assembly forms: `SADDW VD.TA, VN.TA, VM.TB`.
19114    /// Operands: `rd`, `rn`, `rm`.
19115    pub fn saddw<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
19116    where
19117        Self: SaddwEmitter<T0, T1, T2>,
19118    {
19119        <Self as SaddwEmitter<T0, T1, T2>>::saddw(self, rd, rn, rm);
19120    }
19121    /// Emits the `SADDW2` instruction.
19122    /// Assembly forms: `SADDW2 VD.TA, VN.TA, VM.TB`.
19123    /// Operands: `rd`, `rn`, `rm`.
19124    pub fn saddw2<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
19125    where
19126        Self: Saddw2Emitter<T0, T1, T2>,
19127    {
19128        <Self as Saddw2Emitter<T0, T1, T2>>::saddw2(self, rd, rn, rm);
19129    }
19130    /// Emits the `SCVTF` instruction.
19131    /// Assembly forms: `SCVTF SD, WN`; `SCVTF SD, WN, #FBITS`; `SCVTF SD, XN`; `SCVTF SD, XN, #FBITS` (and related forms).
19132    /// Operands: `rd`, `rn`.
19133    pub fn scvtf<T0, T1>(&mut self, rd: T0, rn: T1)
19134    where
19135        Self: ScvtfEmitter<T0, T1>,
19136    {
19137        <Self as ScvtfEmitter<T0, T1>>::scvtf(self, rd, rn);
19138    }
19139    /// Emits the `SCVTF_3` instruction.
19140    /// Assembly forms: `SCVTF SD, WN`; `SCVTF SD, WN, #FBITS`; `SCVTF SD, XN`; `SCVTF SD, XN, #FBITS` (and related forms).
19141    /// Operands: `rd`, `rn`, `fbits_or_bits`.
19142    pub fn scvtf_3<T0, T1, T2>(&mut self, rd: T0, rn: T1, fbits_or_bits: T2)
19143    where
19144        Self: Scvtf3Emitter<T0, T1, T2>,
19145    {
19146        <Self as Scvtf3Emitter<T0, T1, T2>>::scvtf_3(self, rd, rn, fbits_or_bits);
19147    }
19148    /// Emits the `SHADD` instruction.
19149    /// Assembly forms: `SHADD VD.T, VN.T, VM.T`; `SHADD VD.T, VN.T, VM.T`.
19150    /// Operands: `rd`, `rn`, `rm`.
19151    pub fn shadd<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
19152    where
19153        Self: ShaddEmitter<T0, T1, T2>,
19154    {
19155        <Self as ShaddEmitter<T0, T1, T2>>::shadd(self, rd, rn, rm);
19156    }
19157    /// Emits the `SHL` instruction.
19158    /// Assembly forms: `SHL DD, DN, #N`; `SHL VD.T, VN.T, #N`; `SHL VD.T, VN.T, #N`.
19159    /// Operands: `rd`, `rn`, `shift`.
19160    pub fn shl<T0, T1, T2>(&mut self, rd: T0, rn: T1, shift: T2)
19161    where
19162        Self: ShlEmitter<T0, T1, T2>,
19163    {
19164        <Self as ShlEmitter<T0, T1, T2>>::shl(self, rd, rn, shift);
19165    }
19166    /// Emits the `SHLL` instruction.
19167    /// Assembly forms: `SHLL VD.8H, VN.8B, #8`; `SHLL VD.4S, VN.4H, #16`; `SHLL VD.2D, VN.2S, #32`.
19168    /// Operands: `rd`, `rn`, `operand_3`.
19169    pub fn shll<T0, T1, T2>(&mut self, rd: T0, rn: T1, operand_3: T2)
19170    where
19171        Self: ShllEmitter<T0, T1, T2>,
19172    {
19173        <Self as ShllEmitter<T0, T1, T2>>::shll(self, rd, rn, operand_3);
19174    }
19175    /// Emits the `SHLL2` instruction.
19176    /// Assembly forms: `SHLL2 VD.8H, VN.16B, #8`; `SHLL2 VD.4S, VN.8H, #16`; `SHLL2 VD.2D, VN.4S, #32`.
19177    /// Operands: `rd`, `rn`, `operand_3`.
19178    pub fn shll2<T0, T1, T2>(&mut self, rd: T0, rn: T1, operand_3: T2)
19179    where
19180        Self: Shll2Emitter<T0, T1, T2>,
19181    {
19182        <Self as Shll2Emitter<T0, T1, T2>>::shll2(self, rd, rn, operand_3);
19183    }
19184    /// Emits the `SHRN` instruction.
19185    /// Assembly forms: `SHRN VD.TA, VN.TB, #N`.
19186    /// Operands: `rd`, `rn`, `shift`.
19187    pub fn shrn<T0, T1, T2>(&mut self, rd: T0, rn: T1, shift: T2)
19188    where
19189        Self: ShrnEmitter<T0, T1, T2>,
19190    {
19191        <Self as ShrnEmitter<T0, T1, T2>>::shrn(self, rd, rn, shift);
19192    }
19193    /// Emits the `SHRN2` instruction.
19194    /// Assembly forms: `SHRN2 VX.TA, VN.TB, #N`.
19195    /// Operands: `operand_1`, `rn`, `shift`.
19196    pub fn shrn2<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, shift: T2)
19197    where
19198        Self: Shrn2Emitter<T0, T1, T2>,
19199    {
19200        <Self as Shrn2Emitter<T0, T1, T2>>::shrn2(self, operand_1, rn, shift);
19201    }
19202    /// Emits the `SHSUB` instruction.
19203    /// Assembly forms: `SHSUB VD.T, VN.T, VM.T`; `SHSUB VD.T, VN.T, VM.T`.
19204    /// Operands: `rd`, `rn`, `rm`.
19205    pub fn shsub<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
19206    where
19207        Self: ShsubEmitter<T0, T1, T2>,
19208    {
19209        <Self as ShsubEmitter<T0, T1, T2>>::shsub(self, rd, rn, rm);
19210    }
19211    /// Emits the `SLI` instruction.
19212    /// Assembly forms: `SLI DX, DN, #N`; `SLI VX.T, VN.T, #N`; `SLI VX.T, VN.T, #N`.
19213    /// Operands: `operand_1`, `rn`, `shift`.
19214    pub fn sli<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, shift: T2)
19215    where
19216        Self: SliEmitter<T0, T1, T2>,
19217    {
19218        <Self as SliEmitter<T0, T1, T2>>::sli(self, operand_1, rn, shift);
19219    }
19220    /// Emits the `SMAXP` instruction.
19221    /// Assembly forms: `SMAXP VD.T, VN.T, VM.T`; `SMAXP VD.T, VN.T, VM.T`.
19222    /// Operands: `rd`, `rn`, `rm`.
19223    pub fn smaxp<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
19224    where
19225        Self: SmaxpEmitter<T0, T1, T2>,
19226    {
19227        <Self as SmaxpEmitter<T0, T1, T2>>::smaxp(self, rd, rn, rm);
19228    }
19229    /// Emits the `SMAXV` instruction.
19230    /// Assembly forms: `SMAXV BD, VN.8B`; `SMAXV BD, VN.16B`; `SMAXV HD, VN.4H`; `SMAXV HD, VN.8H` (and related forms).
19231    /// Operands: `rd`, `rn`.
19232    pub fn smaxv<T0, T1>(&mut self, rd: T0, rn: T1)
19233    where
19234        Self: SmaxvEmitter<T0, T1>,
19235    {
19236        <Self as SmaxvEmitter<T0, T1>>::smaxv(self, rd, rn);
19237    }
19238    /// Emits the `SMINP` instruction.
19239    /// Assembly forms: `SMINP VD.T, VN.T, VM.T`; `SMINP VD.T, VN.T, VM.T`.
19240    /// Operands: `rd`, `rn`, `rm`.
19241    pub fn sminp<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
19242    where
19243        Self: SminpEmitter<T0, T1, T2>,
19244    {
19245        <Self as SminpEmitter<T0, T1, T2>>::sminp(self, rd, rn, rm);
19246    }
19247    /// Emits the `SMINV` instruction.
19248    /// Assembly forms: `SMINV BD, VN.8B`; `SMINV BD, VN.16B`; `SMINV HD, VN.4H`; `SMINV HD, VN.8H` (and related forms).
19249    /// Operands: `rd`, `rn`.
19250    pub fn sminv<T0, T1>(&mut self, rd: T0, rn: T1)
19251    where
19252        Self: SminvEmitter<T0, T1>,
19253    {
19254        <Self as SminvEmitter<T0, T1>>::sminv(self, rd, rn);
19255    }
19256    /// Emits the `SMLAL` instruction.
19257    /// Assembly forms: `SMLAL VX.TA, VN.TB, VM.TB`; `SMLAL VX.4S, VN.4H, VM.H[#IDX]`; `SMLAL VX.2D, VN.2S, VM.S[#IDX]`.
19258    /// Operands: `operand_1`, `rn`, `rm`.
19259    pub fn smlal<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)
19260    where
19261        Self: SmlalEmitter<T0, T1, T2>,
19262    {
19263        <Self as SmlalEmitter<T0, T1, T2>>::smlal(self, operand_1, rn, rm);
19264    }
19265    /// Emits the `SMLAL2` instruction.
19266    /// Assembly forms: `SMLAL2 VX.TA, VN.TB, VM.TB`; `SMLAL2 VX.4S, VN.8H, VM.H[#IDX]`; `SMLAL2 VX.2D, VN.4S, VM.S[#IDX]`.
19267    /// Operands: `operand_1`, `rn`, `rm`.
19268    pub fn smlal2<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)
19269    where
19270        Self: Smlal2Emitter<T0, T1, T2>,
19271    {
19272        <Self as Smlal2Emitter<T0, T1, T2>>::smlal2(self, operand_1, rn, rm);
19273    }
19274    /// Emits the `SMLSL` instruction.
19275    /// Assembly forms: `SMLSL VX.TA, VN.TB, VM.TB`; `SMLSL VX.4S, VN.4H, VM.H[#IDX]`; `SMLSL VX.2D, VN.2S, VM.S[#IDX]`.
19276    /// Operands: `operand_1`, `rn`, `rm`.
19277    pub fn smlsl<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)
19278    where
19279        Self: SmlslEmitter<T0, T1, T2>,
19280    {
19281        <Self as SmlslEmitter<T0, T1, T2>>::smlsl(self, operand_1, rn, rm);
19282    }
19283    /// Emits the `SMLSL2` instruction.
19284    /// Assembly forms: `SMLSL2 VX.TA, VN.TB, VM.TB`; `SMLSL2 VX.4S, VN.8H, VM.H[#IDX]`; `SMLSL2 VX.2D, VN.4S, VM.S[#IDX]`.
19285    /// Operands: `operand_1`, `rn`, `rm`.
19286    pub fn smlsl2<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)
19287    where
19288        Self: Smlsl2Emitter<T0, T1, T2>,
19289    {
19290        <Self as Smlsl2Emitter<T0, T1, T2>>::smlsl2(self, operand_1, rn, rm);
19291    }
19292    /// Emits the `SMOV` instruction.
19293    /// Assembly forms: `SMOV WD, VN.B[#IDX]`; `SMOV WD, VN.H[#IDX]`; `SMOV XD, VN.B[#IDX]`; `SMOV XD, VN.H[#IDX]` (and related forms).
19294    /// Operands: `rd`, `rn`.
19295    pub fn smov<T0, T1>(&mut self, rd: T0, rn: T1)
19296    where
19297        Self: SmovEmitter<T0, T1>,
19298    {
19299        <Self as SmovEmitter<T0, T1>>::smov(self, rd, rn);
19300    }
19301    /// Emits the `SMULL2` instruction.
19302    /// Assembly forms: `SMULL2 VD.TA, VN.TB, VM.TB`; `SMULL2 VD.4S, VN.8H, VM.H[#IDX]`; `SMULL2 VD.2D, VN.4S, VM.S[#IDX]`.
19303    /// Operands: `rd`, `rn`, `rm`.
19304    pub fn smull2<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
19305    where
19306        Self: Smull2Emitter<T0, T1, T2>,
19307    {
19308        <Self as Smull2Emitter<T0, T1, T2>>::smull2(self, rd, rn, rm);
19309    }
19310    /// Emits the `SQABS` instruction.
19311    /// Assembly forms: `SQABS BD, BN`; `SQABS HD, HN`; `SQABS SD, SN`; `SQABS DD, DN` (and related forms).
19312    /// Operands: `rd`, `rn`.
19313    pub fn sqabs<T0, T1>(&mut self, rd: T0, rn: T1)
19314    where
19315        Self: SqabsEmitter<T0, T1>,
19316    {
19317        <Self as SqabsEmitter<T0, T1>>::sqabs(self, rd, rn);
19318    }
19319    /// Emits the `SQADD` instruction.
19320    /// Assembly forms: `SQADD BD, BN, BM`; `SQADD HD, HN, HM`; `SQADD SD, SN, SM`; `SQADD DD, DN, DM` (and related forms).
19321    /// Operands: `rd`, `rn`, `rm`.
19322    pub fn sqadd<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
19323    where
19324        Self: SqaddEmitter<T0, T1, T2>,
19325    {
19326        <Self as SqaddEmitter<T0, T1, T2>>::sqadd(self, rd, rn, rm);
19327    }
19328    /// Emits the `SQDMLAL` instruction.
19329    /// Assembly forms: `SQDMLAL SX, HN, HM`; `SQDMLAL DX, SN, SM`; `SQDMLAL SX, HN, VM.H[#IDX]`; `SQDMLAL DX, SN, VM.S[#IDX]` (and related forms).
19330    /// Operands: `operand_1`, `rn`, `rm`.
19331    pub fn sqdmlal<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)
19332    where
19333        Self: SqdmlalEmitter<T0, T1, T2>,
19334    {
19335        <Self as SqdmlalEmitter<T0, T1, T2>>::sqdmlal(self, operand_1, rn, rm);
19336    }
19337    /// Emits the `SQDMLAL2` instruction.
19338    /// Assembly forms: `SQDMLAL2 VX.TA, VN.TB, VM.TB`; `SQDMLAL2 VX.4S, VN.8H, VM.H[#IDX]`; `SQDMLAL2 VX.2D, VN.4S, VM.S[#IDX]`.
19339    /// Operands: `operand_1`, `rn`, `rm`.
19340    pub fn sqdmlal2<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)
19341    where
19342        Self: Sqdmlal2Emitter<T0, T1, T2>,
19343    {
19344        <Self as Sqdmlal2Emitter<T0, T1, T2>>::sqdmlal2(self, operand_1, rn, rm);
19345    }
19346    /// Emits the `SQDMLSL` instruction.
19347    /// Assembly forms: `SQDMLSL SX, HN, HM`; `SQDMLSL DX, SN, SM`; `SQDMLSL SX, HN, VM.H[#IDX]`; `SQDMLSL DX, SN, VM.S[#IDX]` (and related forms).
19348    /// Operands: `operand_1`, `rn`, `rm`.
19349    pub fn sqdmlsl<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)
19350    where
19351        Self: SqdmlslEmitter<T0, T1, T2>,
19352    {
19353        <Self as SqdmlslEmitter<T0, T1, T2>>::sqdmlsl(self, operand_1, rn, rm);
19354    }
19355    /// Emits the `SQDMLSL2` instruction.
19356    /// Assembly forms: `SQDMLSL2 VX.TA, VN.TB, VM.TB`; `SQDMLSL2 VX.4S, VN.8H, VM.H[#IDX]`; `SQDMLSL2 VX.2D, VN.4S, VM.S[#IDX]`.
19357    /// Operands: `operand_1`, `rn`, `rm`.
19358    pub fn sqdmlsl2<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)
19359    where
19360        Self: Sqdmlsl2Emitter<T0, T1, T2>,
19361    {
19362        <Self as Sqdmlsl2Emitter<T0, T1, T2>>::sqdmlsl2(self, operand_1, rn, rm);
19363    }
19364    /// Emits the `SQDMULH` instruction.
19365    /// Assembly forms: `SQDMULH HD, HN, HM`; `SQDMULH SD, SN, SM`; `SQDMULH HD, HN, VM.H[#IDX]`; `SQDMULH SD, SN, VM.S[#IDX]` (and related forms).
19366    /// Operands: `rd`, `rn`, `rm`.
19367    pub fn sqdmulh<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
19368    where
19369        Self: SqdmulhEmitter<T0, T1, T2>,
19370    {
19371        <Self as SqdmulhEmitter<T0, T1, T2>>::sqdmulh(self, rd, rn, rm);
19372    }
19373    /// Emits the `SQDMULL` instruction.
19374    /// Assembly forms: `SQDMULL SD, HN, HM`; `SQDMULL DD, SN, SM`; `SQDMULL SD, HN, VM.H[#IDX]`; `SQDMULL DD, SN, VM.S[#IDX]` (and related forms).
19375    /// Operands: `rd`, `rn`, `rm`.
19376    pub fn sqdmull<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
19377    where
19378        Self: SqdmullEmitter<T0, T1, T2>,
19379    {
19380        <Self as SqdmullEmitter<T0, T1, T2>>::sqdmull(self, rd, rn, rm);
19381    }
19382    /// Emits the `SQDMULL2` instruction.
19383    /// Assembly forms: `SQDMULL2 VD.TA, VN.TB, VM.TB`; `SQDMULL2 VD.4S, VN.8H, VM.H[#IDX]`; `SQDMULL2 VD.2D, VN.4S, VM.S[#IDX]`.
19384    /// Operands: `rd`, `rn`, `rm`.
19385    pub fn sqdmull2<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
19386    where
19387        Self: Sqdmull2Emitter<T0, T1, T2>,
19388    {
19389        <Self as Sqdmull2Emitter<T0, T1, T2>>::sqdmull2(self, rd, rn, rm);
19390    }
19391    /// Emits the `SQNEG` instruction.
19392    /// Assembly forms: `SQNEG BD, BN`; `SQNEG HD, HN`; `SQNEG SD, SN`; `SQNEG DD, DN` (and related forms).
19393    /// Operands: `rd`, `rn`.
19394    pub fn sqneg<T0, T1>(&mut self, rd: T0, rn: T1)
19395    where
19396        Self: SqnegEmitter<T0, T1>,
19397    {
19398        <Self as SqnegEmitter<T0, T1>>::sqneg(self, rd, rn);
19399    }
19400    /// Emits the `SQRDMULH` instruction.
19401    /// Assembly forms: `SQRDMULH HD, HN, HM`; `SQRDMULH SD, SN, SM`; `SQRDMULH HD, HN, VM.H[#IDX]`; `SQRDMULH SD, SN, VM.S[#IDX]` (and related forms).
19402    /// Operands: `rd`, `rn`, `rm`.
19403    pub fn sqrdmulh<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
19404    where
19405        Self: SqrdmulhEmitter<T0, T1, T2>,
19406    {
19407        <Self as SqrdmulhEmitter<T0, T1, T2>>::sqrdmulh(self, rd, rn, rm);
19408    }
19409    /// Emits the `SQRSHL` instruction.
19410    /// Assembly forms: `SQRSHL BD, BN, BM`; `SQRSHL HD, HN, HM`; `SQRSHL SD, SN, SM`; `SQRSHL DD, DN, DM` (and related forms).
19411    /// Operands: `rd`, `rn`, `rm`.
19412    pub fn sqrshl<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
19413    where
19414        Self: SqrshlEmitter<T0, T1, T2>,
19415    {
19416        <Self as SqrshlEmitter<T0, T1, T2>>::sqrshl(self, rd, rn, rm);
19417    }
19418    /// Emits the `SQRSHRN` instruction.
19419    /// Assembly forms: `SQRSHRN BD, HN, #N`; `SQRSHRN HD, SN, #N`; `SQRSHRN SD, DN, #N`; `SQRSHRN VD.8B, VN.8H, #N` (and related forms).
19420    /// Operands: `rd`, `rn`, `shift`.
19421    pub fn sqrshrn<T0, T1, T2>(&mut self, rd: T0, rn: T1, shift: T2)
19422    where
19423        Self: SqrshrnEmitter<T0, T1, T2>,
19424    {
19425        <Self as SqrshrnEmitter<T0, T1, T2>>::sqrshrn(self, rd, rn, shift);
19426    }
19427    /// Emits the `SQRSHRN2` instruction.
19428    /// Assembly forms: `SQRSHRN2 VX.16B, VN.8H, #N`; `SQRSHRN2 VX.8H, VN.4S, #N`; `SQRSHRN2 VX.4S, VN.2D, #N`.
19429    /// Operands: `operand_1`, `rn`, `shift`.
19430    pub fn sqrshrn2<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, shift: T2)
19431    where
19432        Self: Sqrshrn2Emitter<T0, T1, T2>,
19433    {
19434        <Self as Sqrshrn2Emitter<T0, T1, T2>>::sqrshrn2(self, operand_1, rn, shift);
19435    }
19436    /// Emits the `SQRSHRUN` instruction.
19437    /// Assembly forms: `SQRSHRUN BD, HN, #N`; `SQRSHRUN HD, SN, #N`; `SQRSHRUN SD, DN, #N`; `SQRSHRUN VD.8B, VN.8H, #N` (and related forms).
19438    /// Operands: `rd`, `rn`, `shift`.
19439    pub fn sqrshrun<T0, T1, T2>(&mut self, rd: T0, rn: T1, shift: T2)
19440    where
19441        Self: SqrshrunEmitter<T0, T1, T2>,
19442    {
19443        <Self as SqrshrunEmitter<T0, T1, T2>>::sqrshrun(self, rd, rn, shift);
19444    }
19445    /// Emits the `SQRSHRUN2` instruction.
19446    /// Assembly forms: `SQRSHRUN2 VX.16B, VN.8H, #N`; `SQRSHRUN2 VX.8H, VN.4S, #N`; `SQRSHRUN2 VX.4S, VN.2D, #N`.
19447    /// Operands: `operand_1`, `rn`, `shift`.
19448    pub fn sqrshrun2<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, shift: T2)
19449    where
19450        Self: Sqrshrun2Emitter<T0, T1, T2>,
19451    {
19452        <Self as Sqrshrun2Emitter<T0, T1, T2>>::sqrshrun2(self, operand_1, rn, shift);
19453    }
19454    /// Emits the `SQSHL` instruction.
19455    /// Assembly forms: `SQSHL BD, BN, BM`; `SQSHL HD, HN, HM`; `SQSHL SD, SN, SM`; `SQSHL DD, DN, DM` (and related forms).
19456    /// Operands: `rd`, `rn`, `rm_or_shift`.
19457    pub fn sqshl<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm_or_shift: T2)
19458    where
19459        Self: SqshlEmitter<T0, T1, T2>,
19460    {
19461        <Self as SqshlEmitter<T0, T1, T2>>::sqshl(self, rd, rn, rm_or_shift);
19462    }
19463    /// Emits the `SQSHLU` instruction.
19464    /// Assembly forms: `SQSHLU BD, BN, #N`; `SQSHLU HD, HN, #N`; `SQSHLU SD, SN, #N`; `SQSHLU DD, DN, #N` (and related forms).
19465    /// Operands: `rd`, `rn`, `shift`.
19466    pub fn sqshlu<T0, T1, T2>(&mut self, rd: T0, rn: T1, shift: T2)
19467    where
19468        Self: SqshluEmitter<T0, T1, T2>,
19469    {
19470        <Self as SqshluEmitter<T0, T1, T2>>::sqshlu(self, rd, rn, shift);
19471    }
19472    /// Emits the `SQSHRN` instruction.
19473    /// Assembly forms: `SQSHRN BD, HN, #N`; `SQSHRN HD, SN, #N`; `SQSHRN SD, DN, #N`; `SQSHRN VD.TA, VN.TB, #N`.
19474    /// Operands: `rd`, `rn`, `shift`.
19475    pub fn sqshrn<T0, T1, T2>(&mut self, rd: T0, rn: T1, shift: T2)
19476    where
19477        Self: SqshrnEmitter<T0, T1, T2>,
19478    {
19479        <Self as SqshrnEmitter<T0, T1, T2>>::sqshrn(self, rd, rn, shift);
19480    }
19481    /// Emits the `SQSHRN2` instruction.
19482    /// Assembly forms: `SQSHRN2 VX.TA, VN.TB, #N`.
19483    /// Operands: `operand_1`, `rn`, `shift`.
19484    pub fn sqshrn2<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, shift: T2)
19485    where
19486        Self: Sqshrn2Emitter<T0, T1, T2>,
19487    {
19488        <Self as Sqshrn2Emitter<T0, T1, T2>>::sqshrn2(self, operand_1, rn, shift);
19489    }
19490    /// Emits the `SQSHRUN` instruction.
19491    /// Assembly forms: `SQSHRUN BD, HN, #N`; `SQSHRUN HD, SN, #N`; `SQSHRUN SD, DN, #N`; `SQSHRUN VD.8B, VN.8H, #N` (and related forms).
19492    /// Operands: `rd`, `rn`, `shift`.
19493    pub fn sqshrun<T0, T1, T2>(&mut self, rd: T0, rn: T1, shift: T2)
19494    where
19495        Self: SqshrunEmitter<T0, T1, T2>,
19496    {
19497        <Self as SqshrunEmitter<T0, T1, T2>>::sqshrun(self, rd, rn, shift);
19498    }
19499    /// Emits the `SQSHRUN2` instruction.
19500    /// Assembly forms: `SQSHRUN2 VX.16B, VN.8H, #N`; `SQSHRUN2 VX.8H, VN.4S, #N`; `SQSHRUN2 VX.4S, VN.2D, #N`.
19501    /// Operands: `operand_1`, `rn`, `shift`.
19502    pub fn sqshrun2<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, shift: T2)
19503    where
19504        Self: Sqshrun2Emitter<T0, T1, T2>,
19505    {
19506        <Self as Sqshrun2Emitter<T0, T1, T2>>::sqshrun2(self, operand_1, rn, shift);
19507    }
19508    /// Emits the `SQSUB` instruction.
19509    /// Assembly forms: `SQSUB BD, BN, BM`; `SQSUB HD, HN, HM`; `SQSUB SD, SN, SM`; `SQSUB DD, DN, DM` (and related forms).
19510    /// Operands: `rd`, `rn`, `rm`.
19511    pub fn sqsub<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
19512    where
19513        Self: SqsubEmitter<T0, T1, T2>,
19514    {
19515        <Self as SqsubEmitter<T0, T1, T2>>::sqsub(self, rd, rn, rm);
19516    }
19517    /// Emits the `SQXTN` instruction.
19518    /// Assembly forms: `SQXTN BD, HN`; `SQXTN HD, SN`; `SQXTN SD, DN`; `SQXTN VD.TA, VN.TB`.
19519    /// Operands: `rd`, `rn`.
19520    pub fn sqxtn<T0, T1>(&mut self, rd: T0, rn: T1)
19521    where
19522        Self: SqxtnEmitter<T0, T1>,
19523    {
19524        <Self as SqxtnEmitter<T0, T1>>::sqxtn(self, rd, rn);
19525    }
19526    /// Emits the `SQXTN2` instruction.
19527    /// Assembly forms: `SQXTN2 VX.TA, VN.TB`.
19528    /// Operands: `operand_1`, `rn`.
19529    pub fn sqxtn2<T0, T1>(&mut self, operand_1: T0, rn: T1)
19530    where
19531        Self: Sqxtn2Emitter<T0, T1>,
19532    {
19533        <Self as Sqxtn2Emitter<T0, T1>>::sqxtn2(self, operand_1, rn);
19534    }
19535    /// Emits the `SQXTUN` instruction.
19536    /// Assembly forms: `SQXTUN BD, HN`; `SQXTUN HD, SN`; `SQXTUN SD, DN`; `SQXTUN VD.TA, VN.TB`.
19537    /// Operands: `rd`, `rn`.
19538    pub fn sqxtun<T0, T1>(&mut self, rd: T0, rn: T1)
19539    where
19540        Self: SqxtunEmitter<T0, T1>,
19541    {
19542        <Self as SqxtunEmitter<T0, T1>>::sqxtun(self, rd, rn);
19543    }
19544    /// Emits the `SQXTUN2` instruction.
19545    /// Assembly forms: `SQXTUN2 VX.TA, VN.TB`.
19546    /// Operands: `operand_1`, `rn`.
19547    pub fn sqxtun2<T0, T1>(&mut self, operand_1: T0, rn: T1)
19548    where
19549        Self: Sqxtun2Emitter<T0, T1>,
19550    {
19551        <Self as Sqxtun2Emitter<T0, T1>>::sqxtun2(self, operand_1, rn);
19552    }
19553    /// Emits the `SRHADD` instruction.
19554    /// Assembly forms: `SRHADD VD.T, VN.T, VM.T`; `SRHADD VD.T, VN.T, VM.T`.
19555    /// Operands: `rd`, `rn`, `rm`.
19556    pub fn srhadd<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
19557    where
19558        Self: SrhaddEmitter<T0, T1, T2>,
19559    {
19560        <Self as SrhaddEmitter<T0, T1, T2>>::srhadd(self, rd, rn, rm);
19561    }
19562    /// Emits the `SRI` instruction.
19563    /// Assembly forms: `SRI DX, DN, #N`; `SRI VX.T, VN.T, #N`; `SRI VX.T, VN.T, #N`.
19564    /// Operands: `operand_1`, `rn`, `shift`.
19565    pub fn sri<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, shift: T2)
19566    where
19567        Self: SriEmitter<T0, T1, T2>,
19568    {
19569        <Self as SriEmitter<T0, T1, T2>>::sri(self, operand_1, rn, shift);
19570    }
19571    /// Emits the `SRSHL` instruction.
19572    /// Assembly forms: `SRSHL DD, DN, DM`; `SRSHL VD.T, VN.T, VM.T`; `SRSHL VD.T, VN.T, VM.T`.
19573    /// Operands: `rd`, `rn`, `rm`.
19574    pub fn srshl<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
19575    where
19576        Self: SrshlEmitter<T0, T1, T2>,
19577    {
19578        <Self as SrshlEmitter<T0, T1, T2>>::srshl(self, rd, rn, rm);
19579    }
19580    /// Emits the `SRSHR` instruction.
19581    /// Assembly forms: `SRSHR DD, DN, #N`; `SRSHR VD.T, VN.T, #N`; `SRSHR VD.T, VN.T, #N`.
19582    /// Operands: `rd`, `rn`, `shift`.
19583    pub fn srshr<T0, T1, T2>(&mut self, rd: T0, rn: T1, shift: T2)
19584    where
19585        Self: SrshrEmitter<T0, T1, T2>,
19586    {
19587        <Self as SrshrEmitter<T0, T1, T2>>::srshr(self, rd, rn, shift);
19588    }
19589    /// Emits the `SRSRA` instruction.
19590    /// Assembly forms: `SRSRA DX, DN, #N`; `SRSRA VX.T, VN.T, #N`; `SRSRA VX.T, VN.T, #N`.
19591    /// Operands: `operand_1`, `rn`, `shift`.
19592    pub fn srsra<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, shift: T2)
19593    where
19594        Self: SrsraEmitter<T0, T1, T2>,
19595    {
19596        <Self as SrsraEmitter<T0, T1, T2>>::srsra(self, operand_1, rn, shift);
19597    }
19598    /// Emits the `SSHL` instruction.
19599    /// Assembly forms: `SSHL DD, DN, DM`; `SSHL VD.T, VN.T, VM.T`; `SSHL VD.T, VN.T, VM.T`.
19600    /// Operands: `rd`, `rn`, `rm`.
19601    pub fn sshl<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
19602    where
19603        Self: SshlEmitter<T0, T1, T2>,
19604    {
19605        <Self as SshlEmitter<T0, T1, T2>>::sshl(self, rd, rn, rm);
19606    }
19607    /// Emits the `SSHLL` instruction.
19608    /// Assembly forms: `SSHLL VD.TA, VN.TB, #N`.
19609    /// Operands: `rd`, `rn`, `shift`.
19610    pub fn sshll<T0, T1, T2>(&mut self, rd: T0, rn: T1, shift: T2)
19611    where
19612        Self: SshllEmitter<T0, T1, T2>,
19613    {
19614        <Self as SshllEmitter<T0, T1, T2>>::sshll(self, rd, rn, shift);
19615    }
19616    /// Emits the `SSHLL2` instruction.
19617    /// Assembly forms: `SSHLL2 VD.TA, VN.TB, #N`.
19618    /// Operands: `rd`, `rn`, `shift`.
19619    pub fn sshll2<T0, T1, T2>(&mut self, rd: T0, rn: T1, shift: T2)
19620    where
19621        Self: Sshll2Emitter<T0, T1, T2>,
19622    {
19623        <Self as Sshll2Emitter<T0, T1, T2>>::sshll2(self, rd, rn, shift);
19624    }
19625    /// Emits the `SSHR` instruction.
19626    /// Assembly forms: `SSHR DD, DN, #N`; `SSHR VD.T, VN.T, #N`; `SSHR VD.T, VN.T, #N`.
19627    /// Operands: `rd`, `rn`, `shift`.
19628    pub fn sshr<T0, T1, T2>(&mut self, rd: T0, rn: T1, shift: T2)
19629    where
19630        Self: SshrEmitter<T0, T1, T2>,
19631    {
19632        <Self as SshrEmitter<T0, T1, T2>>::sshr(self, rd, rn, shift);
19633    }
19634    /// Emits the `SSRA` instruction.
19635    /// Assembly forms: `SSRA DX, DN, #N`; `SSRA VX.T, VN.T, #N`; `SSRA VX.T, VN.T, #N`.
19636    /// Operands: `operand_1`, `rn`, `shift`.
19637    pub fn ssra<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, shift: T2)
19638    where
19639        Self: SsraEmitter<T0, T1, T2>,
19640    {
19641        <Self as SsraEmitter<T0, T1, T2>>::ssra(self, operand_1, rn, shift);
19642    }
19643    /// Emits the `SSUBL` instruction.
19644    /// Assembly forms: `SSUBL VD.TA, VN.TB, VM.TB`.
19645    /// Operands: `rd`, `rn`, `rm`.
19646    pub fn ssubl<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
19647    where
19648        Self: SsublEmitter<T0, T1, T2>,
19649    {
19650        <Self as SsublEmitter<T0, T1, T2>>::ssubl(self, rd, rn, rm);
19651    }
19652    /// Emits the `SSUBL2` instruction.
19653    /// Assembly forms: `SSUBL2 VD.TA, VN.TB, VM.TB`.
19654    /// Operands: `rd`, `rn`, `rm`.
19655    pub fn ssubl2<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
19656    where
19657        Self: Ssubl2Emitter<T0, T1, T2>,
19658    {
19659        <Self as Ssubl2Emitter<T0, T1, T2>>::ssubl2(self, rd, rn, rm);
19660    }
19661    /// Emits the `SSUBW` instruction.
19662    /// Assembly forms: `SSUBW VD.TA, VN.TA, VM.TB`.
19663    /// Operands: `rd`, `rn`, `rm`.
19664    pub fn ssubw<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
19665    where
19666        Self: SsubwEmitter<T0, T1, T2>,
19667    {
19668        <Self as SsubwEmitter<T0, T1, T2>>::ssubw(self, rd, rn, rm);
19669    }
19670    /// Emits the `SSUBW2` instruction.
19671    /// Assembly forms: `SSUBW2 VD.TA, VN.TA, VM.TB`.
19672    /// Operands: `rd`, `rn`, `rm`.
19673    pub fn ssubw2<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
19674    where
19675        Self: Ssubw2Emitter<T0, T1, T2>,
19676    {
19677        <Self as Ssubw2Emitter<T0, T1, T2>>::ssubw2(self, rd, rn, rm);
19678    }
19679    /// Emits the `ST1` instruction.
19680    /// Assembly forms: `ST1 VS.B[#IDX], [XN|SP]`; `ST1 VS.H[#IDX], [XN|SP]`; `ST1 VS.S[#IDX], [XN|SP]`; `ST1 VS.D[#IDX], [XN|SP]` (and related forms).
19681    /// Operands: `rs_or_operand_1`, `addr`.
19682    pub fn st1<T0, T1>(&mut self, rs_or_operand_1: T0, addr: T1)
19683    where
19684        Self: St1Emitter<T0, T1>,
19685    {
19686        <Self as St1Emitter<T0, T1>>::st1(self, rs_or_operand_1, addr);
19687    }
19688    /// Emits the `ST1_3` instruction.
19689    /// Assembly forms: `ST1 VS.B[#IDX], [XN|SP]`; `ST1 VS.H[#IDX], [XN|SP]`; `ST1 VS.S[#IDX], [XN|SP]`; `ST1 VS.D[#IDX], [XN|SP]` (and related forms).
19690    /// Operands: `rd`, `rn`, `addr`.
19691    pub fn st1_3<T0, T1, T2>(&mut self, rd: T0, rn: T1, addr: T2)
19692    where
19693        Self: St13Emitter<T0, T1, T2>,
19694    {
19695        <Self as St13Emitter<T0, T1, T2>>::st1_3(self, rd, rn, addr);
19696    }
19697    /// Emits the `ST1_4` instruction.
19698    /// Assembly forms: `ST1 VS.B[#IDX], [XN|SP]`; `ST1 VS.H[#IDX], [XN|SP]`; `ST1 VS.S[#IDX], [XN|SP]`; `ST1 VS.D[#IDX], [XN|SP]` (and related forms).
19699    /// Operands: `rd`, `rn`, `rm1`, `addr`.
19700    pub fn st1_4<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm1: T2, addr: T3)
19701    where
19702        Self: St14Emitter<T0, T1, T2, T3>,
19703    {
19704        <Self as St14Emitter<T0, T1, T2, T3>>::st1_4(self, rd, rn, rm1, addr);
19705    }
19706    /// Emits the `ST1_5` instruction.
19707    /// Assembly forms: `ST1 VS.B[#IDX], [XN|SP]`; `ST1 VS.H[#IDX], [XN|SP]`; `ST1 VS.S[#IDX], [XN|SP]`; `ST1 VS.D[#IDX], [XN|SP]` (and related forms).
19708    /// Operands: `rd`, `rn`, `rm1`, `rm2`, `addr`.
19709    pub fn st1_5<T0, T1, T2, T3, T4>(&mut self, rd: T0, rn: T1, rm1: T2, rm2: T3, addr: T4)
19710    where
19711        Self: St15Emitter<T0, T1, T2, T3, T4>,
19712    {
19713        <Self as St15Emitter<T0, T1, T2, T3, T4>>::st1_5(self, rd, rn, rm1, rm2, addr);
19714    }
19715    /// Emits the `ST2` instruction.
19716    /// Assembly forms: `ST2 2X{VS.B}+[#IDX], [XN|SP]`; `ST2 2X{VS.H}+[#IDX], [XN|SP]`; `ST2 2X{VS.S}+[#IDX], [XN|SP]`; `ST2 2X{VS.D}+[#IDX], [XN|SP]` (and related forms).
19717    /// Operands: `rd`, `rn`, `addr`.
19718    pub fn st2<T0, T1, T2>(&mut self, rd: T0, rn: T1, addr: T2)
19719    where
19720        Self: St2Emitter<T0, T1, T2>,
19721    {
19722        <Self as St2Emitter<T0, T1, T2>>::st2(self, rd, rn, addr);
19723    }
19724    /// Emits the `ST3` instruction.
19725    /// Assembly forms: `ST3 3X{VS.B}+[#IDX], [XN|SP]`; `ST3 3X{VS.H}+[#IDX], [XN|SP]`; `ST3 3X{VS.S}+[#IDX], [XN|SP]`; `ST3 3X{VS.D}+[#IDX], [XN|SP]` (and related forms).
19726    /// Operands: `rd`, `rn`, `rm1`, `addr`.
19727    pub fn st3<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm1: T2, addr: T3)
19728    where
19729        Self: St3Emitter<T0, T1, T2, T3>,
19730    {
19731        <Self as St3Emitter<T0, T1, T2, T3>>::st3(self, rd, rn, rm1, addr);
19732    }
19733    /// Emits the `ST4` instruction.
19734    /// Assembly forms: `ST4 4X{VS.B}+[#IDX], [XN|SP]`; `ST4 4X{VS.H}+[#IDX], [XN|SP]`; `ST4 4X{VS.S}+[#IDX], [XN|SP]`; `ST4 4X{VS.D}+[#IDX], [XN|SP]` (and related forms).
19735    /// Operands: `rd`, `rn`, `rm1`, `rm2`, `addr`.
19736    pub fn st4<T0, T1, T2, T3, T4>(&mut self, rd: T0, rn: T1, rm1: T2, rm2: T3, addr: T4)
19737    where
19738        Self: St4Emitter<T0, T1, T2, T3, T4>,
19739    {
19740        <Self as St4Emitter<T0, T1, T2, T3, T4>>::st4(self, rd, rn, rm1, rm2, addr);
19741    }
19742    /// Emits the `SUBHN` instruction.
19743    /// Assembly forms: `SUBHN VD.TA, VN.TB, VM.TB`.
19744    /// Operands: `rd`, `rn`, `rm`.
19745    pub fn subhn<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
19746    where
19747        Self: SubhnEmitter<T0, T1, T2>,
19748    {
19749        <Self as SubhnEmitter<T0, T1, T2>>::subhn(self, rd, rn, rm);
19750    }
19751    /// Emits the `SUBHN2` instruction.
19752    /// Assembly forms: `SUBHN2 VX.TA, VN.TB, VM.TB`.
19753    /// Operands: `operand_1`, `rn`, `rm`.
19754    pub fn subhn2<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)
19755    where
19756        Self: Subhn2Emitter<T0, T1, T2>,
19757    {
19758        <Self as Subhn2Emitter<T0, T1, T2>>::subhn2(self, operand_1, rn, rm);
19759    }
19760    /// Emits the `SUQADD` instruction.
19761    /// Assembly forms: `SUQADD BX, BN`; `SUQADD HX, HN`; `SUQADD SX, SN`; `SUQADD DX, DN` (and related forms).
19762    /// Operands: `operand_1`, `rn`.
19763    pub fn suqadd<T0, T1>(&mut self, operand_1: T0, rn: T1)
19764    where
19765        Self: SuqaddEmitter<T0, T1>,
19766    {
19767        <Self as SuqaddEmitter<T0, T1>>::suqadd(self, operand_1, rn);
19768    }
19769    /// Emits the `SXTL` instruction.
19770    /// Assembly forms: `SXTL VD.TA, VN.TB`.
19771    /// Operands: `rd`, `rn`.
19772    pub fn sxtl<T0, T1>(&mut self, rd: T0, rn: T1)
19773    where
19774        Self: SxtlEmitter<T0, T1>,
19775    {
19776        <Self as SxtlEmitter<T0, T1>>::sxtl(self, rd, rn);
19777    }
19778    /// Emits the `SXTL2` instruction.
19779    /// Assembly forms: `SXTL2 VD.TA, VN.TB`.
19780    /// Operands: `rd`, `rn`.
19781    pub fn sxtl2<T0, T1>(&mut self, rd: T0, rn: T1)
19782    where
19783        Self: Sxtl2Emitter<T0, T1>,
19784    {
19785        <Self as Sxtl2Emitter<T0, T1>>::sxtl2(self, rd, rn);
19786    }
19787    /// Emits the `TBL` instruction.
19788    /// Assembly forms: `TBL VD.8B, VN.16B, VM.8B`; `TBL VD.16B, VN.16B, VM.16B`; `TBL VD.8B, 2X{VN.16B}+, VM.8B`; `TBL VD.16B, 2X{VN.16B}+, VM.16B` (and related forms).
19789    /// Operands: `rd`, `rn_or_operand_2`, `rm`.
19790    pub fn tbl<T0, T1, T2>(&mut self, rd: T0, rn_or_operand_2: T1, rm: T2)
19791    where
19792        Self: TblEmitter<T0, T1, T2>,
19793    {
19794        <Self as TblEmitter<T0, T1, T2>>::tbl(self, rd, rn_or_operand_2, rm);
19795    }
19796    /// Emits the `TBL_4` instruction.
19797    /// Assembly forms: `TBL VD.8B, VN.16B, VM.8B`; `TBL VD.16B, VN.16B, VM.16B`; `TBL VD.8B, 2X{VN.16B}+, VM.8B`; `TBL VD.16B, 2X{VN.16B}+, VM.16B` (and related forms).
19798    /// Operands: `rd`, `rn`, `rm1`, `rm2`.
19799    pub fn tbl_4<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm1: T2, rm2: T3)
19800    where
19801        Self: Tbl4Emitter<T0, T1, T2, T3>,
19802    {
19803        <Self as Tbl4Emitter<T0, T1, T2, T3>>::tbl_4(self, rd, rn, rm1, rm2);
19804    }
19805    /// Emits the `TBL_5` instruction.
19806    /// Assembly forms: `TBL VD.8B, VN.16B, VM.8B`; `TBL VD.16B, VN.16B, VM.16B`; `TBL VD.8B, 2X{VN.16B}+, VM.8B`; `TBL VD.16B, 2X{VN.16B}+, VM.16B` (and related forms).
19807    /// Operands: `rd`, `rn`, `rm1`, `rm2`, `rm3`.
19808    pub fn tbl_5<T0, T1, T2, T3, T4>(&mut self, rd: T0, rn: T1, rm1: T2, rm2: T3, rm3: T4)
19809    where
19810        Self: Tbl5Emitter<T0, T1, T2, T3, T4>,
19811    {
19812        <Self as Tbl5Emitter<T0, T1, T2, T3, T4>>::tbl_5(self, rd, rn, rm1, rm2, rm3);
19813    }
19814    /// Emits the `TBL_6` instruction.
19815    /// Assembly forms: `TBL VD.8B, VN.16B, VM.8B`; `TBL VD.16B, VN.16B, VM.16B`; `TBL VD.8B, 2X{VN.16B}+, VM.8B`; `TBL VD.16B, 2X{VN.16B}+, VM.16B` (and related forms).
19816    /// Operands: `rd`, `rn`, `rm1`, `rm2`, `rm3`, `rm4`.
19817    pub fn tbl_6<T0, T1, T2, T3, T4, T5>(
19818        &mut self,
19819        rd: T0,
19820        rn: T1,
19821        rm1: T2,
19822        rm2: T3,
19823        rm3: T4,
19824        rm4: T5,
19825    ) where
19826        Self: Tbl6Emitter<T0, T1, T2, T3, T4, T5>,
19827    {
19828        <Self as Tbl6Emitter<T0, T1, T2, T3, T4, T5>>::tbl_6(self, rd, rn, rm1, rm2, rm3, rm4);
19829    }
19830    /// Emits the `TBX` instruction.
19831    /// Assembly forms: `TBX VX.8B, VN.16B, VM.8B`; `TBX VX.16B, VN.16B, VM.16B`; `TBX VX.8B, 2X{VN.16B}+, VM.8B`; `TBX VX.16B, 2X{VN.16B}+, VM.16B` (and related forms).
19832    /// Operands: `operand_1`, `rn_or_operand_2`, `rm`.
19833    pub fn tbx<T0, T1, T2>(&mut self, operand_1: T0, rn_or_operand_2: T1, rm: T2)
19834    where
19835        Self: TbxEmitter<T0, T1, T2>,
19836    {
19837        <Self as TbxEmitter<T0, T1, T2>>::tbx(self, operand_1, rn_or_operand_2, rm);
19838    }
19839    /// Emits the `TBX_4` instruction.
19840    /// Assembly forms: `TBX VX.8B, VN.16B, VM.8B`; `TBX VX.16B, VN.16B, VM.16B`; `TBX VX.8B, 2X{VN.16B}+, VM.8B`; `TBX VX.16B, 2X{VN.16B}+, VM.16B` (and related forms).
19841    /// Operands: `rd`, `rn`, `rm1`, `rm2`.
19842    pub fn tbx_4<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm1: T2, rm2: T3)
19843    where
19844        Self: Tbx4Emitter<T0, T1, T2, T3>,
19845    {
19846        <Self as Tbx4Emitter<T0, T1, T2, T3>>::tbx_4(self, rd, rn, rm1, rm2);
19847    }
19848    /// Emits the `TBX_5` instruction.
19849    /// Assembly forms: `TBX VX.8B, VN.16B, VM.8B`; `TBX VX.16B, VN.16B, VM.16B`; `TBX VX.8B, 2X{VN.16B}+, VM.8B`; `TBX VX.16B, 2X{VN.16B}+, VM.16B` (and related forms).
19850    /// Operands: `rd`, `rn`, `rm1`, `rm2`, `rm3`.
19851    pub fn tbx_5<T0, T1, T2, T3, T4>(&mut self, rd: T0, rn: T1, rm1: T2, rm2: T3, rm3: T4)
19852    where
19853        Self: Tbx5Emitter<T0, T1, T2, T3, T4>,
19854    {
19855        <Self as Tbx5Emitter<T0, T1, T2, T3, T4>>::tbx_5(self, rd, rn, rm1, rm2, rm3);
19856    }
19857    /// Emits the `TBX_6` instruction.
19858    /// Assembly forms: `TBX VX.8B, VN.16B, VM.8B`; `TBX VX.16B, VN.16B, VM.16B`; `TBX VX.8B, 2X{VN.16B}+, VM.8B`; `TBX VX.16B, 2X{VN.16B}+, VM.16B` (and related forms).
19859    /// Operands: `rd`, `rn`, `rm1`, `rm2`, `rm3`, `rm4`.
19860    pub fn tbx_6<T0, T1, T2, T3, T4, T5>(
19861        &mut self,
19862        rd: T0,
19863        rn: T1,
19864        rm1: T2,
19865        rm2: T3,
19866        rm3: T4,
19867        rm4: T5,
19868    ) where
19869        Self: Tbx6Emitter<T0, T1, T2, T3, T4, T5>,
19870    {
19871        <Self as Tbx6Emitter<T0, T1, T2, T3, T4, T5>>::tbx_6(self, rd, rn, rm1, rm2, rm3, rm4);
19872    }
19873    /// Emits the `TRN1` instruction.
19874    /// Assembly forms: `TRN1 VD.T, VN.T, VM.T`; `TRN1 VD.T, VN.T, VM.T`.
19875    /// Operands: `rd`, `rn`, `rm`.
19876    pub fn trn1<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
19877    where
19878        Self: Trn1Emitter<T0, T1, T2>,
19879    {
19880        <Self as Trn1Emitter<T0, T1, T2>>::trn1(self, rd, rn, rm);
19881    }
19882    /// Emits the `TRN2` instruction.
19883    /// Assembly forms: `TRN2 VD.T, VN.T, VM.T`; `TRN2 VD.T, VN.T, VM.T`.
19884    /// Operands: `rd`, `rn`, `rm`.
19885    pub fn trn2<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
19886    where
19887        Self: Trn2Emitter<T0, T1, T2>,
19888    {
19889        <Self as Trn2Emitter<T0, T1, T2>>::trn2(self, rd, rn, rm);
19890    }
19891    /// Emits the `UABA` instruction.
19892    /// Assembly forms: `UABA VX.T, VN.T, VM.T`; `UABA VX.T, VN.T, VM.T`.
19893    /// Operands: `operand_1`, `rn`, `rm`.
19894    pub fn uaba<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)
19895    where
19896        Self: UabaEmitter<T0, T1, T2>,
19897    {
19898        <Self as UabaEmitter<T0, T1, T2>>::uaba(self, operand_1, rn, rm);
19899    }
19900    /// Emits the `UABAL` instruction.
19901    /// Assembly forms: `UABAL VX.TA, VN.TB, VM.TB`.
19902    /// Operands: `operand_1`, `rn`, `rm`.
19903    pub fn uabal<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)
19904    where
19905        Self: UabalEmitter<T0, T1, T2>,
19906    {
19907        <Self as UabalEmitter<T0, T1, T2>>::uabal(self, operand_1, rn, rm);
19908    }
19909    /// Emits the `UABAL2` instruction.
19910    /// Assembly forms: `UABAL2 VX.TA, VN.TB, VM.TB`.
19911    /// Operands: `operand_1`, `rn`, `rm`.
19912    pub fn uabal2<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)
19913    where
19914        Self: Uabal2Emitter<T0, T1, T2>,
19915    {
19916        <Self as Uabal2Emitter<T0, T1, T2>>::uabal2(self, operand_1, rn, rm);
19917    }
19918    /// Emits the `UABD` instruction.
19919    /// Assembly forms: `UABD VD.T, VN.T, VM.T`; `UABD VD.T, VN.T, VM.T`.
19920    /// Operands: `rd`, `rn`, `rm`.
19921    pub fn uabd<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
19922    where
19923        Self: UabdEmitter<T0, T1, T2>,
19924    {
19925        <Self as UabdEmitter<T0, T1, T2>>::uabd(self, rd, rn, rm);
19926    }
19927    /// Emits the `UABDL` instruction.
19928    /// Assembly forms: `UABDL VD.TA, VN.TB, VM.TB`.
19929    /// Operands: `rd`, `rn`, `rm`.
19930    pub fn uabdl<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
19931    where
19932        Self: UabdlEmitter<T0, T1, T2>,
19933    {
19934        <Self as UabdlEmitter<T0, T1, T2>>::uabdl(self, rd, rn, rm);
19935    }
19936    /// Emits the `UABDL2` instruction.
19937    /// Assembly forms: `UABDL2 VD.TA, VN.TB, VM.TB`.
19938    /// Operands: `rd`, `rn`, `rm`.
19939    pub fn uabdl2<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
19940    where
19941        Self: Uabdl2Emitter<T0, T1, T2>,
19942    {
19943        <Self as Uabdl2Emitter<T0, T1, T2>>::uabdl2(self, rd, rn, rm);
19944    }
19945    /// Emits the `UADALP` instruction.
19946    /// Assembly forms: `UADALP VX.TA, VN.TB`; `UADALP VX.TA, VN.TB`.
19947    /// Operands: `operand_1`, `rn`.
19948    pub fn uadalp<T0, T1>(&mut self, operand_1: T0, rn: T1)
19949    where
19950        Self: UadalpEmitter<T0, T1>,
19951    {
19952        <Self as UadalpEmitter<T0, T1>>::uadalp(self, operand_1, rn);
19953    }
19954    /// Emits the `UADDL` instruction.
19955    /// Assembly forms: `UADDL VD.TA, VN.TB, VM.TB`.
19956    /// Operands: `rd`, `rn`, `rm`.
19957    pub fn uaddl<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
19958    where
19959        Self: UaddlEmitter<T0, T1, T2>,
19960    {
19961        <Self as UaddlEmitter<T0, T1, T2>>::uaddl(self, rd, rn, rm);
19962    }
19963    /// Emits the `UADDL2` instruction.
19964    /// Assembly forms: `UADDL2 VD.TA, VN.TB, VM.TB`.
19965    /// Operands: `rd`, `rn`, `rm`.
19966    pub fn uaddl2<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
19967    where
19968        Self: Uaddl2Emitter<T0, T1, T2>,
19969    {
19970        <Self as Uaddl2Emitter<T0, T1, T2>>::uaddl2(self, rd, rn, rm);
19971    }
19972    /// Emits the `UADDLP` instruction.
19973    /// Assembly forms: `UADDLP VD.TA, VN.TB`; `UADDLP VD.TA, VN.TB`.
19974    /// Operands: `rd`, `rn`.
19975    pub fn uaddlp<T0, T1>(&mut self, rd: T0, rn: T1)
19976    where
19977        Self: UaddlpEmitter<T0, T1>,
19978    {
19979        <Self as UaddlpEmitter<T0, T1>>::uaddlp(self, rd, rn);
19980    }
19981    /// Emits the `UADDLV` instruction.
19982    /// Assembly forms: `UADDLV HD, VN.8B`; `UADDLV HD, VN.16B`; `UADDLV SD, VN.4H`; `UADDLV SD, VN.8H` (and related forms).
19983    /// Operands: `rd`, `rn`.
19984    pub fn uaddlv<T0, T1>(&mut self, rd: T0, rn: T1)
19985    where
19986        Self: UaddlvEmitter<T0, T1>,
19987    {
19988        <Self as UaddlvEmitter<T0, T1>>::uaddlv(self, rd, rn);
19989    }
19990    /// Emits the `UADDW` instruction.
19991    /// Assembly forms: `UADDW VD.TA, VN.TA, VM.TB`.
19992    /// Operands: `rd`, `rn`, `rm`.
19993    pub fn uaddw<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
19994    where
19995        Self: UaddwEmitter<T0, T1, T2>,
19996    {
19997        <Self as UaddwEmitter<T0, T1, T2>>::uaddw(self, rd, rn, rm);
19998    }
19999    /// Emits the `UADDW2` instruction.
20000    /// Assembly forms: `UADDW2 VD.TA, VN.TA, VM.TB`.
20001    /// Operands: `rd`, `rn`, `rm`.
20002    pub fn uaddw2<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
20003    where
20004        Self: Uaddw2Emitter<T0, T1, T2>,
20005    {
20006        <Self as Uaddw2Emitter<T0, T1, T2>>::uaddw2(self, rd, rn, rm);
20007    }
20008    /// Emits the `UCVTF` instruction.
20009    /// Assembly forms: `UCVTF SD, WN`; `UCVTF SD, WN, #FBITS`; `UCVTF SD, XN`; `UCVTF SD, XN, #FBITS` (and related forms).
20010    /// Operands: `rd`, `rn`.
20011    pub fn ucvtf<T0, T1>(&mut self, rd: T0, rn: T1)
20012    where
20013        Self: UcvtfEmitter<T0, T1>,
20014    {
20015        <Self as UcvtfEmitter<T0, T1>>::ucvtf(self, rd, rn);
20016    }
20017    /// Emits the `UCVTF_3` instruction.
20018    /// Assembly forms: `UCVTF SD, WN`; `UCVTF SD, WN, #FBITS`; `UCVTF SD, XN`; `UCVTF SD, XN, #FBITS` (and related forms).
20019    /// Operands: `rd`, `rn`, `fbits_or_bits`.
20020    pub fn ucvtf_3<T0, T1, T2>(&mut self, rd: T0, rn: T1, fbits_or_bits: T2)
20021    where
20022        Self: Ucvtf3Emitter<T0, T1, T2>,
20023    {
20024        <Self as Ucvtf3Emitter<T0, T1, T2>>::ucvtf_3(self, rd, rn, fbits_or_bits);
20025    }
20026    /// Emits the `UHADD` instruction.
20027    /// Assembly forms: `UHADD VD.T, VN.T, VM.T`; `UHADD VD.T, VN.T, VM.T`.
20028    /// Operands: `rd`, `rn`, `rm`.
20029    pub fn uhadd<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
20030    where
20031        Self: UhaddEmitter<T0, T1, T2>,
20032    {
20033        <Self as UhaddEmitter<T0, T1, T2>>::uhadd(self, rd, rn, rm);
20034    }
20035    /// Emits the `UHSUB` instruction.
20036    /// Assembly forms: `UHSUB VD.T, VN.T, VM.T`; `UHSUB VD.T, VN.T, VM.T`.
20037    /// Operands: `rd`, `rn`, `rm`.
20038    pub fn uhsub<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
20039    where
20040        Self: UhsubEmitter<T0, T1, T2>,
20041    {
20042        <Self as UhsubEmitter<T0, T1, T2>>::uhsub(self, rd, rn, rm);
20043    }
20044    /// Emits the `UMAXP` instruction.
20045    /// Assembly forms: `UMAXP VD.T, VN.T, VM.T`; `UMAXP VD.T, VN.T, VM.T`.
20046    /// Operands: `rd`, `rn`, `rm`.
20047    pub fn umaxp<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
20048    where
20049        Self: UmaxpEmitter<T0, T1, T2>,
20050    {
20051        <Self as UmaxpEmitter<T0, T1, T2>>::umaxp(self, rd, rn, rm);
20052    }
20053    /// Emits the `UMAXV` instruction.
20054    /// Assembly forms: `UMAXV BD, VN.8B`; `UMAXV BD, VN.16B`; `UMAXV HD, VN.4H`; `UMAXV HD, VN.8H` (and related forms).
20055    /// Operands: `rd`, `rn`.
20056    pub fn umaxv<T0, T1>(&mut self, rd: T0, rn: T1)
20057    where
20058        Self: UmaxvEmitter<T0, T1>,
20059    {
20060        <Self as UmaxvEmitter<T0, T1>>::umaxv(self, rd, rn);
20061    }
20062    /// Emits the `UMINP` instruction.
20063    /// Assembly forms: `UMINP VD.T, VN.T, VM.T`; `UMINP VD.T, VN.T, VM.T`.
20064    /// Operands: `rd`, `rn`, `rm`.
20065    pub fn uminp<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
20066    where
20067        Self: UminpEmitter<T0, T1, T2>,
20068    {
20069        <Self as UminpEmitter<T0, T1, T2>>::uminp(self, rd, rn, rm);
20070    }
20071    /// Emits the `UMINV` instruction.
20072    /// Assembly forms: `UMINV BD, VN.8B`; `UMINV BD, VN.16B`; `UMINV HD, VN.4H`; `UMINV HD, VN.8H` (and related forms).
20073    /// Operands: `rd`, `rn`.
20074    pub fn uminv<T0, T1>(&mut self, rd: T0, rn: T1)
20075    where
20076        Self: UminvEmitter<T0, T1>,
20077    {
20078        <Self as UminvEmitter<T0, T1>>::uminv(self, rd, rn);
20079    }
20080    /// Emits the `UMLAL` instruction.
20081    /// Assembly forms: `UMLAL VD.TA, VN.TB, VM.TB`; `UMLAL VD.4S, VN.4H, VM.H[#IDX]`; `UMLAL VD.2D, VN.2S, VM.S[#IDX]`.
20082    /// Operands: `rd`, `rn`, `rm`.
20083    pub fn umlal<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
20084    where
20085        Self: UmlalEmitter<T0, T1, T2>,
20086    {
20087        <Self as UmlalEmitter<T0, T1, T2>>::umlal(self, rd, rn, rm);
20088    }
20089    /// Emits the `UMLAL2` instruction.
20090    /// Assembly forms: `UMLAL2 VD.TA, VN.TB, VM.TB`; `UMLAL2 VD.4S, VN.8H, VM.H[#IDX]`; `UMLAL2 VD.2D, VN.4S, VM.S[#IDX]`.
20091    /// Operands: `rd`, `rn`, `rm`.
20092    pub fn umlal2<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
20093    where
20094        Self: Umlal2Emitter<T0, T1, T2>,
20095    {
20096        <Self as Umlal2Emitter<T0, T1, T2>>::umlal2(self, rd, rn, rm);
20097    }
20098    /// Emits the `UMLSL` instruction.
20099    /// Assembly forms: `UMLSL VD.TA, VN.TB, VM.TB`; `UMLSL VD.4S, VN.4H, VM.H[#IDX]`; `UMLSL VD.2D, VN.2S, VM.S[#IDX]`.
20100    /// Operands: `rd`, `rn`, `rm`.
20101    pub fn umlsl<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
20102    where
20103        Self: UmlslEmitter<T0, T1, T2>,
20104    {
20105        <Self as UmlslEmitter<T0, T1, T2>>::umlsl(self, rd, rn, rm);
20106    }
20107    /// Emits the `UMLSL2` instruction.
20108    /// Assembly forms: `UMLSL2 VD.TA, VN.TB, VM.TB`; `UMLSL2 VD.4S, VN.8H, VM.H[#IDX]`; `UMLSL2 VD.2D, VN.4S, VM.S[#IDX]`.
20109    /// Operands: `rd`, `rn`, `rm`.
20110    pub fn umlsl2<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
20111    where
20112        Self: Umlsl2Emitter<T0, T1, T2>,
20113    {
20114        <Self as Umlsl2Emitter<T0, T1, T2>>::umlsl2(self, rd, rn, rm);
20115    }
20116    /// Emits the `UMOV` instruction.
20117    /// Assembly forms: `UMOV WD, VN.B[#IDX]`; `UMOV WD, VN.H[#IDX]`; `UMOV|MOV WD, VN.S[#IDX]`; `UMOV|MOV XD, VN.D[#IDX]`.
20118    /// Operands: `rd`, `rn`.
20119    pub fn umov<T0, T1>(&mut self, rd: T0, rn: T1)
20120    where
20121        Self: UmovEmitter<T0, T1>,
20122    {
20123        <Self as UmovEmitter<T0, T1>>::umov(self, rd, rn);
20124    }
20125    /// Emits the `UMULL2` instruction.
20126    /// Assembly forms: `UMULL2 VD.TA, VN.TB, VM.TB`; `UMULL2 VD.4S, VN.8H, VM.H[#IDX]`; `UMULL2 VD.2D, VN.4S, VM.S[#IDX]`.
20127    /// Operands: `rd`, `rn`, `rm`.
20128    pub fn umull2<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
20129    where
20130        Self: Umull2Emitter<T0, T1, T2>,
20131    {
20132        <Self as Umull2Emitter<T0, T1, T2>>::umull2(self, rd, rn, rm);
20133    }
20134    /// Emits the `UQADD` instruction.
20135    /// Assembly forms: `UQADD BD, BN, BM`; `UQADD HD, HN, HM`; `UQADD SD, SN, SM`; `UQADD DD, DN, DM` (and related forms).
20136    /// Operands: `rd`, `rn`, `rm`.
20137    pub fn uqadd<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
20138    where
20139        Self: UqaddEmitter<T0, T1, T2>,
20140    {
20141        <Self as UqaddEmitter<T0, T1, T2>>::uqadd(self, rd, rn, rm);
20142    }
20143    /// Emits the `UQRSHL` instruction.
20144    /// Assembly forms: `UQRSHL BD, BN, BM`; `UQRSHL HD, HN, HM`; `UQRSHL SD, SN, SM`; `UQRSHL DD, DN, DM` (and related forms).
20145    /// Operands: `rd`, `rn`, `rm`.
20146    pub fn uqrshl<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
20147    where
20148        Self: UqrshlEmitter<T0, T1, T2>,
20149    {
20150        <Self as UqrshlEmitter<T0, T1, T2>>::uqrshl(self, rd, rn, rm);
20151    }
20152    /// Emits the `UQRSHRN` instruction.
20153    /// Assembly forms: `UQRSHRN BD, HN, #N`; `UQRSHRN HD, SN, #N`; `UQRSHRN SD, DN, #N`; `UQRSHRN VD.8B, VN.8H, #N` (and related forms).
20154    /// Operands: `rd`, `rn`, `shift`.
20155    pub fn uqrshrn<T0, T1, T2>(&mut self, rd: T0, rn: T1, shift: T2)
20156    where
20157        Self: UqrshrnEmitter<T0, T1, T2>,
20158    {
20159        <Self as UqrshrnEmitter<T0, T1, T2>>::uqrshrn(self, rd, rn, shift);
20160    }
20161    /// Emits the `UQRSHRN2` instruction.
20162    /// Assembly forms: `UQRSHRN2 VX.16B, VN.8H, #N`; `UQRSHRN2 VX.8H, VN.4S, #N`; `UQRSHRN2 VX.4S, VN.2D, #N`.
20163    /// Operands: `operand_1`, `rn`, `shift`.
20164    pub fn uqrshrn2<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, shift: T2)
20165    where
20166        Self: Uqrshrn2Emitter<T0, T1, T2>,
20167    {
20168        <Self as Uqrshrn2Emitter<T0, T1, T2>>::uqrshrn2(self, operand_1, rn, shift);
20169    }
20170    /// Emits the `UQSHL` instruction.
20171    /// Assembly forms: `UQSHL BD, BN, BM`; `UQSHL HD, HN, HM`; `UQSHL SD, SN, SM`; `UQSHL DD, DN, DM` (and related forms).
20172    /// Operands: `rd`, `rn`, `rm_or_shift`.
20173    pub fn uqshl<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm_or_shift: T2)
20174    where
20175        Self: UqshlEmitter<T0, T1, T2>,
20176    {
20177        <Self as UqshlEmitter<T0, T1, T2>>::uqshl(self, rd, rn, rm_or_shift);
20178    }
20179    /// Emits the `UQSHRN` instruction.
20180    /// Assembly forms: `UQSHRN BD, HN, #N`; `UQSHRN HD, SN, #N`; `UQSHRN SD, DN, #N`; `UQSHRN VD.TA, VN.TB, #N`.
20181    /// Operands: `rd`, `rn`, `shift`.
20182    pub fn uqshrn<T0, T1, T2>(&mut self, rd: T0, rn: T1, shift: T2)
20183    where
20184        Self: UqshrnEmitter<T0, T1, T2>,
20185    {
20186        <Self as UqshrnEmitter<T0, T1, T2>>::uqshrn(self, rd, rn, shift);
20187    }
20188    /// Emits the `UQSHRN2` instruction.
20189    /// Assembly forms: `UQSHRN2 VX.TA, VN.TB, #N`.
20190    /// Operands: `operand_1`, `rn`, `shift`.
20191    pub fn uqshrn2<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, shift: T2)
20192    where
20193        Self: Uqshrn2Emitter<T0, T1, T2>,
20194    {
20195        <Self as Uqshrn2Emitter<T0, T1, T2>>::uqshrn2(self, operand_1, rn, shift);
20196    }
20197    /// Emits the `UQSUB` instruction.
20198    /// Assembly forms: `UQSUB BD, BN, BM`; `UQSUB HD, HN, HM`; `UQSUB SD, SN, SM`; `UQSUB DD, DN, DM` (and related forms).
20199    /// Operands: `rd`, `rn`, `rm`.
20200    pub fn uqsub<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
20201    where
20202        Self: UqsubEmitter<T0, T1, T2>,
20203    {
20204        <Self as UqsubEmitter<T0, T1, T2>>::uqsub(self, rd, rn, rm);
20205    }
20206    /// Emits the `UQXTN` instruction.
20207    /// Assembly forms: `UQXTN BD, HN`; `UQXTN HD, SN`; `UQXTN SD, DN`; `UQXTN VD.TA, VN.TB`.
20208    /// Operands: `rd`, `rn`.
20209    pub fn uqxtn<T0, T1>(&mut self, rd: T0, rn: T1)
20210    where
20211        Self: UqxtnEmitter<T0, T1>,
20212    {
20213        <Self as UqxtnEmitter<T0, T1>>::uqxtn(self, rd, rn);
20214    }
20215    /// Emits the `UQXTN2` instruction.
20216    /// Assembly forms: `UQXTN2 VX.TA, VN.TB`.
20217    /// Operands: `operand_1`, `rn`.
20218    pub fn uqxtn2<T0, T1>(&mut self, operand_1: T0, rn: T1)
20219    where
20220        Self: Uqxtn2Emitter<T0, T1>,
20221    {
20222        <Self as Uqxtn2Emitter<T0, T1>>::uqxtn2(self, operand_1, rn);
20223    }
20224    /// Emits the `URECPE` instruction.
20225    /// Assembly forms: `URECPE VD.2S, VN.2S`; `URECPE VD.4S, VN.4S`.
20226    /// Operands: `rd`, `rn`.
20227    pub fn urecpe<T0, T1>(&mut self, rd: T0, rn: T1)
20228    where
20229        Self: UrecpeEmitter<T0, T1>,
20230    {
20231        <Self as UrecpeEmitter<T0, T1>>::urecpe(self, rd, rn);
20232    }
20233    /// Emits the `URHADD` instruction.
20234    /// Assembly forms: `URHADD VD.T, VN.T, VM.T`; `URHADD VD.T, VN.T, VM.T`.
20235    /// Operands: `rd`, `rn`, `rm`.
20236    pub fn urhadd<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
20237    where
20238        Self: UrhaddEmitter<T0, T1, T2>,
20239    {
20240        <Self as UrhaddEmitter<T0, T1, T2>>::urhadd(self, rd, rn, rm);
20241    }
20242    /// Emits the `URSHL` instruction.
20243    /// Assembly forms: `URSHL DD, DN, DM`; `URSHL VD.T, VN.T, VM.T`; `URSHL VD.T, VN.T, VM.T`.
20244    /// Operands: `rd`, `rn`, `rm`.
20245    pub fn urshl<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
20246    where
20247        Self: UrshlEmitter<T0, T1, T2>,
20248    {
20249        <Self as UrshlEmitter<T0, T1, T2>>::urshl(self, rd, rn, rm);
20250    }
20251    /// Emits the `URSHR` instruction.
20252    /// Assembly forms: `URSHR DD, DN, #N`; `URSHR VD.T, VN.T, #N`; `URSHR VD.T, VN.T, #N`.
20253    /// Operands: `rd`, `rn`, `shift`.
20254    pub fn urshr<T0, T1, T2>(&mut self, rd: T0, rn: T1, shift: T2)
20255    where
20256        Self: UrshrEmitter<T0, T1, T2>,
20257    {
20258        <Self as UrshrEmitter<T0, T1, T2>>::urshr(self, rd, rn, shift);
20259    }
20260    /// Emits the `URSQRTE` instruction.
20261    /// Assembly forms: `URSQRTE VD.2S, VN.2S`; `URSQRTE VD.4S, VN.4S`.
20262    /// Operands: `rd`, `rn`.
20263    pub fn ursqrte<T0, T1>(&mut self, rd: T0, rn: T1)
20264    where
20265        Self: UrsqrteEmitter<T0, T1>,
20266    {
20267        <Self as UrsqrteEmitter<T0, T1>>::ursqrte(self, rd, rn);
20268    }
20269    /// Emits the `URSRA` instruction.
20270    /// Assembly forms: `URSRA DX, DN, #N`; `URSRA VX.T, VN.T, #N`; `URSRA VX.T, VN.T, #N`.
20271    /// Operands: `operand_1`, `rn`, `shift`.
20272    pub fn ursra<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, shift: T2)
20273    where
20274        Self: UrsraEmitter<T0, T1, T2>,
20275    {
20276        <Self as UrsraEmitter<T0, T1, T2>>::ursra(self, operand_1, rn, shift);
20277    }
20278    /// Emits the `USHL` instruction.
20279    /// Assembly forms: `USHL DD, DN, DM`; `USHL VD.T, VN.T, VM.T`; `USHL VD.T, VN.T, VM.T`.
20280    /// Operands: `rd`, `rn`, `rm`.
20281    pub fn ushl<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
20282    where
20283        Self: UshlEmitter<T0, T1, T2>,
20284    {
20285        <Self as UshlEmitter<T0, T1, T2>>::ushl(self, rd, rn, rm);
20286    }
20287    /// Emits the `USHLL` instruction.
20288    /// Assembly forms: `USHLL VD.TA, VN.TB, #N`.
20289    /// Operands: `rd`, `rn`, `shift`.
20290    pub fn ushll<T0, T1, T2>(&mut self, rd: T0, rn: T1, shift: T2)
20291    where
20292        Self: UshllEmitter<T0, T1, T2>,
20293    {
20294        <Self as UshllEmitter<T0, T1, T2>>::ushll(self, rd, rn, shift);
20295    }
20296    /// Emits the `USHLL2` instruction.
20297    /// Assembly forms: `USHLL2 VD.TA, VN.TB, #N`.
20298    /// Operands: `rd`, `rn`, `shift`.
20299    pub fn ushll2<T0, T1, T2>(&mut self, rd: T0, rn: T1, shift: T2)
20300    where
20301        Self: Ushll2Emitter<T0, T1, T2>,
20302    {
20303        <Self as Ushll2Emitter<T0, T1, T2>>::ushll2(self, rd, rn, shift);
20304    }
20305    /// Emits the `USHR` instruction.
20306    /// Assembly forms: `USHR DD, DN, #N`; `USHR VD.T, VN.T, #N`; `USHR VD.T, VN.T, #N`.
20307    /// Operands: `rd`, `rn`, `shift`.
20308    pub fn ushr<T0, T1, T2>(&mut self, rd: T0, rn: T1, shift: T2)
20309    where
20310        Self: UshrEmitter<T0, T1, T2>,
20311    {
20312        <Self as UshrEmitter<T0, T1, T2>>::ushr(self, rd, rn, shift);
20313    }
20314    /// Emits the `USQADD` instruction.
20315    /// Assembly forms: `USQADD BX, BN`; `USQADD HX, HN`; `USQADD SX, SN`; `USQADD DX, DN` (and related forms).
20316    /// Operands: `operand_1`, `rn`.
20317    pub fn usqadd<T0, T1>(&mut self, operand_1: T0, rn: T1)
20318    where
20319        Self: UsqaddEmitter<T0, T1>,
20320    {
20321        <Self as UsqaddEmitter<T0, T1>>::usqadd(self, operand_1, rn);
20322    }
20323    /// Emits the `USRA` instruction.
20324    /// Assembly forms: `USRA DX, DN, #N`; `USRA VX.T, VN.T, #N`; `USRA VX.T, VN.T, #N`.
20325    /// Operands: `operand_1`, `rn`, `shift`.
20326    pub fn usra<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, shift: T2)
20327    where
20328        Self: UsraEmitter<T0, T1, T2>,
20329    {
20330        <Self as UsraEmitter<T0, T1, T2>>::usra(self, operand_1, rn, shift);
20331    }
20332    /// Emits the `USUBL` instruction.
20333    /// Assembly forms: `USUBL VD.TA, VN.TB, VM.TB`.
20334    /// Operands: `rd`, `rn`, `rm`.
20335    pub fn usubl<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
20336    where
20337        Self: UsublEmitter<T0, T1, T2>,
20338    {
20339        <Self as UsublEmitter<T0, T1, T2>>::usubl(self, rd, rn, rm);
20340    }
20341    /// Emits the `USUBL2` instruction.
20342    /// Assembly forms: `USUBL2 VD.TA, VN.TB, VM.TB`.
20343    /// Operands: `rd`, `rn`, `rm`.
20344    pub fn usubl2<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
20345    where
20346        Self: Usubl2Emitter<T0, T1, T2>,
20347    {
20348        <Self as Usubl2Emitter<T0, T1, T2>>::usubl2(self, rd, rn, rm);
20349    }
20350    /// Emits the `USUBW` instruction.
20351    /// Assembly forms: `USUBW VD.TA, VN.TA, VM.TB`.
20352    /// Operands: `rd`, `rn`, `rm`.
20353    pub fn usubw<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
20354    where
20355        Self: UsubwEmitter<T0, T1, T2>,
20356    {
20357        <Self as UsubwEmitter<T0, T1, T2>>::usubw(self, rd, rn, rm);
20358    }
20359    /// Emits the `USUBW2` instruction.
20360    /// Assembly forms: `USUBW2 VD.TA, VN.TA, VM.TB`.
20361    /// Operands: `rd`, `rn`, `rm`.
20362    pub fn usubw2<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
20363    where
20364        Self: Usubw2Emitter<T0, T1, T2>,
20365    {
20366        <Self as Usubw2Emitter<T0, T1, T2>>::usubw2(self, rd, rn, rm);
20367    }
20368    /// Emits the `UXTL` instruction.
20369    /// Assembly forms: `UXTL VD.TA, VN.TB`.
20370    /// Operands: `rd`, `rn`.
20371    pub fn uxtl<T0, T1>(&mut self, rd: T0, rn: T1)
20372    where
20373        Self: UxtlEmitter<T0, T1>,
20374    {
20375        <Self as UxtlEmitter<T0, T1>>::uxtl(self, rd, rn);
20376    }
20377    /// Emits the `UXTL2` instruction.
20378    /// Assembly forms: `UXTL2 VD.TA, VN.TB`.
20379    /// Operands: `rd`, `rn`.
20380    pub fn uxtl2<T0, T1>(&mut self, rd: T0, rn: T1)
20381    where
20382        Self: Uxtl2Emitter<T0, T1>,
20383    {
20384        <Self as Uxtl2Emitter<T0, T1>>::uxtl2(self, rd, rn);
20385    }
20386    /// Emits the `UZP1` instruction.
20387    /// Assembly forms: `UZP1 VD.T, VN.T, VM.T`; `UZP1 VD.T, VN.T, VM.T`.
20388    /// Operands: `rd`, `rn`, `rm`.
20389    pub fn uzp1<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
20390    where
20391        Self: Uzp1Emitter<T0, T1, T2>,
20392    {
20393        <Self as Uzp1Emitter<T0, T1, T2>>::uzp1(self, rd, rn, rm);
20394    }
20395    /// Emits the `UZP2` instruction.
20396    /// Assembly forms: `UZP2 VD.T, VN.T, VM.T`; `UZP2 VD.T, VN.T, VM.T`.
20397    /// Operands: `rd`, `rn`, `rm`.
20398    pub fn uzp2<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
20399    where
20400        Self: Uzp2Emitter<T0, T1, T2>,
20401    {
20402        <Self as Uzp2Emitter<T0, T1, T2>>::uzp2(self, rd, rn, rm);
20403    }
20404    /// Emits the `XTN` instruction.
20405    /// Assembly forms: `XTN VD.TA, VN.TB`.
20406    /// Operands: `rd`, `rn`.
20407    pub fn xtn<T0, T1>(&mut self, rd: T0, rn: T1)
20408    where
20409        Self: XtnEmitter<T0, T1>,
20410    {
20411        <Self as XtnEmitter<T0, T1>>::xtn(self, rd, rn);
20412    }
20413    /// Emits the `XTN2` instruction.
20414    /// Assembly forms: `XTN2 VX.TA, VN.TB`.
20415    /// Operands: `operand_1`, `rn`.
20416    pub fn xtn2<T0, T1>(&mut self, operand_1: T0, rn: T1)
20417    where
20418        Self: Xtn2Emitter<T0, T1>,
20419    {
20420        <Self as Xtn2Emitter<T0, T1>>::xtn2(self, operand_1, rn);
20421    }
20422    /// Emits the `ZIP1` instruction.
20423    /// Assembly forms: `ZIP1 VD.T, VN.T, VM.T`; `ZIP1 VD.T, VN.T, VM.T`.
20424    /// Operands: `rd`, `rn`, `rm`.
20425    pub fn zip1<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
20426    where
20427        Self: Zip1Emitter<T0, T1, T2>,
20428    {
20429        <Self as Zip1Emitter<T0, T1, T2>>::zip1(self, rd, rn, rm);
20430    }
20431    /// Emits the `ZIP2` instruction.
20432    /// Assembly forms: `ZIP2 VD.T, VN.T, VM.T`; `ZIP2 VD.T, VN.T, VM.T`.
20433    /// Operands: `rd`, `rn`, `rm`.
20434    pub fn zip2<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
20435    where
20436        Self: Zip2Emitter<T0, T1, T2>,
20437    {
20438        <Self as Zip2Emitter<T0, T1, T2>>::zip2(self, rd, rn, rm);
20439    }
20440    /// Emits the `AESD` instruction.
20441    /// Assembly forms: `AESD VD.16B, VN.16B`.
20442    /// Operands: `rd`, `rn`.
20443    pub fn aesd<T0, T1>(&mut self, rd: T0, rn: T1)
20444    where
20445        Self: AesdEmitter<T0, T1>,
20446    {
20447        <Self as AesdEmitter<T0, T1>>::aesd(self, rd, rn);
20448    }
20449    /// Emits the `AESE` instruction.
20450    /// Assembly forms: `AESE VD.16B, VN.16B`.
20451    /// Operands: `rd`, `rn`.
20452    pub fn aese<T0, T1>(&mut self, rd: T0, rn: T1)
20453    where
20454        Self: AeseEmitter<T0, T1>,
20455    {
20456        <Self as AeseEmitter<T0, T1>>::aese(self, rd, rn);
20457    }
20458    /// Emits the `AESIMC` instruction.
20459    /// Assembly forms: `AESIMC VD.16B, VN.16B`.
20460    /// Operands: `rd`, `rn`.
20461    pub fn aesimc<T0, T1>(&mut self, rd: T0, rn: T1)
20462    where
20463        Self: AesimcEmitter<T0, T1>,
20464    {
20465        <Self as AesimcEmitter<T0, T1>>::aesimc(self, rd, rn);
20466    }
20467    /// Emits the `AESMC` instruction.
20468    /// Assembly forms: `AESMC VD.16B, VN.16B`.
20469    /// Operands: `rd`, `rn`.
20470    pub fn aesmc<T0, T1>(&mut self, rd: T0, rn: T1)
20471    where
20472        Self: AesmcEmitter<T0, T1>,
20473    {
20474        <Self as AesmcEmitter<T0, T1>>::aesmc(self, rd, rn);
20475    }
20476    /// Emits the `SHA1C` instruction.
20477    /// Assembly forms: `SHA1C QX, SN, VM.4S`.
20478    /// Operands: `operand_1`, `rn`, `rm`.
20479    pub fn sha1c<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)
20480    where
20481        Self: Sha1cEmitter<T0, T1, T2>,
20482    {
20483        <Self as Sha1cEmitter<T0, T1, T2>>::sha1c(self, operand_1, rn, rm);
20484    }
20485    /// Emits the `SHA1H` instruction.
20486    /// Assembly forms: `SHA1H SD, SN`.
20487    /// Operands: `rd`, `rn`.
20488    pub fn sha1h<T0, T1>(&mut self, rd: T0, rn: T1)
20489    where
20490        Self: Sha1hEmitter<T0, T1>,
20491    {
20492        <Self as Sha1hEmitter<T0, T1>>::sha1h(self, rd, rn);
20493    }
20494    /// Emits the `SHA1M` instruction.
20495    /// Assembly forms: `SHA1M QX, SN, VM.4S`.
20496    /// Operands: `operand_1`, `rn`, `rm`.
20497    pub fn sha1m<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)
20498    where
20499        Self: Sha1mEmitter<T0, T1, T2>,
20500    {
20501        <Self as Sha1mEmitter<T0, T1, T2>>::sha1m(self, operand_1, rn, rm);
20502    }
20503    /// Emits the `SHA1P` instruction.
20504    /// Assembly forms: `SHA1P QX, SN, VM.4S`.
20505    /// Operands: `operand_1`, `rn`, `rm`.
20506    pub fn sha1p<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)
20507    where
20508        Self: Sha1pEmitter<T0, T1, T2>,
20509    {
20510        <Self as Sha1pEmitter<T0, T1, T2>>::sha1p(self, operand_1, rn, rm);
20511    }
20512    /// Emits the `SHA1SU0` instruction.
20513    /// Assembly forms: `SHA1SU0 VX.4S, VN.4S, VM.4S`.
20514    /// Operands: `operand_1`, `rn`, `rm`.
20515    pub fn sha1su0<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)
20516    where
20517        Self: Sha1su0Emitter<T0, T1, T2>,
20518    {
20519        <Self as Sha1su0Emitter<T0, T1, T2>>::sha1su0(self, operand_1, rn, rm);
20520    }
20521    /// Emits the `SHA1SU1` instruction.
20522    /// Assembly forms: `SHA1SU1 VX.4S, VN.4S`.
20523    /// Operands: `operand_1`, `rn`.
20524    pub fn sha1su1<T0, T1>(&mut self, operand_1: T0, rn: T1)
20525    where
20526        Self: Sha1su1Emitter<T0, T1>,
20527    {
20528        <Self as Sha1su1Emitter<T0, T1>>::sha1su1(self, operand_1, rn);
20529    }
20530    /// Emits the `SHA256H` instruction.
20531    /// Assembly forms: `SHA256H QX, QN, VM.4S`.
20532    /// Operands: `operand_1`, `rn`, `rm`.
20533    pub fn sha256h<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)
20534    where
20535        Self: Sha256hEmitter<T0, T1, T2>,
20536    {
20537        <Self as Sha256hEmitter<T0, T1, T2>>::sha256h(self, operand_1, rn, rm);
20538    }
20539    /// Emits the `SHA256H2` instruction.
20540    /// Assembly forms: `SHA256H2 QX, QN, VM.4S`.
20541    /// Operands: `operand_1`, `rn`, `rm`.
20542    pub fn sha256h2<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)
20543    where
20544        Self: Sha256h2Emitter<T0, T1, T2>,
20545    {
20546        <Self as Sha256h2Emitter<T0, T1, T2>>::sha256h2(self, operand_1, rn, rm);
20547    }
20548    /// Emits the `SHA256SU0` instruction.
20549    /// Assembly forms: `SHA256SU0 VX.4S, VN.4S`.
20550    /// Operands: `operand_1`, `rn`.
20551    pub fn sha256su0<T0, T1>(&mut self, operand_1: T0, rn: T1)
20552    where
20553        Self: Sha256su0Emitter<T0, T1>,
20554    {
20555        <Self as Sha256su0Emitter<T0, T1>>::sha256su0(self, operand_1, rn);
20556    }
20557    /// Emits the `SHA256SU1` instruction.
20558    /// Assembly forms: `SHA256SU1 VX.4S, VN.4S, VM.4S`.
20559    /// Operands: `operand_1`, `rn`, `rm`.
20560    pub fn sha256su1<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)
20561    where
20562        Self: Sha256su1Emitter<T0, T1, T2>,
20563    {
20564        <Self as Sha256su1Emitter<T0, T1, T2>>::sha256su1(self, operand_1, rn, rm);
20565    }
20566    /// Emits the `SQRDMLAH` instruction.
20567    /// Assembly forms: `SQRDMLAH HX, HN, HM`; `SQRDMLAH SX, SN, SM`; `SQRDMLAH HX, HN, VN.H[#IDX]`; `SQRDMLAH SX, SN, VN.S[#IDX]` (and related forms).
20568    /// Operands: `operand_1`, `rn`, `rm_or_rn`.
20569    pub fn sqrdmlah<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm_or_rn: T2)
20570    where
20571        Self: SqrdmlahEmitter<T0, T1, T2>,
20572    {
20573        <Self as SqrdmlahEmitter<T0, T1, T2>>::sqrdmlah(self, operand_1, rn, rm_or_rn);
20574    }
20575    /// Emits the `SQRDMLSH` instruction.
20576    /// Assembly forms: `SQRDMLSH HX, HN, HM`; `SQRDMLSH SX, SN, SM`; `SQRDMLSH HX, HN, VN.H[#IDX]`; `SQRDMLSH SX, SN, VN.S[#IDX]` (and related forms).
20577    /// Operands: `operand_1`, `rn`, `rm_or_rn`.
20578    pub fn sqrdmlsh<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm_or_rn: T2)
20579    where
20580        Self: SqrdmlshEmitter<T0, T1, T2>,
20581    {
20582        <Self as SqrdmlshEmitter<T0, T1, T2>>::sqrdmlsh(self, operand_1, rn, rm_or_rn);
20583    }
20584    /// Emits the `FCADD` instruction.
20585    /// Assembly forms: `FCADD VD.T, VN.T, VM.T, #ROTATE`; `FCADD VD.T, VN.T, VM.T, #ROTATE`.
20586    /// Operands: `rd`, `rn`, `rm`, `rotate`.
20587    pub fn fcadd<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm: T2, rotate: T3)
20588    where
20589        Self: FcaddEmitter<T0, T1, T2, T3>,
20590    {
20591        <Self as FcaddEmitter<T0, T1, T2, T3>>::fcadd(self, rd, rn, rm, rotate);
20592    }
20593    /// Emits the `FCMLA` instruction.
20594    /// Assembly forms: `FCMLA VD.T, VN.T, VM.T, #ROTATE`; `FCMLA VD.T, VN.T, VM.T, #ROTATE`; `FCMLA VD.4H, VN.4H, VM.H[#IDX], #ROTATE`; `FCMLA VD.8H, VN.8H, VM.H[#IDX], #ROTATE` (and related forms).
20595    /// Operands: `rd`, `rn`, `rm`, `rotate`.
20596    pub fn fcmla<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm: T2, rotate: T3)
20597    where
20598        Self: FcmlaEmitter<T0, T1, T2, T3>,
20599    {
20600        <Self as FcmlaEmitter<T0, T1, T2, T3>>::fcmla(self, rd, rn, rm, rotate);
20601    }
20602    /// Emits the `FJCVTZS` instruction.
20603    /// Assembly forms: `FJCVTZS WD, DN`.
20604    /// Operands: `rd`, `rn`.
20605    pub fn fjcvtzs<T0, T1>(&mut self, rd: T0, rn: T1)
20606    where
20607        Self: FjcvtzsEmitter<T0, T1>,
20608    {
20609        <Self as FjcvtzsEmitter<T0, T1>>::fjcvtzs(self, rd, rn);
20610    }
20611    /// Emits the `FMLAL` instruction.
20612    /// Assembly forms: `FMLAL VX.2S, VN.2H, VM.2H`; `FMLAL VX.4S, VN.4H, VM.4H`; `FMLAL VX.2S, VN.2H, VM.H[#IDX]`; `FMLAL VX.4S, VN.4H, VM.H[#IDX]`.
20613    /// Operands: `operand_1`, `rn`, `rm`.
20614    pub fn fmlal<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)
20615    where
20616        Self: FmlalEmitter<T0, T1, T2>,
20617    {
20618        <Self as FmlalEmitter<T0, T1, T2>>::fmlal(self, operand_1, rn, rm);
20619    }
20620    /// Emits the `FMLAL2` instruction.
20621    /// Assembly forms: `FMLAL2 VX.2S, VN.2H, VM.2H`; `FMLAL2 VX.4S, VN.4H, VM.4H`; `FMLAL2 VX.2S, VN.2H, VM.H[#IDX]`; `FMLAL2 VX.4S, VN.4H, VM.H[#IDX]`.
20622    /// Operands: `operand_1`, `rn`, `rm`.
20623    pub fn fmlal2<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)
20624    where
20625        Self: Fmlal2Emitter<T0, T1, T2>,
20626    {
20627        <Self as Fmlal2Emitter<T0, T1, T2>>::fmlal2(self, operand_1, rn, rm);
20628    }
20629    /// Emits the `FMLSL` instruction.
20630    /// Assembly forms: `FMLSL VX.2S, VN.2H, VM.2H`; `FMLSL VX.4S, VN.4H, VM.4H`; `FMLSL VX.2S, VN.2H, VM.H[#IDX]`; `FMLSL VX.4S, VN.4H, VM.H[#IDX]`.
20631    /// Operands: `operand_1`, `rn`, `rm`.
20632    pub fn fmlsl<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)
20633    where
20634        Self: FmlslEmitter<T0, T1, T2>,
20635    {
20636        <Self as FmlslEmitter<T0, T1, T2>>::fmlsl(self, operand_1, rn, rm);
20637    }
20638    /// Emits the `FMLSL2` instruction.
20639    /// Assembly forms: `FMLSL2 VX.2S, VN.2H, VM.2H`; `FMLSL2 VX.4S, VN.4H, VM.4H`; `FMLSL2 VX.2S, VN.2H, VM.H[#IDX]`; `FMLSL2 VX.4S, VN.4H, VM.H[#IDX]`.
20640    /// Operands: `operand_1`, `rn`, `rm`.
20641    pub fn fmlsl2<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)
20642    where
20643        Self: Fmlsl2Emitter<T0, T1, T2>,
20644    {
20645        <Self as Fmlsl2Emitter<T0, T1, T2>>::fmlsl2(self, operand_1, rn, rm);
20646    }
20647    /// Emits the `BCAX` instruction.
20648    /// Assembly forms: `BCAX VD.16B, VN.16B, VM.16B, VA.16B`.
20649    /// Operands: `rd`, `rn`, `rm`, `operand_4`.
20650    pub fn bcax<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm: T2, operand_4: T3)
20651    where
20652        Self: BcaxEmitter<T0, T1, T2, T3>,
20653    {
20654        <Self as BcaxEmitter<T0, T1, T2, T3>>::bcax(self, rd, rn, rm, operand_4);
20655    }
20656    /// Emits the `EOR3` instruction.
20657    /// Assembly forms: `EOR3 VD.16B, VN.16B, VM.16B, VA.16B`.
20658    /// Operands: `rd`, `rn`, `rm`, `operand_4`.
20659    pub fn eor3<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm: T2, operand_4: T3)
20660    where
20661        Self: Eor3Emitter<T0, T1, T2, T3>,
20662    {
20663        <Self as Eor3Emitter<T0, T1, T2, T3>>::eor3(self, rd, rn, rm, operand_4);
20664    }
20665    /// Emits the `RAX1` instruction.
20666    /// Assembly forms: `RAX1 VD.2D, VN.2D, VM.2D`.
20667    /// Operands: `rd`, `rn`, `rm`.
20668    pub fn rax1<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
20669    where
20670        Self: Rax1Emitter<T0, T1, T2>,
20671    {
20672        <Self as Rax1Emitter<T0, T1, T2>>::rax1(self, rd, rn, rm);
20673    }
20674    /// Emits the `XAR` instruction.
20675    /// Assembly forms: `XAR VD.2D, VN.2D, VM.2D, #IMM`.
20676    /// Operands: `rd`, `rn`, `rm`, `imm`.
20677    pub fn xar<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm: T2, imm: T3)
20678    where
20679        Self: XarEmitter<T0, T1, T2, T3>,
20680    {
20681        <Self as XarEmitter<T0, T1, T2, T3>>::xar(self, rd, rn, rm, imm);
20682    }
20683    /// Emits the `SHA512H` instruction.
20684    /// Assembly forms: `SHA512H QX, QN, VM.2D`.
20685    /// Operands: `operand_1`, `rn`, `rm`.
20686    pub fn sha512h<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)
20687    where
20688        Self: Sha512hEmitter<T0, T1, T2>,
20689    {
20690        <Self as Sha512hEmitter<T0, T1, T2>>::sha512h(self, operand_1, rn, rm);
20691    }
20692    /// Emits the `SHA512H2` instruction.
20693    /// Assembly forms: `SHA512H2 QX, QN, VM.2D`.
20694    /// Operands: `operand_1`, `rn`, `rm`.
20695    pub fn sha512h2<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)
20696    where
20697        Self: Sha512h2Emitter<T0, T1, T2>,
20698    {
20699        <Self as Sha512h2Emitter<T0, T1, T2>>::sha512h2(self, operand_1, rn, rm);
20700    }
20701    /// Emits the `SHA512SU0` instruction.
20702    /// Assembly forms: `SHA512SU0 VX.2D, VN.2D`.
20703    /// Operands: `operand_1`, `rn`.
20704    pub fn sha512su0<T0, T1>(&mut self, operand_1: T0, rn: T1)
20705    where
20706        Self: Sha512su0Emitter<T0, T1>,
20707    {
20708        <Self as Sha512su0Emitter<T0, T1>>::sha512su0(self, operand_1, rn);
20709    }
20710    /// Emits the `SHA512SU1` instruction.
20711    /// Assembly forms: `SHA512SU1 VX.2D, VN.2D, VM.2D`.
20712    /// Operands: `operand_1`, `rn`, `rm`.
20713    pub fn sha512su1<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)
20714    where
20715        Self: Sha512su1Emitter<T0, T1, T2>,
20716    {
20717        <Self as Sha512su1Emitter<T0, T1, T2>>::sha512su1(self, operand_1, rn, rm);
20718    }
20719    /// Emits the `SM3PARTW1` instruction.
20720    /// Assembly forms: `SM3PARTW1 VX.4S, VN.4S, VM.4S`.
20721    /// Operands: `operand_1`, `rn`, `rm`.
20722    pub fn sm3partw1<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)
20723    where
20724        Self: Sm3partw1Emitter<T0, T1, T2>,
20725    {
20726        <Self as Sm3partw1Emitter<T0, T1, T2>>::sm3partw1(self, operand_1, rn, rm);
20727    }
20728    /// Emits the `SM3PARTW2` instruction.
20729    /// Assembly forms: `SM3PARTW2 VX.4S, VN.4S, VM.4S`.
20730    /// Operands: `operand_1`, `rn`, `rm`.
20731    pub fn sm3partw2<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)
20732    where
20733        Self: Sm3partw2Emitter<T0, T1, T2>,
20734    {
20735        <Self as Sm3partw2Emitter<T0, T1, T2>>::sm3partw2(self, operand_1, rn, rm);
20736    }
20737    /// Emits the `SM3SS1` instruction.
20738    /// Assembly forms: `SM3SS1 VD.4S, VN.4S, VM.4S, VA.4S`.
20739    /// Operands: `rd`, `rn`, `rm`, `operand_4`.
20740    pub fn sm3ss1<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm: T2, operand_4: T3)
20741    where
20742        Self: Sm3ss1Emitter<T0, T1, T2, T3>,
20743    {
20744        <Self as Sm3ss1Emitter<T0, T1, T2, T3>>::sm3ss1(self, rd, rn, rm, operand_4);
20745    }
20746    /// Emits the `SM3TT1A` instruction.
20747    /// Assembly forms: `SM3TT1A VX.4S, VN.4S, VM.4[#IDX]`.
20748    /// Operands: `operand_1`, `rn`, `rm`.
20749    pub fn sm3tt1a<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)
20750    where
20751        Self: Sm3tt1aEmitter<T0, T1, T2>,
20752    {
20753        <Self as Sm3tt1aEmitter<T0, T1, T2>>::sm3tt1a(self, operand_1, rn, rm);
20754    }
20755    /// Emits the `SM3TT1B` instruction.
20756    /// Assembly forms: `SM3TT1B VX.4S, VN.4S, VM.4[#IDX]`.
20757    /// Operands: `operand_1`, `rn`, `rm`.
20758    pub fn sm3tt1b<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)
20759    where
20760        Self: Sm3tt1bEmitter<T0, T1, T2>,
20761    {
20762        <Self as Sm3tt1bEmitter<T0, T1, T2>>::sm3tt1b(self, operand_1, rn, rm);
20763    }
20764    /// Emits the `SM3TT2A` instruction.
20765    /// Assembly forms: `SM3TT2A VX.4S, VN.4S, VM.4[#IDX]`.
20766    /// Operands: `operand_1`, `rn`, `rm`.
20767    pub fn sm3tt2a<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)
20768    where
20769        Self: Sm3tt2aEmitter<T0, T1, T2>,
20770    {
20771        <Self as Sm3tt2aEmitter<T0, T1, T2>>::sm3tt2a(self, operand_1, rn, rm);
20772    }
20773    /// Emits the `SM3TT2B` instruction.
20774    /// Assembly forms: `SM3TT2B VX.4S, VN.4S, VM.4[#IDX]`.
20775    /// Operands: `operand_1`, `rn`, `rm`.
20776    pub fn sm3tt2b<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)
20777    where
20778        Self: Sm3tt2bEmitter<T0, T1, T2>,
20779    {
20780        <Self as Sm3tt2bEmitter<T0, T1, T2>>::sm3tt2b(self, operand_1, rn, rm);
20781    }
20782    /// Emits the `SM4E` instruction.
20783    /// Assembly forms: `SM4E VX.4S, VN.4S`.
20784    /// Operands: `operand_1`, `rn`.
20785    pub fn sm4e<T0, T1>(&mut self, operand_1: T0, rn: T1)
20786    where
20787        Self: Sm4eEmitter<T0, T1>,
20788    {
20789        <Self as Sm4eEmitter<T0, T1>>::sm4e(self, operand_1, rn);
20790    }
20791    /// Emits the `SM4EKEY` instruction.
20792    /// Assembly forms: `SM4EKEY VD.4S, VN.4S, VM.4S`.
20793    /// Operands: `rd`, `rn`, `rm`.
20794    pub fn sm4ekey<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)
20795    where
20796        Self: Sm4ekeyEmitter<T0, T1, T2>,
20797    {
20798        <Self as Sm4ekeyEmitter<T0, T1, T2>>::sm4ekey(self, rd, rn, rm);
20799    }
20800    /// Emits the `SDOT` instruction.
20801    /// Assembly forms: `SDOT VX.2S, VN.8B, VM.8B`; `SDOT VX.4S, VN.16B, VM.16B`; `SDOT VX.2S, VN.8B, VM.4B[#IDX]`; `SDOT VX.4S, VN.16B, VM.4B[#IDX]`.
20802    /// Operands: `operand_1`, `rn`, `rm`.
20803    pub fn sdot<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)
20804    where
20805        Self: SdotEmitter<T0, T1, T2>,
20806    {
20807        <Self as SdotEmitter<T0, T1, T2>>::sdot(self, operand_1, rn, rm);
20808    }
20809    /// Emits the `UDOT` instruction.
20810    /// Assembly forms: `UDOT VX.2S, VN.8B, VM.8B`; `UDOT VX.4S, VN.16B, VM.16B`; `UDOT VX.2S, VN.8B, VM.4B[#IDX]`; `UDOT VX.4S, VN.16B, VM.4B[#IDX]`.
20811    /// Operands: `operand_1`, `rn`, `rm`.
20812    pub fn udot<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)
20813    where
20814        Self: UdotEmitter<T0, T1, T2>,
20815    {
20816        <Self as UdotEmitter<T0, T1, T2>>::udot(self, operand_1, rn, rm);
20817    }
20818    /// Emits the `BFCVT` instruction.
20819    /// Assembly forms: `BFCVT HD, SN`.
20820    /// Operands: `rd`, `rn`.
20821    pub fn bfcvt<T0, T1>(&mut self, rd: T0, rn: T1)
20822    where
20823        Self: BfcvtEmitter<T0, T1>,
20824    {
20825        <Self as BfcvtEmitter<T0, T1>>::bfcvt(self, rd, rn);
20826    }
20827    /// Emits the `BFCVTN` instruction.
20828    /// Assembly forms: `BFCVTN VD.4H, VN.4S`.
20829    /// Operands: `rd`, `rn`.
20830    pub fn bfcvtn<T0, T1>(&mut self, rd: T0, rn: T1)
20831    where
20832        Self: BfcvtnEmitter<T0, T1>,
20833    {
20834        <Self as BfcvtnEmitter<T0, T1>>::bfcvtn(self, rd, rn);
20835    }
20836    /// Emits the `BFCVTN2` instruction.
20837    /// Assembly forms: `BFCVTN2 VD.8H, VN.4S`.
20838    /// Operands: `rd`, `rn`.
20839    pub fn bfcvtn2<T0, T1>(&mut self, rd: T0, rn: T1)
20840    where
20841        Self: Bfcvtn2Emitter<T0, T1>,
20842    {
20843        <Self as Bfcvtn2Emitter<T0, T1>>::bfcvtn2(self, rd, rn);
20844    }
20845    /// Emits the `BFMLALB` instruction.
20846    /// Assembly forms: `BFMLALB VX.4S, VN.8H, VM.8H`; `BFMLALB VX.4S, VN.8H, VM.H[#IDX]`.
20847    /// Operands: `operand_1`, `rn`, `rm`.
20848    pub fn bfmlalb<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)
20849    where
20850        Self: BfmlalbEmitter<T0, T1, T2>,
20851    {
20852        <Self as BfmlalbEmitter<T0, T1, T2>>::bfmlalb(self, operand_1, rn, rm);
20853    }
20854    /// Emits the `BFMLALT` instruction.
20855    /// Assembly forms: `BFMLALT VX.4S, VN.8H, VM.8H`; `BFMLALT VX.4S, VN.8H, VM.H[#IDX]`.
20856    /// Operands: `operand_1`, `rn`, `rm`.
20857    pub fn bfmlalt<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)
20858    where
20859        Self: BfmlaltEmitter<T0, T1, T2>,
20860    {
20861        <Self as BfmlaltEmitter<T0, T1, T2>>::bfmlalt(self, operand_1, rn, rm);
20862    }
20863    /// Emits the `BFMMLA` instruction.
20864    /// Assembly forms: `BFMMLA VX.4S, VN.8H, VM.8H`.
20865    /// Operands: `operand_1`, `rn`, `rm`.
20866    pub fn bfmmla<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)
20867    where
20868        Self: BfmmlaEmitter<T0, T1, T2>,
20869    {
20870        <Self as BfmmlaEmitter<T0, T1, T2>>::bfmmla(self, operand_1, rn, rm);
20871    }
20872    /// Emits the `BFDOT` instruction.
20873    /// Assembly forms: `BFDOT VX.2S, VN.4H, VM.4H`; `BFDOT VX.4S, VN.8H, VM.8H`; `BFDOT VX.2S, VN.4H, VM.2H[#IDX]`; `BFDOT VX.4S, VN.8H, VM.2H[#IDX]`.
20874    /// Operands: `operand_1`, `rn`, `rm`.
20875    pub fn bfdot<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)
20876    where
20877        Self: BfdotEmitter<T0, T1, T2>,
20878    {
20879        <Self as BfdotEmitter<T0, T1, T2>>::bfdot(self, operand_1, rn, rm);
20880    }
20881    /// Emits the `SMMLA` instruction.
20882    /// Assembly forms: `SMMLA VX.4S, VN.16B, VM.16B`.
20883    /// Operands: `operand_1`, `rn`, `rm`.
20884    pub fn smmla<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)
20885    where
20886        Self: SmmlaEmitter<T0, T1, T2>,
20887    {
20888        <Self as SmmlaEmitter<T0, T1, T2>>::smmla(self, operand_1, rn, rm);
20889    }
20890    /// Emits the `SUDOT` instruction.
20891    /// Assembly forms: `SUDOT VX.2S, VN.8B, VM.4B[#IDX]`; `SUDOT VX.4S, VN.16B, VM.4B[#IDX]`.
20892    /// Operands: `operand_1`, `rn`, `rm`.
20893    pub fn sudot<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)
20894    where
20895        Self: SudotEmitter<T0, T1, T2>,
20896    {
20897        <Self as SudotEmitter<T0, T1, T2>>::sudot(self, operand_1, rn, rm);
20898    }
20899    /// Emits the `UMMLA` instruction.
20900    /// Assembly forms: `UMMLA VX.4S, VN.16B, VM.16B`.
20901    /// Operands: `operand_1`, `rn`, `rm`.
20902    pub fn ummla<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)
20903    where
20904        Self: UmmlaEmitter<T0, T1, T2>,
20905    {
20906        <Self as UmmlaEmitter<T0, T1, T2>>::ummla(self, operand_1, rn, rm);
20907    }
20908    /// Emits the `USDOT` instruction.
20909    /// Assembly forms: `USDOT VX.2S, VN.8B, VM.TB`; `USDOT VX.4S, VN.16B, VM.TB`; `USDOT VX.2S, VN.8B, VM.4B[#IDX]`; `USDOT VX.4S, VN.16B, VM.4B[#IDX]`.
20910    /// Operands: `operand_1`, `rn`, `rm`.
20911    pub fn usdot<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)
20912    where
20913        Self: UsdotEmitter<T0, T1, T2>,
20914    {
20915        <Self as UsdotEmitter<T0, T1, T2>>::usdot(self, operand_1, rn, rm);
20916    }
20917    /// Emits the `USMMLA` instruction.
20918    /// Assembly forms: `USMMLA VX.4S, VN.16B, VM.16B`.
20919    /// Operands: `operand_1`, `rn`, `rm`.
20920    pub fn usmmla<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)
20921    where
20922        Self: UsmmlaEmitter<T0, T1, T2>,
20923    {
20924        <Self as UsmmlaEmitter<T0, T1, T2>>::usmmla(self, operand_1, rn, rm);
20925    }
20926}
asmkit/aarch64/emitter.rs

asmkit/aarch64/
emitter.rs
