asmkit/x86/features/
PREFETCHW.rs

1use crate::x86::assembler::*;
2use crate::x86::operands::*;
3use super::super::opcodes::*;
4use crate::core::emitter::*;
5use crate::core::operand::*;
6
7/// A dummy operand that represents no register. Here just for simplicity.
8const NOREG: Operand = Operand::new();
9
10/// `PREFETCHW` (PREFETCHW). 
11/// Fetches the cache line of data from memory that contains the byte specified with the source operand to a location in the 1st or 2nd level cache and invalidates other cached instances of the line.
12///
13///
14/// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/PREFETCHW.html).
15///
16/// Supported operand variants:
17///
18/// ```text
19/// +---+----------+
20/// | # | Operands |
21/// +---+----------+
22/// | 1 | Mem      |
23/// +---+----------+
24/// ```
25pub trait PrefetchwEmitter<A> {
26    fn prefetchw(&mut self, op0: A);
27}
28
29impl<'a> PrefetchwEmitter<Mem> for Assembler<'a> {
30    fn prefetchw(&mut self, op0: Mem) {
31        self.emit(PREFETCHWM, op0.as_operand(), &NOREG, &NOREG, &NOREG);
32    }
33}
34
35
36impl<'a> Assembler<'a> {
37    /// `PREFETCHW` (PREFETCHW). 
38    /// Fetches the cache line of data from memory that contains the byte specified with the source operand to a location in the 1st or 2nd level cache and invalidates other cached instances of the line.
39    ///
40    ///
41    /// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/PREFETCHW.html).
42    ///
43    /// Supported operand variants:
44    ///
45    /// ```text
46    /// +---+----------+
47    /// | # | Operands |
48    /// +---+----------+
49    /// | 1 | Mem      |
50    /// +---+----------+
51    /// ```
52    #[inline]
53    pub fn prefetchw<A>(&mut self, op0: A)
54    where Assembler<'a>: PrefetchwEmitter<A> {
55        <Self as PrefetchwEmitter<A>>::prefetchw(self, op0);
56    }
57}
asmkit/x86/features/PREFETCHW.rs

asmkit/x86/features/
PREFETCHW.rs
