asmkit/x86/features/
MOVDIR64B.rs

1use crate::x86::assembler::*;
2use crate::x86::operands::*;
3use super::super::opcodes::*;
4use crate::core::emitter::*;
5use crate::core::operand::*;
6
7/// A dummy operand that represents no register. Here just for simplicity.
8const NOREG: Operand = Operand::new();
9
10/// `MOVDIR64B` (MOVDIR64B). 
11/// Moves 64-bytes as direct-store with 64-byte write atomicity from source memory address to destination memory address. The source operand is a normal memory operand. The destination operand is a memory location specified in a general-purpose register. The register content is interpreted as an offset into ES segment without any segment override. In 64-bit mode, the register operand width is 64-bits (32-bits with 67H prefix). Outside of 64-bit mode, the register width is 32-bits when CS.D=1 (16-bits with 67H prefix), and 16-bits when CS.D=0 (32-bits with 67H prefix). MOVDIR64B requires the destination address to be 64-byte aligned. No alignment restriction is enforced for source operand.
12///
13///
14/// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/MOVDIR64B.html).
15///
16/// Supported operand variants:
17///
18/// ```text
19/// +---+----------+
20/// | # | Operands |
21/// +---+----------+
22/// | 1 | Gpq, Mem |
23/// +---+----------+
24/// ```
25pub trait Movdir64bEmitter<A, B> {
26    fn movdir64b(&mut self, op0: A, op1: B);
27}
28
29impl<'a> Movdir64bEmitter<Gpq, Mem> for Assembler<'a> {
30    fn movdir64b(&mut self, op0: Gpq, op1: Mem) {
31        self.emit(MOVDIR64BRM, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
32    }
33}
34
35
36impl<'a> Assembler<'a> {
37    /// `MOVDIR64B` (MOVDIR64B). 
38    /// Moves 64-bytes as direct-store with 64-byte write atomicity from source memory address to destination memory address. The source operand is a normal memory operand. The destination operand is a memory location specified in a general-purpose register. The register content is interpreted as an offset into ES segment without any segment override. In 64-bit mode, the register operand width is 64-bits (32-bits with 67H prefix). Outside of 64-bit mode, the register width is 32-bits when CS.D=1 (16-bits with 67H prefix), and 16-bits when CS.D=0 (32-bits with 67H prefix). MOVDIR64B requires the destination address to be 64-byte aligned. No alignment restriction is enforced for source operand.
39    ///
40    ///
41    /// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/MOVDIR64B.html).
42    ///
43    /// Supported operand variants:
44    ///
45    /// ```text
46    /// +---+----------+
47    /// | # | Operands |
48    /// +---+----------+
49    /// | 1 | Gpq, Mem |
50    /// +---+----------+
51    /// ```
52    #[inline]
53    pub fn movdir64b<A, B>(&mut self, op0: A, op1: B)
54    where Assembler<'a>: Movdir64bEmitter<A, B> {
55        <Self as Movdir64bEmitter<A, B>>::movdir64b(self, op0, op1);
56    }
57}
asmkit/x86/features/MOVDIR64B.rs

asmkit/x86/features/
MOVDIR64B.rs
