asmkit/x86/features/AVX512_VPOPCNTDQ.rs
1use crate::x86::assembler::*;
2use crate::x86::operands::*;
3use super::super::opcodes::*;
4use crate::core::emitter::*;
5use crate::core::operand::*;
6
7/// A dummy operand that represents no register. Here just for simplicity.
8const NOREG: Operand = Operand::new();
9
10/// `VPOPCNTD` (VPOPCNTD).
11/// This instruction counts the number of bits set to one in each byte, word, dword or qword element of its source (e.g., zmm2 or memory) and places the results in the destination register (zmm1). This instruction supports memory fault suppression.
12///
13///
14/// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VPOPCNT.html).
15///
16/// Supported operand variants:
17///
18/// ```text
19/// +---+----------+
20/// | # | Operands |
21/// +---+----------+
22/// | 1 | Xmm, Mem |
23/// | 2 | Xmm, Xmm |
24/// | 3 | Ymm, Mem |
25/// | 4 | Ymm, Ymm |
26/// | 5 | Zmm, Mem |
27/// | 6 | Zmm, Zmm |
28/// +---+----------+
29/// ```
30pub trait VpopcntdEmitter<A, B> {
31 fn vpopcntd(&mut self, op0: A, op1: B);
32}
33
34impl<'a> VpopcntdEmitter<Xmm, Xmm> for Assembler<'a> {
35 fn vpopcntd(&mut self, op0: Xmm, op1: Xmm) {
36 self.emit(VPOPCNTD128RR, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
37 }
38}
39
40impl<'a> VpopcntdEmitter<Xmm, Mem> for Assembler<'a> {
41 fn vpopcntd(&mut self, op0: Xmm, op1: Mem) {
42 self.emit(VPOPCNTD128RM, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
43 }
44}
45
46impl<'a> VpopcntdEmitter<Ymm, Ymm> for Assembler<'a> {
47 fn vpopcntd(&mut self, op0: Ymm, op1: Ymm) {
48 self.emit(VPOPCNTD256RR, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
49 }
50}
51
52impl<'a> VpopcntdEmitter<Ymm, Mem> for Assembler<'a> {
53 fn vpopcntd(&mut self, op0: Ymm, op1: Mem) {
54 self.emit(VPOPCNTD256RM, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
55 }
56}
57
58impl<'a> VpopcntdEmitter<Zmm, Zmm> for Assembler<'a> {
59 fn vpopcntd(&mut self, op0: Zmm, op1: Zmm) {
60 self.emit(VPOPCNTD512RR, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
61 }
62}
63
64impl<'a> VpopcntdEmitter<Zmm, Mem> for Assembler<'a> {
65 fn vpopcntd(&mut self, op0: Zmm, op1: Mem) {
66 self.emit(VPOPCNTD512RM, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
67 }
68}
69
70/// `VPOPCNTD_MASK` (VPOPCNTD).
71/// This instruction counts the number of bits set to one in each byte, word, dword or qword element of its source (e.g., zmm2 or memory) and places the results in the destination register (zmm1). This instruction supports memory fault suppression.
72///
73///
74/// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VPOPCNT.html).
75///
76/// Supported operand variants:
77///
78/// ```text
79/// +---+----------+
80/// | # | Operands |
81/// +---+----------+
82/// | 1 | Xmm, Mem |
83/// | 2 | Xmm, Xmm |
84/// | 3 | Ymm, Mem |
85/// | 4 | Ymm, Ymm |
86/// | 5 | Zmm, Mem |
87/// | 6 | Zmm, Zmm |
88/// +---+----------+
89/// ```
90pub trait VpopcntdMaskEmitter<A, B> {
91 fn vpopcntd_mask(&mut self, op0: A, op1: B);
92}
93
94impl<'a> VpopcntdMaskEmitter<Xmm, Xmm> for Assembler<'a> {
95 fn vpopcntd_mask(&mut self, op0: Xmm, op1: Xmm) {
96 self.emit(VPOPCNTD128RR_MASK, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
97 }
98}
99
100impl<'a> VpopcntdMaskEmitter<Xmm, Mem> for Assembler<'a> {
101 fn vpopcntd_mask(&mut self, op0: Xmm, op1: Mem) {
102 self.emit(VPOPCNTD128RM_MASK, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
103 }
104}
105
106impl<'a> VpopcntdMaskEmitter<Ymm, Ymm> for Assembler<'a> {
107 fn vpopcntd_mask(&mut self, op0: Ymm, op1: Ymm) {
108 self.emit(VPOPCNTD256RR_MASK, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
109 }
110}
111
112impl<'a> VpopcntdMaskEmitter<Ymm, Mem> for Assembler<'a> {
113 fn vpopcntd_mask(&mut self, op0: Ymm, op1: Mem) {
114 self.emit(VPOPCNTD256RM_MASK, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
115 }
116}
117
118impl<'a> VpopcntdMaskEmitter<Zmm, Zmm> for Assembler<'a> {
119 fn vpopcntd_mask(&mut self, op0: Zmm, op1: Zmm) {
120 self.emit(VPOPCNTD512RR_MASK, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
121 }
122}
123
124impl<'a> VpopcntdMaskEmitter<Zmm, Mem> for Assembler<'a> {
125 fn vpopcntd_mask(&mut self, op0: Zmm, op1: Mem) {
126 self.emit(VPOPCNTD512RM_MASK, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
127 }
128}
129
130/// `VPOPCNTD_MASKZ` (VPOPCNTD).
131/// This instruction counts the number of bits set to one in each byte, word, dword or qword element of its source (e.g., zmm2 or memory) and places the results in the destination register (zmm1). This instruction supports memory fault suppression.
132///
133///
134/// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VPOPCNT.html).
135///
136/// Supported operand variants:
137///
138/// ```text
139/// +---+----------+
140/// | # | Operands |
141/// +---+----------+
142/// | 1 | Xmm, Mem |
143/// | 2 | Xmm, Xmm |
144/// | 3 | Ymm, Mem |
145/// | 4 | Ymm, Ymm |
146/// | 5 | Zmm, Mem |
147/// | 6 | Zmm, Zmm |
148/// +---+----------+
149/// ```
150pub trait VpopcntdMaskzEmitter<A, B> {
151 fn vpopcntd_maskz(&mut self, op0: A, op1: B);
152}
153
154impl<'a> VpopcntdMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
155 fn vpopcntd_maskz(&mut self, op0: Xmm, op1: Xmm) {
156 self.emit(VPOPCNTD128RR_MASKZ, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
157 }
158}
159
160impl<'a> VpopcntdMaskzEmitter<Xmm, Mem> for Assembler<'a> {
161 fn vpopcntd_maskz(&mut self, op0: Xmm, op1: Mem) {
162 self.emit(VPOPCNTD128RM_MASKZ, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
163 }
164}
165
166impl<'a> VpopcntdMaskzEmitter<Ymm, Ymm> for Assembler<'a> {
167 fn vpopcntd_maskz(&mut self, op0: Ymm, op1: Ymm) {
168 self.emit(VPOPCNTD256RR_MASKZ, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
169 }
170}
171
172impl<'a> VpopcntdMaskzEmitter<Ymm, Mem> for Assembler<'a> {
173 fn vpopcntd_maskz(&mut self, op0: Ymm, op1: Mem) {
174 self.emit(VPOPCNTD256RM_MASKZ, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
175 }
176}
177
178impl<'a> VpopcntdMaskzEmitter<Zmm, Zmm> for Assembler<'a> {
179 fn vpopcntd_maskz(&mut self, op0: Zmm, op1: Zmm) {
180 self.emit(VPOPCNTD512RR_MASKZ, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
181 }
182}
183
184impl<'a> VpopcntdMaskzEmitter<Zmm, Mem> for Assembler<'a> {
185 fn vpopcntd_maskz(&mut self, op0: Zmm, op1: Mem) {
186 self.emit(VPOPCNTD512RM_MASKZ, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
187 }
188}
189
190/// `VPOPCNTQ` (VPOPCNTQ).
191/// This instruction counts the number of bits set to one in each byte, word, dword or qword element of its source (e.g., zmm2 or memory) and places the results in the destination register (zmm1). This instruction supports memory fault suppression.
192///
193///
194/// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VPOPCNT.html).
195///
196/// Supported operand variants:
197///
198/// ```text
199/// +---+----------+
200/// | # | Operands |
201/// +---+----------+
202/// | 1 | Xmm, Mem |
203/// | 2 | Xmm, Xmm |
204/// | 3 | Ymm, Mem |
205/// | 4 | Ymm, Ymm |
206/// | 5 | Zmm, Mem |
207/// | 6 | Zmm, Zmm |
208/// +---+----------+
209/// ```
210pub trait VpopcntqEmitter<A, B> {
211 fn vpopcntq(&mut self, op0: A, op1: B);
212}
213
214impl<'a> VpopcntqEmitter<Xmm, Xmm> for Assembler<'a> {
215 fn vpopcntq(&mut self, op0: Xmm, op1: Xmm) {
216 self.emit(VPOPCNTQ128RR, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
217 }
218}
219
220impl<'a> VpopcntqEmitter<Xmm, Mem> for Assembler<'a> {
221 fn vpopcntq(&mut self, op0: Xmm, op1: Mem) {
222 self.emit(VPOPCNTQ128RM, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
223 }
224}
225
226impl<'a> VpopcntqEmitter<Ymm, Ymm> for Assembler<'a> {
227 fn vpopcntq(&mut self, op0: Ymm, op1: Ymm) {
228 self.emit(VPOPCNTQ256RR, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
229 }
230}
231
232impl<'a> VpopcntqEmitter<Ymm, Mem> for Assembler<'a> {
233 fn vpopcntq(&mut self, op0: Ymm, op1: Mem) {
234 self.emit(VPOPCNTQ256RM, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
235 }
236}
237
238impl<'a> VpopcntqEmitter<Zmm, Zmm> for Assembler<'a> {
239 fn vpopcntq(&mut self, op0: Zmm, op1: Zmm) {
240 self.emit(VPOPCNTQ512RR, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
241 }
242}
243
244impl<'a> VpopcntqEmitter<Zmm, Mem> for Assembler<'a> {
245 fn vpopcntq(&mut self, op0: Zmm, op1: Mem) {
246 self.emit(VPOPCNTQ512RM, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
247 }
248}
249
250/// `VPOPCNTQ_MASK` (VPOPCNTQ).
251/// This instruction counts the number of bits set to one in each byte, word, dword or qword element of its source (e.g., zmm2 or memory) and places the results in the destination register (zmm1). This instruction supports memory fault suppression.
252///
253///
254/// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VPOPCNT.html).
255///
256/// Supported operand variants:
257///
258/// ```text
259/// +---+----------+
260/// | # | Operands |
261/// +---+----------+
262/// | 1 | Xmm, Mem |
263/// | 2 | Xmm, Xmm |
264/// | 3 | Ymm, Mem |
265/// | 4 | Ymm, Ymm |
266/// | 5 | Zmm, Mem |
267/// | 6 | Zmm, Zmm |
268/// +---+----------+
269/// ```
270pub trait VpopcntqMaskEmitter<A, B> {
271 fn vpopcntq_mask(&mut self, op0: A, op1: B);
272}
273
274impl<'a> VpopcntqMaskEmitter<Xmm, Xmm> for Assembler<'a> {
275 fn vpopcntq_mask(&mut self, op0: Xmm, op1: Xmm) {
276 self.emit(VPOPCNTQ128RR_MASK, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
277 }
278}
279
280impl<'a> VpopcntqMaskEmitter<Xmm, Mem> for Assembler<'a> {
281 fn vpopcntq_mask(&mut self, op0: Xmm, op1: Mem) {
282 self.emit(VPOPCNTQ128RM_MASK, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
283 }
284}
285
286impl<'a> VpopcntqMaskEmitter<Ymm, Ymm> for Assembler<'a> {
287 fn vpopcntq_mask(&mut self, op0: Ymm, op1: Ymm) {
288 self.emit(VPOPCNTQ256RR_MASK, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
289 }
290}
291
292impl<'a> VpopcntqMaskEmitter<Ymm, Mem> for Assembler<'a> {
293 fn vpopcntq_mask(&mut self, op0: Ymm, op1: Mem) {
294 self.emit(VPOPCNTQ256RM_MASK, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
295 }
296}
297
298impl<'a> VpopcntqMaskEmitter<Zmm, Zmm> for Assembler<'a> {
299 fn vpopcntq_mask(&mut self, op0: Zmm, op1: Zmm) {
300 self.emit(VPOPCNTQ512RR_MASK, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
301 }
302}
303
304impl<'a> VpopcntqMaskEmitter<Zmm, Mem> for Assembler<'a> {
305 fn vpopcntq_mask(&mut self, op0: Zmm, op1: Mem) {
306 self.emit(VPOPCNTQ512RM_MASK, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
307 }
308}
309
310/// `VPOPCNTQ_MASKZ` (VPOPCNTQ).
311/// This instruction counts the number of bits set to one in each byte, word, dword or qword element of its source (e.g., zmm2 or memory) and places the results in the destination register (zmm1). This instruction supports memory fault suppression.
312///
313///
314/// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VPOPCNT.html).
315///
316/// Supported operand variants:
317///
318/// ```text
319/// +---+----------+
320/// | # | Operands |
321/// +---+----------+
322/// | 1 | Xmm, Mem |
323/// | 2 | Xmm, Xmm |
324/// | 3 | Ymm, Mem |
325/// | 4 | Ymm, Ymm |
326/// | 5 | Zmm, Mem |
327/// | 6 | Zmm, Zmm |
328/// +---+----------+
329/// ```
330pub trait VpopcntqMaskzEmitter<A, B> {
331 fn vpopcntq_maskz(&mut self, op0: A, op1: B);
332}
333
334impl<'a> VpopcntqMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
335 fn vpopcntq_maskz(&mut self, op0: Xmm, op1: Xmm) {
336 self.emit(VPOPCNTQ128RR_MASKZ, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
337 }
338}
339
340impl<'a> VpopcntqMaskzEmitter<Xmm, Mem> for Assembler<'a> {
341 fn vpopcntq_maskz(&mut self, op0: Xmm, op1: Mem) {
342 self.emit(VPOPCNTQ128RM_MASKZ, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
343 }
344}
345
346impl<'a> VpopcntqMaskzEmitter<Ymm, Ymm> for Assembler<'a> {
347 fn vpopcntq_maskz(&mut self, op0: Ymm, op1: Ymm) {
348 self.emit(VPOPCNTQ256RR_MASKZ, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
349 }
350}
351
352impl<'a> VpopcntqMaskzEmitter<Ymm, Mem> for Assembler<'a> {
353 fn vpopcntq_maskz(&mut self, op0: Ymm, op1: Mem) {
354 self.emit(VPOPCNTQ256RM_MASKZ, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
355 }
356}
357
358impl<'a> VpopcntqMaskzEmitter<Zmm, Zmm> for Assembler<'a> {
359 fn vpopcntq_maskz(&mut self, op0: Zmm, op1: Zmm) {
360 self.emit(VPOPCNTQ512RR_MASKZ, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
361 }
362}
363
364impl<'a> VpopcntqMaskzEmitter<Zmm, Mem> for Assembler<'a> {
365 fn vpopcntq_maskz(&mut self, op0: Zmm, op1: Mem) {
366 self.emit(VPOPCNTQ512RM_MASKZ, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
367 }
368}
369
370
371impl<'a> Assembler<'a> {
372 /// `VPOPCNTD` (VPOPCNTD).
373 /// This instruction counts the number of bits set to one in each byte, word, dword or qword element of its source (e.g., zmm2 or memory) and places the results in the destination register (zmm1). This instruction supports memory fault suppression.
374 ///
375 ///
376 /// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VPOPCNT.html).
377 ///
378 /// Supported operand variants:
379 ///
380 /// ```text
381 /// +---+----------+
382 /// | # | Operands |
383 /// +---+----------+
384 /// | 1 | Xmm, Mem |
385 /// | 2 | Xmm, Xmm |
386 /// | 3 | Ymm, Mem |
387 /// | 4 | Ymm, Ymm |
388 /// | 5 | Zmm, Mem |
389 /// | 6 | Zmm, Zmm |
390 /// +---+----------+
391 /// ```
392 #[inline]
393 pub fn vpopcntd<A, B>(&mut self, op0: A, op1: B)
394 where Assembler<'a>: VpopcntdEmitter<A, B> {
395 <Self as VpopcntdEmitter<A, B>>::vpopcntd(self, op0, op1);
396 }
397 /// `VPOPCNTD_MASK` (VPOPCNTD).
398 /// This instruction counts the number of bits set to one in each byte, word, dword or qword element of its source (e.g., zmm2 or memory) and places the results in the destination register (zmm1). This instruction supports memory fault suppression.
399 ///
400 ///
401 /// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VPOPCNT.html).
402 ///
403 /// Supported operand variants:
404 ///
405 /// ```text
406 /// +---+----------+
407 /// | # | Operands |
408 /// +---+----------+
409 /// | 1 | Xmm, Mem |
410 /// | 2 | Xmm, Xmm |
411 /// | 3 | Ymm, Mem |
412 /// | 4 | Ymm, Ymm |
413 /// | 5 | Zmm, Mem |
414 /// | 6 | Zmm, Zmm |
415 /// +---+----------+
416 /// ```
417 #[inline]
418 pub fn vpopcntd_mask<A, B>(&mut self, op0: A, op1: B)
419 where Assembler<'a>: VpopcntdMaskEmitter<A, B> {
420 <Self as VpopcntdMaskEmitter<A, B>>::vpopcntd_mask(self, op0, op1);
421 }
422 /// `VPOPCNTD_MASKZ` (VPOPCNTD).
423 /// This instruction counts the number of bits set to one in each byte, word, dword or qword element of its source (e.g., zmm2 or memory) and places the results in the destination register (zmm1). This instruction supports memory fault suppression.
424 ///
425 ///
426 /// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VPOPCNT.html).
427 ///
428 /// Supported operand variants:
429 ///
430 /// ```text
431 /// +---+----------+
432 /// | # | Operands |
433 /// +---+----------+
434 /// | 1 | Xmm, Mem |
435 /// | 2 | Xmm, Xmm |
436 /// | 3 | Ymm, Mem |
437 /// | 4 | Ymm, Ymm |
438 /// | 5 | Zmm, Mem |
439 /// | 6 | Zmm, Zmm |
440 /// +---+----------+
441 /// ```
442 #[inline]
443 pub fn vpopcntd_maskz<A, B>(&mut self, op0: A, op1: B)
444 where Assembler<'a>: VpopcntdMaskzEmitter<A, B> {
445 <Self as VpopcntdMaskzEmitter<A, B>>::vpopcntd_maskz(self, op0, op1);
446 }
447 /// `VPOPCNTQ` (VPOPCNTQ).
448 /// This instruction counts the number of bits set to one in each byte, word, dword or qword element of its source (e.g., zmm2 or memory) and places the results in the destination register (zmm1). This instruction supports memory fault suppression.
449 ///
450 ///
451 /// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VPOPCNT.html).
452 ///
453 /// Supported operand variants:
454 ///
455 /// ```text
456 /// +---+----------+
457 /// | # | Operands |
458 /// +---+----------+
459 /// | 1 | Xmm, Mem |
460 /// | 2 | Xmm, Xmm |
461 /// | 3 | Ymm, Mem |
462 /// | 4 | Ymm, Ymm |
463 /// | 5 | Zmm, Mem |
464 /// | 6 | Zmm, Zmm |
465 /// +---+----------+
466 /// ```
467 #[inline]
468 pub fn vpopcntq<A, B>(&mut self, op0: A, op1: B)
469 where Assembler<'a>: VpopcntqEmitter<A, B> {
470 <Self as VpopcntqEmitter<A, B>>::vpopcntq(self, op0, op1);
471 }
472 /// `VPOPCNTQ_MASK` (VPOPCNTQ).
473 /// This instruction counts the number of bits set to one in each byte, word, dword or qword element of its source (e.g., zmm2 or memory) and places the results in the destination register (zmm1). This instruction supports memory fault suppression.
474 ///
475 ///
476 /// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VPOPCNT.html).
477 ///
478 /// Supported operand variants:
479 ///
480 /// ```text
481 /// +---+----------+
482 /// | # | Operands |
483 /// +---+----------+
484 /// | 1 | Xmm, Mem |
485 /// | 2 | Xmm, Xmm |
486 /// | 3 | Ymm, Mem |
487 /// | 4 | Ymm, Ymm |
488 /// | 5 | Zmm, Mem |
489 /// | 6 | Zmm, Zmm |
490 /// +---+----------+
491 /// ```
492 #[inline]
493 pub fn vpopcntq_mask<A, B>(&mut self, op0: A, op1: B)
494 where Assembler<'a>: VpopcntqMaskEmitter<A, B> {
495 <Self as VpopcntqMaskEmitter<A, B>>::vpopcntq_mask(self, op0, op1);
496 }
497 /// `VPOPCNTQ_MASKZ` (VPOPCNTQ).
498 /// This instruction counts the number of bits set to one in each byte, word, dword or qword element of its source (e.g., zmm2 or memory) and places the results in the destination register (zmm1). This instruction supports memory fault suppression.
499 ///
500 ///
501 /// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VPOPCNT.html).
502 ///
503 /// Supported operand variants:
504 ///
505 /// ```text
506 /// +---+----------+
507 /// | # | Operands |
508 /// +---+----------+
509 /// | 1 | Xmm, Mem |
510 /// | 2 | Xmm, Xmm |
511 /// | 3 | Ymm, Mem |
512 /// | 4 | Ymm, Ymm |
513 /// | 5 | Zmm, Mem |
514 /// | 6 | Zmm, Zmm |
515 /// +---+----------+
516 /// ```
517 #[inline]
518 pub fn vpopcntq_maskz<A, B>(&mut self, op0: A, op1: B)
519 where Assembler<'a>: VpopcntqMaskzEmitter<A, B> {
520 <Self as VpopcntqMaskzEmitter<A, B>>::vpopcntq_maskz(self, op0, op1);
521 }
522}