asmkit/x86/features/
AVX512_VNNI.rs

1use crate::x86::assembler::*;
2use crate::x86::operands::*;
3use super::super::opcodes::*;
4use crate::core::emitter::*;
5use crate::core::operand::*;
6
7/// A dummy operand that represents no register. Here just for simplicity.
8const NOREG: Operand = Operand::new();
9
10/// `VPDPBUSD` (VPDPBUSD). 
11/// Multiplies the individual unsigned bytes of the first source operand by the corresponding signed bytes of the second source operand, producing intermediate signed word results. The word results are then summed and accumulated in the destination dword element size operand.
12///
13///
14/// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VPDPBUSD.html).
15///
16/// Supported operand variants:
17///
18/// ```text
19/// +---+---------------+
20/// | # | Operands      |
21/// +---+---------------+
22/// | 1 | Xmm, Xmm, Mem |
23/// | 2 | Xmm, Xmm, Xmm |
24/// | 3 | Ymm, Ymm, Mem |
25/// | 4 | Ymm, Ymm, Ymm |
26/// | 5 | Zmm, Zmm, Mem |
27/// | 6 | Zmm, Zmm, Zmm |
28/// +---+---------------+
29/// ```
30pub trait VpdpbusdEmitter<A, B, C> {
31    fn vpdpbusd(&mut self, op0: A, op1: B, op2: C);
32}
33
34impl<'a> VpdpbusdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
35    fn vpdpbusd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
36        self.emit(VPDPBUSD128RRR, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
37    }
38}
39
40impl<'a> VpdpbusdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
41    fn vpdpbusd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
42        self.emit(VPDPBUSD128RRM, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
43    }
44}
45
46impl<'a> VpdpbusdEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
47    fn vpdpbusd(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
48        self.emit(VPDPBUSD256RRR, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
49    }
50}
51
52impl<'a> VpdpbusdEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
53    fn vpdpbusd(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
54        self.emit(VPDPBUSD256RRM, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
55    }
56}
57
58impl<'a> VpdpbusdEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
59    fn vpdpbusd(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
60        self.emit(VPDPBUSD512RRR, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
61    }
62}
63
64impl<'a> VpdpbusdEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
65    fn vpdpbusd(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
66        self.emit(VPDPBUSD512RRM, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
67    }
68}
69
70/// `VPDPBUSDS` (VPDPBUSDS). 
71/// Multiplies the individual unsigned bytes of the first source operand by the corresponding signed bytes of the second source operand, producing intermediate signed word results. The word results are then summed and accumulated in the destination dword element size operand. If the intermediate sum overflows a 32b signed number the result is saturated to either 0x7FFF_FFFF for positive numbers of 0x8000_0000 for negative numbers.
72///
73///
74/// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VPDPBUSDS.html).
75///
76/// Supported operand variants:
77///
78/// ```text
79/// +---+---------------+
80/// | # | Operands      |
81/// +---+---------------+
82/// | 1 | Xmm, Xmm, Mem |
83/// | 2 | Xmm, Xmm, Xmm |
84/// | 3 | Ymm, Ymm, Mem |
85/// | 4 | Ymm, Ymm, Ymm |
86/// | 5 | Zmm, Zmm, Mem |
87/// | 6 | Zmm, Zmm, Zmm |
88/// +---+---------------+
89/// ```
90pub trait VpdpbusdsEmitter<A, B, C> {
91    fn vpdpbusds(&mut self, op0: A, op1: B, op2: C);
92}
93
94impl<'a> VpdpbusdsEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
95    fn vpdpbusds(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
96        self.emit(VPDPBUSDS128RRR, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
97    }
98}
99
100impl<'a> VpdpbusdsEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
101    fn vpdpbusds(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
102        self.emit(VPDPBUSDS128RRM, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
103    }
104}
105
106impl<'a> VpdpbusdsEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
107    fn vpdpbusds(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
108        self.emit(VPDPBUSDS256RRR, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
109    }
110}
111
112impl<'a> VpdpbusdsEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
113    fn vpdpbusds(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
114        self.emit(VPDPBUSDS256RRM, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
115    }
116}
117
118impl<'a> VpdpbusdsEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
119    fn vpdpbusds(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
120        self.emit(VPDPBUSDS512RRR, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
121    }
122}
123
124impl<'a> VpdpbusdsEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
125    fn vpdpbusds(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
126        self.emit(VPDPBUSDS512RRM, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
127    }
128}
129
130/// `VPDPBUSDS_MASK` (VPDPBUSDS). 
131/// Multiplies the individual unsigned bytes of the first source operand by the corresponding signed bytes of the second source operand, producing intermediate signed word results. The word results are then summed and accumulated in the destination dword element size operand. If the intermediate sum overflows a 32b signed number the result is saturated to either 0x7FFF_FFFF for positive numbers of 0x8000_0000 for negative numbers.
132///
133///
134/// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VPDPBUSDS.html).
135///
136/// Supported operand variants:
137///
138/// ```text
139/// +---+---------------+
140/// | # | Operands      |
141/// +---+---------------+
142/// | 1 | Xmm, Xmm, Mem |
143/// | 2 | Xmm, Xmm, Xmm |
144/// | 3 | Ymm, Ymm, Mem |
145/// | 4 | Ymm, Ymm, Ymm |
146/// | 5 | Zmm, Zmm, Mem |
147/// | 6 | Zmm, Zmm, Zmm |
148/// +---+---------------+
149/// ```
150pub trait VpdpbusdsMaskEmitter<A, B, C> {
151    fn vpdpbusds_mask(&mut self, op0: A, op1: B, op2: C);
152}
153
154impl<'a> VpdpbusdsMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
155    fn vpdpbusds_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
156        self.emit(VPDPBUSDS128RRR_MASK, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
157    }
158}
159
160impl<'a> VpdpbusdsMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
161    fn vpdpbusds_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
162        self.emit(VPDPBUSDS128RRM_MASK, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
163    }
164}
165
166impl<'a> VpdpbusdsMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
167    fn vpdpbusds_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
168        self.emit(VPDPBUSDS256RRR_MASK, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
169    }
170}
171
172impl<'a> VpdpbusdsMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
173    fn vpdpbusds_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
174        self.emit(VPDPBUSDS256RRM_MASK, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
175    }
176}
177
178impl<'a> VpdpbusdsMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
179    fn vpdpbusds_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
180        self.emit(VPDPBUSDS512RRR_MASK, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
181    }
182}
183
184impl<'a> VpdpbusdsMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
185    fn vpdpbusds_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
186        self.emit(VPDPBUSDS512RRM_MASK, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
187    }
188}
189
190/// `VPDPBUSDS_MASKZ` (VPDPBUSDS). 
191/// Multiplies the individual unsigned bytes of the first source operand by the corresponding signed bytes of the second source operand, producing intermediate signed word results. The word results are then summed and accumulated in the destination dword element size operand. If the intermediate sum overflows a 32b signed number the result is saturated to either 0x7FFF_FFFF for positive numbers of 0x8000_0000 for negative numbers.
192///
193///
194/// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VPDPBUSDS.html).
195///
196/// Supported operand variants:
197///
198/// ```text
199/// +---+---------------+
200/// | # | Operands      |
201/// +---+---------------+
202/// | 1 | Xmm, Xmm, Mem |
203/// | 2 | Xmm, Xmm, Xmm |
204/// | 3 | Ymm, Ymm, Mem |
205/// | 4 | Ymm, Ymm, Ymm |
206/// | 5 | Zmm, Zmm, Mem |
207/// | 6 | Zmm, Zmm, Zmm |
208/// +---+---------------+
209/// ```
210pub trait VpdpbusdsMaskzEmitter<A, B, C> {
211    fn vpdpbusds_maskz(&mut self, op0: A, op1: B, op2: C);
212}
213
214impl<'a> VpdpbusdsMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
215    fn vpdpbusds_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
216        self.emit(VPDPBUSDS128RRR_MASKZ, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
217    }
218}
219
220impl<'a> VpdpbusdsMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
221    fn vpdpbusds_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
222        self.emit(VPDPBUSDS128RRM_MASKZ, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
223    }
224}
225
226impl<'a> VpdpbusdsMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
227    fn vpdpbusds_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
228        self.emit(VPDPBUSDS256RRR_MASKZ, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
229    }
230}
231
232impl<'a> VpdpbusdsMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
233    fn vpdpbusds_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
234        self.emit(VPDPBUSDS256RRM_MASKZ, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
235    }
236}
237
238impl<'a> VpdpbusdsMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
239    fn vpdpbusds_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
240        self.emit(VPDPBUSDS512RRR_MASKZ, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
241    }
242}
243
244impl<'a> VpdpbusdsMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
245    fn vpdpbusds_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
246        self.emit(VPDPBUSDS512RRM_MASKZ, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
247    }
248}
249
250/// `VPDPBUSD_MASK` (VPDPBUSD). 
251/// Multiplies the individual unsigned bytes of the first source operand by the corresponding signed bytes of the second source operand, producing intermediate signed word results. The word results are then summed and accumulated in the destination dword element size operand.
252///
253///
254/// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VPDPBUSD.html).
255///
256/// Supported operand variants:
257///
258/// ```text
259/// +---+---------------+
260/// | # | Operands      |
261/// +---+---------------+
262/// | 1 | Xmm, Xmm, Mem |
263/// | 2 | Xmm, Xmm, Xmm |
264/// | 3 | Ymm, Ymm, Mem |
265/// | 4 | Ymm, Ymm, Ymm |
266/// | 5 | Zmm, Zmm, Mem |
267/// | 6 | Zmm, Zmm, Zmm |
268/// +---+---------------+
269/// ```
270pub trait VpdpbusdMaskEmitter<A, B, C> {
271    fn vpdpbusd_mask(&mut self, op0: A, op1: B, op2: C);
272}
273
274impl<'a> VpdpbusdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
275    fn vpdpbusd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
276        self.emit(VPDPBUSD128RRR_MASK, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
277    }
278}
279
280impl<'a> VpdpbusdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
281    fn vpdpbusd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
282        self.emit(VPDPBUSD128RRM_MASK, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
283    }
284}
285
286impl<'a> VpdpbusdMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
287    fn vpdpbusd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
288        self.emit(VPDPBUSD256RRR_MASK, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
289    }
290}
291
292impl<'a> VpdpbusdMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
293    fn vpdpbusd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
294        self.emit(VPDPBUSD256RRM_MASK, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
295    }
296}
297
298impl<'a> VpdpbusdMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
299    fn vpdpbusd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
300        self.emit(VPDPBUSD512RRR_MASK, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
301    }
302}
303
304impl<'a> VpdpbusdMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
305    fn vpdpbusd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
306        self.emit(VPDPBUSD512RRM_MASK, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
307    }
308}
309
310/// `VPDPBUSD_MASKZ` (VPDPBUSD). 
311/// Multiplies the individual unsigned bytes of the first source operand by the corresponding signed bytes of the second source operand, producing intermediate signed word results. The word results are then summed and accumulated in the destination dword element size operand.
312///
313///
314/// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VPDPBUSD.html).
315///
316/// Supported operand variants:
317///
318/// ```text
319/// +---+---------------+
320/// | # | Operands      |
321/// +---+---------------+
322/// | 1 | Xmm, Xmm, Mem |
323/// | 2 | Xmm, Xmm, Xmm |
324/// | 3 | Ymm, Ymm, Mem |
325/// | 4 | Ymm, Ymm, Ymm |
326/// | 5 | Zmm, Zmm, Mem |
327/// | 6 | Zmm, Zmm, Zmm |
328/// +---+---------------+
329/// ```
330pub trait VpdpbusdMaskzEmitter<A, B, C> {
331    fn vpdpbusd_maskz(&mut self, op0: A, op1: B, op2: C);
332}
333
334impl<'a> VpdpbusdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
335    fn vpdpbusd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
336        self.emit(VPDPBUSD128RRR_MASKZ, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
337    }
338}
339
340impl<'a> VpdpbusdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
341    fn vpdpbusd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
342        self.emit(VPDPBUSD128RRM_MASKZ, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
343    }
344}
345
346impl<'a> VpdpbusdMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
347    fn vpdpbusd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
348        self.emit(VPDPBUSD256RRR_MASKZ, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
349    }
350}
351
352impl<'a> VpdpbusdMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
353    fn vpdpbusd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
354        self.emit(VPDPBUSD256RRM_MASKZ, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
355    }
356}
357
358impl<'a> VpdpbusdMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
359    fn vpdpbusd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
360        self.emit(VPDPBUSD512RRR_MASKZ, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
361    }
362}
363
364impl<'a> VpdpbusdMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
365    fn vpdpbusd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
366        self.emit(VPDPBUSD512RRM_MASKZ, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
367    }
368}
369
370/// `VPDPWSSD` (VPDPWSSD). 
371/// Multiplies the individual signed words of the first source operand by the corresponding signed words of the second source operand, producing intermediate signed, doubleword results. The adjacent doubleword results are then summed and accumulated in the destination operand.
372///
373///
374/// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VPDPWSSD.html).
375///
376/// Supported operand variants:
377///
378/// ```text
379/// +---+---------------+
380/// | # | Operands      |
381/// +---+---------------+
382/// | 1 | Xmm, Xmm, Mem |
383/// | 2 | Xmm, Xmm, Xmm |
384/// | 3 | Ymm, Ymm, Mem |
385/// | 4 | Ymm, Ymm, Ymm |
386/// | 5 | Zmm, Zmm, Mem |
387/// | 6 | Zmm, Zmm, Zmm |
388/// +---+---------------+
389/// ```
390pub trait VpdpwssdEmitter<A, B, C> {
391    fn vpdpwssd(&mut self, op0: A, op1: B, op2: C);
392}
393
394impl<'a> VpdpwssdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
395    fn vpdpwssd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
396        self.emit(VPDPWSSD128RRR, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
397    }
398}
399
400impl<'a> VpdpwssdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
401    fn vpdpwssd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
402        self.emit(VPDPWSSD128RRM, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
403    }
404}
405
406impl<'a> VpdpwssdEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
407    fn vpdpwssd(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
408        self.emit(VPDPWSSD256RRR, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
409    }
410}
411
412impl<'a> VpdpwssdEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
413    fn vpdpwssd(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
414        self.emit(VPDPWSSD256RRM, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
415    }
416}
417
418impl<'a> VpdpwssdEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
419    fn vpdpwssd(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
420        self.emit(VPDPWSSD512RRR, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
421    }
422}
423
424impl<'a> VpdpwssdEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
425    fn vpdpwssd(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
426        self.emit(VPDPWSSD512RRM, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
427    }
428}
429
430/// `VPDPWSSDS` (VPDPWSSDS). 
431/// Multiplies the individual signed words of the first source operand by the corresponding signed words of the second source operand, producing intermediate signed, doubleword results. The adjacent doubleword results are then summed and accumulated in the destination operand. If the intermediate sum overflows a 32b signed number, the result is saturated to either 0x7FFF_FFFF for positive numbers of 0x8000_0000 for negative numbers.
432///
433///
434/// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VPDPWSSDS.html).
435///
436/// Supported operand variants:
437///
438/// ```text
439/// +---+---------------+
440/// | # | Operands      |
441/// +---+---------------+
442/// | 1 | Xmm, Xmm, Mem |
443/// | 2 | Xmm, Xmm, Xmm |
444/// | 3 | Ymm, Ymm, Mem |
445/// | 4 | Ymm, Ymm, Ymm |
446/// | 5 | Zmm, Zmm, Mem |
447/// | 6 | Zmm, Zmm, Zmm |
448/// +---+---------------+
449/// ```
450pub trait VpdpwssdsEmitter<A, B, C> {
451    fn vpdpwssds(&mut self, op0: A, op1: B, op2: C);
452}
453
454impl<'a> VpdpwssdsEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
455    fn vpdpwssds(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
456        self.emit(VPDPWSSDS128RRR, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
457    }
458}
459
460impl<'a> VpdpwssdsEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
461    fn vpdpwssds(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
462        self.emit(VPDPWSSDS128RRM, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
463    }
464}
465
466impl<'a> VpdpwssdsEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
467    fn vpdpwssds(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
468        self.emit(VPDPWSSDS256RRR, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
469    }
470}
471
472impl<'a> VpdpwssdsEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
473    fn vpdpwssds(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
474        self.emit(VPDPWSSDS256RRM, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
475    }
476}
477
478impl<'a> VpdpwssdsEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
479    fn vpdpwssds(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
480        self.emit(VPDPWSSDS512RRR, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
481    }
482}
483
484impl<'a> VpdpwssdsEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
485    fn vpdpwssds(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
486        self.emit(VPDPWSSDS512RRM, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
487    }
488}
489
490/// `VPDPWSSDS_MASK` (VPDPWSSDS). 
491/// Multiplies the individual signed words of the first source operand by the corresponding signed words of the second source operand, producing intermediate signed, doubleword results. The adjacent doubleword results are then summed and accumulated in the destination operand. If the intermediate sum overflows a 32b signed number, the result is saturated to either 0x7FFF_FFFF for positive numbers of 0x8000_0000 for negative numbers.
492///
493///
494/// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VPDPWSSDS.html).
495///
496/// Supported operand variants:
497///
498/// ```text
499/// +---+---------------+
500/// | # | Operands      |
501/// +---+---------------+
502/// | 1 | Xmm, Xmm, Mem |
503/// | 2 | Xmm, Xmm, Xmm |
504/// | 3 | Ymm, Ymm, Mem |
505/// | 4 | Ymm, Ymm, Ymm |
506/// | 5 | Zmm, Zmm, Mem |
507/// | 6 | Zmm, Zmm, Zmm |
508/// +---+---------------+
509/// ```
510pub trait VpdpwssdsMaskEmitter<A, B, C> {
511    fn vpdpwssds_mask(&mut self, op0: A, op1: B, op2: C);
512}
513
514impl<'a> VpdpwssdsMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
515    fn vpdpwssds_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
516        self.emit(VPDPWSSDS128RRR_MASK, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
517    }
518}
519
520impl<'a> VpdpwssdsMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
521    fn vpdpwssds_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
522        self.emit(VPDPWSSDS128RRM_MASK, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
523    }
524}
525
526impl<'a> VpdpwssdsMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
527    fn vpdpwssds_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
528        self.emit(VPDPWSSDS256RRR_MASK, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
529    }
530}
531
532impl<'a> VpdpwssdsMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
533    fn vpdpwssds_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
534        self.emit(VPDPWSSDS256RRM_MASK, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
535    }
536}
537
538impl<'a> VpdpwssdsMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
539    fn vpdpwssds_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
540        self.emit(VPDPWSSDS512RRR_MASK, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
541    }
542}
543
544impl<'a> VpdpwssdsMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
545    fn vpdpwssds_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
546        self.emit(VPDPWSSDS512RRM_MASK, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
547    }
548}
549
550/// `VPDPWSSDS_MASKZ` (VPDPWSSDS). 
551/// Multiplies the individual signed words of the first source operand by the corresponding signed words of the second source operand, producing intermediate signed, doubleword results. The adjacent doubleword results are then summed and accumulated in the destination operand. If the intermediate sum overflows a 32b signed number, the result is saturated to either 0x7FFF_FFFF for positive numbers of 0x8000_0000 for negative numbers.
552///
553///
554/// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VPDPWSSDS.html).
555///
556/// Supported operand variants:
557///
558/// ```text
559/// +---+---------------+
560/// | # | Operands      |
561/// +---+---------------+
562/// | 1 | Xmm, Xmm, Mem |
563/// | 2 | Xmm, Xmm, Xmm |
564/// | 3 | Ymm, Ymm, Mem |
565/// | 4 | Ymm, Ymm, Ymm |
566/// | 5 | Zmm, Zmm, Mem |
567/// | 6 | Zmm, Zmm, Zmm |
568/// +---+---------------+
569/// ```
570pub trait VpdpwssdsMaskzEmitter<A, B, C> {
571    fn vpdpwssds_maskz(&mut self, op0: A, op1: B, op2: C);
572}
573
574impl<'a> VpdpwssdsMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
575    fn vpdpwssds_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
576        self.emit(VPDPWSSDS128RRR_MASKZ, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
577    }
578}
579
580impl<'a> VpdpwssdsMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
581    fn vpdpwssds_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
582        self.emit(VPDPWSSDS128RRM_MASKZ, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
583    }
584}
585
586impl<'a> VpdpwssdsMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
587    fn vpdpwssds_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
588        self.emit(VPDPWSSDS256RRR_MASKZ, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
589    }
590}
591
592impl<'a> VpdpwssdsMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
593    fn vpdpwssds_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
594        self.emit(VPDPWSSDS256RRM_MASKZ, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
595    }
596}
597
598impl<'a> VpdpwssdsMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
599    fn vpdpwssds_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
600        self.emit(VPDPWSSDS512RRR_MASKZ, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
601    }
602}
603
604impl<'a> VpdpwssdsMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
605    fn vpdpwssds_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
606        self.emit(VPDPWSSDS512RRM_MASKZ, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
607    }
608}
609
610/// `VPDPWSSD_MASK` (VPDPWSSD). 
611/// Multiplies the individual signed words of the first source operand by the corresponding signed words of the second source operand, producing intermediate signed, doubleword results. The adjacent doubleword results are then summed and accumulated in the destination operand.
612///
613///
614/// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VPDPWSSD.html).
615///
616/// Supported operand variants:
617///
618/// ```text
619/// +---+---------------+
620/// | # | Operands      |
621/// +---+---------------+
622/// | 1 | Xmm, Xmm, Mem |
623/// | 2 | Xmm, Xmm, Xmm |
624/// | 3 | Ymm, Ymm, Mem |
625/// | 4 | Ymm, Ymm, Ymm |
626/// | 5 | Zmm, Zmm, Mem |
627/// | 6 | Zmm, Zmm, Zmm |
628/// +---+---------------+
629/// ```
630pub trait VpdpwssdMaskEmitter<A, B, C> {
631    fn vpdpwssd_mask(&mut self, op0: A, op1: B, op2: C);
632}
633
634impl<'a> VpdpwssdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
635    fn vpdpwssd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
636        self.emit(VPDPWSSD128RRR_MASK, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
637    }
638}
639
640impl<'a> VpdpwssdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
641    fn vpdpwssd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
642        self.emit(VPDPWSSD128RRM_MASK, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
643    }
644}
645
646impl<'a> VpdpwssdMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
647    fn vpdpwssd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
648        self.emit(VPDPWSSD256RRR_MASK, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
649    }
650}
651
652impl<'a> VpdpwssdMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
653    fn vpdpwssd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
654        self.emit(VPDPWSSD256RRM_MASK, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
655    }
656}
657
658impl<'a> VpdpwssdMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
659    fn vpdpwssd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
660        self.emit(VPDPWSSD512RRR_MASK, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
661    }
662}
663
664impl<'a> VpdpwssdMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
665    fn vpdpwssd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
666        self.emit(VPDPWSSD512RRM_MASK, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
667    }
668}
669
670/// `VPDPWSSD_MASKZ` (VPDPWSSD). 
671/// Multiplies the individual signed words of the first source operand by the corresponding signed words of the second source operand, producing intermediate signed, doubleword results. The adjacent doubleword results are then summed and accumulated in the destination operand.
672///
673///
674/// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VPDPWSSD.html).
675///
676/// Supported operand variants:
677///
678/// ```text
679/// +---+---------------+
680/// | # | Operands      |
681/// +---+---------------+
682/// | 1 | Xmm, Xmm, Mem |
683/// | 2 | Xmm, Xmm, Xmm |
684/// | 3 | Ymm, Ymm, Mem |
685/// | 4 | Ymm, Ymm, Ymm |
686/// | 5 | Zmm, Zmm, Mem |
687/// | 6 | Zmm, Zmm, Zmm |
688/// +---+---------------+
689/// ```
690pub trait VpdpwssdMaskzEmitter<A, B, C> {
691    fn vpdpwssd_maskz(&mut self, op0: A, op1: B, op2: C);
692}
693
694impl<'a> VpdpwssdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
695    fn vpdpwssd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
696        self.emit(VPDPWSSD128RRR_MASKZ, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
697    }
698}
699
700impl<'a> VpdpwssdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
701    fn vpdpwssd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
702        self.emit(VPDPWSSD128RRM_MASKZ, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
703    }
704}
705
706impl<'a> VpdpwssdMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
707    fn vpdpwssd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
708        self.emit(VPDPWSSD256RRR_MASKZ, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
709    }
710}
711
712impl<'a> VpdpwssdMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
713    fn vpdpwssd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
714        self.emit(VPDPWSSD256RRM_MASKZ, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
715    }
716}
717
718impl<'a> VpdpwssdMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
719    fn vpdpwssd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
720        self.emit(VPDPWSSD512RRR_MASKZ, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
721    }
722}
723
724impl<'a> VpdpwssdMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
725    fn vpdpwssd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
726        self.emit(VPDPWSSD512RRM_MASKZ, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
727    }
728}
729
730
731impl<'a> Assembler<'a> {
732    /// `VPDPBUSD` (VPDPBUSD). 
733    /// Multiplies the individual unsigned bytes of the first source operand by the corresponding signed bytes of the second source operand, producing intermediate signed word results. The word results are then summed and accumulated in the destination dword element size operand.
734    ///
735    ///
736    /// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VPDPBUSD.html).
737    ///
738    /// Supported operand variants:
739    ///
740    /// ```text
741    /// +---+---------------+
742    /// | # | Operands      |
743    /// +---+---------------+
744    /// | 1 | Xmm, Xmm, Mem |
745    /// | 2 | Xmm, Xmm, Xmm |
746    /// | 3 | Ymm, Ymm, Mem |
747    /// | 4 | Ymm, Ymm, Ymm |
748    /// | 5 | Zmm, Zmm, Mem |
749    /// | 6 | Zmm, Zmm, Zmm |
750    /// +---+---------------+
751    /// ```
752    #[inline]
753    pub fn vpdpbusd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
754    where Assembler<'a>: VpdpbusdEmitter<A, B, C> {
755        <Self as VpdpbusdEmitter<A, B, C>>::vpdpbusd(self, op0, op1, op2);
756    }
757    /// `VPDPBUSDS` (VPDPBUSDS). 
758    /// Multiplies the individual unsigned bytes of the first source operand by the corresponding signed bytes of the second source operand, producing intermediate signed word results. The word results are then summed and accumulated in the destination dword element size operand. If the intermediate sum overflows a 32b signed number the result is saturated to either 0x7FFF_FFFF for positive numbers of 0x8000_0000 for negative numbers.
759    ///
760    ///
761    /// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VPDPBUSDS.html).
762    ///
763    /// Supported operand variants:
764    ///
765    /// ```text
766    /// +---+---------------+
767    /// | # | Operands      |
768    /// +---+---------------+
769    /// | 1 | Xmm, Xmm, Mem |
770    /// | 2 | Xmm, Xmm, Xmm |
771    /// | 3 | Ymm, Ymm, Mem |
772    /// | 4 | Ymm, Ymm, Ymm |
773    /// | 5 | Zmm, Zmm, Mem |
774    /// | 6 | Zmm, Zmm, Zmm |
775    /// +---+---------------+
776    /// ```
777    #[inline]
778    pub fn vpdpbusds<A, B, C>(&mut self, op0: A, op1: B, op2: C)
779    where Assembler<'a>: VpdpbusdsEmitter<A, B, C> {
780        <Self as VpdpbusdsEmitter<A, B, C>>::vpdpbusds(self, op0, op1, op2);
781    }
782    /// `VPDPBUSDS_MASK` (VPDPBUSDS). 
783    /// Multiplies the individual unsigned bytes of the first source operand by the corresponding signed bytes of the second source operand, producing intermediate signed word results. The word results are then summed and accumulated in the destination dword element size operand. If the intermediate sum overflows a 32b signed number the result is saturated to either 0x7FFF_FFFF for positive numbers of 0x8000_0000 for negative numbers.
784    ///
785    ///
786    /// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VPDPBUSDS.html).
787    ///
788    /// Supported operand variants:
789    ///
790    /// ```text
791    /// +---+---------------+
792    /// | # | Operands      |
793    /// +---+---------------+
794    /// | 1 | Xmm, Xmm, Mem |
795    /// | 2 | Xmm, Xmm, Xmm |
796    /// | 3 | Ymm, Ymm, Mem |
797    /// | 4 | Ymm, Ymm, Ymm |
798    /// | 5 | Zmm, Zmm, Mem |
799    /// | 6 | Zmm, Zmm, Zmm |
800    /// +---+---------------+
801    /// ```
802    #[inline]
803    pub fn vpdpbusds_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
804    where Assembler<'a>: VpdpbusdsMaskEmitter<A, B, C> {
805        <Self as VpdpbusdsMaskEmitter<A, B, C>>::vpdpbusds_mask(self, op0, op1, op2);
806    }
807    /// `VPDPBUSDS_MASKZ` (VPDPBUSDS). 
808    /// Multiplies the individual unsigned bytes of the first source operand by the corresponding signed bytes of the second source operand, producing intermediate signed word results. The word results are then summed and accumulated in the destination dword element size operand. If the intermediate sum overflows a 32b signed number the result is saturated to either 0x7FFF_FFFF for positive numbers of 0x8000_0000 for negative numbers.
809    ///
810    ///
811    /// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VPDPBUSDS.html).
812    ///
813    /// Supported operand variants:
814    ///
815    /// ```text
816    /// +---+---------------+
817    /// | # | Operands      |
818    /// +---+---------------+
819    /// | 1 | Xmm, Xmm, Mem |
820    /// | 2 | Xmm, Xmm, Xmm |
821    /// | 3 | Ymm, Ymm, Mem |
822    /// | 4 | Ymm, Ymm, Ymm |
823    /// | 5 | Zmm, Zmm, Mem |
824    /// | 6 | Zmm, Zmm, Zmm |
825    /// +---+---------------+
826    /// ```
827    #[inline]
828    pub fn vpdpbusds_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
829    where Assembler<'a>: VpdpbusdsMaskzEmitter<A, B, C> {
830        <Self as VpdpbusdsMaskzEmitter<A, B, C>>::vpdpbusds_maskz(self, op0, op1, op2);
831    }
832    /// `VPDPBUSD_MASK` (VPDPBUSD). 
833    /// Multiplies the individual unsigned bytes of the first source operand by the corresponding signed bytes of the second source operand, producing intermediate signed word results. The word results are then summed and accumulated in the destination dword element size operand.
834    ///
835    ///
836    /// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VPDPBUSD.html).
837    ///
838    /// Supported operand variants:
839    ///
840    /// ```text
841    /// +---+---------------+
842    /// | # | Operands      |
843    /// +---+---------------+
844    /// | 1 | Xmm, Xmm, Mem |
845    /// | 2 | Xmm, Xmm, Xmm |
846    /// | 3 | Ymm, Ymm, Mem |
847    /// | 4 | Ymm, Ymm, Ymm |
848    /// | 5 | Zmm, Zmm, Mem |
849    /// | 6 | Zmm, Zmm, Zmm |
850    /// +---+---------------+
851    /// ```
852    #[inline]
853    pub fn vpdpbusd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
854    where Assembler<'a>: VpdpbusdMaskEmitter<A, B, C> {
855        <Self as VpdpbusdMaskEmitter<A, B, C>>::vpdpbusd_mask(self, op0, op1, op2);
856    }
857    /// `VPDPBUSD_MASKZ` (VPDPBUSD). 
858    /// Multiplies the individual unsigned bytes of the first source operand by the corresponding signed bytes of the second source operand, producing intermediate signed word results. The word results are then summed and accumulated in the destination dword element size operand.
859    ///
860    ///
861    /// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VPDPBUSD.html).
862    ///
863    /// Supported operand variants:
864    ///
865    /// ```text
866    /// +---+---------------+
867    /// | # | Operands      |
868    /// +---+---------------+
869    /// | 1 | Xmm, Xmm, Mem |
870    /// | 2 | Xmm, Xmm, Xmm |
871    /// | 3 | Ymm, Ymm, Mem |
872    /// | 4 | Ymm, Ymm, Ymm |
873    /// | 5 | Zmm, Zmm, Mem |
874    /// | 6 | Zmm, Zmm, Zmm |
875    /// +---+---------------+
876    /// ```
877    #[inline]
878    pub fn vpdpbusd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
879    where Assembler<'a>: VpdpbusdMaskzEmitter<A, B, C> {
880        <Self as VpdpbusdMaskzEmitter<A, B, C>>::vpdpbusd_maskz(self, op0, op1, op2);
881    }
882    /// `VPDPWSSD` (VPDPWSSD). 
883    /// Multiplies the individual signed words of the first source operand by the corresponding signed words of the second source operand, producing intermediate signed, doubleword results. The adjacent doubleword results are then summed and accumulated in the destination operand.
884    ///
885    ///
886    /// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VPDPWSSD.html).
887    ///
888    /// Supported operand variants:
889    ///
890    /// ```text
891    /// +---+---------------+
892    /// | # | Operands      |
893    /// +---+---------------+
894    /// | 1 | Xmm, Xmm, Mem |
895    /// | 2 | Xmm, Xmm, Xmm |
896    /// | 3 | Ymm, Ymm, Mem |
897    /// | 4 | Ymm, Ymm, Ymm |
898    /// | 5 | Zmm, Zmm, Mem |
899    /// | 6 | Zmm, Zmm, Zmm |
900    /// +---+---------------+
901    /// ```
902    #[inline]
903    pub fn vpdpwssd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
904    where Assembler<'a>: VpdpwssdEmitter<A, B, C> {
905        <Self as VpdpwssdEmitter<A, B, C>>::vpdpwssd(self, op0, op1, op2);
906    }
907    /// `VPDPWSSDS` (VPDPWSSDS). 
908    /// Multiplies the individual signed words of the first source operand by the corresponding signed words of the second source operand, producing intermediate signed, doubleword results. The adjacent doubleword results are then summed and accumulated in the destination operand. If the intermediate sum overflows a 32b signed number, the result is saturated to either 0x7FFF_FFFF for positive numbers of 0x8000_0000 for negative numbers.
909    ///
910    ///
911    /// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VPDPWSSDS.html).
912    ///
913    /// Supported operand variants:
914    ///
915    /// ```text
916    /// +---+---------------+
917    /// | # | Operands      |
918    /// +---+---------------+
919    /// | 1 | Xmm, Xmm, Mem |
920    /// | 2 | Xmm, Xmm, Xmm |
921    /// | 3 | Ymm, Ymm, Mem |
922    /// | 4 | Ymm, Ymm, Ymm |
923    /// | 5 | Zmm, Zmm, Mem |
924    /// | 6 | Zmm, Zmm, Zmm |
925    /// +---+---------------+
926    /// ```
927    #[inline]
928    pub fn vpdpwssds<A, B, C>(&mut self, op0: A, op1: B, op2: C)
929    where Assembler<'a>: VpdpwssdsEmitter<A, B, C> {
930        <Self as VpdpwssdsEmitter<A, B, C>>::vpdpwssds(self, op0, op1, op2);
931    }
932    /// `VPDPWSSDS_MASK` (VPDPWSSDS). 
933    /// Multiplies the individual signed words of the first source operand by the corresponding signed words of the second source operand, producing intermediate signed, doubleword results. The adjacent doubleword results are then summed and accumulated in the destination operand. If the intermediate sum overflows a 32b signed number, the result is saturated to either 0x7FFF_FFFF for positive numbers of 0x8000_0000 for negative numbers.
934    ///
935    ///
936    /// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VPDPWSSDS.html).
937    ///
938    /// Supported operand variants:
939    ///
940    /// ```text
941    /// +---+---------------+
942    /// | # | Operands      |
943    /// +---+---------------+
944    /// | 1 | Xmm, Xmm, Mem |
945    /// | 2 | Xmm, Xmm, Xmm |
946    /// | 3 | Ymm, Ymm, Mem |
947    /// | 4 | Ymm, Ymm, Ymm |
948    /// | 5 | Zmm, Zmm, Mem |
949    /// | 6 | Zmm, Zmm, Zmm |
950    /// +---+---------------+
951    /// ```
952    #[inline]
953    pub fn vpdpwssds_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
954    where Assembler<'a>: VpdpwssdsMaskEmitter<A, B, C> {
955        <Self as VpdpwssdsMaskEmitter<A, B, C>>::vpdpwssds_mask(self, op0, op1, op2);
956    }
957    /// `VPDPWSSDS_MASKZ` (VPDPWSSDS). 
958    /// Multiplies the individual signed words of the first source operand by the corresponding signed words of the second source operand, producing intermediate signed, doubleword results. The adjacent doubleword results are then summed and accumulated in the destination operand. If the intermediate sum overflows a 32b signed number, the result is saturated to either 0x7FFF_FFFF for positive numbers of 0x8000_0000 for negative numbers.
959    ///
960    ///
961    /// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VPDPWSSDS.html).
962    ///
963    /// Supported operand variants:
964    ///
965    /// ```text
966    /// +---+---------------+
967    /// | # | Operands      |
968    /// +---+---------------+
969    /// | 1 | Xmm, Xmm, Mem |
970    /// | 2 | Xmm, Xmm, Xmm |
971    /// | 3 | Ymm, Ymm, Mem |
972    /// | 4 | Ymm, Ymm, Ymm |
973    /// | 5 | Zmm, Zmm, Mem |
974    /// | 6 | Zmm, Zmm, Zmm |
975    /// +---+---------------+
976    /// ```
977    #[inline]
978    pub fn vpdpwssds_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
979    where Assembler<'a>: VpdpwssdsMaskzEmitter<A, B, C> {
980        <Self as VpdpwssdsMaskzEmitter<A, B, C>>::vpdpwssds_maskz(self, op0, op1, op2);
981    }
982    /// `VPDPWSSD_MASK` (VPDPWSSD). 
983    /// Multiplies the individual signed words of the first source operand by the corresponding signed words of the second source operand, producing intermediate signed, doubleword results. The adjacent doubleword results are then summed and accumulated in the destination operand.
984    ///
985    ///
986    /// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VPDPWSSD.html).
987    ///
988    /// Supported operand variants:
989    ///
990    /// ```text
991    /// +---+---------------+
992    /// | # | Operands      |
993    /// +---+---------------+
994    /// | 1 | Xmm, Xmm, Mem |
995    /// | 2 | Xmm, Xmm, Xmm |
996    /// | 3 | Ymm, Ymm, Mem |
997    /// | 4 | Ymm, Ymm, Ymm |
998    /// | 5 | Zmm, Zmm, Mem |
999    /// | 6 | Zmm, Zmm, Zmm |
1000    /// +---+---------------+
1001    /// ```
1002    #[inline]
1003    pub fn vpdpwssd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
1004    where Assembler<'a>: VpdpwssdMaskEmitter<A, B, C> {
1005        <Self as VpdpwssdMaskEmitter<A, B, C>>::vpdpwssd_mask(self, op0, op1, op2);
1006    }
1007    /// `VPDPWSSD_MASKZ` (VPDPWSSD). 
1008    /// Multiplies the individual signed words of the first source operand by the corresponding signed words of the second source operand, producing intermediate signed, doubleword results. The adjacent doubleword results are then summed and accumulated in the destination operand.
1009    ///
1010    ///
1011    /// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VPDPWSSD.html).
1012    ///
1013    /// Supported operand variants:
1014    ///
1015    /// ```text
1016    /// +---+---------------+
1017    /// | # | Operands      |
1018    /// +---+---------------+
1019    /// | 1 | Xmm, Xmm, Mem |
1020    /// | 2 | Xmm, Xmm, Xmm |
1021    /// | 3 | Ymm, Ymm, Mem |
1022    /// | 4 | Ymm, Ymm, Ymm |
1023    /// | 5 | Zmm, Zmm, Mem |
1024    /// | 6 | Zmm, Zmm, Zmm |
1025    /// +---+---------------+
1026    /// ```
1027    #[inline]
1028    pub fn vpdpwssd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
1029    where Assembler<'a>: VpdpwssdMaskzEmitter<A, B, C> {
1030        <Self as VpdpwssdMaskzEmitter<A, B, C>>::vpdpwssd_maskz(self, op0, op1, op2);
1031    }
1032}
asmkit/x86/features/AVX512_VNNI.rs

asmkit/x86/features/
AVX512_VNNI.rs
