asmkit/x86/features/
AVX512_BITALG.rs

1use crate::x86::assembler::*;
2use crate::x86::operands::*;
3use super::super::opcodes::*;
4use crate::core::emitter::*;
5use crate::core::operand::*;
6
7/// A dummy operand that represents no register. Here just for simplicity.
8const NOREG: Operand = Operand::new();
9
10/// `VPOPCNTB` (VPOPCNTB). 
11/// This instruction counts the number of bits set to one in each byte, word, dword or qword element of its source (e.g., zmm2 or memory) and places the results in the destination register (zmm1). This instruction supports memory fault suppression.
12///
13///
14/// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VPOPCNT.html).
15///
16/// Supported operand variants:
17///
18/// ```text
19/// +---+----------+
20/// | # | Operands |
21/// +---+----------+
22/// | 1 | Xmm, Mem |
23/// | 2 | Xmm, Xmm |
24/// | 3 | Ymm, Mem |
25/// | 4 | Ymm, Ymm |
26/// | 5 | Zmm, Mem |
27/// | 6 | Zmm, Zmm |
28/// +---+----------+
29/// ```
30pub trait VpopcntbEmitter<A, B> {
31    fn vpopcntb(&mut self, op0: A, op1: B);
32}
33
34impl<'a> VpopcntbEmitter<Xmm, Xmm> for Assembler<'a> {
35    fn vpopcntb(&mut self, op0: Xmm, op1: Xmm) {
36        self.emit(VPOPCNTB128RR, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
37    }
38}
39
40impl<'a> VpopcntbEmitter<Xmm, Mem> for Assembler<'a> {
41    fn vpopcntb(&mut self, op0: Xmm, op1: Mem) {
42        self.emit(VPOPCNTB128RM, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
43    }
44}
45
46impl<'a> VpopcntbEmitter<Ymm, Ymm> for Assembler<'a> {
47    fn vpopcntb(&mut self, op0: Ymm, op1: Ymm) {
48        self.emit(VPOPCNTB256RR, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
49    }
50}
51
52impl<'a> VpopcntbEmitter<Ymm, Mem> for Assembler<'a> {
53    fn vpopcntb(&mut self, op0: Ymm, op1: Mem) {
54        self.emit(VPOPCNTB256RM, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
55    }
56}
57
58impl<'a> VpopcntbEmitter<Zmm, Zmm> for Assembler<'a> {
59    fn vpopcntb(&mut self, op0: Zmm, op1: Zmm) {
60        self.emit(VPOPCNTB512RR, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
61    }
62}
63
64impl<'a> VpopcntbEmitter<Zmm, Mem> for Assembler<'a> {
65    fn vpopcntb(&mut self, op0: Zmm, op1: Mem) {
66        self.emit(VPOPCNTB512RM, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
67    }
68}
69
70/// `VPOPCNTB_MASK` (VPOPCNTB). 
71/// This instruction counts the number of bits set to one in each byte, word, dword or qword element of its source (e.g., zmm2 or memory) and places the results in the destination register (zmm1). This instruction supports memory fault suppression.
72///
73///
74/// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VPOPCNT.html).
75///
76/// Supported operand variants:
77///
78/// ```text
79/// +---+----------+
80/// | # | Operands |
81/// +---+----------+
82/// | 1 | Xmm, Mem |
83/// | 2 | Xmm, Xmm |
84/// | 3 | Ymm, Mem |
85/// | 4 | Ymm, Ymm |
86/// | 5 | Zmm, Mem |
87/// | 6 | Zmm, Zmm |
88/// +---+----------+
89/// ```
90pub trait VpopcntbMaskEmitter<A, B> {
91    fn vpopcntb_mask(&mut self, op0: A, op1: B);
92}
93
94impl<'a> VpopcntbMaskEmitter<Xmm, Xmm> for Assembler<'a> {
95    fn vpopcntb_mask(&mut self, op0: Xmm, op1: Xmm) {
96        self.emit(VPOPCNTB128RR_MASK, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
97    }
98}
99
100impl<'a> VpopcntbMaskEmitter<Xmm, Mem> for Assembler<'a> {
101    fn vpopcntb_mask(&mut self, op0: Xmm, op1: Mem) {
102        self.emit(VPOPCNTB128RM_MASK, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
103    }
104}
105
106impl<'a> VpopcntbMaskEmitter<Ymm, Ymm> for Assembler<'a> {
107    fn vpopcntb_mask(&mut self, op0: Ymm, op1: Ymm) {
108        self.emit(VPOPCNTB256RR_MASK, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
109    }
110}
111
112impl<'a> VpopcntbMaskEmitter<Ymm, Mem> for Assembler<'a> {
113    fn vpopcntb_mask(&mut self, op0: Ymm, op1: Mem) {
114        self.emit(VPOPCNTB256RM_MASK, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
115    }
116}
117
118impl<'a> VpopcntbMaskEmitter<Zmm, Zmm> for Assembler<'a> {
119    fn vpopcntb_mask(&mut self, op0: Zmm, op1: Zmm) {
120        self.emit(VPOPCNTB512RR_MASK, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
121    }
122}
123
124impl<'a> VpopcntbMaskEmitter<Zmm, Mem> for Assembler<'a> {
125    fn vpopcntb_mask(&mut self, op0: Zmm, op1: Mem) {
126        self.emit(VPOPCNTB512RM_MASK, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
127    }
128}
129
130/// `VPOPCNTB_MASKZ` (VPOPCNTB). 
131/// This instruction counts the number of bits set to one in each byte, word, dword or qword element of its source (e.g., zmm2 or memory) and places the results in the destination register (zmm1). This instruction supports memory fault suppression.
132///
133///
134/// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VPOPCNT.html).
135///
136/// Supported operand variants:
137///
138/// ```text
139/// +---+----------+
140/// | # | Operands |
141/// +---+----------+
142/// | 1 | Xmm, Mem |
143/// | 2 | Xmm, Xmm |
144/// | 3 | Ymm, Mem |
145/// | 4 | Ymm, Ymm |
146/// | 5 | Zmm, Mem |
147/// | 6 | Zmm, Zmm |
148/// +---+----------+
149/// ```
150pub trait VpopcntbMaskzEmitter<A, B> {
151    fn vpopcntb_maskz(&mut self, op0: A, op1: B);
152}
153
154impl<'a> VpopcntbMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
155    fn vpopcntb_maskz(&mut self, op0: Xmm, op1: Xmm) {
156        self.emit(VPOPCNTB128RR_MASKZ, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
157    }
158}
159
160impl<'a> VpopcntbMaskzEmitter<Xmm, Mem> for Assembler<'a> {
161    fn vpopcntb_maskz(&mut self, op0: Xmm, op1: Mem) {
162        self.emit(VPOPCNTB128RM_MASKZ, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
163    }
164}
165
166impl<'a> VpopcntbMaskzEmitter<Ymm, Ymm> for Assembler<'a> {
167    fn vpopcntb_maskz(&mut self, op0: Ymm, op1: Ymm) {
168        self.emit(VPOPCNTB256RR_MASKZ, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
169    }
170}
171
172impl<'a> VpopcntbMaskzEmitter<Ymm, Mem> for Assembler<'a> {
173    fn vpopcntb_maskz(&mut self, op0: Ymm, op1: Mem) {
174        self.emit(VPOPCNTB256RM_MASKZ, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
175    }
176}
177
178impl<'a> VpopcntbMaskzEmitter<Zmm, Zmm> for Assembler<'a> {
179    fn vpopcntb_maskz(&mut self, op0: Zmm, op1: Zmm) {
180        self.emit(VPOPCNTB512RR_MASKZ, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
181    }
182}
183
184impl<'a> VpopcntbMaskzEmitter<Zmm, Mem> for Assembler<'a> {
185    fn vpopcntb_maskz(&mut self, op0: Zmm, op1: Mem) {
186        self.emit(VPOPCNTB512RM_MASKZ, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
187    }
188}
189
190/// `VPOPCNTW` (VPOPCNTW). 
191/// This instruction counts the number of bits set to one in each byte, word, dword or qword element of its source (e.g., zmm2 or memory) and places the results in the destination register (zmm1). This instruction supports memory fault suppression.
192///
193///
194/// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VPOPCNT.html).
195///
196/// Supported operand variants:
197///
198/// ```text
199/// +---+----------+
200/// | # | Operands |
201/// +---+----------+
202/// | 1 | Xmm, Mem |
203/// | 2 | Xmm, Xmm |
204/// | 3 | Ymm, Mem |
205/// | 4 | Ymm, Ymm |
206/// | 5 | Zmm, Mem |
207/// | 6 | Zmm, Zmm |
208/// +---+----------+
209/// ```
210pub trait VpopcntwEmitter<A, B> {
211    fn vpopcntw(&mut self, op0: A, op1: B);
212}
213
214impl<'a> VpopcntwEmitter<Xmm, Xmm> for Assembler<'a> {
215    fn vpopcntw(&mut self, op0: Xmm, op1: Xmm) {
216        self.emit(VPOPCNTW128RR, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
217    }
218}
219
220impl<'a> VpopcntwEmitter<Xmm, Mem> for Assembler<'a> {
221    fn vpopcntw(&mut self, op0: Xmm, op1: Mem) {
222        self.emit(VPOPCNTW128RM, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
223    }
224}
225
226impl<'a> VpopcntwEmitter<Ymm, Ymm> for Assembler<'a> {
227    fn vpopcntw(&mut self, op0: Ymm, op1: Ymm) {
228        self.emit(VPOPCNTW256RR, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
229    }
230}
231
232impl<'a> VpopcntwEmitter<Ymm, Mem> for Assembler<'a> {
233    fn vpopcntw(&mut self, op0: Ymm, op1: Mem) {
234        self.emit(VPOPCNTW256RM, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
235    }
236}
237
238impl<'a> VpopcntwEmitter<Zmm, Zmm> for Assembler<'a> {
239    fn vpopcntw(&mut self, op0: Zmm, op1: Zmm) {
240        self.emit(VPOPCNTW512RR, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
241    }
242}
243
244impl<'a> VpopcntwEmitter<Zmm, Mem> for Assembler<'a> {
245    fn vpopcntw(&mut self, op0: Zmm, op1: Mem) {
246        self.emit(VPOPCNTW512RM, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
247    }
248}
249
250/// `VPOPCNTW_MASK` (VPOPCNTW). 
251/// This instruction counts the number of bits set to one in each byte, word, dword or qword element of its source (e.g., zmm2 or memory) and places the results in the destination register (zmm1). This instruction supports memory fault suppression.
252///
253///
254/// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VPOPCNT.html).
255///
256/// Supported operand variants:
257///
258/// ```text
259/// +---+----------+
260/// | # | Operands |
261/// +---+----------+
262/// | 1 | Xmm, Mem |
263/// | 2 | Xmm, Xmm |
264/// | 3 | Ymm, Mem |
265/// | 4 | Ymm, Ymm |
266/// | 5 | Zmm, Mem |
267/// | 6 | Zmm, Zmm |
268/// +---+----------+
269/// ```
270pub trait VpopcntwMaskEmitter<A, B> {
271    fn vpopcntw_mask(&mut self, op0: A, op1: B);
272}
273
274impl<'a> VpopcntwMaskEmitter<Xmm, Xmm> for Assembler<'a> {
275    fn vpopcntw_mask(&mut self, op0: Xmm, op1: Xmm) {
276        self.emit(VPOPCNTW128RR_MASK, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
277    }
278}
279
280impl<'a> VpopcntwMaskEmitter<Xmm, Mem> for Assembler<'a> {
281    fn vpopcntw_mask(&mut self, op0: Xmm, op1: Mem) {
282        self.emit(VPOPCNTW128RM_MASK, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
283    }
284}
285
286impl<'a> VpopcntwMaskEmitter<Ymm, Ymm> for Assembler<'a> {
287    fn vpopcntw_mask(&mut self, op0: Ymm, op1: Ymm) {
288        self.emit(VPOPCNTW256RR_MASK, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
289    }
290}
291
292impl<'a> VpopcntwMaskEmitter<Ymm, Mem> for Assembler<'a> {
293    fn vpopcntw_mask(&mut self, op0: Ymm, op1: Mem) {
294        self.emit(VPOPCNTW256RM_MASK, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
295    }
296}
297
298impl<'a> VpopcntwMaskEmitter<Zmm, Zmm> for Assembler<'a> {
299    fn vpopcntw_mask(&mut self, op0: Zmm, op1: Zmm) {
300        self.emit(VPOPCNTW512RR_MASK, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
301    }
302}
303
304impl<'a> VpopcntwMaskEmitter<Zmm, Mem> for Assembler<'a> {
305    fn vpopcntw_mask(&mut self, op0: Zmm, op1: Mem) {
306        self.emit(VPOPCNTW512RM_MASK, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
307    }
308}
309
310/// `VPOPCNTW_MASKZ` (VPOPCNTW). 
311/// This instruction counts the number of bits set to one in each byte, word, dword or qword element of its source (e.g., zmm2 or memory) and places the results in the destination register (zmm1). This instruction supports memory fault suppression.
312///
313///
314/// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VPOPCNT.html).
315///
316/// Supported operand variants:
317///
318/// ```text
319/// +---+----------+
320/// | # | Operands |
321/// +---+----------+
322/// | 1 | Xmm, Mem |
323/// | 2 | Xmm, Xmm |
324/// | 3 | Ymm, Mem |
325/// | 4 | Ymm, Ymm |
326/// | 5 | Zmm, Mem |
327/// | 6 | Zmm, Zmm |
328/// +---+----------+
329/// ```
330pub trait VpopcntwMaskzEmitter<A, B> {
331    fn vpopcntw_maskz(&mut self, op0: A, op1: B);
332}
333
334impl<'a> VpopcntwMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
335    fn vpopcntw_maskz(&mut self, op0: Xmm, op1: Xmm) {
336        self.emit(VPOPCNTW128RR_MASKZ, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
337    }
338}
339
340impl<'a> VpopcntwMaskzEmitter<Xmm, Mem> for Assembler<'a> {
341    fn vpopcntw_maskz(&mut self, op0: Xmm, op1: Mem) {
342        self.emit(VPOPCNTW128RM_MASKZ, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
343    }
344}
345
346impl<'a> VpopcntwMaskzEmitter<Ymm, Ymm> for Assembler<'a> {
347    fn vpopcntw_maskz(&mut self, op0: Ymm, op1: Ymm) {
348        self.emit(VPOPCNTW256RR_MASKZ, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
349    }
350}
351
352impl<'a> VpopcntwMaskzEmitter<Ymm, Mem> for Assembler<'a> {
353    fn vpopcntw_maskz(&mut self, op0: Ymm, op1: Mem) {
354        self.emit(VPOPCNTW256RM_MASKZ, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
355    }
356}
357
358impl<'a> VpopcntwMaskzEmitter<Zmm, Zmm> for Assembler<'a> {
359    fn vpopcntw_maskz(&mut self, op0: Zmm, op1: Zmm) {
360        self.emit(VPOPCNTW512RR_MASKZ, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
361    }
362}
363
364impl<'a> VpopcntwMaskzEmitter<Zmm, Mem> for Assembler<'a> {
365    fn vpopcntw_maskz(&mut self, op0: Zmm, op1: Mem) {
366        self.emit(VPOPCNTW512RM_MASKZ, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
367    }
368}
369
370/// `VPSHUFBITQMB` (VPSHUFBITQMB). 
371/// The VPSHUFBITQMB instruction performs a bit gather select using second source as control and first source as data. Each bit uses 6 control bits (2nd source operand) to select which data bit is going to be gathered (first source operand). A given bit can only access 64 different bits of data (first 64 destination bits can access first 64 data bits, second 64 destination bits can access second 64 data bits, etc.).
372///
373///
374/// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VPSHUFBITQMB.html).
375///
376/// Supported operand variants:
377///
378/// ```text
379/// +---+----------------+
380/// | # | Operands       |
381/// +---+----------------+
382/// | 1 | KReg, Xmm, Mem |
383/// | 2 | KReg, Xmm, Xmm |
384/// | 3 | KReg, Ymm, Mem |
385/// | 4 | KReg, Ymm, Ymm |
386/// | 5 | KReg, Zmm, Mem |
387/// | 6 | KReg, Zmm, Zmm |
388/// +---+----------------+
389/// ```
390pub trait VpshufbitqmbEmitter<A, B, C> {
391    fn vpshufbitqmb(&mut self, op0: A, op1: B, op2: C);
392}
393
394impl<'a> VpshufbitqmbEmitter<KReg, Xmm, Xmm> for Assembler<'a> {
395    fn vpshufbitqmb(&mut self, op0: KReg, op1: Xmm, op2: Xmm) {
396        self.emit(VPSHUFBITQMB128KRR, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
397    }
398}
399
400impl<'a> VpshufbitqmbEmitter<KReg, Xmm, Mem> for Assembler<'a> {
401    fn vpshufbitqmb(&mut self, op0: KReg, op1: Xmm, op2: Mem) {
402        self.emit(VPSHUFBITQMB128KRM, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
403    }
404}
405
406impl<'a> VpshufbitqmbEmitter<KReg, Ymm, Ymm> for Assembler<'a> {
407    fn vpshufbitqmb(&mut self, op0: KReg, op1: Ymm, op2: Ymm) {
408        self.emit(VPSHUFBITQMB256KRR, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
409    }
410}
411
412impl<'a> VpshufbitqmbEmitter<KReg, Ymm, Mem> for Assembler<'a> {
413    fn vpshufbitqmb(&mut self, op0: KReg, op1: Ymm, op2: Mem) {
414        self.emit(VPSHUFBITQMB256KRM, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
415    }
416}
417
418impl<'a> VpshufbitqmbEmitter<KReg, Zmm, Zmm> for Assembler<'a> {
419    fn vpshufbitqmb(&mut self, op0: KReg, op1: Zmm, op2: Zmm) {
420        self.emit(VPSHUFBITQMB512KRR, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
421    }
422}
423
424impl<'a> VpshufbitqmbEmitter<KReg, Zmm, Mem> for Assembler<'a> {
425    fn vpshufbitqmb(&mut self, op0: KReg, op1: Zmm, op2: Mem) {
426        self.emit(VPSHUFBITQMB512KRM, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
427    }
428}
429
430/// `VPSHUFBITQMB_MASK` (VPSHUFBITQMB). 
431/// The VPSHUFBITQMB instruction performs a bit gather select using second source as control and first source as data. Each bit uses 6 control bits (2nd source operand) to select which data bit is going to be gathered (first source operand). A given bit can only access 64 different bits of data (first 64 destination bits can access first 64 data bits, second 64 destination bits can access second 64 data bits, etc.).
432///
433///
434/// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VPSHUFBITQMB.html).
435///
436/// Supported operand variants:
437///
438/// ```text
439/// +---+----------------+
440/// | # | Operands       |
441/// +---+----------------+
442/// | 1 | KReg, Xmm, Mem |
443/// | 2 | KReg, Xmm, Xmm |
444/// | 3 | KReg, Ymm, Mem |
445/// | 4 | KReg, Ymm, Ymm |
446/// | 5 | KReg, Zmm, Mem |
447/// | 6 | KReg, Zmm, Zmm |
448/// +---+----------------+
449/// ```
450pub trait VpshufbitqmbMaskEmitter<A, B, C> {
451    fn vpshufbitqmb_mask(&mut self, op0: A, op1: B, op2: C);
452}
453
454impl<'a> VpshufbitqmbMaskEmitter<KReg, Xmm, Xmm> for Assembler<'a> {
455    fn vpshufbitqmb_mask(&mut self, op0: KReg, op1: Xmm, op2: Xmm) {
456        self.emit(VPSHUFBITQMB128KRR_MASK, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
457    }
458}
459
460impl<'a> VpshufbitqmbMaskEmitter<KReg, Xmm, Mem> for Assembler<'a> {
461    fn vpshufbitqmb_mask(&mut self, op0: KReg, op1: Xmm, op2: Mem) {
462        self.emit(VPSHUFBITQMB128KRM_MASK, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
463    }
464}
465
466impl<'a> VpshufbitqmbMaskEmitter<KReg, Ymm, Ymm> for Assembler<'a> {
467    fn vpshufbitqmb_mask(&mut self, op0: KReg, op1: Ymm, op2: Ymm) {
468        self.emit(VPSHUFBITQMB256KRR_MASK, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
469    }
470}
471
472impl<'a> VpshufbitqmbMaskEmitter<KReg, Ymm, Mem> for Assembler<'a> {
473    fn vpshufbitqmb_mask(&mut self, op0: KReg, op1: Ymm, op2: Mem) {
474        self.emit(VPSHUFBITQMB256KRM_MASK, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
475    }
476}
477
478impl<'a> VpshufbitqmbMaskEmitter<KReg, Zmm, Zmm> for Assembler<'a> {
479    fn vpshufbitqmb_mask(&mut self, op0: KReg, op1: Zmm, op2: Zmm) {
480        self.emit(VPSHUFBITQMB512KRR_MASK, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
481    }
482}
483
484impl<'a> VpshufbitqmbMaskEmitter<KReg, Zmm, Mem> for Assembler<'a> {
485    fn vpshufbitqmb_mask(&mut self, op0: KReg, op1: Zmm, op2: Mem) {
486        self.emit(VPSHUFBITQMB512KRM_MASK, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
487    }
488}
489
490
491impl<'a> Assembler<'a> {
492    /// `VPOPCNTB` (VPOPCNTB). 
493    /// This instruction counts the number of bits set to one in each byte, word, dword or qword element of its source (e.g., zmm2 or memory) and places the results in the destination register (zmm1). This instruction supports memory fault suppression.
494    ///
495    ///
496    /// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VPOPCNT.html).
497    ///
498    /// Supported operand variants:
499    ///
500    /// ```text
501    /// +---+----------+
502    /// | # | Operands |
503    /// +---+----------+
504    /// | 1 | Xmm, Mem |
505    /// | 2 | Xmm, Xmm |
506    /// | 3 | Ymm, Mem |
507    /// | 4 | Ymm, Ymm |
508    /// | 5 | Zmm, Mem |
509    /// | 6 | Zmm, Zmm |
510    /// +---+----------+
511    /// ```
512    #[inline]
513    pub fn vpopcntb<A, B>(&mut self, op0: A, op1: B)
514    where Assembler<'a>: VpopcntbEmitter<A, B> {
515        <Self as VpopcntbEmitter<A, B>>::vpopcntb(self, op0, op1);
516    }
517    /// `VPOPCNTB_MASK` (VPOPCNTB). 
518    /// This instruction counts the number of bits set to one in each byte, word, dword or qword element of its source (e.g., zmm2 or memory) and places the results in the destination register (zmm1). This instruction supports memory fault suppression.
519    ///
520    ///
521    /// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VPOPCNT.html).
522    ///
523    /// Supported operand variants:
524    ///
525    /// ```text
526    /// +---+----------+
527    /// | # | Operands |
528    /// +---+----------+
529    /// | 1 | Xmm, Mem |
530    /// | 2 | Xmm, Xmm |
531    /// | 3 | Ymm, Mem |
532    /// | 4 | Ymm, Ymm |
533    /// | 5 | Zmm, Mem |
534    /// | 6 | Zmm, Zmm |
535    /// +---+----------+
536    /// ```
537    #[inline]
538    pub fn vpopcntb_mask<A, B>(&mut self, op0: A, op1: B)
539    where Assembler<'a>: VpopcntbMaskEmitter<A, B> {
540        <Self as VpopcntbMaskEmitter<A, B>>::vpopcntb_mask(self, op0, op1);
541    }
542    /// `VPOPCNTB_MASKZ` (VPOPCNTB). 
543    /// This instruction counts the number of bits set to one in each byte, word, dword or qword element of its source (e.g., zmm2 or memory) and places the results in the destination register (zmm1). This instruction supports memory fault suppression.
544    ///
545    ///
546    /// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VPOPCNT.html).
547    ///
548    /// Supported operand variants:
549    ///
550    /// ```text
551    /// +---+----------+
552    /// | # | Operands |
553    /// +---+----------+
554    /// | 1 | Xmm, Mem |
555    /// | 2 | Xmm, Xmm |
556    /// | 3 | Ymm, Mem |
557    /// | 4 | Ymm, Ymm |
558    /// | 5 | Zmm, Mem |
559    /// | 6 | Zmm, Zmm |
560    /// +---+----------+
561    /// ```
562    #[inline]
563    pub fn vpopcntb_maskz<A, B>(&mut self, op0: A, op1: B)
564    where Assembler<'a>: VpopcntbMaskzEmitter<A, B> {
565        <Self as VpopcntbMaskzEmitter<A, B>>::vpopcntb_maskz(self, op0, op1);
566    }
567    /// `VPOPCNTW` (VPOPCNTW). 
568    /// This instruction counts the number of bits set to one in each byte, word, dword or qword element of its source (e.g., zmm2 or memory) and places the results in the destination register (zmm1). This instruction supports memory fault suppression.
569    ///
570    ///
571    /// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VPOPCNT.html).
572    ///
573    /// Supported operand variants:
574    ///
575    /// ```text
576    /// +---+----------+
577    /// | # | Operands |
578    /// +---+----------+
579    /// | 1 | Xmm, Mem |
580    /// | 2 | Xmm, Xmm |
581    /// | 3 | Ymm, Mem |
582    /// | 4 | Ymm, Ymm |
583    /// | 5 | Zmm, Mem |
584    /// | 6 | Zmm, Zmm |
585    /// +---+----------+
586    /// ```
587    #[inline]
588    pub fn vpopcntw<A, B>(&mut self, op0: A, op1: B)
589    where Assembler<'a>: VpopcntwEmitter<A, B> {
590        <Self as VpopcntwEmitter<A, B>>::vpopcntw(self, op0, op1);
591    }
592    /// `VPOPCNTW_MASK` (VPOPCNTW). 
593    /// This instruction counts the number of bits set to one in each byte, word, dword or qword element of its source (e.g., zmm2 or memory) and places the results in the destination register (zmm1). This instruction supports memory fault suppression.
594    ///
595    ///
596    /// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VPOPCNT.html).
597    ///
598    /// Supported operand variants:
599    ///
600    /// ```text
601    /// +---+----------+
602    /// | # | Operands |
603    /// +---+----------+
604    /// | 1 | Xmm, Mem |
605    /// | 2 | Xmm, Xmm |
606    /// | 3 | Ymm, Mem |
607    /// | 4 | Ymm, Ymm |
608    /// | 5 | Zmm, Mem |
609    /// | 6 | Zmm, Zmm |
610    /// +---+----------+
611    /// ```
612    #[inline]
613    pub fn vpopcntw_mask<A, B>(&mut self, op0: A, op1: B)
614    where Assembler<'a>: VpopcntwMaskEmitter<A, B> {
615        <Self as VpopcntwMaskEmitter<A, B>>::vpopcntw_mask(self, op0, op1);
616    }
617    /// `VPOPCNTW_MASKZ` (VPOPCNTW). 
618    /// This instruction counts the number of bits set to one in each byte, word, dword or qword element of its source (e.g., zmm2 or memory) and places the results in the destination register (zmm1). This instruction supports memory fault suppression.
619    ///
620    ///
621    /// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VPOPCNT.html).
622    ///
623    /// Supported operand variants:
624    ///
625    /// ```text
626    /// +---+----------+
627    /// | # | Operands |
628    /// +---+----------+
629    /// | 1 | Xmm, Mem |
630    /// | 2 | Xmm, Xmm |
631    /// | 3 | Ymm, Mem |
632    /// | 4 | Ymm, Ymm |
633    /// | 5 | Zmm, Mem |
634    /// | 6 | Zmm, Zmm |
635    /// +---+----------+
636    /// ```
637    #[inline]
638    pub fn vpopcntw_maskz<A, B>(&mut self, op0: A, op1: B)
639    where Assembler<'a>: VpopcntwMaskzEmitter<A, B> {
640        <Self as VpopcntwMaskzEmitter<A, B>>::vpopcntw_maskz(self, op0, op1);
641    }
642    /// `VPSHUFBITQMB` (VPSHUFBITQMB). 
643    /// The VPSHUFBITQMB instruction performs a bit gather select using second source as control and first source as data. Each bit uses 6 control bits (2nd source operand) to select which data bit is going to be gathered (first source operand). A given bit can only access 64 different bits of data (first 64 destination bits can access first 64 data bits, second 64 destination bits can access second 64 data bits, etc.).
644    ///
645    ///
646    /// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VPSHUFBITQMB.html).
647    ///
648    /// Supported operand variants:
649    ///
650    /// ```text
651    /// +---+----------------+
652    /// | # | Operands       |
653    /// +---+----------------+
654    /// | 1 | KReg, Xmm, Mem |
655    /// | 2 | KReg, Xmm, Xmm |
656    /// | 3 | KReg, Ymm, Mem |
657    /// | 4 | KReg, Ymm, Ymm |
658    /// | 5 | KReg, Zmm, Mem |
659    /// | 6 | KReg, Zmm, Zmm |
660    /// +---+----------------+
661    /// ```
662    #[inline]
663    pub fn vpshufbitqmb<A, B, C>(&mut self, op0: A, op1: B, op2: C)
664    where Assembler<'a>: VpshufbitqmbEmitter<A, B, C> {
665        <Self as VpshufbitqmbEmitter<A, B, C>>::vpshufbitqmb(self, op0, op1, op2);
666    }
667    /// `VPSHUFBITQMB_MASK` (VPSHUFBITQMB). 
668    /// The VPSHUFBITQMB instruction performs a bit gather select using second source as control and first source as data. Each bit uses 6 control bits (2nd source operand) to select which data bit is going to be gathered (first source operand). A given bit can only access 64 different bits of data (first 64 destination bits can access first 64 data bits, second 64 destination bits can access second 64 data bits, etc.).
669    ///
670    ///
671    /// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VPSHUFBITQMB.html).
672    ///
673    /// Supported operand variants:
674    ///
675    /// ```text
676    /// +---+----------------+
677    /// | # | Operands       |
678    /// +---+----------------+
679    /// | 1 | KReg, Xmm, Mem |
680    /// | 2 | KReg, Xmm, Xmm |
681    /// | 3 | KReg, Ymm, Mem |
682    /// | 4 | KReg, Ymm, Ymm |
683    /// | 5 | KReg, Zmm, Mem |
684    /// | 6 | KReg, Zmm, Zmm |
685    /// +---+----------------+
686    /// ```
687    #[inline]
688    pub fn vpshufbitqmb_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
689    where Assembler<'a>: VpshufbitqmbMaskEmitter<A, B, C> {
690        <Self as VpshufbitqmbMaskEmitter<A, B, C>>::vpshufbitqmb_mask(self, op0, op1, op2);
691    }
692}
asmkit/x86/features/AVX512_BITALG.rs

asmkit/x86/features/
AVX512_BITALG.rs
