asmkit/x86/features/XSAVE.rs
1use crate::x86::assembler::*;
2use crate::x86::operands::*;
3use super::super::opcodes::*;
4use crate::core::emitter::*;
5use crate::core::operand::*;
6
7/// A dummy operand that represents no register. Here just for simplicity.
8const NOREG: Operand = Operand::new();
9
10/// `XGETBV` (XGETBV).
11/// Reads the contents of the extended control register (XCR) specified in the ECX register into registers EDX:EAX. (On processors that support the Intel 64 architecture, the high-order 32 bits of RCX are ignored.) The EDX register is loaded with the high-order 32 bits of the XCR and the EAX register is loaded with the low-order 32 bits. (On processors that support the Intel 64 architecture, the high-order 32 bits of each of RAX and RDX are cleared.) If fewer than 64 bits are implemented in the XCR being read, the values returned to EDX:EAX in unimplemented bit locations are undefined.
12///
13///
14/// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/XGETBV.html).
15///
16/// Supported operand variants:
17///
18/// ```text
19/// +---+----------+
20/// | # | Operands |
21/// +---+----------+
22/// | 1 | (none) |
23/// +---+----------+
24/// ```
25pub trait XgetbvEmitter {
26 fn xgetbv(&mut self);
27}
28
29impl<'a> XgetbvEmitter for Assembler<'a> {
30 fn xgetbv(&mut self) {
31 self.emit(XGETBV, &NOREG, &NOREG, &NOREG, &NOREG);
32 }
33}
34
35/// `XRSTOR` (XRSTOR).
36/// Performs a full or partial restore of processor state components from the XSAVE area located at the memory address specified by the source operand. The implicit EDX:EAX register pair specifies a 64-bit instruction mask. The specific state components restored correspond to the bits set in the requested-feature bitmap (RFBM), which is the logical-AND of EDX:EAX and XCR0.
37///
38///
39/// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/XRSTOR.html).
40///
41/// Supported operand variants:
42///
43/// ```text
44/// +---+----------+
45/// | # | Operands |
46/// +---+----------+
47/// | 1 | Mem |
48/// +---+----------+
49/// ```
50pub trait XrstorEmitter<A> {
51 fn xrstor(&mut self, op0: A);
52}
53
54impl<'a> XrstorEmitter<Mem> for Assembler<'a> {
55 fn xrstor(&mut self, op0: Mem) {
56 self.emit(XRSTOR32M, op0.as_operand(), &NOREG, &NOREG, &NOREG);
57 }
58}
59
60/// `XSAVE` (XSAVE).
61/// Performs a full or partial save of processor state components to the XSAVE area located at the memory address specified by the destination operand. The implicit EDX:EAX register pair specifies a 64-bit instruction mask. The specific state components saved correspond to the bits set in the requested-feature bitmap (RFBM), which is the logical-AND of EDX:EAX and XCR0.
62///
63///
64/// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/XSAVE.html).
65///
66/// Supported operand variants:
67///
68/// ```text
69/// +---+----------+
70/// | # | Operands |
71/// +---+----------+
72/// | 1 | Mem |
73/// +---+----------+
74/// ```
75pub trait XsaveEmitter<A> {
76 fn xsave(&mut self, op0: A);
77}
78
79impl<'a> XsaveEmitter<Mem> for Assembler<'a> {
80 fn xsave(&mut self, op0: Mem) {
81 self.emit(XSAVE32M, op0.as_operand(), &NOREG, &NOREG, &NOREG);
82 }
83}
84
85/// `XSETBV` (XSETBV).
86/// Writes the contents of registers EDX:EAX into the 64-bit extended control register (XCR) specified in the ECX register. (On processors that support the Intel 64 architecture, the high-order 32 bits of RCX are ignored.) The contents of the EDX register are copied to high-order 32 bits of the selected XCR and the contents of the EAX register are copied to low-order 32 bits of the XCR. (On processors that support the Intel 64 architecture, the high-order 32 bits of each of RAX and RDX are ignored.) Undefined or reserved bits in an XCR should be set to values previously read.
87///
88///
89/// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/XSETBV.html).
90///
91/// Supported operand variants:
92///
93/// ```text
94/// +---+----------+
95/// | # | Operands |
96/// +---+----------+
97/// | 1 | (none) |
98/// +---+----------+
99/// ```
100pub trait XsetbvEmitter {
101 fn xsetbv(&mut self);
102}
103
104impl<'a> XsetbvEmitter for Assembler<'a> {
105 fn xsetbv(&mut self) {
106 self.emit(XSETBV, &NOREG, &NOREG, &NOREG, &NOREG);
107 }
108}
109
110
111impl<'a> Assembler<'a> {
112 /// `XGETBV` (XGETBV).
113 /// Reads the contents of the extended control register (XCR) specified in the ECX register into registers EDX:EAX. (On processors that support the Intel 64 architecture, the high-order 32 bits of RCX are ignored.) The EDX register is loaded with the high-order 32 bits of the XCR and the EAX register is loaded with the low-order 32 bits. (On processors that support the Intel 64 architecture, the high-order 32 bits of each of RAX and RDX are cleared.) If fewer than 64 bits are implemented in the XCR being read, the values returned to EDX:EAX in unimplemented bit locations are undefined.
114 ///
115 ///
116 /// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/XGETBV.html).
117 ///
118 /// Supported operand variants:
119 ///
120 /// ```text
121 /// +---+----------+
122 /// | # | Operands |
123 /// +---+----------+
124 /// | 1 | (none) |
125 /// +---+----------+
126 /// ```
127 #[inline]
128 pub fn xgetbv(&mut self)
129 where Assembler<'a>: XgetbvEmitter {
130 <Self as XgetbvEmitter>::xgetbv(self);
131 }
132 /// `XRSTOR` (XRSTOR).
133 /// Performs a full or partial restore of processor state components from the XSAVE area located at the memory address specified by the source operand. The implicit EDX:EAX register pair specifies a 64-bit instruction mask. The specific state components restored correspond to the bits set in the requested-feature bitmap (RFBM), which is the logical-AND of EDX:EAX and XCR0.
134 ///
135 ///
136 /// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/XRSTOR.html).
137 ///
138 /// Supported operand variants:
139 ///
140 /// ```text
141 /// +---+----------+
142 /// | # | Operands |
143 /// +---+----------+
144 /// | 1 | Mem |
145 /// +---+----------+
146 /// ```
147 #[inline]
148 pub fn xrstor<A>(&mut self, op0: A)
149 where Assembler<'a>: XrstorEmitter<A> {
150 <Self as XrstorEmitter<A>>::xrstor(self, op0);
151 }
152 /// `XSAVE` (XSAVE).
153 /// Performs a full or partial save of processor state components to the XSAVE area located at the memory address specified by the destination operand. The implicit EDX:EAX register pair specifies a 64-bit instruction mask. The specific state components saved correspond to the bits set in the requested-feature bitmap (RFBM), which is the logical-AND of EDX:EAX and XCR0.
154 ///
155 ///
156 /// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/XSAVE.html).
157 ///
158 /// Supported operand variants:
159 ///
160 /// ```text
161 /// +---+----------+
162 /// | # | Operands |
163 /// +---+----------+
164 /// | 1 | Mem |
165 /// +---+----------+
166 /// ```
167 #[inline]
168 pub fn xsave<A>(&mut self, op0: A)
169 where Assembler<'a>: XsaveEmitter<A> {
170 <Self as XsaveEmitter<A>>::xsave(self, op0);
171 }
172 /// `XSETBV` (XSETBV).
173 /// Writes the contents of registers EDX:EAX into the 64-bit extended control register (XCR) specified in the ECX register. (On processors that support the Intel 64 architecture, the high-order 32 bits of RCX are ignored.) The contents of the EDX register are copied to high-order 32 bits of the selected XCR and the contents of the EAX register are copied to low-order 32 bits of the XCR. (On processors that support the Intel 64 architecture, the high-order 32 bits of each of RAX and RDX are ignored.) Undefined or reserved bits in an XCR should be set to values previously read.
174 ///
175 ///
176 /// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/XSETBV.html).
177 ///
178 /// Supported operand variants:
179 ///
180 /// ```text
181 /// +---+----------+
182 /// | # | Operands |
183 /// +---+----------+
184 /// | 1 | (none) |
185 /// +---+----------+
186 /// ```
187 #[inline]
188 pub fn xsetbv(&mut self)
189 where Assembler<'a>: XsetbvEmitter {
190 <Self as XsetbvEmitter>::xsetbv(self);
191 }
192}