asmkit/x86/features/
WAITPKG.rs

1use crate::x86::assembler::*;
2use crate::x86::operands::*;
3use super::super::opcodes::*;
4use crate::core::emitter::*;
5use crate::core::operand::*;
6
7/// A dummy operand that represents no register. Here just for simplicity.
8const NOREG: Operand = Operand::new();
9
10/// `TPAUSE` (TPAUSE). 
11/// TPAUSE instructs the processor to enter an implementation-dependent optimized state. There are two such optimized states to choose from: light-weight power/performance optimized state, and improved power/performance optimized state. The selection between the two is governed by the explicit input register bit[0] source operand.
12///
13///
14/// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/TPAUSE.html).
15///
16/// Supported operand variants:
17///
18/// ```text
19/// +---+----------+
20/// | # | Operands |
21/// +---+----------+
22/// | 1 | Gpd      |
23/// +---+----------+
24/// ```
25pub trait TpauseEmitter<A> {
26    fn tpause(&mut self, op0: A);
27}
28
29impl<'a> TpauseEmitter<Gpd> for Assembler<'a> {
30    fn tpause(&mut self, op0: Gpd) {
31        self.emit(TPAUSER, op0.as_operand(), &NOREG, &NOREG, &NOREG);
32    }
33}
34
35/// `UMONITOR` (UMONITOR). 
36/// The UMONITOR instruction arms address monitoring hardware using an address specified in the source register (the address range that the monitoring hardware checks for store operations can be determined by using the CPUID monitor leaf function, EAX=05H). A store to an address within the specified address range triggers the monitoring hardware. The state of monitor hardware is used by UMWAIT.
37///
38///
39/// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/UMONITOR.html).
40///
41/// Supported operand variants:
42///
43/// ```text
44/// +---+----------+
45/// | # | Operands |
46/// +---+----------+
47/// | 1 | Gpd      |
48/// | 2 | Gpq      |
49/// +---+----------+
50/// ```
51pub trait UmonitorEmitter<A> {
52    fn umonitor(&mut self, op0: A);
53}
54
55impl<'a> UmonitorEmitter<Gpd> for Assembler<'a> {
56    fn umonitor(&mut self, op0: Gpd) {
57        self.emit(UMONITOR32R, op0.as_operand(), &NOREG, &NOREG, &NOREG);
58    }
59}
60
61impl<'a> UmonitorEmitter<Gpq> for Assembler<'a> {
62    fn umonitor(&mut self, op0: Gpq) {
63        self.emit(UMONITOR64R, op0.as_operand(), &NOREG, &NOREG, &NOREG);
64    }
65}
66
67/// `UMWAIT` (UMWAIT). 
68/// UMWAIT instructs the processor to enter an implementation-dependent optimized state while monitoring a range of addresses. The optimized state may be either a light-weight power/performance optimized state or an improved power/performance optimized state. The selection between the two states is governed by the explicit input register bit[0] source operand.
69///
70///
71/// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/UMWAIT.html).
72///
73/// Supported operand variants:
74///
75/// ```text
76/// +---+----------+
77/// | # | Operands |
78/// +---+----------+
79/// | 1 | Gpd      |
80/// +---+----------+
81/// ```
82pub trait UmwaitEmitter<A> {
83    fn umwait(&mut self, op0: A);
84}
85
86impl<'a> UmwaitEmitter<Gpd> for Assembler<'a> {
87    fn umwait(&mut self, op0: Gpd) {
88        self.emit(UMWAITR, op0.as_operand(), &NOREG, &NOREG, &NOREG);
89    }
90}
91
92
93impl<'a> Assembler<'a> {
94    /// `TPAUSE` (TPAUSE). 
95    /// TPAUSE instructs the processor to enter an implementation-dependent optimized state. There are two such optimized states to choose from: light-weight power/performance optimized state, and improved power/performance optimized state. The selection between the two is governed by the explicit input register bit[0] source operand.
96    ///
97    ///
98    /// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/TPAUSE.html).
99    ///
100    /// Supported operand variants:
101    ///
102    /// ```text
103    /// +---+----------+
104    /// | # | Operands |
105    /// +---+----------+
106    /// | 1 | Gpd      |
107    /// +---+----------+
108    /// ```
109    #[inline]
110    pub fn tpause<A>(&mut self, op0: A)
111    where Assembler<'a>: TpauseEmitter<A> {
112        <Self as TpauseEmitter<A>>::tpause(self, op0);
113    }
114    /// `UMONITOR` (UMONITOR). 
115    /// The UMONITOR instruction arms address monitoring hardware using an address specified in the source register (the address range that the monitoring hardware checks for store operations can be determined by using the CPUID monitor leaf function, EAX=05H). A store to an address within the specified address range triggers the monitoring hardware. The state of monitor hardware is used by UMWAIT.
116    ///
117    ///
118    /// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/UMONITOR.html).
119    ///
120    /// Supported operand variants:
121    ///
122    /// ```text
123    /// +---+----------+
124    /// | # | Operands |
125    /// +---+----------+
126    /// | 1 | Gpd      |
127    /// | 2 | Gpq      |
128    /// +---+----------+
129    /// ```
130    #[inline]
131    pub fn umonitor<A>(&mut self, op0: A)
132    where Assembler<'a>: UmonitorEmitter<A> {
133        <Self as UmonitorEmitter<A>>::umonitor(self, op0);
134    }
135    /// `UMWAIT` (UMWAIT). 
136    /// UMWAIT instructs the processor to enter an implementation-dependent optimized state while monitoring a range of addresses. The optimized state may be either a light-weight power/performance optimized state or an improved power/performance optimized state. The selection between the two states is governed by the explicit input register bit[0] source operand.
137    ///
138    ///
139    /// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/UMWAIT.html).
140    ///
141    /// Supported operand variants:
142    ///
143    /// ```text
144    /// +---+----------+
145    /// | # | Operands |
146    /// +---+----------+
147    /// | 1 | Gpd      |
148    /// +---+----------+
149    /// ```
150    #[inline]
151    pub fn umwait<A>(&mut self, op0: A)
152    where Assembler<'a>: UmwaitEmitter<A> {
153        <Self as UmwaitEmitter<A>>::umwait(self, op0);
154    }
155}
asmkit/x86/features/WAITPKG.rs

asmkit/x86/features/
WAITPKG.rs
