asmkit/x86/features/
INVPCID.rs

1use crate::x86::assembler::*;
2use crate::x86::operands::*;
3use super::super::opcodes::*;
4use crate::core::emitter::*;
5use crate::core::operand::*;
6
7/// A dummy operand that represents no register. Here just for simplicity.
8const NOREG: Operand = Operand::new();
9
10/// `INVPCID` (INVPCID). 
11/// Invalidates mappings in the translation lookaside buffers (TLBs) and paging-structure caches based on process-context identifier (PCID). (See Section 4.10, “Caching Translation Information,” in the Intel 64 and IA-32 Architecture Software Developer’s Manual, Volume 3A.) Invalidation is based on the INVPCID type specified in the register operand and the INVPCID descriptor specified in the memory operand.
12///
13///
14/// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/INVPCID.html).
15///
16/// Supported operand variants:
17///
18/// ```text
19/// +---+----------+
20/// | # | Operands |
21/// +---+----------+
22/// | 1 | Gpq, Mem |
23/// +---+----------+
24/// ```
25pub trait InvpcidEmitter<A, B> {
26    fn invpcid(&mut self, op0: A, op1: B);
27}
28
29impl<'a> InvpcidEmitter<Gpq, Mem> for Assembler<'a> {
30    fn invpcid(&mut self, op0: Gpq, op1: Mem) {
31        self.emit(INVPCIDRM, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
32    }
33}
34
35
36impl<'a> Assembler<'a> {
37    /// `INVPCID` (INVPCID). 
38    /// Invalidates mappings in the translation lookaside buffers (TLBs) and paging-structure caches based on process-context identifier (PCID). (See Section 4.10, “Caching Translation Information,” in the Intel 64 and IA-32 Architecture Software Developer’s Manual, Volume 3A.) Invalidation is based on the INVPCID type specified in the register operand and the INVPCID descriptor specified in the memory operand.
39    ///
40    ///
41    /// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/INVPCID.html).
42    ///
43    /// Supported operand variants:
44    ///
45    /// ```text
46    /// +---+----------+
47    /// | # | Operands |
48    /// +---+----------+
49    /// | 1 | Gpq, Mem |
50    /// +---+----------+
51    /// ```
52    #[inline]
53    pub fn invpcid<A, B>(&mut self, op0: A, op1: B)
54    where Assembler<'a>: InvpcidEmitter<A, B> {
55        <Self as InvpcidEmitter<A, B>>::invpcid(self, op0, op1);
56    }
57}
asmkit/x86/features/INVPCID.rs

asmkit/x86/features/
INVPCID.rs
