asmkit/x86/features/
CLDEMOTE.rs

1use crate::x86::assembler::*;
2use crate::x86::operands::*;
3use super::super::opcodes::*;
4use crate::core::emitter::*;
5use crate::core::operand::*;
6
7/// A dummy operand that represents no register. Here just for simplicity.
8const NOREG: Operand = Operand::new();
9
10/// `CLDEMOTE` (CLDEMOTE). 
11/// Hints to hardware that the cache line that contains the linear address specified with the memory operand should be moved (“demoted”) from the cache(s) closest to the processor core to a level more distant from the processor core. This may accelerate subsequent accesses to the line by other cores in the same coherence domain, especially if the line was written by the core that demotes the line. Moving the line in such a manner is a performance optimization, i.e., it is a hint which does not modify architectural state. Hardware may choose which level in the cache hierarchy to retain the line (e.g., L3 in typical server designs). The source operand is a byte memory location.
12///
13///
14/// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/CLDEMOTE.html).
15///
16/// Supported operand variants:
17///
18/// ```text
19/// +---+----------+
20/// | # | Operands |
21/// +---+----------+
22/// | 1 | Mem      |
23/// +---+----------+
24/// ```
25pub trait CldemoteEmitter<A> {
26    fn cldemote(&mut self, op0: A);
27}
28
29impl<'a> CldemoteEmitter<Mem> for Assembler<'a> {
30    fn cldemote(&mut self, op0: Mem) {
31        self.emit(CLDEMOTEM, op0.as_operand(), &NOREG, &NOREG, &NOREG);
32    }
33}
34
35
36impl<'a> Assembler<'a> {
37    /// `CLDEMOTE` (CLDEMOTE). 
38    /// Hints to hardware that the cache line that contains the linear address specified with the memory operand should be moved (“demoted”) from the cache(s) closest to the processor core to a level more distant from the processor core. This may accelerate subsequent accesses to the line by other cores in the same coherence domain, especially if the line was written by the core that demotes the line. Moving the line in such a manner is a performance optimization, i.e., it is a hint which does not modify architectural state. Hardware may choose which level in the cache hierarchy to retain the line (e.g., L3 in typical server designs). The source operand is a byte memory location.
39    ///
40    ///
41    /// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/CLDEMOTE.html).
42    ///
43    /// Supported operand variants:
44    ///
45    /// ```text
46    /// +---+----------+
47    /// | # | Operands |
48    /// +---+----------+
49    /// | 1 | Mem      |
50    /// +---+----------+
51    /// ```
52    #[inline]
53    pub fn cldemote<A>(&mut self, op0: A)
54    where Assembler<'a>: CldemoteEmitter<A> {
55        <Self as CldemoteEmitter<A>>::cldemote(self, op0);
56    }
57}
asmkit/x86/features/CLDEMOTE.rs

asmkit/x86/features/
CLDEMOTE.rs
