asmkit/x86/features/
AVX512_VP2INTERSECT.rs

1use crate::x86::assembler::*;
2use crate::x86::operands::*;
3use super::super::opcodes::*;
4use crate::core::emitter::*;
5use crate::core::operand::*;
6
7/// A dummy operand that represents no register. Here just for simplicity.
8const NOREG: Operand = Operand::new();
9
10/// `VP2INTERSECTD` (VP2INTERSECTD). 
11/// This instruction writes an even/odd pair of mask registers. The mask register destination indicated in the MODRM.REG field is used to form the basis of the register pair. The low bit of that field is masked off (set to zero) to create the first register of the pair.
12///
13///
14/// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VP2INTERSECTD%3AVP2INTERSECTQ.html).
15///
16/// Supported operand variants:
17///
18/// ```text
19/// +---+----------------+
20/// | # | Operands       |
21/// +---+----------------+
22/// | 1 | KReg, Xmm, Mem |
23/// | 2 | KReg, Xmm, Xmm |
24/// | 3 | KReg, Ymm, Mem |
25/// | 4 | KReg, Ymm, Ymm |
26/// | 5 | KReg, Zmm, Mem |
27/// | 6 | KReg, Zmm, Zmm |
28/// +---+----------------+
29/// ```
30pub trait Vp2intersectdEmitter<A, B, C> {
31    fn vp2intersectd(&mut self, op0: A, op1: B, op2: C);
32}
33
34impl<'a> Vp2intersectdEmitter<KReg, Xmm, Xmm> for Assembler<'a> {
35    fn vp2intersectd(&mut self, op0: KReg, op1: Xmm, op2: Xmm) {
36        self.emit(VP2INTERSECTD128KRR, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
37    }
38}
39
40impl<'a> Vp2intersectdEmitter<KReg, Xmm, Mem> for Assembler<'a> {
41    fn vp2intersectd(&mut self, op0: KReg, op1: Xmm, op2: Mem) {
42        self.emit(VP2INTERSECTD128KRM, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
43    }
44}
45
46impl<'a> Vp2intersectdEmitter<KReg, Ymm, Ymm> for Assembler<'a> {
47    fn vp2intersectd(&mut self, op0: KReg, op1: Ymm, op2: Ymm) {
48        self.emit(VP2INTERSECTD256KRR, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
49    }
50}
51
52impl<'a> Vp2intersectdEmitter<KReg, Ymm, Mem> for Assembler<'a> {
53    fn vp2intersectd(&mut self, op0: KReg, op1: Ymm, op2: Mem) {
54        self.emit(VP2INTERSECTD256KRM, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
55    }
56}
57
58impl<'a> Vp2intersectdEmitter<KReg, Zmm, Zmm> for Assembler<'a> {
59    fn vp2intersectd(&mut self, op0: KReg, op1: Zmm, op2: Zmm) {
60        self.emit(VP2INTERSECTD512KRR, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
61    }
62}
63
64impl<'a> Vp2intersectdEmitter<KReg, Zmm, Mem> for Assembler<'a> {
65    fn vp2intersectd(&mut self, op0: KReg, op1: Zmm, op2: Mem) {
66        self.emit(VP2INTERSECTD512KRM, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
67    }
68}
69
70/// `VP2INTERSECTQ` (VP2INTERSECTQ). 
71/// This instruction writes an even/odd pair of mask registers. The mask register destination indicated in the MODRM.REG field is used to form the basis of the register pair. The low bit of that field is masked off (set to zero) to create the first register of the pair.
72///
73///
74/// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VP2INTERSECTD%3AVP2INTERSECTQ.html).
75///
76/// Supported operand variants:
77///
78/// ```text
79/// +---+----------------+
80/// | # | Operands       |
81/// +---+----------------+
82/// | 1 | KReg, Xmm, Mem |
83/// | 2 | KReg, Xmm, Xmm |
84/// | 3 | KReg, Ymm, Mem |
85/// | 4 | KReg, Ymm, Ymm |
86/// | 5 | KReg, Zmm, Mem |
87/// | 6 | KReg, Zmm, Zmm |
88/// +---+----------------+
89/// ```
90pub trait Vp2intersectqEmitter<A, B, C> {
91    fn vp2intersectq(&mut self, op0: A, op1: B, op2: C);
92}
93
94impl<'a> Vp2intersectqEmitter<KReg, Xmm, Xmm> for Assembler<'a> {
95    fn vp2intersectq(&mut self, op0: KReg, op1: Xmm, op2: Xmm) {
96        self.emit(VP2INTERSECTQ128KRR, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
97    }
98}
99
100impl<'a> Vp2intersectqEmitter<KReg, Xmm, Mem> for Assembler<'a> {
101    fn vp2intersectq(&mut self, op0: KReg, op1: Xmm, op2: Mem) {
102        self.emit(VP2INTERSECTQ128KRM, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
103    }
104}
105
106impl<'a> Vp2intersectqEmitter<KReg, Ymm, Ymm> for Assembler<'a> {
107    fn vp2intersectq(&mut self, op0: KReg, op1: Ymm, op2: Ymm) {
108        self.emit(VP2INTERSECTQ256KRR, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
109    }
110}
111
112impl<'a> Vp2intersectqEmitter<KReg, Ymm, Mem> for Assembler<'a> {
113    fn vp2intersectq(&mut self, op0: KReg, op1: Ymm, op2: Mem) {
114        self.emit(VP2INTERSECTQ256KRM, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
115    }
116}
117
118impl<'a> Vp2intersectqEmitter<KReg, Zmm, Zmm> for Assembler<'a> {
119    fn vp2intersectq(&mut self, op0: KReg, op1: Zmm, op2: Zmm) {
120        self.emit(VP2INTERSECTQ512KRR, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
121    }
122}
123
124impl<'a> Vp2intersectqEmitter<KReg, Zmm, Mem> for Assembler<'a> {
125    fn vp2intersectq(&mut self, op0: KReg, op1: Zmm, op2: Mem) {
126        self.emit(VP2INTERSECTQ512KRM, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
127    }
128}
129
130
131impl<'a> Assembler<'a> {
132    /// `VP2INTERSECTD` (VP2INTERSECTD). 
133    /// This instruction writes an even/odd pair of mask registers. The mask register destination indicated in the MODRM.REG field is used to form the basis of the register pair. The low bit of that field is masked off (set to zero) to create the first register of the pair.
134    ///
135    ///
136    /// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VP2INTERSECTD%3AVP2INTERSECTQ.html).
137    ///
138    /// Supported operand variants:
139    ///
140    /// ```text
141    /// +---+----------------+
142    /// | # | Operands       |
143    /// +---+----------------+
144    /// | 1 | KReg, Xmm, Mem |
145    /// | 2 | KReg, Xmm, Xmm |
146    /// | 3 | KReg, Ymm, Mem |
147    /// | 4 | KReg, Ymm, Ymm |
148    /// | 5 | KReg, Zmm, Mem |
149    /// | 6 | KReg, Zmm, Zmm |
150    /// +---+----------------+
151    /// ```
152    #[inline]
153    pub fn vp2intersectd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
154    where Assembler<'a>: Vp2intersectdEmitter<A, B, C> {
155        <Self as Vp2intersectdEmitter<A, B, C>>::vp2intersectd(self, op0, op1, op2);
156    }
157    /// `VP2INTERSECTQ` (VP2INTERSECTQ). 
158    /// This instruction writes an even/odd pair of mask registers. The mask register destination indicated in the MODRM.REG field is used to form the basis of the register pair. The low bit of that field is masked off (set to zero) to create the first register of the pair.
159    ///
160    ///
161    /// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VP2INTERSECTD%3AVP2INTERSECTQ.html).
162    ///
163    /// Supported operand variants:
164    ///
165    /// ```text
166    /// +---+----------------+
167    /// | # | Operands       |
168    /// +---+----------------+
169    /// | 1 | KReg, Xmm, Mem |
170    /// | 2 | KReg, Xmm, Xmm |
171    /// | 3 | KReg, Ymm, Mem |
172    /// | 4 | KReg, Ymm, Ymm |
173    /// | 5 | KReg, Zmm, Mem |
174    /// | 6 | KReg, Zmm, Zmm |
175    /// +---+----------------+
176    /// ```
177    #[inline]
178    pub fn vp2intersectq<A, B, C>(&mut self, op0: A, op1: B, op2: C)
179    where Assembler<'a>: Vp2intersectqEmitter<A, B, C> {
180        <Self as Vp2intersectqEmitter<A, B, C>>::vp2intersectq(self, op0, op1, op2);
181    }
182}
asmkit/x86/features/AVX512_VP2INTERSECT.rs

asmkit/x86/features/
AVX512_VP2INTERSECT.rs
