asmkit/x86/features/AVX512_IFMA.rs
1use crate::x86::assembler::*;
2use crate::x86::operands::*;
3use super::super::opcodes::*;
4use crate::core::emitter::*;
5use crate::core::operand::*;
6
7/// A dummy operand that represents no register. Here just for simplicity.
8const NOREG: Operand = Operand::new();
9
10/// `VPMADD52HUQ` (VPMADD52HUQ).
11/// Multiplies packed unsigned 52-bit integers in each qword element of the first source operand (the second operand) with the packed unsigned 52-bit integers in the corresponding elements of the second source operand (the third operand) to form packed 104-bit intermediate results. The high 52-bit, unsigned integer of each 104-bit product is added to the corresponding qword unsigned integer of the destination operand (the first operand) under the writemask k1.
12///
13///
14/// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VPMADD52HUQ.html).
15///
16/// Supported operand variants:
17///
18/// ```text
19/// +---+---------------+
20/// | # | Operands |
21/// +---+---------------+
22/// | 1 | Xmm, Xmm, Mem |
23/// | 2 | Xmm, Xmm, Xmm |
24/// | 3 | Ymm, Ymm, Mem |
25/// | 4 | Ymm, Ymm, Ymm |
26/// | 5 | Zmm, Zmm, Mem |
27/// | 6 | Zmm, Zmm, Zmm |
28/// +---+---------------+
29/// ```
30pub trait Vpmadd52huqEmitter<A, B, C> {
31 fn vpmadd52huq(&mut self, op0: A, op1: B, op2: C);
32}
33
34impl<'a> Vpmadd52huqEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
35 fn vpmadd52huq(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
36 self.emit(VPMADD52HUQ128RRR, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
37 }
38}
39
40impl<'a> Vpmadd52huqEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
41 fn vpmadd52huq(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
42 self.emit(VPMADD52HUQ128RRM, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
43 }
44}
45
46impl<'a> Vpmadd52huqEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
47 fn vpmadd52huq(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
48 self.emit(VPMADD52HUQ256RRR, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
49 }
50}
51
52impl<'a> Vpmadd52huqEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
53 fn vpmadd52huq(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
54 self.emit(VPMADD52HUQ256RRM, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
55 }
56}
57
58impl<'a> Vpmadd52huqEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
59 fn vpmadd52huq(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
60 self.emit(VPMADD52HUQ512RRR, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
61 }
62}
63
64impl<'a> Vpmadd52huqEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
65 fn vpmadd52huq(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
66 self.emit(VPMADD52HUQ512RRM, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
67 }
68}
69
70/// `VPMADD52HUQ_MASK` (VPMADD52HUQ).
71/// Multiplies packed unsigned 52-bit integers in each qword element of the first source operand (the second operand) with the packed unsigned 52-bit integers in the corresponding elements of the second source operand (the third operand) to form packed 104-bit intermediate results. The high 52-bit, unsigned integer of each 104-bit product is added to the corresponding qword unsigned integer of the destination operand (the first operand) under the writemask k1.
72///
73///
74/// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VPMADD52HUQ.html).
75///
76/// Supported operand variants:
77///
78/// ```text
79/// +---+---------------+
80/// | # | Operands |
81/// +---+---------------+
82/// | 1 | Xmm, Xmm, Mem |
83/// | 2 | Xmm, Xmm, Xmm |
84/// | 3 | Ymm, Ymm, Mem |
85/// | 4 | Ymm, Ymm, Ymm |
86/// | 5 | Zmm, Zmm, Mem |
87/// | 6 | Zmm, Zmm, Zmm |
88/// +---+---------------+
89/// ```
90pub trait Vpmadd52huqMaskEmitter<A, B, C> {
91 fn vpmadd52huq_mask(&mut self, op0: A, op1: B, op2: C);
92}
93
94impl<'a> Vpmadd52huqMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
95 fn vpmadd52huq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
96 self.emit(VPMADD52HUQ128RRR_MASK, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
97 }
98}
99
100impl<'a> Vpmadd52huqMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
101 fn vpmadd52huq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
102 self.emit(VPMADD52HUQ128RRM_MASK, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
103 }
104}
105
106impl<'a> Vpmadd52huqMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
107 fn vpmadd52huq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
108 self.emit(VPMADD52HUQ256RRR_MASK, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
109 }
110}
111
112impl<'a> Vpmadd52huqMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
113 fn vpmadd52huq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
114 self.emit(VPMADD52HUQ256RRM_MASK, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
115 }
116}
117
118impl<'a> Vpmadd52huqMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
119 fn vpmadd52huq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
120 self.emit(VPMADD52HUQ512RRR_MASK, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
121 }
122}
123
124impl<'a> Vpmadd52huqMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
125 fn vpmadd52huq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
126 self.emit(VPMADD52HUQ512RRM_MASK, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
127 }
128}
129
130/// `VPMADD52HUQ_MASKZ` (VPMADD52HUQ).
131/// Multiplies packed unsigned 52-bit integers in each qword element of the first source operand (the second operand) with the packed unsigned 52-bit integers in the corresponding elements of the second source operand (the third operand) to form packed 104-bit intermediate results. The high 52-bit, unsigned integer of each 104-bit product is added to the corresponding qword unsigned integer of the destination operand (the first operand) under the writemask k1.
132///
133///
134/// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VPMADD52HUQ.html).
135///
136/// Supported operand variants:
137///
138/// ```text
139/// +---+---------------+
140/// | # | Operands |
141/// +---+---------------+
142/// | 1 | Xmm, Xmm, Mem |
143/// | 2 | Xmm, Xmm, Xmm |
144/// | 3 | Ymm, Ymm, Mem |
145/// | 4 | Ymm, Ymm, Ymm |
146/// | 5 | Zmm, Zmm, Mem |
147/// | 6 | Zmm, Zmm, Zmm |
148/// +---+---------------+
149/// ```
150pub trait Vpmadd52huqMaskzEmitter<A, B, C> {
151 fn vpmadd52huq_maskz(&mut self, op0: A, op1: B, op2: C);
152}
153
154impl<'a> Vpmadd52huqMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
155 fn vpmadd52huq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
156 self.emit(VPMADD52HUQ128RRR_MASKZ, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
157 }
158}
159
160impl<'a> Vpmadd52huqMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
161 fn vpmadd52huq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
162 self.emit(VPMADD52HUQ128RRM_MASKZ, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
163 }
164}
165
166impl<'a> Vpmadd52huqMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
167 fn vpmadd52huq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
168 self.emit(VPMADD52HUQ256RRR_MASKZ, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
169 }
170}
171
172impl<'a> Vpmadd52huqMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
173 fn vpmadd52huq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
174 self.emit(VPMADD52HUQ256RRM_MASKZ, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
175 }
176}
177
178impl<'a> Vpmadd52huqMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
179 fn vpmadd52huq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
180 self.emit(VPMADD52HUQ512RRR_MASKZ, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
181 }
182}
183
184impl<'a> Vpmadd52huqMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
185 fn vpmadd52huq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
186 self.emit(VPMADD52HUQ512RRM_MASKZ, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
187 }
188}
189
190/// `VPMADD52LUQ` (VPMADD52LUQ).
191/// Multiplies packed unsigned 52-bit integers in each qword element of the first source operand (the second operand) with the packed unsigned 52-bit integers in the corresponding elements of the second source operand (the third operand) to form packed 104-bit intermediate results. The low 52-bit, unsigned integer of each 104-bit product is added to the corresponding qword unsigned integer of the destination operand (the first operand) under the writemask k1.
192///
193///
194/// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VPMADD52LUQ.html).
195///
196/// Supported operand variants:
197///
198/// ```text
199/// +---+---------------+
200/// | # | Operands |
201/// +---+---------------+
202/// | 1 | Xmm, Xmm, Mem |
203/// | 2 | Xmm, Xmm, Xmm |
204/// | 3 | Ymm, Ymm, Mem |
205/// | 4 | Ymm, Ymm, Ymm |
206/// | 5 | Zmm, Zmm, Mem |
207/// | 6 | Zmm, Zmm, Zmm |
208/// +---+---------------+
209/// ```
210pub trait Vpmadd52luqEmitter<A, B, C> {
211 fn vpmadd52luq(&mut self, op0: A, op1: B, op2: C);
212}
213
214impl<'a> Vpmadd52luqEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
215 fn vpmadd52luq(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
216 self.emit(VPMADD52LUQ128RRR, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
217 }
218}
219
220impl<'a> Vpmadd52luqEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
221 fn vpmadd52luq(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
222 self.emit(VPMADD52LUQ128RRM, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
223 }
224}
225
226impl<'a> Vpmadd52luqEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
227 fn vpmadd52luq(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
228 self.emit(VPMADD52LUQ256RRR, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
229 }
230}
231
232impl<'a> Vpmadd52luqEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
233 fn vpmadd52luq(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
234 self.emit(VPMADD52LUQ256RRM, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
235 }
236}
237
238impl<'a> Vpmadd52luqEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
239 fn vpmadd52luq(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
240 self.emit(VPMADD52LUQ512RRR, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
241 }
242}
243
244impl<'a> Vpmadd52luqEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
245 fn vpmadd52luq(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
246 self.emit(VPMADD52LUQ512RRM, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
247 }
248}
249
250/// `VPMADD52LUQ_MASK` (VPMADD52LUQ).
251/// Multiplies packed unsigned 52-bit integers in each qword element of the first source operand (the second operand) with the packed unsigned 52-bit integers in the corresponding elements of the second source operand (the third operand) to form packed 104-bit intermediate results. The low 52-bit, unsigned integer of each 104-bit product is added to the corresponding qword unsigned integer of the destination operand (the first operand) under the writemask k1.
252///
253///
254/// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VPMADD52LUQ.html).
255///
256/// Supported operand variants:
257///
258/// ```text
259/// +---+---------------+
260/// | # | Operands |
261/// +---+---------------+
262/// | 1 | Xmm, Xmm, Mem |
263/// | 2 | Xmm, Xmm, Xmm |
264/// | 3 | Ymm, Ymm, Mem |
265/// | 4 | Ymm, Ymm, Ymm |
266/// | 5 | Zmm, Zmm, Mem |
267/// | 6 | Zmm, Zmm, Zmm |
268/// +---+---------------+
269/// ```
270pub trait Vpmadd52luqMaskEmitter<A, B, C> {
271 fn vpmadd52luq_mask(&mut self, op0: A, op1: B, op2: C);
272}
273
274impl<'a> Vpmadd52luqMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
275 fn vpmadd52luq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
276 self.emit(VPMADD52LUQ128RRR_MASK, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
277 }
278}
279
280impl<'a> Vpmadd52luqMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
281 fn vpmadd52luq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
282 self.emit(VPMADD52LUQ128RRM_MASK, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
283 }
284}
285
286impl<'a> Vpmadd52luqMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
287 fn vpmadd52luq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
288 self.emit(VPMADD52LUQ256RRR_MASK, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
289 }
290}
291
292impl<'a> Vpmadd52luqMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
293 fn vpmadd52luq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
294 self.emit(VPMADD52LUQ256RRM_MASK, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
295 }
296}
297
298impl<'a> Vpmadd52luqMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
299 fn vpmadd52luq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
300 self.emit(VPMADD52LUQ512RRR_MASK, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
301 }
302}
303
304impl<'a> Vpmadd52luqMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
305 fn vpmadd52luq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
306 self.emit(VPMADD52LUQ512RRM_MASK, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
307 }
308}
309
310/// `VPMADD52LUQ_MASKZ` (VPMADD52LUQ).
311/// Multiplies packed unsigned 52-bit integers in each qword element of the first source operand (the second operand) with the packed unsigned 52-bit integers in the corresponding elements of the second source operand (the third operand) to form packed 104-bit intermediate results. The low 52-bit, unsigned integer of each 104-bit product is added to the corresponding qword unsigned integer of the destination operand (the first operand) under the writemask k1.
312///
313///
314/// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VPMADD52LUQ.html).
315///
316/// Supported operand variants:
317///
318/// ```text
319/// +---+---------------+
320/// | # | Operands |
321/// +---+---------------+
322/// | 1 | Xmm, Xmm, Mem |
323/// | 2 | Xmm, Xmm, Xmm |
324/// | 3 | Ymm, Ymm, Mem |
325/// | 4 | Ymm, Ymm, Ymm |
326/// | 5 | Zmm, Zmm, Mem |
327/// | 6 | Zmm, Zmm, Zmm |
328/// +---+---------------+
329/// ```
330pub trait Vpmadd52luqMaskzEmitter<A, B, C> {
331 fn vpmadd52luq_maskz(&mut self, op0: A, op1: B, op2: C);
332}
333
334impl<'a> Vpmadd52luqMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
335 fn vpmadd52luq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
336 self.emit(VPMADD52LUQ128RRR_MASKZ, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
337 }
338}
339
340impl<'a> Vpmadd52luqMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
341 fn vpmadd52luq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
342 self.emit(VPMADD52LUQ128RRM_MASKZ, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
343 }
344}
345
346impl<'a> Vpmadd52luqMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
347 fn vpmadd52luq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
348 self.emit(VPMADD52LUQ256RRR_MASKZ, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
349 }
350}
351
352impl<'a> Vpmadd52luqMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
353 fn vpmadd52luq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
354 self.emit(VPMADD52LUQ256RRM_MASKZ, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
355 }
356}
357
358impl<'a> Vpmadd52luqMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
359 fn vpmadd52luq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
360 self.emit(VPMADD52LUQ512RRR_MASKZ, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
361 }
362}
363
364impl<'a> Vpmadd52luqMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
365 fn vpmadd52luq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
366 self.emit(VPMADD52LUQ512RRM_MASKZ, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
367 }
368}
369
370
371impl<'a> Assembler<'a> {
372 /// `VPMADD52HUQ` (VPMADD52HUQ).
373 /// Multiplies packed unsigned 52-bit integers in each qword element of the first source operand (the second operand) with the packed unsigned 52-bit integers in the corresponding elements of the second source operand (the third operand) to form packed 104-bit intermediate results. The high 52-bit, unsigned integer of each 104-bit product is added to the corresponding qword unsigned integer of the destination operand (the first operand) under the writemask k1.
374 ///
375 ///
376 /// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VPMADD52HUQ.html).
377 ///
378 /// Supported operand variants:
379 ///
380 /// ```text
381 /// +---+---------------+
382 /// | # | Operands |
383 /// +---+---------------+
384 /// | 1 | Xmm, Xmm, Mem |
385 /// | 2 | Xmm, Xmm, Xmm |
386 /// | 3 | Ymm, Ymm, Mem |
387 /// | 4 | Ymm, Ymm, Ymm |
388 /// | 5 | Zmm, Zmm, Mem |
389 /// | 6 | Zmm, Zmm, Zmm |
390 /// +---+---------------+
391 /// ```
392 #[inline]
393 pub fn vpmadd52huq<A, B, C>(&mut self, op0: A, op1: B, op2: C)
394 where Assembler<'a>: Vpmadd52huqEmitter<A, B, C> {
395 <Self as Vpmadd52huqEmitter<A, B, C>>::vpmadd52huq(self, op0, op1, op2);
396 }
397 /// `VPMADD52HUQ_MASK` (VPMADD52HUQ).
398 /// Multiplies packed unsigned 52-bit integers in each qword element of the first source operand (the second operand) with the packed unsigned 52-bit integers in the corresponding elements of the second source operand (the third operand) to form packed 104-bit intermediate results. The high 52-bit, unsigned integer of each 104-bit product is added to the corresponding qword unsigned integer of the destination operand (the first operand) under the writemask k1.
399 ///
400 ///
401 /// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VPMADD52HUQ.html).
402 ///
403 /// Supported operand variants:
404 ///
405 /// ```text
406 /// +---+---------------+
407 /// | # | Operands |
408 /// +---+---------------+
409 /// | 1 | Xmm, Xmm, Mem |
410 /// | 2 | Xmm, Xmm, Xmm |
411 /// | 3 | Ymm, Ymm, Mem |
412 /// | 4 | Ymm, Ymm, Ymm |
413 /// | 5 | Zmm, Zmm, Mem |
414 /// | 6 | Zmm, Zmm, Zmm |
415 /// +---+---------------+
416 /// ```
417 #[inline]
418 pub fn vpmadd52huq_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
419 where Assembler<'a>: Vpmadd52huqMaskEmitter<A, B, C> {
420 <Self as Vpmadd52huqMaskEmitter<A, B, C>>::vpmadd52huq_mask(self, op0, op1, op2);
421 }
422 /// `VPMADD52HUQ_MASKZ` (VPMADD52HUQ).
423 /// Multiplies packed unsigned 52-bit integers in each qword element of the first source operand (the second operand) with the packed unsigned 52-bit integers in the corresponding elements of the second source operand (the third operand) to form packed 104-bit intermediate results. The high 52-bit, unsigned integer of each 104-bit product is added to the corresponding qword unsigned integer of the destination operand (the first operand) under the writemask k1.
424 ///
425 ///
426 /// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VPMADD52HUQ.html).
427 ///
428 /// Supported operand variants:
429 ///
430 /// ```text
431 /// +---+---------------+
432 /// | # | Operands |
433 /// +---+---------------+
434 /// | 1 | Xmm, Xmm, Mem |
435 /// | 2 | Xmm, Xmm, Xmm |
436 /// | 3 | Ymm, Ymm, Mem |
437 /// | 4 | Ymm, Ymm, Ymm |
438 /// | 5 | Zmm, Zmm, Mem |
439 /// | 6 | Zmm, Zmm, Zmm |
440 /// +---+---------------+
441 /// ```
442 #[inline]
443 pub fn vpmadd52huq_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
444 where Assembler<'a>: Vpmadd52huqMaskzEmitter<A, B, C> {
445 <Self as Vpmadd52huqMaskzEmitter<A, B, C>>::vpmadd52huq_maskz(self, op0, op1, op2);
446 }
447 /// `VPMADD52LUQ` (VPMADD52LUQ).
448 /// Multiplies packed unsigned 52-bit integers in each qword element of the first source operand (the second operand) with the packed unsigned 52-bit integers in the corresponding elements of the second source operand (the third operand) to form packed 104-bit intermediate results. The low 52-bit, unsigned integer of each 104-bit product is added to the corresponding qword unsigned integer of the destination operand (the first operand) under the writemask k1.
449 ///
450 ///
451 /// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VPMADD52LUQ.html).
452 ///
453 /// Supported operand variants:
454 ///
455 /// ```text
456 /// +---+---------------+
457 /// | # | Operands |
458 /// +---+---------------+
459 /// | 1 | Xmm, Xmm, Mem |
460 /// | 2 | Xmm, Xmm, Xmm |
461 /// | 3 | Ymm, Ymm, Mem |
462 /// | 4 | Ymm, Ymm, Ymm |
463 /// | 5 | Zmm, Zmm, Mem |
464 /// | 6 | Zmm, Zmm, Zmm |
465 /// +---+---------------+
466 /// ```
467 #[inline]
468 pub fn vpmadd52luq<A, B, C>(&mut self, op0: A, op1: B, op2: C)
469 where Assembler<'a>: Vpmadd52luqEmitter<A, B, C> {
470 <Self as Vpmadd52luqEmitter<A, B, C>>::vpmadd52luq(self, op0, op1, op2);
471 }
472 /// `VPMADD52LUQ_MASK` (VPMADD52LUQ).
473 /// Multiplies packed unsigned 52-bit integers in each qword element of the first source operand (the second operand) with the packed unsigned 52-bit integers in the corresponding elements of the second source operand (the third operand) to form packed 104-bit intermediate results. The low 52-bit, unsigned integer of each 104-bit product is added to the corresponding qword unsigned integer of the destination operand (the first operand) under the writemask k1.
474 ///
475 ///
476 /// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VPMADD52LUQ.html).
477 ///
478 /// Supported operand variants:
479 ///
480 /// ```text
481 /// +---+---------------+
482 /// | # | Operands |
483 /// +---+---------------+
484 /// | 1 | Xmm, Xmm, Mem |
485 /// | 2 | Xmm, Xmm, Xmm |
486 /// | 3 | Ymm, Ymm, Mem |
487 /// | 4 | Ymm, Ymm, Ymm |
488 /// | 5 | Zmm, Zmm, Mem |
489 /// | 6 | Zmm, Zmm, Zmm |
490 /// +---+---------------+
491 /// ```
492 #[inline]
493 pub fn vpmadd52luq_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
494 where Assembler<'a>: Vpmadd52luqMaskEmitter<A, B, C> {
495 <Self as Vpmadd52luqMaskEmitter<A, B, C>>::vpmadd52luq_mask(self, op0, op1, op2);
496 }
497 /// `VPMADD52LUQ_MASKZ` (VPMADD52LUQ).
498 /// Multiplies packed unsigned 52-bit integers in each qword element of the first source operand (the second operand) with the packed unsigned 52-bit integers in the corresponding elements of the second source operand (the third operand) to form packed 104-bit intermediate results. The low 52-bit, unsigned integer of each 104-bit product is added to the corresponding qword unsigned integer of the destination operand (the first operand) under the writemask k1.
499 ///
500 ///
501 /// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VPMADD52LUQ.html).
502 ///
503 /// Supported operand variants:
504 ///
505 /// ```text
506 /// +---+---------------+
507 /// | # | Operands |
508 /// +---+---------------+
509 /// | 1 | Xmm, Xmm, Mem |
510 /// | 2 | Xmm, Xmm, Xmm |
511 /// | 3 | Ymm, Ymm, Mem |
512 /// | 4 | Ymm, Ymm, Ymm |
513 /// | 5 | Zmm, Zmm, Mem |
514 /// | 6 | Zmm, Zmm, Zmm |
515 /// +---+---------------+
516 /// ```
517 #[inline]
518 pub fn vpmadd52luq_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
519 where Assembler<'a>: Vpmadd52luqMaskzEmitter<A, B, C> {
520 <Self as Vpmadd52luqMaskzEmitter<A, B, C>>::vpmadd52luq_maskz(self, op0, op1, op2);
521 }
522}