asmkit/x86/features/
AVX512_BF16.rs

1use crate::x86::assembler::*;
2use crate::x86::operands::*;
3use super::super::opcodes::*;
4use crate::core::emitter::*;
5use crate::core::operand::*;
6
7/// A dummy operand that represents no register. Here just for simplicity.
8const NOREG: Operand = Operand::new();
9
10/// `VCVTNE2PS2BF16` (VCVTNE2PS2BF16). 
11/// Converts two SIMD registers of packed single data into a single register of packed BF16 data.
12///
13///
14/// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VCVTNE2PS2BF16.html).
15///
16/// Supported operand variants:
17///
18/// ```text
19/// +---+---------------+
20/// | # | Operands      |
21/// +---+---------------+
22/// | 1 | Xmm, Xmm, Mem |
23/// | 2 | Xmm, Xmm, Xmm |
24/// | 3 | Ymm, Ymm, Mem |
25/// | 4 | Ymm, Ymm, Ymm |
26/// | 5 | Zmm, Zmm, Mem |
27/// | 6 | Zmm, Zmm, Zmm |
28/// +---+---------------+
29/// ```
30pub trait Vcvtne2ps2bf16Emitter<A, B, C> {
31    fn vcvtne2ps2bf16(&mut self, op0: A, op1: B, op2: C);
32}
33
34impl<'a> Vcvtne2ps2bf16Emitter<Xmm, Xmm, Xmm> for Assembler<'a> {
35    fn vcvtne2ps2bf16(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
36        self.emit(VCVTNE2PS2BF16_128RRR, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
37    }
38}
39
40impl<'a> Vcvtne2ps2bf16Emitter<Xmm, Xmm, Mem> for Assembler<'a> {
41    fn vcvtne2ps2bf16(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
42        self.emit(VCVTNE2PS2BF16_128RRM, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
43    }
44}
45
46impl<'a> Vcvtne2ps2bf16Emitter<Ymm, Ymm, Ymm> for Assembler<'a> {
47    fn vcvtne2ps2bf16(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
48        self.emit(VCVTNE2PS2BF16_256RRR, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
49    }
50}
51
52impl<'a> Vcvtne2ps2bf16Emitter<Ymm, Ymm, Mem> for Assembler<'a> {
53    fn vcvtne2ps2bf16(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
54        self.emit(VCVTNE2PS2BF16_256RRM, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
55    }
56}
57
58impl<'a> Vcvtne2ps2bf16Emitter<Zmm, Zmm, Zmm> for Assembler<'a> {
59    fn vcvtne2ps2bf16(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
60        self.emit(VCVTNE2PS2BF16_512RRR, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
61    }
62}
63
64impl<'a> Vcvtne2ps2bf16Emitter<Zmm, Zmm, Mem> for Assembler<'a> {
65    fn vcvtne2ps2bf16(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
66        self.emit(VCVTNE2PS2BF16_512RRM, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
67    }
68}
69
70/// `VCVTNE2PS2BF16_MASK` (VCVTNE2PS2BF16). 
71/// Converts two SIMD registers of packed single data into a single register of packed BF16 data.
72///
73///
74/// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VCVTNE2PS2BF16.html).
75///
76/// Supported operand variants:
77///
78/// ```text
79/// +---+---------------+
80/// | # | Operands      |
81/// +---+---------------+
82/// | 1 | Xmm, Xmm, Mem |
83/// | 2 | Xmm, Xmm, Xmm |
84/// | 3 | Ymm, Ymm, Mem |
85/// | 4 | Ymm, Ymm, Ymm |
86/// | 5 | Zmm, Zmm, Mem |
87/// | 6 | Zmm, Zmm, Zmm |
88/// +---+---------------+
89/// ```
90pub trait Vcvtne2ps2bf16MaskEmitter<A, B, C> {
91    fn vcvtne2ps2bf16_mask(&mut self, op0: A, op1: B, op2: C);
92}
93
94impl<'a> Vcvtne2ps2bf16MaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
95    fn vcvtne2ps2bf16_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
96        self.emit(VCVTNE2PS2BF16_128RRR_MASK, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
97    }
98}
99
100impl<'a> Vcvtne2ps2bf16MaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
101    fn vcvtne2ps2bf16_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
102        self.emit(VCVTNE2PS2BF16_128RRM_MASK, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
103    }
104}
105
106impl<'a> Vcvtne2ps2bf16MaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
107    fn vcvtne2ps2bf16_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
108        self.emit(VCVTNE2PS2BF16_256RRR_MASK, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
109    }
110}
111
112impl<'a> Vcvtne2ps2bf16MaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
113    fn vcvtne2ps2bf16_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
114        self.emit(VCVTNE2PS2BF16_256RRM_MASK, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
115    }
116}
117
118impl<'a> Vcvtne2ps2bf16MaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
119    fn vcvtne2ps2bf16_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
120        self.emit(VCVTNE2PS2BF16_512RRR_MASK, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
121    }
122}
123
124impl<'a> Vcvtne2ps2bf16MaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
125    fn vcvtne2ps2bf16_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
126        self.emit(VCVTNE2PS2BF16_512RRM_MASK, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
127    }
128}
129
130/// `VCVTNE2PS2BF16_MASKZ` (VCVTNE2PS2BF16). 
131/// Converts two SIMD registers of packed single data into a single register of packed BF16 data.
132///
133///
134/// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VCVTNE2PS2BF16.html).
135///
136/// Supported operand variants:
137///
138/// ```text
139/// +---+---------------+
140/// | # | Operands      |
141/// +---+---------------+
142/// | 1 | Xmm, Xmm, Mem |
143/// | 2 | Xmm, Xmm, Xmm |
144/// | 3 | Ymm, Ymm, Mem |
145/// | 4 | Ymm, Ymm, Ymm |
146/// | 5 | Zmm, Zmm, Mem |
147/// | 6 | Zmm, Zmm, Zmm |
148/// +---+---------------+
149/// ```
150pub trait Vcvtne2ps2bf16MaskzEmitter<A, B, C> {
151    fn vcvtne2ps2bf16_maskz(&mut self, op0: A, op1: B, op2: C);
152}
153
154impl<'a> Vcvtne2ps2bf16MaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
155    fn vcvtne2ps2bf16_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
156        self.emit(VCVTNE2PS2BF16_128RRR_MASKZ, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
157    }
158}
159
160impl<'a> Vcvtne2ps2bf16MaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
161    fn vcvtne2ps2bf16_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
162        self.emit(VCVTNE2PS2BF16_128RRM_MASKZ, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
163    }
164}
165
166impl<'a> Vcvtne2ps2bf16MaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
167    fn vcvtne2ps2bf16_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
168        self.emit(VCVTNE2PS2BF16_256RRR_MASKZ, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
169    }
170}
171
172impl<'a> Vcvtne2ps2bf16MaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
173    fn vcvtne2ps2bf16_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
174        self.emit(VCVTNE2PS2BF16_256RRM_MASKZ, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
175    }
176}
177
178impl<'a> Vcvtne2ps2bf16MaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
179    fn vcvtne2ps2bf16_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
180        self.emit(VCVTNE2PS2BF16_512RRR_MASKZ, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
181    }
182}
183
184impl<'a> Vcvtne2ps2bf16MaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
185    fn vcvtne2ps2bf16_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
186        self.emit(VCVTNE2PS2BF16_512RRM_MASKZ, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
187    }
188}
189
190/// `VCVTNEPS2BF16` (VCVTNEPS2BF16). 
191/// Converts one SIMD register of packed single data into a single register of packed BF16 data.
192///
193///
194/// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VCVTNEPS2BF16.html).
195///
196/// Supported operand variants:
197///
198/// ```text
199/// +---+----------+
200/// | # | Operands |
201/// +---+----------+
202/// | 1 | Xmm, Mem |
203/// | 2 | Xmm, Xmm |
204/// | 3 | Xmm, Ymm |
205/// | 4 | Ymm, Mem |
206/// | 5 | Ymm, Zmm |
207/// +---+----------+
208/// ```
209pub trait Vcvtneps2bf16Emitter<A, B> {
210    fn vcvtneps2bf16(&mut self, op0: A, op1: B);
211}
212
213impl<'a> Vcvtneps2bf16Emitter<Xmm, Xmm> for Assembler<'a> {
214    fn vcvtneps2bf16(&mut self, op0: Xmm, op1: Xmm) {
215        self.emit(VCVTNEPS2BF16_128RR, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
216    }
217}
218
219impl<'a> Vcvtneps2bf16Emitter<Xmm, Mem> for Assembler<'a> {
220    fn vcvtneps2bf16(&mut self, op0: Xmm, op1: Mem) {
221        self.emit(VCVTNEPS2BF16_128RM, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
222    }
223}
224
225impl<'a> Vcvtneps2bf16Emitter<Xmm, Ymm> for Assembler<'a> {
226    fn vcvtneps2bf16(&mut self, op0: Xmm, op1: Ymm) {
227        self.emit(VCVTNEPS2BF16_256RR, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
228    }
229}
230
231impl<'a> Vcvtneps2bf16Emitter<Ymm, Zmm> for Assembler<'a> {
232    fn vcvtneps2bf16(&mut self, op0: Ymm, op1: Zmm) {
233        self.emit(VCVTNEPS2BF16_512RR, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
234    }
235}
236
237impl<'a> Vcvtneps2bf16Emitter<Ymm, Mem> for Assembler<'a> {
238    fn vcvtneps2bf16(&mut self, op0: Ymm, op1: Mem) {
239        self.emit(VCVTNEPS2BF16_512RM, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
240    }
241}
242
243/// `VCVTNEPS2BF16_MASK` (VCVTNEPS2BF16). 
244/// Converts one SIMD register of packed single data into a single register of packed BF16 data.
245///
246///
247/// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VCVTNEPS2BF16.html).
248///
249/// Supported operand variants:
250///
251/// ```text
252/// +---+----------+
253/// | # | Operands |
254/// +---+----------+
255/// | 1 | Xmm, Mem |
256/// | 2 | Xmm, Xmm |
257/// | 3 | Xmm, Ymm |
258/// | 4 | Ymm, Mem |
259/// | 5 | Ymm, Zmm |
260/// +---+----------+
261/// ```
262pub trait Vcvtneps2bf16MaskEmitter<A, B> {
263    fn vcvtneps2bf16_mask(&mut self, op0: A, op1: B);
264}
265
266impl<'a> Vcvtneps2bf16MaskEmitter<Xmm, Xmm> for Assembler<'a> {
267    fn vcvtneps2bf16_mask(&mut self, op0: Xmm, op1: Xmm) {
268        self.emit(VCVTNEPS2BF16_128RR_MASK, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
269    }
270}
271
272impl<'a> Vcvtneps2bf16MaskEmitter<Xmm, Mem> for Assembler<'a> {
273    fn vcvtneps2bf16_mask(&mut self, op0: Xmm, op1: Mem) {
274        self.emit(VCVTNEPS2BF16_128RM_MASK, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
275    }
276}
277
278impl<'a> Vcvtneps2bf16MaskEmitter<Xmm, Ymm> for Assembler<'a> {
279    fn vcvtneps2bf16_mask(&mut self, op0: Xmm, op1: Ymm) {
280        self.emit(VCVTNEPS2BF16_256RR_MASK, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
281    }
282}
283
284impl<'a> Vcvtneps2bf16MaskEmitter<Ymm, Zmm> for Assembler<'a> {
285    fn vcvtneps2bf16_mask(&mut self, op0: Ymm, op1: Zmm) {
286        self.emit(VCVTNEPS2BF16_512RR_MASK, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
287    }
288}
289
290impl<'a> Vcvtneps2bf16MaskEmitter<Ymm, Mem> for Assembler<'a> {
291    fn vcvtneps2bf16_mask(&mut self, op0: Ymm, op1: Mem) {
292        self.emit(VCVTNEPS2BF16_512RM_MASK, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
293    }
294}
295
296/// `VCVTNEPS2BF16_MASKZ` (VCVTNEPS2BF16). 
297/// Converts one SIMD register of packed single data into a single register of packed BF16 data.
298///
299///
300/// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VCVTNEPS2BF16.html).
301///
302/// Supported operand variants:
303///
304/// ```text
305/// +---+----------+
306/// | # | Operands |
307/// +---+----------+
308/// | 1 | Xmm, Mem |
309/// | 2 | Xmm, Xmm |
310/// | 3 | Xmm, Ymm |
311/// | 4 | Ymm, Mem |
312/// | 5 | Ymm, Zmm |
313/// +---+----------+
314/// ```
315pub trait Vcvtneps2bf16MaskzEmitter<A, B> {
316    fn vcvtneps2bf16_maskz(&mut self, op0: A, op1: B);
317}
318
319impl<'a> Vcvtneps2bf16MaskzEmitter<Xmm, Xmm> for Assembler<'a> {
320    fn vcvtneps2bf16_maskz(&mut self, op0: Xmm, op1: Xmm) {
321        self.emit(VCVTNEPS2BF16_128RR_MASKZ, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
322    }
323}
324
325impl<'a> Vcvtneps2bf16MaskzEmitter<Xmm, Mem> for Assembler<'a> {
326    fn vcvtneps2bf16_maskz(&mut self, op0: Xmm, op1: Mem) {
327        self.emit(VCVTNEPS2BF16_128RM_MASKZ, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
328    }
329}
330
331impl<'a> Vcvtneps2bf16MaskzEmitter<Xmm, Ymm> for Assembler<'a> {
332    fn vcvtneps2bf16_maskz(&mut self, op0: Xmm, op1: Ymm) {
333        self.emit(VCVTNEPS2BF16_256RR_MASKZ, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
334    }
335}
336
337impl<'a> Vcvtneps2bf16MaskzEmitter<Ymm, Zmm> for Assembler<'a> {
338    fn vcvtneps2bf16_maskz(&mut self, op0: Ymm, op1: Zmm) {
339        self.emit(VCVTNEPS2BF16_512RR_MASKZ, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
340    }
341}
342
343impl<'a> Vcvtneps2bf16MaskzEmitter<Ymm, Mem> for Assembler<'a> {
344    fn vcvtneps2bf16_maskz(&mut self, op0: Ymm, op1: Mem) {
345        self.emit(VCVTNEPS2BF16_512RM_MASKZ, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
346    }
347}
348
349/// `VDPBF16PS` (VDPBF16PS). 
350/// This instruction performs a SIMD dot-product of two BF16 pairs and accumulates into a packed single precision register.
351///
352///
353/// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VDPBF16PS.html).
354///
355/// Supported operand variants:
356///
357/// ```text
358/// +---+---------------+
359/// | # | Operands      |
360/// +---+---------------+
361/// | 1 | Xmm, Xmm, Mem |
362/// | 2 | Xmm, Xmm, Xmm |
363/// | 3 | Ymm, Ymm, Mem |
364/// | 4 | Ymm, Ymm, Ymm |
365/// | 5 | Zmm, Zmm, Mem |
366/// | 6 | Zmm, Zmm, Zmm |
367/// +---+---------------+
368/// ```
369pub trait Vdpbf16psEmitter<A, B, C> {
370    fn vdpbf16ps(&mut self, op0: A, op1: B, op2: C);
371}
372
373impl<'a> Vdpbf16psEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
374    fn vdpbf16ps(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
375        self.emit(VDPBF16PS128RRR, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
376    }
377}
378
379impl<'a> Vdpbf16psEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
380    fn vdpbf16ps(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
381        self.emit(VDPBF16PS128RRM, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
382    }
383}
384
385impl<'a> Vdpbf16psEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
386    fn vdpbf16ps(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
387        self.emit(VDPBF16PS256RRR, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
388    }
389}
390
391impl<'a> Vdpbf16psEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
392    fn vdpbf16ps(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
393        self.emit(VDPBF16PS256RRM, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
394    }
395}
396
397impl<'a> Vdpbf16psEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
398    fn vdpbf16ps(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
399        self.emit(VDPBF16PS512RRR, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
400    }
401}
402
403impl<'a> Vdpbf16psEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
404    fn vdpbf16ps(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
405        self.emit(VDPBF16PS512RRM, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
406    }
407}
408
409/// `VDPBF16PS_MASK` (VDPBF16PS). 
410/// This instruction performs a SIMD dot-product of two BF16 pairs and accumulates into a packed single precision register.
411///
412///
413/// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VDPBF16PS.html).
414///
415/// Supported operand variants:
416///
417/// ```text
418/// +---+---------------+
419/// | # | Operands      |
420/// +---+---------------+
421/// | 1 | Xmm, Xmm, Mem |
422/// | 2 | Xmm, Xmm, Xmm |
423/// | 3 | Ymm, Ymm, Mem |
424/// | 4 | Ymm, Ymm, Ymm |
425/// | 5 | Zmm, Zmm, Mem |
426/// | 6 | Zmm, Zmm, Zmm |
427/// +---+---------------+
428/// ```
429pub trait Vdpbf16psMaskEmitter<A, B, C> {
430    fn vdpbf16ps_mask(&mut self, op0: A, op1: B, op2: C);
431}
432
433impl<'a> Vdpbf16psMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
434    fn vdpbf16ps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
435        self.emit(VDPBF16PS128RRR_MASK, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
436    }
437}
438
439impl<'a> Vdpbf16psMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
440    fn vdpbf16ps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
441        self.emit(VDPBF16PS128RRM_MASK, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
442    }
443}
444
445impl<'a> Vdpbf16psMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
446    fn vdpbf16ps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
447        self.emit(VDPBF16PS256RRR_MASK, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
448    }
449}
450
451impl<'a> Vdpbf16psMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
452    fn vdpbf16ps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
453        self.emit(VDPBF16PS256RRM_MASK, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
454    }
455}
456
457impl<'a> Vdpbf16psMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
458    fn vdpbf16ps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
459        self.emit(VDPBF16PS512RRR_MASK, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
460    }
461}
462
463impl<'a> Vdpbf16psMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
464    fn vdpbf16ps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
465        self.emit(VDPBF16PS512RRM_MASK, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
466    }
467}
468
469/// `VDPBF16PS_MASKZ` (VDPBF16PS). 
470/// This instruction performs a SIMD dot-product of two BF16 pairs and accumulates into a packed single precision register.
471///
472///
473/// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VDPBF16PS.html).
474///
475/// Supported operand variants:
476///
477/// ```text
478/// +---+---------------+
479/// | # | Operands      |
480/// +---+---------------+
481/// | 1 | Xmm, Xmm, Mem |
482/// | 2 | Xmm, Xmm, Xmm |
483/// | 3 | Ymm, Ymm, Mem |
484/// | 4 | Ymm, Ymm, Ymm |
485/// | 5 | Zmm, Zmm, Mem |
486/// | 6 | Zmm, Zmm, Zmm |
487/// +---+---------------+
488/// ```
489pub trait Vdpbf16psMaskzEmitter<A, B, C> {
490    fn vdpbf16ps_maskz(&mut self, op0: A, op1: B, op2: C);
491}
492
493impl<'a> Vdpbf16psMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
494    fn vdpbf16ps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
495        self.emit(VDPBF16PS128RRR_MASKZ, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
496    }
497}
498
499impl<'a> Vdpbf16psMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
500    fn vdpbf16ps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
501        self.emit(VDPBF16PS128RRM_MASKZ, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
502    }
503}
504
505impl<'a> Vdpbf16psMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
506    fn vdpbf16ps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
507        self.emit(VDPBF16PS256RRR_MASKZ, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
508    }
509}
510
511impl<'a> Vdpbf16psMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
512    fn vdpbf16ps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
513        self.emit(VDPBF16PS256RRM_MASKZ, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
514    }
515}
516
517impl<'a> Vdpbf16psMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
518    fn vdpbf16ps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
519        self.emit(VDPBF16PS512RRR_MASKZ, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
520    }
521}
522
523impl<'a> Vdpbf16psMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
524    fn vdpbf16ps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
525        self.emit(VDPBF16PS512RRM_MASKZ, op0.as_operand(), op1.as_operand(), op2.as_operand(), &NOREG);
526    }
527}
528
529
530impl<'a> Assembler<'a> {
531    /// `VCVTNE2PS2BF16` (VCVTNE2PS2BF16). 
532    /// Converts two SIMD registers of packed single data into a single register of packed BF16 data.
533    ///
534    ///
535    /// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VCVTNE2PS2BF16.html).
536    ///
537    /// Supported operand variants:
538    ///
539    /// ```text
540    /// +---+---------------+
541    /// | # | Operands      |
542    /// +---+---------------+
543    /// | 1 | Xmm, Xmm, Mem |
544    /// | 2 | Xmm, Xmm, Xmm |
545    /// | 3 | Ymm, Ymm, Mem |
546    /// | 4 | Ymm, Ymm, Ymm |
547    /// | 5 | Zmm, Zmm, Mem |
548    /// | 6 | Zmm, Zmm, Zmm |
549    /// +---+---------------+
550    /// ```
551    #[inline]
552    pub fn vcvtne2ps2bf16<A, B, C>(&mut self, op0: A, op1: B, op2: C)
553    where Assembler<'a>: Vcvtne2ps2bf16Emitter<A, B, C> {
554        <Self as Vcvtne2ps2bf16Emitter<A, B, C>>::vcvtne2ps2bf16(self, op0, op1, op2);
555    }
556    /// `VCVTNE2PS2BF16_MASK` (VCVTNE2PS2BF16). 
557    /// Converts two SIMD registers of packed single data into a single register of packed BF16 data.
558    ///
559    ///
560    /// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VCVTNE2PS2BF16.html).
561    ///
562    /// Supported operand variants:
563    ///
564    /// ```text
565    /// +---+---------------+
566    /// | # | Operands      |
567    /// +---+---------------+
568    /// | 1 | Xmm, Xmm, Mem |
569    /// | 2 | Xmm, Xmm, Xmm |
570    /// | 3 | Ymm, Ymm, Mem |
571    /// | 4 | Ymm, Ymm, Ymm |
572    /// | 5 | Zmm, Zmm, Mem |
573    /// | 6 | Zmm, Zmm, Zmm |
574    /// +---+---------------+
575    /// ```
576    #[inline]
577    pub fn vcvtne2ps2bf16_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
578    where Assembler<'a>: Vcvtne2ps2bf16MaskEmitter<A, B, C> {
579        <Self as Vcvtne2ps2bf16MaskEmitter<A, B, C>>::vcvtne2ps2bf16_mask(self, op0, op1, op2);
580    }
581    /// `VCVTNE2PS2BF16_MASKZ` (VCVTNE2PS2BF16). 
582    /// Converts two SIMD registers of packed single data into a single register of packed BF16 data.
583    ///
584    ///
585    /// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VCVTNE2PS2BF16.html).
586    ///
587    /// Supported operand variants:
588    ///
589    /// ```text
590    /// +---+---------------+
591    /// | # | Operands      |
592    /// +---+---------------+
593    /// | 1 | Xmm, Xmm, Mem |
594    /// | 2 | Xmm, Xmm, Xmm |
595    /// | 3 | Ymm, Ymm, Mem |
596    /// | 4 | Ymm, Ymm, Ymm |
597    /// | 5 | Zmm, Zmm, Mem |
598    /// | 6 | Zmm, Zmm, Zmm |
599    /// +---+---------------+
600    /// ```
601    #[inline]
602    pub fn vcvtne2ps2bf16_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
603    where Assembler<'a>: Vcvtne2ps2bf16MaskzEmitter<A, B, C> {
604        <Self as Vcvtne2ps2bf16MaskzEmitter<A, B, C>>::vcvtne2ps2bf16_maskz(self, op0, op1, op2);
605    }
606    /// `VCVTNEPS2BF16` (VCVTNEPS2BF16). 
607    /// Converts one SIMD register of packed single data into a single register of packed BF16 data.
608    ///
609    ///
610    /// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VCVTNEPS2BF16.html).
611    ///
612    /// Supported operand variants:
613    ///
614    /// ```text
615    /// +---+----------+
616    /// | # | Operands |
617    /// +---+----------+
618    /// | 1 | Xmm, Mem |
619    /// | 2 | Xmm, Xmm |
620    /// | 3 | Xmm, Ymm |
621    /// | 4 | Ymm, Mem |
622    /// | 5 | Ymm, Zmm |
623    /// +---+----------+
624    /// ```
625    #[inline]
626    pub fn vcvtneps2bf16<A, B>(&mut self, op0: A, op1: B)
627    where Assembler<'a>: Vcvtneps2bf16Emitter<A, B> {
628        <Self as Vcvtneps2bf16Emitter<A, B>>::vcvtneps2bf16(self, op0, op1);
629    }
630    /// `VCVTNEPS2BF16_MASK` (VCVTNEPS2BF16). 
631    /// Converts one SIMD register of packed single data into a single register of packed BF16 data.
632    ///
633    ///
634    /// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VCVTNEPS2BF16.html).
635    ///
636    /// Supported operand variants:
637    ///
638    /// ```text
639    /// +---+----------+
640    /// | # | Operands |
641    /// +---+----------+
642    /// | 1 | Xmm, Mem |
643    /// | 2 | Xmm, Xmm |
644    /// | 3 | Xmm, Ymm |
645    /// | 4 | Ymm, Mem |
646    /// | 5 | Ymm, Zmm |
647    /// +---+----------+
648    /// ```
649    #[inline]
650    pub fn vcvtneps2bf16_mask<A, B>(&mut self, op0: A, op1: B)
651    where Assembler<'a>: Vcvtneps2bf16MaskEmitter<A, B> {
652        <Self as Vcvtneps2bf16MaskEmitter<A, B>>::vcvtneps2bf16_mask(self, op0, op1);
653    }
654    /// `VCVTNEPS2BF16_MASKZ` (VCVTNEPS2BF16). 
655    /// Converts one SIMD register of packed single data into a single register of packed BF16 data.
656    ///
657    ///
658    /// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VCVTNEPS2BF16.html).
659    ///
660    /// Supported operand variants:
661    ///
662    /// ```text
663    /// +---+----------+
664    /// | # | Operands |
665    /// +---+----------+
666    /// | 1 | Xmm, Mem |
667    /// | 2 | Xmm, Xmm |
668    /// | 3 | Xmm, Ymm |
669    /// | 4 | Ymm, Mem |
670    /// | 5 | Ymm, Zmm |
671    /// +---+----------+
672    /// ```
673    #[inline]
674    pub fn vcvtneps2bf16_maskz<A, B>(&mut self, op0: A, op1: B)
675    where Assembler<'a>: Vcvtneps2bf16MaskzEmitter<A, B> {
676        <Self as Vcvtneps2bf16MaskzEmitter<A, B>>::vcvtneps2bf16_maskz(self, op0, op1);
677    }
678    /// `VDPBF16PS` (VDPBF16PS). 
679    /// This instruction performs a SIMD dot-product of two BF16 pairs and accumulates into a packed single precision register.
680    ///
681    ///
682    /// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VDPBF16PS.html).
683    ///
684    /// Supported operand variants:
685    ///
686    /// ```text
687    /// +---+---------------+
688    /// | # | Operands      |
689    /// +---+---------------+
690    /// | 1 | Xmm, Xmm, Mem |
691    /// | 2 | Xmm, Xmm, Xmm |
692    /// | 3 | Ymm, Ymm, Mem |
693    /// | 4 | Ymm, Ymm, Ymm |
694    /// | 5 | Zmm, Zmm, Mem |
695    /// | 6 | Zmm, Zmm, Zmm |
696    /// +---+---------------+
697    /// ```
698    #[inline]
699    pub fn vdpbf16ps<A, B, C>(&mut self, op0: A, op1: B, op2: C)
700    where Assembler<'a>: Vdpbf16psEmitter<A, B, C> {
701        <Self as Vdpbf16psEmitter<A, B, C>>::vdpbf16ps(self, op0, op1, op2);
702    }
703    /// `VDPBF16PS_MASK` (VDPBF16PS). 
704    /// This instruction performs a SIMD dot-product of two BF16 pairs and accumulates into a packed single precision register.
705    ///
706    ///
707    /// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VDPBF16PS.html).
708    ///
709    /// Supported operand variants:
710    ///
711    /// ```text
712    /// +---+---------------+
713    /// | # | Operands      |
714    /// +---+---------------+
715    /// | 1 | Xmm, Xmm, Mem |
716    /// | 2 | Xmm, Xmm, Xmm |
717    /// | 3 | Ymm, Ymm, Mem |
718    /// | 4 | Ymm, Ymm, Ymm |
719    /// | 5 | Zmm, Zmm, Mem |
720    /// | 6 | Zmm, Zmm, Zmm |
721    /// +---+---------------+
722    /// ```
723    #[inline]
724    pub fn vdpbf16ps_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
725    where Assembler<'a>: Vdpbf16psMaskEmitter<A, B, C> {
726        <Self as Vdpbf16psMaskEmitter<A, B, C>>::vdpbf16ps_mask(self, op0, op1, op2);
727    }
728    /// `VDPBF16PS_MASKZ` (VDPBF16PS). 
729    /// This instruction performs a SIMD dot-product of two BF16 pairs and accumulates into a packed single precision register.
730    ///
731    ///
732    /// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/VDPBF16PS.html).
733    ///
734    /// Supported operand variants:
735    ///
736    /// ```text
737    /// +---+---------------+
738    /// | # | Operands      |
739    /// +---+---------------+
740    /// | 1 | Xmm, Xmm, Mem |
741    /// | 2 | Xmm, Xmm, Xmm |
742    /// | 3 | Ymm, Ymm, Mem |
743    /// | 4 | Ymm, Ymm, Ymm |
744    /// | 5 | Zmm, Zmm, Mem |
745    /// | 6 | Zmm, Zmm, Zmm |
746    /// +---+---------------+
747    /// ```
748    #[inline]
749    pub fn vdpbf16ps_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
750    where Assembler<'a>: Vdpbf16psMaskzEmitter<A, B, C> {
751        <Self as Vdpbf16psMaskzEmitter<A, B, C>>::vdpbf16ps_maskz(self, op0, op1, op2);
752    }
753}
asmkit/x86/features/AVX512_BF16.rs

asmkit/x86/features/
AVX512_BF16.rs
