asmkit/x86/features/ADX.rs
1use crate::x86::assembler::*;
2use crate::x86::operands::*;
3use super::super::opcodes::*;
4use crate::core::emitter::*;
5use crate::core::operand::*;
6
7/// A dummy operand that represents no register. Here just for simplicity.
8const NOREG: Operand = Operand::new();
9
10/// `ADCX` (ADCX).
11/// Performs an unsigned addition of the destination operand (first operand), the source operand (second operand) and the carry-flag (CF) and stores the result in the destination operand. The destination operand is a general-purpose register, whereas the source operand can be a general-purpose register or memory location. The state of CF can represent a carry from a previous addition. The instruction sets the CF flag with the carry generated by the unsigned addition of the operands.
12///
13///
14/// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/ADCX.html).
15///
16/// Supported operand variants:
17///
18/// ```text
19/// +---+----------+
20/// | # | Operands |
21/// +---+----------+
22/// | 1 | Gpd, Gpd |
23/// | 2 | Gpd, Mem |
24/// | 3 | Gpq, Gpq |
25/// | 4 | Gpq, Mem |
26/// +---+----------+
27/// ```
28pub trait AdcxEmitter<A, B> {
29 fn adcx(&mut self, op0: A, op1: B);
30}
31
32impl<'a> AdcxEmitter<Gpd, Gpd> for Assembler<'a> {
33 fn adcx(&mut self, op0: Gpd, op1: Gpd) {
34 self.emit(ADCX32RR, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
35 }
36}
37
38impl<'a> AdcxEmitter<Gpd, Mem> for Assembler<'a> {
39 fn adcx(&mut self, op0: Gpd, op1: Mem) {
40 self.emit(ADCX32RM, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
41 }
42}
43
44impl<'a> AdcxEmitter<Gpq, Gpq> for Assembler<'a> {
45 fn adcx(&mut self, op0: Gpq, op1: Gpq) {
46 self.emit(ADCX64RR, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
47 }
48}
49
50impl<'a> AdcxEmitter<Gpq, Mem> for Assembler<'a> {
51 fn adcx(&mut self, op0: Gpq, op1: Mem) {
52 self.emit(ADCX64RM, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
53 }
54}
55
56/// `ADOX` (ADOX).
57/// Performs an unsigned addition of the destination operand (first operand), the source operand (second operand) and the overflow-flag (OF) and stores the result in the destination operand. The destination operand is a general-purpose register, whereas the source operand can be a general-purpose register or memory location. The state of OF represents a carry from a previous addition. The instruction sets the OF flag with the carry generated by the unsigned addition of the operands.
58///
59///
60/// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/ADOX.html).
61///
62/// Supported operand variants:
63///
64/// ```text
65/// +---+----------+
66/// | # | Operands |
67/// +---+----------+
68/// | 1 | Gpd, Gpd |
69/// | 2 | Gpd, Mem |
70/// | 3 | Gpq, Gpq |
71/// | 4 | Gpq, Mem |
72/// +---+----------+
73/// ```
74pub trait AdoxEmitter<A, B> {
75 fn adox(&mut self, op0: A, op1: B);
76}
77
78impl<'a> AdoxEmitter<Gpd, Gpd> for Assembler<'a> {
79 fn adox(&mut self, op0: Gpd, op1: Gpd) {
80 self.emit(ADOX32RR, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
81 }
82}
83
84impl<'a> AdoxEmitter<Gpd, Mem> for Assembler<'a> {
85 fn adox(&mut self, op0: Gpd, op1: Mem) {
86 self.emit(ADOX32RM, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
87 }
88}
89
90impl<'a> AdoxEmitter<Gpq, Gpq> for Assembler<'a> {
91 fn adox(&mut self, op0: Gpq, op1: Gpq) {
92 self.emit(ADOX64RR, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
93 }
94}
95
96impl<'a> AdoxEmitter<Gpq, Mem> for Assembler<'a> {
97 fn adox(&mut self, op0: Gpq, op1: Mem) {
98 self.emit(ADOX64RM, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
99 }
100}
101
102
103impl<'a> Assembler<'a> {
104 /// `ADCX` (ADCX).
105 /// Performs an unsigned addition of the destination operand (first operand), the source operand (second operand) and the carry-flag (CF) and stores the result in the destination operand. The destination operand is a general-purpose register, whereas the source operand can be a general-purpose register or memory location. The state of CF can represent a carry from a previous addition. The instruction sets the CF flag with the carry generated by the unsigned addition of the operands.
106 ///
107 ///
108 /// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/ADCX.html).
109 ///
110 /// Supported operand variants:
111 ///
112 /// ```text
113 /// +---+----------+
114 /// | # | Operands |
115 /// +---+----------+
116 /// | 1 | Gpd, Gpd |
117 /// | 2 | Gpd, Mem |
118 /// | 3 | Gpq, Gpq |
119 /// | 4 | Gpq, Mem |
120 /// +---+----------+
121 /// ```
122 #[inline]
123 pub fn adcx<A, B>(&mut self, op0: A, op1: B)
124 where Assembler<'a>: AdcxEmitter<A, B> {
125 <Self as AdcxEmitter<A, B>>::adcx(self, op0, op1);
126 }
127 /// `ADOX` (ADOX).
128 /// Performs an unsigned addition of the destination operand (first operand), the source operand (second operand) and the overflow-flag (OF) and stores the result in the destination operand. The destination operand is a general-purpose register, whereas the source operand can be a general-purpose register or memory location. The state of OF represents a carry from a previous addition. The instruction sets the OF flag with the carry generated by the unsigned addition of the operands.
129 ///
130 ///
131 /// For more details, see the [Intel manual](https://www.felixcloutier.com/x86/ADOX.html).
132 ///
133 /// Supported operand variants:
134 ///
135 /// ```text
136 /// +---+----------+
137 /// | # | Operands |
138 /// +---+----------+
139 /// | 1 | Gpd, Gpd |
140 /// | 2 | Gpd, Mem |
141 /// | 3 | Gpq, Gpq |
142 /// | 4 | Gpq, Mem |
143 /// +---+----------+
144 /// ```
145 #[inline]
146 pub fn adox<A, B>(&mut self, op0: A, op1: B)
147 where Assembler<'a>: AdoxEmitter<A, B> {
148 <Self as AdoxEmitter<A, B>>::adox(self, op0, op1);
149 }
150}