asmkit/x86/features/
AVX512_IFMA.rs

1use super::super::opcodes::*;
2use crate::core::emitter::*;
3use crate::core::operand::*;
4use crate::x86::assembler::*;
5use crate::x86::operands::*;
6
7/// A dummy operand that represents no register. Here just for simplicity.
8const NOREG: Operand = Operand::new();
9
10/// `VPMADD52HUQ`.
11///
12/// Supported operand variants:
13///
14/// ```text
15/// +---+---------------+
16/// | # | Operands      |
17/// +---+---------------+
18/// | 1 | Xmm, Xmm, Mem |
19/// | 2 | Xmm, Xmm, Xmm |
20/// | 3 | Ymm, Ymm, Mem |
21/// | 4 | Ymm, Ymm, Ymm |
22/// | 5 | Zmm, Zmm, Mem |
23/// | 6 | Zmm, Zmm, Zmm |
24/// +---+---------------+
25/// ```
26pub trait Vpmadd52huqEmitter<A, B, C> {
27    fn vpmadd52huq(&mut self, op0: A, op1: B, op2: C);
28}
29
30impl<'a> Vpmadd52huqEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
31    fn vpmadd52huq(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
32        self.emit(
33            VPMADD52HUQ128RRR,
34            op0.as_operand(),
35            op1.as_operand(),
36            op2.as_operand(),
37            &NOREG,
38        );
39    }
40}
41
42impl<'a> Vpmadd52huqEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
43    fn vpmadd52huq(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
44        self.emit(
45            VPMADD52HUQ128RRM,
46            op0.as_operand(),
47            op1.as_operand(),
48            op2.as_operand(),
49            &NOREG,
50        );
51    }
52}
53
54impl<'a> Vpmadd52huqEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
55    fn vpmadd52huq(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
56        self.emit(
57            VPMADD52HUQ256RRR,
58            op0.as_operand(),
59            op1.as_operand(),
60            op2.as_operand(),
61            &NOREG,
62        );
63    }
64}
65
66impl<'a> Vpmadd52huqEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
67    fn vpmadd52huq(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
68        self.emit(
69            VPMADD52HUQ256RRM,
70            op0.as_operand(),
71            op1.as_operand(),
72            op2.as_operand(),
73            &NOREG,
74        );
75    }
76}
77
78impl<'a> Vpmadd52huqEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
79    fn vpmadd52huq(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
80        self.emit(
81            VPMADD52HUQ512RRR,
82            op0.as_operand(),
83            op1.as_operand(),
84            op2.as_operand(),
85            &NOREG,
86        );
87    }
88}
89
90impl<'a> Vpmadd52huqEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
91    fn vpmadd52huq(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
92        self.emit(
93            VPMADD52HUQ512RRM,
94            op0.as_operand(),
95            op1.as_operand(),
96            op2.as_operand(),
97            &NOREG,
98        );
99    }
100}
101
102/// `VPMADD52HUQ_MASK`.
103///
104/// Supported operand variants:
105///
106/// ```text
107/// +---+---------------+
108/// | # | Operands      |
109/// +---+---------------+
110/// | 1 | Xmm, Xmm, Mem |
111/// | 2 | Xmm, Xmm, Xmm |
112/// | 3 | Ymm, Ymm, Mem |
113/// | 4 | Ymm, Ymm, Ymm |
114/// | 5 | Zmm, Zmm, Mem |
115/// | 6 | Zmm, Zmm, Zmm |
116/// +---+---------------+
117/// ```
118pub trait Vpmadd52huqMaskEmitter<A, B, C> {
119    fn vpmadd52huq_mask(&mut self, op0: A, op1: B, op2: C);
120}
121
122impl<'a> Vpmadd52huqMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
123    fn vpmadd52huq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
124        self.emit(
125            VPMADD52HUQ128RRR_MASK,
126            op0.as_operand(),
127            op1.as_operand(),
128            op2.as_operand(),
129            &NOREG,
130        );
131    }
132}
133
134impl<'a> Vpmadd52huqMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
135    fn vpmadd52huq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
136        self.emit(
137            VPMADD52HUQ128RRM_MASK,
138            op0.as_operand(),
139            op1.as_operand(),
140            op2.as_operand(),
141            &NOREG,
142        );
143    }
144}
145
146impl<'a> Vpmadd52huqMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
147    fn vpmadd52huq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
148        self.emit(
149            VPMADD52HUQ256RRR_MASK,
150            op0.as_operand(),
151            op1.as_operand(),
152            op2.as_operand(),
153            &NOREG,
154        );
155    }
156}
157
158impl<'a> Vpmadd52huqMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
159    fn vpmadd52huq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
160        self.emit(
161            VPMADD52HUQ256RRM_MASK,
162            op0.as_operand(),
163            op1.as_operand(),
164            op2.as_operand(),
165            &NOREG,
166        );
167    }
168}
169
170impl<'a> Vpmadd52huqMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
171    fn vpmadd52huq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
172        self.emit(
173            VPMADD52HUQ512RRR_MASK,
174            op0.as_operand(),
175            op1.as_operand(),
176            op2.as_operand(),
177            &NOREG,
178        );
179    }
180}
181
182impl<'a> Vpmadd52huqMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
183    fn vpmadd52huq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
184        self.emit(
185            VPMADD52HUQ512RRM_MASK,
186            op0.as_operand(),
187            op1.as_operand(),
188            op2.as_operand(),
189            &NOREG,
190        );
191    }
192}
193
194/// `VPMADD52HUQ_MASKZ`.
195///
196/// Supported operand variants:
197///
198/// ```text
199/// +---+---------------+
200/// | # | Operands      |
201/// +---+---------------+
202/// | 1 | Xmm, Xmm, Mem |
203/// | 2 | Xmm, Xmm, Xmm |
204/// | 3 | Ymm, Ymm, Mem |
205/// | 4 | Ymm, Ymm, Ymm |
206/// | 5 | Zmm, Zmm, Mem |
207/// | 6 | Zmm, Zmm, Zmm |
208/// +---+---------------+
209/// ```
210pub trait Vpmadd52huqMaskzEmitter<A, B, C> {
211    fn vpmadd52huq_maskz(&mut self, op0: A, op1: B, op2: C);
212}
213
214impl<'a> Vpmadd52huqMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
215    fn vpmadd52huq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
216        self.emit(
217            VPMADD52HUQ128RRR_MASKZ,
218            op0.as_operand(),
219            op1.as_operand(),
220            op2.as_operand(),
221            &NOREG,
222        );
223    }
224}
225
226impl<'a> Vpmadd52huqMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
227    fn vpmadd52huq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
228        self.emit(
229            VPMADD52HUQ128RRM_MASKZ,
230            op0.as_operand(),
231            op1.as_operand(),
232            op2.as_operand(),
233            &NOREG,
234        );
235    }
236}
237
238impl<'a> Vpmadd52huqMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
239    fn vpmadd52huq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
240        self.emit(
241            VPMADD52HUQ256RRR_MASKZ,
242            op0.as_operand(),
243            op1.as_operand(),
244            op2.as_operand(),
245            &NOREG,
246        );
247    }
248}
249
250impl<'a> Vpmadd52huqMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
251    fn vpmadd52huq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
252        self.emit(
253            VPMADD52HUQ256RRM_MASKZ,
254            op0.as_operand(),
255            op1.as_operand(),
256            op2.as_operand(),
257            &NOREG,
258        );
259    }
260}
261
262impl<'a> Vpmadd52huqMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
263    fn vpmadd52huq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
264        self.emit(
265            VPMADD52HUQ512RRR_MASKZ,
266            op0.as_operand(),
267            op1.as_operand(),
268            op2.as_operand(),
269            &NOREG,
270        );
271    }
272}
273
274impl<'a> Vpmadd52huqMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
275    fn vpmadd52huq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
276        self.emit(
277            VPMADD52HUQ512RRM_MASKZ,
278            op0.as_operand(),
279            op1.as_operand(),
280            op2.as_operand(),
281            &NOREG,
282        );
283    }
284}
285
286/// `VPMADD52LUQ`.
287///
288/// Supported operand variants:
289///
290/// ```text
291/// +---+---------------+
292/// | # | Operands      |
293/// +---+---------------+
294/// | 1 | Xmm, Xmm, Mem |
295/// | 2 | Xmm, Xmm, Xmm |
296/// | 3 | Ymm, Ymm, Mem |
297/// | 4 | Ymm, Ymm, Ymm |
298/// | 5 | Zmm, Zmm, Mem |
299/// | 6 | Zmm, Zmm, Zmm |
300/// +---+---------------+
301/// ```
302pub trait Vpmadd52luqEmitter<A, B, C> {
303    fn vpmadd52luq(&mut self, op0: A, op1: B, op2: C);
304}
305
306impl<'a> Vpmadd52luqEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
307    fn vpmadd52luq(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
308        self.emit(
309            VPMADD52LUQ128RRR,
310            op0.as_operand(),
311            op1.as_operand(),
312            op2.as_operand(),
313            &NOREG,
314        );
315    }
316}
317
318impl<'a> Vpmadd52luqEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
319    fn vpmadd52luq(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
320        self.emit(
321            VPMADD52LUQ128RRM,
322            op0.as_operand(),
323            op1.as_operand(),
324            op2.as_operand(),
325            &NOREG,
326        );
327    }
328}
329
330impl<'a> Vpmadd52luqEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
331    fn vpmadd52luq(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
332        self.emit(
333            VPMADD52LUQ256RRR,
334            op0.as_operand(),
335            op1.as_operand(),
336            op2.as_operand(),
337            &NOREG,
338        );
339    }
340}
341
342impl<'a> Vpmadd52luqEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
343    fn vpmadd52luq(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
344        self.emit(
345            VPMADD52LUQ256RRM,
346            op0.as_operand(),
347            op1.as_operand(),
348            op2.as_operand(),
349            &NOREG,
350        );
351    }
352}
353
354impl<'a> Vpmadd52luqEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
355    fn vpmadd52luq(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
356        self.emit(
357            VPMADD52LUQ512RRR,
358            op0.as_operand(),
359            op1.as_operand(),
360            op2.as_operand(),
361            &NOREG,
362        );
363    }
364}
365
366impl<'a> Vpmadd52luqEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
367    fn vpmadd52luq(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
368        self.emit(
369            VPMADD52LUQ512RRM,
370            op0.as_operand(),
371            op1.as_operand(),
372            op2.as_operand(),
373            &NOREG,
374        );
375    }
376}
377
378/// `VPMADD52LUQ_MASK`.
379///
380/// Supported operand variants:
381///
382/// ```text
383/// +---+---------------+
384/// | # | Operands      |
385/// +---+---------------+
386/// | 1 | Xmm, Xmm, Mem |
387/// | 2 | Xmm, Xmm, Xmm |
388/// | 3 | Ymm, Ymm, Mem |
389/// | 4 | Ymm, Ymm, Ymm |
390/// | 5 | Zmm, Zmm, Mem |
391/// | 6 | Zmm, Zmm, Zmm |
392/// +---+---------------+
393/// ```
394pub trait Vpmadd52luqMaskEmitter<A, B, C> {
395    fn vpmadd52luq_mask(&mut self, op0: A, op1: B, op2: C);
396}
397
398impl<'a> Vpmadd52luqMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
399    fn vpmadd52luq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
400        self.emit(
401            VPMADD52LUQ128RRR_MASK,
402            op0.as_operand(),
403            op1.as_operand(),
404            op2.as_operand(),
405            &NOREG,
406        );
407    }
408}
409
410impl<'a> Vpmadd52luqMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
411    fn vpmadd52luq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
412        self.emit(
413            VPMADD52LUQ128RRM_MASK,
414            op0.as_operand(),
415            op1.as_operand(),
416            op2.as_operand(),
417            &NOREG,
418        );
419    }
420}
421
422impl<'a> Vpmadd52luqMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
423    fn vpmadd52luq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
424        self.emit(
425            VPMADD52LUQ256RRR_MASK,
426            op0.as_operand(),
427            op1.as_operand(),
428            op2.as_operand(),
429            &NOREG,
430        );
431    }
432}
433
434impl<'a> Vpmadd52luqMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
435    fn vpmadd52luq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
436        self.emit(
437            VPMADD52LUQ256RRM_MASK,
438            op0.as_operand(),
439            op1.as_operand(),
440            op2.as_operand(),
441            &NOREG,
442        );
443    }
444}
445
446impl<'a> Vpmadd52luqMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
447    fn vpmadd52luq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
448        self.emit(
449            VPMADD52LUQ512RRR_MASK,
450            op0.as_operand(),
451            op1.as_operand(),
452            op2.as_operand(),
453            &NOREG,
454        );
455    }
456}
457
458impl<'a> Vpmadd52luqMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
459    fn vpmadd52luq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
460        self.emit(
461            VPMADD52LUQ512RRM_MASK,
462            op0.as_operand(),
463            op1.as_operand(),
464            op2.as_operand(),
465            &NOREG,
466        );
467    }
468}
469
470/// `VPMADD52LUQ_MASKZ`.
471///
472/// Supported operand variants:
473///
474/// ```text
475/// +---+---------------+
476/// | # | Operands      |
477/// +---+---------------+
478/// | 1 | Xmm, Xmm, Mem |
479/// | 2 | Xmm, Xmm, Xmm |
480/// | 3 | Ymm, Ymm, Mem |
481/// | 4 | Ymm, Ymm, Ymm |
482/// | 5 | Zmm, Zmm, Mem |
483/// | 6 | Zmm, Zmm, Zmm |
484/// +---+---------------+
485/// ```
486pub trait Vpmadd52luqMaskzEmitter<A, B, C> {
487    fn vpmadd52luq_maskz(&mut self, op0: A, op1: B, op2: C);
488}
489
490impl<'a> Vpmadd52luqMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
491    fn vpmadd52luq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
492        self.emit(
493            VPMADD52LUQ128RRR_MASKZ,
494            op0.as_operand(),
495            op1.as_operand(),
496            op2.as_operand(),
497            &NOREG,
498        );
499    }
500}
501
502impl<'a> Vpmadd52luqMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
503    fn vpmadd52luq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
504        self.emit(
505            VPMADD52LUQ128RRM_MASKZ,
506            op0.as_operand(),
507            op1.as_operand(),
508            op2.as_operand(),
509            &NOREG,
510        );
511    }
512}
513
514impl<'a> Vpmadd52luqMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
515    fn vpmadd52luq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
516        self.emit(
517            VPMADD52LUQ256RRR_MASKZ,
518            op0.as_operand(),
519            op1.as_operand(),
520            op2.as_operand(),
521            &NOREG,
522        );
523    }
524}
525
526impl<'a> Vpmadd52luqMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
527    fn vpmadd52luq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
528        self.emit(
529            VPMADD52LUQ256RRM_MASKZ,
530            op0.as_operand(),
531            op1.as_operand(),
532            op2.as_operand(),
533            &NOREG,
534        );
535    }
536}
537
538impl<'a> Vpmadd52luqMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
539    fn vpmadd52luq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
540        self.emit(
541            VPMADD52LUQ512RRR_MASKZ,
542            op0.as_operand(),
543            op1.as_operand(),
544            op2.as_operand(),
545            &NOREG,
546        );
547    }
548}
549
550impl<'a> Vpmadd52luqMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
551    fn vpmadd52luq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
552        self.emit(
553            VPMADD52LUQ512RRM_MASKZ,
554            op0.as_operand(),
555            op1.as_operand(),
556            op2.as_operand(),
557            &NOREG,
558        );
559    }
560}
561
562impl<'a> Assembler<'a> {
563    /// `VPMADD52HUQ`.
564    ///
565    /// Supported operand variants:
566    ///
567    /// ```text
568    /// +---+---------------+
569    /// | # | Operands      |
570    /// +---+---------------+
571    /// | 1 | Xmm, Xmm, Mem |
572    /// | 2 | Xmm, Xmm, Xmm |
573    /// | 3 | Ymm, Ymm, Mem |
574    /// | 4 | Ymm, Ymm, Ymm |
575    /// | 5 | Zmm, Zmm, Mem |
576    /// | 6 | Zmm, Zmm, Zmm |
577    /// +---+---------------+
578    /// ```
579    #[inline]
580    pub fn vpmadd52huq<A, B, C>(&mut self, op0: A, op1: B, op2: C)
581    where
582        Assembler<'a>: Vpmadd52huqEmitter<A, B, C>,
583    {
584        <Self as Vpmadd52huqEmitter<A, B, C>>::vpmadd52huq(self, op0, op1, op2);
585    }
586    /// `VPMADD52HUQ_MASK`.
587    ///
588    /// Supported operand variants:
589    ///
590    /// ```text
591    /// +---+---------------+
592    /// | # | Operands      |
593    /// +---+---------------+
594    /// | 1 | Xmm, Xmm, Mem |
595    /// | 2 | Xmm, Xmm, Xmm |
596    /// | 3 | Ymm, Ymm, Mem |
597    /// | 4 | Ymm, Ymm, Ymm |
598    /// | 5 | Zmm, Zmm, Mem |
599    /// | 6 | Zmm, Zmm, Zmm |
600    /// +---+---------------+
601    /// ```
602    #[inline]
603    pub fn vpmadd52huq_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
604    where
605        Assembler<'a>: Vpmadd52huqMaskEmitter<A, B, C>,
606    {
607        <Self as Vpmadd52huqMaskEmitter<A, B, C>>::vpmadd52huq_mask(self, op0, op1, op2);
608    }
609    /// `VPMADD52HUQ_MASKZ`.
610    ///
611    /// Supported operand variants:
612    ///
613    /// ```text
614    /// +---+---------------+
615    /// | # | Operands      |
616    /// +---+---------------+
617    /// | 1 | Xmm, Xmm, Mem |
618    /// | 2 | Xmm, Xmm, Xmm |
619    /// | 3 | Ymm, Ymm, Mem |
620    /// | 4 | Ymm, Ymm, Ymm |
621    /// | 5 | Zmm, Zmm, Mem |
622    /// | 6 | Zmm, Zmm, Zmm |
623    /// +---+---------------+
624    /// ```
625    #[inline]
626    pub fn vpmadd52huq_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
627    where
628        Assembler<'a>: Vpmadd52huqMaskzEmitter<A, B, C>,
629    {
630        <Self as Vpmadd52huqMaskzEmitter<A, B, C>>::vpmadd52huq_maskz(self, op0, op1, op2);
631    }
632    /// `VPMADD52LUQ`.
633    ///
634    /// Supported operand variants:
635    ///
636    /// ```text
637    /// +---+---------------+
638    /// | # | Operands      |
639    /// +---+---------------+
640    /// | 1 | Xmm, Xmm, Mem |
641    /// | 2 | Xmm, Xmm, Xmm |
642    /// | 3 | Ymm, Ymm, Mem |
643    /// | 4 | Ymm, Ymm, Ymm |
644    /// | 5 | Zmm, Zmm, Mem |
645    /// | 6 | Zmm, Zmm, Zmm |
646    /// +---+---------------+
647    /// ```
648    #[inline]
649    pub fn vpmadd52luq<A, B, C>(&mut self, op0: A, op1: B, op2: C)
650    where
651        Assembler<'a>: Vpmadd52luqEmitter<A, B, C>,
652    {
653        <Self as Vpmadd52luqEmitter<A, B, C>>::vpmadd52luq(self, op0, op1, op2);
654    }
655    /// `VPMADD52LUQ_MASK`.
656    ///
657    /// Supported operand variants:
658    ///
659    /// ```text
660    /// +---+---------------+
661    /// | # | Operands      |
662    /// +---+---------------+
663    /// | 1 | Xmm, Xmm, Mem |
664    /// | 2 | Xmm, Xmm, Xmm |
665    /// | 3 | Ymm, Ymm, Mem |
666    /// | 4 | Ymm, Ymm, Ymm |
667    /// | 5 | Zmm, Zmm, Mem |
668    /// | 6 | Zmm, Zmm, Zmm |
669    /// +---+---------------+
670    /// ```
671    #[inline]
672    pub fn vpmadd52luq_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
673    where
674        Assembler<'a>: Vpmadd52luqMaskEmitter<A, B, C>,
675    {
676        <Self as Vpmadd52luqMaskEmitter<A, B, C>>::vpmadd52luq_mask(self, op0, op1, op2);
677    }
678    /// `VPMADD52LUQ_MASKZ`.
679    ///
680    /// Supported operand variants:
681    ///
682    /// ```text
683    /// +---+---------------+
684    /// | # | Operands      |
685    /// +---+---------------+
686    /// | 1 | Xmm, Xmm, Mem |
687    /// | 2 | Xmm, Xmm, Xmm |
688    /// | 3 | Ymm, Ymm, Mem |
689    /// | 4 | Ymm, Ymm, Ymm |
690    /// | 5 | Zmm, Zmm, Mem |
691    /// | 6 | Zmm, Zmm, Zmm |
692    /// +---+---------------+
693    /// ```
694    #[inline]
695    pub fn vpmadd52luq_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
696    where
697        Assembler<'a>: Vpmadd52luqMaskzEmitter<A, B, C>,
698    {
699        <Self as Vpmadd52luqMaskzEmitter<A, B, C>>::vpmadd52luq_maskz(self, op0, op1, op2);
700    }
701}
asmkit/x86/features/AVX512_IFMA.rs

asmkit/x86/features/
AVX512_IFMA.rs
