asmkit/x86/features/
AVX512_BF16.rs

1use super::super::opcodes::*;
2use crate::core::emitter::*;
3use crate::core::operand::*;
4use crate::x86::assembler::*;
5use crate::x86::operands::*;
6
7/// A dummy operand that represents no register. Here just for simplicity.
8const NOREG: Operand = Operand::new();
9
10/// `VCVTNE2PS2BF16`.
11///
12/// Supported operand variants:
13///
14/// ```text
15/// +---+---------------+
16/// | # | Operands      |
17/// +---+---------------+
18/// | 1 | Xmm, Xmm, Mem |
19/// | 2 | Xmm, Xmm, Xmm |
20/// | 3 | Ymm, Ymm, Mem |
21/// | 4 | Ymm, Ymm, Ymm |
22/// | 5 | Zmm, Zmm, Mem |
23/// | 6 | Zmm, Zmm, Zmm |
24/// +---+---------------+
25/// ```
26pub trait Vcvtne2ps2bf16Emitter<A, B, C> {
27    fn vcvtne2ps2bf16(&mut self, op0: A, op1: B, op2: C);
28}
29
30impl<'a> Vcvtne2ps2bf16Emitter<Xmm, Xmm, Xmm> for Assembler<'a> {
31    fn vcvtne2ps2bf16(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
32        self.emit(
33            VCVTNE2PS2BF16_128RRR,
34            op0.as_operand(),
35            op1.as_operand(),
36            op2.as_operand(),
37            &NOREG,
38        );
39    }
40}
41
42impl<'a> Vcvtne2ps2bf16Emitter<Xmm, Xmm, Mem> for Assembler<'a> {
43    fn vcvtne2ps2bf16(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
44        self.emit(
45            VCVTNE2PS2BF16_128RRM,
46            op0.as_operand(),
47            op1.as_operand(),
48            op2.as_operand(),
49            &NOREG,
50        );
51    }
52}
53
54impl<'a> Vcvtne2ps2bf16Emitter<Ymm, Ymm, Ymm> for Assembler<'a> {
55    fn vcvtne2ps2bf16(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
56        self.emit(
57            VCVTNE2PS2BF16_256RRR,
58            op0.as_operand(),
59            op1.as_operand(),
60            op2.as_operand(),
61            &NOREG,
62        );
63    }
64}
65
66impl<'a> Vcvtne2ps2bf16Emitter<Ymm, Ymm, Mem> for Assembler<'a> {
67    fn vcvtne2ps2bf16(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
68        self.emit(
69            VCVTNE2PS2BF16_256RRM,
70            op0.as_operand(),
71            op1.as_operand(),
72            op2.as_operand(),
73            &NOREG,
74        );
75    }
76}
77
78impl<'a> Vcvtne2ps2bf16Emitter<Zmm, Zmm, Zmm> for Assembler<'a> {
79    fn vcvtne2ps2bf16(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
80        self.emit(
81            VCVTNE2PS2BF16_512RRR,
82            op0.as_operand(),
83            op1.as_operand(),
84            op2.as_operand(),
85            &NOREG,
86        );
87    }
88}
89
90impl<'a> Vcvtne2ps2bf16Emitter<Zmm, Zmm, Mem> for Assembler<'a> {
91    fn vcvtne2ps2bf16(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
92        self.emit(
93            VCVTNE2PS2BF16_512RRM,
94            op0.as_operand(),
95            op1.as_operand(),
96            op2.as_operand(),
97            &NOREG,
98        );
99    }
100}
101
102/// `VCVTNE2PS2BF16_MASK`.
103///
104/// Supported operand variants:
105///
106/// ```text
107/// +---+---------------+
108/// | # | Operands      |
109/// +---+---------------+
110/// | 1 | Xmm, Xmm, Mem |
111/// | 2 | Xmm, Xmm, Xmm |
112/// | 3 | Ymm, Ymm, Mem |
113/// | 4 | Ymm, Ymm, Ymm |
114/// | 5 | Zmm, Zmm, Mem |
115/// | 6 | Zmm, Zmm, Zmm |
116/// +---+---------------+
117/// ```
118pub trait Vcvtne2ps2bf16MaskEmitter<A, B, C> {
119    fn vcvtne2ps2bf16_mask(&mut self, op0: A, op1: B, op2: C);
120}
121
122impl<'a> Vcvtne2ps2bf16MaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
123    fn vcvtne2ps2bf16_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
124        self.emit(
125            VCVTNE2PS2BF16_128RRR_MASK,
126            op0.as_operand(),
127            op1.as_operand(),
128            op2.as_operand(),
129            &NOREG,
130        );
131    }
132}
133
134impl<'a> Vcvtne2ps2bf16MaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
135    fn vcvtne2ps2bf16_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
136        self.emit(
137            VCVTNE2PS2BF16_128RRM_MASK,
138            op0.as_operand(),
139            op1.as_operand(),
140            op2.as_operand(),
141            &NOREG,
142        );
143    }
144}
145
146impl<'a> Vcvtne2ps2bf16MaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
147    fn vcvtne2ps2bf16_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
148        self.emit(
149            VCVTNE2PS2BF16_256RRR_MASK,
150            op0.as_operand(),
151            op1.as_operand(),
152            op2.as_operand(),
153            &NOREG,
154        );
155    }
156}
157
158impl<'a> Vcvtne2ps2bf16MaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
159    fn vcvtne2ps2bf16_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
160        self.emit(
161            VCVTNE2PS2BF16_256RRM_MASK,
162            op0.as_operand(),
163            op1.as_operand(),
164            op2.as_operand(),
165            &NOREG,
166        );
167    }
168}
169
170impl<'a> Vcvtne2ps2bf16MaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
171    fn vcvtne2ps2bf16_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
172        self.emit(
173            VCVTNE2PS2BF16_512RRR_MASK,
174            op0.as_operand(),
175            op1.as_operand(),
176            op2.as_operand(),
177            &NOREG,
178        );
179    }
180}
181
182impl<'a> Vcvtne2ps2bf16MaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
183    fn vcvtne2ps2bf16_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
184        self.emit(
185            VCVTNE2PS2BF16_512RRM_MASK,
186            op0.as_operand(),
187            op1.as_operand(),
188            op2.as_operand(),
189            &NOREG,
190        );
191    }
192}
193
194/// `VCVTNE2PS2BF16_MASKZ`.
195///
196/// Supported operand variants:
197///
198/// ```text
199/// +---+---------------+
200/// | # | Operands      |
201/// +---+---------------+
202/// | 1 | Xmm, Xmm, Mem |
203/// | 2 | Xmm, Xmm, Xmm |
204/// | 3 | Ymm, Ymm, Mem |
205/// | 4 | Ymm, Ymm, Ymm |
206/// | 5 | Zmm, Zmm, Mem |
207/// | 6 | Zmm, Zmm, Zmm |
208/// +---+---------------+
209/// ```
210pub trait Vcvtne2ps2bf16MaskzEmitter<A, B, C> {
211    fn vcvtne2ps2bf16_maskz(&mut self, op0: A, op1: B, op2: C);
212}
213
214impl<'a> Vcvtne2ps2bf16MaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
215    fn vcvtne2ps2bf16_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
216        self.emit(
217            VCVTNE2PS2BF16_128RRR_MASKZ,
218            op0.as_operand(),
219            op1.as_operand(),
220            op2.as_operand(),
221            &NOREG,
222        );
223    }
224}
225
226impl<'a> Vcvtne2ps2bf16MaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
227    fn vcvtne2ps2bf16_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
228        self.emit(
229            VCVTNE2PS2BF16_128RRM_MASKZ,
230            op0.as_operand(),
231            op1.as_operand(),
232            op2.as_operand(),
233            &NOREG,
234        );
235    }
236}
237
238impl<'a> Vcvtne2ps2bf16MaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
239    fn vcvtne2ps2bf16_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
240        self.emit(
241            VCVTNE2PS2BF16_256RRR_MASKZ,
242            op0.as_operand(),
243            op1.as_operand(),
244            op2.as_operand(),
245            &NOREG,
246        );
247    }
248}
249
250impl<'a> Vcvtne2ps2bf16MaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
251    fn vcvtne2ps2bf16_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
252        self.emit(
253            VCVTNE2PS2BF16_256RRM_MASKZ,
254            op0.as_operand(),
255            op1.as_operand(),
256            op2.as_operand(),
257            &NOREG,
258        );
259    }
260}
261
262impl<'a> Vcvtne2ps2bf16MaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
263    fn vcvtne2ps2bf16_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
264        self.emit(
265            VCVTNE2PS2BF16_512RRR_MASKZ,
266            op0.as_operand(),
267            op1.as_operand(),
268            op2.as_operand(),
269            &NOREG,
270        );
271    }
272}
273
274impl<'a> Vcvtne2ps2bf16MaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
275    fn vcvtne2ps2bf16_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
276        self.emit(
277            VCVTNE2PS2BF16_512RRM_MASKZ,
278            op0.as_operand(),
279            op1.as_operand(),
280            op2.as_operand(),
281            &NOREG,
282        );
283    }
284}
285
286/// `VCVTNEPS2BF16`.
287///
288/// Supported operand variants:
289///
290/// ```text
291/// +---+----------+
292/// | # | Operands |
293/// +---+----------+
294/// | 1 | Xmm, Mem |
295/// | 2 | Xmm, Xmm |
296/// | 3 | Xmm, Ymm |
297/// | 4 | Ymm, Mem |
298/// | 5 | Ymm, Zmm |
299/// +---+----------+
300/// ```
301pub trait Vcvtneps2bf16Emitter<A, B> {
302    fn vcvtneps2bf16(&mut self, op0: A, op1: B);
303}
304
305impl<'a> Vcvtneps2bf16Emitter<Xmm, Xmm> for Assembler<'a> {
306    fn vcvtneps2bf16(&mut self, op0: Xmm, op1: Xmm) {
307        self.emit(
308            VCVTNEPS2BF16_128RR,
309            op0.as_operand(),
310            op1.as_operand(),
311            &NOREG,
312            &NOREG,
313        );
314    }
315}
316
317impl<'a> Vcvtneps2bf16Emitter<Xmm, Mem> for Assembler<'a> {
318    fn vcvtneps2bf16(&mut self, op0: Xmm, op1: Mem) {
319        self.emit(
320            VCVTNEPS2BF16_128RM,
321            op0.as_operand(),
322            op1.as_operand(),
323            &NOREG,
324            &NOREG,
325        );
326    }
327}
328
329impl<'a> Vcvtneps2bf16Emitter<Xmm, Ymm> for Assembler<'a> {
330    fn vcvtneps2bf16(&mut self, op0: Xmm, op1: Ymm) {
331        self.emit(
332            VCVTNEPS2BF16_256RR,
333            op0.as_operand(),
334            op1.as_operand(),
335            &NOREG,
336            &NOREG,
337        );
338    }
339}
340
341impl<'a> Vcvtneps2bf16Emitter<Ymm, Zmm> for Assembler<'a> {
342    fn vcvtneps2bf16(&mut self, op0: Ymm, op1: Zmm) {
343        self.emit(
344            VCVTNEPS2BF16_512RR,
345            op0.as_operand(),
346            op1.as_operand(),
347            &NOREG,
348            &NOREG,
349        );
350    }
351}
352
353impl<'a> Vcvtneps2bf16Emitter<Ymm, Mem> for Assembler<'a> {
354    fn vcvtneps2bf16(&mut self, op0: Ymm, op1: Mem) {
355        self.emit(
356            VCVTNEPS2BF16_512RM,
357            op0.as_operand(),
358            op1.as_operand(),
359            &NOREG,
360            &NOREG,
361        );
362    }
363}
364
365/// `VCVTNEPS2BF16_MASK`.
366///
367/// Supported operand variants:
368///
369/// ```text
370/// +---+----------+
371/// | # | Operands |
372/// +---+----------+
373/// | 1 | Xmm, Mem |
374/// | 2 | Xmm, Xmm |
375/// | 3 | Xmm, Ymm |
376/// | 4 | Ymm, Mem |
377/// | 5 | Ymm, Zmm |
378/// +---+----------+
379/// ```
380pub trait Vcvtneps2bf16MaskEmitter<A, B> {
381    fn vcvtneps2bf16_mask(&mut self, op0: A, op1: B);
382}
383
384impl<'a> Vcvtneps2bf16MaskEmitter<Xmm, Xmm> for Assembler<'a> {
385    fn vcvtneps2bf16_mask(&mut self, op0: Xmm, op1: Xmm) {
386        self.emit(
387            VCVTNEPS2BF16_128RR_MASK,
388            op0.as_operand(),
389            op1.as_operand(),
390            &NOREG,
391            &NOREG,
392        );
393    }
394}
395
396impl<'a> Vcvtneps2bf16MaskEmitter<Xmm, Mem> for Assembler<'a> {
397    fn vcvtneps2bf16_mask(&mut self, op0: Xmm, op1: Mem) {
398        self.emit(
399            VCVTNEPS2BF16_128RM_MASK,
400            op0.as_operand(),
401            op1.as_operand(),
402            &NOREG,
403            &NOREG,
404        );
405    }
406}
407
408impl<'a> Vcvtneps2bf16MaskEmitter<Xmm, Ymm> for Assembler<'a> {
409    fn vcvtneps2bf16_mask(&mut self, op0: Xmm, op1: Ymm) {
410        self.emit(
411            VCVTNEPS2BF16_256RR_MASK,
412            op0.as_operand(),
413            op1.as_operand(),
414            &NOREG,
415            &NOREG,
416        );
417    }
418}
419
420impl<'a> Vcvtneps2bf16MaskEmitter<Ymm, Zmm> for Assembler<'a> {
421    fn vcvtneps2bf16_mask(&mut self, op0: Ymm, op1: Zmm) {
422        self.emit(
423            VCVTNEPS2BF16_512RR_MASK,
424            op0.as_operand(),
425            op1.as_operand(),
426            &NOREG,
427            &NOREG,
428        );
429    }
430}
431
432impl<'a> Vcvtneps2bf16MaskEmitter<Ymm, Mem> for Assembler<'a> {
433    fn vcvtneps2bf16_mask(&mut self, op0: Ymm, op1: Mem) {
434        self.emit(
435            VCVTNEPS2BF16_512RM_MASK,
436            op0.as_operand(),
437            op1.as_operand(),
438            &NOREG,
439            &NOREG,
440        );
441    }
442}
443
444/// `VCVTNEPS2BF16_MASKZ`.
445///
446/// Supported operand variants:
447///
448/// ```text
449/// +---+----------+
450/// | # | Operands |
451/// +---+----------+
452/// | 1 | Xmm, Mem |
453/// | 2 | Xmm, Xmm |
454/// | 3 | Xmm, Ymm |
455/// | 4 | Ymm, Mem |
456/// | 5 | Ymm, Zmm |
457/// +---+----------+
458/// ```
459pub trait Vcvtneps2bf16MaskzEmitter<A, B> {
460    fn vcvtneps2bf16_maskz(&mut self, op0: A, op1: B);
461}
462
463impl<'a> Vcvtneps2bf16MaskzEmitter<Xmm, Xmm> for Assembler<'a> {
464    fn vcvtneps2bf16_maskz(&mut self, op0: Xmm, op1: Xmm) {
465        self.emit(
466            VCVTNEPS2BF16_128RR_MASKZ,
467            op0.as_operand(),
468            op1.as_operand(),
469            &NOREG,
470            &NOREG,
471        );
472    }
473}
474
475impl<'a> Vcvtneps2bf16MaskzEmitter<Xmm, Mem> for Assembler<'a> {
476    fn vcvtneps2bf16_maskz(&mut self, op0: Xmm, op1: Mem) {
477        self.emit(
478            VCVTNEPS2BF16_128RM_MASKZ,
479            op0.as_operand(),
480            op1.as_operand(),
481            &NOREG,
482            &NOREG,
483        );
484    }
485}
486
487impl<'a> Vcvtneps2bf16MaskzEmitter<Xmm, Ymm> for Assembler<'a> {
488    fn vcvtneps2bf16_maskz(&mut self, op0: Xmm, op1: Ymm) {
489        self.emit(
490            VCVTNEPS2BF16_256RR_MASKZ,
491            op0.as_operand(),
492            op1.as_operand(),
493            &NOREG,
494            &NOREG,
495        );
496    }
497}
498
499impl<'a> Vcvtneps2bf16MaskzEmitter<Ymm, Zmm> for Assembler<'a> {
500    fn vcvtneps2bf16_maskz(&mut self, op0: Ymm, op1: Zmm) {
501        self.emit(
502            VCVTNEPS2BF16_512RR_MASKZ,
503            op0.as_operand(),
504            op1.as_operand(),
505            &NOREG,
506            &NOREG,
507        );
508    }
509}
510
511impl<'a> Vcvtneps2bf16MaskzEmitter<Ymm, Mem> for Assembler<'a> {
512    fn vcvtneps2bf16_maskz(&mut self, op0: Ymm, op1: Mem) {
513        self.emit(
514            VCVTNEPS2BF16_512RM_MASKZ,
515            op0.as_operand(),
516            op1.as_operand(),
517            &NOREG,
518            &NOREG,
519        );
520    }
521}
522
523/// `VDPBF16PS`.
524///
525/// Supported operand variants:
526///
527/// ```text
528/// +---+---------------+
529/// | # | Operands      |
530/// +---+---------------+
531/// | 1 | Xmm, Xmm, Mem |
532/// | 2 | Xmm, Xmm, Xmm |
533/// | 3 | Ymm, Ymm, Mem |
534/// | 4 | Ymm, Ymm, Ymm |
535/// | 5 | Zmm, Zmm, Mem |
536/// | 6 | Zmm, Zmm, Zmm |
537/// +---+---------------+
538/// ```
539pub trait Vdpbf16psEmitter<A, B, C> {
540    fn vdpbf16ps(&mut self, op0: A, op1: B, op2: C);
541}
542
543impl<'a> Vdpbf16psEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
544    fn vdpbf16ps(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
545        self.emit(
546            VDPBF16PS128RRR,
547            op0.as_operand(),
548            op1.as_operand(),
549            op2.as_operand(),
550            &NOREG,
551        );
552    }
553}
554
555impl<'a> Vdpbf16psEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
556    fn vdpbf16ps(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
557        self.emit(
558            VDPBF16PS128RRM,
559            op0.as_operand(),
560            op1.as_operand(),
561            op2.as_operand(),
562            &NOREG,
563        );
564    }
565}
566
567impl<'a> Vdpbf16psEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
568    fn vdpbf16ps(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
569        self.emit(
570            VDPBF16PS256RRR,
571            op0.as_operand(),
572            op1.as_operand(),
573            op2.as_operand(),
574            &NOREG,
575        );
576    }
577}
578
579impl<'a> Vdpbf16psEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
580    fn vdpbf16ps(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
581        self.emit(
582            VDPBF16PS256RRM,
583            op0.as_operand(),
584            op1.as_operand(),
585            op2.as_operand(),
586            &NOREG,
587        );
588    }
589}
590
591impl<'a> Vdpbf16psEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
592    fn vdpbf16ps(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
593        self.emit(
594            VDPBF16PS512RRR,
595            op0.as_operand(),
596            op1.as_operand(),
597            op2.as_operand(),
598            &NOREG,
599        );
600    }
601}
602
603impl<'a> Vdpbf16psEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
604    fn vdpbf16ps(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
605        self.emit(
606            VDPBF16PS512RRM,
607            op0.as_operand(),
608            op1.as_operand(),
609            op2.as_operand(),
610            &NOREG,
611        );
612    }
613}
614
615/// `VDPBF16PS_MASK`.
616///
617/// Supported operand variants:
618///
619/// ```text
620/// +---+---------------+
621/// | # | Operands      |
622/// +---+---------------+
623/// | 1 | Xmm, Xmm, Mem |
624/// | 2 | Xmm, Xmm, Xmm |
625/// | 3 | Ymm, Ymm, Mem |
626/// | 4 | Ymm, Ymm, Ymm |
627/// | 5 | Zmm, Zmm, Mem |
628/// | 6 | Zmm, Zmm, Zmm |
629/// +---+---------------+
630/// ```
631pub trait Vdpbf16psMaskEmitter<A, B, C> {
632    fn vdpbf16ps_mask(&mut self, op0: A, op1: B, op2: C);
633}
634
635impl<'a> Vdpbf16psMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
636    fn vdpbf16ps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
637        self.emit(
638            VDPBF16PS128RRR_MASK,
639            op0.as_operand(),
640            op1.as_operand(),
641            op2.as_operand(),
642            &NOREG,
643        );
644    }
645}
646
647impl<'a> Vdpbf16psMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
648    fn vdpbf16ps_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
649        self.emit(
650            VDPBF16PS128RRM_MASK,
651            op0.as_operand(),
652            op1.as_operand(),
653            op2.as_operand(),
654            &NOREG,
655        );
656    }
657}
658
659impl<'a> Vdpbf16psMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
660    fn vdpbf16ps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
661        self.emit(
662            VDPBF16PS256RRR_MASK,
663            op0.as_operand(),
664            op1.as_operand(),
665            op2.as_operand(),
666            &NOREG,
667        );
668    }
669}
670
671impl<'a> Vdpbf16psMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
672    fn vdpbf16ps_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
673        self.emit(
674            VDPBF16PS256RRM_MASK,
675            op0.as_operand(),
676            op1.as_operand(),
677            op2.as_operand(),
678            &NOREG,
679        );
680    }
681}
682
683impl<'a> Vdpbf16psMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
684    fn vdpbf16ps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
685        self.emit(
686            VDPBF16PS512RRR_MASK,
687            op0.as_operand(),
688            op1.as_operand(),
689            op2.as_operand(),
690            &NOREG,
691        );
692    }
693}
694
695impl<'a> Vdpbf16psMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
696    fn vdpbf16ps_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
697        self.emit(
698            VDPBF16PS512RRM_MASK,
699            op0.as_operand(),
700            op1.as_operand(),
701            op2.as_operand(),
702            &NOREG,
703        );
704    }
705}
706
707/// `VDPBF16PS_MASKZ`.
708///
709/// Supported operand variants:
710///
711/// ```text
712/// +---+---------------+
713/// | # | Operands      |
714/// +---+---------------+
715/// | 1 | Xmm, Xmm, Mem |
716/// | 2 | Xmm, Xmm, Xmm |
717/// | 3 | Ymm, Ymm, Mem |
718/// | 4 | Ymm, Ymm, Ymm |
719/// | 5 | Zmm, Zmm, Mem |
720/// | 6 | Zmm, Zmm, Zmm |
721/// +---+---------------+
722/// ```
723pub trait Vdpbf16psMaskzEmitter<A, B, C> {
724    fn vdpbf16ps_maskz(&mut self, op0: A, op1: B, op2: C);
725}
726
727impl<'a> Vdpbf16psMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
728    fn vdpbf16ps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
729        self.emit(
730            VDPBF16PS128RRR_MASKZ,
731            op0.as_operand(),
732            op1.as_operand(),
733            op2.as_operand(),
734            &NOREG,
735        );
736    }
737}
738
739impl<'a> Vdpbf16psMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
740    fn vdpbf16ps_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
741        self.emit(
742            VDPBF16PS128RRM_MASKZ,
743            op0.as_operand(),
744            op1.as_operand(),
745            op2.as_operand(),
746            &NOREG,
747        );
748    }
749}
750
751impl<'a> Vdpbf16psMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
752    fn vdpbf16ps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
753        self.emit(
754            VDPBF16PS256RRR_MASKZ,
755            op0.as_operand(),
756            op1.as_operand(),
757            op2.as_operand(),
758            &NOREG,
759        );
760    }
761}
762
763impl<'a> Vdpbf16psMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
764    fn vdpbf16ps_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
765        self.emit(
766            VDPBF16PS256RRM_MASKZ,
767            op0.as_operand(),
768            op1.as_operand(),
769            op2.as_operand(),
770            &NOREG,
771        );
772    }
773}
774
775impl<'a> Vdpbf16psMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
776    fn vdpbf16ps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
777        self.emit(
778            VDPBF16PS512RRR_MASKZ,
779            op0.as_operand(),
780            op1.as_operand(),
781            op2.as_operand(),
782            &NOREG,
783        );
784    }
785}
786
787impl<'a> Vdpbf16psMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
788    fn vdpbf16ps_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
789        self.emit(
790            VDPBF16PS512RRM_MASKZ,
791            op0.as_operand(),
792            op1.as_operand(),
793            op2.as_operand(),
794            &NOREG,
795        );
796    }
797}
798
799impl<'a> Assembler<'a> {
800    /// `VCVTNE2PS2BF16`.
801    ///
802    /// Supported operand variants:
803    ///
804    /// ```text
805    /// +---+---------------+
806    /// | # | Operands      |
807    /// +---+---------------+
808    /// | 1 | Xmm, Xmm, Mem |
809    /// | 2 | Xmm, Xmm, Xmm |
810    /// | 3 | Ymm, Ymm, Mem |
811    /// | 4 | Ymm, Ymm, Ymm |
812    /// | 5 | Zmm, Zmm, Mem |
813    /// | 6 | Zmm, Zmm, Zmm |
814    /// +---+---------------+
815    /// ```
816    #[inline]
817    pub fn vcvtne2ps2bf16<A, B, C>(&mut self, op0: A, op1: B, op2: C)
818    where
819        Assembler<'a>: Vcvtne2ps2bf16Emitter<A, B, C>,
820    {
821        <Self as Vcvtne2ps2bf16Emitter<A, B, C>>::vcvtne2ps2bf16(self, op0, op1, op2);
822    }
823    /// `VCVTNE2PS2BF16_MASK`.
824    ///
825    /// Supported operand variants:
826    ///
827    /// ```text
828    /// +---+---------------+
829    /// | # | Operands      |
830    /// +---+---------------+
831    /// | 1 | Xmm, Xmm, Mem |
832    /// | 2 | Xmm, Xmm, Xmm |
833    /// | 3 | Ymm, Ymm, Mem |
834    /// | 4 | Ymm, Ymm, Ymm |
835    /// | 5 | Zmm, Zmm, Mem |
836    /// | 6 | Zmm, Zmm, Zmm |
837    /// +---+---------------+
838    /// ```
839    #[inline]
840    pub fn vcvtne2ps2bf16_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
841    where
842        Assembler<'a>: Vcvtne2ps2bf16MaskEmitter<A, B, C>,
843    {
844        <Self as Vcvtne2ps2bf16MaskEmitter<A, B, C>>::vcvtne2ps2bf16_mask(self, op0, op1, op2);
845    }
846    /// `VCVTNE2PS2BF16_MASKZ`.
847    ///
848    /// Supported operand variants:
849    ///
850    /// ```text
851    /// +---+---------------+
852    /// | # | Operands      |
853    /// +---+---------------+
854    /// | 1 | Xmm, Xmm, Mem |
855    /// | 2 | Xmm, Xmm, Xmm |
856    /// | 3 | Ymm, Ymm, Mem |
857    /// | 4 | Ymm, Ymm, Ymm |
858    /// | 5 | Zmm, Zmm, Mem |
859    /// | 6 | Zmm, Zmm, Zmm |
860    /// +---+---------------+
861    /// ```
862    #[inline]
863    pub fn vcvtne2ps2bf16_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
864    where
865        Assembler<'a>: Vcvtne2ps2bf16MaskzEmitter<A, B, C>,
866    {
867        <Self as Vcvtne2ps2bf16MaskzEmitter<A, B, C>>::vcvtne2ps2bf16_maskz(self, op0, op1, op2);
868    }
869    /// `VCVTNEPS2BF16`.
870    ///
871    /// Supported operand variants:
872    ///
873    /// ```text
874    /// +---+----------+
875    /// | # | Operands |
876    /// +---+----------+
877    /// | 1 | Xmm, Mem |
878    /// | 2 | Xmm, Xmm |
879    /// | 3 | Xmm, Ymm |
880    /// | 4 | Ymm, Mem |
881    /// | 5 | Ymm, Zmm |
882    /// +---+----------+
883    /// ```
884    #[inline]
885    pub fn vcvtneps2bf16<A, B>(&mut self, op0: A, op1: B)
886    where
887        Assembler<'a>: Vcvtneps2bf16Emitter<A, B>,
888    {
889        <Self as Vcvtneps2bf16Emitter<A, B>>::vcvtneps2bf16(self, op0, op1);
890    }
891    /// `VCVTNEPS2BF16_MASK`.
892    ///
893    /// Supported operand variants:
894    ///
895    /// ```text
896    /// +---+----------+
897    /// | # | Operands |
898    /// +---+----------+
899    /// | 1 | Xmm, Mem |
900    /// | 2 | Xmm, Xmm |
901    /// | 3 | Xmm, Ymm |
902    /// | 4 | Ymm, Mem |
903    /// | 5 | Ymm, Zmm |
904    /// +---+----------+
905    /// ```
906    #[inline]
907    pub fn vcvtneps2bf16_mask<A, B>(&mut self, op0: A, op1: B)
908    where
909        Assembler<'a>: Vcvtneps2bf16MaskEmitter<A, B>,
910    {
911        <Self as Vcvtneps2bf16MaskEmitter<A, B>>::vcvtneps2bf16_mask(self, op0, op1);
912    }
913    /// `VCVTNEPS2BF16_MASKZ`.
914    ///
915    /// Supported operand variants:
916    ///
917    /// ```text
918    /// +---+----------+
919    /// | # | Operands |
920    /// +---+----------+
921    /// | 1 | Xmm, Mem |
922    /// | 2 | Xmm, Xmm |
923    /// | 3 | Xmm, Ymm |
924    /// | 4 | Ymm, Mem |
925    /// | 5 | Ymm, Zmm |
926    /// +---+----------+
927    /// ```
928    #[inline]
929    pub fn vcvtneps2bf16_maskz<A, B>(&mut self, op0: A, op1: B)
930    where
931        Assembler<'a>: Vcvtneps2bf16MaskzEmitter<A, B>,
932    {
933        <Self as Vcvtneps2bf16MaskzEmitter<A, B>>::vcvtneps2bf16_maskz(self, op0, op1);
934    }
935    /// `VDPBF16PS`.
936    ///
937    /// Supported operand variants:
938    ///
939    /// ```text
940    /// +---+---------------+
941    /// | # | Operands      |
942    /// +---+---------------+
943    /// | 1 | Xmm, Xmm, Mem |
944    /// | 2 | Xmm, Xmm, Xmm |
945    /// | 3 | Ymm, Ymm, Mem |
946    /// | 4 | Ymm, Ymm, Ymm |
947    /// | 5 | Zmm, Zmm, Mem |
948    /// | 6 | Zmm, Zmm, Zmm |
949    /// +---+---------------+
950    /// ```
951    #[inline]
952    pub fn vdpbf16ps<A, B, C>(&mut self, op0: A, op1: B, op2: C)
953    where
954        Assembler<'a>: Vdpbf16psEmitter<A, B, C>,
955    {
956        <Self as Vdpbf16psEmitter<A, B, C>>::vdpbf16ps(self, op0, op1, op2);
957    }
958    /// `VDPBF16PS_MASK`.
959    ///
960    /// Supported operand variants:
961    ///
962    /// ```text
963    /// +---+---------------+
964    /// | # | Operands      |
965    /// +---+---------------+
966    /// | 1 | Xmm, Xmm, Mem |
967    /// | 2 | Xmm, Xmm, Xmm |
968    /// | 3 | Ymm, Ymm, Mem |
969    /// | 4 | Ymm, Ymm, Ymm |
970    /// | 5 | Zmm, Zmm, Mem |
971    /// | 6 | Zmm, Zmm, Zmm |
972    /// +---+---------------+
973    /// ```
974    #[inline]
975    pub fn vdpbf16ps_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
976    where
977        Assembler<'a>: Vdpbf16psMaskEmitter<A, B, C>,
978    {
979        <Self as Vdpbf16psMaskEmitter<A, B, C>>::vdpbf16ps_mask(self, op0, op1, op2);
980    }
981    /// `VDPBF16PS_MASKZ`.
982    ///
983    /// Supported operand variants:
984    ///
985    /// ```text
986    /// +---+---------------+
987    /// | # | Operands      |
988    /// +---+---------------+
989    /// | 1 | Xmm, Xmm, Mem |
990    /// | 2 | Xmm, Xmm, Xmm |
991    /// | 3 | Ymm, Ymm, Mem |
992    /// | 4 | Ymm, Ymm, Ymm |
993    /// | 5 | Zmm, Zmm, Mem |
994    /// | 6 | Zmm, Zmm, Zmm |
995    /// +---+---------------+
996    /// ```
997    #[inline]
998    pub fn vdpbf16ps_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
999    where
1000        Assembler<'a>: Vdpbf16psMaskzEmitter<A, B, C>,
1001    {
1002        <Self as Vdpbf16psMaskzEmitter<A, B, C>>::vdpbf16ps_maskz(self, op0, op1, op2);
1003    }
1004}
asmkit/x86/features/AVX512_BF16.rs

asmkit/x86/features/
AVX512_BF16.rs
