asmkit/x86/features/
AVX512_BITALG.rs

1use super::super::opcodes::*;
2use crate::core::emitter::*;
3use crate::core::operand::*;
4use crate::x86::assembler::*;
5use crate::x86::operands::*;
6
7/// A dummy operand that represents no register. Here just for simplicity.
8const NOREG: Operand = Operand::new();
9
10/// `VPOPCNTB`.
11///
12/// Supported operand variants:
13///
14/// ```text
15/// +---+----------+
16/// | # | Operands |
17/// +---+----------+
18/// | 1 | Xmm, Mem |
19/// | 2 | Xmm, Xmm |
20/// | 3 | Ymm, Mem |
21/// | 4 | Ymm, Ymm |
22/// | 5 | Zmm, Mem |
23/// | 6 | Zmm, Zmm |
24/// +---+----------+
25/// ```
26pub trait VpopcntbEmitter<A, B> {
27    fn vpopcntb(&mut self, op0: A, op1: B);
28}
29
30impl<'a> VpopcntbEmitter<Xmm, Xmm> for Assembler<'a> {
31    fn vpopcntb(&mut self, op0: Xmm, op1: Xmm) {
32        self.emit(
33            VPOPCNTB128RR,
34            op0.as_operand(),
35            op1.as_operand(),
36            &NOREG,
37            &NOREG,
38        );
39    }
40}
41
42impl<'a> VpopcntbEmitter<Xmm, Mem> for Assembler<'a> {
43    fn vpopcntb(&mut self, op0: Xmm, op1: Mem) {
44        self.emit(
45            VPOPCNTB128RM,
46            op0.as_operand(),
47            op1.as_operand(),
48            &NOREG,
49            &NOREG,
50        );
51    }
52}
53
54impl<'a> VpopcntbEmitter<Ymm, Ymm> for Assembler<'a> {
55    fn vpopcntb(&mut self, op0: Ymm, op1: Ymm) {
56        self.emit(
57            VPOPCNTB256RR,
58            op0.as_operand(),
59            op1.as_operand(),
60            &NOREG,
61            &NOREG,
62        );
63    }
64}
65
66impl<'a> VpopcntbEmitter<Ymm, Mem> for Assembler<'a> {
67    fn vpopcntb(&mut self, op0: Ymm, op1: Mem) {
68        self.emit(
69            VPOPCNTB256RM,
70            op0.as_operand(),
71            op1.as_operand(),
72            &NOREG,
73            &NOREG,
74        );
75    }
76}
77
78impl<'a> VpopcntbEmitter<Zmm, Zmm> for Assembler<'a> {
79    fn vpopcntb(&mut self, op0: Zmm, op1: Zmm) {
80        self.emit(
81            VPOPCNTB512RR,
82            op0.as_operand(),
83            op1.as_operand(),
84            &NOREG,
85            &NOREG,
86        );
87    }
88}
89
90impl<'a> VpopcntbEmitter<Zmm, Mem> for Assembler<'a> {
91    fn vpopcntb(&mut self, op0: Zmm, op1: Mem) {
92        self.emit(
93            VPOPCNTB512RM,
94            op0.as_operand(),
95            op1.as_operand(),
96            &NOREG,
97            &NOREG,
98        );
99    }
100}
101
102/// `VPOPCNTB_MASK`.
103///
104/// Supported operand variants:
105///
106/// ```text
107/// +---+----------+
108/// | # | Operands |
109/// +---+----------+
110/// | 1 | Xmm, Mem |
111/// | 2 | Xmm, Xmm |
112/// | 3 | Ymm, Mem |
113/// | 4 | Ymm, Ymm |
114/// | 5 | Zmm, Mem |
115/// | 6 | Zmm, Zmm |
116/// +---+----------+
117/// ```
118pub trait VpopcntbMaskEmitter<A, B> {
119    fn vpopcntb_mask(&mut self, op0: A, op1: B);
120}
121
122impl<'a> VpopcntbMaskEmitter<Xmm, Xmm> for Assembler<'a> {
123    fn vpopcntb_mask(&mut self, op0: Xmm, op1: Xmm) {
124        self.emit(
125            VPOPCNTB128RR_MASK,
126            op0.as_operand(),
127            op1.as_operand(),
128            &NOREG,
129            &NOREG,
130        );
131    }
132}
133
134impl<'a> VpopcntbMaskEmitter<Xmm, Mem> for Assembler<'a> {
135    fn vpopcntb_mask(&mut self, op0: Xmm, op1: Mem) {
136        self.emit(
137            VPOPCNTB128RM_MASK,
138            op0.as_operand(),
139            op1.as_operand(),
140            &NOREG,
141            &NOREG,
142        );
143    }
144}
145
146impl<'a> VpopcntbMaskEmitter<Ymm, Ymm> for Assembler<'a> {
147    fn vpopcntb_mask(&mut self, op0: Ymm, op1: Ymm) {
148        self.emit(
149            VPOPCNTB256RR_MASK,
150            op0.as_operand(),
151            op1.as_operand(),
152            &NOREG,
153            &NOREG,
154        );
155    }
156}
157
158impl<'a> VpopcntbMaskEmitter<Ymm, Mem> for Assembler<'a> {
159    fn vpopcntb_mask(&mut self, op0: Ymm, op1: Mem) {
160        self.emit(
161            VPOPCNTB256RM_MASK,
162            op0.as_operand(),
163            op1.as_operand(),
164            &NOREG,
165            &NOREG,
166        );
167    }
168}
169
170impl<'a> VpopcntbMaskEmitter<Zmm, Zmm> for Assembler<'a> {
171    fn vpopcntb_mask(&mut self, op0: Zmm, op1: Zmm) {
172        self.emit(
173            VPOPCNTB512RR_MASK,
174            op0.as_operand(),
175            op1.as_operand(),
176            &NOREG,
177            &NOREG,
178        );
179    }
180}
181
182impl<'a> VpopcntbMaskEmitter<Zmm, Mem> for Assembler<'a> {
183    fn vpopcntb_mask(&mut self, op0: Zmm, op1: Mem) {
184        self.emit(
185            VPOPCNTB512RM_MASK,
186            op0.as_operand(),
187            op1.as_operand(),
188            &NOREG,
189            &NOREG,
190        );
191    }
192}
193
194/// `VPOPCNTB_MASKZ`.
195///
196/// Supported operand variants:
197///
198/// ```text
199/// +---+----------+
200/// | # | Operands |
201/// +---+----------+
202/// | 1 | Xmm, Mem |
203/// | 2 | Xmm, Xmm |
204/// | 3 | Ymm, Mem |
205/// | 4 | Ymm, Ymm |
206/// | 5 | Zmm, Mem |
207/// | 6 | Zmm, Zmm |
208/// +---+----------+
209/// ```
210pub trait VpopcntbMaskzEmitter<A, B> {
211    fn vpopcntb_maskz(&mut self, op0: A, op1: B);
212}
213
214impl<'a> VpopcntbMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
215    fn vpopcntb_maskz(&mut self, op0: Xmm, op1: Xmm) {
216        self.emit(
217            VPOPCNTB128RR_MASKZ,
218            op0.as_operand(),
219            op1.as_operand(),
220            &NOREG,
221            &NOREG,
222        );
223    }
224}
225
226impl<'a> VpopcntbMaskzEmitter<Xmm, Mem> for Assembler<'a> {
227    fn vpopcntb_maskz(&mut self, op0: Xmm, op1: Mem) {
228        self.emit(
229            VPOPCNTB128RM_MASKZ,
230            op0.as_operand(),
231            op1.as_operand(),
232            &NOREG,
233            &NOREG,
234        );
235    }
236}
237
238impl<'a> VpopcntbMaskzEmitter<Ymm, Ymm> for Assembler<'a> {
239    fn vpopcntb_maskz(&mut self, op0: Ymm, op1: Ymm) {
240        self.emit(
241            VPOPCNTB256RR_MASKZ,
242            op0.as_operand(),
243            op1.as_operand(),
244            &NOREG,
245            &NOREG,
246        );
247    }
248}
249
250impl<'a> VpopcntbMaskzEmitter<Ymm, Mem> for Assembler<'a> {
251    fn vpopcntb_maskz(&mut self, op0: Ymm, op1: Mem) {
252        self.emit(
253            VPOPCNTB256RM_MASKZ,
254            op0.as_operand(),
255            op1.as_operand(),
256            &NOREG,
257            &NOREG,
258        );
259    }
260}
261
262impl<'a> VpopcntbMaskzEmitter<Zmm, Zmm> for Assembler<'a> {
263    fn vpopcntb_maskz(&mut self, op0: Zmm, op1: Zmm) {
264        self.emit(
265            VPOPCNTB512RR_MASKZ,
266            op0.as_operand(),
267            op1.as_operand(),
268            &NOREG,
269            &NOREG,
270        );
271    }
272}
273
274impl<'a> VpopcntbMaskzEmitter<Zmm, Mem> for Assembler<'a> {
275    fn vpopcntb_maskz(&mut self, op0: Zmm, op1: Mem) {
276        self.emit(
277            VPOPCNTB512RM_MASKZ,
278            op0.as_operand(),
279            op1.as_operand(),
280            &NOREG,
281            &NOREG,
282        );
283    }
284}
285
286/// `VPOPCNTW`.
287///
288/// Supported operand variants:
289///
290/// ```text
291/// +---+----------+
292/// | # | Operands |
293/// +---+----------+
294/// | 1 | Xmm, Mem |
295/// | 2 | Xmm, Xmm |
296/// | 3 | Ymm, Mem |
297/// | 4 | Ymm, Ymm |
298/// | 5 | Zmm, Mem |
299/// | 6 | Zmm, Zmm |
300/// +---+----------+
301/// ```
302pub trait VpopcntwEmitter<A, B> {
303    fn vpopcntw(&mut self, op0: A, op1: B);
304}
305
306impl<'a> VpopcntwEmitter<Xmm, Xmm> for Assembler<'a> {
307    fn vpopcntw(&mut self, op0: Xmm, op1: Xmm) {
308        self.emit(
309            VPOPCNTW128RR,
310            op0.as_operand(),
311            op1.as_operand(),
312            &NOREG,
313            &NOREG,
314        );
315    }
316}
317
318impl<'a> VpopcntwEmitter<Xmm, Mem> for Assembler<'a> {
319    fn vpopcntw(&mut self, op0: Xmm, op1: Mem) {
320        self.emit(
321            VPOPCNTW128RM,
322            op0.as_operand(),
323            op1.as_operand(),
324            &NOREG,
325            &NOREG,
326        );
327    }
328}
329
330impl<'a> VpopcntwEmitter<Ymm, Ymm> for Assembler<'a> {
331    fn vpopcntw(&mut self, op0: Ymm, op1: Ymm) {
332        self.emit(
333            VPOPCNTW256RR,
334            op0.as_operand(),
335            op1.as_operand(),
336            &NOREG,
337            &NOREG,
338        );
339    }
340}
341
342impl<'a> VpopcntwEmitter<Ymm, Mem> for Assembler<'a> {
343    fn vpopcntw(&mut self, op0: Ymm, op1: Mem) {
344        self.emit(
345            VPOPCNTW256RM,
346            op0.as_operand(),
347            op1.as_operand(),
348            &NOREG,
349            &NOREG,
350        );
351    }
352}
353
354impl<'a> VpopcntwEmitter<Zmm, Zmm> for Assembler<'a> {
355    fn vpopcntw(&mut self, op0: Zmm, op1: Zmm) {
356        self.emit(
357            VPOPCNTW512RR,
358            op0.as_operand(),
359            op1.as_operand(),
360            &NOREG,
361            &NOREG,
362        );
363    }
364}
365
366impl<'a> VpopcntwEmitter<Zmm, Mem> for Assembler<'a> {
367    fn vpopcntw(&mut self, op0: Zmm, op1: Mem) {
368        self.emit(
369            VPOPCNTW512RM,
370            op0.as_operand(),
371            op1.as_operand(),
372            &NOREG,
373            &NOREG,
374        );
375    }
376}
377
378/// `VPOPCNTW_MASK`.
379///
380/// Supported operand variants:
381///
382/// ```text
383/// +---+----------+
384/// | # | Operands |
385/// +---+----------+
386/// | 1 | Xmm, Mem |
387/// | 2 | Xmm, Xmm |
388/// | 3 | Ymm, Mem |
389/// | 4 | Ymm, Ymm |
390/// | 5 | Zmm, Mem |
391/// | 6 | Zmm, Zmm |
392/// +---+----------+
393/// ```
394pub trait VpopcntwMaskEmitter<A, B> {
395    fn vpopcntw_mask(&mut self, op0: A, op1: B);
396}
397
398impl<'a> VpopcntwMaskEmitter<Xmm, Xmm> for Assembler<'a> {
399    fn vpopcntw_mask(&mut self, op0: Xmm, op1: Xmm) {
400        self.emit(
401            VPOPCNTW128RR_MASK,
402            op0.as_operand(),
403            op1.as_operand(),
404            &NOREG,
405            &NOREG,
406        );
407    }
408}
409
410impl<'a> VpopcntwMaskEmitter<Xmm, Mem> for Assembler<'a> {
411    fn vpopcntw_mask(&mut self, op0: Xmm, op1: Mem) {
412        self.emit(
413            VPOPCNTW128RM_MASK,
414            op0.as_operand(),
415            op1.as_operand(),
416            &NOREG,
417            &NOREG,
418        );
419    }
420}
421
422impl<'a> VpopcntwMaskEmitter<Ymm, Ymm> for Assembler<'a> {
423    fn vpopcntw_mask(&mut self, op0: Ymm, op1: Ymm) {
424        self.emit(
425            VPOPCNTW256RR_MASK,
426            op0.as_operand(),
427            op1.as_operand(),
428            &NOREG,
429            &NOREG,
430        );
431    }
432}
433
434impl<'a> VpopcntwMaskEmitter<Ymm, Mem> for Assembler<'a> {
435    fn vpopcntw_mask(&mut self, op0: Ymm, op1: Mem) {
436        self.emit(
437            VPOPCNTW256RM_MASK,
438            op0.as_operand(),
439            op1.as_operand(),
440            &NOREG,
441            &NOREG,
442        );
443    }
444}
445
446impl<'a> VpopcntwMaskEmitter<Zmm, Zmm> for Assembler<'a> {
447    fn vpopcntw_mask(&mut self, op0: Zmm, op1: Zmm) {
448        self.emit(
449            VPOPCNTW512RR_MASK,
450            op0.as_operand(),
451            op1.as_operand(),
452            &NOREG,
453            &NOREG,
454        );
455    }
456}
457
458impl<'a> VpopcntwMaskEmitter<Zmm, Mem> for Assembler<'a> {
459    fn vpopcntw_mask(&mut self, op0: Zmm, op1: Mem) {
460        self.emit(
461            VPOPCNTW512RM_MASK,
462            op0.as_operand(),
463            op1.as_operand(),
464            &NOREG,
465            &NOREG,
466        );
467    }
468}
469
470/// `VPOPCNTW_MASKZ`.
471///
472/// Supported operand variants:
473///
474/// ```text
475/// +---+----------+
476/// | # | Operands |
477/// +---+----------+
478/// | 1 | Xmm, Mem |
479/// | 2 | Xmm, Xmm |
480/// | 3 | Ymm, Mem |
481/// | 4 | Ymm, Ymm |
482/// | 5 | Zmm, Mem |
483/// | 6 | Zmm, Zmm |
484/// +---+----------+
485/// ```
486pub trait VpopcntwMaskzEmitter<A, B> {
487    fn vpopcntw_maskz(&mut self, op0: A, op1: B);
488}
489
490impl<'a> VpopcntwMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
491    fn vpopcntw_maskz(&mut self, op0: Xmm, op1: Xmm) {
492        self.emit(
493            VPOPCNTW128RR_MASKZ,
494            op0.as_operand(),
495            op1.as_operand(),
496            &NOREG,
497            &NOREG,
498        );
499    }
500}
501
502impl<'a> VpopcntwMaskzEmitter<Xmm, Mem> for Assembler<'a> {
503    fn vpopcntw_maskz(&mut self, op0: Xmm, op1: Mem) {
504        self.emit(
505            VPOPCNTW128RM_MASKZ,
506            op0.as_operand(),
507            op1.as_operand(),
508            &NOREG,
509            &NOREG,
510        );
511    }
512}
513
514impl<'a> VpopcntwMaskzEmitter<Ymm, Ymm> for Assembler<'a> {
515    fn vpopcntw_maskz(&mut self, op0: Ymm, op1: Ymm) {
516        self.emit(
517            VPOPCNTW256RR_MASKZ,
518            op0.as_operand(),
519            op1.as_operand(),
520            &NOREG,
521            &NOREG,
522        );
523    }
524}
525
526impl<'a> VpopcntwMaskzEmitter<Ymm, Mem> for Assembler<'a> {
527    fn vpopcntw_maskz(&mut self, op0: Ymm, op1: Mem) {
528        self.emit(
529            VPOPCNTW256RM_MASKZ,
530            op0.as_operand(),
531            op1.as_operand(),
532            &NOREG,
533            &NOREG,
534        );
535    }
536}
537
538impl<'a> VpopcntwMaskzEmitter<Zmm, Zmm> for Assembler<'a> {
539    fn vpopcntw_maskz(&mut self, op0: Zmm, op1: Zmm) {
540        self.emit(
541            VPOPCNTW512RR_MASKZ,
542            op0.as_operand(),
543            op1.as_operand(),
544            &NOREG,
545            &NOREG,
546        );
547    }
548}
549
550impl<'a> VpopcntwMaskzEmitter<Zmm, Mem> for Assembler<'a> {
551    fn vpopcntw_maskz(&mut self, op0: Zmm, op1: Mem) {
552        self.emit(
553            VPOPCNTW512RM_MASKZ,
554            op0.as_operand(),
555            op1.as_operand(),
556            &NOREG,
557            &NOREG,
558        );
559    }
560}
561
562/// `VPSHUFBITQMB`.
563///
564/// Supported operand variants:
565///
566/// ```text
567/// +---+----------------+
568/// | # | Operands       |
569/// +---+----------------+
570/// | 1 | KReg, Xmm, Mem |
571/// | 2 | KReg, Xmm, Xmm |
572/// | 3 | KReg, Ymm, Mem |
573/// | 4 | KReg, Ymm, Ymm |
574/// | 5 | KReg, Zmm, Mem |
575/// | 6 | KReg, Zmm, Zmm |
576/// +---+----------------+
577/// ```
578pub trait VpshufbitqmbEmitter<A, B, C> {
579    fn vpshufbitqmb(&mut self, op0: A, op1: B, op2: C);
580}
581
582impl<'a> VpshufbitqmbEmitter<KReg, Xmm, Xmm> for Assembler<'a> {
583    fn vpshufbitqmb(&mut self, op0: KReg, op1: Xmm, op2: Xmm) {
584        self.emit(
585            VPSHUFBITQMB128KRR,
586            op0.as_operand(),
587            op1.as_operand(),
588            op2.as_operand(),
589            &NOREG,
590        );
591    }
592}
593
594impl<'a> VpshufbitqmbEmitter<KReg, Xmm, Mem> for Assembler<'a> {
595    fn vpshufbitqmb(&mut self, op0: KReg, op1: Xmm, op2: Mem) {
596        self.emit(
597            VPSHUFBITQMB128KRM,
598            op0.as_operand(),
599            op1.as_operand(),
600            op2.as_operand(),
601            &NOREG,
602        );
603    }
604}
605
606impl<'a> VpshufbitqmbEmitter<KReg, Ymm, Ymm> for Assembler<'a> {
607    fn vpshufbitqmb(&mut self, op0: KReg, op1: Ymm, op2: Ymm) {
608        self.emit(
609            VPSHUFBITQMB256KRR,
610            op0.as_operand(),
611            op1.as_operand(),
612            op2.as_operand(),
613            &NOREG,
614        );
615    }
616}
617
618impl<'a> VpshufbitqmbEmitter<KReg, Ymm, Mem> for Assembler<'a> {
619    fn vpshufbitqmb(&mut self, op0: KReg, op1: Ymm, op2: Mem) {
620        self.emit(
621            VPSHUFBITQMB256KRM,
622            op0.as_operand(),
623            op1.as_operand(),
624            op2.as_operand(),
625            &NOREG,
626        );
627    }
628}
629
630impl<'a> VpshufbitqmbEmitter<KReg, Zmm, Zmm> for Assembler<'a> {
631    fn vpshufbitqmb(&mut self, op0: KReg, op1: Zmm, op2: Zmm) {
632        self.emit(
633            VPSHUFBITQMB512KRR,
634            op0.as_operand(),
635            op1.as_operand(),
636            op2.as_operand(),
637            &NOREG,
638        );
639    }
640}
641
642impl<'a> VpshufbitqmbEmitter<KReg, Zmm, Mem> for Assembler<'a> {
643    fn vpshufbitqmb(&mut self, op0: KReg, op1: Zmm, op2: Mem) {
644        self.emit(
645            VPSHUFBITQMB512KRM,
646            op0.as_operand(),
647            op1.as_operand(),
648            op2.as_operand(),
649            &NOREG,
650        );
651    }
652}
653
654/// `VPSHUFBITQMB_MASK`.
655///
656/// Supported operand variants:
657///
658/// ```text
659/// +---+----------------+
660/// | # | Operands       |
661/// +---+----------------+
662/// | 1 | KReg, Xmm, Mem |
663/// | 2 | KReg, Xmm, Xmm |
664/// | 3 | KReg, Ymm, Mem |
665/// | 4 | KReg, Ymm, Ymm |
666/// | 5 | KReg, Zmm, Mem |
667/// | 6 | KReg, Zmm, Zmm |
668/// +---+----------------+
669/// ```
670pub trait VpshufbitqmbMaskEmitter<A, B, C> {
671    fn vpshufbitqmb_mask(&mut self, op0: A, op1: B, op2: C);
672}
673
674impl<'a> VpshufbitqmbMaskEmitter<KReg, Xmm, Xmm> for Assembler<'a> {
675    fn vpshufbitqmb_mask(&mut self, op0: KReg, op1: Xmm, op2: Xmm) {
676        self.emit(
677            VPSHUFBITQMB128KRR_MASK,
678            op0.as_operand(),
679            op1.as_operand(),
680            op2.as_operand(),
681            &NOREG,
682        );
683    }
684}
685
686impl<'a> VpshufbitqmbMaskEmitter<KReg, Xmm, Mem> for Assembler<'a> {
687    fn vpshufbitqmb_mask(&mut self, op0: KReg, op1: Xmm, op2: Mem) {
688        self.emit(
689            VPSHUFBITQMB128KRM_MASK,
690            op0.as_operand(),
691            op1.as_operand(),
692            op2.as_operand(),
693            &NOREG,
694        );
695    }
696}
697
698impl<'a> VpshufbitqmbMaskEmitter<KReg, Ymm, Ymm> for Assembler<'a> {
699    fn vpshufbitqmb_mask(&mut self, op0: KReg, op1: Ymm, op2: Ymm) {
700        self.emit(
701            VPSHUFBITQMB256KRR_MASK,
702            op0.as_operand(),
703            op1.as_operand(),
704            op2.as_operand(),
705            &NOREG,
706        );
707    }
708}
709
710impl<'a> VpshufbitqmbMaskEmitter<KReg, Ymm, Mem> for Assembler<'a> {
711    fn vpshufbitqmb_mask(&mut self, op0: KReg, op1: Ymm, op2: Mem) {
712        self.emit(
713            VPSHUFBITQMB256KRM_MASK,
714            op0.as_operand(),
715            op1.as_operand(),
716            op2.as_operand(),
717            &NOREG,
718        );
719    }
720}
721
722impl<'a> VpshufbitqmbMaskEmitter<KReg, Zmm, Zmm> for Assembler<'a> {
723    fn vpshufbitqmb_mask(&mut self, op0: KReg, op1: Zmm, op2: Zmm) {
724        self.emit(
725            VPSHUFBITQMB512KRR_MASK,
726            op0.as_operand(),
727            op1.as_operand(),
728            op2.as_operand(),
729            &NOREG,
730        );
731    }
732}
733
734impl<'a> VpshufbitqmbMaskEmitter<KReg, Zmm, Mem> for Assembler<'a> {
735    fn vpshufbitqmb_mask(&mut self, op0: KReg, op1: Zmm, op2: Mem) {
736        self.emit(
737            VPSHUFBITQMB512KRM_MASK,
738            op0.as_operand(),
739            op1.as_operand(),
740            op2.as_operand(),
741            &NOREG,
742        );
743    }
744}
745
746impl<'a> Assembler<'a> {
747    /// `VPOPCNTB`.
748    ///
749    /// Supported operand variants:
750    ///
751    /// ```text
752    /// +---+----------+
753    /// | # | Operands |
754    /// +---+----------+
755    /// | 1 | Xmm, Mem |
756    /// | 2 | Xmm, Xmm |
757    /// | 3 | Ymm, Mem |
758    /// | 4 | Ymm, Ymm |
759    /// | 5 | Zmm, Mem |
760    /// | 6 | Zmm, Zmm |
761    /// +---+----------+
762    /// ```
763    #[inline]
764    pub fn vpopcntb<A, B>(&mut self, op0: A, op1: B)
765    where
766        Assembler<'a>: VpopcntbEmitter<A, B>,
767    {
768        <Self as VpopcntbEmitter<A, B>>::vpopcntb(self, op0, op1);
769    }
770    /// `VPOPCNTB_MASK`.
771    ///
772    /// Supported operand variants:
773    ///
774    /// ```text
775    /// +---+----------+
776    /// | # | Operands |
777    /// +---+----------+
778    /// | 1 | Xmm, Mem |
779    /// | 2 | Xmm, Xmm |
780    /// | 3 | Ymm, Mem |
781    /// | 4 | Ymm, Ymm |
782    /// | 5 | Zmm, Mem |
783    /// | 6 | Zmm, Zmm |
784    /// +---+----------+
785    /// ```
786    #[inline]
787    pub fn vpopcntb_mask<A, B>(&mut self, op0: A, op1: B)
788    where
789        Assembler<'a>: VpopcntbMaskEmitter<A, B>,
790    {
791        <Self as VpopcntbMaskEmitter<A, B>>::vpopcntb_mask(self, op0, op1);
792    }
793    /// `VPOPCNTB_MASKZ`.
794    ///
795    /// Supported operand variants:
796    ///
797    /// ```text
798    /// +---+----------+
799    /// | # | Operands |
800    /// +---+----------+
801    /// | 1 | Xmm, Mem |
802    /// | 2 | Xmm, Xmm |
803    /// | 3 | Ymm, Mem |
804    /// | 4 | Ymm, Ymm |
805    /// | 5 | Zmm, Mem |
806    /// | 6 | Zmm, Zmm |
807    /// +---+----------+
808    /// ```
809    #[inline]
810    pub fn vpopcntb_maskz<A, B>(&mut self, op0: A, op1: B)
811    where
812        Assembler<'a>: VpopcntbMaskzEmitter<A, B>,
813    {
814        <Self as VpopcntbMaskzEmitter<A, B>>::vpopcntb_maskz(self, op0, op1);
815    }
816    /// `VPOPCNTW`.
817    ///
818    /// Supported operand variants:
819    ///
820    /// ```text
821    /// +---+----------+
822    /// | # | Operands |
823    /// +---+----------+
824    /// | 1 | Xmm, Mem |
825    /// | 2 | Xmm, Xmm |
826    /// | 3 | Ymm, Mem |
827    /// | 4 | Ymm, Ymm |
828    /// | 5 | Zmm, Mem |
829    /// | 6 | Zmm, Zmm |
830    /// +---+----------+
831    /// ```
832    #[inline]
833    pub fn vpopcntw<A, B>(&mut self, op0: A, op1: B)
834    where
835        Assembler<'a>: VpopcntwEmitter<A, B>,
836    {
837        <Self as VpopcntwEmitter<A, B>>::vpopcntw(self, op0, op1);
838    }
839    /// `VPOPCNTW_MASK`.
840    ///
841    /// Supported operand variants:
842    ///
843    /// ```text
844    /// +---+----------+
845    /// | # | Operands |
846    /// +---+----------+
847    /// | 1 | Xmm, Mem |
848    /// | 2 | Xmm, Xmm |
849    /// | 3 | Ymm, Mem |
850    /// | 4 | Ymm, Ymm |
851    /// | 5 | Zmm, Mem |
852    /// | 6 | Zmm, Zmm |
853    /// +---+----------+
854    /// ```
855    #[inline]
856    pub fn vpopcntw_mask<A, B>(&mut self, op0: A, op1: B)
857    where
858        Assembler<'a>: VpopcntwMaskEmitter<A, B>,
859    {
860        <Self as VpopcntwMaskEmitter<A, B>>::vpopcntw_mask(self, op0, op1);
861    }
862    /// `VPOPCNTW_MASKZ`.
863    ///
864    /// Supported operand variants:
865    ///
866    /// ```text
867    /// +---+----------+
868    /// | # | Operands |
869    /// +---+----------+
870    /// | 1 | Xmm, Mem |
871    /// | 2 | Xmm, Xmm |
872    /// | 3 | Ymm, Mem |
873    /// | 4 | Ymm, Ymm |
874    /// | 5 | Zmm, Mem |
875    /// | 6 | Zmm, Zmm |
876    /// +---+----------+
877    /// ```
878    #[inline]
879    pub fn vpopcntw_maskz<A, B>(&mut self, op0: A, op1: B)
880    where
881        Assembler<'a>: VpopcntwMaskzEmitter<A, B>,
882    {
883        <Self as VpopcntwMaskzEmitter<A, B>>::vpopcntw_maskz(self, op0, op1);
884    }
885    /// `VPSHUFBITQMB`.
886    ///
887    /// Supported operand variants:
888    ///
889    /// ```text
890    /// +---+----------------+
891    /// | # | Operands       |
892    /// +---+----------------+
893    /// | 1 | KReg, Xmm, Mem |
894    /// | 2 | KReg, Xmm, Xmm |
895    /// | 3 | KReg, Ymm, Mem |
896    /// | 4 | KReg, Ymm, Ymm |
897    /// | 5 | KReg, Zmm, Mem |
898    /// | 6 | KReg, Zmm, Zmm |
899    /// +---+----------------+
900    /// ```
901    #[inline]
902    pub fn vpshufbitqmb<A, B, C>(&mut self, op0: A, op1: B, op2: C)
903    where
904        Assembler<'a>: VpshufbitqmbEmitter<A, B, C>,
905    {
906        <Self as VpshufbitqmbEmitter<A, B, C>>::vpshufbitqmb(self, op0, op1, op2);
907    }
908    /// `VPSHUFBITQMB_MASK`.
909    ///
910    /// Supported operand variants:
911    ///
912    /// ```text
913    /// +---+----------------+
914    /// | # | Operands       |
915    /// +---+----------------+
916    /// | 1 | KReg, Xmm, Mem |
917    /// | 2 | KReg, Xmm, Xmm |
918    /// | 3 | KReg, Ymm, Mem |
919    /// | 4 | KReg, Ymm, Ymm |
920    /// | 5 | KReg, Zmm, Mem |
921    /// | 6 | KReg, Zmm, Zmm |
922    /// +---+----------------+
923    /// ```
924    #[inline]
925    pub fn vpshufbitqmb_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
926    where
927        Assembler<'a>: VpshufbitqmbMaskEmitter<A, B, C>,
928    {
929        <Self as VpshufbitqmbMaskEmitter<A, B, C>>::vpshufbitqmb_mask(self, op0, op1, op2);
930    }
931}
asmkit/x86/features/AVX512_BITALG.rs

asmkit/x86/features/
AVX512_BITALG.rs
