asmkit/x86/features/
SHA.rs

1use super::super::opcodes::*;
2use crate::core::emitter::*;
3use crate::core::operand::*;
4use crate::x86::assembler::*;
5use crate::x86::operands::*;
6
7/// A dummy operand that represents no register. Here just for simplicity.
8const NOREG: Operand = Operand::new();
9
10/// `SHA1MSG1`.
11///
12/// Supported operand variants:
13///
14/// ```text
15/// +---+----------+
16/// | # | Operands |
17/// +---+----------+
18/// | 1 | Xmm, Mem |
19/// | 2 | Xmm, Xmm |
20/// +---+----------+
21/// ```
22pub trait Sha1msg1Emitter<A, B> {
23    fn sha1msg1(&mut self, op0: A, op1: B);
24}
25
26impl<'a> Sha1msg1Emitter<Xmm, Xmm> for Assembler<'a> {
27    fn sha1msg1(&mut self, op0: Xmm, op1: Xmm) {
28        self.emit(
29            SHA1MSG1RR,
30            op0.as_operand(),
31            op1.as_operand(),
32            &NOREG,
33            &NOREG,
34        );
35    }
36}
37
38impl<'a> Sha1msg1Emitter<Xmm, Mem> for Assembler<'a> {
39    fn sha1msg1(&mut self, op0: Xmm, op1: Mem) {
40        self.emit(
41            SHA1MSG1RM,
42            op0.as_operand(),
43            op1.as_operand(),
44            &NOREG,
45            &NOREG,
46        );
47    }
48}
49
50/// `SHA1MSG2`.
51///
52/// Supported operand variants:
53///
54/// ```text
55/// +---+----------+
56/// | # | Operands |
57/// +---+----------+
58/// | 1 | Xmm, Mem |
59/// | 2 | Xmm, Xmm |
60/// +---+----------+
61/// ```
62pub trait Sha1msg2Emitter<A, B> {
63    fn sha1msg2(&mut self, op0: A, op1: B);
64}
65
66impl<'a> Sha1msg2Emitter<Xmm, Xmm> for Assembler<'a> {
67    fn sha1msg2(&mut self, op0: Xmm, op1: Xmm) {
68        self.emit(
69            SHA1MSG2RR,
70            op0.as_operand(),
71            op1.as_operand(),
72            &NOREG,
73            &NOREG,
74        );
75    }
76}
77
78impl<'a> Sha1msg2Emitter<Xmm, Mem> for Assembler<'a> {
79    fn sha1msg2(&mut self, op0: Xmm, op1: Mem) {
80        self.emit(
81            SHA1MSG2RM,
82            op0.as_operand(),
83            op1.as_operand(),
84            &NOREG,
85            &NOREG,
86        );
87    }
88}
89
90/// `SHA1NEXTE`.
91///
92/// Supported operand variants:
93///
94/// ```text
95/// +---+----------+
96/// | # | Operands |
97/// +---+----------+
98/// | 1 | Xmm, Mem |
99/// | 2 | Xmm, Xmm |
100/// +---+----------+
101/// ```
102pub trait Sha1nexteEmitter<A, B> {
103    fn sha1nexte(&mut self, op0: A, op1: B);
104}
105
106impl<'a> Sha1nexteEmitter<Xmm, Xmm> for Assembler<'a> {
107    fn sha1nexte(&mut self, op0: Xmm, op1: Xmm) {
108        self.emit(
109            SHA1NEXTERR,
110            op0.as_operand(),
111            op1.as_operand(),
112            &NOREG,
113            &NOREG,
114        );
115    }
116}
117
118impl<'a> Sha1nexteEmitter<Xmm, Mem> for Assembler<'a> {
119    fn sha1nexte(&mut self, op0: Xmm, op1: Mem) {
120        self.emit(
121            SHA1NEXTERM,
122            op0.as_operand(),
123            op1.as_operand(),
124            &NOREG,
125            &NOREG,
126        );
127    }
128}
129
130/// `SHA1RNDS4`.
131///
132/// Supported operand variants:
133///
134/// ```text
135/// +---+---------------+
136/// | # | Operands      |
137/// +---+---------------+
138/// | 1 | Xmm, Mem, Imm |
139/// | 2 | Xmm, Xmm, Imm |
140/// +---+---------------+
141/// ```
142pub trait Sha1rnds4Emitter<A, B, C> {
143    fn sha1rnds4(&mut self, op0: A, op1: B, op2: C);
144}
145
146impl<'a> Sha1rnds4Emitter<Xmm, Xmm, Imm> for Assembler<'a> {
147    fn sha1rnds4(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
148        self.emit(
149            SHA1RNDS4RRI,
150            op0.as_operand(),
151            op1.as_operand(),
152            op2.as_operand(),
153            &NOREG,
154        );
155    }
156}
157
158impl<'a> Sha1rnds4Emitter<Xmm, Mem, Imm> for Assembler<'a> {
159    fn sha1rnds4(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
160        self.emit(
161            SHA1RNDS4RMI,
162            op0.as_operand(),
163            op1.as_operand(),
164            op2.as_operand(),
165            &NOREG,
166        );
167    }
168}
169
170/// `SHA256MSG1`.
171///
172/// Supported operand variants:
173///
174/// ```text
175/// +---+----------+
176/// | # | Operands |
177/// +---+----------+
178/// | 1 | Xmm, Mem |
179/// | 2 | Xmm, Xmm |
180/// +---+----------+
181/// ```
182pub trait Sha256msg1Emitter<A, B> {
183    fn sha256msg1(&mut self, op0: A, op1: B);
184}
185
186impl<'a> Sha256msg1Emitter<Xmm, Xmm> for Assembler<'a> {
187    fn sha256msg1(&mut self, op0: Xmm, op1: Xmm) {
188        self.emit(
189            SHA256MSG1RR,
190            op0.as_operand(),
191            op1.as_operand(),
192            &NOREG,
193            &NOREG,
194        );
195    }
196}
197
198impl<'a> Sha256msg1Emitter<Xmm, Mem> for Assembler<'a> {
199    fn sha256msg1(&mut self, op0: Xmm, op1: Mem) {
200        self.emit(
201            SHA256MSG1RM,
202            op0.as_operand(),
203            op1.as_operand(),
204            &NOREG,
205            &NOREG,
206        );
207    }
208}
209
210/// `SHA256MSG2`.
211///
212/// Supported operand variants:
213///
214/// ```text
215/// +---+----------+
216/// | # | Operands |
217/// +---+----------+
218/// | 1 | Xmm, Mem |
219/// | 2 | Xmm, Xmm |
220/// +---+----------+
221/// ```
222pub trait Sha256msg2Emitter<A, B> {
223    fn sha256msg2(&mut self, op0: A, op1: B);
224}
225
226impl<'a> Sha256msg2Emitter<Xmm, Xmm> for Assembler<'a> {
227    fn sha256msg2(&mut self, op0: Xmm, op1: Xmm) {
228        self.emit(
229            SHA256MSG2RR,
230            op0.as_operand(),
231            op1.as_operand(),
232            &NOREG,
233            &NOREG,
234        );
235    }
236}
237
238impl<'a> Sha256msg2Emitter<Xmm, Mem> for Assembler<'a> {
239    fn sha256msg2(&mut self, op0: Xmm, op1: Mem) {
240        self.emit(
241            SHA256MSG2RM,
242            op0.as_operand(),
243            op1.as_operand(),
244            &NOREG,
245            &NOREG,
246        );
247    }
248}
249
250/// `SHA256RNDS2`.
251///
252/// Supported operand variants:
253///
254/// ```text
255/// +---+---------------+
256/// | # | Operands      |
257/// +---+---------------+
258/// | 1 | Xmm, Mem, Xmm |
259/// | 2 | Xmm, Xmm, Xmm |
260/// +---+---------------+
261/// ```
262pub trait Sha256rnds2Emitter<A, B, C> {
263    fn sha256rnds2(&mut self, op0: A, op1: B, op2: C);
264}
265
266impl<'a> Sha256rnds2Emitter<Xmm, Xmm, Xmm> for Assembler<'a> {
267    fn sha256rnds2(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
268        self.emit(
269            SHA256RNDS2RRR,
270            op0.as_operand(),
271            op1.as_operand(),
272            op2.as_operand(),
273            &NOREG,
274        );
275    }
276}
277
278impl<'a> Sha256rnds2Emitter<Xmm, Mem, Xmm> for Assembler<'a> {
279    fn sha256rnds2(&mut self, op0: Xmm, op1: Mem, op2: Xmm) {
280        self.emit(
281            SHA256RNDS2RMR,
282            op0.as_operand(),
283            op1.as_operand(),
284            op2.as_operand(),
285            &NOREG,
286        );
287    }
288}
289
290impl<'a> Assembler<'a> {
291    /// `SHA1MSG1`.
292    ///
293    /// Supported operand variants:
294    ///
295    /// ```text
296    /// +---+----------+
297    /// | # | Operands |
298    /// +---+----------+
299    /// | 1 | Xmm, Mem |
300    /// | 2 | Xmm, Xmm |
301    /// +---+----------+
302    /// ```
303    #[inline]
304    pub fn sha1msg1<A, B>(&mut self, op0: A, op1: B)
305    where
306        Assembler<'a>: Sha1msg1Emitter<A, B>,
307    {
308        <Self as Sha1msg1Emitter<A, B>>::sha1msg1(self, op0, op1);
309    }
310    /// `SHA1MSG2`.
311    ///
312    /// Supported operand variants:
313    ///
314    /// ```text
315    /// +---+----------+
316    /// | # | Operands |
317    /// +---+----------+
318    /// | 1 | Xmm, Mem |
319    /// | 2 | Xmm, Xmm |
320    /// +---+----------+
321    /// ```
322    #[inline]
323    pub fn sha1msg2<A, B>(&mut self, op0: A, op1: B)
324    where
325        Assembler<'a>: Sha1msg2Emitter<A, B>,
326    {
327        <Self as Sha1msg2Emitter<A, B>>::sha1msg2(self, op0, op1);
328    }
329    /// `SHA1NEXTE`.
330    ///
331    /// Supported operand variants:
332    ///
333    /// ```text
334    /// +---+----------+
335    /// | # | Operands |
336    /// +---+----------+
337    /// | 1 | Xmm, Mem |
338    /// | 2 | Xmm, Xmm |
339    /// +---+----------+
340    /// ```
341    #[inline]
342    pub fn sha1nexte<A, B>(&mut self, op0: A, op1: B)
343    where
344        Assembler<'a>: Sha1nexteEmitter<A, B>,
345    {
346        <Self as Sha1nexteEmitter<A, B>>::sha1nexte(self, op0, op1);
347    }
348    /// `SHA1RNDS4`.
349    ///
350    /// Supported operand variants:
351    ///
352    /// ```text
353    /// +---+---------------+
354    /// | # | Operands      |
355    /// +---+---------------+
356    /// | 1 | Xmm, Mem, Imm |
357    /// | 2 | Xmm, Xmm, Imm |
358    /// +---+---------------+
359    /// ```
360    #[inline]
361    pub fn sha1rnds4<A, B, C>(&mut self, op0: A, op1: B, op2: C)
362    where
363        Assembler<'a>: Sha1rnds4Emitter<A, B, C>,
364    {
365        <Self as Sha1rnds4Emitter<A, B, C>>::sha1rnds4(self, op0, op1, op2);
366    }
367    /// `SHA256MSG1`.
368    ///
369    /// Supported operand variants:
370    ///
371    /// ```text
372    /// +---+----------+
373    /// | # | Operands |
374    /// +---+----------+
375    /// | 1 | Xmm, Mem |
376    /// | 2 | Xmm, Xmm |
377    /// +---+----------+
378    /// ```
379    #[inline]
380    pub fn sha256msg1<A, B>(&mut self, op0: A, op1: B)
381    where
382        Assembler<'a>: Sha256msg1Emitter<A, B>,
383    {
384        <Self as Sha256msg1Emitter<A, B>>::sha256msg1(self, op0, op1);
385    }
386    /// `SHA256MSG2`.
387    ///
388    /// Supported operand variants:
389    ///
390    /// ```text
391    /// +---+----------+
392    /// | # | Operands |
393    /// +---+----------+
394    /// | 1 | Xmm, Mem |
395    /// | 2 | Xmm, Xmm |
396    /// +---+----------+
397    /// ```
398    #[inline]
399    pub fn sha256msg2<A, B>(&mut self, op0: A, op1: B)
400    where
401        Assembler<'a>: Sha256msg2Emitter<A, B>,
402    {
403        <Self as Sha256msg2Emitter<A, B>>::sha256msg2(self, op0, op1);
404    }
405    /// `SHA256RNDS2`.
406    ///
407    /// Supported operand variants:
408    ///
409    /// ```text
410    /// +---+---------------+
411    /// | # | Operands      |
412    /// +---+---------------+
413    /// | 1 | Xmm, Mem, Xmm |
414    /// | 2 | Xmm, Xmm, Xmm |
415    /// +---+---------------+
416    /// ```
417    #[inline]
418    pub fn sha256rnds2<A, B, C>(&mut self, op0: A, op1: B, op2: C)
419    where
420        Assembler<'a>: Sha256rnds2Emitter<A, B, C>,
421    {
422        <Self as Sha256rnds2Emitter<A, B, C>>::sha256rnds2(self, op0, op1, op2);
423    }
424}
asmkit/x86/features/SHA.rs

asmkit/x86/features/
SHA.rs
