asmkit/x86/features/
AVX512_VBMI2.rs

1use super::super::opcodes::*;
2use crate::core::emitter::*;
3use crate::core::operand::*;
4use crate::x86::assembler::*;
5use crate::x86::operands::*;
6
7/// A dummy operand that represents no register. Here just for simplicity.
8const NOREG: Operand = Operand::new();
9
10/// `VPCOMPRESSB`.
11///
12/// Supported operand variants:
13///
14/// ```text
15/// +---+----------+
16/// | # | Operands |
17/// +---+----------+
18/// | 1 | Mem, Xmm |
19/// | 2 | Mem, Ymm |
20/// | 3 | Mem, Zmm |
21/// | 4 | Xmm, Xmm |
22/// | 5 | Ymm, Ymm |
23/// | 6 | Zmm, Zmm |
24/// +---+----------+
25/// ```
26pub trait VpcompressbEmitter<A, B> {
27    fn vpcompressb(&mut self, op0: A, op1: B);
28}
29
30impl<'a> VpcompressbEmitter<Mem, Xmm> for Assembler<'a> {
31    fn vpcompressb(&mut self, op0: Mem, op1: Xmm) {
32        self.emit(
33            VPCOMPRESSB128MR,
34            op0.as_operand(),
35            op1.as_operand(),
36            &NOREG,
37            &NOREG,
38        );
39    }
40}
41
42impl<'a> VpcompressbEmitter<Mem, Ymm> for Assembler<'a> {
43    fn vpcompressb(&mut self, op0: Mem, op1: Ymm) {
44        self.emit(
45            VPCOMPRESSB256MR,
46            op0.as_operand(),
47            op1.as_operand(),
48            &NOREG,
49            &NOREG,
50        );
51    }
52}
53
54impl<'a> VpcompressbEmitter<Mem, Zmm> for Assembler<'a> {
55    fn vpcompressb(&mut self, op0: Mem, op1: Zmm) {
56        self.emit(
57            VPCOMPRESSB512MR,
58            op0.as_operand(),
59            op1.as_operand(),
60            &NOREG,
61            &NOREG,
62        );
63    }
64}
65
66impl<'a> VpcompressbEmitter<Xmm, Xmm> for Assembler<'a> {
67    fn vpcompressb(&mut self, op0: Xmm, op1: Xmm) {
68        self.emit(
69            VPCOMPRESSB128RR,
70            op0.as_operand(),
71            op1.as_operand(),
72            &NOREG,
73            &NOREG,
74        );
75    }
76}
77
78impl<'a> VpcompressbEmitter<Ymm, Ymm> for Assembler<'a> {
79    fn vpcompressb(&mut self, op0: Ymm, op1: Ymm) {
80        self.emit(
81            VPCOMPRESSB256RR,
82            op0.as_operand(),
83            op1.as_operand(),
84            &NOREG,
85            &NOREG,
86        );
87    }
88}
89
90impl<'a> VpcompressbEmitter<Zmm, Zmm> for Assembler<'a> {
91    fn vpcompressb(&mut self, op0: Zmm, op1: Zmm) {
92        self.emit(
93            VPCOMPRESSB512RR,
94            op0.as_operand(),
95            op1.as_operand(),
96            &NOREG,
97            &NOREG,
98        );
99    }
100}
101
102/// `VPCOMPRESSB_MASK`.
103///
104/// Supported operand variants:
105///
106/// ```text
107/// +---+----------+
108/// | # | Operands |
109/// +---+----------+
110/// | 1 | Mem, Xmm |
111/// | 2 | Mem, Ymm |
112/// | 3 | Mem, Zmm |
113/// | 4 | Xmm, Xmm |
114/// | 5 | Ymm, Ymm |
115/// | 6 | Zmm, Zmm |
116/// +---+----------+
117/// ```
118pub trait VpcompressbMaskEmitter<A, B> {
119    fn vpcompressb_mask(&mut self, op0: A, op1: B);
120}
121
122impl<'a> VpcompressbMaskEmitter<Mem, Xmm> for Assembler<'a> {
123    fn vpcompressb_mask(&mut self, op0: Mem, op1: Xmm) {
124        self.emit(
125            VPCOMPRESSB128MR_MASK,
126            op0.as_operand(),
127            op1.as_operand(),
128            &NOREG,
129            &NOREG,
130        );
131    }
132}
133
134impl<'a> VpcompressbMaskEmitter<Mem, Ymm> for Assembler<'a> {
135    fn vpcompressb_mask(&mut self, op0: Mem, op1: Ymm) {
136        self.emit(
137            VPCOMPRESSB256MR_MASK,
138            op0.as_operand(),
139            op1.as_operand(),
140            &NOREG,
141            &NOREG,
142        );
143    }
144}
145
146impl<'a> VpcompressbMaskEmitter<Mem, Zmm> for Assembler<'a> {
147    fn vpcompressb_mask(&mut self, op0: Mem, op1: Zmm) {
148        self.emit(
149            VPCOMPRESSB512MR_MASK,
150            op0.as_operand(),
151            op1.as_operand(),
152            &NOREG,
153            &NOREG,
154        );
155    }
156}
157
158impl<'a> VpcompressbMaskEmitter<Xmm, Xmm> for Assembler<'a> {
159    fn vpcompressb_mask(&mut self, op0: Xmm, op1: Xmm) {
160        self.emit(
161            VPCOMPRESSB128RR_MASK,
162            op0.as_operand(),
163            op1.as_operand(),
164            &NOREG,
165            &NOREG,
166        );
167    }
168}
169
170impl<'a> VpcompressbMaskEmitter<Ymm, Ymm> for Assembler<'a> {
171    fn vpcompressb_mask(&mut self, op0: Ymm, op1: Ymm) {
172        self.emit(
173            VPCOMPRESSB256RR_MASK,
174            op0.as_operand(),
175            op1.as_operand(),
176            &NOREG,
177            &NOREG,
178        );
179    }
180}
181
182impl<'a> VpcompressbMaskEmitter<Zmm, Zmm> for Assembler<'a> {
183    fn vpcompressb_mask(&mut self, op0: Zmm, op1: Zmm) {
184        self.emit(
185            VPCOMPRESSB512RR_MASK,
186            op0.as_operand(),
187            op1.as_operand(),
188            &NOREG,
189            &NOREG,
190        );
191    }
192}
193
194/// `VPCOMPRESSB_MASKZ`.
195///
196/// Supported operand variants:
197///
198/// ```text
199/// +---+----------+
200/// | # | Operands |
201/// +---+----------+
202/// | 1 | Xmm, Xmm |
203/// | 2 | Ymm, Ymm |
204/// | 3 | Zmm, Zmm |
205/// +---+----------+
206/// ```
207pub trait VpcompressbMaskzEmitter<A, B> {
208    fn vpcompressb_maskz(&mut self, op0: A, op1: B);
209}
210
211impl<'a> VpcompressbMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
212    fn vpcompressb_maskz(&mut self, op0: Xmm, op1: Xmm) {
213        self.emit(
214            VPCOMPRESSB128RR_MASKZ,
215            op0.as_operand(),
216            op1.as_operand(),
217            &NOREG,
218            &NOREG,
219        );
220    }
221}
222
223impl<'a> VpcompressbMaskzEmitter<Ymm, Ymm> for Assembler<'a> {
224    fn vpcompressb_maskz(&mut self, op0: Ymm, op1: Ymm) {
225        self.emit(
226            VPCOMPRESSB256RR_MASKZ,
227            op0.as_operand(),
228            op1.as_operand(),
229            &NOREG,
230            &NOREG,
231        );
232    }
233}
234
235impl<'a> VpcompressbMaskzEmitter<Zmm, Zmm> for Assembler<'a> {
236    fn vpcompressb_maskz(&mut self, op0: Zmm, op1: Zmm) {
237        self.emit(
238            VPCOMPRESSB512RR_MASKZ,
239            op0.as_operand(),
240            op1.as_operand(),
241            &NOREG,
242            &NOREG,
243        );
244    }
245}
246
247/// `VPCOMPRESSW`.
248///
249/// Supported operand variants:
250///
251/// ```text
252/// +---+----------+
253/// | # | Operands |
254/// +---+----------+
255/// | 1 | Mem, Xmm |
256/// | 2 | Mem, Ymm |
257/// | 3 | Mem, Zmm |
258/// | 4 | Xmm, Xmm |
259/// | 5 | Ymm, Ymm |
260/// | 6 | Zmm, Zmm |
261/// +---+----------+
262/// ```
263pub trait VpcompresswEmitter<A, B> {
264    fn vpcompressw(&mut self, op0: A, op1: B);
265}
266
267impl<'a> VpcompresswEmitter<Mem, Xmm> for Assembler<'a> {
268    fn vpcompressw(&mut self, op0: Mem, op1: Xmm) {
269        self.emit(
270            VPCOMPRESSW128MR,
271            op0.as_operand(),
272            op1.as_operand(),
273            &NOREG,
274            &NOREG,
275        );
276    }
277}
278
279impl<'a> VpcompresswEmitter<Mem, Ymm> for Assembler<'a> {
280    fn vpcompressw(&mut self, op0: Mem, op1: Ymm) {
281        self.emit(
282            VPCOMPRESSW256MR,
283            op0.as_operand(),
284            op1.as_operand(),
285            &NOREG,
286            &NOREG,
287        );
288    }
289}
290
291impl<'a> VpcompresswEmitter<Mem, Zmm> for Assembler<'a> {
292    fn vpcompressw(&mut self, op0: Mem, op1: Zmm) {
293        self.emit(
294            VPCOMPRESSW512MR,
295            op0.as_operand(),
296            op1.as_operand(),
297            &NOREG,
298            &NOREG,
299        );
300    }
301}
302
303impl<'a> VpcompresswEmitter<Xmm, Xmm> for Assembler<'a> {
304    fn vpcompressw(&mut self, op0: Xmm, op1: Xmm) {
305        self.emit(
306            VPCOMPRESSW128RR,
307            op0.as_operand(),
308            op1.as_operand(),
309            &NOREG,
310            &NOREG,
311        );
312    }
313}
314
315impl<'a> VpcompresswEmitter<Ymm, Ymm> for Assembler<'a> {
316    fn vpcompressw(&mut self, op0: Ymm, op1: Ymm) {
317        self.emit(
318            VPCOMPRESSW256RR,
319            op0.as_operand(),
320            op1.as_operand(),
321            &NOREG,
322            &NOREG,
323        );
324    }
325}
326
327impl<'a> VpcompresswEmitter<Zmm, Zmm> for Assembler<'a> {
328    fn vpcompressw(&mut self, op0: Zmm, op1: Zmm) {
329        self.emit(
330            VPCOMPRESSW512RR,
331            op0.as_operand(),
332            op1.as_operand(),
333            &NOREG,
334            &NOREG,
335        );
336    }
337}
338
339/// `VPCOMPRESSW_MASK`.
340///
341/// Supported operand variants:
342///
343/// ```text
344/// +---+----------+
345/// | # | Operands |
346/// +---+----------+
347/// | 1 | Mem, Xmm |
348/// | 2 | Mem, Ymm |
349/// | 3 | Mem, Zmm |
350/// | 4 | Xmm, Xmm |
351/// | 5 | Ymm, Ymm |
352/// | 6 | Zmm, Zmm |
353/// +---+----------+
354/// ```
355pub trait VpcompresswMaskEmitter<A, B> {
356    fn vpcompressw_mask(&mut self, op0: A, op1: B);
357}
358
359impl<'a> VpcompresswMaskEmitter<Mem, Xmm> for Assembler<'a> {
360    fn vpcompressw_mask(&mut self, op0: Mem, op1: Xmm) {
361        self.emit(
362            VPCOMPRESSW128MR_MASK,
363            op0.as_operand(),
364            op1.as_operand(),
365            &NOREG,
366            &NOREG,
367        );
368    }
369}
370
371impl<'a> VpcompresswMaskEmitter<Mem, Ymm> for Assembler<'a> {
372    fn vpcompressw_mask(&mut self, op0: Mem, op1: Ymm) {
373        self.emit(
374            VPCOMPRESSW256MR_MASK,
375            op0.as_operand(),
376            op1.as_operand(),
377            &NOREG,
378            &NOREG,
379        );
380    }
381}
382
383impl<'a> VpcompresswMaskEmitter<Mem, Zmm> for Assembler<'a> {
384    fn vpcompressw_mask(&mut self, op0: Mem, op1: Zmm) {
385        self.emit(
386            VPCOMPRESSW512MR_MASK,
387            op0.as_operand(),
388            op1.as_operand(),
389            &NOREG,
390            &NOREG,
391        );
392    }
393}
394
395impl<'a> VpcompresswMaskEmitter<Xmm, Xmm> for Assembler<'a> {
396    fn vpcompressw_mask(&mut self, op0: Xmm, op1: Xmm) {
397        self.emit(
398            VPCOMPRESSW128RR_MASK,
399            op0.as_operand(),
400            op1.as_operand(),
401            &NOREG,
402            &NOREG,
403        );
404    }
405}
406
407impl<'a> VpcompresswMaskEmitter<Ymm, Ymm> for Assembler<'a> {
408    fn vpcompressw_mask(&mut self, op0: Ymm, op1: Ymm) {
409        self.emit(
410            VPCOMPRESSW256RR_MASK,
411            op0.as_operand(),
412            op1.as_operand(),
413            &NOREG,
414            &NOREG,
415        );
416    }
417}
418
419impl<'a> VpcompresswMaskEmitter<Zmm, Zmm> for Assembler<'a> {
420    fn vpcompressw_mask(&mut self, op0: Zmm, op1: Zmm) {
421        self.emit(
422            VPCOMPRESSW512RR_MASK,
423            op0.as_operand(),
424            op1.as_operand(),
425            &NOREG,
426            &NOREG,
427        );
428    }
429}
430
431/// `VPCOMPRESSW_MASKZ`.
432///
433/// Supported operand variants:
434///
435/// ```text
436/// +---+----------+
437/// | # | Operands |
438/// +---+----------+
439/// | 1 | Xmm, Xmm |
440/// | 2 | Ymm, Ymm |
441/// | 3 | Zmm, Zmm |
442/// +---+----------+
443/// ```
444pub trait VpcompresswMaskzEmitter<A, B> {
445    fn vpcompressw_maskz(&mut self, op0: A, op1: B);
446}
447
448impl<'a> VpcompresswMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
449    fn vpcompressw_maskz(&mut self, op0: Xmm, op1: Xmm) {
450        self.emit(
451            VPCOMPRESSW128RR_MASKZ,
452            op0.as_operand(),
453            op1.as_operand(),
454            &NOREG,
455            &NOREG,
456        );
457    }
458}
459
460impl<'a> VpcompresswMaskzEmitter<Ymm, Ymm> for Assembler<'a> {
461    fn vpcompressw_maskz(&mut self, op0: Ymm, op1: Ymm) {
462        self.emit(
463            VPCOMPRESSW256RR_MASKZ,
464            op0.as_operand(),
465            op1.as_operand(),
466            &NOREG,
467            &NOREG,
468        );
469    }
470}
471
472impl<'a> VpcompresswMaskzEmitter<Zmm, Zmm> for Assembler<'a> {
473    fn vpcompressw_maskz(&mut self, op0: Zmm, op1: Zmm) {
474        self.emit(
475            VPCOMPRESSW512RR_MASKZ,
476            op0.as_operand(),
477            op1.as_operand(),
478            &NOREG,
479            &NOREG,
480        );
481    }
482}
483
484/// `VPEXPANDB`.
485///
486/// Supported operand variants:
487///
488/// ```text
489/// +---+----------+
490/// | # | Operands |
491/// +---+----------+
492/// | 1 | Xmm, Mem |
493/// | 2 | Xmm, Xmm |
494/// | 3 | Ymm, Mem |
495/// | 4 | Ymm, Ymm |
496/// | 5 | Zmm, Mem |
497/// | 6 | Zmm, Zmm |
498/// +---+----------+
499/// ```
500pub trait VpexpandbEmitter<A, B> {
501    fn vpexpandb(&mut self, op0: A, op1: B);
502}
503
504impl<'a> VpexpandbEmitter<Xmm, Mem> for Assembler<'a> {
505    fn vpexpandb(&mut self, op0: Xmm, op1: Mem) {
506        self.emit(
507            VPEXPANDB128RM,
508            op0.as_operand(),
509            op1.as_operand(),
510            &NOREG,
511            &NOREG,
512        );
513    }
514}
515
516impl<'a> VpexpandbEmitter<Ymm, Mem> for Assembler<'a> {
517    fn vpexpandb(&mut self, op0: Ymm, op1: Mem) {
518        self.emit(
519            VPEXPANDB256RM,
520            op0.as_operand(),
521            op1.as_operand(),
522            &NOREG,
523            &NOREG,
524        );
525    }
526}
527
528impl<'a> VpexpandbEmitter<Zmm, Mem> for Assembler<'a> {
529    fn vpexpandb(&mut self, op0: Zmm, op1: Mem) {
530        self.emit(
531            VPEXPANDB512RM,
532            op0.as_operand(),
533            op1.as_operand(),
534            &NOREG,
535            &NOREG,
536        );
537    }
538}
539
540impl<'a> VpexpandbEmitter<Xmm, Xmm> for Assembler<'a> {
541    fn vpexpandb(&mut self, op0: Xmm, op1: Xmm) {
542        self.emit(
543            VPEXPANDB128RR,
544            op0.as_operand(),
545            op1.as_operand(),
546            &NOREG,
547            &NOREG,
548        );
549    }
550}
551
552impl<'a> VpexpandbEmitter<Ymm, Ymm> for Assembler<'a> {
553    fn vpexpandb(&mut self, op0: Ymm, op1: Ymm) {
554        self.emit(
555            VPEXPANDB256RR,
556            op0.as_operand(),
557            op1.as_operand(),
558            &NOREG,
559            &NOREG,
560        );
561    }
562}
563
564impl<'a> VpexpandbEmitter<Zmm, Zmm> for Assembler<'a> {
565    fn vpexpandb(&mut self, op0: Zmm, op1: Zmm) {
566        self.emit(
567            VPEXPANDB512RR,
568            op0.as_operand(),
569            op1.as_operand(),
570            &NOREG,
571            &NOREG,
572        );
573    }
574}
575
576/// `VPEXPANDB_MASK`.
577///
578/// Supported operand variants:
579///
580/// ```text
581/// +---+----------+
582/// | # | Operands |
583/// +---+----------+
584/// | 1 | Xmm, Mem |
585/// | 2 | Xmm, Xmm |
586/// | 3 | Ymm, Mem |
587/// | 4 | Ymm, Ymm |
588/// | 5 | Zmm, Mem |
589/// | 6 | Zmm, Zmm |
590/// +---+----------+
591/// ```
592pub trait VpexpandbMaskEmitter<A, B> {
593    fn vpexpandb_mask(&mut self, op0: A, op1: B);
594}
595
596impl<'a> VpexpandbMaskEmitter<Xmm, Mem> for Assembler<'a> {
597    fn vpexpandb_mask(&mut self, op0: Xmm, op1: Mem) {
598        self.emit(
599            VPEXPANDB128RM_MASK,
600            op0.as_operand(),
601            op1.as_operand(),
602            &NOREG,
603            &NOREG,
604        );
605    }
606}
607
608impl<'a> VpexpandbMaskEmitter<Ymm, Mem> for Assembler<'a> {
609    fn vpexpandb_mask(&mut self, op0: Ymm, op1: Mem) {
610        self.emit(
611            VPEXPANDB256RM_MASK,
612            op0.as_operand(),
613            op1.as_operand(),
614            &NOREG,
615            &NOREG,
616        );
617    }
618}
619
620impl<'a> VpexpandbMaskEmitter<Zmm, Mem> for Assembler<'a> {
621    fn vpexpandb_mask(&mut self, op0: Zmm, op1: Mem) {
622        self.emit(
623            VPEXPANDB512RM_MASK,
624            op0.as_operand(),
625            op1.as_operand(),
626            &NOREG,
627            &NOREG,
628        );
629    }
630}
631
632impl<'a> VpexpandbMaskEmitter<Xmm, Xmm> for Assembler<'a> {
633    fn vpexpandb_mask(&mut self, op0: Xmm, op1: Xmm) {
634        self.emit(
635            VPEXPANDB128RR_MASK,
636            op0.as_operand(),
637            op1.as_operand(),
638            &NOREG,
639            &NOREG,
640        );
641    }
642}
643
644impl<'a> VpexpandbMaskEmitter<Ymm, Ymm> for Assembler<'a> {
645    fn vpexpandb_mask(&mut self, op0: Ymm, op1: Ymm) {
646        self.emit(
647            VPEXPANDB256RR_MASK,
648            op0.as_operand(),
649            op1.as_operand(),
650            &NOREG,
651            &NOREG,
652        );
653    }
654}
655
656impl<'a> VpexpandbMaskEmitter<Zmm, Zmm> for Assembler<'a> {
657    fn vpexpandb_mask(&mut self, op0: Zmm, op1: Zmm) {
658        self.emit(
659            VPEXPANDB512RR_MASK,
660            op0.as_operand(),
661            op1.as_operand(),
662            &NOREG,
663            &NOREG,
664        );
665    }
666}
667
668/// `VPEXPANDB_MASKZ`.
669///
670/// Supported operand variants:
671///
672/// ```text
673/// +---+----------+
674/// | # | Operands |
675/// +---+----------+
676/// | 1 | Xmm, Mem |
677/// | 2 | Xmm, Xmm |
678/// | 3 | Ymm, Mem |
679/// | 4 | Ymm, Ymm |
680/// | 5 | Zmm, Mem |
681/// | 6 | Zmm, Zmm |
682/// +---+----------+
683/// ```
684pub trait VpexpandbMaskzEmitter<A, B> {
685    fn vpexpandb_maskz(&mut self, op0: A, op1: B);
686}
687
688impl<'a> VpexpandbMaskzEmitter<Xmm, Mem> for Assembler<'a> {
689    fn vpexpandb_maskz(&mut self, op0: Xmm, op1: Mem) {
690        self.emit(
691            VPEXPANDB128RM_MASKZ,
692            op0.as_operand(),
693            op1.as_operand(),
694            &NOREG,
695            &NOREG,
696        );
697    }
698}
699
700impl<'a> VpexpandbMaskzEmitter<Ymm, Mem> for Assembler<'a> {
701    fn vpexpandb_maskz(&mut self, op0: Ymm, op1: Mem) {
702        self.emit(
703            VPEXPANDB256RM_MASKZ,
704            op0.as_operand(),
705            op1.as_operand(),
706            &NOREG,
707            &NOREG,
708        );
709    }
710}
711
712impl<'a> VpexpandbMaskzEmitter<Zmm, Mem> for Assembler<'a> {
713    fn vpexpandb_maskz(&mut self, op0: Zmm, op1: Mem) {
714        self.emit(
715            VPEXPANDB512RM_MASKZ,
716            op0.as_operand(),
717            op1.as_operand(),
718            &NOREG,
719            &NOREG,
720        );
721    }
722}
723
724impl<'a> VpexpandbMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
725    fn vpexpandb_maskz(&mut self, op0: Xmm, op1: Xmm) {
726        self.emit(
727            VPEXPANDB128RR_MASKZ,
728            op0.as_operand(),
729            op1.as_operand(),
730            &NOREG,
731            &NOREG,
732        );
733    }
734}
735
736impl<'a> VpexpandbMaskzEmitter<Ymm, Ymm> for Assembler<'a> {
737    fn vpexpandb_maskz(&mut self, op0: Ymm, op1: Ymm) {
738        self.emit(
739            VPEXPANDB256RR_MASKZ,
740            op0.as_operand(),
741            op1.as_operand(),
742            &NOREG,
743            &NOREG,
744        );
745    }
746}
747
748impl<'a> VpexpandbMaskzEmitter<Zmm, Zmm> for Assembler<'a> {
749    fn vpexpandb_maskz(&mut self, op0: Zmm, op1: Zmm) {
750        self.emit(
751            VPEXPANDB512RR_MASKZ,
752            op0.as_operand(),
753            op1.as_operand(),
754            &NOREG,
755            &NOREG,
756        );
757    }
758}
759
760/// `VPEXPANDW`.
761///
762/// Supported operand variants:
763///
764/// ```text
765/// +---+----------+
766/// | # | Operands |
767/// +---+----------+
768/// | 1 | Xmm, Mem |
769/// | 2 | Xmm, Xmm |
770/// | 3 | Ymm, Mem |
771/// | 4 | Ymm, Ymm |
772/// | 5 | Zmm, Mem |
773/// | 6 | Zmm, Zmm |
774/// +---+----------+
775/// ```
776pub trait VpexpandwEmitter<A, B> {
777    fn vpexpandw(&mut self, op0: A, op1: B);
778}
779
780impl<'a> VpexpandwEmitter<Xmm, Mem> for Assembler<'a> {
781    fn vpexpandw(&mut self, op0: Xmm, op1: Mem) {
782        self.emit(
783            VPEXPANDW128RM,
784            op0.as_operand(),
785            op1.as_operand(),
786            &NOREG,
787            &NOREG,
788        );
789    }
790}
791
792impl<'a> VpexpandwEmitter<Ymm, Mem> for Assembler<'a> {
793    fn vpexpandw(&mut self, op0: Ymm, op1: Mem) {
794        self.emit(
795            VPEXPANDW256RM,
796            op0.as_operand(),
797            op1.as_operand(),
798            &NOREG,
799            &NOREG,
800        );
801    }
802}
803
804impl<'a> VpexpandwEmitter<Zmm, Mem> for Assembler<'a> {
805    fn vpexpandw(&mut self, op0: Zmm, op1: Mem) {
806        self.emit(
807            VPEXPANDW512RM,
808            op0.as_operand(),
809            op1.as_operand(),
810            &NOREG,
811            &NOREG,
812        );
813    }
814}
815
816impl<'a> VpexpandwEmitter<Xmm, Xmm> for Assembler<'a> {
817    fn vpexpandw(&mut self, op0: Xmm, op1: Xmm) {
818        self.emit(
819            VPEXPANDW128RR,
820            op0.as_operand(),
821            op1.as_operand(),
822            &NOREG,
823            &NOREG,
824        );
825    }
826}
827
828impl<'a> VpexpandwEmitter<Ymm, Ymm> for Assembler<'a> {
829    fn vpexpandw(&mut self, op0: Ymm, op1: Ymm) {
830        self.emit(
831            VPEXPANDW256RR,
832            op0.as_operand(),
833            op1.as_operand(),
834            &NOREG,
835            &NOREG,
836        );
837    }
838}
839
840impl<'a> VpexpandwEmitter<Zmm, Zmm> for Assembler<'a> {
841    fn vpexpandw(&mut self, op0: Zmm, op1: Zmm) {
842        self.emit(
843            VPEXPANDW512RR,
844            op0.as_operand(),
845            op1.as_operand(),
846            &NOREG,
847            &NOREG,
848        );
849    }
850}
851
852/// `VPEXPANDW_MASK`.
853///
854/// Supported operand variants:
855///
856/// ```text
857/// +---+----------+
858/// | # | Operands |
859/// +---+----------+
860/// | 1 | Xmm, Mem |
861/// | 2 | Xmm, Xmm |
862/// | 3 | Ymm, Mem |
863/// | 4 | Ymm, Ymm |
864/// | 5 | Zmm, Mem |
865/// | 6 | Zmm, Zmm |
866/// +---+----------+
867/// ```
868pub trait VpexpandwMaskEmitter<A, B> {
869    fn vpexpandw_mask(&mut self, op0: A, op1: B);
870}
871
872impl<'a> VpexpandwMaskEmitter<Xmm, Mem> for Assembler<'a> {
873    fn vpexpandw_mask(&mut self, op0: Xmm, op1: Mem) {
874        self.emit(
875            VPEXPANDW128RM_MASK,
876            op0.as_operand(),
877            op1.as_operand(),
878            &NOREG,
879            &NOREG,
880        );
881    }
882}
883
884impl<'a> VpexpandwMaskEmitter<Ymm, Mem> for Assembler<'a> {
885    fn vpexpandw_mask(&mut self, op0: Ymm, op1: Mem) {
886        self.emit(
887            VPEXPANDW256RM_MASK,
888            op0.as_operand(),
889            op1.as_operand(),
890            &NOREG,
891            &NOREG,
892        );
893    }
894}
895
896impl<'a> VpexpandwMaskEmitter<Zmm, Mem> for Assembler<'a> {
897    fn vpexpandw_mask(&mut self, op0: Zmm, op1: Mem) {
898        self.emit(
899            VPEXPANDW512RM_MASK,
900            op0.as_operand(),
901            op1.as_operand(),
902            &NOREG,
903            &NOREG,
904        );
905    }
906}
907
908impl<'a> VpexpandwMaskEmitter<Xmm, Xmm> for Assembler<'a> {
909    fn vpexpandw_mask(&mut self, op0: Xmm, op1: Xmm) {
910        self.emit(
911            VPEXPANDW128RR_MASK,
912            op0.as_operand(),
913            op1.as_operand(),
914            &NOREG,
915            &NOREG,
916        );
917    }
918}
919
920impl<'a> VpexpandwMaskEmitter<Ymm, Ymm> for Assembler<'a> {
921    fn vpexpandw_mask(&mut self, op0: Ymm, op1: Ymm) {
922        self.emit(
923            VPEXPANDW256RR_MASK,
924            op0.as_operand(),
925            op1.as_operand(),
926            &NOREG,
927            &NOREG,
928        );
929    }
930}
931
932impl<'a> VpexpandwMaskEmitter<Zmm, Zmm> for Assembler<'a> {
933    fn vpexpandw_mask(&mut self, op0: Zmm, op1: Zmm) {
934        self.emit(
935            VPEXPANDW512RR_MASK,
936            op0.as_operand(),
937            op1.as_operand(),
938            &NOREG,
939            &NOREG,
940        );
941    }
942}
943
944/// `VPEXPANDW_MASKZ`.
945///
946/// Supported operand variants:
947///
948/// ```text
949/// +---+----------+
950/// | # | Operands |
951/// +---+----------+
952/// | 1 | Xmm, Mem |
953/// | 2 | Xmm, Xmm |
954/// | 3 | Ymm, Mem |
955/// | 4 | Ymm, Ymm |
956/// | 5 | Zmm, Mem |
957/// | 6 | Zmm, Zmm |
958/// +---+----------+
959/// ```
960pub trait VpexpandwMaskzEmitter<A, B> {
961    fn vpexpandw_maskz(&mut self, op0: A, op1: B);
962}
963
964impl<'a> VpexpandwMaskzEmitter<Xmm, Mem> for Assembler<'a> {
965    fn vpexpandw_maskz(&mut self, op0: Xmm, op1: Mem) {
966        self.emit(
967            VPEXPANDW128RM_MASKZ,
968            op0.as_operand(),
969            op1.as_operand(),
970            &NOREG,
971            &NOREG,
972        );
973    }
974}
975
976impl<'a> VpexpandwMaskzEmitter<Ymm, Mem> for Assembler<'a> {
977    fn vpexpandw_maskz(&mut self, op0: Ymm, op1: Mem) {
978        self.emit(
979            VPEXPANDW256RM_MASKZ,
980            op0.as_operand(),
981            op1.as_operand(),
982            &NOREG,
983            &NOREG,
984        );
985    }
986}
987
988impl<'a> VpexpandwMaskzEmitter<Zmm, Mem> for Assembler<'a> {
989    fn vpexpandw_maskz(&mut self, op0: Zmm, op1: Mem) {
990        self.emit(
991            VPEXPANDW512RM_MASKZ,
992            op0.as_operand(),
993            op1.as_operand(),
994            &NOREG,
995            &NOREG,
996        );
997    }
998}
999
1000impl<'a> VpexpandwMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
1001    fn vpexpandw_maskz(&mut self, op0: Xmm, op1: Xmm) {
1002        self.emit(
1003            VPEXPANDW128RR_MASKZ,
1004            op0.as_operand(),
1005            op1.as_operand(),
1006            &NOREG,
1007            &NOREG,
1008        );
1009    }
1010}
1011
1012impl<'a> VpexpandwMaskzEmitter<Ymm, Ymm> for Assembler<'a> {
1013    fn vpexpandw_maskz(&mut self, op0: Ymm, op1: Ymm) {
1014        self.emit(
1015            VPEXPANDW256RR_MASKZ,
1016            op0.as_operand(),
1017            op1.as_operand(),
1018            &NOREG,
1019            &NOREG,
1020        );
1021    }
1022}
1023
1024impl<'a> VpexpandwMaskzEmitter<Zmm, Zmm> for Assembler<'a> {
1025    fn vpexpandw_maskz(&mut self, op0: Zmm, op1: Zmm) {
1026        self.emit(
1027            VPEXPANDW512RR_MASKZ,
1028            op0.as_operand(),
1029            op1.as_operand(),
1030            &NOREG,
1031            &NOREG,
1032        );
1033    }
1034}
1035
1036/// `VPSHLDD`.
1037///
1038/// Supported operand variants:
1039///
1040/// ```text
1041/// +---+--------------------+
1042/// | # | Operands           |
1043/// +---+--------------------+
1044/// | 1 | Xmm, Xmm, Mem, Imm |
1045/// | 2 | Xmm, Xmm, Xmm, Imm |
1046/// | 3 | Ymm, Ymm, Mem, Imm |
1047/// | 4 | Ymm, Ymm, Ymm, Imm |
1048/// | 5 | Zmm, Zmm, Mem, Imm |
1049/// | 6 | Zmm, Zmm, Zmm, Imm |
1050/// +---+--------------------+
1051/// ```
1052pub trait VpshlddEmitter<A, B, C, D> {
1053    fn vpshldd(&mut self, op0: A, op1: B, op2: C, op3: D);
1054}
1055
1056impl<'a> VpshlddEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
1057    fn vpshldd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
1058        self.emit(
1059            VPSHLDD128RRRI,
1060            op0.as_operand(),
1061            op1.as_operand(),
1062            op2.as_operand(),
1063            op3.as_operand(),
1064        );
1065    }
1066}
1067
1068impl<'a> VpshlddEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
1069    fn vpshldd(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
1070        self.emit(
1071            VPSHLDD128RRMI,
1072            op0.as_operand(),
1073            op1.as_operand(),
1074            op2.as_operand(),
1075            op3.as_operand(),
1076        );
1077    }
1078}
1079
1080impl<'a> VpshlddEmitter<Ymm, Ymm, Ymm, Imm> for Assembler<'a> {
1081    fn vpshldd(&mut self, op0: Ymm, op1: Ymm, op2: Ymm, op3: Imm) {
1082        self.emit(
1083            VPSHLDD256RRRI,
1084            op0.as_operand(),
1085            op1.as_operand(),
1086            op2.as_operand(),
1087            op3.as_operand(),
1088        );
1089    }
1090}
1091
1092impl<'a> VpshlddEmitter<Ymm, Ymm, Mem, Imm> for Assembler<'a> {
1093    fn vpshldd(&mut self, op0: Ymm, op1: Ymm, op2: Mem, op3: Imm) {
1094        self.emit(
1095            VPSHLDD256RRMI,
1096            op0.as_operand(),
1097            op1.as_operand(),
1098            op2.as_operand(),
1099            op3.as_operand(),
1100        );
1101    }
1102}
1103
1104impl<'a> VpshlddEmitter<Zmm, Zmm, Zmm, Imm> for Assembler<'a> {
1105    fn vpshldd(&mut self, op0: Zmm, op1: Zmm, op2: Zmm, op3: Imm) {
1106        self.emit(
1107            VPSHLDD512RRRI,
1108            op0.as_operand(),
1109            op1.as_operand(),
1110            op2.as_operand(),
1111            op3.as_operand(),
1112        );
1113    }
1114}
1115
1116impl<'a> VpshlddEmitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
1117    fn vpshldd(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
1118        self.emit(
1119            VPSHLDD512RRMI,
1120            op0.as_operand(),
1121            op1.as_operand(),
1122            op2.as_operand(),
1123            op3.as_operand(),
1124        );
1125    }
1126}
1127
1128/// `VPSHLDD_MASK`.
1129///
1130/// Supported operand variants:
1131///
1132/// ```text
1133/// +---+--------------------+
1134/// | # | Operands           |
1135/// +---+--------------------+
1136/// | 1 | Xmm, Xmm, Mem, Imm |
1137/// | 2 | Xmm, Xmm, Xmm, Imm |
1138/// | 3 | Ymm, Ymm, Mem, Imm |
1139/// | 4 | Ymm, Ymm, Ymm, Imm |
1140/// | 5 | Zmm, Zmm, Mem, Imm |
1141/// | 6 | Zmm, Zmm, Zmm, Imm |
1142/// +---+--------------------+
1143/// ```
1144pub trait VpshlddMaskEmitter<A, B, C, D> {
1145    fn vpshldd_mask(&mut self, op0: A, op1: B, op2: C, op3: D);
1146}
1147
1148impl<'a> VpshlddMaskEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
1149    fn vpshldd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
1150        self.emit(
1151            VPSHLDD128RRRI_MASK,
1152            op0.as_operand(),
1153            op1.as_operand(),
1154            op2.as_operand(),
1155            op3.as_operand(),
1156        );
1157    }
1158}
1159
1160impl<'a> VpshlddMaskEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
1161    fn vpshldd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
1162        self.emit(
1163            VPSHLDD128RRMI_MASK,
1164            op0.as_operand(),
1165            op1.as_operand(),
1166            op2.as_operand(),
1167            op3.as_operand(),
1168        );
1169    }
1170}
1171
1172impl<'a> VpshlddMaskEmitter<Ymm, Ymm, Ymm, Imm> for Assembler<'a> {
1173    fn vpshldd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm, op3: Imm) {
1174        self.emit(
1175            VPSHLDD256RRRI_MASK,
1176            op0.as_operand(),
1177            op1.as_operand(),
1178            op2.as_operand(),
1179            op3.as_operand(),
1180        );
1181    }
1182}
1183
1184impl<'a> VpshlddMaskEmitter<Ymm, Ymm, Mem, Imm> for Assembler<'a> {
1185    fn vpshldd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem, op3: Imm) {
1186        self.emit(
1187            VPSHLDD256RRMI_MASK,
1188            op0.as_operand(),
1189            op1.as_operand(),
1190            op2.as_operand(),
1191            op3.as_operand(),
1192        );
1193    }
1194}
1195
1196impl<'a> VpshlddMaskEmitter<Zmm, Zmm, Zmm, Imm> for Assembler<'a> {
1197    fn vpshldd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm, op3: Imm) {
1198        self.emit(
1199            VPSHLDD512RRRI_MASK,
1200            op0.as_operand(),
1201            op1.as_operand(),
1202            op2.as_operand(),
1203            op3.as_operand(),
1204        );
1205    }
1206}
1207
1208impl<'a> VpshlddMaskEmitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
1209    fn vpshldd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
1210        self.emit(
1211            VPSHLDD512RRMI_MASK,
1212            op0.as_operand(),
1213            op1.as_operand(),
1214            op2.as_operand(),
1215            op3.as_operand(),
1216        );
1217    }
1218}
1219
1220/// `VPSHLDD_MASKZ`.
1221///
1222/// Supported operand variants:
1223///
1224/// ```text
1225/// +---+--------------------+
1226/// | # | Operands           |
1227/// +---+--------------------+
1228/// | 1 | Xmm, Xmm, Mem, Imm |
1229/// | 2 | Xmm, Xmm, Xmm, Imm |
1230/// | 3 | Ymm, Ymm, Mem, Imm |
1231/// | 4 | Ymm, Ymm, Ymm, Imm |
1232/// | 5 | Zmm, Zmm, Mem, Imm |
1233/// | 6 | Zmm, Zmm, Zmm, Imm |
1234/// +---+--------------------+
1235/// ```
1236pub trait VpshlddMaskzEmitter<A, B, C, D> {
1237    fn vpshldd_maskz(&mut self, op0: A, op1: B, op2: C, op3: D);
1238}
1239
1240impl<'a> VpshlddMaskzEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
1241    fn vpshldd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
1242        self.emit(
1243            VPSHLDD128RRRI_MASKZ,
1244            op0.as_operand(),
1245            op1.as_operand(),
1246            op2.as_operand(),
1247            op3.as_operand(),
1248        );
1249    }
1250}
1251
1252impl<'a> VpshlddMaskzEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
1253    fn vpshldd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
1254        self.emit(
1255            VPSHLDD128RRMI_MASKZ,
1256            op0.as_operand(),
1257            op1.as_operand(),
1258            op2.as_operand(),
1259            op3.as_operand(),
1260        );
1261    }
1262}
1263
1264impl<'a> VpshlddMaskzEmitter<Ymm, Ymm, Ymm, Imm> for Assembler<'a> {
1265    fn vpshldd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm, op3: Imm) {
1266        self.emit(
1267            VPSHLDD256RRRI_MASKZ,
1268            op0.as_operand(),
1269            op1.as_operand(),
1270            op2.as_operand(),
1271            op3.as_operand(),
1272        );
1273    }
1274}
1275
1276impl<'a> VpshlddMaskzEmitter<Ymm, Ymm, Mem, Imm> for Assembler<'a> {
1277    fn vpshldd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem, op3: Imm) {
1278        self.emit(
1279            VPSHLDD256RRMI_MASKZ,
1280            op0.as_operand(),
1281            op1.as_operand(),
1282            op2.as_operand(),
1283            op3.as_operand(),
1284        );
1285    }
1286}
1287
1288impl<'a> VpshlddMaskzEmitter<Zmm, Zmm, Zmm, Imm> for Assembler<'a> {
1289    fn vpshldd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm, op3: Imm) {
1290        self.emit(
1291            VPSHLDD512RRRI_MASKZ,
1292            op0.as_operand(),
1293            op1.as_operand(),
1294            op2.as_operand(),
1295            op3.as_operand(),
1296        );
1297    }
1298}
1299
1300impl<'a> VpshlddMaskzEmitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
1301    fn vpshldd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
1302        self.emit(
1303            VPSHLDD512RRMI_MASKZ,
1304            op0.as_operand(),
1305            op1.as_operand(),
1306            op2.as_operand(),
1307            op3.as_operand(),
1308        );
1309    }
1310}
1311
1312/// `VPSHLDQ`.
1313///
1314/// Supported operand variants:
1315///
1316/// ```text
1317/// +---+--------------------+
1318/// | # | Operands           |
1319/// +---+--------------------+
1320/// | 1 | Xmm, Xmm, Mem, Imm |
1321/// | 2 | Xmm, Xmm, Xmm, Imm |
1322/// | 3 | Ymm, Ymm, Mem, Imm |
1323/// | 4 | Ymm, Ymm, Ymm, Imm |
1324/// | 5 | Zmm, Zmm, Mem, Imm |
1325/// | 6 | Zmm, Zmm, Zmm, Imm |
1326/// +---+--------------------+
1327/// ```
1328pub trait VpshldqEmitter<A, B, C, D> {
1329    fn vpshldq(&mut self, op0: A, op1: B, op2: C, op3: D);
1330}
1331
1332impl<'a> VpshldqEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
1333    fn vpshldq(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
1334        self.emit(
1335            VPSHLDQ128RRRI,
1336            op0.as_operand(),
1337            op1.as_operand(),
1338            op2.as_operand(),
1339            op3.as_operand(),
1340        );
1341    }
1342}
1343
1344impl<'a> VpshldqEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
1345    fn vpshldq(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
1346        self.emit(
1347            VPSHLDQ128RRMI,
1348            op0.as_operand(),
1349            op1.as_operand(),
1350            op2.as_operand(),
1351            op3.as_operand(),
1352        );
1353    }
1354}
1355
1356impl<'a> VpshldqEmitter<Ymm, Ymm, Ymm, Imm> for Assembler<'a> {
1357    fn vpshldq(&mut self, op0: Ymm, op1: Ymm, op2: Ymm, op3: Imm) {
1358        self.emit(
1359            VPSHLDQ256RRRI,
1360            op0.as_operand(),
1361            op1.as_operand(),
1362            op2.as_operand(),
1363            op3.as_operand(),
1364        );
1365    }
1366}
1367
1368impl<'a> VpshldqEmitter<Ymm, Ymm, Mem, Imm> for Assembler<'a> {
1369    fn vpshldq(&mut self, op0: Ymm, op1: Ymm, op2: Mem, op3: Imm) {
1370        self.emit(
1371            VPSHLDQ256RRMI,
1372            op0.as_operand(),
1373            op1.as_operand(),
1374            op2.as_operand(),
1375            op3.as_operand(),
1376        );
1377    }
1378}
1379
1380impl<'a> VpshldqEmitter<Zmm, Zmm, Zmm, Imm> for Assembler<'a> {
1381    fn vpshldq(&mut self, op0: Zmm, op1: Zmm, op2: Zmm, op3: Imm) {
1382        self.emit(
1383            VPSHLDQ512RRRI,
1384            op0.as_operand(),
1385            op1.as_operand(),
1386            op2.as_operand(),
1387            op3.as_operand(),
1388        );
1389    }
1390}
1391
1392impl<'a> VpshldqEmitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
1393    fn vpshldq(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
1394        self.emit(
1395            VPSHLDQ512RRMI,
1396            op0.as_operand(),
1397            op1.as_operand(),
1398            op2.as_operand(),
1399            op3.as_operand(),
1400        );
1401    }
1402}
1403
1404/// `VPSHLDQ_MASK`.
1405///
1406/// Supported operand variants:
1407///
1408/// ```text
1409/// +---+--------------------+
1410/// | # | Operands           |
1411/// +---+--------------------+
1412/// | 1 | Xmm, Xmm, Mem, Imm |
1413/// | 2 | Xmm, Xmm, Xmm, Imm |
1414/// | 3 | Ymm, Ymm, Mem, Imm |
1415/// | 4 | Ymm, Ymm, Ymm, Imm |
1416/// | 5 | Zmm, Zmm, Mem, Imm |
1417/// | 6 | Zmm, Zmm, Zmm, Imm |
1418/// +---+--------------------+
1419/// ```
1420pub trait VpshldqMaskEmitter<A, B, C, D> {
1421    fn vpshldq_mask(&mut self, op0: A, op1: B, op2: C, op3: D);
1422}
1423
1424impl<'a> VpshldqMaskEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
1425    fn vpshldq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
1426        self.emit(
1427            VPSHLDQ128RRRI_MASK,
1428            op0.as_operand(),
1429            op1.as_operand(),
1430            op2.as_operand(),
1431            op3.as_operand(),
1432        );
1433    }
1434}
1435
1436impl<'a> VpshldqMaskEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
1437    fn vpshldq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
1438        self.emit(
1439            VPSHLDQ128RRMI_MASK,
1440            op0.as_operand(),
1441            op1.as_operand(),
1442            op2.as_operand(),
1443            op3.as_operand(),
1444        );
1445    }
1446}
1447
1448impl<'a> VpshldqMaskEmitter<Ymm, Ymm, Ymm, Imm> for Assembler<'a> {
1449    fn vpshldq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm, op3: Imm) {
1450        self.emit(
1451            VPSHLDQ256RRRI_MASK,
1452            op0.as_operand(),
1453            op1.as_operand(),
1454            op2.as_operand(),
1455            op3.as_operand(),
1456        );
1457    }
1458}
1459
1460impl<'a> VpshldqMaskEmitter<Ymm, Ymm, Mem, Imm> for Assembler<'a> {
1461    fn vpshldq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem, op3: Imm) {
1462        self.emit(
1463            VPSHLDQ256RRMI_MASK,
1464            op0.as_operand(),
1465            op1.as_operand(),
1466            op2.as_operand(),
1467            op3.as_operand(),
1468        );
1469    }
1470}
1471
1472impl<'a> VpshldqMaskEmitter<Zmm, Zmm, Zmm, Imm> for Assembler<'a> {
1473    fn vpshldq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm, op3: Imm) {
1474        self.emit(
1475            VPSHLDQ512RRRI_MASK,
1476            op0.as_operand(),
1477            op1.as_operand(),
1478            op2.as_operand(),
1479            op3.as_operand(),
1480        );
1481    }
1482}
1483
1484impl<'a> VpshldqMaskEmitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
1485    fn vpshldq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
1486        self.emit(
1487            VPSHLDQ512RRMI_MASK,
1488            op0.as_operand(),
1489            op1.as_operand(),
1490            op2.as_operand(),
1491            op3.as_operand(),
1492        );
1493    }
1494}
1495
1496/// `VPSHLDQ_MASKZ`.
1497///
1498/// Supported operand variants:
1499///
1500/// ```text
1501/// +---+--------------------+
1502/// | # | Operands           |
1503/// +---+--------------------+
1504/// | 1 | Xmm, Xmm, Mem, Imm |
1505/// | 2 | Xmm, Xmm, Xmm, Imm |
1506/// | 3 | Ymm, Ymm, Mem, Imm |
1507/// | 4 | Ymm, Ymm, Ymm, Imm |
1508/// | 5 | Zmm, Zmm, Mem, Imm |
1509/// | 6 | Zmm, Zmm, Zmm, Imm |
1510/// +---+--------------------+
1511/// ```
1512pub trait VpshldqMaskzEmitter<A, B, C, D> {
1513    fn vpshldq_maskz(&mut self, op0: A, op1: B, op2: C, op3: D);
1514}
1515
1516impl<'a> VpshldqMaskzEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
1517    fn vpshldq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
1518        self.emit(
1519            VPSHLDQ128RRRI_MASKZ,
1520            op0.as_operand(),
1521            op1.as_operand(),
1522            op2.as_operand(),
1523            op3.as_operand(),
1524        );
1525    }
1526}
1527
1528impl<'a> VpshldqMaskzEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
1529    fn vpshldq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
1530        self.emit(
1531            VPSHLDQ128RRMI_MASKZ,
1532            op0.as_operand(),
1533            op1.as_operand(),
1534            op2.as_operand(),
1535            op3.as_operand(),
1536        );
1537    }
1538}
1539
1540impl<'a> VpshldqMaskzEmitter<Ymm, Ymm, Ymm, Imm> for Assembler<'a> {
1541    fn vpshldq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm, op3: Imm) {
1542        self.emit(
1543            VPSHLDQ256RRRI_MASKZ,
1544            op0.as_operand(),
1545            op1.as_operand(),
1546            op2.as_operand(),
1547            op3.as_operand(),
1548        );
1549    }
1550}
1551
1552impl<'a> VpshldqMaskzEmitter<Ymm, Ymm, Mem, Imm> for Assembler<'a> {
1553    fn vpshldq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem, op3: Imm) {
1554        self.emit(
1555            VPSHLDQ256RRMI_MASKZ,
1556            op0.as_operand(),
1557            op1.as_operand(),
1558            op2.as_operand(),
1559            op3.as_operand(),
1560        );
1561    }
1562}
1563
1564impl<'a> VpshldqMaskzEmitter<Zmm, Zmm, Zmm, Imm> for Assembler<'a> {
1565    fn vpshldq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm, op3: Imm) {
1566        self.emit(
1567            VPSHLDQ512RRRI_MASKZ,
1568            op0.as_operand(),
1569            op1.as_operand(),
1570            op2.as_operand(),
1571            op3.as_operand(),
1572        );
1573    }
1574}
1575
1576impl<'a> VpshldqMaskzEmitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
1577    fn vpshldq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
1578        self.emit(
1579            VPSHLDQ512RRMI_MASKZ,
1580            op0.as_operand(),
1581            op1.as_operand(),
1582            op2.as_operand(),
1583            op3.as_operand(),
1584        );
1585    }
1586}
1587
1588/// `VPSHLDVD`.
1589///
1590/// Supported operand variants:
1591///
1592/// ```text
1593/// +---+---------------+
1594/// | # | Operands      |
1595/// +---+---------------+
1596/// | 1 | Xmm, Xmm, Mem |
1597/// | 2 | Xmm, Xmm, Xmm |
1598/// | 3 | Ymm, Ymm, Mem |
1599/// | 4 | Ymm, Ymm, Ymm |
1600/// | 5 | Zmm, Zmm, Mem |
1601/// | 6 | Zmm, Zmm, Zmm |
1602/// +---+---------------+
1603/// ```
1604pub trait VpshldvdEmitter<A, B, C> {
1605    fn vpshldvd(&mut self, op0: A, op1: B, op2: C);
1606}
1607
1608impl<'a> VpshldvdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
1609    fn vpshldvd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
1610        self.emit(
1611            VPSHLDVD128RRR,
1612            op0.as_operand(),
1613            op1.as_operand(),
1614            op2.as_operand(),
1615            &NOREG,
1616        );
1617    }
1618}
1619
1620impl<'a> VpshldvdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
1621    fn vpshldvd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
1622        self.emit(
1623            VPSHLDVD128RRM,
1624            op0.as_operand(),
1625            op1.as_operand(),
1626            op2.as_operand(),
1627            &NOREG,
1628        );
1629    }
1630}
1631
1632impl<'a> VpshldvdEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
1633    fn vpshldvd(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
1634        self.emit(
1635            VPSHLDVD256RRR,
1636            op0.as_operand(),
1637            op1.as_operand(),
1638            op2.as_operand(),
1639            &NOREG,
1640        );
1641    }
1642}
1643
1644impl<'a> VpshldvdEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
1645    fn vpshldvd(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
1646        self.emit(
1647            VPSHLDVD256RRM,
1648            op0.as_operand(),
1649            op1.as_operand(),
1650            op2.as_operand(),
1651            &NOREG,
1652        );
1653    }
1654}
1655
1656impl<'a> VpshldvdEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
1657    fn vpshldvd(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
1658        self.emit(
1659            VPSHLDVD512RRR,
1660            op0.as_operand(),
1661            op1.as_operand(),
1662            op2.as_operand(),
1663            &NOREG,
1664        );
1665    }
1666}
1667
1668impl<'a> VpshldvdEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
1669    fn vpshldvd(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
1670        self.emit(
1671            VPSHLDVD512RRM,
1672            op0.as_operand(),
1673            op1.as_operand(),
1674            op2.as_operand(),
1675            &NOREG,
1676        );
1677    }
1678}
1679
1680/// `VPSHLDVD_MASK`.
1681///
1682/// Supported operand variants:
1683///
1684/// ```text
1685/// +---+---------------+
1686/// | # | Operands      |
1687/// +---+---------------+
1688/// | 1 | Xmm, Xmm, Mem |
1689/// | 2 | Xmm, Xmm, Xmm |
1690/// | 3 | Ymm, Ymm, Mem |
1691/// | 4 | Ymm, Ymm, Ymm |
1692/// | 5 | Zmm, Zmm, Mem |
1693/// | 6 | Zmm, Zmm, Zmm |
1694/// +---+---------------+
1695/// ```
1696pub trait VpshldvdMaskEmitter<A, B, C> {
1697    fn vpshldvd_mask(&mut self, op0: A, op1: B, op2: C);
1698}
1699
1700impl<'a> VpshldvdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
1701    fn vpshldvd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
1702        self.emit(
1703            VPSHLDVD128RRR_MASK,
1704            op0.as_operand(),
1705            op1.as_operand(),
1706            op2.as_operand(),
1707            &NOREG,
1708        );
1709    }
1710}
1711
1712impl<'a> VpshldvdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
1713    fn vpshldvd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
1714        self.emit(
1715            VPSHLDVD128RRM_MASK,
1716            op0.as_operand(),
1717            op1.as_operand(),
1718            op2.as_operand(),
1719            &NOREG,
1720        );
1721    }
1722}
1723
1724impl<'a> VpshldvdMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
1725    fn vpshldvd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
1726        self.emit(
1727            VPSHLDVD256RRR_MASK,
1728            op0.as_operand(),
1729            op1.as_operand(),
1730            op2.as_operand(),
1731            &NOREG,
1732        );
1733    }
1734}
1735
1736impl<'a> VpshldvdMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
1737    fn vpshldvd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
1738        self.emit(
1739            VPSHLDVD256RRM_MASK,
1740            op0.as_operand(),
1741            op1.as_operand(),
1742            op2.as_operand(),
1743            &NOREG,
1744        );
1745    }
1746}
1747
1748impl<'a> VpshldvdMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
1749    fn vpshldvd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
1750        self.emit(
1751            VPSHLDVD512RRR_MASK,
1752            op0.as_operand(),
1753            op1.as_operand(),
1754            op2.as_operand(),
1755            &NOREG,
1756        );
1757    }
1758}
1759
1760impl<'a> VpshldvdMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
1761    fn vpshldvd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
1762        self.emit(
1763            VPSHLDVD512RRM_MASK,
1764            op0.as_operand(),
1765            op1.as_operand(),
1766            op2.as_operand(),
1767            &NOREG,
1768        );
1769    }
1770}
1771
1772/// `VPSHLDVD_MASKZ`.
1773///
1774/// Supported operand variants:
1775///
1776/// ```text
1777/// +---+---------------+
1778/// | # | Operands      |
1779/// +---+---------------+
1780/// | 1 | Xmm, Xmm, Mem |
1781/// | 2 | Xmm, Xmm, Xmm |
1782/// | 3 | Ymm, Ymm, Mem |
1783/// | 4 | Ymm, Ymm, Ymm |
1784/// | 5 | Zmm, Zmm, Mem |
1785/// | 6 | Zmm, Zmm, Zmm |
1786/// +---+---------------+
1787/// ```
1788pub trait VpshldvdMaskzEmitter<A, B, C> {
1789    fn vpshldvd_maskz(&mut self, op0: A, op1: B, op2: C);
1790}
1791
1792impl<'a> VpshldvdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
1793    fn vpshldvd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
1794        self.emit(
1795            VPSHLDVD128RRR_MASKZ,
1796            op0.as_operand(),
1797            op1.as_operand(),
1798            op2.as_operand(),
1799            &NOREG,
1800        );
1801    }
1802}
1803
1804impl<'a> VpshldvdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
1805    fn vpshldvd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
1806        self.emit(
1807            VPSHLDVD128RRM_MASKZ,
1808            op0.as_operand(),
1809            op1.as_operand(),
1810            op2.as_operand(),
1811            &NOREG,
1812        );
1813    }
1814}
1815
1816impl<'a> VpshldvdMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
1817    fn vpshldvd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
1818        self.emit(
1819            VPSHLDVD256RRR_MASKZ,
1820            op0.as_operand(),
1821            op1.as_operand(),
1822            op2.as_operand(),
1823            &NOREG,
1824        );
1825    }
1826}
1827
1828impl<'a> VpshldvdMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
1829    fn vpshldvd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
1830        self.emit(
1831            VPSHLDVD256RRM_MASKZ,
1832            op0.as_operand(),
1833            op1.as_operand(),
1834            op2.as_operand(),
1835            &NOREG,
1836        );
1837    }
1838}
1839
1840impl<'a> VpshldvdMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
1841    fn vpshldvd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
1842        self.emit(
1843            VPSHLDVD512RRR_MASKZ,
1844            op0.as_operand(),
1845            op1.as_operand(),
1846            op2.as_operand(),
1847            &NOREG,
1848        );
1849    }
1850}
1851
1852impl<'a> VpshldvdMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
1853    fn vpshldvd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
1854        self.emit(
1855            VPSHLDVD512RRM_MASKZ,
1856            op0.as_operand(),
1857            op1.as_operand(),
1858            op2.as_operand(),
1859            &NOREG,
1860        );
1861    }
1862}
1863
1864/// `VPSHLDVQ`.
1865///
1866/// Supported operand variants:
1867///
1868/// ```text
1869/// +---+---------------+
1870/// | # | Operands      |
1871/// +---+---------------+
1872/// | 1 | Xmm, Xmm, Mem |
1873/// | 2 | Xmm, Xmm, Xmm |
1874/// | 3 | Ymm, Ymm, Mem |
1875/// | 4 | Ymm, Ymm, Ymm |
1876/// | 5 | Zmm, Zmm, Mem |
1877/// | 6 | Zmm, Zmm, Zmm |
1878/// +---+---------------+
1879/// ```
1880pub trait VpshldvqEmitter<A, B, C> {
1881    fn vpshldvq(&mut self, op0: A, op1: B, op2: C);
1882}
1883
1884impl<'a> VpshldvqEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
1885    fn vpshldvq(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
1886        self.emit(
1887            VPSHLDVQ128RRR,
1888            op0.as_operand(),
1889            op1.as_operand(),
1890            op2.as_operand(),
1891            &NOREG,
1892        );
1893    }
1894}
1895
1896impl<'a> VpshldvqEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
1897    fn vpshldvq(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
1898        self.emit(
1899            VPSHLDVQ128RRM,
1900            op0.as_operand(),
1901            op1.as_operand(),
1902            op2.as_operand(),
1903            &NOREG,
1904        );
1905    }
1906}
1907
1908impl<'a> VpshldvqEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
1909    fn vpshldvq(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
1910        self.emit(
1911            VPSHLDVQ256RRR,
1912            op0.as_operand(),
1913            op1.as_operand(),
1914            op2.as_operand(),
1915            &NOREG,
1916        );
1917    }
1918}
1919
1920impl<'a> VpshldvqEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
1921    fn vpshldvq(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
1922        self.emit(
1923            VPSHLDVQ256RRM,
1924            op0.as_operand(),
1925            op1.as_operand(),
1926            op2.as_operand(),
1927            &NOREG,
1928        );
1929    }
1930}
1931
1932impl<'a> VpshldvqEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
1933    fn vpshldvq(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
1934        self.emit(
1935            VPSHLDVQ512RRR,
1936            op0.as_operand(),
1937            op1.as_operand(),
1938            op2.as_operand(),
1939            &NOREG,
1940        );
1941    }
1942}
1943
1944impl<'a> VpshldvqEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
1945    fn vpshldvq(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
1946        self.emit(
1947            VPSHLDVQ512RRM,
1948            op0.as_operand(),
1949            op1.as_operand(),
1950            op2.as_operand(),
1951            &NOREG,
1952        );
1953    }
1954}
1955
1956/// `VPSHLDVQ_MASK`.
1957///
1958/// Supported operand variants:
1959///
1960/// ```text
1961/// +---+---------------+
1962/// | # | Operands      |
1963/// +---+---------------+
1964/// | 1 | Xmm, Xmm, Mem |
1965/// | 2 | Xmm, Xmm, Xmm |
1966/// | 3 | Ymm, Ymm, Mem |
1967/// | 4 | Ymm, Ymm, Ymm |
1968/// | 5 | Zmm, Zmm, Mem |
1969/// | 6 | Zmm, Zmm, Zmm |
1970/// +---+---------------+
1971/// ```
1972pub trait VpshldvqMaskEmitter<A, B, C> {
1973    fn vpshldvq_mask(&mut self, op0: A, op1: B, op2: C);
1974}
1975
1976impl<'a> VpshldvqMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
1977    fn vpshldvq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
1978        self.emit(
1979            VPSHLDVQ128RRR_MASK,
1980            op0.as_operand(),
1981            op1.as_operand(),
1982            op2.as_operand(),
1983            &NOREG,
1984        );
1985    }
1986}
1987
1988impl<'a> VpshldvqMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
1989    fn vpshldvq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
1990        self.emit(
1991            VPSHLDVQ128RRM_MASK,
1992            op0.as_operand(),
1993            op1.as_operand(),
1994            op2.as_operand(),
1995            &NOREG,
1996        );
1997    }
1998}
1999
2000impl<'a> VpshldvqMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
2001    fn vpshldvq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
2002        self.emit(
2003            VPSHLDVQ256RRR_MASK,
2004            op0.as_operand(),
2005            op1.as_operand(),
2006            op2.as_operand(),
2007            &NOREG,
2008        );
2009    }
2010}
2011
2012impl<'a> VpshldvqMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
2013    fn vpshldvq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
2014        self.emit(
2015            VPSHLDVQ256RRM_MASK,
2016            op0.as_operand(),
2017            op1.as_operand(),
2018            op2.as_operand(),
2019            &NOREG,
2020        );
2021    }
2022}
2023
2024impl<'a> VpshldvqMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
2025    fn vpshldvq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
2026        self.emit(
2027            VPSHLDVQ512RRR_MASK,
2028            op0.as_operand(),
2029            op1.as_operand(),
2030            op2.as_operand(),
2031            &NOREG,
2032        );
2033    }
2034}
2035
2036impl<'a> VpshldvqMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
2037    fn vpshldvq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
2038        self.emit(
2039            VPSHLDVQ512RRM_MASK,
2040            op0.as_operand(),
2041            op1.as_operand(),
2042            op2.as_operand(),
2043            &NOREG,
2044        );
2045    }
2046}
2047
2048/// `VPSHLDVQ_MASKZ`.
2049///
2050/// Supported operand variants:
2051///
2052/// ```text
2053/// +---+---------------+
2054/// | # | Operands      |
2055/// +---+---------------+
2056/// | 1 | Xmm, Xmm, Mem |
2057/// | 2 | Xmm, Xmm, Xmm |
2058/// | 3 | Ymm, Ymm, Mem |
2059/// | 4 | Ymm, Ymm, Ymm |
2060/// | 5 | Zmm, Zmm, Mem |
2061/// | 6 | Zmm, Zmm, Zmm |
2062/// +---+---------------+
2063/// ```
2064pub trait VpshldvqMaskzEmitter<A, B, C> {
2065    fn vpshldvq_maskz(&mut self, op0: A, op1: B, op2: C);
2066}
2067
2068impl<'a> VpshldvqMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
2069    fn vpshldvq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
2070        self.emit(
2071            VPSHLDVQ128RRR_MASKZ,
2072            op0.as_operand(),
2073            op1.as_operand(),
2074            op2.as_operand(),
2075            &NOREG,
2076        );
2077    }
2078}
2079
2080impl<'a> VpshldvqMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
2081    fn vpshldvq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
2082        self.emit(
2083            VPSHLDVQ128RRM_MASKZ,
2084            op0.as_operand(),
2085            op1.as_operand(),
2086            op2.as_operand(),
2087            &NOREG,
2088        );
2089    }
2090}
2091
2092impl<'a> VpshldvqMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
2093    fn vpshldvq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
2094        self.emit(
2095            VPSHLDVQ256RRR_MASKZ,
2096            op0.as_operand(),
2097            op1.as_operand(),
2098            op2.as_operand(),
2099            &NOREG,
2100        );
2101    }
2102}
2103
2104impl<'a> VpshldvqMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
2105    fn vpshldvq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
2106        self.emit(
2107            VPSHLDVQ256RRM_MASKZ,
2108            op0.as_operand(),
2109            op1.as_operand(),
2110            op2.as_operand(),
2111            &NOREG,
2112        );
2113    }
2114}
2115
2116impl<'a> VpshldvqMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
2117    fn vpshldvq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
2118        self.emit(
2119            VPSHLDVQ512RRR_MASKZ,
2120            op0.as_operand(),
2121            op1.as_operand(),
2122            op2.as_operand(),
2123            &NOREG,
2124        );
2125    }
2126}
2127
2128impl<'a> VpshldvqMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
2129    fn vpshldvq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
2130        self.emit(
2131            VPSHLDVQ512RRM_MASKZ,
2132            op0.as_operand(),
2133            op1.as_operand(),
2134            op2.as_operand(),
2135            &NOREG,
2136        );
2137    }
2138}
2139
2140/// `VPSHLDVW`.
2141///
2142/// Supported operand variants:
2143///
2144/// ```text
2145/// +---+---------------+
2146/// | # | Operands      |
2147/// +---+---------------+
2148/// | 1 | Xmm, Xmm, Mem |
2149/// | 2 | Xmm, Xmm, Xmm |
2150/// | 3 | Ymm, Ymm, Mem |
2151/// | 4 | Ymm, Ymm, Ymm |
2152/// | 5 | Zmm, Zmm, Mem |
2153/// | 6 | Zmm, Zmm, Zmm |
2154/// +---+---------------+
2155/// ```
2156pub trait VpshldvwEmitter<A, B, C> {
2157    fn vpshldvw(&mut self, op0: A, op1: B, op2: C);
2158}
2159
2160impl<'a> VpshldvwEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
2161    fn vpshldvw(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
2162        self.emit(
2163            VPSHLDVW128RRR,
2164            op0.as_operand(),
2165            op1.as_operand(),
2166            op2.as_operand(),
2167            &NOREG,
2168        );
2169    }
2170}
2171
2172impl<'a> VpshldvwEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
2173    fn vpshldvw(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
2174        self.emit(
2175            VPSHLDVW128RRM,
2176            op0.as_operand(),
2177            op1.as_operand(),
2178            op2.as_operand(),
2179            &NOREG,
2180        );
2181    }
2182}
2183
2184impl<'a> VpshldvwEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
2185    fn vpshldvw(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
2186        self.emit(
2187            VPSHLDVW256RRR,
2188            op0.as_operand(),
2189            op1.as_operand(),
2190            op2.as_operand(),
2191            &NOREG,
2192        );
2193    }
2194}
2195
2196impl<'a> VpshldvwEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
2197    fn vpshldvw(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
2198        self.emit(
2199            VPSHLDVW256RRM,
2200            op0.as_operand(),
2201            op1.as_operand(),
2202            op2.as_operand(),
2203            &NOREG,
2204        );
2205    }
2206}
2207
2208impl<'a> VpshldvwEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
2209    fn vpshldvw(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
2210        self.emit(
2211            VPSHLDVW512RRR,
2212            op0.as_operand(),
2213            op1.as_operand(),
2214            op2.as_operand(),
2215            &NOREG,
2216        );
2217    }
2218}
2219
2220impl<'a> VpshldvwEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
2221    fn vpshldvw(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
2222        self.emit(
2223            VPSHLDVW512RRM,
2224            op0.as_operand(),
2225            op1.as_operand(),
2226            op2.as_operand(),
2227            &NOREG,
2228        );
2229    }
2230}
2231
2232/// `VPSHLDVW_MASK`.
2233///
2234/// Supported operand variants:
2235///
2236/// ```text
2237/// +---+---------------+
2238/// | # | Operands      |
2239/// +---+---------------+
2240/// | 1 | Xmm, Xmm, Mem |
2241/// | 2 | Xmm, Xmm, Xmm |
2242/// | 3 | Ymm, Ymm, Mem |
2243/// | 4 | Ymm, Ymm, Ymm |
2244/// | 5 | Zmm, Zmm, Mem |
2245/// | 6 | Zmm, Zmm, Zmm |
2246/// +---+---------------+
2247/// ```
2248pub trait VpshldvwMaskEmitter<A, B, C> {
2249    fn vpshldvw_mask(&mut self, op0: A, op1: B, op2: C);
2250}
2251
2252impl<'a> VpshldvwMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
2253    fn vpshldvw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
2254        self.emit(
2255            VPSHLDVW128RRR_MASK,
2256            op0.as_operand(),
2257            op1.as_operand(),
2258            op2.as_operand(),
2259            &NOREG,
2260        );
2261    }
2262}
2263
2264impl<'a> VpshldvwMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
2265    fn vpshldvw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
2266        self.emit(
2267            VPSHLDVW128RRM_MASK,
2268            op0.as_operand(),
2269            op1.as_operand(),
2270            op2.as_operand(),
2271            &NOREG,
2272        );
2273    }
2274}
2275
2276impl<'a> VpshldvwMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
2277    fn vpshldvw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
2278        self.emit(
2279            VPSHLDVW256RRR_MASK,
2280            op0.as_operand(),
2281            op1.as_operand(),
2282            op2.as_operand(),
2283            &NOREG,
2284        );
2285    }
2286}
2287
2288impl<'a> VpshldvwMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
2289    fn vpshldvw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
2290        self.emit(
2291            VPSHLDVW256RRM_MASK,
2292            op0.as_operand(),
2293            op1.as_operand(),
2294            op2.as_operand(),
2295            &NOREG,
2296        );
2297    }
2298}
2299
2300impl<'a> VpshldvwMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
2301    fn vpshldvw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
2302        self.emit(
2303            VPSHLDVW512RRR_MASK,
2304            op0.as_operand(),
2305            op1.as_operand(),
2306            op2.as_operand(),
2307            &NOREG,
2308        );
2309    }
2310}
2311
2312impl<'a> VpshldvwMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
2313    fn vpshldvw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
2314        self.emit(
2315            VPSHLDVW512RRM_MASK,
2316            op0.as_operand(),
2317            op1.as_operand(),
2318            op2.as_operand(),
2319            &NOREG,
2320        );
2321    }
2322}
2323
2324/// `VPSHLDVW_MASKZ`.
2325///
2326/// Supported operand variants:
2327///
2328/// ```text
2329/// +---+---------------+
2330/// | # | Operands      |
2331/// +---+---------------+
2332/// | 1 | Xmm, Xmm, Mem |
2333/// | 2 | Xmm, Xmm, Xmm |
2334/// | 3 | Ymm, Ymm, Mem |
2335/// | 4 | Ymm, Ymm, Ymm |
2336/// | 5 | Zmm, Zmm, Mem |
2337/// | 6 | Zmm, Zmm, Zmm |
2338/// +---+---------------+
2339/// ```
2340pub trait VpshldvwMaskzEmitter<A, B, C> {
2341    fn vpshldvw_maskz(&mut self, op0: A, op1: B, op2: C);
2342}
2343
2344impl<'a> VpshldvwMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
2345    fn vpshldvw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
2346        self.emit(
2347            VPSHLDVW128RRR_MASKZ,
2348            op0.as_operand(),
2349            op1.as_operand(),
2350            op2.as_operand(),
2351            &NOREG,
2352        );
2353    }
2354}
2355
2356impl<'a> VpshldvwMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
2357    fn vpshldvw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
2358        self.emit(
2359            VPSHLDVW128RRM_MASKZ,
2360            op0.as_operand(),
2361            op1.as_operand(),
2362            op2.as_operand(),
2363            &NOREG,
2364        );
2365    }
2366}
2367
2368impl<'a> VpshldvwMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
2369    fn vpshldvw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
2370        self.emit(
2371            VPSHLDVW256RRR_MASKZ,
2372            op0.as_operand(),
2373            op1.as_operand(),
2374            op2.as_operand(),
2375            &NOREG,
2376        );
2377    }
2378}
2379
2380impl<'a> VpshldvwMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
2381    fn vpshldvw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
2382        self.emit(
2383            VPSHLDVW256RRM_MASKZ,
2384            op0.as_operand(),
2385            op1.as_operand(),
2386            op2.as_operand(),
2387            &NOREG,
2388        );
2389    }
2390}
2391
2392impl<'a> VpshldvwMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
2393    fn vpshldvw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
2394        self.emit(
2395            VPSHLDVW512RRR_MASKZ,
2396            op0.as_operand(),
2397            op1.as_operand(),
2398            op2.as_operand(),
2399            &NOREG,
2400        );
2401    }
2402}
2403
2404impl<'a> VpshldvwMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
2405    fn vpshldvw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
2406        self.emit(
2407            VPSHLDVW512RRM_MASKZ,
2408            op0.as_operand(),
2409            op1.as_operand(),
2410            op2.as_operand(),
2411            &NOREG,
2412        );
2413    }
2414}
2415
2416/// `VPSHLDW`.
2417///
2418/// Supported operand variants:
2419///
2420/// ```text
2421/// +---+--------------------+
2422/// | # | Operands           |
2423/// +---+--------------------+
2424/// | 1 | Xmm, Xmm, Mem, Imm |
2425/// | 2 | Xmm, Xmm, Xmm, Imm |
2426/// | 3 | Ymm, Ymm, Mem, Imm |
2427/// | 4 | Ymm, Ymm, Ymm, Imm |
2428/// | 5 | Zmm, Zmm, Mem, Imm |
2429/// | 6 | Zmm, Zmm, Zmm, Imm |
2430/// +---+--------------------+
2431/// ```
2432pub trait VpshldwEmitter<A, B, C, D> {
2433    fn vpshldw(&mut self, op0: A, op1: B, op2: C, op3: D);
2434}
2435
2436impl<'a> VpshldwEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
2437    fn vpshldw(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
2438        self.emit(
2439            VPSHLDW128RRRI,
2440            op0.as_operand(),
2441            op1.as_operand(),
2442            op2.as_operand(),
2443            op3.as_operand(),
2444        );
2445    }
2446}
2447
2448impl<'a> VpshldwEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
2449    fn vpshldw(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
2450        self.emit(
2451            VPSHLDW128RRMI,
2452            op0.as_operand(),
2453            op1.as_operand(),
2454            op2.as_operand(),
2455            op3.as_operand(),
2456        );
2457    }
2458}
2459
2460impl<'a> VpshldwEmitter<Ymm, Ymm, Ymm, Imm> for Assembler<'a> {
2461    fn vpshldw(&mut self, op0: Ymm, op1: Ymm, op2: Ymm, op3: Imm) {
2462        self.emit(
2463            VPSHLDW256RRRI,
2464            op0.as_operand(),
2465            op1.as_operand(),
2466            op2.as_operand(),
2467            op3.as_operand(),
2468        );
2469    }
2470}
2471
2472impl<'a> VpshldwEmitter<Ymm, Ymm, Mem, Imm> for Assembler<'a> {
2473    fn vpshldw(&mut self, op0: Ymm, op1: Ymm, op2: Mem, op3: Imm) {
2474        self.emit(
2475            VPSHLDW256RRMI,
2476            op0.as_operand(),
2477            op1.as_operand(),
2478            op2.as_operand(),
2479            op3.as_operand(),
2480        );
2481    }
2482}
2483
2484impl<'a> VpshldwEmitter<Zmm, Zmm, Zmm, Imm> for Assembler<'a> {
2485    fn vpshldw(&mut self, op0: Zmm, op1: Zmm, op2: Zmm, op3: Imm) {
2486        self.emit(
2487            VPSHLDW512RRRI,
2488            op0.as_operand(),
2489            op1.as_operand(),
2490            op2.as_operand(),
2491            op3.as_operand(),
2492        );
2493    }
2494}
2495
2496impl<'a> VpshldwEmitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
2497    fn vpshldw(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
2498        self.emit(
2499            VPSHLDW512RRMI,
2500            op0.as_operand(),
2501            op1.as_operand(),
2502            op2.as_operand(),
2503            op3.as_operand(),
2504        );
2505    }
2506}
2507
2508/// `VPSHLDW_MASK`.
2509///
2510/// Supported operand variants:
2511///
2512/// ```text
2513/// +---+--------------------+
2514/// | # | Operands           |
2515/// +---+--------------------+
2516/// | 1 | Xmm, Xmm, Mem, Imm |
2517/// | 2 | Xmm, Xmm, Xmm, Imm |
2518/// | 3 | Ymm, Ymm, Mem, Imm |
2519/// | 4 | Ymm, Ymm, Ymm, Imm |
2520/// | 5 | Zmm, Zmm, Mem, Imm |
2521/// | 6 | Zmm, Zmm, Zmm, Imm |
2522/// +---+--------------------+
2523/// ```
2524pub trait VpshldwMaskEmitter<A, B, C, D> {
2525    fn vpshldw_mask(&mut self, op0: A, op1: B, op2: C, op3: D);
2526}
2527
2528impl<'a> VpshldwMaskEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
2529    fn vpshldw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
2530        self.emit(
2531            VPSHLDW128RRRI_MASK,
2532            op0.as_operand(),
2533            op1.as_operand(),
2534            op2.as_operand(),
2535            op3.as_operand(),
2536        );
2537    }
2538}
2539
2540impl<'a> VpshldwMaskEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
2541    fn vpshldw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
2542        self.emit(
2543            VPSHLDW128RRMI_MASK,
2544            op0.as_operand(),
2545            op1.as_operand(),
2546            op2.as_operand(),
2547            op3.as_operand(),
2548        );
2549    }
2550}
2551
2552impl<'a> VpshldwMaskEmitter<Ymm, Ymm, Ymm, Imm> for Assembler<'a> {
2553    fn vpshldw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm, op3: Imm) {
2554        self.emit(
2555            VPSHLDW256RRRI_MASK,
2556            op0.as_operand(),
2557            op1.as_operand(),
2558            op2.as_operand(),
2559            op3.as_operand(),
2560        );
2561    }
2562}
2563
2564impl<'a> VpshldwMaskEmitter<Ymm, Ymm, Mem, Imm> for Assembler<'a> {
2565    fn vpshldw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem, op3: Imm) {
2566        self.emit(
2567            VPSHLDW256RRMI_MASK,
2568            op0.as_operand(),
2569            op1.as_operand(),
2570            op2.as_operand(),
2571            op3.as_operand(),
2572        );
2573    }
2574}
2575
2576impl<'a> VpshldwMaskEmitter<Zmm, Zmm, Zmm, Imm> for Assembler<'a> {
2577    fn vpshldw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm, op3: Imm) {
2578        self.emit(
2579            VPSHLDW512RRRI_MASK,
2580            op0.as_operand(),
2581            op1.as_operand(),
2582            op2.as_operand(),
2583            op3.as_operand(),
2584        );
2585    }
2586}
2587
2588impl<'a> VpshldwMaskEmitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
2589    fn vpshldw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
2590        self.emit(
2591            VPSHLDW512RRMI_MASK,
2592            op0.as_operand(),
2593            op1.as_operand(),
2594            op2.as_operand(),
2595            op3.as_operand(),
2596        );
2597    }
2598}
2599
2600/// `VPSHLDW_MASKZ`.
2601///
2602/// Supported operand variants:
2603///
2604/// ```text
2605/// +---+--------------------+
2606/// | # | Operands           |
2607/// +---+--------------------+
2608/// | 1 | Xmm, Xmm, Mem, Imm |
2609/// | 2 | Xmm, Xmm, Xmm, Imm |
2610/// | 3 | Ymm, Ymm, Mem, Imm |
2611/// | 4 | Ymm, Ymm, Ymm, Imm |
2612/// | 5 | Zmm, Zmm, Mem, Imm |
2613/// | 6 | Zmm, Zmm, Zmm, Imm |
2614/// +---+--------------------+
2615/// ```
2616pub trait VpshldwMaskzEmitter<A, B, C, D> {
2617    fn vpshldw_maskz(&mut self, op0: A, op1: B, op2: C, op3: D);
2618}
2619
2620impl<'a> VpshldwMaskzEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
2621    fn vpshldw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
2622        self.emit(
2623            VPSHLDW128RRRI_MASKZ,
2624            op0.as_operand(),
2625            op1.as_operand(),
2626            op2.as_operand(),
2627            op3.as_operand(),
2628        );
2629    }
2630}
2631
2632impl<'a> VpshldwMaskzEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
2633    fn vpshldw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
2634        self.emit(
2635            VPSHLDW128RRMI_MASKZ,
2636            op0.as_operand(),
2637            op1.as_operand(),
2638            op2.as_operand(),
2639            op3.as_operand(),
2640        );
2641    }
2642}
2643
2644impl<'a> VpshldwMaskzEmitter<Ymm, Ymm, Ymm, Imm> for Assembler<'a> {
2645    fn vpshldw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm, op3: Imm) {
2646        self.emit(
2647            VPSHLDW256RRRI_MASKZ,
2648            op0.as_operand(),
2649            op1.as_operand(),
2650            op2.as_operand(),
2651            op3.as_operand(),
2652        );
2653    }
2654}
2655
2656impl<'a> VpshldwMaskzEmitter<Ymm, Ymm, Mem, Imm> for Assembler<'a> {
2657    fn vpshldw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem, op3: Imm) {
2658        self.emit(
2659            VPSHLDW256RRMI_MASKZ,
2660            op0.as_operand(),
2661            op1.as_operand(),
2662            op2.as_operand(),
2663            op3.as_operand(),
2664        );
2665    }
2666}
2667
2668impl<'a> VpshldwMaskzEmitter<Zmm, Zmm, Zmm, Imm> for Assembler<'a> {
2669    fn vpshldw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm, op3: Imm) {
2670        self.emit(
2671            VPSHLDW512RRRI_MASKZ,
2672            op0.as_operand(),
2673            op1.as_operand(),
2674            op2.as_operand(),
2675            op3.as_operand(),
2676        );
2677    }
2678}
2679
2680impl<'a> VpshldwMaskzEmitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
2681    fn vpshldw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
2682        self.emit(
2683            VPSHLDW512RRMI_MASKZ,
2684            op0.as_operand(),
2685            op1.as_operand(),
2686            op2.as_operand(),
2687            op3.as_operand(),
2688        );
2689    }
2690}
2691
2692/// `VPSHRDD`.
2693///
2694/// Supported operand variants:
2695///
2696/// ```text
2697/// +---+--------------------+
2698/// | # | Operands           |
2699/// +---+--------------------+
2700/// | 1 | Xmm, Xmm, Mem, Imm |
2701/// | 2 | Xmm, Xmm, Xmm, Imm |
2702/// | 3 | Ymm, Ymm, Mem, Imm |
2703/// | 4 | Ymm, Ymm, Ymm, Imm |
2704/// | 5 | Zmm, Zmm, Mem, Imm |
2705/// | 6 | Zmm, Zmm, Zmm, Imm |
2706/// +---+--------------------+
2707/// ```
2708pub trait VpshrddEmitter<A, B, C, D> {
2709    fn vpshrdd(&mut self, op0: A, op1: B, op2: C, op3: D);
2710}
2711
2712impl<'a> VpshrddEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
2713    fn vpshrdd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
2714        self.emit(
2715            VPSHRDD128RRRI,
2716            op0.as_operand(),
2717            op1.as_operand(),
2718            op2.as_operand(),
2719            op3.as_operand(),
2720        );
2721    }
2722}
2723
2724impl<'a> VpshrddEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
2725    fn vpshrdd(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
2726        self.emit(
2727            VPSHRDD128RRMI,
2728            op0.as_operand(),
2729            op1.as_operand(),
2730            op2.as_operand(),
2731            op3.as_operand(),
2732        );
2733    }
2734}
2735
2736impl<'a> VpshrddEmitter<Ymm, Ymm, Ymm, Imm> for Assembler<'a> {
2737    fn vpshrdd(&mut self, op0: Ymm, op1: Ymm, op2: Ymm, op3: Imm) {
2738        self.emit(
2739            VPSHRDD256RRRI,
2740            op0.as_operand(),
2741            op1.as_operand(),
2742            op2.as_operand(),
2743            op3.as_operand(),
2744        );
2745    }
2746}
2747
2748impl<'a> VpshrddEmitter<Ymm, Ymm, Mem, Imm> for Assembler<'a> {
2749    fn vpshrdd(&mut self, op0: Ymm, op1: Ymm, op2: Mem, op3: Imm) {
2750        self.emit(
2751            VPSHRDD256RRMI,
2752            op0.as_operand(),
2753            op1.as_operand(),
2754            op2.as_operand(),
2755            op3.as_operand(),
2756        );
2757    }
2758}
2759
2760impl<'a> VpshrddEmitter<Zmm, Zmm, Zmm, Imm> for Assembler<'a> {
2761    fn vpshrdd(&mut self, op0: Zmm, op1: Zmm, op2: Zmm, op3: Imm) {
2762        self.emit(
2763            VPSHRDD512RRRI,
2764            op0.as_operand(),
2765            op1.as_operand(),
2766            op2.as_operand(),
2767            op3.as_operand(),
2768        );
2769    }
2770}
2771
2772impl<'a> VpshrddEmitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
2773    fn vpshrdd(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
2774        self.emit(
2775            VPSHRDD512RRMI,
2776            op0.as_operand(),
2777            op1.as_operand(),
2778            op2.as_operand(),
2779            op3.as_operand(),
2780        );
2781    }
2782}
2783
2784/// `VPSHRDD_MASK`.
2785///
2786/// Supported operand variants:
2787///
2788/// ```text
2789/// +---+--------------------+
2790/// | # | Operands           |
2791/// +---+--------------------+
2792/// | 1 | Xmm, Xmm, Mem, Imm |
2793/// | 2 | Xmm, Xmm, Xmm, Imm |
2794/// | 3 | Ymm, Ymm, Mem, Imm |
2795/// | 4 | Ymm, Ymm, Ymm, Imm |
2796/// | 5 | Zmm, Zmm, Mem, Imm |
2797/// | 6 | Zmm, Zmm, Zmm, Imm |
2798/// +---+--------------------+
2799/// ```
2800pub trait VpshrddMaskEmitter<A, B, C, D> {
2801    fn vpshrdd_mask(&mut self, op0: A, op1: B, op2: C, op3: D);
2802}
2803
2804impl<'a> VpshrddMaskEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
2805    fn vpshrdd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
2806        self.emit(
2807            VPSHRDD128RRRI_MASK,
2808            op0.as_operand(),
2809            op1.as_operand(),
2810            op2.as_operand(),
2811            op3.as_operand(),
2812        );
2813    }
2814}
2815
2816impl<'a> VpshrddMaskEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
2817    fn vpshrdd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
2818        self.emit(
2819            VPSHRDD128RRMI_MASK,
2820            op0.as_operand(),
2821            op1.as_operand(),
2822            op2.as_operand(),
2823            op3.as_operand(),
2824        );
2825    }
2826}
2827
2828impl<'a> VpshrddMaskEmitter<Ymm, Ymm, Ymm, Imm> for Assembler<'a> {
2829    fn vpshrdd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm, op3: Imm) {
2830        self.emit(
2831            VPSHRDD256RRRI_MASK,
2832            op0.as_operand(),
2833            op1.as_operand(),
2834            op2.as_operand(),
2835            op3.as_operand(),
2836        );
2837    }
2838}
2839
2840impl<'a> VpshrddMaskEmitter<Ymm, Ymm, Mem, Imm> for Assembler<'a> {
2841    fn vpshrdd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem, op3: Imm) {
2842        self.emit(
2843            VPSHRDD256RRMI_MASK,
2844            op0.as_operand(),
2845            op1.as_operand(),
2846            op2.as_operand(),
2847            op3.as_operand(),
2848        );
2849    }
2850}
2851
2852impl<'a> VpshrddMaskEmitter<Zmm, Zmm, Zmm, Imm> for Assembler<'a> {
2853    fn vpshrdd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm, op3: Imm) {
2854        self.emit(
2855            VPSHRDD512RRRI_MASK,
2856            op0.as_operand(),
2857            op1.as_operand(),
2858            op2.as_operand(),
2859            op3.as_operand(),
2860        );
2861    }
2862}
2863
2864impl<'a> VpshrddMaskEmitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
2865    fn vpshrdd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
2866        self.emit(
2867            VPSHRDD512RRMI_MASK,
2868            op0.as_operand(),
2869            op1.as_operand(),
2870            op2.as_operand(),
2871            op3.as_operand(),
2872        );
2873    }
2874}
2875
2876/// `VPSHRDD_MASKZ`.
2877///
2878/// Supported operand variants:
2879///
2880/// ```text
2881/// +---+--------------------+
2882/// | # | Operands           |
2883/// +---+--------------------+
2884/// | 1 | Xmm, Xmm, Mem, Imm |
2885/// | 2 | Xmm, Xmm, Xmm, Imm |
2886/// | 3 | Ymm, Ymm, Mem, Imm |
2887/// | 4 | Ymm, Ymm, Ymm, Imm |
2888/// | 5 | Zmm, Zmm, Mem, Imm |
2889/// | 6 | Zmm, Zmm, Zmm, Imm |
2890/// +---+--------------------+
2891/// ```
2892pub trait VpshrddMaskzEmitter<A, B, C, D> {
2893    fn vpshrdd_maskz(&mut self, op0: A, op1: B, op2: C, op3: D);
2894}
2895
2896impl<'a> VpshrddMaskzEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
2897    fn vpshrdd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
2898        self.emit(
2899            VPSHRDD128RRRI_MASKZ,
2900            op0.as_operand(),
2901            op1.as_operand(),
2902            op2.as_operand(),
2903            op3.as_operand(),
2904        );
2905    }
2906}
2907
2908impl<'a> VpshrddMaskzEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
2909    fn vpshrdd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
2910        self.emit(
2911            VPSHRDD128RRMI_MASKZ,
2912            op0.as_operand(),
2913            op1.as_operand(),
2914            op2.as_operand(),
2915            op3.as_operand(),
2916        );
2917    }
2918}
2919
2920impl<'a> VpshrddMaskzEmitter<Ymm, Ymm, Ymm, Imm> for Assembler<'a> {
2921    fn vpshrdd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm, op3: Imm) {
2922        self.emit(
2923            VPSHRDD256RRRI_MASKZ,
2924            op0.as_operand(),
2925            op1.as_operand(),
2926            op2.as_operand(),
2927            op3.as_operand(),
2928        );
2929    }
2930}
2931
2932impl<'a> VpshrddMaskzEmitter<Ymm, Ymm, Mem, Imm> for Assembler<'a> {
2933    fn vpshrdd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem, op3: Imm) {
2934        self.emit(
2935            VPSHRDD256RRMI_MASKZ,
2936            op0.as_operand(),
2937            op1.as_operand(),
2938            op2.as_operand(),
2939            op3.as_operand(),
2940        );
2941    }
2942}
2943
2944impl<'a> VpshrddMaskzEmitter<Zmm, Zmm, Zmm, Imm> for Assembler<'a> {
2945    fn vpshrdd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm, op3: Imm) {
2946        self.emit(
2947            VPSHRDD512RRRI_MASKZ,
2948            op0.as_operand(),
2949            op1.as_operand(),
2950            op2.as_operand(),
2951            op3.as_operand(),
2952        );
2953    }
2954}
2955
2956impl<'a> VpshrddMaskzEmitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
2957    fn vpshrdd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
2958        self.emit(
2959            VPSHRDD512RRMI_MASKZ,
2960            op0.as_operand(),
2961            op1.as_operand(),
2962            op2.as_operand(),
2963            op3.as_operand(),
2964        );
2965    }
2966}
2967
2968/// `VPSHRDQ`.
2969///
2970/// Supported operand variants:
2971///
2972/// ```text
2973/// +---+--------------------+
2974/// | # | Operands           |
2975/// +---+--------------------+
2976/// | 1 | Xmm, Xmm, Mem, Imm |
2977/// | 2 | Xmm, Xmm, Xmm, Imm |
2978/// | 3 | Ymm, Ymm, Mem, Imm |
2979/// | 4 | Ymm, Ymm, Ymm, Imm |
2980/// | 5 | Zmm, Zmm, Mem, Imm |
2981/// | 6 | Zmm, Zmm, Zmm, Imm |
2982/// +---+--------------------+
2983/// ```
2984pub trait VpshrdqEmitter<A, B, C, D> {
2985    fn vpshrdq(&mut self, op0: A, op1: B, op2: C, op3: D);
2986}
2987
2988impl<'a> VpshrdqEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
2989    fn vpshrdq(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
2990        self.emit(
2991            VPSHRDQ128RRRI,
2992            op0.as_operand(),
2993            op1.as_operand(),
2994            op2.as_operand(),
2995            op3.as_operand(),
2996        );
2997    }
2998}
2999
3000impl<'a> VpshrdqEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
3001    fn vpshrdq(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
3002        self.emit(
3003            VPSHRDQ128RRMI,
3004            op0.as_operand(),
3005            op1.as_operand(),
3006            op2.as_operand(),
3007            op3.as_operand(),
3008        );
3009    }
3010}
3011
3012impl<'a> VpshrdqEmitter<Ymm, Ymm, Ymm, Imm> for Assembler<'a> {
3013    fn vpshrdq(&mut self, op0: Ymm, op1: Ymm, op2: Ymm, op3: Imm) {
3014        self.emit(
3015            VPSHRDQ256RRRI,
3016            op0.as_operand(),
3017            op1.as_operand(),
3018            op2.as_operand(),
3019            op3.as_operand(),
3020        );
3021    }
3022}
3023
3024impl<'a> VpshrdqEmitter<Ymm, Ymm, Mem, Imm> for Assembler<'a> {
3025    fn vpshrdq(&mut self, op0: Ymm, op1: Ymm, op2: Mem, op3: Imm) {
3026        self.emit(
3027            VPSHRDQ256RRMI,
3028            op0.as_operand(),
3029            op1.as_operand(),
3030            op2.as_operand(),
3031            op3.as_operand(),
3032        );
3033    }
3034}
3035
3036impl<'a> VpshrdqEmitter<Zmm, Zmm, Zmm, Imm> for Assembler<'a> {
3037    fn vpshrdq(&mut self, op0: Zmm, op1: Zmm, op2: Zmm, op3: Imm) {
3038        self.emit(
3039            VPSHRDQ512RRRI,
3040            op0.as_operand(),
3041            op1.as_operand(),
3042            op2.as_operand(),
3043            op3.as_operand(),
3044        );
3045    }
3046}
3047
3048impl<'a> VpshrdqEmitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
3049    fn vpshrdq(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
3050        self.emit(
3051            VPSHRDQ512RRMI,
3052            op0.as_operand(),
3053            op1.as_operand(),
3054            op2.as_operand(),
3055            op3.as_operand(),
3056        );
3057    }
3058}
3059
3060/// `VPSHRDQ_MASK`.
3061///
3062/// Supported operand variants:
3063///
3064/// ```text
3065/// +---+--------------------+
3066/// | # | Operands           |
3067/// +---+--------------------+
3068/// | 1 | Xmm, Xmm, Mem, Imm |
3069/// | 2 | Xmm, Xmm, Xmm, Imm |
3070/// | 3 | Ymm, Ymm, Mem, Imm |
3071/// | 4 | Ymm, Ymm, Ymm, Imm |
3072/// | 5 | Zmm, Zmm, Mem, Imm |
3073/// | 6 | Zmm, Zmm, Zmm, Imm |
3074/// +---+--------------------+
3075/// ```
3076pub trait VpshrdqMaskEmitter<A, B, C, D> {
3077    fn vpshrdq_mask(&mut self, op0: A, op1: B, op2: C, op3: D);
3078}
3079
3080impl<'a> VpshrdqMaskEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
3081    fn vpshrdq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
3082        self.emit(
3083            VPSHRDQ128RRRI_MASK,
3084            op0.as_operand(),
3085            op1.as_operand(),
3086            op2.as_operand(),
3087            op3.as_operand(),
3088        );
3089    }
3090}
3091
3092impl<'a> VpshrdqMaskEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
3093    fn vpshrdq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
3094        self.emit(
3095            VPSHRDQ128RRMI_MASK,
3096            op0.as_operand(),
3097            op1.as_operand(),
3098            op2.as_operand(),
3099            op3.as_operand(),
3100        );
3101    }
3102}
3103
3104impl<'a> VpshrdqMaskEmitter<Ymm, Ymm, Ymm, Imm> for Assembler<'a> {
3105    fn vpshrdq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm, op3: Imm) {
3106        self.emit(
3107            VPSHRDQ256RRRI_MASK,
3108            op0.as_operand(),
3109            op1.as_operand(),
3110            op2.as_operand(),
3111            op3.as_operand(),
3112        );
3113    }
3114}
3115
3116impl<'a> VpshrdqMaskEmitter<Ymm, Ymm, Mem, Imm> for Assembler<'a> {
3117    fn vpshrdq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem, op3: Imm) {
3118        self.emit(
3119            VPSHRDQ256RRMI_MASK,
3120            op0.as_operand(),
3121            op1.as_operand(),
3122            op2.as_operand(),
3123            op3.as_operand(),
3124        );
3125    }
3126}
3127
3128impl<'a> VpshrdqMaskEmitter<Zmm, Zmm, Zmm, Imm> for Assembler<'a> {
3129    fn vpshrdq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm, op3: Imm) {
3130        self.emit(
3131            VPSHRDQ512RRRI_MASK,
3132            op0.as_operand(),
3133            op1.as_operand(),
3134            op2.as_operand(),
3135            op3.as_operand(),
3136        );
3137    }
3138}
3139
3140impl<'a> VpshrdqMaskEmitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
3141    fn vpshrdq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
3142        self.emit(
3143            VPSHRDQ512RRMI_MASK,
3144            op0.as_operand(),
3145            op1.as_operand(),
3146            op2.as_operand(),
3147            op3.as_operand(),
3148        );
3149    }
3150}
3151
3152/// `VPSHRDQ_MASKZ`.
3153///
3154/// Supported operand variants:
3155///
3156/// ```text
3157/// +---+--------------------+
3158/// | # | Operands           |
3159/// +---+--------------------+
3160/// | 1 | Xmm, Xmm, Mem, Imm |
3161/// | 2 | Xmm, Xmm, Xmm, Imm |
3162/// | 3 | Ymm, Ymm, Mem, Imm |
3163/// | 4 | Ymm, Ymm, Ymm, Imm |
3164/// | 5 | Zmm, Zmm, Mem, Imm |
3165/// | 6 | Zmm, Zmm, Zmm, Imm |
3166/// +---+--------------------+
3167/// ```
3168pub trait VpshrdqMaskzEmitter<A, B, C, D> {
3169    fn vpshrdq_maskz(&mut self, op0: A, op1: B, op2: C, op3: D);
3170}
3171
3172impl<'a> VpshrdqMaskzEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
3173    fn vpshrdq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
3174        self.emit(
3175            VPSHRDQ128RRRI_MASKZ,
3176            op0.as_operand(),
3177            op1.as_operand(),
3178            op2.as_operand(),
3179            op3.as_operand(),
3180        );
3181    }
3182}
3183
3184impl<'a> VpshrdqMaskzEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
3185    fn vpshrdq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
3186        self.emit(
3187            VPSHRDQ128RRMI_MASKZ,
3188            op0.as_operand(),
3189            op1.as_operand(),
3190            op2.as_operand(),
3191            op3.as_operand(),
3192        );
3193    }
3194}
3195
3196impl<'a> VpshrdqMaskzEmitter<Ymm, Ymm, Ymm, Imm> for Assembler<'a> {
3197    fn vpshrdq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm, op3: Imm) {
3198        self.emit(
3199            VPSHRDQ256RRRI_MASKZ,
3200            op0.as_operand(),
3201            op1.as_operand(),
3202            op2.as_operand(),
3203            op3.as_operand(),
3204        );
3205    }
3206}
3207
3208impl<'a> VpshrdqMaskzEmitter<Ymm, Ymm, Mem, Imm> for Assembler<'a> {
3209    fn vpshrdq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem, op3: Imm) {
3210        self.emit(
3211            VPSHRDQ256RRMI_MASKZ,
3212            op0.as_operand(),
3213            op1.as_operand(),
3214            op2.as_operand(),
3215            op3.as_operand(),
3216        );
3217    }
3218}
3219
3220impl<'a> VpshrdqMaskzEmitter<Zmm, Zmm, Zmm, Imm> for Assembler<'a> {
3221    fn vpshrdq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm, op3: Imm) {
3222        self.emit(
3223            VPSHRDQ512RRRI_MASKZ,
3224            op0.as_operand(),
3225            op1.as_operand(),
3226            op2.as_operand(),
3227            op3.as_operand(),
3228        );
3229    }
3230}
3231
3232impl<'a> VpshrdqMaskzEmitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
3233    fn vpshrdq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
3234        self.emit(
3235            VPSHRDQ512RRMI_MASKZ,
3236            op0.as_operand(),
3237            op1.as_operand(),
3238            op2.as_operand(),
3239            op3.as_operand(),
3240        );
3241    }
3242}
3243
3244/// `VPSHRDVD`.
3245///
3246/// Supported operand variants:
3247///
3248/// ```text
3249/// +---+---------------+
3250/// | # | Operands      |
3251/// +---+---------------+
3252/// | 1 | Xmm, Xmm, Mem |
3253/// | 2 | Xmm, Xmm, Xmm |
3254/// | 3 | Ymm, Ymm, Mem |
3255/// | 4 | Ymm, Ymm, Ymm |
3256/// | 5 | Zmm, Zmm, Mem |
3257/// | 6 | Zmm, Zmm, Zmm |
3258/// +---+---------------+
3259/// ```
3260pub trait VpshrdvdEmitter<A, B, C> {
3261    fn vpshrdvd(&mut self, op0: A, op1: B, op2: C);
3262}
3263
3264impl<'a> VpshrdvdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
3265    fn vpshrdvd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
3266        self.emit(
3267            VPSHRDVD128RRR,
3268            op0.as_operand(),
3269            op1.as_operand(),
3270            op2.as_operand(),
3271            &NOREG,
3272        );
3273    }
3274}
3275
3276impl<'a> VpshrdvdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
3277    fn vpshrdvd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
3278        self.emit(
3279            VPSHRDVD128RRM,
3280            op0.as_operand(),
3281            op1.as_operand(),
3282            op2.as_operand(),
3283            &NOREG,
3284        );
3285    }
3286}
3287
3288impl<'a> VpshrdvdEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
3289    fn vpshrdvd(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
3290        self.emit(
3291            VPSHRDVD256RRR,
3292            op0.as_operand(),
3293            op1.as_operand(),
3294            op2.as_operand(),
3295            &NOREG,
3296        );
3297    }
3298}
3299
3300impl<'a> VpshrdvdEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
3301    fn vpshrdvd(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
3302        self.emit(
3303            VPSHRDVD256RRM,
3304            op0.as_operand(),
3305            op1.as_operand(),
3306            op2.as_operand(),
3307            &NOREG,
3308        );
3309    }
3310}
3311
3312impl<'a> VpshrdvdEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
3313    fn vpshrdvd(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
3314        self.emit(
3315            VPSHRDVD512RRR,
3316            op0.as_operand(),
3317            op1.as_operand(),
3318            op2.as_operand(),
3319            &NOREG,
3320        );
3321    }
3322}
3323
3324impl<'a> VpshrdvdEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
3325    fn vpshrdvd(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
3326        self.emit(
3327            VPSHRDVD512RRM,
3328            op0.as_operand(),
3329            op1.as_operand(),
3330            op2.as_operand(),
3331            &NOREG,
3332        );
3333    }
3334}
3335
3336/// `VPSHRDVD_MASK`.
3337///
3338/// Supported operand variants:
3339///
3340/// ```text
3341/// +---+---------------+
3342/// | # | Operands      |
3343/// +---+---------------+
3344/// | 1 | Xmm, Xmm, Mem |
3345/// | 2 | Xmm, Xmm, Xmm |
3346/// | 3 | Ymm, Ymm, Mem |
3347/// | 4 | Ymm, Ymm, Ymm |
3348/// | 5 | Zmm, Zmm, Mem |
3349/// | 6 | Zmm, Zmm, Zmm |
3350/// +---+---------------+
3351/// ```
3352pub trait VpshrdvdMaskEmitter<A, B, C> {
3353    fn vpshrdvd_mask(&mut self, op0: A, op1: B, op2: C);
3354}
3355
3356impl<'a> VpshrdvdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
3357    fn vpshrdvd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
3358        self.emit(
3359            VPSHRDVD128RRR_MASK,
3360            op0.as_operand(),
3361            op1.as_operand(),
3362            op2.as_operand(),
3363            &NOREG,
3364        );
3365    }
3366}
3367
3368impl<'a> VpshrdvdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
3369    fn vpshrdvd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
3370        self.emit(
3371            VPSHRDVD128RRM_MASK,
3372            op0.as_operand(),
3373            op1.as_operand(),
3374            op2.as_operand(),
3375            &NOREG,
3376        );
3377    }
3378}
3379
3380impl<'a> VpshrdvdMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
3381    fn vpshrdvd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
3382        self.emit(
3383            VPSHRDVD256RRR_MASK,
3384            op0.as_operand(),
3385            op1.as_operand(),
3386            op2.as_operand(),
3387            &NOREG,
3388        );
3389    }
3390}
3391
3392impl<'a> VpshrdvdMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
3393    fn vpshrdvd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
3394        self.emit(
3395            VPSHRDVD256RRM_MASK,
3396            op0.as_operand(),
3397            op1.as_operand(),
3398            op2.as_operand(),
3399            &NOREG,
3400        );
3401    }
3402}
3403
3404impl<'a> VpshrdvdMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
3405    fn vpshrdvd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
3406        self.emit(
3407            VPSHRDVD512RRR_MASK,
3408            op0.as_operand(),
3409            op1.as_operand(),
3410            op2.as_operand(),
3411            &NOREG,
3412        );
3413    }
3414}
3415
3416impl<'a> VpshrdvdMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
3417    fn vpshrdvd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
3418        self.emit(
3419            VPSHRDVD512RRM_MASK,
3420            op0.as_operand(),
3421            op1.as_operand(),
3422            op2.as_operand(),
3423            &NOREG,
3424        );
3425    }
3426}
3427
3428/// `VPSHRDVD_MASKZ`.
3429///
3430/// Supported operand variants:
3431///
3432/// ```text
3433/// +---+---------------+
3434/// | # | Operands      |
3435/// +---+---------------+
3436/// | 1 | Xmm, Xmm, Mem |
3437/// | 2 | Xmm, Xmm, Xmm |
3438/// | 3 | Ymm, Ymm, Mem |
3439/// | 4 | Ymm, Ymm, Ymm |
3440/// | 5 | Zmm, Zmm, Mem |
3441/// | 6 | Zmm, Zmm, Zmm |
3442/// +---+---------------+
3443/// ```
3444pub trait VpshrdvdMaskzEmitter<A, B, C> {
3445    fn vpshrdvd_maskz(&mut self, op0: A, op1: B, op2: C);
3446}
3447
3448impl<'a> VpshrdvdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
3449    fn vpshrdvd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
3450        self.emit(
3451            VPSHRDVD128RRR_MASKZ,
3452            op0.as_operand(),
3453            op1.as_operand(),
3454            op2.as_operand(),
3455            &NOREG,
3456        );
3457    }
3458}
3459
3460impl<'a> VpshrdvdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
3461    fn vpshrdvd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
3462        self.emit(
3463            VPSHRDVD128RRM_MASKZ,
3464            op0.as_operand(),
3465            op1.as_operand(),
3466            op2.as_operand(),
3467            &NOREG,
3468        );
3469    }
3470}
3471
3472impl<'a> VpshrdvdMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
3473    fn vpshrdvd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
3474        self.emit(
3475            VPSHRDVD256RRR_MASKZ,
3476            op0.as_operand(),
3477            op1.as_operand(),
3478            op2.as_operand(),
3479            &NOREG,
3480        );
3481    }
3482}
3483
3484impl<'a> VpshrdvdMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
3485    fn vpshrdvd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
3486        self.emit(
3487            VPSHRDVD256RRM_MASKZ,
3488            op0.as_operand(),
3489            op1.as_operand(),
3490            op2.as_operand(),
3491            &NOREG,
3492        );
3493    }
3494}
3495
3496impl<'a> VpshrdvdMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
3497    fn vpshrdvd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
3498        self.emit(
3499            VPSHRDVD512RRR_MASKZ,
3500            op0.as_operand(),
3501            op1.as_operand(),
3502            op2.as_operand(),
3503            &NOREG,
3504        );
3505    }
3506}
3507
3508impl<'a> VpshrdvdMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
3509    fn vpshrdvd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
3510        self.emit(
3511            VPSHRDVD512RRM_MASKZ,
3512            op0.as_operand(),
3513            op1.as_operand(),
3514            op2.as_operand(),
3515            &NOREG,
3516        );
3517    }
3518}
3519
3520/// `VPSHRDVQ`.
3521///
3522/// Supported operand variants:
3523///
3524/// ```text
3525/// +---+---------------+
3526/// | # | Operands      |
3527/// +---+---------------+
3528/// | 1 | Xmm, Xmm, Mem |
3529/// | 2 | Xmm, Xmm, Xmm |
3530/// | 3 | Ymm, Ymm, Mem |
3531/// | 4 | Ymm, Ymm, Ymm |
3532/// | 5 | Zmm, Zmm, Mem |
3533/// | 6 | Zmm, Zmm, Zmm |
3534/// +---+---------------+
3535/// ```
3536pub trait VpshrdvqEmitter<A, B, C> {
3537    fn vpshrdvq(&mut self, op0: A, op1: B, op2: C);
3538}
3539
3540impl<'a> VpshrdvqEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
3541    fn vpshrdvq(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
3542        self.emit(
3543            VPSHRDVQ128RRR,
3544            op0.as_operand(),
3545            op1.as_operand(),
3546            op2.as_operand(),
3547            &NOREG,
3548        );
3549    }
3550}
3551
3552impl<'a> VpshrdvqEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
3553    fn vpshrdvq(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
3554        self.emit(
3555            VPSHRDVQ128RRM,
3556            op0.as_operand(),
3557            op1.as_operand(),
3558            op2.as_operand(),
3559            &NOREG,
3560        );
3561    }
3562}
3563
3564impl<'a> VpshrdvqEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
3565    fn vpshrdvq(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
3566        self.emit(
3567            VPSHRDVQ256RRR,
3568            op0.as_operand(),
3569            op1.as_operand(),
3570            op2.as_operand(),
3571            &NOREG,
3572        );
3573    }
3574}
3575
3576impl<'a> VpshrdvqEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
3577    fn vpshrdvq(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
3578        self.emit(
3579            VPSHRDVQ256RRM,
3580            op0.as_operand(),
3581            op1.as_operand(),
3582            op2.as_operand(),
3583            &NOREG,
3584        );
3585    }
3586}
3587
3588impl<'a> VpshrdvqEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
3589    fn vpshrdvq(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
3590        self.emit(
3591            VPSHRDVQ512RRR,
3592            op0.as_operand(),
3593            op1.as_operand(),
3594            op2.as_operand(),
3595            &NOREG,
3596        );
3597    }
3598}
3599
3600impl<'a> VpshrdvqEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
3601    fn vpshrdvq(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
3602        self.emit(
3603            VPSHRDVQ512RRM,
3604            op0.as_operand(),
3605            op1.as_operand(),
3606            op2.as_operand(),
3607            &NOREG,
3608        );
3609    }
3610}
3611
3612/// `VPSHRDVQ_MASK`.
3613///
3614/// Supported operand variants:
3615///
3616/// ```text
3617/// +---+---------------+
3618/// | # | Operands      |
3619/// +---+---------------+
3620/// | 1 | Xmm, Xmm, Mem |
3621/// | 2 | Xmm, Xmm, Xmm |
3622/// | 3 | Ymm, Ymm, Mem |
3623/// | 4 | Ymm, Ymm, Ymm |
3624/// | 5 | Zmm, Zmm, Mem |
3625/// | 6 | Zmm, Zmm, Zmm |
3626/// +---+---------------+
3627/// ```
3628pub trait VpshrdvqMaskEmitter<A, B, C> {
3629    fn vpshrdvq_mask(&mut self, op0: A, op1: B, op2: C);
3630}
3631
3632impl<'a> VpshrdvqMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
3633    fn vpshrdvq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
3634        self.emit(
3635            VPSHRDVQ128RRR_MASK,
3636            op0.as_operand(),
3637            op1.as_operand(),
3638            op2.as_operand(),
3639            &NOREG,
3640        );
3641    }
3642}
3643
3644impl<'a> VpshrdvqMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
3645    fn vpshrdvq_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
3646        self.emit(
3647            VPSHRDVQ128RRM_MASK,
3648            op0.as_operand(),
3649            op1.as_operand(),
3650            op2.as_operand(),
3651            &NOREG,
3652        );
3653    }
3654}
3655
3656impl<'a> VpshrdvqMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
3657    fn vpshrdvq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
3658        self.emit(
3659            VPSHRDVQ256RRR_MASK,
3660            op0.as_operand(),
3661            op1.as_operand(),
3662            op2.as_operand(),
3663            &NOREG,
3664        );
3665    }
3666}
3667
3668impl<'a> VpshrdvqMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
3669    fn vpshrdvq_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
3670        self.emit(
3671            VPSHRDVQ256RRM_MASK,
3672            op0.as_operand(),
3673            op1.as_operand(),
3674            op2.as_operand(),
3675            &NOREG,
3676        );
3677    }
3678}
3679
3680impl<'a> VpshrdvqMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
3681    fn vpshrdvq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
3682        self.emit(
3683            VPSHRDVQ512RRR_MASK,
3684            op0.as_operand(),
3685            op1.as_operand(),
3686            op2.as_operand(),
3687            &NOREG,
3688        );
3689    }
3690}
3691
3692impl<'a> VpshrdvqMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
3693    fn vpshrdvq_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
3694        self.emit(
3695            VPSHRDVQ512RRM_MASK,
3696            op0.as_operand(),
3697            op1.as_operand(),
3698            op2.as_operand(),
3699            &NOREG,
3700        );
3701    }
3702}
3703
3704/// `VPSHRDVQ_MASKZ`.
3705///
3706/// Supported operand variants:
3707///
3708/// ```text
3709/// +---+---------------+
3710/// | # | Operands      |
3711/// +---+---------------+
3712/// | 1 | Xmm, Xmm, Mem |
3713/// | 2 | Xmm, Xmm, Xmm |
3714/// | 3 | Ymm, Ymm, Mem |
3715/// | 4 | Ymm, Ymm, Ymm |
3716/// | 5 | Zmm, Zmm, Mem |
3717/// | 6 | Zmm, Zmm, Zmm |
3718/// +---+---------------+
3719/// ```
3720pub trait VpshrdvqMaskzEmitter<A, B, C> {
3721    fn vpshrdvq_maskz(&mut self, op0: A, op1: B, op2: C);
3722}
3723
3724impl<'a> VpshrdvqMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
3725    fn vpshrdvq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
3726        self.emit(
3727            VPSHRDVQ128RRR_MASKZ,
3728            op0.as_operand(),
3729            op1.as_operand(),
3730            op2.as_operand(),
3731            &NOREG,
3732        );
3733    }
3734}
3735
3736impl<'a> VpshrdvqMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
3737    fn vpshrdvq_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
3738        self.emit(
3739            VPSHRDVQ128RRM_MASKZ,
3740            op0.as_operand(),
3741            op1.as_operand(),
3742            op2.as_operand(),
3743            &NOREG,
3744        );
3745    }
3746}
3747
3748impl<'a> VpshrdvqMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
3749    fn vpshrdvq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
3750        self.emit(
3751            VPSHRDVQ256RRR_MASKZ,
3752            op0.as_operand(),
3753            op1.as_operand(),
3754            op2.as_operand(),
3755            &NOREG,
3756        );
3757    }
3758}
3759
3760impl<'a> VpshrdvqMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
3761    fn vpshrdvq_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
3762        self.emit(
3763            VPSHRDVQ256RRM_MASKZ,
3764            op0.as_operand(),
3765            op1.as_operand(),
3766            op2.as_operand(),
3767            &NOREG,
3768        );
3769    }
3770}
3771
3772impl<'a> VpshrdvqMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
3773    fn vpshrdvq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
3774        self.emit(
3775            VPSHRDVQ512RRR_MASKZ,
3776            op0.as_operand(),
3777            op1.as_operand(),
3778            op2.as_operand(),
3779            &NOREG,
3780        );
3781    }
3782}
3783
3784impl<'a> VpshrdvqMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
3785    fn vpshrdvq_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
3786        self.emit(
3787            VPSHRDVQ512RRM_MASKZ,
3788            op0.as_operand(),
3789            op1.as_operand(),
3790            op2.as_operand(),
3791            &NOREG,
3792        );
3793    }
3794}
3795
3796/// `VPSHRDVW`.
3797///
3798/// Supported operand variants:
3799///
3800/// ```text
3801/// +---+---------------+
3802/// | # | Operands      |
3803/// +---+---------------+
3804/// | 1 | Xmm, Xmm, Mem |
3805/// | 2 | Xmm, Xmm, Xmm |
3806/// | 3 | Ymm, Ymm, Mem |
3807/// | 4 | Ymm, Ymm, Ymm |
3808/// | 5 | Zmm, Zmm, Mem |
3809/// | 6 | Zmm, Zmm, Zmm |
3810/// +---+---------------+
3811/// ```
3812pub trait VpshrdvwEmitter<A, B, C> {
3813    fn vpshrdvw(&mut self, op0: A, op1: B, op2: C);
3814}
3815
3816impl<'a> VpshrdvwEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
3817    fn vpshrdvw(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
3818        self.emit(
3819            VPSHRDVW128RRR,
3820            op0.as_operand(),
3821            op1.as_operand(),
3822            op2.as_operand(),
3823            &NOREG,
3824        );
3825    }
3826}
3827
3828impl<'a> VpshrdvwEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
3829    fn vpshrdvw(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
3830        self.emit(
3831            VPSHRDVW128RRM,
3832            op0.as_operand(),
3833            op1.as_operand(),
3834            op2.as_operand(),
3835            &NOREG,
3836        );
3837    }
3838}
3839
3840impl<'a> VpshrdvwEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
3841    fn vpshrdvw(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
3842        self.emit(
3843            VPSHRDVW256RRR,
3844            op0.as_operand(),
3845            op1.as_operand(),
3846            op2.as_operand(),
3847            &NOREG,
3848        );
3849    }
3850}
3851
3852impl<'a> VpshrdvwEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
3853    fn vpshrdvw(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
3854        self.emit(
3855            VPSHRDVW256RRM,
3856            op0.as_operand(),
3857            op1.as_operand(),
3858            op2.as_operand(),
3859            &NOREG,
3860        );
3861    }
3862}
3863
3864impl<'a> VpshrdvwEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
3865    fn vpshrdvw(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
3866        self.emit(
3867            VPSHRDVW512RRR,
3868            op0.as_operand(),
3869            op1.as_operand(),
3870            op2.as_operand(),
3871            &NOREG,
3872        );
3873    }
3874}
3875
3876impl<'a> VpshrdvwEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
3877    fn vpshrdvw(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
3878        self.emit(
3879            VPSHRDVW512RRM,
3880            op0.as_operand(),
3881            op1.as_operand(),
3882            op2.as_operand(),
3883            &NOREG,
3884        );
3885    }
3886}
3887
3888/// `VPSHRDVW_MASK`.
3889///
3890/// Supported operand variants:
3891///
3892/// ```text
3893/// +---+---------------+
3894/// | # | Operands      |
3895/// +---+---------------+
3896/// | 1 | Xmm, Xmm, Mem |
3897/// | 2 | Xmm, Xmm, Xmm |
3898/// | 3 | Ymm, Ymm, Mem |
3899/// | 4 | Ymm, Ymm, Ymm |
3900/// | 5 | Zmm, Zmm, Mem |
3901/// | 6 | Zmm, Zmm, Zmm |
3902/// +---+---------------+
3903/// ```
3904pub trait VpshrdvwMaskEmitter<A, B, C> {
3905    fn vpshrdvw_mask(&mut self, op0: A, op1: B, op2: C);
3906}
3907
3908impl<'a> VpshrdvwMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
3909    fn vpshrdvw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
3910        self.emit(
3911            VPSHRDVW128RRR_MASK,
3912            op0.as_operand(),
3913            op1.as_operand(),
3914            op2.as_operand(),
3915            &NOREG,
3916        );
3917    }
3918}
3919
3920impl<'a> VpshrdvwMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
3921    fn vpshrdvw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
3922        self.emit(
3923            VPSHRDVW128RRM_MASK,
3924            op0.as_operand(),
3925            op1.as_operand(),
3926            op2.as_operand(),
3927            &NOREG,
3928        );
3929    }
3930}
3931
3932impl<'a> VpshrdvwMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
3933    fn vpshrdvw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
3934        self.emit(
3935            VPSHRDVW256RRR_MASK,
3936            op0.as_operand(),
3937            op1.as_operand(),
3938            op2.as_operand(),
3939            &NOREG,
3940        );
3941    }
3942}
3943
3944impl<'a> VpshrdvwMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
3945    fn vpshrdvw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
3946        self.emit(
3947            VPSHRDVW256RRM_MASK,
3948            op0.as_operand(),
3949            op1.as_operand(),
3950            op2.as_operand(),
3951            &NOREG,
3952        );
3953    }
3954}
3955
3956impl<'a> VpshrdvwMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
3957    fn vpshrdvw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
3958        self.emit(
3959            VPSHRDVW512RRR_MASK,
3960            op0.as_operand(),
3961            op1.as_operand(),
3962            op2.as_operand(),
3963            &NOREG,
3964        );
3965    }
3966}
3967
3968impl<'a> VpshrdvwMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
3969    fn vpshrdvw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
3970        self.emit(
3971            VPSHRDVW512RRM_MASK,
3972            op0.as_operand(),
3973            op1.as_operand(),
3974            op2.as_operand(),
3975            &NOREG,
3976        );
3977    }
3978}
3979
3980/// `VPSHRDVW_MASKZ`.
3981///
3982/// Supported operand variants:
3983///
3984/// ```text
3985/// +---+---------------+
3986/// | # | Operands      |
3987/// +---+---------------+
3988/// | 1 | Xmm, Xmm, Mem |
3989/// | 2 | Xmm, Xmm, Xmm |
3990/// | 3 | Ymm, Ymm, Mem |
3991/// | 4 | Ymm, Ymm, Ymm |
3992/// | 5 | Zmm, Zmm, Mem |
3993/// | 6 | Zmm, Zmm, Zmm |
3994/// +---+---------------+
3995/// ```
3996pub trait VpshrdvwMaskzEmitter<A, B, C> {
3997    fn vpshrdvw_maskz(&mut self, op0: A, op1: B, op2: C);
3998}
3999
4000impl<'a> VpshrdvwMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
4001    fn vpshrdvw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
4002        self.emit(
4003            VPSHRDVW128RRR_MASKZ,
4004            op0.as_operand(),
4005            op1.as_operand(),
4006            op2.as_operand(),
4007            &NOREG,
4008        );
4009    }
4010}
4011
4012impl<'a> VpshrdvwMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
4013    fn vpshrdvw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
4014        self.emit(
4015            VPSHRDVW128RRM_MASKZ,
4016            op0.as_operand(),
4017            op1.as_operand(),
4018            op2.as_operand(),
4019            &NOREG,
4020        );
4021    }
4022}
4023
4024impl<'a> VpshrdvwMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
4025    fn vpshrdvw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
4026        self.emit(
4027            VPSHRDVW256RRR_MASKZ,
4028            op0.as_operand(),
4029            op1.as_operand(),
4030            op2.as_operand(),
4031            &NOREG,
4032        );
4033    }
4034}
4035
4036impl<'a> VpshrdvwMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
4037    fn vpshrdvw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
4038        self.emit(
4039            VPSHRDVW256RRM_MASKZ,
4040            op0.as_operand(),
4041            op1.as_operand(),
4042            op2.as_operand(),
4043            &NOREG,
4044        );
4045    }
4046}
4047
4048impl<'a> VpshrdvwMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
4049    fn vpshrdvw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
4050        self.emit(
4051            VPSHRDVW512RRR_MASKZ,
4052            op0.as_operand(),
4053            op1.as_operand(),
4054            op2.as_operand(),
4055            &NOREG,
4056        );
4057    }
4058}
4059
4060impl<'a> VpshrdvwMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
4061    fn vpshrdvw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
4062        self.emit(
4063            VPSHRDVW512RRM_MASKZ,
4064            op0.as_operand(),
4065            op1.as_operand(),
4066            op2.as_operand(),
4067            &NOREG,
4068        );
4069    }
4070}
4071
4072/// `VPSHRDW`.
4073///
4074/// Supported operand variants:
4075///
4076/// ```text
4077/// +---+--------------------+
4078/// | # | Operands           |
4079/// +---+--------------------+
4080/// | 1 | Xmm, Xmm, Mem, Imm |
4081/// | 2 | Xmm, Xmm, Xmm, Imm |
4082/// | 3 | Ymm, Ymm, Mem, Imm |
4083/// | 4 | Ymm, Ymm, Ymm, Imm |
4084/// | 5 | Zmm, Zmm, Mem, Imm |
4085/// | 6 | Zmm, Zmm, Zmm, Imm |
4086/// +---+--------------------+
4087/// ```
4088pub trait VpshrdwEmitter<A, B, C, D> {
4089    fn vpshrdw(&mut self, op0: A, op1: B, op2: C, op3: D);
4090}
4091
4092impl<'a> VpshrdwEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
4093    fn vpshrdw(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
4094        self.emit(
4095            VPSHRDW128RRRI,
4096            op0.as_operand(),
4097            op1.as_operand(),
4098            op2.as_operand(),
4099            op3.as_operand(),
4100        );
4101    }
4102}
4103
4104impl<'a> VpshrdwEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
4105    fn vpshrdw(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
4106        self.emit(
4107            VPSHRDW128RRMI,
4108            op0.as_operand(),
4109            op1.as_operand(),
4110            op2.as_operand(),
4111            op3.as_operand(),
4112        );
4113    }
4114}
4115
4116impl<'a> VpshrdwEmitter<Ymm, Ymm, Ymm, Imm> for Assembler<'a> {
4117    fn vpshrdw(&mut self, op0: Ymm, op1: Ymm, op2: Ymm, op3: Imm) {
4118        self.emit(
4119            VPSHRDW256RRRI,
4120            op0.as_operand(),
4121            op1.as_operand(),
4122            op2.as_operand(),
4123            op3.as_operand(),
4124        );
4125    }
4126}
4127
4128impl<'a> VpshrdwEmitter<Ymm, Ymm, Mem, Imm> for Assembler<'a> {
4129    fn vpshrdw(&mut self, op0: Ymm, op1: Ymm, op2: Mem, op3: Imm) {
4130        self.emit(
4131            VPSHRDW256RRMI,
4132            op0.as_operand(),
4133            op1.as_operand(),
4134            op2.as_operand(),
4135            op3.as_operand(),
4136        );
4137    }
4138}
4139
4140impl<'a> VpshrdwEmitter<Zmm, Zmm, Zmm, Imm> for Assembler<'a> {
4141    fn vpshrdw(&mut self, op0: Zmm, op1: Zmm, op2: Zmm, op3: Imm) {
4142        self.emit(
4143            VPSHRDW512RRRI,
4144            op0.as_operand(),
4145            op1.as_operand(),
4146            op2.as_operand(),
4147            op3.as_operand(),
4148        );
4149    }
4150}
4151
4152impl<'a> VpshrdwEmitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
4153    fn vpshrdw(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
4154        self.emit(
4155            VPSHRDW512RRMI,
4156            op0.as_operand(),
4157            op1.as_operand(),
4158            op2.as_operand(),
4159            op3.as_operand(),
4160        );
4161    }
4162}
4163
4164/// `VPSHRDW_MASK`.
4165///
4166/// Supported operand variants:
4167///
4168/// ```text
4169/// +---+--------------------+
4170/// | # | Operands           |
4171/// +---+--------------------+
4172/// | 1 | Xmm, Xmm, Mem, Imm |
4173/// | 2 | Xmm, Xmm, Xmm, Imm |
4174/// | 3 | Ymm, Ymm, Mem, Imm |
4175/// | 4 | Ymm, Ymm, Ymm, Imm |
4176/// | 5 | Zmm, Zmm, Mem, Imm |
4177/// | 6 | Zmm, Zmm, Zmm, Imm |
4178/// +---+--------------------+
4179/// ```
4180pub trait VpshrdwMaskEmitter<A, B, C, D> {
4181    fn vpshrdw_mask(&mut self, op0: A, op1: B, op2: C, op3: D);
4182}
4183
4184impl<'a> VpshrdwMaskEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
4185    fn vpshrdw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
4186        self.emit(
4187            VPSHRDW128RRRI_MASK,
4188            op0.as_operand(),
4189            op1.as_operand(),
4190            op2.as_operand(),
4191            op3.as_operand(),
4192        );
4193    }
4194}
4195
4196impl<'a> VpshrdwMaskEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
4197    fn vpshrdw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
4198        self.emit(
4199            VPSHRDW128RRMI_MASK,
4200            op0.as_operand(),
4201            op1.as_operand(),
4202            op2.as_operand(),
4203            op3.as_operand(),
4204        );
4205    }
4206}
4207
4208impl<'a> VpshrdwMaskEmitter<Ymm, Ymm, Ymm, Imm> for Assembler<'a> {
4209    fn vpshrdw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm, op3: Imm) {
4210        self.emit(
4211            VPSHRDW256RRRI_MASK,
4212            op0.as_operand(),
4213            op1.as_operand(),
4214            op2.as_operand(),
4215            op3.as_operand(),
4216        );
4217    }
4218}
4219
4220impl<'a> VpshrdwMaskEmitter<Ymm, Ymm, Mem, Imm> for Assembler<'a> {
4221    fn vpshrdw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem, op3: Imm) {
4222        self.emit(
4223            VPSHRDW256RRMI_MASK,
4224            op0.as_operand(),
4225            op1.as_operand(),
4226            op2.as_operand(),
4227            op3.as_operand(),
4228        );
4229    }
4230}
4231
4232impl<'a> VpshrdwMaskEmitter<Zmm, Zmm, Zmm, Imm> for Assembler<'a> {
4233    fn vpshrdw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm, op3: Imm) {
4234        self.emit(
4235            VPSHRDW512RRRI_MASK,
4236            op0.as_operand(),
4237            op1.as_operand(),
4238            op2.as_operand(),
4239            op3.as_operand(),
4240        );
4241    }
4242}
4243
4244impl<'a> VpshrdwMaskEmitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
4245    fn vpshrdw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
4246        self.emit(
4247            VPSHRDW512RRMI_MASK,
4248            op0.as_operand(),
4249            op1.as_operand(),
4250            op2.as_operand(),
4251            op3.as_operand(),
4252        );
4253    }
4254}
4255
4256/// `VPSHRDW_MASKZ`.
4257///
4258/// Supported operand variants:
4259///
4260/// ```text
4261/// +---+--------------------+
4262/// | # | Operands           |
4263/// +---+--------------------+
4264/// | 1 | Xmm, Xmm, Mem, Imm |
4265/// | 2 | Xmm, Xmm, Xmm, Imm |
4266/// | 3 | Ymm, Ymm, Mem, Imm |
4267/// | 4 | Ymm, Ymm, Ymm, Imm |
4268/// | 5 | Zmm, Zmm, Mem, Imm |
4269/// | 6 | Zmm, Zmm, Zmm, Imm |
4270/// +---+--------------------+
4271/// ```
4272pub trait VpshrdwMaskzEmitter<A, B, C, D> {
4273    fn vpshrdw_maskz(&mut self, op0: A, op1: B, op2: C, op3: D);
4274}
4275
4276impl<'a> VpshrdwMaskzEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
4277    fn vpshrdw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
4278        self.emit(
4279            VPSHRDW128RRRI_MASKZ,
4280            op0.as_operand(),
4281            op1.as_operand(),
4282            op2.as_operand(),
4283            op3.as_operand(),
4284        );
4285    }
4286}
4287
4288impl<'a> VpshrdwMaskzEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
4289    fn vpshrdw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
4290        self.emit(
4291            VPSHRDW128RRMI_MASKZ,
4292            op0.as_operand(),
4293            op1.as_operand(),
4294            op2.as_operand(),
4295            op3.as_operand(),
4296        );
4297    }
4298}
4299
4300impl<'a> VpshrdwMaskzEmitter<Ymm, Ymm, Ymm, Imm> for Assembler<'a> {
4301    fn vpshrdw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm, op3: Imm) {
4302        self.emit(
4303            VPSHRDW256RRRI_MASKZ,
4304            op0.as_operand(),
4305            op1.as_operand(),
4306            op2.as_operand(),
4307            op3.as_operand(),
4308        );
4309    }
4310}
4311
4312impl<'a> VpshrdwMaskzEmitter<Ymm, Ymm, Mem, Imm> for Assembler<'a> {
4313    fn vpshrdw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem, op3: Imm) {
4314        self.emit(
4315            VPSHRDW256RRMI_MASKZ,
4316            op0.as_operand(),
4317            op1.as_operand(),
4318            op2.as_operand(),
4319            op3.as_operand(),
4320        );
4321    }
4322}
4323
4324impl<'a> VpshrdwMaskzEmitter<Zmm, Zmm, Zmm, Imm> for Assembler<'a> {
4325    fn vpshrdw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm, op3: Imm) {
4326        self.emit(
4327            VPSHRDW512RRRI_MASKZ,
4328            op0.as_operand(),
4329            op1.as_operand(),
4330            op2.as_operand(),
4331            op3.as_operand(),
4332        );
4333    }
4334}
4335
4336impl<'a> VpshrdwMaskzEmitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
4337    fn vpshrdw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
4338        self.emit(
4339            VPSHRDW512RRMI_MASKZ,
4340            op0.as_operand(),
4341            op1.as_operand(),
4342            op2.as_operand(),
4343            op3.as_operand(),
4344        );
4345    }
4346}
4347
4348impl<'a> Assembler<'a> {
4349    /// `VPCOMPRESSB`.
4350    ///
4351    /// Supported operand variants:
4352    ///
4353    /// ```text
4354    /// +---+----------+
4355    /// | # | Operands |
4356    /// +---+----------+
4357    /// | 1 | Mem, Xmm |
4358    /// | 2 | Mem, Ymm |
4359    /// | 3 | Mem, Zmm |
4360    /// | 4 | Xmm, Xmm |
4361    /// | 5 | Ymm, Ymm |
4362    /// | 6 | Zmm, Zmm |
4363    /// +---+----------+
4364    /// ```
4365    #[inline]
4366    pub fn vpcompressb<A, B>(&mut self, op0: A, op1: B)
4367    where
4368        Assembler<'a>: VpcompressbEmitter<A, B>,
4369    {
4370        <Self as VpcompressbEmitter<A, B>>::vpcompressb(self, op0, op1);
4371    }
4372    /// `VPCOMPRESSB_MASK`.
4373    ///
4374    /// Supported operand variants:
4375    ///
4376    /// ```text
4377    /// +---+----------+
4378    /// | # | Operands |
4379    /// +---+----------+
4380    /// | 1 | Mem, Xmm |
4381    /// | 2 | Mem, Ymm |
4382    /// | 3 | Mem, Zmm |
4383    /// | 4 | Xmm, Xmm |
4384    /// | 5 | Ymm, Ymm |
4385    /// | 6 | Zmm, Zmm |
4386    /// +---+----------+
4387    /// ```
4388    #[inline]
4389    pub fn vpcompressb_mask<A, B>(&mut self, op0: A, op1: B)
4390    where
4391        Assembler<'a>: VpcompressbMaskEmitter<A, B>,
4392    {
4393        <Self as VpcompressbMaskEmitter<A, B>>::vpcompressb_mask(self, op0, op1);
4394    }
4395    /// `VPCOMPRESSB_MASKZ`.
4396    ///
4397    /// Supported operand variants:
4398    ///
4399    /// ```text
4400    /// +---+----------+
4401    /// | # | Operands |
4402    /// +---+----------+
4403    /// | 1 | Xmm, Xmm |
4404    /// | 2 | Ymm, Ymm |
4405    /// | 3 | Zmm, Zmm |
4406    /// +---+----------+
4407    /// ```
4408    #[inline]
4409    pub fn vpcompressb_maskz<A, B>(&mut self, op0: A, op1: B)
4410    where
4411        Assembler<'a>: VpcompressbMaskzEmitter<A, B>,
4412    {
4413        <Self as VpcompressbMaskzEmitter<A, B>>::vpcompressb_maskz(self, op0, op1);
4414    }
4415    /// `VPCOMPRESSW`.
4416    ///
4417    /// Supported operand variants:
4418    ///
4419    /// ```text
4420    /// +---+----------+
4421    /// | # | Operands |
4422    /// +---+----------+
4423    /// | 1 | Mem, Xmm |
4424    /// | 2 | Mem, Ymm |
4425    /// | 3 | Mem, Zmm |
4426    /// | 4 | Xmm, Xmm |
4427    /// | 5 | Ymm, Ymm |
4428    /// | 6 | Zmm, Zmm |
4429    /// +---+----------+
4430    /// ```
4431    #[inline]
4432    pub fn vpcompressw<A, B>(&mut self, op0: A, op1: B)
4433    where
4434        Assembler<'a>: VpcompresswEmitter<A, B>,
4435    {
4436        <Self as VpcompresswEmitter<A, B>>::vpcompressw(self, op0, op1);
4437    }
4438    /// `VPCOMPRESSW_MASK`.
4439    ///
4440    /// Supported operand variants:
4441    ///
4442    /// ```text
4443    /// +---+----------+
4444    /// | # | Operands |
4445    /// +---+----------+
4446    /// | 1 | Mem, Xmm |
4447    /// | 2 | Mem, Ymm |
4448    /// | 3 | Mem, Zmm |
4449    /// | 4 | Xmm, Xmm |
4450    /// | 5 | Ymm, Ymm |
4451    /// | 6 | Zmm, Zmm |
4452    /// +---+----------+
4453    /// ```
4454    #[inline]
4455    pub fn vpcompressw_mask<A, B>(&mut self, op0: A, op1: B)
4456    where
4457        Assembler<'a>: VpcompresswMaskEmitter<A, B>,
4458    {
4459        <Self as VpcompresswMaskEmitter<A, B>>::vpcompressw_mask(self, op0, op1);
4460    }
4461    /// `VPCOMPRESSW_MASKZ`.
4462    ///
4463    /// Supported operand variants:
4464    ///
4465    /// ```text
4466    /// +---+----------+
4467    /// | # | Operands |
4468    /// +---+----------+
4469    /// | 1 | Xmm, Xmm |
4470    /// | 2 | Ymm, Ymm |
4471    /// | 3 | Zmm, Zmm |
4472    /// +---+----------+
4473    /// ```
4474    #[inline]
4475    pub fn vpcompressw_maskz<A, B>(&mut self, op0: A, op1: B)
4476    where
4477        Assembler<'a>: VpcompresswMaskzEmitter<A, B>,
4478    {
4479        <Self as VpcompresswMaskzEmitter<A, B>>::vpcompressw_maskz(self, op0, op1);
4480    }
4481    /// `VPEXPANDB`.
4482    ///
4483    /// Supported operand variants:
4484    ///
4485    /// ```text
4486    /// +---+----------+
4487    /// | # | Operands |
4488    /// +---+----------+
4489    /// | 1 | Xmm, Mem |
4490    /// | 2 | Xmm, Xmm |
4491    /// | 3 | Ymm, Mem |
4492    /// | 4 | Ymm, Ymm |
4493    /// | 5 | Zmm, Mem |
4494    /// | 6 | Zmm, Zmm |
4495    /// +---+----------+
4496    /// ```
4497    #[inline]
4498    pub fn vpexpandb<A, B>(&mut self, op0: A, op1: B)
4499    where
4500        Assembler<'a>: VpexpandbEmitter<A, B>,
4501    {
4502        <Self as VpexpandbEmitter<A, B>>::vpexpandb(self, op0, op1);
4503    }
4504    /// `VPEXPANDB_MASK`.
4505    ///
4506    /// Supported operand variants:
4507    ///
4508    /// ```text
4509    /// +---+----------+
4510    /// | # | Operands |
4511    /// +---+----------+
4512    /// | 1 | Xmm, Mem |
4513    /// | 2 | Xmm, Xmm |
4514    /// | 3 | Ymm, Mem |
4515    /// | 4 | Ymm, Ymm |
4516    /// | 5 | Zmm, Mem |
4517    /// | 6 | Zmm, Zmm |
4518    /// +---+----------+
4519    /// ```
4520    #[inline]
4521    pub fn vpexpandb_mask<A, B>(&mut self, op0: A, op1: B)
4522    where
4523        Assembler<'a>: VpexpandbMaskEmitter<A, B>,
4524    {
4525        <Self as VpexpandbMaskEmitter<A, B>>::vpexpandb_mask(self, op0, op1);
4526    }
4527    /// `VPEXPANDB_MASKZ`.
4528    ///
4529    /// Supported operand variants:
4530    ///
4531    /// ```text
4532    /// +---+----------+
4533    /// | # | Operands |
4534    /// +---+----------+
4535    /// | 1 | Xmm, Mem |
4536    /// | 2 | Xmm, Xmm |
4537    /// | 3 | Ymm, Mem |
4538    /// | 4 | Ymm, Ymm |
4539    /// | 5 | Zmm, Mem |
4540    /// | 6 | Zmm, Zmm |
4541    /// +---+----------+
4542    /// ```
4543    #[inline]
4544    pub fn vpexpandb_maskz<A, B>(&mut self, op0: A, op1: B)
4545    where
4546        Assembler<'a>: VpexpandbMaskzEmitter<A, B>,
4547    {
4548        <Self as VpexpandbMaskzEmitter<A, B>>::vpexpandb_maskz(self, op0, op1);
4549    }
4550    /// `VPEXPANDW`.
4551    ///
4552    /// Supported operand variants:
4553    ///
4554    /// ```text
4555    /// +---+----------+
4556    /// | # | Operands |
4557    /// +---+----------+
4558    /// | 1 | Xmm, Mem |
4559    /// | 2 | Xmm, Xmm |
4560    /// | 3 | Ymm, Mem |
4561    /// | 4 | Ymm, Ymm |
4562    /// | 5 | Zmm, Mem |
4563    /// | 6 | Zmm, Zmm |
4564    /// +---+----------+
4565    /// ```
4566    #[inline]
4567    pub fn vpexpandw<A, B>(&mut self, op0: A, op1: B)
4568    where
4569        Assembler<'a>: VpexpandwEmitter<A, B>,
4570    {
4571        <Self as VpexpandwEmitter<A, B>>::vpexpandw(self, op0, op1);
4572    }
4573    /// `VPEXPANDW_MASK`.
4574    ///
4575    /// Supported operand variants:
4576    ///
4577    /// ```text
4578    /// +---+----------+
4579    /// | # | Operands |
4580    /// +---+----------+
4581    /// | 1 | Xmm, Mem |
4582    /// | 2 | Xmm, Xmm |
4583    /// | 3 | Ymm, Mem |
4584    /// | 4 | Ymm, Ymm |
4585    /// | 5 | Zmm, Mem |
4586    /// | 6 | Zmm, Zmm |
4587    /// +---+----------+
4588    /// ```
4589    #[inline]
4590    pub fn vpexpandw_mask<A, B>(&mut self, op0: A, op1: B)
4591    where
4592        Assembler<'a>: VpexpandwMaskEmitter<A, B>,
4593    {
4594        <Self as VpexpandwMaskEmitter<A, B>>::vpexpandw_mask(self, op0, op1);
4595    }
4596    /// `VPEXPANDW_MASKZ`.
4597    ///
4598    /// Supported operand variants:
4599    ///
4600    /// ```text
4601    /// +---+----------+
4602    /// | # | Operands |
4603    /// +---+----------+
4604    /// | 1 | Xmm, Mem |
4605    /// | 2 | Xmm, Xmm |
4606    /// | 3 | Ymm, Mem |
4607    /// | 4 | Ymm, Ymm |
4608    /// | 5 | Zmm, Mem |
4609    /// | 6 | Zmm, Zmm |
4610    /// +---+----------+
4611    /// ```
4612    #[inline]
4613    pub fn vpexpandw_maskz<A, B>(&mut self, op0: A, op1: B)
4614    where
4615        Assembler<'a>: VpexpandwMaskzEmitter<A, B>,
4616    {
4617        <Self as VpexpandwMaskzEmitter<A, B>>::vpexpandw_maskz(self, op0, op1);
4618    }
4619    /// `VPSHLDD`.
4620    ///
4621    /// Supported operand variants:
4622    ///
4623    /// ```text
4624    /// +---+--------------------+
4625    /// | # | Operands           |
4626    /// +---+--------------------+
4627    /// | 1 | Xmm, Xmm, Mem, Imm |
4628    /// | 2 | Xmm, Xmm, Xmm, Imm |
4629    /// | 3 | Ymm, Ymm, Mem, Imm |
4630    /// | 4 | Ymm, Ymm, Ymm, Imm |
4631    /// | 5 | Zmm, Zmm, Mem, Imm |
4632    /// | 6 | Zmm, Zmm, Zmm, Imm |
4633    /// +---+--------------------+
4634    /// ```
4635    #[inline]
4636    pub fn vpshldd<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
4637    where
4638        Assembler<'a>: VpshlddEmitter<A, B, C, D>,
4639    {
4640        <Self as VpshlddEmitter<A, B, C, D>>::vpshldd(self, op0, op1, op2, op3);
4641    }
4642    /// `VPSHLDD_MASK`.
4643    ///
4644    /// Supported operand variants:
4645    ///
4646    /// ```text
4647    /// +---+--------------------+
4648    /// | # | Operands           |
4649    /// +---+--------------------+
4650    /// | 1 | Xmm, Xmm, Mem, Imm |
4651    /// | 2 | Xmm, Xmm, Xmm, Imm |
4652    /// | 3 | Ymm, Ymm, Mem, Imm |
4653    /// | 4 | Ymm, Ymm, Ymm, Imm |
4654    /// | 5 | Zmm, Zmm, Mem, Imm |
4655    /// | 6 | Zmm, Zmm, Zmm, Imm |
4656    /// +---+--------------------+
4657    /// ```
4658    #[inline]
4659    pub fn vpshldd_mask<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
4660    where
4661        Assembler<'a>: VpshlddMaskEmitter<A, B, C, D>,
4662    {
4663        <Self as VpshlddMaskEmitter<A, B, C, D>>::vpshldd_mask(self, op0, op1, op2, op3);
4664    }
4665    /// `VPSHLDD_MASKZ`.
4666    ///
4667    /// Supported operand variants:
4668    ///
4669    /// ```text
4670    /// +---+--------------------+
4671    /// | # | Operands           |
4672    /// +---+--------------------+
4673    /// | 1 | Xmm, Xmm, Mem, Imm |
4674    /// | 2 | Xmm, Xmm, Xmm, Imm |
4675    /// | 3 | Ymm, Ymm, Mem, Imm |
4676    /// | 4 | Ymm, Ymm, Ymm, Imm |
4677    /// | 5 | Zmm, Zmm, Mem, Imm |
4678    /// | 6 | Zmm, Zmm, Zmm, Imm |
4679    /// +---+--------------------+
4680    /// ```
4681    #[inline]
4682    pub fn vpshldd_maskz<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
4683    where
4684        Assembler<'a>: VpshlddMaskzEmitter<A, B, C, D>,
4685    {
4686        <Self as VpshlddMaskzEmitter<A, B, C, D>>::vpshldd_maskz(self, op0, op1, op2, op3);
4687    }
4688    /// `VPSHLDQ`.
4689    ///
4690    /// Supported operand variants:
4691    ///
4692    /// ```text
4693    /// +---+--------------------+
4694    /// | # | Operands           |
4695    /// +---+--------------------+
4696    /// | 1 | Xmm, Xmm, Mem, Imm |
4697    /// | 2 | Xmm, Xmm, Xmm, Imm |
4698    /// | 3 | Ymm, Ymm, Mem, Imm |
4699    /// | 4 | Ymm, Ymm, Ymm, Imm |
4700    /// | 5 | Zmm, Zmm, Mem, Imm |
4701    /// | 6 | Zmm, Zmm, Zmm, Imm |
4702    /// +---+--------------------+
4703    /// ```
4704    #[inline]
4705    pub fn vpshldq<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
4706    where
4707        Assembler<'a>: VpshldqEmitter<A, B, C, D>,
4708    {
4709        <Self as VpshldqEmitter<A, B, C, D>>::vpshldq(self, op0, op1, op2, op3);
4710    }
4711    /// `VPSHLDQ_MASK`.
4712    ///
4713    /// Supported operand variants:
4714    ///
4715    /// ```text
4716    /// +---+--------------------+
4717    /// | # | Operands           |
4718    /// +---+--------------------+
4719    /// | 1 | Xmm, Xmm, Mem, Imm |
4720    /// | 2 | Xmm, Xmm, Xmm, Imm |
4721    /// | 3 | Ymm, Ymm, Mem, Imm |
4722    /// | 4 | Ymm, Ymm, Ymm, Imm |
4723    /// | 5 | Zmm, Zmm, Mem, Imm |
4724    /// | 6 | Zmm, Zmm, Zmm, Imm |
4725    /// +---+--------------------+
4726    /// ```
4727    #[inline]
4728    pub fn vpshldq_mask<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
4729    where
4730        Assembler<'a>: VpshldqMaskEmitter<A, B, C, D>,
4731    {
4732        <Self as VpshldqMaskEmitter<A, B, C, D>>::vpshldq_mask(self, op0, op1, op2, op3);
4733    }
4734    /// `VPSHLDQ_MASKZ`.
4735    ///
4736    /// Supported operand variants:
4737    ///
4738    /// ```text
4739    /// +---+--------------------+
4740    /// | # | Operands           |
4741    /// +---+--------------------+
4742    /// | 1 | Xmm, Xmm, Mem, Imm |
4743    /// | 2 | Xmm, Xmm, Xmm, Imm |
4744    /// | 3 | Ymm, Ymm, Mem, Imm |
4745    /// | 4 | Ymm, Ymm, Ymm, Imm |
4746    /// | 5 | Zmm, Zmm, Mem, Imm |
4747    /// | 6 | Zmm, Zmm, Zmm, Imm |
4748    /// +---+--------------------+
4749    /// ```
4750    #[inline]
4751    pub fn vpshldq_maskz<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
4752    where
4753        Assembler<'a>: VpshldqMaskzEmitter<A, B, C, D>,
4754    {
4755        <Self as VpshldqMaskzEmitter<A, B, C, D>>::vpshldq_maskz(self, op0, op1, op2, op3);
4756    }
4757    /// `VPSHLDVD`.
4758    ///
4759    /// Supported operand variants:
4760    ///
4761    /// ```text
4762    /// +---+---------------+
4763    /// | # | Operands      |
4764    /// +---+---------------+
4765    /// | 1 | Xmm, Xmm, Mem |
4766    /// | 2 | Xmm, Xmm, Xmm |
4767    /// | 3 | Ymm, Ymm, Mem |
4768    /// | 4 | Ymm, Ymm, Ymm |
4769    /// | 5 | Zmm, Zmm, Mem |
4770    /// | 6 | Zmm, Zmm, Zmm |
4771    /// +---+---------------+
4772    /// ```
4773    #[inline]
4774    pub fn vpshldvd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
4775    where
4776        Assembler<'a>: VpshldvdEmitter<A, B, C>,
4777    {
4778        <Self as VpshldvdEmitter<A, B, C>>::vpshldvd(self, op0, op1, op2);
4779    }
4780    /// `VPSHLDVD_MASK`.
4781    ///
4782    /// Supported operand variants:
4783    ///
4784    /// ```text
4785    /// +---+---------------+
4786    /// | # | Operands      |
4787    /// +---+---------------+
4788    /// | 1 | Xmm, Xmm, Mem |
4789    /// | 2 | Xmm, Xmm, Xmm |
4790    /// | 3 | Ymm, Ymm, Mem |
4791    /// | 4 | Ymm, Ymm, Ymm |
4792    /// | 5 | Zmm, Zmm, Mem |
4793    /// | 6 | Zmm, Zmm, Zmm |
4794    /// +---+---------------+
4795    /// ```
4796    #[inline]
4797    pub fn vpshldvd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
4798    where
4799        Assembler<'a>: VpshldvdMaskEmitter<A, B, C>,
4800    {
4801        <Self as VpshldvdMaskEmitter<A, B, C>>::vpshldvd_mask(self, op0, op1, op2);
4802    }
4803    /// `VPSHLDVD_MASKZ`.
4804    ///
4805    /// Supported operand variants:
4806    ///
4807    /// ```text
4808    /// +---+---------------+
4809    /// | # | Operands      |
4810    /// +---+---------------+
4811    /// | 1 | Xmm, Xmm, Mem |
4812    /// | 2 | Xmm, Xmm, Xmm |
4813    /// | 3 | Ymm, Ymm, Mem |
4814    /// | 4 | Ymm, Ymm, Ymm |
4815    /// | 5 | Zmm, Zmm, Mem |
4816    /// | 6 | Zmm, Zmm, Zmm |
4817    /// +---+---------------+
4818    /// ```
4819    #[inline]
4820    pub fn vpshldvd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
4821    where
4822        Assembler<'a>: VpshldvdMaskzEmitter<A, B, C>,
4823    {
4824        <Self as VpshldvdMaskzEmitter<A, B, C>>::vpshldvd_maskz(self, op0, op1, op2);
4825    }
4826    /// `VPSHLDVQ`.
4827    ///
4828    /// Supported operand variants:
4829    ///
4830    /// ```text
4831    /// +---+---------------+
4832    /// | # | Operands      |
4833    /// +---+---------------+
4834    /// | 1 | Xmm, Xmm, Mem |
4835    /// | 2 | Xmm, Xmm, Xmm |
4836    /// | 3 | Ymm, Ymm, Mem |
4837    /// | 4 | Ymm, Ymm, Ymm |
4838    /// | 5 | Zmm, Zmm, Mem |
4839    /// | 6 | Zmm, Zmm, Zmm |
4840    /// +---+---------------+
4841    /// ```
4842    #[inline]
4843    pub fn vpshldvq<A, B, C>(&mut self, op0: A, op1: B, op2: C)
4844    where
4845        Assembler<'a>: VpshldvqEmitter<A, B, C>,
4846    {
4847        <Self as VpshldvqEmitter<A, B, C>>::vpshldvq(self, op0, op1, op2);
4848    }
4849    /// `VPSHLDVQ_MASK`.
4850    ///
4851    /// Supported operand variants:
4852    ///
4853    /// ```text
4854    /// +---+---------------+
4855    /// | # | Operands      |
4856    /// +---+---------------+
4857    /// | 1 | Xmm, Xmm, Mem |
4858    /// | 2 | Xmm, Xmm, Xmm |
4859    /// | 3 | Ymm, Ymm, Mem |
4860    /// | 4 | Ymm, Ymm, Ymm |
4861    /// | 5 | Zmm, Zmm, Mem |
4862    /// | 6 | Zmm, Zmm, Zmm |
4863    /// +---+---------------+
4864    /// ```
4865    #[inline]
4866    pub fn vpshldvq_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
4867    where
4868        Assembler<'a>: VpshldvqMaskEmitter<A, B, C>,
4869    {
4870        <Self as VpshldvqMaskEmitter<A, B, C>>::vpshldvq_mask(self, op0, op1, op2);
4871    }
4872    /// `VPSHLDVQ_MASKZ`.
4873    ///
4874    /// Supported operand variants:
4875    ///
4876    /// ```text
4877    /// +---+---------------+
4878    /// | # | Operands      |
4879    /// +---+---------------+
4880    /// | 1 | Xmm, Xmm, Mem |
4881    /// | 2 | Xmm, Xmm, Xmm |
4882    /// | 3 | Ymm, Ymm, Mem |
4883    /// | 4 | Ymm, Ymm, Ymm |
4884    /// | 5 | Zmm, Zmm, Mem |
4885    /// | 6 | Zmm, Zmm, Zmm |
4886    /// +---+---------------+
4887    /// ```
4888    #[inline]
4889    pub fn vpshldvq_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
4890    where
4891        Assembler<'a>: VpshldvqMaskzEmitter<A, B, C>,
4892    {
4893        <Self as VpshldvqMaskzEmitter<A, B, C>>::vpshldvq_maskz(self, op0, op1, op2);
4894    }
4895    /// `VPSHLDVW`.
4896    ///
4897    /// Supported operand variants:
4898    ///
4899    /// ```text
4900    /// +---+---------------+
4901    /// | # | Operands      |
4902    /// +---+---------------+
4903    /// | 1 | Xmm, Xmm, Mem |
4904    /// | 2 | Xmm, Xmm, Xmm |
4905    /// | 3 | Ymm, Ymm, Mem |
4906    /// | 4 | Ymm, Ymm, Ymm |
4907    /// | 5 | Zmm, Zmm, Mem |
4908    /// | 6 | Zmm, Zmm, Zmm |
4909    /// +---+---------------+
4910    /// ```
4911    #[inline]
4912    pub fn vpshldvw<A, B, C>(&mut self, op0: A, op1: B, op2: C)
4913    where
4914        Assembler<'a>: VpshldvwEmitter<A, B, C>,
4915    {
4916        <Self as VpshldvwEmitter<A, B, C>>::vpshldvw(self, op0, op1, op2);
4917    }
4918    /// `VPSHLDVW_MASK`.
4919    ///
4920    /// Supported operand variants:
4921    ///
4922    /// ```text
4923    /// +---+---------------+
4924    /// | # | Operands      |
4925    /// +---+---------------+
4926    /// | 1 | Xmm, Xmm, Mem |
4927    /// | 2 | Xmm, Xmm, Xmm |
4928    /// | 3 | Ymm, Ymm, Mem |
4929    /// | 4 | Ymm, Ymm, Ymm |
4930    /// | 5 | Zmm, Zmm, Mem |
4931    /// | 6 | Zmm, Zmm, Zmm |
4932    /// +---+---------------+
4933    /// ```
4934    #[inline]
4935    pub fn vpshldvw_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
4936    where
4937        Assembler<'a>: VpshldvwMaskEmitter<A, B, C>,
4938    {
4939        <Self as VpshldvwMaskEmitter<A, B, C>>::vpshldvw_mask(self, op0, op1, op2);
4940    }
4941    /// `VPSHLDVW_MASKZ`.
4942    ///
4943    /// Supported operand variants:
4944    ///
4945    /// ```text
4946    /// +---+---------------+
4947    /// | # | Operands      |
4948    /// +---+---------------+
4949    /// | 1 | Xmm, Xmm, Mem |
4950    /// | 2 | Xmm, Xmm, Xmm |
4951    /// | 3 | Ymm, Ymm, Mem |
4952    /// | 4 | Ymm, Ymm, Ymm |
4953    /// | 5 | Zmm, Zmm, Mem |
4954    /// | 6 | Zmm, Zmm, Zmm |
4955    /// +---+---------------+
4956    /// ```
4957    #[inline]
4958    pub fn vpshldvw_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
4959    where
4960        Assembler<'a>: VpshldvwMaskzEmitter<A, B, C>,
4961    {
4962        <Self as VpshldvwMaskzEmitter<A, B, C>>::vpshldvw_maskz(self, op0, op1, op2);
4963    }
4964    /// `VPSHLDW`.
4965    ///
4966    /// Supported operand variants:
4967    ///
4968    /// ```text
4969    /// +---+--------------------+
4970    /// | # | Operands           |
4971    /// +---+--------------------+
4972    /// | 1 | Xmm, Xmm, Mem, Imm |
4973    /// | 2 | Xmm, Xmm, Xmm, Imm |
4974    /// | 3 | Ymm, Ymm, Mem, Imm |
4975    /// | 4 | Ymm, Ymm, Ymm, Imm |
4976    /// | 5 | Zmm, Zmm, Mem, Imm |
4977    /// | 6 | Zmm, Zmm, Zmm, Imm |
4978    /// +---+--------------------+
4979    /// ```
4980    #[inline]
4981    pub fn vpshldw<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
4982    where
4983        Assembler<'a>: VpshldwEmitter<A, B, C, D>,
4984    {
4985        <Self as VpshldwEmitter<A, B, C, D>>::vpshldw(self, op0, op1, op2, op3);
4986    }
4987    /// `VPSHLDW_MASK`.
4988    ///
4989    /// Supported operand variants:
4990    ///
4991    /// ```text
4992    /// +---+--------------------+
4993    /// | # | Operands           |
4994    /// +---+--------------------+
4995    /// | 1 | Xmm, Xmm, Mem, Imm |
4996    /// | 2 | Xmm, Xmm, Xmm, Imm |
4997    /// | 3 | Ymm, Ymm, Mem, Imm |
4998    /// | 4 | Ymm, Ymm, Ymm, Imm |
4999    /// | 5 | Zmm, Zmm, Mem, Imm |
5000    /// | 6 | Zmm, Zmm, Zmm, Imm |
5001    /// +---+--------------------+
5002    /// ```
5003    #[inline]
5004    pub fn vpshldw_mask<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
5005    where
5006        Assembler<'a>: VpshldwMaskEmitter<A, B, C, D>,
5007    {
5008        <Self as VpshldwMaskEmitter<A, B, C, D>>::vpshldw_mask(self, op0, op1, op2, op3);
5009    }
5010    /// `VPSHLDW_MASKZ`.
5011    ///
5012    /// Supported operand variants:
5013    ///
5014    /// ```text
5015    /// +---+--------------------+
5016    /// | # | Operands           |
5017    /// +---+--------------------+
5018    /// | 1 | Xmm, Xmm, Mem, Imm |
5019    /// | 2 | Xmm, Xmm, Xmm, Imm |
5020    /// | 3 | Ymm, Ymm, Mem, Imm |
5021    /// | 4 | Ymm, Ymm, Ymm, Imm |
5022    /// | 5 | Zmm, Zmm, Mem, Imm |
5023    /// | 6 | Zmm, Zmm, Zmm, Imm |
5024    /// +---+--------------------+
5025    /// ```
5026    #[inline]
5027    pub fn vpshldw_maskz<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
5028    where
5029        Assembler<'a>: VpshldwMaskzEmitter<A, B, C, D>,
5030    {
5031        <Self as VpshldwMaskzEmitter<A, B, C, D>>::vpshldw_maskz(self, op0, op1, op2, op3);
5032    }
5033    /// `VPSHRDD`.
5034    ///
5035    /// Supported operand variants:
5036    ///
5037    /// ```text
5038    /// +---+--------------------+
5039    /// | # | Operands           |
5040    /// +---+--------------------+
5041    /// | 1 | Xmm, Xmm, Mem, Imm |
5042    /// | 2 | Xmm, Xmm, Xmm, Imm |
5043    /// | 3 | Ymm, Ymm, Mem, Imm |
5044    /// | 4 | Ymm, Ymm, Ymm, Imm |
5045    /// | 5 | Zmm, Zmm, Mem, Imm |
5046    /// | 6 | Zmm, Zmm, Zmm, Imm |
5047    /// +---+--------------------+
5048    /// ```
5049    #[inline]
5050    pub fn vpshrdd<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
5051    where
5052        Assembler<'a>: VpshrddEmitter<A, B, C, D>,
5053    {
5054        <Self as VpshrddEmitter<A, B, C, D>>::vpshrdd(self, op0, op1, op2, op3);
5055    }
5056    /// `VPSHRDD_MASK`.
5057    ///
5058    /// Supported operand variants:
5059    ///
5060    /// ```text
5061    /// +---+--------------------+
5062    /// | # | Operands           |
5063    /// +---+--------------------+
5064    /// | 1 | Xmm, Xmm, Mem, Imm |
5065    /// | 2 | Xmm, Xmm, Xmm, Imm |
5066    /// | 3 | Ymm, Ymm, Mem, Imm |
5067    /// | 4 | Ymm, Ymm, Ymm, Imm |
5068    /// | 5 | Zmm, Zmm, Mem, Imm |
5069    /// | 6 | Zmm, Zmm, Zmm, Imm |
5070    /// +---+--------------------+
5071    /// ```
5072    #[inline]
5073    pub fn vpshrdd_mask<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
5074    where
5075        Assembler<'a>: VpshrddMaskEmitter<A, B, C, D>,
5076    {
5077        <Self as VpshrddMaskEmitter<A, B, C, D>>::vpshrdd_mask(self, op0, op1, op2, op3);
5078    }
5079    /// `VPSHRDD_MASKZ`.
5080    ///
5081    /// Supported operand variants:
5082    ///
5083    /// ```text
5084    /// +---+--------------------+
5085    /// | # | Operands           |
5086    /// +---+--------------------+
5087    /// | 1 | Xmm, Xmm, Mem, Imm |
5088    /// | 2 | Xmm, Xmm, Xmm, Imm |
5089    /// | 3 | Ymm, Ymm, Mem, Imm |
5090    /// | 4 | Ymm, Ymm, Ymm, Imm |
5091    /// | 5 | Zmm, Zmm, Mem, Imm |
5092    /// | 6 | Zmm, Zmm, Zmm, Imm |
5093    /// +---+--------------------+
5094    /// ```
5095    #[inline]
5096    pub fn vpshrdd_maskz<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
5097    where
5098        Assembler<'a>: VpshrddMaskzEmitter<A, B, C, D>,
5099    {
5100        <Self as VpshrddMaskzEmitter<A, B, C, D>>::vpshrdd_maskz(self, op0, op1, op2, op3);
5101    }
5102    /// `VPSHRDQ`.
5103    ///
5104    /// Supported operand variants:
5105    ///
5106    /// ```text
5107    /// +---+--------------------+
5108    /// | # | Operands           |
5109    /// +---+--------------------+
5110    /// | 1 | Xmm, Xmm, Mem, Imm |
5111    /// | 2 | Xmm, Xmm, Xmm, Imm |
5112    /// | 3 | Ymm, Ymm, Mem, Imm |
5113    /// | 4 | Ymm, Ymm, Ymm, Imm |
5114    /// | 5 | Zmm, Zmm, Mem, Imm |
5115    /// | 6 | Zmm, Zmm, Zmm, Imm |
5116    /// +---+--------------------+
5117    /// ```
5118    #[inline]
5119    pub fn vpshrdq<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
5120    where
5121        Assembler<'a>: VpshrdqEmitter<A, B, C, D>,
5122    {
5123        <Self as VpshrdqEmitter<A, B, C, D>>::vpshrdq(self, op0, op1, op2, op3);
5124    }
5125    /// `VPSHRDQ_MASK`.
5126    ///
5127    /// Supported operand variants:
5128    ///
5129    /// ```text
5130    /// +---+--------------------+
5131    /// | # | Operands           |
5132    /// +---+--------------------+
5133    /// | 1 | Xmm, Xmm, Mem, Imm |
5134    /// | 2 | Xmm, Xmm, Xmm, Imm |
5135    /// | 3 | Ymm, Ymm, Mem, Imm |
5136    /// | 4 | Ymm, Ymm, Ymm, Imm |
5137    /// | 5 | Zmm, Zmm, Mem, Imm |
5138    /// | 6 | Zmm, Zmm, Zmm, Imm |
5139    /// +---+--------------------+
5140    /// ```
5141    #[inline]
5142    pub fn vpshrdq_mask<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
5143    where
5144        Assembler<'a>: VpshrdqMaskEmitter<A, B, C, D>,
5145    {
5146        <Self as VpshrdqMaskEmitter<A, B, C, D>>::vpshrdq_mask(self, op0, op1, op2, op3);
5147    }
5148    /// `VPSHRDQ_MASKZ`.
5149    ///
5150    /// Supported operand variants:
5151    ///
5152    /// ```text
5153    /// +---+--------------------+
5154    /// | # | Operands           |
5155    /// +---+--------------------+
5156    /// | 1 | Xmm, Xmm, Mem, Imm |
5157    /// | 2 | Xmm, Xmm, Xmm, Imm |
5158    /// | 3 | Ymm, Ymm, Mem, Imm |
5159    /// | 4 | Ymm, Ymm, Ymm, Imm |
5160    /// | 5 | Zmm, Zmm, Mem, Imm |
5161    /// | 6 | Zmm, Zmm, Zmm, Imm |
5162    /// +---+--------------------+
5163    /// ```
5164    #[inline]
5165    pub fn vpshrdq_maskz<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
5166    where
5167        Assembler<'a>: VpshrdqMaskzEmitter<A, B, C, D>,
5168    {
5169        <Self as VpshrdqMaskzEmitter<A, B, C, D>>::vpshrdq_maskz(self, op0, op1, op2, op3);
5170    }
5171    /// `VPSHRDVD`.
5172    ///
5173    /// Supported operand variants:
5174    ///
5175    /// ```text
5176    /// +---+---------------+
5177    /// | # | Operands      |
5178    /// +---+---------------+
5179    /// | 1 | Xmm, Xmm, Mem |
5180    /// | 2 | Xmm, Xmm, Xmm |
5181    /// | 3 | Ymm, Ymm, Mem |
5182    /// | 4 | Ymm, Ymm, Ymm |
5183    /// | 5 | Zmm, Zmm, Mem |
5184    /// | 6 | Zmm, Zmm, Zmm |
5185    /// +---+---------------+
5186    /// ```
5187    #[inline]
5188    pub fn vpshrdvd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
5189    where
5190        Assembler<'a>: VpshrdvdEmitter<A, B, C>,
5191    {
5192        <Self as VpshrdvdEmitter<A, B, C>>::vpshrdvd(self, op0, op1, op2);
5193    }
5194    /// `VPSHRDVD_MASK`.
5195    ///
5196    /// Supported operand variants:
5197    ///
5198    /// ```text
5199    /// +---+---------------+
5200    /// | # | Operands      |
5201    /// +---+---------------+
5202    /// | 1 | Xmm, Xmm, Mem |
5203    /// | 2 | Xmm, Xmm, Xmm |
5204    /// | 3 | Ymm, Ymm, Mem |
5205    /// | 4 | Ymm, Ymm, Ymm |
5206    /// | 5 | Zmm, Zmm, Mem |
5207    /// | 6 | Zmm, Zmm, Zmm |
5208    /// +---+---------------+
5209    /// ```
5210    #[inline]
5211    pub fn vpshrdvd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
5212    where
5213        Assembler<'a>: VpshrdvdMaskEmitter<A, B, C>,
5214    {
5215        <Self as VpshrdvdMaskEmitter<A, B, C>>::vpshrdvd_mask(self, op0, op1, op2);
5216    }
5217    /// `VPSHRDVD_MASKZ`.
5218    ///
5219    /// Supported operand variants:
5220    ///
5221    /// ```text
5222    /// +---+---------------+
5223    /// | # | Operands      |
5224    /// +---+---------------+
5225    /// | 1 | Xmm, Xmm, Mem |
5226    /// | 2 | Xmm, Xmm, Xmm |
5227    /// | 3 | Ymm, Ymm, Mem |
5228    /// | 4 | Ymm, Ymm, Ymm |
5229    /// | 5 | Zmm, Zmm, Mem |
5230    /// | 6 | Zmm, Zmm, Zmm |
5231    /// +---+---------------+
5232    /// ```
5233    #[inline]
5234    pub fn vpshrdvd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
5235    where
5236        Assembler<'a>: VpshrdvdMaskzEmitter<A, B, C>,
5237    {
5238        <Self as VpshrdvdMaskzEmitter<A, B, C>>::vpshrdvd_maskz(self, op0, op1, op2);
5239    }
5240    /// `VPSHRDVQ`.
5241    ///
5242    /// Supported operand variants:
5243    ///
5244    /// ```text
5245    /// +---+---------------+
5246    /// | # | Operands      |
5247    /// +---+---------------+
5248    /// | 1 | Xmm, Xmm, Mem |
5249    /// | 2 | Xmm, Xmm, Xmm |
5250    /// | 3 | Ymm, Ymm, Mem |
5251    /// | 4 | Ymm, Ymm, Ymm |
5252    /// | 5 | Zmm, Zmm, Mem |
5253    /// | 6 | Zmm, Zmm, Zmm |
5254    /// +---+---------------+
5255    /// ```
5256    #[inline]
5257    pub fn vpshrdvq<A, B, C>(&mut self, op0: A, op1: B, op2: C)
5258    where
5259        Assembler<'a>: VpshrdvqEmitter<A, B, C>,
5260    {
5261        <Self as VpshrdvqEmitter<A, B, C>>::vpshrdvq(self, op0, op1, op2);
5262    }
5263    /// `VPSHRDVQ_MASK`.
5264    ///
5265    /// Supported operand variants:
5266    ///
5267    /// ```text
5268    /// +---+---------------+
5269    /// | # | Operands      |
5270    /// +---+---------------+
5271    /// | 1 | Xmm, Xmm, Mem |
5272    /// | 2 | Xmm, Xmm, Xmm |
5273    /// | 3 | Ymm, Ymm, Mem |
5274    /// | 4 | Ymm, Ymm, Ymm |
5275    /// | 5 | Zmm, Zmm, Mem |
5276    /// | 6 | Zmm, Zmm, Zmm |
5277    /// +---+---------------+
5278    /// ```
5279    #[inline]
5280    pub fn vpshrdvq_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
5281    where
5282        Assembler<'a>: VpshrdvqMaskEmitter<A, B, C>,
5283    {
5284        <Self as VpshrdvqMaskEmitter<A, B, C>>::vpshrdvq_mask(self, op0, op1, op2);
5285    }
5286    /// `VPSHRDVQ_MASKZ`.
5287    ///
5288    /// Supported operand variants:
5289    ///
5290    /// ```text
5291    /// +---+---------------+
5292    /// | # | Operands      |
5293    /// +---+---------------+
5294    /// | 1 | Xmm, Xmm, Mem |
5295    /// | 2 | Xmm, Xmm, Xmm |
5296    /// | 3 | Ymm, Ymm, Mem |
5297    /// | 4 | Ymm, Ymm, Ymm |
5298    /// | 5 | Zmm, Zmm, Mem |
5299    /// | 6 | Zmm, Zmm, Zmm |
5300    /// +---+---------------+
5301    /// ```
5302    #[inline]
5303    pub fn vpshrdvq_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
5304    where
5305        Assembler<'a>: VpshrdvqMaskzEmitter<A, B, C>,
5306    {
5307        <Self as VpshrdvqMaskzEmitter<A, B, C>>::vpshrdvq_maskz(self, op0, op1, op2);
5308    }
5309    /// `VPSHRDVW`.
5310    ///
5311    /// Supported operand variants:
5312    ///
5313    /// ```text
5314    /// +---+---------------+
5315    /// | # | Operands      |
5316    /// +---+---------------+
5317    /// | 1 | Xmm, Xmm, Mem |
5318    /// | 2 | Xmm, Xmm, Xmm |
5319    /// | 3 | Ymm, Ymm, Mem |
5320    /// | 4 | Ymm, Ymm, Ymm |
5321    /// | 5 | Zmm, Zmm, Mem |
5322    /// | 6 | Zmm, Zmm, Zmm |
5323    /// +---+---------------+
5324    /// ```
5325    #[inline]
5326    pub fn vpshrdvw<A, B, C>(&mut self, op0: A, op1: B, op2: C)
5327    where
5328        Assembler<'a>: VpshrdvwEmitter<A, B, C>,
5329    {
5330        <Self as VpshrdvwEmitter<A, B, C>>::vpshrdvw(self, op0, op1, op2);
5331    }
5332    /// `VPSHRDVW_MASK`.
5333    ///
5334    /// Supported operand variants:
5335    ///
5336    /// ```text
5337    /// +---+---------------+
5338    /// | # | Operands      |
5339    /// +---+---------------+
5340    /// | 1 | Xmm, Xmm, Mem |
5341    /// | 2 | Xmm, Xmm, Xmm |
5342    /// | 3 | Ymm, Ymm, Mem |
5343    /// | 4 | Ymm, Ymm, Ymm |
5344    /// | 5 | Zmm, Zmm, Mem |
5345    /// | 6 | Zmm, Zmm, Zmm |
5346    /// +---+---------------+
5347    /// ```
5348    #[inline]
5349    pub fn vpshrdvw_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
5350    where
5351        Assembler<'a>: VpshrdvwMaskEmitter<A, B, C>,
5352    {
5353        <Self as VpshrdvwMaskEmitter<A, B, C>>::vpshrdvw_mask(self, op0, op1, op2);
5354    }
5355    /// `VPSHRDVW_MASKZ`.
5356    ///
5357    /// Supported operand variants:
5358    ///
5359    /// ```text
5360    /// +---+---------------+
5361    /// | # | Operands      |
5362    /// +---+---------------+
5363    /// | 1 | Xmm, Xmm, Mem |
5364    /// | 2 | Xmm, Xmm, Xmm |
5365    /// | 3 | Ymm, Ymm, Mem |
5366    /// | 4 | Ymm, Ymm, Ymm |
5367    /// | 5 | Zmm, Zmm, Mem |
5368    /// | 6 | Zmm, Zmm, Zmm |
5369    /// +---+---------------+
5370    /// ```
5371    #[inline]
5372    pub fn vpshrdvw_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
5373    where
5374        Assembler<'a>: VpshrdvwMaskzEmitter<A, B, C>,
5375    {
5376        <Self as VpshrdvwMaskzEmitter<A, B, C>>::vpshrdvw_maskz(self, op0, op1, op2);
5377    }
5378    /// `VPSHRDW`.
5379    ///
5380    /// Supported operand variants:
5381    ///
5382    /// ```text
5383    /// +---+--------------------+
5384    /// | # | Operands           |
5385    /// +---+--------------------+
5386    /// | 1 | Xmm, Xmm, Mem, Imm |
5387    /// | 2 | Xmm, Xmm, Xmm, Imm |
5388    /// | 3 | Ymm, Ymm, Mem, Imm |
5389    /// | 4 | Ymm, Ymm, Ymm, Imm |
5390    /// | 5 | Zmm, Zmm, Mem, Imm |
5391    /// | 6 | Zmm, Zmm, Zmm, Imm |
5392    /// +---+--------------------+
5393    /// ```
5394    #[inline]
5395    pub fn vpshrdw<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
5396    where
5397        Assembler<'a>: VpshrdwEmitter<A, B, C, D>,
5398    {
5399        <Self as VpshrdwEmitter<A, B, C, D>>::vpshrdw(self, op0, op1, op2, op3);
5400    }
5401    /// `VPSHRDW_MASK`.
5402    ///
5403    /// Supported operand variants:
5404    ///
5405    /// ```text
5406    /// +---+--------------------+
5407    /// | # | Operands           |
5408    /// +---+--------------------+
5409    /// | 1 | Xmm, Xmm, Mem, Imm |
5410    /// | 2 | Xmm, Xmm, Xmm, Imm |
5411    /// | 3 | Ymm, Ymm, Mem, Imm |
5412    /// | 4 | Ymm, Ymm, Ymm, Imm |
5413    /// | 5 | Zmm, Zmm, Mem, Imm |
5414    /// | 6 | Zmm, Zmm, Zmm, Imm |
5415    /// +---+--------------------+
5416    /// ```
5417    #[inline]
5418    pub fn vpshrdw_mask<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
5419    where
5420        Assembler<'a>: VpshrdwMaskEmitter<A, B, C, D>,
5421    {
5422        <Self as VpshrdwMaskEmitter<A, B, C, D>>::vpshrdw_mask(self, op0, op1, op2, op3);
5423    }
5424    /// `VPSHRDW_MASKZ`.
5425    ///
5426    /// Supported operand variants:
5427    ///
5428    /// ```text
5429    /// +---+--------------------+
5430    /// | # | Operands           |
5431    /// +---+--------------------+
5432    /// | 1 | Xmm, Xmm, Mem, Imm |
5433    /// | 2 | Xmm, Xmm, Xmm, Imm |
5434    /// | 3 | Ymm, Ymm, Mem, Imm |
5435    /// | 4 | Ymm, Ymm, Ymm, Imm |
5436    /// | 5 | Zmm, Zmm, Mem, Imm |
5437    /// | 6 | Zmm, Zmm, Zmm, Imm |
5438    /// +---+--------------------+
5439    /// ```
5440    #[inline]
5441    pub fn vpshrdw_maskz<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
5442    where
5443        Assembler<'a>: VpshrdwMaskzEmitter<A, B, C, D>,
5444    {
5445        <Self as VpshrdwMaskzEmitter<A, B, C, D>>::vpshrdw_maskz(self, op0, op1, op2, op3);
5446    }
5447}
asmkit/x86/features/AVX512_VBMI2.rs

asmkit/x86/features/
AVX512_VBMI2.rs
