asmkit/x86/features/
AVX512BW.rs

1use super::super::opcodes::*;
2use crate::core::emitter::*;
3use crate::core::operand::*;
4use crate::x86::assembler::*;
5use crate::x86::operands::*;
6
7/// A dummy operand that represents no register. Here just for simplicity.
8const NOREG: Operand = Operand::new();
9
10/// `KADDD`.
11///
12/// Supported operand variants:
13///
14/// ```text
15/// +---+------------------+
16/// | # | Operands         |
17/// +---+------------------+
18/// | 1 | KReg, KReg, KReg |
19/// +---+------------------+
20/// ```
21pub trait KadddEmitter<A, B, C> {
22    fn kaddd(&mut self, op0: A, op1: B, op2: C);
23}
24
25impl<'a> KadddEmitter<KReg, KReg, KReg> for Assembler<'a> {
26    fn kaddd(&mut self, op0: KReg, op1: KReg, op2: KReg) {
27        self.emit(
28            KADDDKKK,
29            op0.as_operand(),
30            op1.as_operand(),
31            op2.as_operand(),
32            &NOREG,
33        );
34    }
35}
36
37/// `KADDQ`.
38///
39/// Supported operand variants:
40///
41/// ```text
42/// +---+------------------+
43/// | # | Operands         |
44/// +---+------------------+
45/// | 1 | KReg, KReg, KReg |
46/// +---+------------------+
47/// ```
48pub trait KaddqEmitter<A, B, C> {
49    fn kaddq(&mut self, op0: A, op1: B, op2: C);
50}
51
52impl<'a> KaddqEmitter<KReg, KReg, KReg> for Assembler<'a> {
53    fn kaddq(&mut self, op0: KReg, op1: KReg, op2: KReg) {
54        self.emit(
55            KADDQKKK,
56            op0.as_operand(),
57            op1.as_operand(),
58            op2.as_operand(),
59            &NOREG,
60        );
61    }
62}
63
64/// `KANDD`.
65///
66/// Supported operand variants:
67///
68/// ```text
69/// +---+------------------+
70/// | # | Operands         |
71/// +---+------------------+
72/// | 1 | KReg, KReg, KReg |
73/// +---+------------------+
74/// ```
75pub trait KanddEmitter<A, B, C> {
76    fn kandd(&mut self, op0: A, op1: B, op2: C);
77}
78
79impl<'a> KanddEmitter<KReg, KReg, KReg> for Assembler<'a> {
80    fn kandd(&mut self, op0: KReg, op1: KReg, op2: KReg) {
81        self.emit(
82            KANDDKKK,
83            op0.as_operand(),
84            op1.as_operand(),
85            op2.as_operand(),
86            &NOREG,
87        );
88    }
89}
90
91/// `KANDND`.
92///
93/// Supported operand variants:
94///
95/// ```text
96/// +---+------------------+
97/// | # | Operands         |
98/// +---+------------------+
99/// | 1 | KReg, KReg, KReg |
100/// +---+------------------+
101/// ```
102pub trait KandndEmitter<A, B, C> {
103    fn kandnd(&mut self, op0: A, op1: B, op2: C);
104}
105
106impl<'a> KandndEmitter<KReg, KReg, KReg> for Assembler<'a> {
107    fn kandnd(&mut self, op0: KReg, op1: KReg, op2: KReg) {
108        self.emit(
109            KANDNDKKK,
110            op0.as_operand(),
111            op1.as_operand(),
112            op2.as_operand(),
113            &NOREG,
114        );
115    }
116}
117
118/// `KANDNQ`.
119///
120/// Supported operand variants:
121///
122/// ```text
123/// +---+------------------+
124/// | # | Operands         |
125/// +---+------------------+
126/// | 1 | KReg, KReg, KReg |
127/// +---+------------------+
128/// ```
129pub trait KandnqEmitter<A, B, C> {
130    fn kandnq(&mut self, op0: A, op1: B, op2: C);
131}
132
133impl<'a> KandnqEmitter<KReg, KReg, KReg> for Assembler<'a> {
134    fn kandnq(&mut self, op0: KReg, op1: KReg, op2: KReg) {
135        self.emit(
136            KANDNQKKK,
137            op0.as_operand(),
138            op1.as_operand(),
139            op2.as_operand(),
140            &NOREG,
141        );
142    }
143}
144
145/// `KANDQ`.
146///
147/// Supported operand variants:
148///
149/// ```text
150/// +---+------------------+
151/// | # | Operands         |
152/// +---+------------------+
153/// | 1 | KReg, KReg, KReg |
154/// +---+------------------+
155/// ```
156pub trait KandqEmitter<A, B, C> {
157    fn kandq(&mut self, op0: A, op1: B, op2: C);
158}
159
160impl<'a> KandqEmitter<KReg, KReg, KReg> for Assembler<'a> {
161    fn kandq(&mut self, op0: KReg, op1: KReg, op2: KReg) {
162        self.emit(
163            KANDQKKK,
164            op0.as_operand(),
165            op1.as_operand(),
166            op2.as_operand(),
167            &NOREG,
168        );
169    }
170}
171
172/// `KMOVD`.
173///
174/// Supported operand variants:
175///
176/// ```text
177/// +---+------------+
178/// | # | Operands   |
179/// +---+------------+
180/// | 1 | Gpd, KReg  |
181/// | 2 | KReg, Gpd  |
182/// | 3 | KReg, KReg |
183/// | 4 | KReg, Mem  |
184/// | 5 | Mem, KReg  |
185/// +---+------------+
186/// ```
187pub trait KmovdEmitter<A, B> {
188    fn kmovd(&mut self, op0: A, op1: B);
189}
190
191impl<'a> KmovdEmitter<KReg, KReg> for Assembler<'a> {
192    fn kmovd(&mut self, op0: KReg, op1: KReg) {
193        self.emit(KMOVDKK, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
194    }
195}
196
197impl<'a> KmovdEmitter<KReg, Mem> for Assembler<'a> {
198    fn kmovd(&mut self, op0: KReg, op1: Mem) {
199        self.emit(KMOVDKM, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
200    }
201}
202
203impl<'a> KmovdEmitter<Mem, KReg> for Assembler<'a> {
204    fn kmovd(&mut self, op0: Mem, op1: KReg) {
205        self.emit(KMOVDMK, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
206    }
207}
208
209impl<'a> KmovdEmitter<KReg, Gpd> for Assembler<'a> {
210    fn kmovd(&mut self, op0: KReg, op1: Gpd) {
211        self.emit(KMOVDKR, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
212    }
213}
214
215impl<'a> KmovdEmitter<Gpd, KReg> for Assembler<'a> {
216    fn kmovd(&mut self, op0: Gpd, op1: KReg) {
217        self.emit(KMOVDRK, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
218    }
219}
220
221/// `KMOVQ`.
222///
223/// Supported operand variants:
224///
225/// ```text
226/// +---+------------+
227/// | # | Operands   |
228/// +---+------------+
229/// | 1 | Gpd, KReg  |
230/// | 2 | KReg, Gpd  |
231/// | 3 | KReg, KReg |
232/// | 4 | KReg, Mem  |
233/// | 5 | Mem, KReg  |
234/// +---+------------+
235/// ```
236pub trait KmovqEmitter<A, B> {
237    fn kmovq(&mut self, op0: A, op1: B);
238}
239
240impl<'a> KmovqEmitter<KReg, KReg> for Assembler<'a> {
241    fn kmovq(&mut self, op0: KReg, op1: KReg) {
242        self.emit(KMOVQKK, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
243    }
244}
245
246impl<'a> KmovqEmitter<KReg, Mem> for Assembler<'a> {
247    fn kmovq(&mut self, op0: KReg, op1: Mem) {
248        self.emit(KMOVQKM, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
249    }
250}
251
252impl<'a> KmovqEmitter<Mem, KReg> for Assembler<'a> {
253    fn kmovq(&mut self, op0: Mem, op1: KReg) {
254        self.emit(KMOVQMK, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
255    }
256}
257
258impl<'a> KmovqEmitter<KReg, Gpd> for Assembler<'a> {
259    fn kmovq(&mut self, op0: KReg, op1: Gpd) {
260        self.emit(KMOVQKR, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
261    }
262}
263
264impl<'a> KmovqEmitter<Gpd, KReg> for Assembler<'a> {
265    fn kmovq(&mut self, op0: Gpd, op1: KReg) {
266        self.emit(KMOVQRK, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
267    }
268}
269
270/// `KNOTD`.
271///
272/// Supported operand variants:
273///
274/// ```text
275/// +---+------------+
276/// | # | Operands   |
277/// +---+------------+
278/// | 1 | KReg, KReg |
279/// +---+------------+
280/// ```
281pub trait KnotdEmitter<A, B> {
282    fn knotd(&mut self, op0: A, op1: B);
283}
284
285impl<'a> KnotdEmitter<KReg, KReg> for Assembler<'a> {
286    fn knotd(&mut self, op0: KReg, op1: KReg) {
287        self.emit(KNOTDKK, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
288    }
289}
290
291/// `KNOTQ`.
292///
293/// Supported operand variants:
294///
295/// ```text
296/// +---+------------+
297/// | # | Operands   |
298/// +---+------------+
299/// | 1 | KReg, KReg |
300/// +---+------------+
301/// ```
302pub trait KnotqEmitter<A, B> {
303    fn knotq(&mut self, op0: A, op1: B);
304}
305
306impl<'a> KnotqEmitter<KReg, KReg> for Assembler<'a> {
307    fn knotq(&mut self, op0: KReg, op1: KReg) {
308        self.emit(KNOTQKK, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
309    }
310}
311
312/// `KORD`.
313///
314/// Supported operand variants:
315///
316/// ```text
317/// +---+------------------+
318/// | # | Operands         |
319/// +---+------------------+
320/// | 1 | KReg, KReg, KReg |
321/// +---+------------------+
322/// ```
323pub trait KordEmitter<A, B, C> {
324    fn kord(&mut self, op0: A, op1: B, op2: C);
325}
326
327impl<'a> KordEmitter<KReg, KReg, KReg> for Assembler<'a> {
328    fn kord(&mut self, op0: KReg, op1: KReg, op2: KReg) {
329        self.emit(
330            KORDKKK,
331            op0.as_operand(),
332            op1.as_operand(),
333            op2.as_operand(),
334            &NOREG,
335        );
336    }
337}
338
339/// `KORQ`.
340///
341/// Supported operand variants:
342///
343/// ```text
344/// +---+------------------+
345/// | # | Operands         |
346/// +---+------------------+
347/// | 1 | KReg, KReg, KReg |
348/// +---+------------------+
349/// ```
350pub trait KorqEmitter<A, B, C> {
351    fn korq(&mut self, op0: A, op1: B, op2: C);
352}
353
354impl<'a> KorqEmitter<KReg, KReg, KReg> for Assembler<'a> {
355    fn korq(&mut self, op0: KReg, op1: KReg, op2: KReg) {
356        self.emit(
357            KORQKKK,
358            op0.as_operand(),
359            op1.as_operand(),
360            op2.as_operand(),
361            &NOREG,
362        );
363    }
364}
365
366/// `KORTESTD`.
367///
368/// Supported operand variants:
369///
370/// ```text
371/// +---+------------+
372/// | # | Operands   |
373/// +---+------------+
374/// | 1 | KReg, KReg |
375/// +---+------------+
376/// ```
377pub trait KortestdEmitter<A, B> {
378    fn kortestd(&mut self, op0: A, op1: B);
379}
380
381impl<'a> KortestdEmitter<KReg, KReg> for Assembler<'a> {
382    fn kortestd(&mut self, op0: KReg, op1: KReg) {
383        self.emit(
384            KORTESTDKK,
385            op0.as_operand(),
386            op1.as_operand(),
387            &NOREG,
388            &NOREG,
389        );
390    }
391}
392
393/// `KORTESTQ`.
394///
395/// Supported operand variants:
396///
397/// ```text
398/// +---+------------+
399/// | # | Operands   |
400/// +---+------------+
401/// | 1 | KReg, KReg |
402/// +---+------------+
403/// ```
404pub trait KortestqEmitter<A, B> {
405    fn kortestq(&mut self, op0: A, op1: B);
406}
407
408impl<'a> KortestqEmitter<KReg, KReg> for Assembler<'a> {
409    fn kortestq(&mut self, op0: KReg, op1: KReg) {
410        self.emit(
411            KORTESTQKK,
412            op0.as_operand(),
413            op1.as_operand(),
414            &NOREG,
415            &NOREG,
416        );
417    }
418}
419
420/// `KSHIFTLD`.
421///
422/// Supported operand variants:
423///
424/// ```text
425/// +---+-----------------+
426/// | # | Operands        |
427/// +---+-----------------+
428/// | 1 | KReg, KReg, Imm |
429/// +---+-----------------+
430/// ```
431pub trait KshiftldEmitter<A, B, C> {
432    fn kshiftld(&mut self, op0: A, op1: B, op2: C);
433}
434
435impl<'a> KshiftldEmitter<KReg, KReg, Imm> for Assembler<'a> {
436    fn kshiftld(&mut self, op0: KReg, op1: KReg, op2: Imm) {
437        self.emit(
438            KSHIFTLDKKI,
439            op0.as_operand(),
440            op1.as_operand(),
441            op2.as_operand(),
442            &NOREG,
443        );
444    }
445}
446
447/// `KSHIFTLQ`.
448///
449/// Supported operand variants:
450///
451/// ```text
452/// +---+-----------------+
453/// | # | Operands        |
454/// +---+-----------------+
455/// | 1 | KReg, KReg, Imm |
456/// +---+-----------------+
457/// ```
458pub trait KshiftlqEmitter<A, B, C> {
459    fn kshiftlq(&mut self, op0: A, op1: B, op2: C);
460}
461
462impl<'a> KshiftlqEmitter<KReg, KReg, Imm> for Assembler<'a> {
463    fn kshiftlq(&mut self, op0: KReg, op1: KReg, op2: Imm) {
464        self.emit(
465            KSHIFTLQKKI,
466            op0.as_operand(),
467            op1.as_operand(),
468            op2.as_operand(),
469            &NOREG,
470        );
471    }
472}
473
474/// `KSHIFTRD`.
475///
476/// Supported operand variants:
477///
478/// ```text
479/// +---+-----------------+
480/// | # | Operands        |
481/// +---+-----------------+
482/// | 1 | KReg, KReg, Imm |
483/// +---+-----------------+
484/// ```
485pub trait KshiftrdEmitter<A, B, C> {
486    fn kshiftrd(&mut self, op0: A, op1: B, op2: C);
487}
488
489impl<'a> KshiftrdEmitter<KReg, KReg, Imm> for Assembler<'a> {
490    fn kshiftrd(&mut self, op0: KReg, op1: KReg, op2: Imm) {
491        self.emit(
492            KSHIFTRDKKI,
493            op0.as_operand(),
494            op1.as_operand(),
495            op2.as_operand(),
496            &NOREG,
497        );
498    }
499}
500
501/// `KSHIFTRQ`.
502///
503/// Supported operand variants:
504///
505/// ```text
506/// +---+-----------------+
507/// | # | Operands        |
508/// +---+-----------------+
509/// | 1 | KReg, KReg, Imm |
510/// +---+-----------------+
511/// ```
512pub trait KshiftrqEmitter<A, B, C> {
513    fn kshiftrq(&mut self, op0: A, op1: B, op2: C);
514}
515
516impl<'a> KshiftrqEmitter<KReg, KReg, Imm> for Assembler<'a> {
517    fn kshiftrq(&mut self, op0: KReg, op1: KReg, op2: Imm) {
518        self.emit(
519            KSHIFTRQKKI,
520            op0.as_operand(),
521            op1.as_operand(),
522            op2.as_operand(),
523            &NOREG,
524        );
525    }
526}
527
528/// `KTESTD`.
529///
530/// Supported operand variants:
531///
532/// ```text
533/// +---+------------+
534/// | # | Operands   |
535/// +---+------------+
536/// | 1 | KReg, KReg |
537/// +---+------------+
538/// ```
539pub trait KtestdEmitter<A, B> {
540    fn ktestd(&mut self, op0: A, op1: B);
541}
542
543impl<'a> KtestdEmitter<KReg, KReg> for Assembler<'a> {
544    fn ktestd(&mut self, op0: KReg, op1: KReg) {
545        self.emit(KTESTDKK, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
546    }
547}
548
549/// `KTESTQ`.
550///
551/// Supported operand variants:
552///
553/// ```text
554/// +---+------------+
555/// | # | Operands   |
556/// +---+------------+
557/// | 1 | KReg, KReg |
558/// +---+------------+
559/// ```
560pub trait KtestqEmitter<A, B> {
561    fn ktestq(&mut self, op0: A, op1: B);
562}
563
564impl<'a> KtestqEmitter<KReg, KReg> for Assembler<'a> {
565    fn ktestq(&mut self, op0: KReg, op1: KReg) {
566        self.emit(KTESTQKK, op0.as_operand(), op1.as_operand(), &NOREG, &NOREG);
567    }
568}
569
570/// `KUNPCKDQ`.
571///
572/// Supported operand variants:
573///
574/// ```text
575/// +---+------------------+
576/// | # | Operands         |
577/// +---+------------------+
578/// | 1 | KReg, KReg, KReg |
579/// +---+------------------+
580/// ```
581pub trait KunpckdqEmitter<A, B, C> {
582    fn kunpckdq(&mut self, op0: A, op1: B, op2: C);
583}
584
585impl<'a> KunpckdqEmitter<KReg, KReg, KReg> for Assembler<'a> {
586    fn kunpckdq(&mut self, op0: KReg, op1: KReg, op2: KReg) {
587        self.emit(
588            KUNPCKDQKKK,
589            op0.as_operand(),
590            op1.as_operand(),
591            op2.as_operand(),
592            &NOREG,
593        );
594    }
595}
596
597/// `KUNPCKWD`.
598///
599/// Supported operand variants:
600///
601/// ```text
602/// +---+------------------+
603/// | # | Operands         |
604/// +---+------------------+
605/// | 1 | KReg, KReg, KReg |
606/// +---+------------------+
607/// ```
608pub trait KunpckwdEmitter<A, B, C> {
609    fn kunpckwd(&mut self, op0: A, op1: B, op2: C);
610}
611
612impl<'a> KunpckwdEmitter<KReg, KReg, KReg> for Assembler<'a> {
613    fn kunpckwd(&mut self, op0: KReg, op1: KReg, op2: KReg) {
614        self.emit(
615            KUNPCKWDKKK,
616            op0.as_operand(),
617            op1.as_operand(),
618            op2.as_operand(),
619            &NOREG,
620        );
621    }
622}
623
624/// `KXNORD`.
625///
626/// Supported operand variants:
627///
628/// ```text
629/// +---+------------------+
630/// | # | Operands         |
631/// +---+------------------+
632/// | 1 | KReg, KReg, KReg |
633/// +---+------------------+
634/// ```
635pub trait KxnordEmitter<A, B, C> {
636    fn kxnord(&mut self, op0: A, op1: B, op2: C);
637}
638
639impl<'a> KxnordEmitter<KReg, KReg, KReg> for Assembler<'a> {
640    fn kxnord(&mut self, op0: KReg, op1: KReg, op2: KReg) {
641        self.emit(
642            KXNORDKKK,
643            op0.as_operand(),
644            op1.as_operand(),
645            op2.as_operand(),
646            &NOREG,
647        );
648    }
649}
650
651/// `KXNORQ`.
652///
653/// Supported operand variants:
654///
655/// ```text
656/// +---+------------------+
657/// | # | Operands         |
658/// +---+------------------+
659/// | 1 | KReg, KReg, KReg |
660/// +---+------------------+
661/// ```
662pub trait KxnorqEmitter<A, B, C> {
663    fn kxnorq(&mut self, op0: A, op1: B, op2: C);
664}
665
666impl<'a> KxnorqEmitter<KReg, KReg, KReg> for Assembler<'a> {
667    fn kxnorq(&mut self, op0: KReg, op1: KReg, op2: KReg) {
668        self.emit(
669            KXNORQKKK,
670            op0.as_operand(),
671            op1.as_operand(),
672            op2.as_operand(),
673            &NOREG,
674        );
675    }
676}
677
678/// `KXORD`.
679///
680/// Supported operand variants:
681///
682/// ```text
683/// +---+------------------+
684/// | # | Operands         |
685/// +---+------------------+
686/// | 1 | KReg, KReg, KReg |
687/// +---+------------------+
688/// ```
689pub trait KxordEmitter<A, B, C> {
690    fn kxord(&mut self, op0: A, op1: B, op2: C);
691}
692
693impl<'a> KxordEmitter<KReg, KReg, KReg> for Assembler<'a> {
694    fn kxord(&mut self, op0: KReg, op1: KReg, op2: KReg) {
695        self.emit(
696            KXORDKKK,
697            op0.as_operand(),
698            op1.as_operand(),
699            op2.as_operand(),
700            &NOREG,
701        );
702    }
703}
704
705/// `KXORQ`.
706///
707/// Supported operand variants:
708///
709/// ```text
710/// +---+------------------+
711/// | # | Operands         |
712/// +---+------------------+
713/// | 1 | KReg, KReg, KReg |
714/// +---+------------------+
715/// ```
716pub trait KxorqEmitter<A, B, C> {
717    fn kxorq(&mut self, op0: A, op1: B, op2: C);
718}
719
720impl<'a> KxorqEmitter<KReg, KReg, KReg> for Assembler<'a> {
721    fn kxorq(&mut self, op0: KReg, op1: KReg, op2: KReg) {
722        self.emit(
723            KXORQKKK,
724            op0.as_operand(),
725            op1.as_operand(),
726            op2.as_operand(),
727            &NOREG,
728        );
729    }
730}
731
732/// `VDBPSADBW`.
733///
734/// Supported operand variants:
735///
736/// ```text
737/// +---+--------------------+
738/// | # | Operands           |
739/// +---+--------------------+
740/// | 1 | Xmm, Xmm, Mem, Imm |
741/// | 2 | Xmm, Xmm, Xmm, Imm |
742/// | 3 | Ymm, Ymm, Mem, Imm |
743/// | 4 | Ymm, Ymm, Ymm, Imm |
744/// | 5 | Zmm, Zmm, Mem, Imm |
745/// | 6 | Zmm, Zmm, Zmm, Imm |
746/// +---+--------------------+
747/// ```
748pub trait VdbpsadbwEmitter<A, B, C, D> {
749    fn vdbpsadbw(&mut self, op0: A, op1: B, op2: C, op3: D);
750}
751
752impl<'a> VdbpsadbwEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
753    fn vdbpsadbw(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
754        self.emit(
755            VDBPSADBW128RRRI,
756            op0.as_operand(),
757            op1.as_operand(),
758            op2.as_operand(),
759            op3.as_operand(),
760        );
761    }
762}
763
764impl<'a> VdbpsadbwEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
765    fn vdbpsadbw(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
766        self.emit(
767            VDBPSADBW128RRMI,
768            op0.as_operand(),
769            op1.as_operand(),
770            op2.as_operand(),
771            op3.as_operand(),
772        );
773    }
774}
775
776impl<'a> VdbpsadbwEmitter<Ymm, Ymm, Ymm, Imm> for Assembler<'a> {
777    fn vdbpsadbw(&mut self, op0: Ymm, op1: Ymm, op2: Ymm, op3: Imm) {
778        self.emit(
779            VDBPSADBW256RRRI,
780            op0.as_operand(),
781            op1.as_operand(),
782            op2.as_operand(),
783            op3.as_operand(),
784        );
785    }
786}
787
788impl<'a> VdbpsadbwEmitter<Ymm, Ymm, Mem, Imm> for Assembler<'a> {
789    fn vdbpsadbw(&mut self, op0: Ymm, op1: Ymm, op2: Mem, op3: Imm) {
790        self.emit(
791            VDBPSADBW256RRMI,
792            op0.as_operand(),
793            op1.as_operand(),
794            op2.as_operand(),
795            op3.as_operand(),
796        );
797    }
798}
799
800impl<'a> VdbpsadbwEmitter<Zmm, Zmm, Zmm, Imm> for Assembler<'a> {
801    fn vdbpsadbw(&mut self, op0: Zmm, op1: Zmm, op2: Zmm, op3: Imm) {
802        self.emit(
803            VDBPSADBW512RRRI,
804            op0.as_operand(),
805            op1.as_operand(),
806            op2.as_operand(),
807            op3.as_operand(),
808        );
809    }
810}
811
812impl<'a> VdbpsadbwEmitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
813    fn vdbpsadbw(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
814        self.emit(
815            VDBPSADBW512RRMI,
816            op0.as_operand(),
817            op1.as_operand(),
818            op2.as_operand(),
819            op3.as_operand(),
820        );
821    }
822}
823
824/// `VDBPSADBW_MASK`.
825///
826/// Supported operand variants:
827///
828/// ```text
829/// +---+--------------------+
830/// | # | Operands           |
831/// +---+--------------------+
832/// | 1 | Xmm, Xmm, Mem, Imm |
833/// | 2 | Xmm, Xmm, Xmm, Imm |
834/// | 3 | Ymm, Ymm, Mem, Imm |
835/// | 4 | Ymm, Ymm, Ymm, Imm |
836/// | 5 | Zmm, Zmm, Mem, Imm |
837/// | 6 | Zmm, Zmm, Zmm, Imm |
838/// +---+--------------------+
839/// ```
840pub trait VdbpsadbwMaskEmitter<A, B, C, D> {
841    fn vdbpsadbw_mask(&mut self, op0: A, op1: B, op2: C, op3: D);
842}
843
844impl<'a> VdbpsadbwMaskEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
845    fn vdbpsadbw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
846        self.emit(
847            VDBPSADBW128RRRI_MASK,
848            op0.as_operand(),
849            op1.as_operand(),
850            op2.as_operand(),
851            op3.as_operand(),
852        );
853    }
854}
855
856impl<'a> VdbpsadbwMaskEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
857    fn vdbpsadbw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
858        self.emit(
859            VDBPSADBW128RRMI_MASK,
860            op0.as_operand(),
861            op1.as_operand(),
862            op2.as_operand(),
863            op3.as_operand(),
864        );
865    }
866}
867
868impl<'a> VdbpsadbwMaskEmitter<Ymm, Ymm, Ymm, Imm> for Assembler<'a> {
869    fn vdbpsadbw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm, op3: Imm) {
870        self.emit(
871            VDBPSADBW256RRRI_MASK,
872            op0.as_operand(),
873            op1.as_operand(),
874            op2.as_operand(),
875            op3.as_operand(),
876        );
877    }
878}
879
880impl<'a> VdbpsadbwMaskEmitter<Ymm, Ymm, Mem, Imm> for Assembler<'a> {
881    fn vdbpsadbw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem, op3: Imm) {
882        self.emit(
883            VDBPSADBW256RRMI_MASK,
884            op0.as_operand(),
885            op1.as_operand(),
886            op2.as_operand(),
887            op3.as_operand(),
888        );
889    }
890}
891
892impl<'a> VdbpsadbwMaskEmitter<Zmm, Zmm, Zmm, Imm> for Assembler<'a> {
893    fn vdbpsadbw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm, op3: Imm) {
894        self.emit(
895            VDBPSADBW512RRRI_MASK,
896            op0.as_operand(),
897            op1.as_operand(),
898            op2.as_operand(),
899            op3.as_operand(),
900        );
901    }
902}
903
904impl<'a> VdbpsadbwMaskEmitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
905    fn vdbpsadbw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
906        self.emit(
907            VDBPSADBW512RRMI_MASK,
908            op0.as_operand(),
909            op1.as_operand(),
910            op2.as_operand(),
911            op3.as_operand(),
912        );
913    }
914}
915
916/// `VDBPSADBW_MASKZ`.
917///
918/// Supported operand variants:
919///
920/// ```text
921/// +---+--------------------+
922/// | # | Operands           |
923/// +---+--------------------+
924/// | 1 | Xmm, Xmm, Mem, Imm |
925/// | 2 | Xmm, Xmm, Xmm, Imm |
926/// | 3 | Ymm, Ymm, Mem, Imm |
927/// | 4 | Ymm, Ymm, Ymm, Imm |
928/// | 5 | Zmm, Zmm, Mem, Imm |
929/// | 6 | Zmm, Zmm, Zmm, Imm |
930/// +---+--------------------+
931/// ```
932pub trait VdbpsadbwMaskzEmitter<A, B, C, D> {
933    fn vdbpsadbw_maskz(&mut self, op0: A, op1: B, op2: C, op3: D);
934}
935
936impl<'a> VdbpsadbwMaskzEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
937    fn vdbpsadbw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
938        self.emit(
939            VDBPSADBW128RRRI_MASKZ,
940            op0.as_operand(),
941            op1.as_operand(),
942            op2.as_operand(),
943            op3.as_operand(),
944        );
945    }
946}
947
948impl<'a> VdbpsadbwMaskzEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
949    fn vdbpsadbw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
950        self.emit(
951            VDBPSADBW128RRMI_MASKZ,
952            op0.as_operand(),
953            op1.as_operand(),
954            op2.as_operand(),
955            op3.as_operand(),
956        );
957    }
958}
959
960impl<'a> VdbpsadbwMaskzEmitter<Ymm, Ymm, Ymm, Imm> for Assembler<'a> {
961    fn vdbpsadbw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm, op3: Imm) {
962        self.emit(
963            VDBPSADBW256RRRI_MASKZ,
964            op0.as_operand(),
965            op1.as_operand(),
966            op2.as_operand(),
967            op3.as_operand(),
968        );
969    }
970}
971
972impl<'a> VdbpsadbwMaskzEmitter<Ymm, Ymm, Mem, Imm> for Assembler<'a> {
973    fn vdbpsadbw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem, op3: Imm) {
974        self.emit(
975            VDBPSADBW256RRMI_MASKZ,
976            op0.as_operand(),
977            op1.as_operand(),
978            op2.as_operand(),
979            op3.as_operand(),
980        );
981    }
982}
983
984impl<'a> VdbpsadbwMaskzEmitter<Zmm, Zmm, Zmm, Imm> for Assembler<'a> {
985    fn vdbpsadbw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm, op3: Imm) {
986        self.emit(
987            VDBPSADBW512RRRI_MASKZ,
988            op0.as_operand(),
989            op1.as_operand(),
990            op2.as_operand(),
991            op3.as_operand(),
992        );
993    }
994}
995
996impl<'a> VdbpsadbwMaskzEmitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
997    fn vdbpsadbw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
998        self.emit(
999            VDBPSADBW512RRMI_MASKZ,
1000            op0.as_operand(),
1001            op1.as_operand(),
1002            op2.as_operand(),
1003            op3.as_operand(),
1004        );
1005    }
1006}
1007
1008/// `VMOVDQU16`.
1009///
1010/// Supported operand variants:
1011///
1012/// ```text
1013/// +---+----------+
1014/// | # | Operands |
1015/// +---+----------+
1016/// | 1 | Mem, Xmm |
1017/// | 2 | Mem, Ymm |
1018/// | 3 | Mem, Zmm |
1019/// | 4 | Xmm, Mem |
1020/// | 5 | Xmm, Xmm |
1021/// | 6 | Ymm, Mem |
1022/// | 7 | Ymm, Ymm |
1023/// | 8 | Zmm, Mem |
1024/// | 9 | Zmm, Zmm |
1025/// +---+----------+
1026/// ```
1027pub trait Vmovdqu16Emitter<A, B> {
1028    fn vmovdqu16(&mut self, op0: A, op1: B);
1029}
1030
1031impl<'a> Vmovdqu16Emitter<Xmm, Xmm> for Assembler<'a> {
1032    fn vmovdqu16(&mut self, op0: Xmm, op1: Xmm) {
1033        self.emit(
1034            VMOVDQU16_128RR,
1035            op0.as_operand(),
1036            op1.as_operand(),
1037            &NOREG,
1038            &NOREG,
1039        );
1040    }
1041}
1042
1043impl<'a> Vmovdqu16Emitter<Xmm, Mem> for Assembler<'a> {
1044    fn vmovdqu16(&mut self, op0: Xmm, op1: Mem) {
1045        self.emit(
1046            VMOVDQU16_128RM,
1047            op0.as_operand(),
1048            op1.as_operand(),
1049            &NOREG,
1050            &NOREG,
1051        );
1052    }
1053}
1054
1055impl<'a> Vmovdqu16Emitter<Ymm, Ymm> for Assembler<'a> {
1056    fn vmovdqu16(&mut self, op0: Ymm, op1: Ymm) {
1057        self.emit(
1058            VMOVDQU16_256RR,
1059            op0.as_operand(),
1060            op1.as_operand(),
1061            &NOREG,
1062            &NOREG,
1063        );
1064    }
1065}
1066
1067impl<'a> Vmovdqu16Emitter<Ymm, Mem> for Assembler<'a> {
1068    fn vmovdqu16(&mut self, op0: Ymm, op1: Mem) {
1069        self.emit(
1070            VMOVDQU16_256RM,
1071            op0.as_operand(),
1072            op1.as_operand(),
1073            &NOREG,
1074            &NOREG,
1075        );
1076    }
1077}
1078
1079impl<'a> Vmovdqu16Emitter<Zmm, Zmm> for Assembler<'a> {
1080    fn vmovdqu16(&mut self, op0: Zmm, op1: Zmm) {
1081        self.emit(
1082            VMOVDQU16_512RR,
1083            op0.as_operand(),
1084            op1.as_operand(),
1085            &NOREG,
1086            &NOREG,
1087        );
1088    }
1089}
1090
1091impl<'a> Vmovdqu16Emitter<Zmm, Mem> for Assembler<'a> {
1092    fn vmovdqu16(&mut self, op0: Zmm, op1: Mem) {
1093        self.emit(
1094            VMOVDQU16_512RM,
1095            op0.as_operand(),
1096            op1.as_operand(),
1097            &NOREG,
1098            &NOREG,
1099        );
1100    }
1101}
1102
1103impl<'a> Vmovdqu16Emitter<Mem, Xmm> for Assembler<'a> {
1104    fn vmovdqu16(&mut self, op0: Mem, op1: Xmm) {
1105        self.emit(
1106            VMOVDQU16_128MR,
1107            op0.as_operand(),
1108            op1.as_operand(),
1109            &NOREG,
1110            &NOREG,
1111        );
1112    }
1113}
1114
1115impl<'a> Vmovdqu16Emitter<Mem, Ymm> for Assembler<'a> {
1116    fn vmovdqu16(&mut self, op0: Mem, op1: Ymm) {
1117        self.emit(
1118            VMOVDQU16_256MR,
1119            op0.as_operand(),
1120            op1.as_operand(),
1121            &NOREG,
1122            &NOREG,
1123        );
1124    }
1125}
1126
1127impl<'a> Vmovdqu16Emitter<Mem, Zmm> for Assembler<'a> {
1128    fn vmovdqu16(&mut self, op0: Mem, op1: Zmm) {
1129        self.emit(
1130            VMOVDQU16_512MR,
1131            op0.as_operand(),
1132            op1.as_operand(),
1133            &NOREG,
1134            &NOREG,
1135        );
1136    }
1137}
1138
1139/// `VMOVDQU16_MASK`.
1140///
1141/// Supported operand variants:
1142///
1143/// ```text
1144/// +---+----------+
1145/// | # | Operands |
1146/// +---+----------+
1147/// | 1 | Mem, Xmm |
1148/// | 2 | Mem, Ymm |
1149/// | 3 | Mem, Zmm |
1150/// | 4 | Xmm, Mem |
1151/// | 5 | Xmm, Xmm |
1152/// | 6 | Ymm, Mem |
1153/// | 7 | Ymm, Ymm |
1154/// | 8 | Zmm, Mem |
1155/// | 9 | Zmm, Zmm |
1156/// +---+----------+
1157/// ```
1158pub trait Vmovdqu16MaskEmitter<A, B> {
1159    fn vmovdqu16_mask(&mut self, op0: A, op1: B);
1160}
1161
1162impl<'a> Vmovdqu16MaskEmitter<Xmm, Xmm> for Assembler<'a> {
1163    fn vmovdqu16_mask(&mut self, op0: Xmm, op1: Xmm) {
1164        self.emit(
1165            VMOVDQU16_128RR_MASK,
1166            op0.as_operand(),
1167            op1.as_operand(),
1168            &NOREG,
1169            &NOREG,
1170        );
1171    }
1172}
1173
1174impl<'a> Vmovdqu16MaskEmitter<Xmm, Mem> for Assembler<'a> {
1175    fn vmovdqu16_mask(&mut self, op0: Xmm, op1: Mem) {
1176        self.emit(
1177            VMOVDQU16_128RM_MASK,
1178            op0.as_operand(),
1179            op1.as_operand(),
1180            &NOREG,
1181            &NOREG,
1182        );
1183    }
1184}
1185
1186impl<'a> Vmovdqu16MaskEmitter<Ymm, Ymm> for Assembler<'a> {
1187    fn vmovdqu16_mask(&mut self, op0: Ymm, op1: Ymm) {
1188        self.emit(
1189            VMOVDQU16_256RR_MASK,
1190            op0.as_operand(),
1191            op1.as_operand(),
1192            &NOREG,
1193            &NOREG,
1194        );
1195    }
1196}
1197
1198impl<'a> Vmovdqu16MaskEmitter<Ymm, Mem> for Assembler<'a> {
1199    fn vmovdqu16_mask(&mut self, op0: Ymm, op1: Mem) {
1200        self.emit(
1201            VMOVDQU16_256RM_MASK,
1202            op0.as_operand(),
1203            op1.as_operand(),
1204            &NOREG,
1205            &NOREG,
1206        );
1207    }
1208}
1209
1210impl<'a> Vmovdqu16MaskEmitter<Zmm, Zmm> for Assembler<'a> {
1211    fn vmovdqu16_mask(&mut self, op0: Zmm, op1: Zmm) {
1212        self.emit(
1213            VMOVDQU16_512RR_MASK,
1214            op0.as_operand(),
1215            op1.as_operand(),
1216            &NOREG,
1217            &NOREG,
1218        );
1219    }
1220}
1221
1222impl<'a> Vmovdqu16MaskEmitter<Zmm, Mem> for Assembler<'a> {
1223    fn vmovdqu16_mask(&mut self, op0: Zmm, op1: Mem) {
1224        self.emit(
1225            VMOVDQU16_512RM_MASK,
1226            op0.as_operand(),
1227            op1.as_operand(),
1228            &NOREG,
1229            &NOREG,
1230        );
1231    }
1232}
1233
1234impl<'a> Vmovdqu16MaskEmitter<Mem, Xmm> for Assembler<'a> {
1235    fn vmovdqu16_mask(&mut self, op0: Mem, op1: Xmm) {
1236        self.emit(
1237            VMOVDQU16_128MR_MASK,
1238            op0.as_operand(),
1239            op1.as_operand(),
1240            &NOREG,
1241            &NOREG,
1242        );
1243    }
1244}
1245
1246impl<'a> Vmovdqu16MaskEmitter<Mem, Ymm> for Assembler<'a> {
1247    fn vmovdqu16_mask(&mut self, op0: Mem, op1: Ymm) {
1248        self.emit(
1249            VMOVDQU16_256MR_MASK,
1250            op0.as_operand(),
1251            op1.as_operand(),
1252            &NOREG,
1253            &NOREG,
1254        );
1255    }
1256}
1257
1258impl<'a> Vmovdqu16MaskEmitter<Mem, Zmm> for Assembler<'a> {
1259    fn vmovdqu16_mask(&mut self, op0: Mem, op1: Zmm) {
1260        self.emit(
1261            VMOVDQU16_512MR_MASK,
1262            op0.as_operand(),
1263            op1.as_operand(),
1264            &NOREG,
1265            &NOREG,
1266        );
1267    }
1268}
1269
1270/// `VMOVDQU16_MASKZ`.
1271///
1272/// Supported operand variants:
1273///
1274/// ```text
1275/// +---+----------+
1276/// | # | Operands |
1277/// +---+----------+
1278/// | 1 | Xmm, Mem |
1279/// | 2 | Xmm, Xmm |
1280/// | 3 | Ymm, Mem |
1281/// | 4 | Ymm, Ymm |
1282/// | 5 | Zmm, Mem |
1283/// | 6 | Zmm, Zmm |
1284/// +---+----------+
1285/// ```
1286pub trait Vmovdqu16MaskzEmitter<A, B> {
1287    fn vmovdqu16_maskz(&mut self, op0: A, op1: B);
1288}
1289
1290impl<'a> Vmovdqu16MaskzEmitter<Xmm, Xmm> for Assembler<'a> {
1291    fn vmovdqu16_maskz(&mut self, op0: Xmm, op1: Xmm) {
1292        self.emit(
1293            VMOVDQU16_128RR_MASKZ,
1294            op0.as_operand(),
1295            op1.as_operand(),
1296            &NOREG,
1297            &NOREG,
1298        );
1299    }
1300}
1301
1302impl<'a> Vmovdqu16MaskzEmitter<Xmm, Mem> for Assembler<'a> {
1303    fn vmovdqu16_maskz(&mut self, op0: Xmm, op1: Mem) {
1304        self.emit(
1305            VMOVDQU16_128RM_MASKZ,
1306            op0.as_operand(),
1307            op1.as_operand(),
1308            &NOREG,
1309            &NOREG,
1310        );
1311    }
1312}
1313
1314impl<'a> Vmovdqu16MaskzEmitter<Ymm, Ymm> for Assembler<'a> {
1315    fn vmovdqu16_maskz(&mut self, op0: Ymm, op1: Ymm) {
1316        self.emit(
1317            VMOVDQU16_256RR_MASKZ,
1318            op0.as_operand(),
1319            op1.as_operand(),
1320            &NOREG,
1321            &NOREG,
1322        );
1323    }
1324}
1325
1326impl<'a> Vmovdqu16MaskzEmitter<Ymm, Mem> for Assembler<'a> {
1327    fn vmovdqu16_maskz(&mut self, op0: Ymm, op1: Mem) {
1328        self.emit(
1329            VMOVDQU16_256RM_MASKZ,
1330            op0.as_operand(),
1331            op1.as_operand(),
1332            &NOREG,
1333            &NOREG,
1334        );
1335    }
1336}
1337
1338impl<'a> Vmovdqu16MaskzEmitter<Zmm, Zmm> for Assembler<'a> {
1339    fn vmovdqu16_maskz(&mut self, op0: Zmm, op1: Zmm) {
1340        self.emit(
1341            VMOVDQU16_512RR_MASKZ,
1342            op0.as_operand(),
1343            op1.as_operand(),
1344            &NOREG,
1345            &NOREG,
1346        );
1347    }
1348}
1349
1350impl<'a> Vmovdqu16MaskzEmitter<Zmm, Mem> for Assembler<'a> {
1351    fn vmovdqu16_maskz(&mut self, op0: Zmm, op1: Mem) {
1352        self.emit(
1353            VMOVDQU16_512RM_MASKZ,
1354            op0.as_operand(),
1355            op1.as_operand(),
1356            &NOREG,
1357            &NOREG,
1358        );
1359    }
1360}
1361
1362/// `VMOVDQU8`.
1363///
1364/// Supported operand variants:
1365///
1366/// ```text
1367/// +---+----------+
1368/// | # | Operands |
1369/// +---+----------+
1370/// | 1 | Mem, Xmm |
1371/// | 2 | Mem, Ymm |
1372/// | 3 | Mem, Zmm |
1373/// | 4 | Xmm, Mem |
1374/// | 5 | Xmm, Xmm |
1375/// | 6 | Ymm, Mem |
1376/// | 7 | Ymm, Ymm |
1377/// | 8 | Zmm, Mem |
1378/// | 9 | Zmm, Zmm |
1379/// +---+----------+
1380/// ```
1381pub trait Vmovdqu8Emitter<A, B> {
1382    fn vmovdqu8(&mut self, op0: A, op1: B);
1383}
1384
1385impl<'a> Vmovdqu8Emitter<Xmm, Xmm> for Assembler<'a> {
1386    fn vmovdqu8(&mut self, op0: Xmm, op1: Xmm) {
1387        self.emit(
1388            VMOVDQU8_128RR,
1389            op0.as_operand(),
1390            op1.as_operand(),
1391            &NOREG,
1392            &NOREG,
1393        );
1394    }
1395}
1396
1397impl<'a> Vmovdqu8Emitter<Xmm, Mem> for Assembler<'a> {
1398    fn vmovdqu8(&mut self, op0: Xmm, op1: Mem) {
1399        self.emit(
1400            VMOVDQU8_128RM,
1401            op0.as_operand(),
1402            op1.as_operand(),
1403            &NOREG,
1404            &NOREG,
1405        );
1406    }
1407}
1408
1409impl<'a> Vmovdqu8Emitter<Ymm, Ymm> for Assembler<'a> {
1410    fn vmovdqu8(&mut self, op0: Ymm, op1: Ymm) {
1411        self.emit(
1412            VMOVDQU8_256RR,
1413            op0.as_operand(),
1414            op1.as_operand(),
1415            &NOREG,
1416            &NOREG,
1417        );
1418    }
1419}
1420
1421impl<'a> Vmovdqu8Emitter<Ymm, Mem> for Assembler<'a> {
1422    fn vmovdqu8(&mut self, op0: Ymm, op1: Mem) {
1423        self.emit(
1424            VMOVDQU8_256RM,
1425            op0.as_operand(),
1426            op1.as_operand(),
1427            &NOREG,
1428            &NOREG,
1429        );
1430    }
1431}
1432
1433impl<'a> Vmovdqu8Emitter<Zmm, Zmm> for Assembler<'a> {
1434    fn vmovdqu8(&mut self, op0: Zmm, op1: Zmm) {
1435        self.emit(
1436            VMOVDQU8_512RR,
1437            op0.as_operand(),
1438            op1.as_operand(),
1439            &NOREG,
1440            &NOREG,
1441        );
1442    }
1443}
1444
1445impl<'a> Vmovdqu8Emitter<Zmm, Mem> for Assembler<'a> {
1446    fn vmovdqu8(&mut self, op0: Zmm, op1: Mem) {
1447        self.emit(
1448            VMOVDQU8_512RM,
1449            op0.as_operand(),
1450            op1.as_operand(),
1451            &NOREG,
1452            &NOREG,
1453        );
1454    }
1455}
1456
1457impl<'a> Vmovdqu8Emitter<Mem, Xmm> for Assembler<'a> {
1458    fn vmovdqu8(&mut self, op0: Mem, op1: Xmm) {
1459        self.emit(
1460            VMOVDQU8_128MR,
1461            op0.as_operand(),
1462            op1.as_operand(),
1463            &NOREG,
1464            &NOREG,
1465        );
1466    }
1467}
1468
1469impl<'a> Vmovdqu8Emitter<Mem, Ymm> for Assembler<'a> {
1470    fn vmovdqu8(&mut self, op0: Mem, op1: Ymm) {
1471        self.emit(
1472            VMOVDQU8_256MR,
1473            op0.as_operand(),
1474            op1.as_operand(),
1475            &NOREG,
1476            &NOREG,
1477        );
1478    }
1479}
1480
1481impl<'a> Vmovdqu8Emitter<Mem, Zmm> for Assembler<'a> {
1482    fn vmovdqu8(&mut self, op0: Mem, op1: Zmm) {
1483        self.emit(
1484            VMOVDQU8_512MR,
1485            op0.as_operand(),
1486            op1.as_operand(),
1487            &NOREG,
1488            &NOREG,
1489        );
1490    }
1491}
1492
1493/// `VMOVDQU8_MASK`.
1494///
1495/// Supported operand variants:
1496///
1497/// ```text
1498/// +---+----------+
1499/// | # | Operands |
1500/// +---+----------+
1501/// | 1 | Mem, Xmm |
1502/// | 2 | Mem, Ymm |
1503/// | 3 | Mem, Zmm |
1504/// | 4 | Xmm, Mem |
1505/// | 5 | Xmm, Xmm |
1506/// | 6 | Ymm, Mem |
1507/// | 7 | Ymm, Ymm |
1508/// | 8 | Zmm, Mem |
1509/// | 9 | Zmm, Zmm |
1510/// +---+----------+
1511/// ```
1512pub trait Vmovdqu8MaskEmitter<A, B> {
1513    fn vmovdqu8_mask(&mut self, op0: A, op1: B);
1514}
1515
1516impl<'a> Vmovdqu8MaskEmitter<Xmm, Xmm> for Assembler<'a> {
1517    fn vmovdqu8_mask(&mut self, op0: Xmm, op1: Xmm) {
1518        self.emit(
1519            VMOVDQU8_128RR_MASK,
1520            op0.as_operand(),
1521            op1.as_operand(),
1522            &NOREG,
1523            &NOREG,
1524        );
1525    }
1526}
1527
1528impl<'a> Vmovdqu8MaskEmitter<Xmm, Mem> for Assembler<'a> {
1529    fn vmovdqu8_mask(&mut self, op0: Xmm, op1: Mem) {
1530        self.emit(
1531            VMOVDQU8_128RM_MASK,
1532            op0.as_operand(),
1533            op1.as_operand(),
1534            &NOREG,
1535            &NOREG,
1536        );
1537    }
1538}
1539
1540impl<'a> Vmovdqu8MaskEmitter<Ymm, Ymm> for Assembler<'a> {
1541    fn vmovdqu8_mask(&mut self, op0: Ymm, op1: Ymm) {
1542        self.emit(
1543            VMOVDQU8_256RR_MASK,
1544            op0.as_operand(),
1545            op1.as_operand(),
1546            &NOREG,
1547            &NOREG,
1548        );
1549    }
1550}
1551
1552impl<'a> Vmovdqu8MaskEmitter<Ymm, Mem> for Assembler<'a> {
1553    fn vmovdqu8_mask(&mut self, op0: Ymm, op1: Mem) {
1554        self.emit(
1555            VMOVDQU8_256RM_MASK,
1556            op0.as_operand(),
1557            op1.as_operand(),
1558            &NOREG,
1559            &NOREG,
1560        );
1561    }
1562}
1563
1564impl<'a> Vmovdqu8MaskEmitter<Zmm, Zmm> for Assembler<'a> {
1565    fn vmovdqu8_mask(&mut self, op0: Zmm, op1: Zmm) {
1566        self.emit(
1567            VMOVDQU8_512RR_MASK,
1568            op0.as_operand(),
1569            op1.as_operand(),
1570            &NOREG,
1571            &NOREG,
1572        );
1573    }
1574}
1575
1576impl<'a> Vmovdqu8MaskEmitter<Zmm, Mem> for Assembler<'a> {
1577    fn vmovdqu8_mask(&mut self, op0: Zmm, op1: Mem) {
1578        self.emit(
1579            VMOVDQU8_512RM_MASK,
1580            op0.as_operand(),
1581            op1.as_operand(),
1582            &NOREG,
1583            &NOREG,
1584        );
1585    }
1586}
1587
1588impl<'a> Vmovdqu8MaskEmitter<Mem, Xmm> for Assembler<'a> {
1589    fn vmovdqu8_mask(&mut self, op0: Mem, op1: Xmm) {
1590        self.emit(
1591            VMOVDQU8_128MR_MASK,
1592            op0.as_operand(),
1593            op1.as_operand(),
1594            &NOREG,
1595            &NOREG,
1596        );
1597    }
1598}
1599
1600impl<'a> Vmovdqu8MaskEmitter<Mem, Ymm> for Assembler<'a> {
1601    fn vmovdqu8_mask(&mut self, op0: Mem, op1: Ymm) {
1602        self.emit(
1603            VMOVDQU8_256MR_MASK,
1604            op0.as_operand(),
1605            op1.as_operand(),
1606            &NOREG,
1607            &NOREG,
1608        );
1609    }
1610}
1611
1612impl<'a> Vmovdqu8MaskEmitter<Mem, Zmm> for Assembler<'a> {
1613    fn vmovdqu8_mask(&mut self, op0: Mem, op1: Zmm) {
1614        self.emit(
1615            VMOVDQU8_512MR_MASK,
1616            op0.as_operand(),
1617            op1.as_operand(),
1618            &NOREG,
1619            &NOREG,
1620        );
1621    }
1622}
1623
1624/// `VMOVDQU8_MASKZ`.
1625///
1626/// Supported operand variants:
1627///
1628/// ```text
1629/// +---+----------+
1630/// | # | Operands |
1631/// +---+----------+
1632/// | 1 | Xmm, Mem |
1633/// | 2 | Xmm, Xmm |
1634/// | 3 | Ymm, Mem |
1635/// | 4 | Ymm, Ymm |
1636/// | 5 | Zmm, Mem |
1637/// | 6 | Zmm, Zmm |
1638/// +---+----------+
1639/// ```
1640pub trait Vmovdqu8MaskzEmitter<A, B> {
1641    fn vmovdqu8_maskz(&mut self, op0: A, op1: B);
1642}
1643
1644impl<'a> Vmovdqu8MaskzEmitter<Xmm, Xmm> for Assembler<'a> {
1645    fn vmovdqu8_maskz(&mut self, op0: Xmm, op1: Xmm) {
1646        self.emit(
1647            VMOVDQU8_128RR_MASKZ,
1648            op0.as_operand(),
1649            op1.as_operand(),
1650            &NOREG,
1651            &NOREG,
1652        );
1653    }
1654}
1655
1656impl<'a> Vmovdqu8MaskzEmitter<Xmm, Mem> for Assembler<'a> {
1657    fn vmovdqu8_maskz(&mut self, op0: Xmm, op1: Mem) {
1658        self.emit(
1659            VMOVDQU8_128RM_MASKZ,
1660            op0.as_operand(),
1661            op1.as_operand(),
1662            &NOREG,
1663            &NOREG,
1664        );
1665    }
1666}
1667
1668impl<'a> Vmovdqu8MaskzEmitter<Ymm, Ymm> for Assembler<'a> {
1669    fn vmovdqu8_maskz(&mut self, op0: Ymm, op1: Ymm) {
1670        self.emit(
1671            VMOVDQU8_256RR_MASKZ,
1672            op0.as_operand(),
1673            op1.as_operand(),
1674            &NOREG,
1675            &NOREG,
1676        );
1677    }
1678}
1679
1680impl<'a> Vmovdqu8MaskzEmitter<Ymm, Mem> for Assembler<'a> {
1681    fn vmovdqu8_maskz(&mut self, op0: Ymm, op1: Mem) {
1682        self.emit(
1683            VMOVDQU8_256RM_MASKZ,
1684            op0.as_operand(),
1685            op1.as_operand(),
1686            &NOREG,
1687            &NOREG,
1688        );
1689    }
1690}
1691
1692impl<'a> Vmovdqu8MaskzEmitter<Zmm, Zmm> for Assembler<'a> {
1693    fn vmovdqu8_maskz(&mut self, op0: Zmm, op1: Zmm) {
1694        self.emit(
1695            VMOVDQU8_512RR_MASKZ,
1696            op0.as_operand(),
1697            op1.as_operand(),
1698            &NOREG,
1699            &NOREG,
1700        );
1701    }
1702}
1703
1704impl<'a> Vmovdqu8MaskzEmitter<Zmm, Mem> for Assembler<'a> {
1705    fn vmovdqu8_maskz(&mut self, op0: Zmm, op1: Mem) {
1706        self.emit(
1707            VMOVDQU8_512RM_MASKZ,
1708            op0.as_operand(),
1709            op1.as_operand(),
1710            &NOREG,
1711            &NOREG,
1712        );
1713    }
1714}
1715
1716/// `VPABSB`.
1717///
1718/// Supported operand variants:
1719///
1720/// ```text
1721/// +---+----------+
1722/// | # | Operands |
1723/// +---+----------+
1724/// | 1 | Xmm, Mem |
1725/// | 2 | Xmm, Xmm |
1726/// | 3 | Ymm, Mem |
1727/// | 4 | Ymm, Ymm |
1728/// | 5 | Zmm, Mem |
1729/// | 6 | Zmm, Zmm |
1730/// +---+----------+
1731/// ```
1732pub trait VpabsbEmitter<A, B> {
1733    fn vpabsb(&mut self, op0: A, op1: B);
1734}
1735
1736impl<'a> VpabsbEmitter<Xmm, Xmm> for Assembler<'a> {
1737    fn vpabsb(&mut self, op0: Xmm, op1: Xmm) {
1738        self.emit(
1739            VPABSB128RR,
1740            op0.as_operand(),
1741            op1.as_operand(),
1742            &NOREG,
1743            &NOREG,
1744        );
1745    }
1746}
1747
1748impl<'a> VpabsbEmitter<Xmm, Mem> for Assembler<'a> {
1749    fn vpabsb(&mut self, op0: Xmm, op1: Mem) {
1750        self.emit(
1751            VPABSB128RM,
1752            op0.as_operand(),
1753            op1.as_operand(),
1754            &NOREG,
1755            &NOREG,
1756        );
1757    }
1758}
1759
1760impl<'a> VpabsbEmitter<Ymm, Ymm> for Assembler<'a> {
1761    fn vpabsb(&mut self, op0: Ymm, op1: Ymm) {
1762        self.emit(
1763            VPABSB256RR,
1764            op0.as_operand(),
1765            op1.as_operand(),
1766            &NOREG,
1767            &NOREG,
1768        );
1769    }
1770}
1771
1772impl<'a> VpabsbEmitter<Ymm, Mem> for Assembler<'a> {
1773    fn vpabsb(&mut self, op0: Ymm, op1: Mem) {
1774        self.emit(
1775            VPABSB256RM,
1776            op0.as_operand(),
1777            op1.as_operand(),
1778            &NOREG,
1779            &NOREG,
1780        );
1781    }
1782}
1783
1784impl<'a> VpabsbEmitter<Zmm, Zmm> for Assembler<'a> {
1785    fn vpabsb(&mut self, op0: Zmm, op1: Zmm) {
1786        self.emit(
1787            VPABSB512RR,
1788            op0.as_operand(),
1789            op1.as_operand(),
1790            &NOREG,
1791            &NOREG,
1792        );
1793    }
1794}
1795
1796impl<'a> VpabsbEmitter<Zmm, Mem> for Assembler<'a> {
1797    fn vpabsb(&mut self, op0: Zmm, op1: Mem) {
1798        self.emit(
1799            VPABSB512RM,
1800            op0.as_operand(),
1801            op1.as_operand(),
1802            &NOREG,
1803            &NOREG,
1804        );
1805    }
1806}
1807
1808/// `VPABSB_MASK`.
1809///
1810/// Supported operand variants:
1811///
1812/// ```text
1813/// +---+----------+
1814/// | # | Operands |
1815/// +---+----------+
1816/// | 1 | Xmm, Mem |
1817/// | 2 | Xmm, Xmm |
1818/// | 3 | Ymm, Mem |
1819/// | 4 | Ymm, Ymm |
1820/// | 5 | Zmm, Mem |
1821/// | 6 | Zmm, Zmm |
1822/// +---+----------+
1823/// ```
1824pub trait VpabsbMaskEmitter<A, B> {
1825    fn vpabsb_mask(&mut self, op0: A, op1: B);
1826}
1827
1828impl<'a> VpabsbMaskEmitter<Xmm, Xmm> for Assembler<'a> {
1829    fn vpabsb_mask(&mut self, op0: Xmm, op1: Xmm) {
1830        self.emit(
1831            VPABSB128RR_MASK,
1832            op0.as_operand(),
1833            op1.as_operand(),
1834            &NOREG,
1835            &NOREG,
1836        );
1837    }
1838}
1839
1840impl<'a> VpabsbMaskEmitter<Xmm, Mem> for Assembler<'a> {
1841    fn vpabsb_mask(&mut self, op0: Xmm, op1: Mem) {
1842        self.emit(
1843            VPABSB128RM_MASK,
1844            op0.as_operand(),
1845            op1.as_operand(),
1846            &NOREG,
1847            &NOREG,
1848        );
1849    }
1850}
1851
1852impl<'a> VpabsbMaskEmitter<Ymm, Ymm> for Assembler<'a> {
1853    fn vpabsb_mask(&mut self, op0: Ymm, op1: Ymm) {
1854        self.emit(
1855            VPABSB256RR_MASK,
1856            op0.as_operand(),
1857            op1.as_operand(),
1858            &NOREG,
1859            &NOREG,
1860        );
1861    }
1862}
1863
1864impl<'a> VpabsbMaskEmitter<Ymm, Mem> for Assembler<'a> {
1865    fn vpabsb_mask(&mut self, op0: Ymm, op1: Mem) {
1866        self.emit(
1867            VPABSB256RM_MASK,
1868            op0.as_operand(),
1869            op1.as_operand(),
1870            &NOREG,
1871            &NOREG,
1872        );
1873    }
1874}
1875
1876impl<'a> VpabsbMaskEmitter<Zmm, Zmm> for Assembler<'a> {
1877    fn vpabsb_mask(&mut self, op0: Zmm, op1: Zmm) {
1878        self.emit(
1879            VPABSB512RR_MASK,
1880            op0.as_operand(),
1881            op1.as_operand(),
1882            &NOREG,
1883            &NOREG,
1884        );
1885    }
1886}
1887
1888impl<'a> VpabsbMaskEmitter<Zmm, Mem> for Assembler<'a> {
1889    fn vpabsb_mask(&mut self, op0: Zmm, op1: Mem) {
1890        self.emit(
1891            VPABSB512RM_MASK,
1892            op0.as_operand(),
1893            op1.as_operand(),
1894            &NOREG,
1895            &NOREG,
1896        );
1897    }
1898}
1899
1900/// `VPABSB_MASKZ`.
1901///
1902/// Supported operand variants:
1903///
1904/// ```text
1905/// +---+----------+
1906/// | # | Operands |
1907/// +---+----------+
1908/// | 1 | Xmm, Mem |
1909/// | 2 | Xmm, Xmm |
1910/// | 3 | Ymm, Mem |
1911/// | 4 | Ymm, Ymm |
1912/// | 5 | Zmm, Mem |
1913/// | 6 | Zmm, Zmm |
1914/// +---+----------+
1915/// ```
1916pub trait VpabsbMaskzEmitter<A, B> {
1917    fn vpabsb_maskz(&mut self, op0: A, op1: B);
1918}
1919
1920impl<'a> VpabsbMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
1921    fn vpabsb_maskz(&mut self, op0: Xmm, op1: Xmm) {
1922        self.emit(
1923            VPABSB128RR_MASKZ,
1924            op0.as_operand(),
1925            op1.as_operand(),
1926            &NOREG,
1927            &NOREG,
1928        );
1929    }
1930}
1931
1932impl<'a> VpabsbMaskzEmitter<Xmm, Mem> for Assembler<'a> {
1933    fn vpabsb_maskz(&mut self, op0: Xmm, op1: Mem) {
1934        self.emit(
1935            VPABSB128RM_MASKZ,
1936            op0.as_operand(),
1937            op1.as_operand(),
1938            &NOREG,
1939            &NOREG,
1940        );
1941    }
1942}
1943
1944impl<'a> VpabsbMaskzEmitter<Ymm, Ymm> for Assembler<'a> {
1945    fn vpabsb_maskz(&mut self, op0: Ymm, op1: Ymm) {
1946        self.emit(
1947            VPABSB256RR_MASKZ,
1948            op0.as_operand(),
1949            op1.as_operand(),
1950            &NOREG,
1951            &NOREG,
1952        );
1953    }
1954}
1955
1956impl<'a> VpabsbMaskzEmitter<Ymm, Mem> for Assembler<'a> {
1957    fn vpabsb_maskz(&mut self, op0: Ymm, op1: Mem) {
1958        self.emit(
1959            VPABSB256RM_MASKZ,
1960            op0.as_operand(),
1961            op1.as_operand(),
1962            &NOREG,
1963            &NOREG,
1964        );
1965    }
1966}
1967
1968impl<'a> VpabsbMaskzEmitter<Zmm, Zmm> for Assembler<'a> {
1969    fn vpabsb_maskz(&mut self, op0: Zmm, op1: Zmm) {
1970        self.emit(
1971            VPABSB512RR_MASKZ,
1972            op0.as_operand(),
1973            op1.as_operand(),
1974            &NOREG,
1975            &NOREG,
1976        );
1977    }
1978}
1979
1980impl<'a> VpabsbMaskzEmitter<Zmm, Mem> for Assembler<'a> {
1981    fn vpabsb_maskz(&mut self, op0: Zmm, op1: Mem) {
1982        self.emit(
1983            VPABSB512RM_MASKZ,
1984            op0.as_operand(),
1985            op1.as_operand(),
1986            &NOREG,
1987            &NOREG,
1988        );
1989    }
1990}
1991
1992/// `VPABSW`.
1993///
1994/// Supported operand variants:
1995///
1996/// ```text
1997/// +---+----------+
1998/// | # | Operands |
1999/// +---+----------+
2000/// | 1 | Xmm, Mem |
2001/// | 2 | Xmm, Xmm |
2002/// | 3 | Ymm, Mem |
2003/// | 4 | Ymm, Ymm |
2004/// | 5 | Zmm, Mem |
2005/// | 6 | Zmm, Zmm |
2006/// +---+----------+
2007/// ```
2008pub trait VpabswEmitter<A, B> {
2009    fn vpabsw(&mut self, op0: A, op1: B);
2010}
2011
2012impl<'a> VpabswEmitter<Xmm, Xmm> for Assembler<'a> {
2013    fn vpabsw(&mut self, op0: Xmm, op1: Xmm) {
2014        self.emit(
2015            VPABSW128RR,
2016            op0.as_operand(),
2017            op1.as_operand(),
2018            &NOREG,
2019            &NOREG,
2020        );
2021    }
2022}
2023
2024impl<'a> VpabswEmitter<Xmm, Mem> for Assembler<'a> {
2025    fn vpabsw(&mut self, op0: Xmm, op1: Mem) {
2026        self.emit(
2027            VPABSW128RM,
2028            op0.as_operand(),
2029            op1.as_operand(),
2030            &NOREG,
2031            &NOREG,
2032        );
2033    }
2034}
2035
2036impl<'a> VpabswEmitter<Ymm, Ymm> for Assembler<'a> {
2037    fn vpabsw(&mut self, op0: Ymm, op1: Ymm) {
2038        self.emit(
2039            VPABSW256RR,
2040            op0.as_operand(),
2041            op1.as_operand(),
2042            &NOREG,
2043            &NOREG,
2044        );
2045    }
2046}
2047
2048impl<'a> VpabswEmitter<Ymm, Mem> for Assembler<'a> {
2049    fn vpabsw(&mut self, op0: Ymm, op1: Mem) {
2050        self.emit(
2051            VPABSW256RM,
2052            op0.as_operand(),
2053            op1.as_operand(),
2054            &NOREG,
2055            &NOREG,
2056        );
2057    }
2058}
2059
2060impl<'a> VpabswEmitter<Zmm, Zmm> for Assembler<'a> {
2061    fn vpabsw(&mut self, op0: Zmm, op1: Zmm) {
2062        self.emit(
2063            VPABSW512RR,
2064            op0.as_operand(),
2065            op1.as_operand(),
2066            &NOREG,
2067            &NOREG,
2068        );
2069    }
2070}
2071
2072impl<'a> VpabswEmitter<Zmm, Mem> for Assembler<'a> {
2073    fn vpabsw(&mut self, op0: Zmm, op1: Mem) {
2074        self.emit(
2075            VPABSW512RM,
2076            op0.as_operand(),
2077            op1.as_operand(),
2078            &NOREG,
2079            &NOREG,
2080        );
2081    }
2082}
2083
2084/// `VPABSW_MASK`.
2085///
2086/// Supported operand variants:
2087///
2088/// ```text
2089/// +---+----------+
2090/// | # | Operands |
2091/// +---+----------+
2092/// | 1 | Xmm, Mem |
2093/// | 2 | Xmm, Xmm |
2094/// | 3 | Ymm, Mem |
2095/// | 4 | Ymm, Ymm |
2096/// | 5 | Zmm, Mem |
2097/// | 6 | Zmm, Zmm |
2098/// +---+----------+
2099/// ```
2100pub trait VpabswMaskEmitter<A, B> {
2101    fn vpabsw_mask(&mut self, op0: A, op1: B);
2102}
2103
2104impl<'a> VpabswMaskEmitter<Xmm, Xmm> for Assembler<'a> {
2105    fn vpabsw_mask(&mut self, op0: Xmm, op1: Xmm) {
2106        self.emit(
2107            VPABSW128RR_MASK,
2108            op0.as_operand(),
2109            op1.as_operand(),
2110            &NOREG,
2111            &NOREG,
2112        );
2113    }
2114}
2115
2116impl<'a> VpabswMaskEmitter<Xmm, Mem> for Assembler<'a> {
2117    fn vpabsw_mask(&mut self, op0: Xmm, op1: Mem) {
2118        self.emit(
2119            VPABSW128RM_MASK,
2120            op0.as_operand(),
2121            op1.as_operand(),
2122            &NOREG,
2123            &NOREG,
2124        );
2125    }
2126}
2127
2128impl<'a> VpabswMaskEmitter<Ymm, Ymm> for Assembler<'a> {
2129    fn vpabsw_mask(&mut self, op0: Ymm, op1: Ymm) {
2130        self.emit(
2131            VPABSW256RR_MASK,
2132            op0.as_operand(),
2133            op1.as_operand(),
2134            &NOREG,
2135            &NOREG,
2136        );
2137    }
2138}
2139
2140impl<'a> VpabswMaskEmitter<Ymm, Mem> for Assembler<'a> {
2141    fn vpabsw_mask(&mut self, op0: Ymm, op1: Mem) {
2142        self.emit(
2143            VPABSW256RM_MASK,
2144            op0.as_operand(),
2145            op1.as_operand(),
2146            &NOREG,
2147            &NOREG,
2148        );
2149    }
2150}
2151
2152impl<'a> VpabswMaskEmitter<Zmm, Zmm> for Assembler<'a> {
2153    fn vpabsw_mask(&mut self, op0: Zmm, op1: Zmm) {
2154        self.emit(
2155            VPABSW512RR_MASK,
2156            op0.as_operand(),
2157            op1.as_operand(),
2158            &NOREG,
2159            &NOREG,
2160        );
2161    }
2162}
2163
2164impl<'a> VpabswMaskEmitter<Zmm, Mem> for Assembler<'a> {
2165    fn vpabsw_mask(&mut self, op0: Zmm, op1: Mem) {
2166        self.emit(
2167            VPABSW512RM_MASK,
2168            op0.as_operand(),
2169            op1.as_operand(),
2170            &NOREG,
2171            &NOREG,
2172        );
2173    }
2174}
2175
2176/// `VPABSW_MASKZ`.
2177///
2178/// Supported operand variants:
2179///
2180/// ```text
2181/// +---+----------+
2182/// | # | Operands |
2183/// +---+----------+
2184/// | 1 | Xmm, Mem |
2185/// | 2 | Xmm, Xmm |
2186/// | 3 | Ymm, Mem |
2187/// | 4 | Ymm, Ymm |
2188/// | 5 | Zmm, Mem |
2189/// | 6 | Zmm, Zmm |
2190/// +---+----------+
2191/// ```
2192pub trait VpabswMaskzEmitter<A, B> {
2193    fn vpabsw_maskz(&mut self, op0: A, op1: B);
2194}
2195
2196impl<'a> VpabswMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
2197    fn vpabsw_maskz(&mut self, op0: Xmm, op1: Xmm) {
2198        self.emit(
2199            VPABSW128RR_MASKZ,
2200            op0.as_operand(),
2201            op1.as_operand(),
2202            &NOREG,
2203            &NOREG,
2204        );
2205    }
2206}
2207
2208impl<'a> VpabswMaskzEmitter<Xmm, Mem> for Assembler<'a> {
2209    fn vpabsw_maskz(&mut self, op0: Xmm, op1: Mem) {
2210        self.emit(
2211            VPABSW128RM_MASKZ,
2212            op0.as_operand(),
2213            op1.as_operand(),
2214            &NOREG,
2215            &NOREG,
2216        );
2217    }
2218}
2219
2220impl<'a> VpabswMaskzEmitter<Ymm, Ymm> for Assembler<'a> {
2221    fn vpabsw_maskz(&mut self, op0: Ymm, op1: Ymm) {
2222        self.emit(
2223            VPABSW256RR_MASKZ,
2224            op0.as_operand(),
2225            op1.as_operand(),
2226            &NOREG,
2227            &NOREG,
2228        );
2229    }
2230}
2231
2232impl<'a> VpabswMaskzEmitter<Ymm, Mem> for Assembler<'a> {
2233    fn vpabsw_maskz(&mut self, op0: Ymm, op1: Mem) {
2234        self.emit(
2235            VPABSW256RM_MASKZ,
2236            op0.as_operand(),
2237            op1.as_operand(),
2238            &NOREG,
2239            &NOREG,
2240        );
2241    }
2242}
2243
2244impl<'a> VpabswMaskzEmitter<Zmm, Zmm> for Assembler<'a> {
2245    fn vpabsw_maskz(&mut self, op0: Zmm, op1: Zmm) {
2246        self.emit(
2247            VPABSW512RR_MASKZ,
2248            op0.as_operand(),
2249            op1.as_operand(),
2250            &NOREG,
2251            &NOREG,
2252        );
2253    }
2254}
2255
2256impl<'a> VpabswMaskzEmitter<Zmm, Mem> for Assembler<'a> {
2257    fn vpabsw_maskz(&mut self, op0: Zmm, op1: Mem) {
2258        self.emit(
2259            VPABSW512RM_MASKZ,
2260            op0.as_operand(),
2261            op1.as_operand(),
2262            &NOREG,
2263            &NOREG,
2264        );
2265    }
2266}
2267
2268/// `VPACKSSDW`.
2269///
2270/// Supported operand variants:
2271///
2272/// ```text
2273/// +---+---------------+
2274/// | # | Operands      |
2275/// +---+---------------+
2276/// | 1 | Xmm, Xmm, Mem |
2277/// | 2 | Xmm, Xmm, Xmm |
2278/// | 3 | Ymm, Ymm, Mem |
2279/// | 4 | Ymm, Ymm, Ymm |
2280/// | 5 | Zmm, Zmm, Mem |
2281/// | 6 | Zmm, Zmm, Zmm |
2282/// +---+---------------+
2283/// ```
2284pub trait VpackssdwEmitter<A, B, C> {
2285    fn vpackssdw(&mut self, op0: A, op1: B, op2: C);
2286}
2287
2288impl<'a> VpackssdwEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
2289    fn vpackssdw(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
2290        self.emit(
2291            VPACKSSDW128RRR,
2292            op0.as_operand(),
2293            op1.as_operand(),
2294            op2.as_operand(),
2295            &NOREG,
2296        );
2297    }
2298}
2299
2300impl<'a> VpackssdwEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
2301    fn vpackssdw(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
2302        self.emit(
2303            VPACKSSDW128RRM,
2304            op0.as_operand(),
2305            op1.as_operand(),
2306            op2.as_operand(),
2307            &NOREG,
2308        );
2309    }
2310}
2311
2312impl<'a> VpackssdwEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
2313    fn vpackssdw(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
2314        self.emit(
2315            VPACKSSDW256RRR,
2316            op0.as_operand(),
2317            op1.as_operand(),
2318            op2.as_operand(),
2319            &NOREG,
2320        );
2321    }
2322}
2323
2324impl<'a> VpackssdwEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
2325    fn vpackssdw(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
2326        self.emit(
2327            VPACKSSDW256RRM,
2328            op0.as_operand(),
2329            op1.as_operand(),
2330            op2.as_operand(),
2331            &NOREG,
2332        );
2333    }
2334}
2335
2336impl<'a> VpackssdwEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
2337    fn vpackssdw(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
2338        self.emit(
2339            VPACKSSDW512RRR,
2340            op0.as_operand(),
2341            op1.as_operand(),
2342            op2.as_operand(),
2343            &NOREG,
2344        );
2345    }
2346}
2347
2348impl<'a> VpackssdwEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
2349    fn vpackssdw(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
2350        self.emit(
2351            VPACKSSDW512RRM,
2352            op0.as_operand(),
2353            op1.as_operand(),
2354            op2.as_operand(),
2355            &NOREG,
2356        );
2357    }
2358}
2359
2360/// `VPACKSSDW_MASK`.
2361///
2362/// Supported operand variants:
2363///
2364/// ```text
2365/// +---+---------------+
2366/// | # | Operands      |
2367/// +---+---------------+
2368/// | 1 | Xmm, Xmm, Mem |
2369/// | 2 | Xmm, Xmm, Xmm |
2370/// | 3 | Ymm, Ymm, Mem |
2371/// | 4 | Ymm, Ymm, Ymm |
2372/// | 5 | Zmm, Zmm, Mem |
2373/// | 6 | Zmm, Zmm, Zmm |
2374/// +---+---------------+
2375/// ```
2376pub trait VpackssdwMaskEmitter<A, B, C> {
2377    fn vpackssdw_mask(&mut self, op0: A, op1: B, op2: C);
2378}
2379
2380impl<'a> VpackssdwMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
2381    fn vpackssdw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
2382        self.emit(
2383            VPACKSSDW128RRR_MASK,
2384            op0.as_operand(),
2385            op1.as_operand(),
2386            op2.as_operand(),
2387            &NOREG,
2388        );
2389    }
2390}
2391
2392impl<'a> VpackssdwMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
2393    fn vpackssdw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
2394        self.emit(
2395            VPACKSSDW128RRM_MASK,
2396            op0.as_operand(),
2397            op1.as_operand(),
2398            op2.as_operand(),
2399            &NOREG,
2400        );
2401    }
2402}
2403
2404impl<'a> VpackssdwMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
2405    fn vpackssdw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
2406        self.emit(
2407            VPACKSSDW256RRR_MASK,
2408            op0.as_operand(),
2409            op1.as_operand(),
2410            op2.as_operand(),
2411            &NOREG,
2412        );
2413    }
2414}
2415
2416impl<'a> VpackssdwMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
2417    fn vpackssdw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
2418        self.emit(
2419            VPACKSSDW256RRM_MASK,
2420            op0.as_operand(),
2421            op1.as_operand(),
2422            op2.as_operand(),
2423            &NOREG,
2424        );
2425    }
2426}
2427
2428impl<'a> VpackssdwMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
2429    fn vpackssdw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
2430        self.emit(
2431            VPACKSSDW512RRR_MASK,
2432            op0.as_operand(),
2433            op1.as_operand(),
2434            op2.as_operand(),
2435            &NOREG,
2436        );
2437    }
2438}
2439
2440impl<'a> VpackssdwMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
2441    fn vpackssdw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
2442        self.emit(
2443            VPACKSSDW512RRM_MASK,
2444            op0.as_operand(),
2445            op1.as_operand(),
2446            op2.as_operand(),
2447            &NOREG,
2448        );
2449    }
2450}
2451
2452/// `VPACKSSDW_MASKZ`.
2453///
2454/// Supported operand variants:
2455///
2456/// ```text
2457/// +---+---------------+
2458/// | # | Operands      |
2459/// +---+---------------+
2460/// | 1 | Xmm, Xmm, Mem |
2461/// | 2 | Xmm, Xmm, Xmm |
2462/// | 3 | Ymm, Ymm, Mem |
2463/// | 4 | Ymm, Ymm, Ymm |
2464/// | 5 | Zmm, Zmm, Mem |
2465/// | 6 | Zmm, Zmm, Zmm |
2466/// +---+---------------+
2467/// ```
2468pub trait VpackssdwMaskzEmitter<A, B, C> {
2469    fn vpackssdw_maskz(&mut self, op0: A, op1: B, op2: C);
2470}
2471
2472impl<'a> VpackssdwMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
2473    fn vpackssdw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
2474        self.emit(
2475            VPACKSSDW128RRR_MASKZ,
2476            op0.as_operand(),
2477            op1.as_operand(),
2478            op2.as_operand(),
2479            &NOREG,
2480        );
2481    }
2482}
2483
2484impl<'a> VpackssdwMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
2485    fn vpackssdw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
2486        self.emit(
2487            VPACKSSDW128RRM_MASKZ,
2488            op0.as_operand(),
2489            op1.as_operand(),
2490            op2.as_operand(),
2491            &NOREG,
2492        );
2493    }
2494}
2495
2496impl<'a> VpackssdwMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
2497    fn vpackssdw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
2498        self.emit(
2499            VPACKSSDW256RRR_MASKZ,
2500            op0.as_operand(),
2501            op1.as_operand(),
2502            op2.as_operand(),
2503            &NOREG,
2504        );
2505    }
2506}
2507
2508impl<'a> VpackssdwMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
2509    fn vpackssdw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
2510        self.emit(
2511            VPACKSSDW256RRM_MASKZ,
2512            op0.as_operand(),
2513            op1.as_operand(),
2514            op2.as_operand(),
2515            &NOREG,
2516        );
2517    }
2518}
2519
2520impl<'a> VpackssdwMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
2521    fn vpackssdw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
2522        self.emit(
2523            VPACKSSDW512RRR_MASKZ,
2524            op0.as_operand(),
2525            op1.as_operand(),
2526            op2.as_operand(),
2527            &NOREG,
2528        );
2529    }
2530}
2531
2532impl<'a> VpackssdwMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
2533    fn vpackssdw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
2534        self.emit(
2535            VPACKSSDW512RRM_MASKZ,
2536            op0.as_operand(),
2537            op1.as_operand(),
2538            op2.as_operand(),
2539            &NOREG,
2540        );
2541    }
2542}
2543
2544/// `VPACKSSWB`.
2545///
2546/// Supported operand variants:
2547///
2548/// ```text
2549/// +---+---------------+
2550/// | # | Operands      |
2551/// +---+---------------+
2552/// | 1 | Xmm, Xmm, Mem |
2553/// | 2 | Xmm, Xmm, Xmm |
2554/// | 3 | Ymm, Ymm, Mem |
2555/// | 4 | Ymm, Ymm, Ymm |
2556/// | 5 | Zmm, Zmm, Mem |
2557/// | 6 | Zmm, Zmm, Zmm |
2558/// +---+---------------+
2559/// ```
2560pub trait VpacksswbEmitter<A, B, C> {
2561    fn vpacksswb(&mut self, op0: A, op1: B, op2: C);
2562}
2563
2564impl<'a> VpacksswbEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
2565    fn vpacksswb(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
2566        self.emit(
2567            VPACKSSWB128RRR,
2568            op0.as_operand(),
2569            op1.as_operand(),
2570            op2.as_operand(),
2571            &NOREG,
2572        );
2573    }
2574}
2575
2576impl<'a> VpacksswbEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
2577    fn vpacksswb(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
2578        self.emit(
2579            VPACKSSWB128RRM,
2580            op0.as_operand(),
2581            op1.as_operand(),
2582            op2.as_operand(),
2583            &NOREG,
2584        );
2585    }
2586}
2587
2588impl<'a> VpacksswbEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
2589    fn vpacksswb(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
2590        self.emit(
2591            VPACKSSWB256RRR,
2592            op0.as_operand(),
2593            op1.as_operand(),
2594            op2.as_operand(),
2595            &NOREG,
2596        );
2597    }
2598}
2599
2600impl<'a> VpacksswbEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
2601    fn vpacksswb(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
2602        self.emit(
2603            VPACKSSWB256RRM,
2604            op0.as_operand(),
2605            op1.as_operand(),
2606            op2.as_operand(),
2607            &NOREG,
2608        );
2609    }
2610}
2611
2612impl<'a> VpacksswbEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
2613    fn vpacksswb(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
2614        self.emit(
2615            VPACKSSWB512RRR,
2616            op0.as_operand(),
2617            op1.as_operand(),
2618            op2.as_operand(),
2619            &NOREG,
2620        );
2621    }
2622}
2623
2624impl<'a> VpacksswbEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
2625    fn vpacksswb(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
2626        self.emit(
2627            VPACKSSWB512RRM,
2628            op0.as_operand(),
2629            op1.as_operand(),
2630            op2.as_operand(),
2631            &NOREG,
2632        );
2633    }
2634}
2635
2636/// `VPACKSSWB_MASK`.
2637///
2638/// Supported operand variants:
2639///
2640/// ```text
2641/// +---+---------------+
2642/// | # | Operands      |
2643/// +---+---------------+
2644/// | 1 | Xmm, Xmm, Mem |
2645/// | 2 | Xmm, Xmm, Xmm |
2646/// | 3 | Ymm, Ymm, Mem |
2647/// | 4 | Ymm, Ymm, Ymm |
2648/// | 5 | Zmm, Zmm, Mem |
2649/// | 6 | Zmm, Zmm, Zmm |
2650/// +---+---------------+
2651/// ```
2652pub trait VpacksswbMaskEmitter<A, B, C> {
2653    fn vpacksswb_mask(&mut self, op0: A, op1: B, op2: C);
2654}
2655
2656impl<'a> VpacksswbMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
2657    fn vpacksswb_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
2658        self.emit(
2659            VPACKSSWB128RRR_MASK,
2660            op0.as_operand(),
2661            op1.as_operand(),
2662            op2.as_operand(),
2663            &NOREG,
2664        );
2665    }
2666}
2667
2668impl<'a> VpacksswbMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
2669    fn vpacksswb_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
2670        self.emit(
2671            VPACKSSWB128RRM_MASK,
2672            op0.as_operand(),
2673            op1.as_operand(),
2674            op2.as_operand(),
2675            &NOREG,
2676        );
2677    }
2678}
2679
2680impl<'a> VpacksswbMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
2681    fn vpacksswb_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
2682        self.emit(
2683            VPACKSSWB256RRR_MASK,
2684            op0.as_operand(),
2685            op1.as_operand(),
2686            op2.as_operand(),
2687            &NOREG,
2688        );
2689    }
2690}
2691
2692impl<'a> VpacksswbMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
2693    fn vpacksswb_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
2694        self.emit(
2695            VPACKSSWB256RRM_MASK,
2696            op0.as_operand(),
2697            op1.as_operand(),
2698            op2.as_operand(),
2699            &NOREG,
2700        );
2701    }
2702}
2703
2704impl<'a> VpacksswbMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
2705    fn vpacksswb_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
2706        self.emit(
2707            VPACKSSWB512RRR_MASK,
2708            op0.as_operand(),
2709            op1.as_operand(),
2710            op2.as_operand(),
2711            &NOREG,
2712        );
2713    }
2714}
2715
2716impl<'a> VpacksswbMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
2717    fn vpacksswb_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
2718        self.emit(
2719            VPACKSSWB512RRM_MASK,
2720            op0.as_operand(),
2721            op1.as_operand(),
2722            op2.as_operand(),
2723            &NOREG,
2724        );
2725    }
2726}
2727
2728/// `VPACKSSWB_MASKZ`.
2729///
2730/// Supported operand variants:
2731///
2732/// ```text
2733/// +---+---------------+
2734/// | # | Operands      |
2735/// +---+---------------+
2736/// | 1 | Xmm, Xmm, Mem |
2737/// | 2 | Xmm, Xmm, Xmm |
2738/// | 3 | Ymm, Ymm, Mem |
2739/// | 4 | Ymm, Ymm, Ymm |
2740/// | 5 | Zmm, Zmm, Mem |
2741/// | 6 | Zmm, Zmm, Zmm |
2742/// +---+---------------+
2743/// ```
2744pub trait VpacksswbMaskzEmitter<A, B, C> {
2745    fn vpacksswb_maskz(&mut self, op0: A, op1: B, op2: C);
2746}
2747
2748impl<'a> VpacksswbMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
2749    fn vpacksswb_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
2750        self.emit(
2751            VPACKSSWB128RRR_MASKZ,
2752            op0.as_operand(),
2753            op1.as_operand(),
2754            op2.as_operand(),
2755            &NOREG,
2756        );
2757    }
2758}
2759
2760impl<'a> VpacksswbMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
2761    fn vpacksswb_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
2762        self.emit(
2763            VPACKSSWB128RRM_MASKZ,
2764            op0.as_operand(),
2765            op1.as_operand(),
2766            op2.as_operand(),
2767            &NOREG,
2768        );
2769    }
2770}
2771
2772impl<'a> VpacksswbMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
2773    fn vpacksswb_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
2774        self.emit(
2775            VPACKSSWB256RRR_MASKZ,
2776            op0.as_operand(),
2777            op1.as_operand(),
2778            op2.as_operand(),
2779            &NOREG,
2780        );
2781    }
2782}
2783
2784impl<'a> VpacksswbMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
2785    fn vpacksswb_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
2786        self.emit(
2787            VPACKSSWB256RRM_MASKZ,
2788            op0.as_operand(),
2789            op1.as_operand(),
2790            op2.as_operand(),
2791            &NOREG,
2792        );
2793    }
2794}
2795
2796impl<'a> VpacksswbMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
2797    fn vpacksswb_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
2798        self.emit(
2799            VPACKSSWB512RRR_MASKZ,
2800            op0.as_operand(),
2801            op1.as_operand(),
2802            op2.as_operand(),
2803            &NOREG,
2804        );
2805    }
2806}
2807
2808impl<'a> VpacksswbMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
2809    fn vpacksswb_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
2810        self.emit(
2811            VPACKSSWB512RRM_MASKZ,
2812            op0.as_operand(),
2813            op1.as_operand(),
2814            op2.as_operand(),
2815            &NOREG,
2816        );
2817    }
2818}
2819
2820/// `VPACKUSDW`.
2821///
2822/// Supported operand variants:
2823///
2824/// ```text
2825/// +---+---------------+
2826/// | # | Operands      |
2827/// +---+---------------+
2828/// | 1 | Xmm, Xmm, Mem |
2829/// | 2 | Xmm, Xmm, Xmm |
2830/// | 3 | Ymm, Ymm, Mem |
2831/// | 4 | Ymm, Ymm, Ymm |
2832/// | 5 | Zmm, Zmm, Mem |
2833/// | 6 | Zmm, Zmm, Zmm |
2834/// +---+---------------+
2835/// ```
2836pub trait VpackusdwEmitter<A, B, C> {
2837    fn vpackusdw(&mut self, op0: A, op1: B, op2: C);
2838}
2839
2840impl<'a> VpackusdwEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
2841    fn vpackusdw(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
2842        self.emit(
2843            VPACKUSDW128RRR,
2844            op0.as_operand(),
2845            op1.as_operand(),
2846            op2.as_operand(),
2847            &NOREG,
2848        );
2849    }
2850}
2851
2852impl<'a> VpackusdwEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
2853    fn vpackusdw(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
2854        self.emit(
2855            VPACKUSDW128RRM,
2856            op0.as_operand(),
2857            op1.as_operand(),
2858            op2.as_operand(),
2859            &NOREG,
2860        );
2861    }
2862}
2863
2864impl<'a> VpackusdwEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
2865    fn vpackusdw(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
2866        self.emit(
2867            VPACKUSDW256RRR,
2868            op0.as_operand(),
2869            op1.as_operand(),
2870            op2.as_operand(),
2871            &NOREG,
2872        );
2873    }
2874}
2875
2876impl<'a> VpackusdwEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
2877    fn vpackusdw(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
2878        self.emit(
2879            VPACKUSDW256RRM,
2880            op0.as_operand(),
2881            op1.as_operand(),
2882            op2.as_operand(),
2883            &NOREG,
2884        );
2885    }
2886}
2887
2888impl<'a> VpackusdwEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
2889    fn vpackusdw(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
2890        self.emit(
2891            VPACKUSDW512RRR,
2892            op0.as_operand(),
2893            op1.as_operand(),
2894            op2.as_operand(),
2895            &NOREG,
2896        );
2897    }
2898}
2899
2900impl<'a> VpackusdwEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
2901    fn vpackusdw(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
2902        self.emit(
2903            VPACKUSDW512RRM,
2904            op0.as_operand(),
2905            op1.as_operand(),
2906            op2.as_operand(),
2907            &NOREG,
2908        );
2909    }
2910}
2911
2912/// `VPACKUSDW_MASK`.
2913///
2914/// Supported operand variants:
2915///
2916/// ```text
2917/// +---+---------------+
2918/// | # | Operands      |
2919/// +---+---------------+
2920/// | 1 | Xmm, Xmm, Mem |
2921/// | 2 | Xmm, Xmm, Xmm |
2922/// | 3 | Ymm, Ymm, Mem |
2923/// | 4 | Ymm, Ymm, Ymm |
2924/// | 5 | Zmm, Zmm, Mem |
2925/// | 6 | Zmm, Zmm, Zmm |
2926/// +---+---------------+
2927/// ```
2928pub trait VpackusdwMaskEmitter<A, B, C> {
2929    fn vpackusdw_mask(&mut self, op0: A, op1: B, op2: C);
2930}
2931
2932impl<'a> VpackusdwMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
2933    fn vpackusdw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
2934        self.emit(
2935            VPACKUSDW128RRR_MASK,
2936            op0.as_operand(),
2937            op1.as_operand(),
2938            op2.as_operand(),
2939            &NOREG,
2940        );
2941    }
2942}
2943
2944impl<'a> VpackusdwMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
2945    fn vpackusdw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
2946        self.emit(
2947            VPACKUSDW128RRM_MASK,
2948            op0.as_operand(),
2949            op1.as_operand(),
2950            op2.as_operand(),
2951            &NOREG,
2952        );
2953    }
2954}
2955
2956impl<'a> VpackusdwMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
2957    fn vpackusdw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
2958        self.emit(
2959            VPACKUSDW256RRR_MASK,
2960            op0.as_operand(),
2961            op1.as_operand(),
2962            op2.as_operand(),
2963            &NOREG,
2964        );
2965    }
2966}
2967
2968impl<'a> VpackusdwMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
2969    fn vpackusdw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
2970        self.emit(
2971            VPACKUSDW256RRM_MASK,
2972            op0.as_operand(),
2973            op1.as_operand(),
2974            op2.as_operand(),
2975            &NOREG,
2976        );
2977    }
2978}
2979
2980impl<'a> VpackusdwMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
2981    fn vpackusdw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
2982        self.emit(
2983            VPACKUSDW512RRR_MASK,
2984            op0.as_operand(),
2985            op1.as_operand(),
2986            op2.as_operand(),
2987            &NOREG,
2988        );
2989    }
2990}
2991
2992impl<'a> VpackusdwMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
2993    fn vpackusdw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
2994        self.emit(
2995            VPACKUSDW512RRM_MASK,
2996            op0.as_operand(),
2997            op1.as_operand(),
2998            op2.as_operand(),
2999            &NOREG,
3000        );
3001    }
3002}
3003
3004/// `VPACKUSDW_MASKZ`.
3005///
3006/// Supported operand variants:
3007///
3008/// ```text
3009/// +---+---------------+
3010/// | # | Operands      |
3011/// +---+---------------+
3012/// | 1 | Xmm, Xmm, Mem |
3013/// | 2 | Xmm, Xmm, Xmm |
3014/// | 3 | Ymm, Ymm, Mem |
3015/// | 4 | Ymm, Ymm, Ymm |
3016/// | 5 | Zmm, Zmm, Mem |
3017/// | 6 | Zmm, Zmm, Zmm |
3018/// +---+---------------+
3019/// ```
3020pub trait VpackusdwMaskzEmitter<A, B, C> {
3021    fn vpackusdw_maskz(&mut self, op0: A, op1: B, op2: C);
3022}
3023
3024impl<'a> VpackusdwMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
3025    fn vpackusdw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
3026        self.emit(
3027            VPACKUSDW128RRR_MASKZ,
3028            op0.as_operand(),
3029            op1.as_operand(),
3030            op2.as_operand(),
3031            &NOREG,
3032        );
3033    }
3034}
3035
3036impl<'a> VpackusdwMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
3037    fn vpackusdw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
3038        self.emit(
3039            VPACKUSDW128RRM_MASKZ,
3040            op0.as_operand(),
3041            op1.as_operand(),
3042            op2.as_operand(),
3043            &NOREG,
3044        );
3045    }
3046}
3047
3048impl<'a> VpackusdwMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
3049    fn vpackusdw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
3050        self.emit(
3051            VPACKUSDW256RRR_MASKZ,
3052            op0.as_operand(),
3053            op1.as_operand(),
3054            op2.as_operand(),
3055            &NOREG,
3056        );
3057    }
3058}
3059
3060impl<'a> VpackusdwMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
3061    fn vpackusdw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
3062        self.emit(
3063            VPACKUSDW256RRM_MASKZ,
3064            op0.as_operand(),
3065            op1.as_operand(),
3066            op2.as_operand(),
3067            &NOREG,
3068        );
3069    }
3070}
3071
3072impl<'a> VpackusdwMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
3073    fn vpackusdw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
3074        self.emit(
3075            VPACKUSDW512RRR_MASKZ,
3076            op0.as_operand(),
3077            op1.as_operand(),
3078            op2.as_operand(),
3079            &NOREG,
3080        );
3081    }
3082}
3083
3084impl<'a> VpackusdwMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
3085    fn vpackusdw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
3086        self.emit(
3087            VPACKUSDW512RRM_MASKZ,
3088            op0.as_operand(),
3089            op1.as_operand(),
3090            op2.as_operand(),
3091            &NOREG,
3092        );
3093    }
3094}
3095
3096/// `VPACKUSWB`.
3097///
3098/// Supported operand variants:
3099///
3100/// ```text
3101/// +---+---------------+
3102/// | # | Operands      |
3103/// +---+---------------+
3104/// | 1 | Xmm, Xmm, Mem |
3105/// | 2 | Xmm, Xmm, Xmm |
3106/// | 3 | Ymm, Ymm, Mem |
3107/// | 4 | Ymm, Ymm, Ymm |
3108/// | 5 | Zmm, Zmm, Mem |
3109/// | 6 | Zmm, Zmm, Zmm |
3110/// +---+---------------+
3111/// ```
3112pub trait VpackuswbEmitter<A, B, C> {
3113    fn vpackuswb(&mut self, op0: A, op1: B, op2: C);
3114}
3115
3116impl<'a> VpackuswbEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
3117    fn vpackuswb(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
3118        self.emit(
3119            VPACKUSWB128RRR,
3120            op0.as_operand(),
3121            op1.as_operand(),
3122            op2.as_operand(),
3123            &NOREG,
3124        );
3125    }
3126}
3127
3128impl<'a> VpackuswbEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
3129    fn vpackuswb(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
3130        self.emit(
3131            VPACKUSWB128RRM,
3132            op0.as_operand(),
3133            op1.as_operand(),
3134            op2.as_operand(),
3135            &NOREG,
3136        );
3137    }
3138}
3139
3140impl<'a> VpackuswbEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
3141    fn vpackuswb(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
3142        self.emit(
3143            VPACKUSWB256RRR,
3144            op0.as_operand(),
3145            op1.as_operand(),
3146            op2.as_operand(),
3147            &NOREG,
3148        );
3149    }
3150}
3151
3152impl<'a> VpackuswbEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
3153    fn vpackuswb(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
3154        self.emit(
3155            VPACKUSWB256RRM,
3156            op0.as_operand(),
3157            op1.as_operand(),
3158            op2.as_operand(),
3159            &NOREG,
3160        );
3161    }
3162}
3163
3164impl<'a> VpackuswbEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
3165    fn vpackuswb(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
3166        self.emit(
3167            VPACKUSWB512RRR,
3168            op0.as_operand(),
3169            op1.as_operand(),
3170            op2.as_operand(),
3171            &NOREG,
3172        );
3173    }
3174}
3175
3176impl<'a> VpackuswbEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
3177    fn vpackuswb(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
3178        self.emit(
3179            VPACKUSWB512RRM,
3180            op0.as_operand(),
3181            op1.as_operand(),
3182            op2.as_operand(),
3183            &NOREG,
3184        );
3185    }
3186}
3187
3188/// `VPACKUSWB_MASK`.
3189///
3190/// Supported operand variants:
3191///
3192/// ```text
3193/// +---+---------------+
3194/// | # | Operands      |
3195/// +---+---------------+
3196/// | 1 | Xmm, Xmm, Mem |
3197/// | 2 | Xmm, Xmm, Xmm |
3198/// | 3 | Ymm, Ymm, Mem |
3199/// | 4 | Ymm, Ymm, Ymm |
3200/// | 5 | Zmm, Zmm, Mem |
3201/// | 6 | Zmm, Zmm, Zmm |
3202/// +---+---------------+
3203/// ```
3204pub trait VpackuswbMaskEmitter<A, B, C> {
3205    fn vpackuswb_mask(&mut self, op0: A, op1: B, op2: C);
3206}
3207
3208impl<'a> VpackuswbMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
3209    fn vpackuswb_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
3210        self.emit(
3211            VPACKUSWB128RRR_MASK,
3212            op0.as_operand(),
3213            op1.as_operand(),
3214            op2.as_operand(),
3215            &NOREG,
3216        );
3217    }
3218}
3219
3220impl<'a> VpackuswbMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
3221    fn vpackuswb_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
3222        self.emit(
3223            VPACKUSWB128RRM_MASK,
3224            op0.as_operand(),
3225            op1.as_operand(),
3226            op2.as_operand(),
3227            &NOREG,
3228        );
3229    }
3230}
3231
3232impl<'a> VpackuswbMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
3233    fn vpackuswb_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
3234        self.emit(
3235            VPACKUSWB256RRR_MASK,
3236            op0.as_operand(),
3237            op1.as_operand(),
3238            op2.as_operand(),
3239            &NOREG,
3240        );
3241    }
3242}
3243
3244impl<'a> VpackuswbMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
3245    fn vpackuswb_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
3246        self.emit(
3247            VPACKUSWB256RRM_MASK,
3248            op0.as_operand(),
3249            op1.as_operand(),
3250            op2.as_operand(),
3251            &NOREG,
3252        );
3253    }
3254}
3255
3256impl<'a> VpackuswbMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
3257    fn vpackuswb_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
3258        self.emit(
3259            VPACKUSWB512RRR_MASK,
3260            op0.as_operand(),
3261            op1.as_operand(),
3262            op2.as_operand(),
3263            &NOREG,
3264        );
3265    }
3266}
3267
3268impl<'a> VpackuswbMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
3269    fn vpackuswb_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
3270        self.emit(
3271            VPACKUSWB512RRM_MASK,
3272            op0.as_operand(),
3273            op1.as_operand(),
3274            op2.as_operand(),
3275            &NOREG,
3276        );
3277    }
3278}
3279
3280/// `VPACKUSWB_MASKZ`.
3281///
3282/// Supported operand variants:
3283///
3284/// ```text
3285/// +---+---------------+
3286/// | # | Operands      |
3287/// +---+---------------+
3288/// | 1 | Xmm, Xmm, Mem |
3289/// | 2 | Xmm, Xmm, Xmm |
3290/// | 3 | Ymm, Ymm, Mem |
3291/// | 4 | Ymm, Ymm, Ymm |
3292/// | 5 | Zmm, Zmm, Mem |
3293/// | 6 | Zmm, Zmm, Zmm |
3294/// +---+---------------+
3295/// ```
3296pub trait VpackuswbMaskzEmitter<A, B, C> {
3297    fn vpackuswb_maskz(&mut self, op0: A, op1: B, op2: C);
3298}
3299
3300impl<'a> VpackuswbMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
3301    fn vpackuswb_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
3302        self.emit(
3303            VPACKUSWB128RRR_MASKZ,
3304            op0.as_operand(),
3305            op1.as_operand(),
3306            op2.as_operand(),
3307            &NOREG,
3308        );
3309    }
3310}
3311
3312impl<'a> VpackuswbMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
3313    fn vpackuswb_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
3314        self.emit(
3315            VPACKUSWB128RRM_MASKZ,
3316            op0.as_operand(),
3317            op1.as_operand(),
3318            op2.as_operand(),
3319            &NOREG,
3320        );
3321    }
3322}
3323
3324impl<'a> VpackuswbMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
3325    fn vpackuswb_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
3326        self.emit(
3327            VPACKUSWB256RRR_MASKZ,
3328            op0.as_operand(),
3329            op1.as_operand(),
3330            op2.as_operand(),
3331            &NOREG,
3332        );
3333    }
3334}
3335
3336impl<'a> VpackuswbMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
3337    fn vpackuswb_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
3338        self.emit(
3339            VPACKUSWB256RRM_MASKZ,
3340            op0.as_operand(),
3341            op1.as_operand(),
3342            op2.as_operand(),
3343            &NOREG,
3344        );
3345    }
3346}
3347
3348impl<'a> VpackuswbMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
3349    fn vpackuswb_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
3350        self.emit(
3351            VPACKUSWB512RRR_MASKZ,
3352            op0.as_operand(),
3353            op1.as_operand(),
3354            op2.as_operand(),
3355            &NOREG,
3356        );
3357    }
3358}
3359
3360impl<'a> VpackuswbMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
3361    fn vpackuswb_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
3362        self.emit(
3363            VPACKUSWB512RRM_MASKZ,
3364            op0.as_operand(),
3365            op1.as_operand(),
3366            op2.as_operand(),
3367            &NOREG,
3368        );
3369    }
3370}
3371
3372/// `VPADDB`.
3373///
3374/// Supported operand variants:
3375///
3376/// ```text
3377/// +---+---------------+
3378/// | # | Operands      |
3379/// +---+---------------+
3380/// | 1 | Xmm, Xmm, Mem |
3381/// | 2 | Xmm, Xmm, Xmm |
3382/// | 3 | Ymm, Ymm, Mem |
3383/// | 4 | Ymm, Ymm, Ymm |
3384/// | 5 | Zmm, Zmm, Mem |
3385/// | 6 | Zmm, Zmm, Zmm |
3386/// +---+---------------+
3387/// ```
3388pub trait VpaddbEmitter<A, B, C> {
3389    fn vpaddb(&mut self, op0: A, op1: B, op2: C);
3390}
3391
3392impl<'a> VpaddbEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
3393    fn vpaddb(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
3394        self.emit(
3395            VPADDB128RRR,
3396            op0.as_operand(),
3397            op1.as_operand(),
3398            op2.as_operand(),
3399            &NOREG,
3400        );
3401    }
3402}
3403
3404impl<'a> VpaddbEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
3405    fn vpaddb(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
3406        self.emit(
3407            VPADDB128RRM,
3408            op0.as_operand(),
3409            op1.as_operand(),
3410            op2.as_operand(),
3411            &NOREG,
3412        );
3413    }
3414}
3415
3416impl<'a> VpaddbEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
3417    fn vpaddb(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
3418        self.emit(
3419            VPADDB256RRR,
3420            op0.as_operand(),
3421            op1.as_operand(),
3422            op2.as_operand(),
3423            &NOREG,
3424        );
3425    }
3426}
3427
3428impl<'a> VpaddbEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
3429    fn vpaddb(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
3430        self.emit(
3431            VPADDB256RRM,
3432            op0.as_operand(),
3433            op1.as_operand(),
3434            op2.as_operand(),
3435            &NOREG,
3436        );
3437    }
3438}
3439
3440impl<'a> VpaddbEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
3441    fn vpaddb(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
3442        self.emit(
3443            VPADDB512RRR,
3444            op0.as_operand(),
3445            op1.as_operand(),
3446            op2.as_operand(),
3447            &NOREG,
3448        );
3449    }
3450}
3451
3452impl<'a> VpaddbEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
3453    fn vpaddb(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
3454        self.emit(
3455            VPADDB512RRM,
3456            op0.as_operand(),
3457            op1.as_operand(),
3458            op2.as_operand(),
3459            &NOREG,
3460        );
3461    }
3462}
3463
3464/// `VPADDB_MASK`.
3465///
3466/// Supported operand variants:
3467///
3468/// ```text
3469/// +---+---------------+
3470/// | # | Operands      |
3471/// +---+---------------+
3472/// | 1 | Xmm, Xmm, Mem |
3473/// | 2 | Xmm, Xmm, Xmm |
3474/// | 3 | Ymm, Ymm, Mem |
3475/// | 4 | Ymm, Ymm, Ymm |
3476/// | 5 | Zmm, Zmm, Mem |
3477/// | 6 | Zmm, Zmm, Zmm |
3478/// +---+---------------+
3479/// ```
3480pub trait VpaddbMaskEmitter<A, B, C> {
3481    fn vpaddb_mask(&mut self, op0: A, op1: B, op2: C);
3482}
3483
3484impl<'a> VpaddbMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
3485    fn vpaddb_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
3486        self.emit(
3487            VPADDB128RRR_MASK,
3488            op0.as_operand(),
3489            op1.as_operand(),
3490            op2.as_operand(),
3491            &NOREG,
3492        );
3493    }
3494}
3495
3496impl<'a> VpaddbMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
3497    fn vpaddb_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
3498        self.emit(
3499            VPADDB128RRM_MASK,
3500            op0.as_operand(),
3501            op1.as_operand(),
3502            op2.as_operand(),
3503            &NOREG,
3504        );
3505    }
3506}
3507
3508impl<'a> VpaddbMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
3509    fn vpaddb_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
3510        self.emit(
3511            VPADDB256RRR_MASK,
3512            op0.as_operand(),
3513            op1.as_operand(),
3514            op2.as_operand(),
3515            &NOREG,
3516        );
3517    }
3518}
3519
3520impl<'a> VpaddbMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
3521    fn vpaddb_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
3522        self.emit(
3523            VPADDB256RRM_MASK,
3524            op0.as_operand(),
3525            op1.as_operand(),
3526            op2.as_operand(),
3527            &NOREG,
3528        );
3529    }
3530}
3531
3532impl<'a> VpaddbMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
3533    fn vpaddb_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
3534        self.emit(
3535            VPADDB512RRR_MASK,
3536            op0.as_operand(),
3537            op1.as_operand(),
3538            op2.as_operand(),
3539            &NOREG,
3540        );
3541    }
3542}
3543
3544impl<'a> VpaddbMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
3545    fn vpaddb_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
3546        self.emit(
3547            VPADDB512RRM_MASK,
3548            op0.as_operand(),
3549            op1.as_operand(),
3550            op2.as_operand(),
3551            &NOREG,
3552        );
3553    }
3554}
3555
3556/// `VPADDB_MASKZ`.
3557///
3558/// Supported operand variants:
3559///
3560/// ```text
3561/// +---+---------------+
3562/// | # | Operands      |
3563/// +---+---------------+
3564/// | 1 | Xmm, Xmm, Mem |
3565/// | 2 | Xmm, Xmm, Xmm |
3566/// | 3 | Ymm, Ymm, Mem |
3567/// | 4 | Ymm, Ymm, Ymm |
3568/// | 5 | Zmm, Zmm, Mem |
3569/// | 6 | Zmm, Zmm, Zmm |
3570/// +---+---------------+
3571/// ```
3572pub trait VpaddbMaskzEmitter<A, B, C> {
3573    fn vpaddb_maskz(&mut self, op0: A, op1: B, op2: C);
3574}
3575
3576impl<'a> VpaddbMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
3577    fn vpaddb_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
3578        self.emit(
3579            VPADDB128RRR_MASKZ,
3580            op0.as_operand(),
3581            op1.as_operand(),
3582            op2.as_operand(),
3583            &NOREG,
3584        );
3585    }
3586}
3587
3588impl<'a> VpaddbMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
3589    fn vpaddb_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
3590        self.emit(
3591            VPADDB128RRM_MASKZ,
3592            op0.as_operand(),
3593            op1.as_operand(),
3594            op2.as_operand(),
3595            &NOREG,
3596        );
3597    }
3598}
3599
3600impl<'a> VpaddbMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
3601    fn vpaddb_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
3602        self.emit(
3603            VPADDB256RRR_MASKZ,
3604            op0.as_operand(),
3605            op1.as_operand(),
3606            op2.as_operand(),
3607            &NOREG,
3608        );
3609    }
3610}
3611
3612impl<'a> VpaddbMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
3613    fn vpaddb_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
3614        self.emit(
3615            VPADDB256RRM_MASKZ,
3616            op0.as_operand(),
3617            op1.as_operand(),
3618            op2.as_operand(),
3619            &NOREG,
3620        );
3621    }
3622}
3623
3624impl<'a> VpaddbMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
3625    fn vpaddb_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
3626        self.emit(
3627            VPADDB512RRR_MASKZ,
3628            op0.as_operand(),
3629            op1.as_operand(),
3630            op2.as_operand(),
3631            &NOREG,
3632        );
3633    }
3634}
3635
3636impl<'a> VpaddbMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
3637    fn vpaddb_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
3638        self.emit(
3639            VPADDB512RRM_MASKZ,
3640            op0.as_operand(),
3641            op1.as_operand(),
3642            op2.as_operand(),
3643            &NOREG,
3644        );
3645    }
3646}
3647
3648/// `VPADDSB`.
3649///
3650/// Supported operand variants:
3651///
3652/// ```text
3653/// +---+---------------+
3654/// | # | Operands      |
3655/// +---+---------------+
3656/// | 1 | Xmm, Xmm, Mem |
3657/// | 2 | Xmm, Xmm, Xmm |
3658/// | 3 | Ymm, Ymm, Mem |
3659/// | 4 | Ymm, Ymm, Ymm |
3660/// | 5 | Zmm, Zmm, Mem |
3661/// | 6 | Zmm, Zmm, Zmm |
3662/// +---+---------------+
3663/// ```
3664pub trait VpaddsbEmitter<A, B, C> {
3665    fn vpaddsb(&mut self, op0: A, op1: B, op2: C);
3666}
3667
3668impl<'a> VpaddsbEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
3669    fn vpaddsb(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
3670        self.emit(
3671            VPADDSB128RRR,
3672            op0.as_operand(),
3673            op1.as_operand(),
3674            op2.as_operand(),
3675            &NOREG,
3676        );
3677    }
3678}
3679
3680impl<'a> VpaddsbEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
3681    fn vpaddsb(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
3682        self.emit(
3683            VPADDSB128RRM,
3684            op0.as_operand(),
3685            op1.as_operand(),
3686            op2.as_operand(),
3687            &NOREG,
3688        );
3689    }
3690}
3691
3692impl<'a> VpaddsbEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
3693    fn vpaddsb(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
3694        self.emit(
3695            VPADDSB256RRR,
3696            op0.as_operand(),
3697            op1.as_operand(),
3698            op2.as_operand(),
3699            &NOREG,
3700        );
3701    }
3702}
3703
3704impl<'a> VpaddsbEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
3705    fn vpaddsb(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
3706        self.emit(
3707            VPADDSB256RRM,
3708            op0.as_operand(),
3709            op1.as_operand(),
3710            op2.as_operand(),
3711            &NOREG,
3712        );
3713    }
3714}
3715
3716impl<'a> VpaddsbEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
3717    fn vpaddsb(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
3718        self.emit(
3719            VPADDSB512RRR,
3720            op0.as_operand(),
3721            op1.as_operand(),
3722            op2.as_operand(),
3723            &NOREG,
3724        );
3725    }
3726}
3727
3728impl<'a> VpaddsbEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
3729    fn vpaddsb(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
3730        self.emit(
3731            VPADDSB512RRM,
3732            op0.as_operand(),
3733            op1.as_operand(),
3734            op2.as_operand(),
3735            &NOREG,
3736        );
3737    }
3738}
3739
3740/// `VPADDSB_MASK`.
3741///
3742/// Supported operand variants:
3743///
3744/// ```text
3745/// +---+---------------+
3746/// | # | Operands      |
3747/// +---+---------------+
3748/// | 1 | Xmm, Xmm, Mem |
3749/// | 2 | Xmm, Xmm, Xmm |
3750/// | 3 | Ymm, Ymm, Mem |
3751/// | 4 | Ymm, Ymm, Ymm |
3752/// | 5 | Zmm, Zmm, Mem |
3753/// | 6 | Zmm, Zmm, Zmm |
3754/// +---+---------------+
3755/// ```
3756pub trait VpaddsbMaskEmitter<A, B, C> {
3757    fn vpaddsb_mask(&mut self, op0: A, op1: B, op2: C);
3758}
3759
3760impl<'a> VpaddsbMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
3761    fn vpaddsb_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
3762        self.emit(
3763            VPADDSB128RRR_MASK,
3764            op0.as_operand(),
3765            op1.as_operand(),
3766            op2.as_operand(),
3767            &NOREG,
3768        );
3769    }
3770}
3771
3772impl<'a> VpaddsbMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
3773    fn vpaddsb_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
3774        self.emit(
3775            VPADDSB128RRM_MASK,
3776            op0.as_operand(),
3777            op1.as_operand(),
3778            op2.as_operand(),
3779            &NOREG,
3780        );
3781    }
3782}
3783
3784impl<'a> VpaddsbMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
3785    fn vpaddsb_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
3786        self.emit(
3787            VPADDSB256RRR_MASK,
3788            op0.as_operand(),
3789            op1.as_operand(),
3790            op2.as_operand(),
3791            &NOREG,
3792        );
3793    }
3794}
3795
3796impl<'a> VpaddsbMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
3797    fn vpaddsb_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
3798        self.emit(
3799            VPADDSB256RRM_MASK,
3800            op0.as_operand(),
3801            op1.as_operand(),
3802            op2.as_operand(),
3803            &NOREG,
3804        );
3805    }
3806}
3807
3808impl<'a> VpaddsbMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
3809    fn vpaddsb_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
3810        self.emit(
3811            VPADDSB512RRR_MASK,
3812            op0.as_operand(),
3813            op1.as_operand(),
3814            op2.as_operand(),
3815            &NOREG,
3816        );
3817    }
3818}
3819
3820impl<'a> VpaddsbMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
3821    fn vpaddsb_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
3822        self.emit(
3823            VPADDSB512RRM_MASK,
3824            op0.as_operand(),
3825            op1.as_operand(),
3826            op2.as_operand(),
3827            &NOREG,
3828        );
3829    }
3830}
3831
3832/// `VPADDSB_MASKZ`.
3833///
3834/// Supported operand variants:
3835///
3836/// ```text
3837/// +---+---------------+
3838/// | # | Operands      |
3839/// +---+---------------+
3840/// | 1 | Xmm, Xmm, Mem |
3841/// | 2 | Xmm, Xmm, Xmm |
3842/// | 3 | Ymm, Ymm, Mem |
3843/// | 4 | Ymm, Ymm, Ymm |
3844/// | 5 | Zmm, Zmm, Mem |
3845/// | 6 | Zmm, Zmm, Zmm |
3846/// +---+---------------+
3847/// ```
3848pub trait VpaddsbMaskzEmitter<A, B, C> {
3849    fn vpaddsb_maskz(&mut self, op0: A, op1: B, op2: C);
3850}
3851
3852impl<'a> VpaddsbMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
3853    fn vpaddsb_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
3854        self.emit(
3855            VPADDSB128RRR_MASKZ,
3856            op0.as_operand(),
3857            op1.as_operand(),
3858            op2.as_operand(),
3859            &NOREG,
3860        );
3861    }
3862}
3863
3864impl<'a> VpaddsbMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
3865    fn vpaddsb_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
3866        self.emit(
3867            VPADDSB128RRM_MASKZ,
3868            op0.as_operand(),
3869            op1.as_operand(),
3870            op2.as_operand(),
3871            &NOREG,
3872        );
3873    }
3874}
3875
3876impl<'a> VpaddsbMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
3877    fn vpaddsb_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
3878        self.emit(
3879            VPADDSB256RRR_MASKZ,
3880            op0.as_operand(),
3881            op1.as_operand(),
3882            op2.as_operand(),
3883            &NOREG,
3884        );
3885    }
3886}
3887
3888impl<'a> VpaddsbMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
3889    fn vpaddsb_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
3890        self.emit(
3891            VPADDSB256RRM_MASKZ,
3892            op0.as_operand(),
3893            op1.as_operand(),
3894            op2.as_operand(),
3895            &NOREG,
3896        );
3897    }
3898}
3899
3900impl<'a> VpaddsbMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
3901    fn vpaddsb_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
3902        self.emit(
3903            VPADDSB512RRR_MASKZ,
3904            op0.as_operand(),
3905            op1.as_operand(),
3906            op2.as_operand(),
3907            &NOREG,
3908        );
3909    }
3910}
3911
3912impl<'a> VpaddsbMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
3913    fn vpaddsb_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
3914        self.emit(
3915            VPADDSB512RRM_MASKZ,
3916            op0.as_operand(),
3917            op1.as_operand(),
3918            op2.as_operand(),
3919            &NOREG,
3920        );
3921    }
3922}
3923
3924/// `VPADDSW`.
3925///
3926/// Supported operand variants:
3927///
3928/// ```text
3929/// +---+---------------+
3930/// | # | Operands      |
3931/// +---+---------------+
3932/// | 1 | Xmm, Xmm, Mem |
3933/// | 2 | Xmm, Xmm, Xmm |
3934/// | 3 | Ymm, Ymm, Mem |
3935/// | 4 | Ymm, Ymm, Ymm |
3936/// | 5 | Zmm, Zmm, Mem |
3937/// | 6 | Zmm, Zmm, Zmm |
3938/// +---+---------------+
3939/// ```
3940pub trait VpaddswEmitter<A, B, C> {
3941    fn vpaddsw(&mut self, op0: A, op1: B, op2: C);
3942}
3943
3944impl<'a> VpaddswEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
3945    fn vpaddsw(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
3946        self.emit(
3947            VPADDSW128RRR,
3948            op0.as_operand(),
3949            op1.as_operand(),
3950            op2.as_operand(),
3951            &NOREG,
3952        );
3953    }
3954}
3955
3956impl<'a> VpaddswEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
3957    fn vpaddsw(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
3958        self.emit(
3959            VPADDSW128RRM,
3960            op0.as_operand(),
3961            op1.as_operand(),
3962            op2.as_operand(),
3963            &NOREG,
3964        );
3965    }
3966}
3967
3968impl<'a> VpaddswEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
3969    fn vpaddsw(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
3970        self.emit(
3971            VPADDSW256RRR,
3972            op0.as_operand(),
3973            op1.as_operand(),
3974            op2.as_operand(),
3975            &NOREG,
3976        );
3977    }
3978}
3979
3980impl<'a> VpaddswEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
3981    fn vpaddsw(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
3982        self.emit(
3983            VPADDSW256RRM,
3984            op0.as_operand(),
3985            op1.as_operand(),
3986            op2.as_operand(),
3987            &NOREG,
3988        );
3989    }
3990}
3991
3992impl<'a> VpaddswEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
3993    fn vpaddsw(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
3994        self.emit(
3995            VPADDSW512RRR,
3996            op0.as_operand(),
3997            op1.as_operand(),
3998            op2.as_operand(),
3999            &NOREG,
4000        );
4001    }
4002}
4003
4004impl<'a> VpaddswEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
4005    fn vpaddsw(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
4006        self.emit(
4007            VPADDSW512RRM,
4008            op0.as_operand(),
4009            op1.as_operand(),
4010            op2.as_operand(),
4011            &NOREG,
4012        );
4013    }
4014}
4015
4016/// `VPADDSW_MASK`.
4017///
4018/// Supported operand variants:
4019///
4020/// ```text
4021/// +---+---------------+
4022/// | # | Operands      |
4023/// +---+---------------+
4024/// | 1 | Xmm, Xmm, Mem |
4025/// | 2 | Xmm, Xmm, Xmm |
4026/// | 3 | Ymm, Ymm, Mem |
4027/// | 4 | Ymm, Ymm, Ymm |
4028/// | 5 | Zmm, Zmm, Mem |
4029/// | 6 | Zmm, Zmm, Zmm |
4030/// +---+---------------+
4031/// ```
4032pub trait VpaddswMaskEmitter<A, B, C> {
4033    fn vpaddsw_mask(&mut self, op0: A, op1: B, op2: C);
4034}
4035
4036impl<'a> VpaddswMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
4037    fn vpaddsw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
4038        self.emit(
4039            VPADDSW128RRR_MASK,
4040            op0.as_operand(),
4041            op1.as_operand(),
4042            op2.as_operand(),
4043            &NOREG,
4044        );
4045    }
4046}
4047
4048impl<'a> VpaddswMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
4049    fn vpaddsw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
4050        self.emit(
4051            VPADDSW128RRM_MASK,
4052            op0.as_operand(),
4053            op1.as_operand(),
4054            op2.as_operand(),
4055            &NOREG,
4056        );
4057    }
4058}
4059
4060impl<'a> VpaddswMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
4061    fn vpaddsw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
4062        self.emit(
4063            VPADDSW256RRR_MASK,
4064            op0.as_operand(),
4065            op1.as_operand(),
4066            op2.as_operand(),
4067            &NOREG,
4068        );
4069    }
4070}
4071
4072impl<'a> VpaddswMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
4073    fn vpaddsw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
4074        self.emit(
4075            VPADDSW256RRM_MASK,
4076            op0.as_operand(),
4077            op1.as_operand(),
4078            op2.as_operand(),
4079            &NOREG,
4080        );
4081    }
4082}
4083
4084impl<'a> VpaddswMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
4085    fn vpaddsw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
4086        self.emit(
4087            VPADDSW512RRR_MASK,
4088            op0.as_operand(),
4089            op1.as_operand(),
4090            op2.as_operand(),
4091            &NOREG,
4092        );
4093    }
4094}
4095
4096impl<'a> VpaddswMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
4097    fn vpaddsw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
4098        self.emit(
4099            VPADDSW512RRM_MASK,
4100            op0.as_operand(),
4101            op1.as_operand(),
4102            op2.as_operand(),
4103            &NOREG,
4104        );
4105    }
4106}
4107
4108/// `VPADDSW_MASKZ`.
4109///
4110/// Supported operand variants:
4111///
4112/// ```text
4113/// +---+---------------+
4114/// | # | Operands      |
4115/// +---+---------------+
4116/// | 1 | Xmm, Xmm, Mem |
4117/// | 2 | Xmm, Xmm, Xmm |
4118/// | 3 | Ymm, Ymm, Mem |
4119/// | 4 | Ymm, Ymm, Ymm |
4120/// | 5 | Zmm, Zmm, Mem |
4121/// | 6 | Zmm, Zmm, Zmm |
4122/// +---+---------------+
4123/// ```
4124pub trait VpaddswMaskzEmitter<A, B, C> {
4125    fn vpaddsw_maskz(&mut self, op0: A, op1: B, op2: C);
4126}
4127
4128impl<'a> VpaddswMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
4129    fn vpaddsw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
4130        self.emit(
4131            VPADDSW128RRR_MASKZ,
4132            op0.as_operand(),
4133            op1.as_operand(),
4134            op2.as_operand(),
4135            &NOREG,
4136        );
4137    }
4138}
4139
4140impl<'a> VpaddswMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
4141    fn vpaddsw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
4142        self.emit(
4143            VPADDSW128RRM_MASKZ,
4144            op0.as_operand(),
4145            op1.as_operand(),
4146            op2.as_operand(),
4147            &NOREG,
4148        );
4149    }
4150}
4151
4152impl<'a> VpaddswMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
4153    fn vpaddsw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
4154        self.emit(
4155            VPADDSW256RRR_MASKZ,
4156            op0.as_operand(),
4157            op1.as_operand(),
4158            op2.as_operand(),
4159            &NOREG,
4160        );
4161    }
4162}
4163
4164impl<'a> VpaddswMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
4165    fn vpaddsw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
4166        self.emit(
4167            VPADDSW256RRM_MASKZ,
4168            op0.as_operand(),
4169            op1.as_operand(),
4170            op2.as_operand(),
4171            &NOREG,
4172        );
4173    }
4174}
4175
4176impl<'a> VpaddswMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
4177    fn vpaddsw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
4178        self.emit(
4179            VPADDSW512RRR_MASKZ,
4180            op0.as_operand(),
4181            op1.as_operand(),
4182            op2.as_operand(),
4183            &NOREG,
4184        );
4185    }
4186}
4187
4188impl<'a> VpaddswMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
4189    fn vpaddsw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
4190        self.emit(
4191            VPADDSW512RRM_MASKZ,
4192            op0.as_operand(),
4193            op1.as_operand(),
4194            op2.as_operand(),
4195            &NOREG,
4196        );
4197    }
4198}
4199
4200/// `VPADDUSB`.
4201///
4202/// Supported operand variants:
4203///
4204/// ```text
4205/// +---+---------------+
4206/// | # | Operands      |
4207/// +---+---------------+
4208/// | 1 | Xmm, Xmm, Mem |
4209/// | 2 | Xmm, Xmm, Xmm |
4210/// | 3 | Ymm, Ymm, Mem |
4211/// | 4 | Ymm, Ymm, Ymm |
4212/// | 5 | Zmm, Zmm, Mem |
4213/// | 6 | Zmm, Zmm, Zmm |
4214/// +---+---------------+
4215/// ```
4216pub trait VpaddusbEmitter<A, B, C> {
4217    fn vpaddusb(&mut self, op0: A, op1: B, op2: C);
4218}
4219
4220impl<'a> VpaddusbEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
4221    fn vpaddusb(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
4222        self.emit(
4223            VPADDUSB128RRR,
4224            op0.as_operand(),
4225            op1.as_operand(),
4226            op2.as_operand(),
4227            &NOREG,
4228        );
4229    }
4230}
4231
4232impl<'a> VpaddusbEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
4233    fn vpaddusb(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
4234        self.emit(
4235            VPADDUSB128RRM,
4236            op0.as_operand(),
4237            op1.as_operand(),
4238            op2.as_operand(),
4239            &NOREG,
4240        );
4241    }
4242}
4243
4244impl<'a> VpaddusbEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
4245    fn vpaddusb(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
4246        self.emit(
4247            VPADDUSB256RRR,
4248            op0.as_operand(),
4249            op1.as_operand(),
4250            op2.as_operand(),
4251            &NOREG,
4252        );
4253    }
4254}
4255
4256impl<'a> VpaddusbEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
4257    fn vpaddusb(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
4258        self.emit(
4259            VPADDUSB256RRM,
4260            op0.as_operand(),
4261            op1.as_operand(),
4262            op2.as_operand(),
4263            &NOREG,
4264        );
4265    }
4266}
4267
4268impl<'a> VpaddusbEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
4269    fn vpaddusb(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
4270        self.emit(
4271            VPADDUSB512RRR,
4272            op0.as_operand(),
4273            op1.as_operand(),
4274            op2.as_operand(),
4275            &NOREG,
4276        );
4277    }
4278}
4279
4280impl<'a> VpaddusbEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
4281    fn vpaddusb(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
4282        self.emit(
4283            VPADDUSB512RRM,
4284            op0.as_operand(),
4285            op1.as_operand(),
4286            op2.as_operand(),
4287            &NOREG,
4288        );
4289    }
4290}
4291
4292/// `VPADDUSB_MASK`.
4293///
4294/// Supported operand variants:
4295///
4296/// ```text
4297/// +---+---------------+
4298/// | # | Operands      |
4299/// +---+---------------+
4300/// | 1 | Xmm, Xmm, Mem |
4301/// | 2 | Xmm, Xmm, Xmm |
4302/// | 3 | Ymm, Ymm, Mem |
4303/// | 4 | Ymm, Ymm, Ymm |
4304/// | 5 | Zmm, Zmm, Mem |
4305/// | 6 | Zmm, Zmm, Zmm |
4306/// +---+---------------+
4307/// ```
4308pub trait VpaddusbMaskEmitter<A, B, C> {
4309    fn vpaddusb_mask(&mut self, op0: A, op1: B, op2: C);
4310}
4311
4312impl<'a> VpaddusbMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
4313    fn vpaddusb_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
4314        self.emit(
4315            VPADDUSB128RRR_MASK,
4316            op0.as_operand(),
4317            op1.as_operand(),
4318            op2.as_operand(),
4319            &NOREG,
4320        );
4321    }
4322}
4323
4324impl<'a> VpaddusbMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
4325    fn vpaddusb_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
4326        self.emit(
4327            VPADDUSB128RRM_MASK,
4328            op0.as_operand(),
4329            op1.as_operand(),
4330            op2.as_operand(),
4331            &NOREG,
4332        );
4333    }
4334}
4335
4336impl<'a> VpaddusbMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
4337    fn vpaddusb_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
4338        self.emit(
4339            VPADDUSB256RRR_MASK,
4340            op0.as_operand(),
4341            op1.as_operand(),
4342            op2.as_operand(),
4343            &NOREG,
4344        );
4345    }
4346}
4347
4348impl<'a> VpaddusbMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
4349    fn vpaddusb_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
4350        self.emit(
4351            VPADDUSB256RRM_MASK,
4352            op0.as_operand(),
4353            op1.as_operand(),
4354            op2.as_operand(),
4355            &NOREG,
4356        );
4357    }
4358}
4359
4360impl<'a> VpaddusbMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
4361    fn vpaddusb_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
4362        self.emit(
4363            VPADDUSB512RRR_MASK,
4364            op0.as_operand(),
4365            op1.as_operand(),
4366            op2.as_operand(),
4367            &NOREG,
4368        );
4369    }
4370}
4371
4372impl<'a> VpaddusbMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
4373    fn vpaddusb_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
4374        self.emit(
4375            VPADDUSB512RRM_MASK,
4376            op0.as_operand(),
4377            op1.as_operand(),
4378            op2.as_operand(),
4379            &NOREG,
4380        );
4381    }
4382}
4383
4384/// `VPADDUSB_MASKZ`.
4385///
4386/// Supported operand variants:
4387///
4388/// ```text
4389/// +---+---------------+
4390/// | # | Operands      |
4391/// +---+---------------+
4392/// | 1 | Xmm, Xmm, Mem |
4393/// | 2 | Xmm, Xmm, Xmm |
4394/// | 3 | Ymm, Ymm, Mem |
4395/// | 4 | Ymm, Ymm, Ymm |
4396/// | 5 | Zmm, Zmm, Mem |
4397/// | 6 | Zmm, Zmm, Zmm |
4398/// +---+---------------+
4399/// ```
4400pub trait VpaddusbMaskzEmitter<A, B, C> {
4401    fn vpaddusb_maskz(&mut self, op0: A, op1: B, op2: C);
4402}
4403
4404impl<'a> VpaddusbMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
4405    fn vpaddusb_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
4406        self.emit(
4407            VPADDUSB128RRR_MASKZ,
4408            op0.as_operand(),
4409            op1.as_operand(),
4410            op2.as_operand(),
4411            &NOREG,
4412        );
4413    }
4414}
4415
4416impl<'a> VpaddusbMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
4417    fn vpaddusb_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
4418        self.emit(
4419            VPADDUSB128RRM_MASKZ,
4420            op0.as_operand(),
4421            op1.as_operand(),
4422            op2.as_operand(),
4423            &NOREG,
4424        );
4425    }
4426}
4427
4428impl<'a> VpaddusbMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
4429    fn vpaddusb_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
4430        self.emit(
4431            VPADDUSB256RRR_MASKZ,
4432            op0.as_operand(),
4433            op1.as_operand(),
4434            op2.as_operand(),
4435            &NOREG,
4436        );
4437    }
4438}
4439
4440impl<'a> VpaddusbMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
4441    fn vpaddusb_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
4442        self.emit(
4443            VPADDUSB256RRM_MASKZ,
4444            op0.as_operand(),
4445            op1.as_operand(),
4446            op2.as_operand(),
4447            &NOREG,
4448        );
4449    }
4450}
4451
4452impl<'a> VpaddusbMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
4453    fn vpaddusb_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
4454        self.emit(
4455            VPADDUSB512RRR_MASKZ,
4456            op0.as_operand(),
4457            op1.as_operand(),
4458            op2.as_operand(),
4459            &NOREG,
4460        );
4461    }
4462}
4463
4464impl<'a> VpaddusbMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
4465    fn vpaddusb_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
4466        self.emit(
4467            VPADDUSB512RRM_MASKZ,
4468            op0.as_operand(),
4469            op1.as_operand(),
4470            op2.as_operand(),
4471            &NOREG,
4472        );
4473    }
4474}
4475
4476/// `VPADDUSW`.
4477///
4478/// Supported operand variants:
4479///
4480/// ```text
4481/// +---+---------------+
4482/// | # | Operands      |
4483/// +---+---------------+
4484/// | 1 | Xmm, Xmm, Mem |
4485/// | 2 | Xmm, Xmm, Xmm |
4486/// | 3 | Ymm, Ymm, Mem |
4487/// | 4 | Ymm, Ymm, Ymm |
4488/// | 5 | Zmm, Zmm, Mem |
4489/// | 6 | Zmm, Zmm, Zmm |
4490/// +---+---------------+
4491/// ```
4492pub trait VpadduswEmitter<A, B, C> {
4493    fn vpaddusw(&mut self, op0: A, op1: B, op2: C);
4494}
4495
4496impl<'a> VpadduswEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
4497    fn vpaddusw(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
4498        self.emit(
4499            VPADDUSW128RRR,
4500            op0.as_operand(),
4501            op1.as_operand(),
4502            op2.as_operand(),
4503            &NOREG,
4504        );
4505    }
4506}
4507
4508impl<'a> VpadduswEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
4509    fn vpaddusw(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
4510        self.emit(
4511            VPADDUSW128RRM,
4512            op0.as_operand(),
4513            op1.as_operand(),
4514            op2.as_operand(),
4515            &NOREG,
4516        );
4517    }
4518}
4519
4520impl<'a> VpadduswEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
4521    fn vpaddusw(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
4522        self.emit(
4523            VPADDUSW256RRR,
4524            op0.as_operand(),
4525            op1.as_operand(),
4526            op2.as_operand(),
4527            &NOREG,
4528        );
4529    }
4530}
4531
4532impl<'a> VpadduswEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
4533    fn vpaddusw(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
4534        self.emit(
4535            VPADDUSW256RRM,
4536            op0.as_operand(),
4537            op1.as_operand(),
4538            op2.as_operand(),
4539            &NOREG,
4540        );
4541    }
4542}
4543
4544impl<'a> VpadduswEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
4545    fn vpaddusw(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
4546        self.emit(
4547            VPADDUSW512RRR,
4548            op0.as_operand(),
4549            op1.as_operand(),
4550            op2.as_operand(),
4551            &NOREG,
4552        );
4553    }
4554}
4555
4556impl<'a> VpadduswEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
4557    fn vpaddusw(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
4558        self.emit(
4559            VPADDUSW512RRM,
4560            op0.as_operand(),
4561            op1.as_operand(),
4562            op2.as_operand(),
4563            &NOREG,
4564        );
4565    }
4566}
4567
4568/// `VPADDUSW_MASK`.
4569///
4570/// Supported operand variants:
4571///
4572/// ```text
4573/// +---+---------------+
4574/// | # | Operands      |
4575/// +---+---------------+
4576/// | 1 | Xmm, Xmm, Mem |
4577/// | 2 | Xmm, Xmm, Xmm |
4578/// | 3 | Ymm, Ymm, Mem |
4579/// | 4 | Ymm, Ymm, Ymm |
4580/// | 5 | Zmm, Zmm, Mem |
4581/// | 6 | Zmm, Zmm, Zmm |
4582/// +---+---------------+
4583/// ```
4584pub trait VpadduswMaskEmitter<A, B, C> {
4585    fn vpaddusw_mask(&mut self, op0: A, op1: B, op2: C);
4586}
4587
4588impl<'a> VpadduswMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
4589    fn vpaddusw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
4590        self.emit(
4591            VPADDUSW128RRR_MASK,
4592            op0.as_operand(),
4593            op1.as_operand(),
4594            op2.as_operand(),
4595            &NOREG,
4596        );
4597    }
4598}
4599
4600impl<'a> VpadduswMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
4601    fn vpaddusw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
4602        self.emit(
4603            VPADDUSW128RRM_MASK,
4604            op0.as_operand(),
4605            op1.as_operand(),
4606            op2.as_operand(),
4607            &NOREG,
4608        );
4609    }
4610}
4611
4612impl<'a> VpadduswMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
4613    fn vpaddusw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
4614        self.emit(
4615            VPADDUSW256RRR_MASK,
4616            op0.as_operand(),
4617            op1.as_operand(),
4618            op2.as_operand(),
4619            &NOREG,
4620        );
4621    }
4622}
4623
4624impl<'a> VpadduswMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
4625    fn vpaddusw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
4626        self.emit(
4627            VPADDUSW256RRM_MASK,
4628            op0.as_operand(),
4629            op1.as_operand(),
4630            op2.as_operand(),
4631            &NOREG,
4632        );
4633    }
4634}
4635
4636impl<'a> VpadduswMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
4637    fn vpaddusw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
4638        self.emit(
4639            VPADDUSW512RRR_MASK,
4640            op0.as_operand(),
4641            op1.as_operand(),
4642            op2.as_operand(),
4643            &NOREG,
4644        );
4645    }
4646}
4647
4648impl<'a> VpadduswMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
4649    fn vpaddusw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
4650        self.emit(
4651            VPADDUSW512RRM_MASK,
4652            op0.as_operand(),
4653            op1.as_operand(),
4654            op2.as_operand(),
4655            &NOREG,
4656        );
4657    }
4658}
4659
4660/// `VPADDUSW_MASKZ`.
4661///
4662/// Supported operand variants:
4663///
4664/// ```text
4665/// +---+---------------+
4666/// | # | Operands      |
4667/// +---+---------------+
4668/// | 1 | Xmm, Xmm, Mem |
4669/// | 2 | Xmm, Xmm, Xmm |
4670/// | 3 | Ymm, Ymm, Mem |
4671/// | 4 | Ymm, Ymm, Ymm |
4672/// | 5 | Zmm, Zmm, Mem |
4673/// | 6 | Zmm, Zmm, Zmm |
4674/// +---+---------------+
4675/// ```
4676pub trait VpadduswMaskzEmitter<A, B, C> {
4677    fn vpaddusw_maskz(&mut self, op0: A, op1: B, op2: C);
4678}
4679
4680impl<'a> VpadduswMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
4681    fn vpaddusw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
4682        self.emit(
4683            VPADDUSW128RRR_MASKZ,
4684            op0.as_operand(),
4685            op1.as_operand(),
4686            op2.as_operand(),
4687            &NOREG,
4688        );
4689    }
4690}
4691
4692impl<'a> VpadduswMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
4693    fn vpaddusw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
4694        self.emit(
4695            VPADDUSW128RRM_MASKZ,
4696            op0.as_operand(),
4697            op1.as_operand(),
4698            op2.as_operand(),
4699            &NOREG,
4700        );
4701    }
4702}
4703
4704impl<'a> VpadduswMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
4705    fn vpaddusw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
4706        self.emit(
4707            VPADDUSW256RRR_MASKZ,
4708            op0.as_operand(),
4709            op1.as_operand(),
4710            op2.as_operand(),
4711            &NOREG,
4712        );
4713    }
4714}
4715
4716impl<'a> VpadduswMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
4717    fn vpaddusw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
4718        self.emit(
4719            VPADDUSW256RRM_MASKZ,
4720            op0.as_operand(),
4721            op1.as_operand(),
4722            op2.as_operand(),
4723            &NOREG,
4724        );
4725    }
4726}
4727
4728impl<'a> VpadduswMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
4729    fn vpaddusw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
4730        self.emit(
4731            VPADDUSW512RRR_MASKZ,
4732            op0.as_operand(),
4733            op1.as_operand(),
4734            op2.as_operand(),
4735            &NOREG,
4736        );
4737    }
4738}
4739
4740impl<'a> VpadduswMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
4741    fn vpaddusw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
4742        self.emit(
4743            VPADDUSW512RRM_MASKZ,
4744            op0.as_operand(),
4745            op1.as_operand(),
4746            op2.as_operand(),
4747            &NOREG,
4748        );
4749    }
4750}
4751
4752/// `VPADDW`.
4753///
4754/// Supported operand variants:
4755///
4756/// ```text
4757/// +---+---------------+
4758/// | # | Operands      |
4759/// +---+---------------+
4760/// | 1 | Xmm, Xmm, Mem |
4761/// | 2 | Xmm, Xmm, Xmm |
4762/// | 3 | Ymm, Ymm, Mem |
4763/// | 4 | Ymm, Ymm, Ymm |
4764/// | 5 | Zmm, Zmm, Mem |
4765/// | 6 | Zmm, Zmm, Zmm |
4766/// +---+---------------+
4767/// ```
4768pub trait VpaddwEmitter<A, B, C> {
4769    fn vpaddw(&mut self, op0: A, op1: B, op2: C);
4770}
4771
4772impl<'a> VpaddwEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
4773    fn vpaddw(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
4774        self.emit(
4775            VPADDW128RRR,
4776            op0.as_operand(),
4777            op1.as_operand(),
4778            op2.as_operand(),
4779            &NOREG,
4780        );
4781    }
4782}
4783
4784impl<'a> VpaddwEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
4785    fn vpaddw(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
4786        self.emit(
4787            VPADDW128RRM,
4788            op0.as_operand(),
4789            op1.as_operand(),
4790            op2.as_operand(),
4791            &NOREG,
4792        );
4793    }
4794}
4795
4796impl<'a> VpaddwEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
4797    fn vpaddw(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
4798        self.emit(
4799            VPADDW256RRR,
4800            op0.as_operand(),
4801            op1.as_operand(),
4802            op2.as_operand(),
4803            &NOREG,
4804        );
4805    }
4806}
4807
4808impl<'a> VpaddwEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
4809    fn vpaddw(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
4810        self.emit(
4811            VPADDW256RRM,
4812            op0.as_operand(),
4813            op1.as_operand(),
4814            op2.as_operand(),
4815            &NOREG,
4816        );
4817    }
4818}
4819
4820impl<'a> VpaddwEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
4821    fn vpaddw(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
4822        self.emit(
4823            VPADDW512RRR,
4824            op0.as_operand(),
4825            op1.as_operand(),
4826            op2.as_operand(),
4827            &NOREG,
4828        );
4829    }
4830}
4831
4832impl<'a> VpaddwEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
4833    fn vpaddw(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
4834        self.emit(
4835            VPADDW512RRM,
4836            op0.as_operand(),
4837            op1.as_operand(),
4838            op2.as_operand(),
4839            &NOREG,
4840        );
4841    }
4842}
4843
4844/// `VPADDW_MASK`.
4845///
4846/// Supported operand variants:
4847///
4848/// ```text
4849/// +---+---------------+
4850/// | # | Operands      |
4851/// +---+---------------+
4852/// | 1 | Xmm, Xmm, Mem |
4853/// | 2 | Xmm, Xmm, Xmm |
4854/// | 3 | Ymm, Ymm, Mem |
4855/// | 4 | Ymm, Ymm, Ymm |
4856/// | 5 | Zmm, Zmm, Mem |
4857/// | 6 | Zmm, Zmm, Zmm |
4858/// +---+---------------+
4859/// ```
4860pub trait VpaddwMaskEmitter<A, B, C> {
4861    fn vpaddw_mask(&mut self, op0: A, op1: B, op2: C);
4862}
4863
4864impl<'a> VpaddwMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
4865    fn vpaddw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
4866        self.emit(
4867            VPADDW128RRR_MASK,
4868            op0.as_operand(),
4869            op1.as_operand(),
4870            op2.as_operand(),
4871            &NOREG,
4872        );
4873    }
4874}
4875
4876impl<'a> VpaddwMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
4877    fn vpaddw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
4878        self.emit(
4879            VPADDW128RRM_MASK,
4880            op0.as_operand(),
4881            op1.as_operand(),
4882            op2.as_operand(),
4883            &NOREG,
4884        );
4885    }
4886}
4887
4888impl<'a> VpaddwMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
4889    fn vpaddw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
4890        self.emit(
4891            VPADDW256RRR_MASK,
4892            op0.as_operand(),
4893            op1.as_operand(),
4894            op2.as_operand(),
4895            &NOREG,
4896        );
4897    }
4898}
4899
4900impl<'a> VpaddwMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
4901    fn vpaddw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
4902        self.emit(
4903            VPADDW256RRM_MASK,
4904            op0.as_operand(),
4905            op1.as_operand(),
4906            op2.as_operand(),
4907            &NOREG,
4908        );
4909    }
4910}
4911
4912impl<'a> VpaddwMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
4913    fn vpaddw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
4914        self.emit(
4915            VPADDW512RRR_MASK,
4916            op0.as_operand(),
4917            op1.as_operand(),
4918            op2.as_operand(),
4919            &NOREG,
4920        );
4921    }
4922}
4923
4924impl<'a> VpaddwMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
4925    fn vpaddw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
4926        self.emit(
4927            VPADDW512RRM_MASK,
4928            op0.as_operand(),
4929            op1.as_operand(),
4930            op2.as_operand(),
4931            &NOREG,
4932        );
4933    }
4934}
4935
4936/// `VPADDW_MASKZ`.
4937///
4938/// Supported operand variants:
4939///
4940/// ```text
4941/// +---+---------------+
4942/// | # | Operands      |
4943/// +---+---------------+
4944/// | 1 | Xmm, Xmm, Mem |
4945/// | 2 | Xmm, Xmm, Xmm |
4946/// | 3 | Ymm, Ymm, Mem |
4947/// | 4 | Ymm, Ymm, Ymm |
4948/// | 5 | Zmm, Zmm, Mem |
4949/// | 6 | Zmm, Zmm, Zmm |
4950/// +---+---------------+
4951/// ```
4952pub trait VpaddwMaskzEmitter<A, B, C> {
4953    fn vpaddw_maskz(&mut self, op0: A, op1: B, op2: C);
4954}
4955
4956impl<'a> VpaddwMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
4957    fn vpaddw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
4958        self.emit(
4959            VPADDW128RRR_MASKZ,
4960            op0.as_operand(),
4961            op1.as_operand(),
4962            op2.as_operand(),
4963            &NOREG,
4964        );
4965    }
4966}
4967
4968impl<'a> VpaddwMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
4969    fn vpaddw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
4970        self.emit(
4971            VPADDW128RRM_MASKZ,
4972            op0.as_operand(),
4973            op1.as_operand(),
4974            op2.as_operand(),
4975            &NOREG,
4976        );
4977    }
4978}
4979
4980impl<'a> VpaddwMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
4981    fn vpaddw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
4982        self.emit(
4983            VPADDW256RRR_MASKZ,
4984            op0.as_operand(),
4985            op1.as_operand(),
4986            op2.as_operand(),
4987            &NOREG,
4988        );
4989    }
4990}
4991
4992impl<'a> VpaddwMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
4993    fn vpaddw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
4994        self.emit(
4995            VPADDW256RRM_MASKZ,
4996            op0.as_operand(),
4997            op1.as_operand(),
4998            op2.as_operand(),
4999            &NOREG,
5000        );
5001    }
5002}
5003
5004impl<'a> VpaddwMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
5005    fn vpaddw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
5006        self.emit(
5007            VPADDW512RRR_MASKZ,
5008            op0.as_operand(),
5009            op1.as_operand(),
5010            op2.as_operand(),
5011            &NOREG,
5012        );
5013    }
5014}
5015
5016impl<'a> VpaddwMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
5017    fn vpaddw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
5018        self.emit(
5019            VPADDW512RRM_MASKZ,
5020            op0.as_operand(),
5021            op1.as_operand(),
5022            op2.as_operand(),
5023            &NOREG,
5024        );
5025    }
5026}
5027
5028/// `VPALIGNR`.
5029///
5030/// Supported operand variants:
5031///
5032/// ```text
5033/// +---+--------------------+
5034/// | # | Operands           |
5035/// +---+--------------------+
5036/// | 1 | Xmm, Xmm, Mem, Imm |
5037/// | 2 | Xmm, Xmm, Xmm, Imm |
5038/// | 3 | Ymm, Ymm, Mem, Imm |
5039/// | 4 | Ymm, Ymm, Ymm, Imm |
5040/// | 5 | Zmm, Zmm, Mem, Imm |
5041/// | 6 | Zmm, Zmm, Zmm, Imm |
5042/// +---+--------------------+
5043/// ```
5044pub trait VpalignrEmitter<A, B, C, D> {
5045    fn vpalignr(&mut self, op0: A, op1: B, op2: C, op3: D);
5046}
5047
5048impl<'a> VpalignrEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
5049    fn vpalignr(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
5050        self.emit(
5051            VPALIGNR128RRRI,
5052            op0.as_operand(),
5053            op1.as_operand(),
5054            op2.as_operand(),
5055            op3.as_operand(),
5056        );
5057    }
5058}
5059
5060impl<'a> VpalignrEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
5061    fn vpalignr(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
5062        self.emit(
5063            VPALIGNR128RRMI,
5064            op0.as_operand(),
5065            op1.as_operand(),
5066            op2.as_operand(),
5067            op3.as_operand(),
5068        );
5069    }
5070}
5071
5072impl<'a> VpalignrEmitter<Ymm, Ymm, Ymm, Imm> for Assembler<'a> {
5073    fn vpalignr(&mut self, op0: Ymm, op1: Ymm, op2: Ymm, op3: Imm) {
5074        self.emit(
5075            VPALIGNR256RRRI,
5076            op0.as_operand(),
5077            op1.as_operand(),
5078            op2.as_operand(),
5079            op3.as_operand(),
5080        );
5081    }
5082}
5083
5084impl<'a> VpalignrEmitter<Ymm, Ymm, Mem, Imm> for Assembler<'a> {
5085    fn vpalignr(&mut self, op0: Ymm, op1: Ymm, op2: Mem, op3: Imm) {
5086        self.emit(
5087            VPALIGNR256RRMI,
5088            op0.as_operand(),
5089            op1.as_operand(),
5090            op2.as_operand(),
5091            op3.as_operand(),
5092        );
5093    }
5094}
5095
5096impl<'a> VpalignrEmitter<Zmm, Zmm, Zmm, Imm> for Assembler<'a> {
5097    fn vpalignr(&mut self, op0: Zmm, op1: Zmm, op2: Zmm, op3: Imm) {
5098        self.emit(
5099            VPALIGNR512RRRI,
5100            op0.as_operand(),
5101            op1.as_operand(),
5102            op2.as_operand(),
5103            op3.as_operand(),
5104        );
5105    }
5106}
5107
5108impl<'a> VpalignrEmitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
5109    fn vpalignr(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
5110        self.emit(
5111            VPALIGNR512RRMI,
5112            op0.as_operand(),
5113            op1.as_operand(),
5114            op2.as_operand(),
5115            op3.as_operand(),
5116        );
5117    }
5118}
5119
5120/// `VPALIGNR_MASK`.
5121///
5122/// Supported operand variants:
5123///
5124/// ```text
5125/// +---+--------------------+
5126/// | # | Operands           |
5127/// +---+--------------------+
5128/// | 1 | Xmm, Xmm, Mem, Imm |
5129/// | 2 | Xmm, Xmm, Xmm, Imm |
5130/// | 3 | Ymm, Ymm, Mem, Imm |
5131/// | 4 | Ymm, Ymm, Ymm, Imm |
5132/// | 5 | Zmm, Zmm, Mem, Imm |
5133/// | 6 | Zmm, Zmm, Zmm, Imm |
5134/// +---+--------------------+
5135/// ```
5136pub trait VpalignrMaskEmitter<A, B, C, D> {
5137    fn vpalignr_mask(&mut self, op0: A, op1: B, op2: C, op3: D);
5138}
5139
5140impl<'a> VpalignrMaskEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
5141    fn vpalignr_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
5142        self.emit(
5143            VPALIGNR128RRRI_MASK,
5144            op0.as_operand(),
5145            op1.as_operand(),
5146            op2.as_operand(),
5147            op3.as_operand(),
5148        );
5149    }
5150}
5151
5152impl<'a> VpalignrMaskEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
5153    fn vpalignr_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
5154        self.emit(
5155            VPALIGNR128RRMI_MASK,
5156            op0.as_operand(),
5157            op1.as_operand(),
5158            op2.as_operand(),
5159            op3.as_operand(),
5160        );
5161    }
5162}
5163
5164impl<'a> VpalignrMaskEmitter<Ymm, Ymm, Ymm, Imm> for Assembler<'a> {
5165    fn vpalignr_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm, op3: Imm) {
5166        self.emit(
5167            VPALIGNR256RRRI_MASK,
5168            op0.as_operand(),
5169            op1.as_operand(),
5170            op2.as_operand(),
5171            op3.as_operand(),
5172        );
5173    }
5174}
5175
5176impl<'a> VpalignrMaskEmitter<Ymm, Ymm, Mem, Imm> for Assembler<'a> {
5177    fn vpalignr_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem, op3: Imm) {
5178        self.emit(
5179            VPALIGNR256RRMI_MASK,
5180            op0.as_operand(),
5181            op1.as_operand(),
5182            op2.as_operand(),
5183            op3.as_operand(),
5184        );
5185    }
5186}
5187
5188impl<'a> VpalignrMaskEmitter<Zmm, Zmm, Zmm, Imm> for Assembler<'a> {
5189    fn vpalignr_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm, op3: Imm) {
5190        self.emit(
5191            VPALIGNR512RRRI_MASK,
5192            op0.as_operand(),
5193            op1.as_operand(),
5194            op2.as_operand(),
5195            op3.as_operand(),
5196        );
5197    }
5198}
5199
5200impl<'a> VpalignrMaskEmitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
5201    fn vpalignr_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
5202        self.emit(
5203            VPALIGNR512RRMI_MASK,
5204            op0.as_operand(),
5205            op1.as_operand(),
5206            op2.as_operand(),
5207            op3.as_operand(),
5208        );
5209    }
5210}
5211
5212/// `VPALIGNR_MASKZ`.
5213///
5214/// Supported operand variants:
5215///
5216/// ```text
5217/// +---+--------------------+
5218/// | # | Operands           |
5219/// +---+--------------------+
5220/// | 1 | Xmm, Xmm, Mem, Imm |
5221/// | 2 | Xmm, Xmm, Xmm, Imm |
5222/// | 3 | Ymm, Ymm, Mem, Imm |
5223/// | 4 | Ymm, Ymm, Ymm, Imm |
5224/// | 5 | Zmm, Zmm, Mem, Imm |
5225/// | 6 | Zmm, Zmm, Zmm, Imm |
5226/// +---+--------------------+
5227/// ```
5228pub trait VpalignrMaskzEmitter<A, B, C, D> {
5229    fn vpalignr_maskz(&mut self, op0: A, op1: B, op2: C, op3: D);
5230}
5231
5232impl<'a> VpalignrMaskzEmitter<Xmm, Xmm, Xmm, Imm> for Assembler<'a> {
5233    fn vpalignr_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm, op3: Imm) {
5234        self.emit(
5235            VPALIGNR128RRRI_MASKZ,
5236            op0.as_operand(),
5237            op1.as_operand(),
5238            op2.as_operand(),
5239            op3.as_operand(),
5240        );
5241    }
5242}
5243
5244impl<'a> VpalignrMaskzEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
5245    fn vpalignr_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
5246        self.emit(
5247            VPALIGNR128RRMI_MASKZ,
5248            op0.as_operand(),
5249            op1.as_operand(),
5250            op2.as_operand(),
5251            op3.as_operand(),
5252        );
5253    }
5254}
5255
5256impl<'a> VpalignrMaskzEmitter<Ymm, Ymm, Ymm, Imm> for Assembler<'a> {
5257    fn vpalignr_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm, op3: Imm) {
5258        self.emit(
5259            VPALIGNR256RRRI_MASKZ,
5260            op0.as_operand(),
5261            op1.as_operand(),
5262            op2.as_operand(),
5263            op3.as_operand(),
5264        );
5265    }
5266}
5267
5268impl<'a> VpalignrMaskzEmitter<Ymm, Ymm, Mem, Imm> for Assembler<'a> {
5269    fn vpalignr_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem, op3: Imm) {
5270        self.emit(
5271            VPALIGNR256RRMI_MASKZ,
5272            op0.as_operand(),
5273            op1.as_operand(),
5274            op2.as_operand(),
5275            op3.as_operand(),
5276        );
5277    }
5278}
5279
5280impl<'a> VpalignrMaskzEmitter<Zmm, Zmm, Zmm, Imm> for Assembler<'a> {
5281    fn vpalignr_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm, op3: Imm) {
5282        self.emit(
5283            VPALIGNR512RRRI_MASKZ,
5284            op0.as_operand(),
5285            op1.as_operand(),
5286            op2.as_operand(),
5287            op3.as_operand(),
5288        );
5289    }
5290}
5291
5292impl<'a> VpalignrMaskzEmitter<Zmm, Zmm, Mem, Imm> for Assembler<'a> {
5293    fn vpalignr_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem, op3: Imm) {
5294        self.emit(
5295            VPALIGNR512RRMI_MASKZ,
5296            op0.as_operand(),
5297            op1.as_operand(),
5298            op2.as_operand(),
5299            op3.as_operand(),
5300        );
5301    }
5302}
5303
5304/// `VPAVGB`.
5305///
5306/// Supported operand variants:
5307///
5308/// ```text
5309/// +---+---------------+
5310/// | # | Operands      |
5311/// +---+---------------+
5312/// | 1 | Xmm, Xmm, Mem |
5313/// | 2 | Xmm, Xmm, Xmm |
5314/// | 3 | Ymm, Ymm, Mem |
5315/// | 4 | Ymm, Ymm, Ymm |
5316/// | 5 | Zmm, Zmm, Mem |
5317/// | 6 | Zmm, Zmm, Zmm |
5318/// +---+---------------+
5319/// ```
5320pub trait VpavgbEmitter<A, B, C> {
5321    fn vpavgb(&mut self, op0: A, op1: B, op2: C);
5322}
5323
5324impl<'a> VpavgbEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
5325    fn vpavgb(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
5326        self.emit(
5327            VPAVGB128RRR,
5328            op0.as_operand(),
5329            op1.as_operand(),
5330            op2.as_operand(),
5331            &NOREG,
5332        );
5333    }
5334}
5335
5336impl<'a> VpavgbEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
5337    fn vpavgb(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
5338        self.emit(
5339            VPAVGB128RRM,
5340            op0.as_operand(),
5341            op1.as_operand(),
5342            op2.as_operand(),
5343            &NOREG,
5344        );
5345    }
5346}
5347
5348impl<'a> VpavgbEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
5349    fn vpavgb(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
5350        self.emit(
5351            VPAVGB256RRR,
5352            op0.as_operand(),
5353            op1.as_operand(),
5354            op2.as_operand(),
5355            &NOREG,
5356        );
5357    }
5358}
5359
5360impl<'a> VpavgbEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
5361    fn vpavgb(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
5362        self.emit(
5363            VPAVGB256RRM,
5364            op0.as_operand(),
5365            op1.as_operand(),
5366            op2.as_operand(),
5367            &NOREG,
5368        );
5369    }
5370}
5371
5372impl<'a> VpavgbEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
5373    fn vpavgb(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
5374        self.emit(
5375            VPAVGB512RRR,
5376            op0.as_operand(),
5377            op1.as_operand(),
5378            op2.as_operand(),
5379            &NOREG,
5380        );
5381    }
5382}
5383
5384impl<'a> VpavgbEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
5385    fn vpavgb(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
5386        self.emit(
5387            VPAVGB512RRM,
5388            op0.as_operand(),
5389            op1.as_operand(),
5390            op2.as_operand(),
5391            &NOREG,
5392        );
5393    }
5394}
5395
5396/// `VPAVGB_MASK`.
5397///
5398/// Supported operand variants:
5399///
5400/// ```text
5401/// +---+---------------+
5402/// | # | Operands      |
5403/// +---+---------------+
5404/// | 1 | Xmm, Xmm, Mem |
5405/// | 2 | Xmm, Xmm, Xmm |
5406/// | 3 | Ymm, Ymm, Mem |
5407/// | 4 | Ymm, Ymm, Ymm |
5408/// | 5 | Zmm, Zmm, Mem |
5409/// | 6 | Zmm, Zmm, Zmm |
5410/// +---+---------------+
5411/// ```
5412pub trait VpavgbMaskEmitter<A, B, C> {
5413    fn vpavgb_mask(&mut self, op0: A, op1: B, op2: C);
5414}
5415
5416impl<'a> VpavgbMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
5417    fn vpavgb_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
5418        self.emit(
5419            VPAVGB128RRR_MASK,
5420            op0.as_operand(),
5421            op1.as_operand(),
5422            op2.as_operand(),
5423            &NOREG,
5424        );
5425    }
5426}
5427
5428impl<'a> VpavgbMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
5429    fn vpavgb_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
5430        self.emit(
5431            VPAVGB128RRM_MASK,
5432            op0.as_operand(),
5433            op1.as_operand(),
5434            op2.as_operand(),
5435            &NOREG,
5436        );
5437    }
5438}
5439
5440impl<'a> VpavgbMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
5441    fn vpavgb_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
5442        self.emit(
5443            VPAVGB256RRR_MASK,
5444            op0.as_operand(),
5445            op1.as_operand(),
5446            op2.as_operand(),
5447            &NOREG,
5448        );
5449    }
5450}
5451
5452impl<'a> VpavgbMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
5453    fn vpavgb_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
5454        self.emit(
5455            VPAVGB256RRM_MASK,
5456            op0.as_operand(),
5457            op1.as_operand(),
5458            op2.as_operand(),
5459            &NOREG,
5460        );
5461    }
5462}
5463
5464impl<'a> VpavgbMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
5465    fn vpavgb_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
5466        self.emit(
5467            VPAVGB512RRR_MASK,
5468            op0.as_operand(),
5469            op1.as_operand(),
5470            op2.as_operand(),
5471            &NOREG,
5472        );
5473    }
5474}
5475
5476impl<'a> VpavgbMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
5477    fn vpavgb_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
5478        self.emit(
5479            VPAVGB512RRM_MASK,
5480            op0.as_operand(),
5481            op1.as_operand(),
5482            op2.as_operand(),
5483            &NOREG,
5484        );
5485    }
5486}
5487
5488/// `VPAVGB_MASKZ`.
5489///
5490/// Supported operand variants:
5491///
5492/// ```text
5493/// +---+---------------+
5494/// | # | Operands      |
5495/// +---+---------------+
5496/// | 1 | Xmm, Xmm, Mem |
5497/// | 2 | Xmm, Xmm, Xmm |
5498/// | 3 | Ymm, Ymm, Mem |
5499/// | 4 | Ymm, Ymm, Ymm |
5500/// | 5 | Zmm, Zmm, Mem |
5501/// | 6 | Zmm, Zmm, Zmm |
5502/// +---+---------------+
5503/// ```
5504pub trait VpavgbMaskzEmitter<A, B, C> {
5505    fn vpavgb_maskz(&mut self, op0: A, op1: B, op2: C);
5506}
5507
5508impl<'a> VpavgbMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
5509    fn vpavgb_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
5510        self.emit(
5511            VPAVGB128RRR_MASKZ,
5512            op0.as_operand(),
5513            op1.as_operand(),
5514            op2.as_operand(),
5515            &NOREG,
5516        );
5517    }
5518}
5519
5520impl<'a> VpavgbMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
5521    fn vpavgb_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
5522        self.emit(
5523            VPAVGB128RRM_MASKZ,
5524            op0.as_operand(),
5525            op1.as_operand(),
5526            op2.as_operand(),
5527            &NOREG,
5528        );
5529    }
5530}
5531
5532impl<'a> VpavgbMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
5533    fn vpavgb_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
5534        self.emit(
5535            VPAVGB256RRR_MASKZ,
5536            op0.as_operand(),
5537            op1.as_operand(),
5538            op2.as_operand(),
5539            &NOREG,
5540        );
5541    }
5542}
5543
5544impl<'a> VpavgbMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
5545    fn vpavgb_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
5546        self.emit(
5547            VPAVGB256RRM_MASKZ,
5548            op0.as_operand(),
5549            op1.as_operand(),
5550            op2.as_operand(),
5551            &NOREG,
5552        );
5553    }
5554}
5555
5556impl<'a> VpavgbMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
5557    fn vpavgb_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
5558        self.emit(
5559            VPAVGB512RRR_MASKZ,
5560            op0.as_operand(),
5561            op1.as_operand(),
5562            op2.as_operand(),
5563            &NOREG,
5564        );
5565    }
5566}
5567
5568impl<'a> VpavgbMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
5569    fn vpavgb_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
5570        self.emit(
5571            VPAVGB512RRM_MASKZ,
5572            op0.as_operand(),
5573            op1.as_operand(),
5574            op2.as_operand(),
5575            &NOREG,
5576        );
5577    }
5578}
5579
5580/// `VPAVGW`.
5581///
5582/// Supported operand variants:
5583///
5584/// ```text
5585/// +---+---------------+
5586/// | # | Operands      |
5587/// +---+---------------+
5588/// | 1 | Xmm, Xmm, Mem |
5589/// | 2 | Xmm, Xmm, Xmm |
5590/// | 3 | Ymm, Ymm, Mem |
5591/// | 4 | Ymm, Ymm, Ymm |
5592/// | 5 | Zmm, Zmm, Mem |
5593/// | 6 | Zmm, Zmm, Zmm |
5594/// +---+---------------+
5595/// ```
5596pub trait VpavgwEmitter<A, B, C> {
5597    fn vpavgw(&mut self, op0: A, op1: B, op2: C);
5598}
5599
5600impl<'a> VpavgwEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
5601    fn vpavgw(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
5602        self.emit(
5603            VPAVGW128RRR,
5604            op0.as_operand(),
5605            op1.as_operand(),
5606            op2.as_operand(),
5607            &NOREG,
5608        );
5609    }
5610}
5611
5612impl<'a> VpavgwEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
5613    fn vpavgw(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
5614        self.emit(
5615            VPAVGW128RRM,
5616            op0.as_operand(),
5617            op1.as_operand(),
5618            op2.as_operand(),
5619            &NOREG,
5620        );
5621    }
5622}
5623
5624impl<'a> VpavgwEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
5625    fn vpavgw(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
5626        self.emit(
5627            VPAVGW256RRR,
5628            op0.as_operand(),
5629            op1.as_operand(),
5630            op2.as_operand(),
5631            &NOREG,
5632        );
5633    }
5634}
5635
5636impl<'a> VpavgwEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
5637    fn vpavgw(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
5638        self.emit(
5639            VPAVGW256RRM,
5640            op0.as_operand(),
5641            op1.as_operand(),
5642            op2.as_operand(),
5643            &NOREG,
5644        );
5645    }
5646}
5647
5648impl<'a> VpavgwEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
5649    fn vpavgw(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
5650        self.emit(
5651            VPAVGW512RRR,
5652            op0.as_operand(),
5653            op1.as_operand(),
5654            op2.as_operand(),
5655            &NOREG,
5656        );
5657    }
5658}
5659
5660impl<'a> VpavgwEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
5661    fn vpavgw(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
5662        self.emit(
5663            VPAVGW512RRM,
5664            op0.as_operand(),
5665            op1.as_operand(),
5666            op2.as_operand(),
5667            &NOREG,
5668        );
5669    }
5670}
5671
5672/// `VPAVGW_MASK`.
5673///
5674/// Supported operand variants:
5675///
5676/// ```text
5677/// +---+---------------+
5678/// | # | Operands      |
5679/// +---+---------------+
5680/// | 1 | Xmm, Xmm, Mem |
5681/// | 2 | Xmm, Xmm, Xmm |
5682/// | 3 | Ymm, Ymm, Mem |
5683/// | 4 | Ymm, Ymm, Ymm |
5684/// | 5 | Zmm, Zmm, Mem |
5685/// | 6 | Zmm, Zmm, Zmm |
5686/// +---+---------------+
5687/// ```
5688pub trait VpavgwMaskEmitter<A, B, C> {
5689    fn vpavgw_mask(&mut self, op0: A, op1: B, op2: C);
5690}
5691
5692impl<'a> VpavgwMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
5693    fn vpavgw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
5694        self.emit(
5695            VPAVGW128RRR_MASK,
5696            op0.as_operand(),
5697            op1.as_operand(),
5698            op2.as_operand(),
5699            &NOREG,
5700        );
5701    }
5702}
5703
5704impl<'a> VpavgwMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
5705    fn vpavgw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
5706        self.emit(
5707            VPAVGW128RRM_MASK,
5708            op0.as_operand(),
5709            op1.as_operand(),
5710            op2.as_operand(),
5711            &NOREG,
5712        );
5713    }
5714}
5715
5716impl<'a> VpavgwMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
5717    fn vpavgw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
5718        self.emit(
5719            VPAVGW256RRR_MASK,
5720            op0.as_operand(),
5721            op1.as_operand(),
5722            op2.as_operand(),
5723            &NOREG,
5724        );
5725    }
5726}
5727
5728impl<'a> VpavgwMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
5729    fn vpavgw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
5730        self.emit(
5731            VPAVGW256RRM_MASK,
5732            op0.as_operand(),
5733            op1.as_operand(),
5734            op2.as_operand(),
5735            &NOREG,
5736        );
5737    }
5738}
5739
5740impl<'a> VpavgwMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
5741    fn vpavgw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
5742        self.emit(
5743            VPAVGW512RRR_MASK,
5744            op0.as_operand(),
5745            op1.as_operand(),
5746            op2.as_operand(),
5747            &NOREG,
5748        );
5749    }
5750}
5751
5752impl<'a> VpavgwMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
5753    fn vpavgw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
5754        self.emit(
5755            VPAVGW512RRM_MASK,
5756            op0.as_operand(),
5757            op1.as_operand(),
5758            op2.as_operand(),
5759            &NOREG,
5760        );
5761    }
5762}
5763
5764/// `VPAVGW_MASKZ`.
5765///
5766/// Supported operand variants:
5767///
5768/// ```text
5769/// +---+---------------+
5770/// | # | Operands      |
5771/// +---+---------------+
5772/// | 1 | Xmm, Xmm, Mem |
5773/// | 2 | Xmm, Xmm, Xmm |
5774/// | 3 | Ymm, Ymm, Mem |
5775/// | 4 | Ymm, Ymm, Ymm |
5776/// | 5 | Zmm, Zmm, Mem |
5777/// | 6 | Zmm, Zmm, Zmm |
5778/// +---+---------------+
5779/// ```
5780pub trait VpavgwMaskzEmitter<A, B, C> {
5781    fn vpavgw_maskz(&mut self, op0: A, op1: B, op2: C);
5782}
5783
5784impl<'a> VpavgwMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
5785    fn vpavgw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
5786        self.emit(
5787            VPAVGW128RRR_MASKZ,
5788            op0.as_operand(),
5789            op1.as_operand(),
5790            op2.as_operand(),
5791            &NOREG,
5792        );
5793    }
5794}
5795
5796impl<'a> VpavgwMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
5797    fn vpavgw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
5798        self.emit(
5799            VPAVGW128RRM_MASKZ,
5800            op0.as_operand(),
5801            op1.as_operand(),
5802            op2.as_operand(),
5803            &NOREG,
5804        );
5805    }
5806}
5807
5808impl<'a> VpavgwMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
5809    fn vpavgw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
5810        self.emit(
5811            VPAVGW256RRR_MASKZ,
5812            op0.as_operand(),
5813            op1.as_operand(),
5814            op2.as_operand(),
5815            &NOREG,
5816        );
5817    }
5818}
5819
5820impl<'a> VpavgwMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
5821    fn vpavgw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
5822        self.emit(
5823            VPAVGW256RRM_MASKZ,
5824            op0.as_operand(),
5825            op1.as_operand(),
5826            op2.as_operand(),
5827            &NOREG,
5828        );
5829    }
5830}
5831
5832impl<'a> VpavgwMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
5833    fn vpavgw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
5834        self.emit(
5835            VPAVGW512RRR_MASKZ,
5836            op0.as_operand(),
5837            op1.as_operand(),
5838            op2.as_operand(),
5839            &NOREG,
5840        );
5841    }
5842}
5843
5844impl<'a> VpavgwMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
5845    fn vpavgw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
5846        self.emit(
5847            VPAVGW512RRM_MASKZ,
5848            op0.as_operand(),
5849            op1.as_operand(),
5850            op2.as_operand(),
5851            &NOREG,
5852        );
5853    }
5854}
5855
5856/// `VPBLENDMB`.
5857///
5858/// Supported operand variants:
5859///
5860/// ```text
5861/// +---+---------------+
5862/// | # | Operands      |
5863/// +---+---------------+
5864/// | 1 | Xmm, Xmm, Mem |
5865/// | 2 | Xmm, Xmm, Xmm |
5866/// | 3 | Ymm, Ymm, Mem |
5867/// | 4 | Ymm, Ymm, Ymm |
5868/// | 5 | Zmm, Zmm, Mem |
5869/// | 6 | Zmm, Zmm, Zmm |
5870/// +---+---------------+
5871/// ```
5872pub trait VpblendmbEmitter<A, B, C> {
5873    fn vpblendmb(&mut self, op0: A, op1: B, op2: C);
5874}
5875
5876impl<'a> VpblendmbEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
5877    fn vpblendmb(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
5878        self.emit(
5879            VPBLENDMB128RRR,
5880            op0.as_operand(),
5881            op1.as_operand(),
5882            op2.as_operand(),
5883            &NOREG,
5884        );
5885    }
5886}
5887
5888impl<'a> VpblendmbEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
5889    fn vpblendmb(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
5890        self.emit(
5891            VPBLENDMB128RRM,
5892            op0.as_operand(),
5893            op1.as_operand(),
5894            op2.as_operand(),
5895            &NOREG,
5896        );
5897    }
5898}
5899
5900impl<'a> VpblendmbEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
5901    fn vpblendmb(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
5902        self.emit(
5903            VPBLENDMB256RRR,
5904            op0.as_operand(),
5905            op1.as_operand(),
5906            op2.as_operand(),
5907            &NOREG,
5908        );
5909    }
5910}
5911
5912impl<'a> VpblendmbEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
5913    fn vpblendmb(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
5914        self.emit(
5915            VPBLENDMB256RRM,
5916            op0.as_operand(),
5917            op1.as_operand(),
5918            op2.as_operand(),
5919            &NOREG,
5920        );
5921    }
5922}
5923
5924impl<'a> VpblendmbEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
5925    fn vpblendmb(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
5926        self.emit(
5927            VPBLENDMB512RRR,
5928            op0.as_operand(),
5929            op1.as_operand(),
5930            op2.as_operand(),
5931            &NOREG,
5932        );
5933    }
5934}
5935
5936impl<'a> VpblendmbEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
5937    fn vpblendmb(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
5938        self.emit(
5939            VPBLENDMB512RRM,
5940            op0.as_operand(),
5941            op1.as_operand(),
5942            op2.as_operand(),
5943            &NOREG,
5944        );
5945    }
5946}
5947
5948/// `VPBLENDMB_MASK`.
5949///
5950/// Supported operand variants:
5951///
5952/// ```text
5953/// +---+---------------+
5954/// | # | Operands      |
5955/// +---+---------------+
5956/// | 1 | Xmm, Xmm, Mem |
5957/// | 2 | Xmm, Xmm, Xmm |
5958/// | 3 | Ymm, Ymm, Mem |
5959/// | 4 | Ymm, Ymm, Ymm |
5960/// | 5 | Zmm, Zmm, Mem |
5961/// | 6 | Zmm, Zmm, Zmm |
5962/// +---+---------------+
5963/// ```
5964pub trait VpblendmbMaskEmitter<A, B, C> {
5965    fn vpblendmb_mask(&mut self, op0: A, op1: B, op2: C);
5966}
5967
5968impl<'a> VpblendmbMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
5969    fn vpblendmb_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
5970        self.emit(
5971            VPBLENDMB128RRR_MASK,
5972            op0.as_operand(),
5973            op1.as_operand(),
5974            op2.as_operand(),
5975            &NOREG,
5976        );
5977    }
5978}
5979
5980impl<'a> VpblendmbMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
5981    fn vpblendmb_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
5982        self.emit(
5983            VPBLENDMB128RRM_MASK,
5984            op0.as_operand(),
5985            op1.as_operand(),
5986            op2.as_operand(),
5987            &NOREG,
5988        );
5989    }
5990}
5991
5992impl<'a> VpblendmbMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
5993    fn vpblendmb_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
5994        self.emit(
5995            VPBLENDMB256RRR_MASK,
5996            op0.as_operand(),
5997            op1.as_operand(),
5998            op2.as_operand(),
5999            &NOREG,
6000        );
6001    }
6002}
6003
6004impl<'a> VpblendmbMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
6005    fn vpblendmb_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
6006        self.emit(
6007            VPBLENDMB256RRM_MASK,
6008            op0.as_operand(),
6009            op1.as_operand(),
6010            op2.as_operand(),
6011            &NOREG,
6012        );
6013    }
6014}
6015
6016impl<'a> VpblendmbMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
6017    fn vpblendmb_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
6018        self.emit(
6019            VPBLENDMB512RRR_MASK,
6020            op0.as_operand(),
6021            op1.as_operand(),
6022            op2.as_operand(),
6023            &NOREG,
6024        );
6025    }
6026}
6027
6028impl<'a> VpblendmbMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
6029    fn vpblendmb_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
6030        self.emit(
6031            VPBLENDMB512RRM_MASK,
6032            op0.as_operand(),
6033            op1.as_operand(),
6034            op2.as_operand(),
6035            &NOREG,
6036        );
6037    }
6038}
6039
6040/// `VPBLENDMB_MASKZ`.
6041///
6042/// Supported operand variants:
6043///
6044/// ```text
6045/// +---+---------------+
6046/// | # | Operands      |
6047/// +---+---------------+
6048/// | 1 | Xmm, Xmm, Mem |
6049/// | 2 | Xmm, Xmm, Xmm |
6050/// | 3 | Ymm, Ymm, Mem |
6051/// | 4 | Ymm, Ymm, Ymm |
6052/// | 5 | Zmm, Zmm, Mem |
6053/// | 6 | Zmm, Zmm, Zmm |
6054/// +---+---------------+
6055/// ```
6056pub trait VpblendmbMaskzEmitter<A, B, C> {
6057    fn vpblendmb_maskz(&mut self, op0: A, op1: B, op2: C);
6058}
6059
6060impl<'a> VpblendmbMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
6061    fn vpblendmb_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
6062        self.emit(
6063            VPBLENDMB128RRR_MASKZ,
6064            op0.as_operand(),
6065            op1.as_operand(),
6066            op2.as_operand(),
6067            &NOREG,
6068        );
6069    }
6070}
6071
6072impl<'a> VpblendmbMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
6073    fn vpblendmb_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
6074        self.emit(
6075            VPBLENDMB128RRM_MASKZ,
6076            op0.as_operand(),
6077            op1.as_operand(),
6078            op2.as_operand(),
6079            &NOREG,
6080        );
6081    }
6082}
6083
6084impl<'a> VpblendmbMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
6085    fn vpblendmb_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
6086        self.emit(
6087            VPBLENDMB256RRR_MASKZ,
6088            op0.as_operand(),
6089            op1.as_operand(),
6090            op2.as_operand(),
6091            &NOREG,
6092        );
6093    }
6094}
6095
6096impl<'a> VpblendmbMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
6097    fn vpblendmb_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
6098        self.emit(
6099            VPBLENDMB256RRM_MASKZ,
6100            op0.as_operand(),
6101            op1.as_operand(),
6102            op2.as_operand(),
6103            &NOREG,
6104        );
6105    }
6106}
6107
6108impl<'a> VpblendmbMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
6109    fn vpblendmb_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
6110        self.emit(
6111            VPBLENDMB512RRR_MASKZ,
6112            op0.as_operand(),
6113            op1.as_operand(),
6114            op2.as_operand(),
6115            &NOREG,
6116        );
6117    }
6118}
6119
6120impl<'a> VpblendmbMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
6121    fn vpblendmb_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
6122        self.emit(
6123            VPBLENDMB512RRM_MASKZ,
6124            op0.as_operand(),
6125            op1.as_operand(),
6126            op2.as_operand(),
6127            &NOREG,
6128        );
6129    }
6130}
6131
6132/// `VPBLENDMW`.
6133///
6134/// Supported operand variants:
6135///
6136/// ```text
6137/// +---+---------------+
6138/// | # | Operands      |
6139/// +---+---------------+
6140/// | 1 | Xmm, Xmm, Mem |
6141/// | 2 | Xmm, Xmm, Xmm |
6142/// | 3 | Ymm, Ymm, Mem |
6143/// | 4 | Ymm, Ymm, Ymm |
6144/// | 5 | Zmm, Zmm, Mem |
6145/// | 6 | Zmm, Zmm, Zmm |
6146/// +---+---------------+
6147/// ```
6148pub trait VpblendmwEmitter<A, B, C> {
6149    fn vpblendmw(&mut self, op0: A, op1: B, op2: C);
6150}
6151
6152impl<'a> VpblendmwEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
6153    fn vpblendmw(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
6154        self.emit(
6155            VPBLENDMW128RRR,
6156            op0.as_operand(),
6157            op1.as_operand(),
6158            op2.as_operand(),
6159            &NOREG,
6160        );
6161    }
6162}
6163
6164impl<'a> VpblendmwEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
6165    fn vpblendmw(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
6166        self.emit(
6167            VPBLENDMW128RRM,
6168            op0.as_operand(),
6169            op1.as_operand(),
6170            op2.as_operand(),
6171            &NOREG,
6172        );
6173    }
6174}
6175
6176impl<'a> VpblendmwEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
6177    fn vpblendmw(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
6178        self.emit(
6179            VPBLENDMW256RRR,
6180            op0.as_operand(),
6181            op1.as_operand(),
6182            op2.as_operand(),
6183            &NOREG,
6184        );
6185    }
6186}
6187
6188impl<'a> VpblendmwEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
6189    fn vpblendmw(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
6190        self.emit(
6191            VPBLENDMW256RRM,
6192            op0.as_operand(),
6193            op1.as_operand(),
6194            op2.as_operand(),
6195            &NOREG,
6196        );
6197    }
6198}
6199
6200impl<'a> VpblendmwEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
6201    fn vpblendmw(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
6202        self.emit(
6203            VPBLENDMW512RRR,
6204            op0.as_operand(),
6205            op1.as_operand(),
6206            op2.as_operand(),
6207            &NOREG,
6208        );
6209    }
6210}
6211
6212impl<'a> VpblendmwEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
6213    fn vpblendmw(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
6214        self.emit(
6215            VPBLENDMW512RRM,
6216            op0.as_operand(),
6217            op1.as_operand(),
6218            op2.as_operand(),
6219            &NOREG,
6220        );
6221    }
6222}
6223
6224/// `VPBLENDMW_MASK`.
6225///
6226/// Supported operand variants:
6227///
6228/// ```text
6229/// +---+---------------+
6230/// | # | Operands      |
6231/// +---+---------------+
6232/// | 1 | Xmm, Xmm, Mem |
6233/// | 2 | Xmm, Xmm, Xmm |
6234/// | 3 | Ymm, Ymm, Mem |
6235/// | 4 | Ymm, Ymm, Ymm |
6236/// | 5 | Zmm, Zmm, Mem |
6237/// | 6 | Zmm, Zmm, Zmm |
6238/// +---+---------------+
6239/// ```
6240pub trait VpblendmwMaskEmitter<A, B, C> {
6241    fn vpblendmw_mask(&mut self, op0: A, op1: B, op2: C);
6242}
6243
6244impl<'a> VpblendmwMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
6245    fn vpblendmw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
6246        self.emit(
6247            VPBLENDMW128RRR_MASK,
6248            op0.as_operand(),
6249            op1.as_operand(),
6250            op2.as_operand(),
6251            &NOREG,
6252        );
6253    }
6254}
6255
6256impl<'a> VpblendmwMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
6257    fn vpblendmw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
6258        self.emit(
6259            VPBLENDMW128RRM_MASK,
6260            op0.as_operand(),
6261            op1.as_operand(),
6262            op2.as_operand(),
6263            &NOREG,
6264        );
6265    }
6266}
6267
6268impl<'a> VpblendmwMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
6269    fn vpblendmw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
6270        self.emit(
6271            VPBLENDMW256RRR_MASK,
6272            op0.as_operand(),
6273            op1.as_operand(),
6274            op2.as_operand(),
6275            &NOREG,
6276        );
6277    }
6278}
6279
6280impl<'a> VpblendmwMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
6281    fn vpblendmw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
6282        self.emit(
6283            VPBLENDMW256RRM_MASK,
6284            op0.as_operand(),
6285            op1.as_operand(),
6286            op2.as_operand(),
6287            &NOREG,
6288        );
6289    }
6290}
6291
6292impl<'a> VpblendmwMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
6293    fn vpblendmw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
6294        self.emit(
6295            VPBLENDMW512RRR_MASK,
6296            op0.as_operand(),
6297            op1.as_operand(),
6298            op2.as_operand(),
6299            &NOREG,
6300        );
6301    }
6302}
6303
6304impl<'a> VpblendmwMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
6305    fn vpblendmw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
6306        self.emit(
6307            VPBLENDMW512RRM_MASK,
6308            op0.as_operand(),
6309            op1.as_operand(),
6310            op2.as_operand(),
6311            &NOREG,
6312        );
6313    }
6314}
6315
6316/// `VPBLENDMW_MASKZ`.
6317///
6318/// Supported operand variants:
6319///
6320/// ```text
6321/// +---+---------------+
6322/// | # | Operands      |
6323/// +---+---------------+
6324/// | 1 | Xmm, Xmm, Mem |
6325/// | 2 | Xmm, Xmm, Xmm |
6326/// | 3 | Ymm, Ymm, Mem |
6327/// | 4 | Ymm, Ymm, Ymm |
6328/// | 5 | Zmm, Zmm, Mem |
6329/// | 6 | Zmm, Zmm, Zmm |
6330/// +---+---------------+
6331/// ```
6332pub trait VpblendmwMaskzEmitter<A, B, C> {
6333    fn vpblendmw_maskz(&mut self, op0: A, op1: B, op2: C);
6334}
6335
6336impl<'a> VpblendmwMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
6337    fn vpblendmw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
6338        self.emit(
6339            VPBLENDMW128RRR_MASKZ,
6340            op0.as_operand(),
6341            op1.as_operand(),
6342            op2.as_operand(),
6343            &NOREG,
6344        );
6345    }
6346}
6347
6348impl<'a> VpblendmwMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
6349    fn vpblendmw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
6350        self.emit(
6351            VPBLENDMW128RRM_MASKZ,
6352            op0.as_operand(),
6353            op1.as_operand(),
6354            op2.as_operand(),
6355            &NOREG,
6356        );
6357    }
6358}
6359
6360impl<'a> VpblendmwMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
6361    fn vpblendmw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
6362        self.emit(
6363            VPBLENDMW256RRR_MASKZ,
6364            op0.as_operand(),
6365            op1.as_operand(),
6366            op2.as_operand(),
6367            &NOREG,
6368        );
6369    }
6370}
6371
6372impl<'a> VpblendmwMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
6373    fn vpblendmw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
6374        self.emit(
6375            VPBLENDMW256RRM_MASKZ,
6376            op0.as_operand(),
6377            op1.as_operand(),
6378            op2.as_operand(),
6379            &NOREG,
6380        );
6381    }
6382}
6383
6384impl<'a> VpblendmwMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
6385    fn vpblendmw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
6386        self.emit(
6387            VPBLENDMW512RRR_MASKZ,
6388            op0.as_operand(),
6389            op1.as_operand(),
6390            op2.as_operand(),
6391            &NOREG,
6392        );
6393    }
6394}
6395
6396impl<'a> VpblendmwMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
6397    fn vpblendmw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
6398        self.emit(
6399            VPBLENDMW512RRM_MASKZ,
6400            op0.as_operand(),
6401            op1.as_operand(),
6402            op2.as_operand(),
6403            &NOREG,
6404        );
6405    }
6406}
6407
6408/// `VPBROADCASTB`.
6409///
6410/// Supported operand variants:
6411///
6412/// ```text
6413/// +---+----------+
6414/// | # | Operands |
6415/// +---+----------+
6416/// | 1 | Xmm, Mem |
6417/// | 2 | Xmm, Xmm |
6418/// | 3 | Ymm, Mem |
6419/// | 4 | Ymm, Xmm |
6420/// | 5 | Zmm, Mem |
6421/// | 6 | Zmm, Xmm |
6422/// +---+----------+
6423/// ```
6424pub trait VpbroadcastbEmitter<A, B> {
6425    fn vpbroadcastb(&mut self, op0: A, op1: B);
6426}
6427
6428impl<'a> VpbroadcastbEmitter<Xmm, Xmm> for Assembler<'a> {
6429    fn vpbroadcastb(&mut self, op0: Xmm, op1: Xmm) {
6430        self.emit(
6431            VPBROADCASTB128RR,
6432            op0.as_operand(),
6433            op1.as_operand(),
6434            &NOREG,
6435            &NOREG,
6436        );
6437    }
6438}
6439
6440impl<'a> VpbroadcastbEmitter<Xmm, Mem> for Assembler<'a> {
6441    fn vpbroadcastb(&mut self, op0: Xmm, op1: Mem) {
6442        self.emit(
6443            VPBROADCASTB128RM,
6444            op0.as_operand(),
6445            op1.as_operand(),
6446            &NOREG,
6447            &NOREG,
6448        );
6449    }
6450}
6451
6452impl<'a> VpbroadcastbEmitter<Ymm, Xmm> for Assembler<'a> {
6453    fn vpbroadcastb(&mut self, op0: Ymm, op1: Xmm) {
6454        self.emit(
6455            VPBROADCASTB256RR,
6456            op0.as_operand(),
6457            op1.as_operand(),
6458            &NOREG,
6459            &NOREG,
6460        );
6461    }
6462}
6463
6464impl<'a> VpbroadcastbEmitter<Ymm, Mem> for Assembler<'a> {
6465    fn vpbroadcastb(&mut self, op0: Ymm, op1: Mem) {
6466        self.emit(
6467            VPBROADCASTB256RM,
6468            op0.as_operand(),
6469            op1.as_operand(),
6470            &NOREG,
6471            &NOREG,
6472        );
6473    }
6474}
6475
6476impl<'a> VpbroadcastbEmitter<Zmm, Xmm> for Assembler<'a> {
6477    fn vpbroadcastb(&mut self, op0: Zmm, op1: Xmm) {
6478        self.emit(
6479            VPBROADCASTB512RR,
6480            op0.as_operand(),
6481            op1.as_operand(),
6482            &NOREG,
6483            &NOREG,
6484        );
6485    }
6486}
6487
6488impl<'a> VpbroadcastbEmitter<Zmm, Mem> for Assembler<'a> {
6489    fn vpbroadcastb(&mut self, op0: Zmm, op1: Mem) {
6490        self.emit(
6491            VPBROADCASTB512RM,
6492            op0.as_operand(),
6493            op1.as_operand(),
6494            &NOREG,
6495            &NOREG,
6496        );
6497    }
6498}
6499
6500/// `VPBROADCASTB_GP`.
6501///
6502/// Supported operand variants:
6503///
6504/// ```text
6505/// +---+----------+
6506/// | # | Operands |
6507/// +---+----------+
6508/// | 1 | Xmm, Gpd |
6509/// | 2 | Ymm, Gpd |
6510/// | 3 | Zmm, Gpd |
6511/// +---+----------+
6512/// ```
6513pub trait VpbroadcastbGpEmitter<A, B> {
6514    fn vpbroadcastb_gp(&mut self, op0: A, op1: B);
6515}
6516
6517impl<'a> VpbroadcastbGpEmitter<Xmm, Gpd> for Assembler<'a> {
6518    fn vpbroadcastb_gp(&mut self, op0: Xmm, op1: Gpd) {
6519        self.emit(
6520            VPBROADCASTB_GP128RR,
6521            op0.as_operand(),
6522            op1.as_operand(),
6523            &NOREG,
6524            &NOREG,
6525        );
6526    }
6527}
6528
6529impl<'a> VpbroadcastbGpEmitter<Ymm, Gpd> for Assembler<'a> {
6530    fn vpbroadcastb_gp(&mut self, op0: Ymm, op1: Gpd) {
6531        self.emit(
6532            VPBROADCASTB_GP256RR,
6533            op0.as_operand(),
6534            op1.as_operand(),
6535            &NOREG,
6536            &NOREG,
6537        );
6538    }
6539}
6540
6541impl<'a> VpbroadcastbGpEmitter<Zmm, Gpd> for Assembler<'a> {
6542    fn vpbroadcastb_gp(&mut self, op0: Zmm, op1: Gpd) {
6543        self.emit(
6544            VPBROADCASTB_GP512RR,
6545            op0.as_operand(),
6546            op1.as_operand(),
6547            &NOREG,
6548            &NOREG,
6549        );
6550    }
6551}
6552
6553/// `VPBROADCASTB_GP_MASK`.
6554///
6555/// Supported operand variants:
6556///
6557/// ```text
6558/// +---+----------+
6559/// | # | Operands |
6560/// +---+----------+
6561/// | 1 | Xmm, Gpd |
6562/// | 2 | Ymm, Gpd |
6563/// | 3 | Zmm, Gpd |
6564/// +---+----------+
6565/// ```
6566pub trait VpbroadcastbGpMaskEmitter<A, B> {
6567    fn vpbroadcastb_gp_mask(&mut self, op0: A, op1: B);
6568}
6569
6570impl<'a> VpbroadcastbGpMaskEmitter<Xmm, Gpd> for Assembler<'a> {
6571    fn vpbroadcastb_gp_mask(&mut self, op0: Xmm, op1: Gpd) {
6572        self.emit(
6573            VPBROADCASTB_GP128RR_MASK,
6574            op0.as_operand(),
6575            op1.as_operand(),
6576            &NOREG,
6577            &NOREG,
6578        );
6579    }
6580}
6581
6582impl<'a> VpbroadcastbGpMaskEmitter<Ymm, Gpd> for Assembler<'a> {
6583    fn vpbroadcastb_gp_mask(&mut self, op0: Ymm, op1: Gpd) {
6584        self.emit(
6585            VPBROADCASTB_GP256RR_MASK,
6586            op0.as_operand(),
6587            op1.as_operand(),
6588            &NOREG,
6589            &NOREG,
6590        );
6591    }
6592}
6593
6594impl<'a> VpbroadcastbGpMaskEmitter<Zmm, Gpd> for Assembler<'a> {
6595    fn vpbroadcastb_gp_mask(&mut self, op0: Zmm, op1: Gpd) {
6596        self.emit(
6597            VPBROADCASTB_GP512RR_MASK,
6598            op0.as_operand(),
6599            op1.as_operand(),
6600            &NOREG,
6601            &NOREG,
6602        );
6603    }
6604}
6605
6606/// `VPBROADCASTB_GP_MASKZ`.
6607///
6608/// Supported operand variants:
6609///
6610/// ```text
6611/// +---+----------+
6612/// | # | Operands |
6613/// +---+----------+
6614/// | 1 | Xmm, Gpd |
6615/// | 2 | Ymm, Gpd |
6616/// | 3 | Zmm, Gpd |
6617/// +---+----------+
6618/// ```
6619pub trait VpbroadcastbGpMaskzEmitter<A, B> {
6620    fn vpbroadcastb_gp_maskz(&mut self, op0: A, op1: B);
6621}
6622
6623impl<'a> VpbroadcastbGpMaskzEmitter<Xmm, Gpd> for Assembler<'a> {
6624    fn vpbroadcastb_gp_maskz(&mut self, op0: Xmm, op1: Gpd) {
6625        self.emit(
6626            VPBROADCASTB_GP128RR_MASKZ,
6627            op0.as_operand(),
6628            op1.as_operand(),
6629            &NOREG,
6630            &NOREG,
6631        );
6632    }
6633}
6634
6635impl<'a> VpbroadcastbGpMaskzEmitter<Ymm, Gpd> for Assembler<'a> {
6636    fn vpbroadcastb_gp_maskz(&mut self, op0: Ymm, op1: Gpd) {
6637        self.emit(
6638            VPBROADCASTB_GP256RR_MASKZ,
6639            op0.as_operand(),
6640            op1.as_operand(),
6641            &NOREG,
6642            &NOREG,
6643        );
6644    }
6645}
6646
6647impl<'a> VpbroadcastbGpMaskzEmitter<Zmm, Gpd> for Assembler<'a> {
6648    fn vpbroadcastb_gp_maskz(&mut self, op0: Zmm, op1: Gpd) {
6649        self.emit(
6650            VPBROADCASTB_GP512RR_MASKZ,
6651            op0.as_operand(),
6652            op1.as_operand(),
6653            &NOREG,
6654            &NOREG,
6655        );
6656    }
6657}
6658
6659/// `VPBROADCASTB_MASK`.
6660///
6661/// Supported operand variants:
6662///
6663/// ```text
6664/// +---+----------+
6665/// | # | Operands |
6666/// +---+----------+
6667/// | 1 | Xmm, Mem |
6668/// | 2 | Xmm, Xmm |
6669/// | 3 | Ymm, Mem |
6670/// | 4 | Ymm, Xmm |
6671/// | 5 | Zmm, Mem |
6672/// | 6 | Zmm, Xmm |
6673/// +---+----------+
6674/// ```
6675pub trait VpbroadcastbMaskEmitter<A, B> {
6676    fn vpbroadcastb_mask(&mut self, op0: A, op1: B);
6677}
6678
6679impl<'a> VpbroadcastbMaskEmitter<Xmm, Xmm> for Assembler<'a> {
6680    fn vpbroadcastb_mask(&mut self, op0: Xmm, op1: Xmm) {
6681        self.emit(
6682            VPBROADCASTB128RR_MASK,
6683            op0.as_operand(),
6684            op1.as_operand(),
6685            &NOREG,
6686            &NOREG,
6687        );
6688    }
6689}
6690
6691impl<'a> VpbroadcastbMaskEmitter<Xmm, Mem> for Assembler<'a> {
6692    fn vpbroadcastb_mask(&mut self, op0: Xmm, op1: Mem) {
6693        self.emit(
6694            VPBROADCASTB128RM_MASK,
6695            op0.as_operand(),
6696            op1.as_operand(),
6697            &NOREG,
6698            &NOREG,
6699        );
6700    }
6701}
6702
6703impl<'a> VpbroadcastbMaskEmitter<Ymm, Xmm> for Assembler<'a> {
6704    fn vpbroadcastb_mask(&mut self, op0: Ymm, op1: Xmm) {
6705        self.emit(
6706            VPBROADCASTB256RR_MASK,
6707            op0.as_operand(),
6708            op1.as_operand(),
6709            &NOREG,
6710            &NOREG,
6711        );
6712    }
6713}
6714
6715impl<'a> VpbroadcastbMaskEmitter<Ymm, Mem> for Assembler<'a> {
6716    fn vpbroadcastb_mask(&mut self, op0: Ymm, op1: Mem) {
6717        self.emit(
6718            VPBROADCASTB256RM_MASK,
6719            op0.as_operand(),
6720            op1.as_operand(),
6721            &NOREG,
6722            &NOREG,
6723        );
6724    }
6725}
6726
6727impl<'a> VpbroadcastbMaskEmitter<Zmm, Xmm> for Assembler<'a> {
6728    fn vpbroadcastb_mask(&mut self, op0: Zmm, op1: Xmm) {
6729        self.emit(
6730            VPBROADCASTB512RR_MASK,
6731            op0.as_operand(),
6732            op1.as_operand(),
6733            &NOREG,
6734            &NOREG,
6735        );
6736    }
6737}
6738
6739impl<'a> VpbroadcastbMaskEmitter<Zmm, Mem> for Assembler<'a> {
6740    fn vpbroadcastb_mask(&mut self, op0: Zmm, op1: Mem) {
6741        self.emit(
6742            VPBROADCASTB512RM_MASK,
6743            op0.as_operand(),
6744            op1.as_operand(),
6745            &NOREG,
6746            &NOREG,
6747        );
6748    }
6749}
6750
6751/// `VPBROADCASTB_MASKZ`.
6752///
6753/// Supported operand variants:
6754///
6755/// ```text
6756/// +---+----------+
6757/// | # | Operands |
6758/// +---+----------+
6759/// | 1 | Xmm, Mem |
6760/// | 2 | Xmm, Xmm |
6761/// | 3 | Ymm, Mem |
6762/// | 4 | Ymm, Xmm |
6763/// | 5 | Zmm, Mem |
6764/// | 6 | Zmm, Xmm |
6765/// +---+----------+
6766/// ```
6767pub trait VpbroadcastbMaskzEmitter<A, B> {
6768    fn vpbroadcastb_maskz(&mut self, op0: A, op1: B);
6769}
6770
6771impl<'a> VpbroadcastbMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
6772    fn vpbroadcastb_maskz(&mut self, op0: Xmm, op1: Xmm) {
6773        self.emit(
6774            VPBROADCASTB128RR_MASKZ,
6775            op0.as_operand(),
6776            op1.as_operand(),
6777            &NOREG,
6778            &NOREG,
6779        );
6780    }
6781}
6782
6783impl<'a> VpbroadcastbMaskzEmitter<Xmm, Mem> for Assembler<'a> {
6784    fn vpbroadcastb_maskz(&mut self, op0: Xmm, op1: Mem) {
6785        self.emit(
6786            VPBROADCASTB128RM_MASKZ,
6787            op0.as_operand(),
6788            op1.as_operand(),
6789            &NOREG,
6790            &NOREG,
6791        );
6792    }
6793}
6794
6795impl<'a> VpbroadcastbMaskzEmitter<Ymm, Xmm> for Assembler<'a> {
6796    fn vpbroadcastb_maskz(&mut self, op0: Ymm, op1: Xmm) {
6797        self.emit(
6798            VPBROADCASTB256RR_MASKZ,
6799            op0.as_operand(),
6800            op1.as_operand(),
6801            &NOREG,
6802            &NOREG,
6803        );
6804    }
6805}
6806
6807impl<'a> VpbroadcastbMaskzEmitter<Ymm, Mem> for Assembler<'a> {
6808    fn vpbroadcastb_maskz(&mut self, op0: Ymm, op1: Mem) {
6809        self.emit(
6810            VPBROADCASTB256RM_MASKZ,
6811            op0.as_operand(),
6812            op1.as_operand(),
6813            &NOREG,
6814            &NOREG,
6815        );
6816    }
6817}
6818
6819impl<'a> VpbroadcastbMaskzEmitter<Zmm, Xmm> for Assembler<'a> {
6820    fn vpbroadcastb_maskz(&mut self, op0: Zmm, op1: Xmm) {
6821        self.emit(
6822            VPBROADCASTB512RR_MASKZ,
6823            op0.as_operand(),
6824            op1.as_operand(),
6825            &NOREG,
6826            &NOREG,
6827        );
6828    }
6829}
6830
6831impl<'a> VpbroadcastbMaskzEmitter<Zmm, Mem> for Assembler<'a> {
6832    fn vpbroadcastb_maskz(&mut self, op0: Zmm, op1: Mem) {
6833        self.emit(
6834            VPBROADCASTB512RM_MASKZ,
6835            op0.as_operand(),
6836            op1.as_operand(),
6837            &NOREG,
6838            &NOREG,
6839        );
6840    }
6841}
6842
6843/// `VPBROADCASTW`.
6844///
6845/// Supported operand variants:
6846///
6847/// ```text
6848/// +---+----------+
6849/// | # | Operands |
6850/// +---+----------+
6851/// | 1 | Xmm, Mem |
6852/// | 2 | Xmm, Xmm |
6853/// | 3 | Ymm, Mem |
6854/// | 4 | Ymm, Xmm |
6855/// | 5 | Zmm, Mem |
6856/// | 6 | Zmm, Xmm |
6857/// +---+----------+
6858/// ```
6859pub trait VpbroadcastwEmitter<A, B> {
6860    fn vpbroadcastw(&mut self, op0: A, op1: B);
6861}
6862
6863impl<'a> VpbroadcastwEmitter<Xmm, Xmm> for Assembler<'a> {
6864    fn vpbroadcastw(&mut self, op0: Xmm, op1: Xmm) {
6865        self.emit(
6866            VPBROADCASTW128RR,
6867            op0.as_operand(),
6868            op1.as_operand(),
6869            &NOREG,
6870            &NOREG,
6871        );
6872    }
6873}
6874
6875impl<'a> VpbroadcastwEmitter<Xmm, Mem> for Assembler<'a> {
6876    fn vpbroadcastw(&mut self, op0: Xmm, op1: Mem) {
6877        self.emit(
6878            VPBROADCASTW128RM,
6879            op0.as_operand(),
6880            op1.as_operand(),
6881            &NOREG,
6882            &NOREG,
6883        );
6884    }
6885}
6886
6887impl<'a> VpbroadcastwEmitter<Ymm, Xmm> for Assembler<'a> {
6888    fn vpbroadcastw(&mut self, op0: Ymm, op1: Xmm) {
6889        self.emit(
6890            VPBROADCASTW256RR,
6891            op0.as_operand(),
6892            op1.as_operand(),
6893            &NOREG,
6894            &NOREG,
6895        );
6896    }
6897}
6898
6899impl<'a> VpbroadcastwEmitter<Ymm, Mem> for Assembler<'a> {
6900    fn vpbroadcastw(&mut self, op0: Ymm, op1: Mem) {
6901        self.emit(
6902            VPBROADCASTW256RM,
6903            op0.as_operand(),
6904            op1.as_operand(),
6905            &NOREG,
6906            &NOREG,
6907        );
6908    }
6909}
6910
6911impl<'a> VpbroadcastwEmitter<Zmm, Xmm> for Assembler<'a> {
6912    fn vpbroadcastw(&mut self, op0: Zmm, op1: Xmm) {
6913        self.emit(
6914            VPBROADCASTW512RR,
6915            op0.as_operand(),
6916            op1.as_operand(),
6917            &NOREG,
6918            &NOREG,
6919        );
6920    }
6921}
6922
6923impl<'a> VpbroadcastwEmitter<Zmm, Mem> for Assembler<'a> {
6924    fn vpbroadcastw(&mut self, op0: Zmm, op1: Mem) {
6925        self.emit(
6926            VPBROADCASTW512RM,
6927            op0.as_operand(),
6928            op1.as_operand(),
6929            &NOREG,
6930            &NOREG,
6931        );
6932    }
6933}
6934
6935/// `VPBROADCASTW_GP`.
6936///
6937/// Supported operand variants:
6938///
6939/// ```text
6940/// +---+----------+
6941/// | # | Operands |
6942/// +---+----------+
6943/// | 1 | Xmm, Gpd |
6944/// | 2 | Ymm, Gpd |
6945/// | 3 | Zmm, Gpd |
6946/// +---+----------+
6947/// ```
6948pub trait VpbroadcastwGpEmitter<A, B> {
6949    fn vpbroadcastw_gp(&mut self, op0: A, op1: B);
6950}
6951
6952impl<'a> VpbroadcastwGpEmitter<Xmm, Gpd> for Assembler<'a> {
6953    fn vpbroadcastw_gp(&mut self, op0: Xmm, op1: Gpd) {
6954        self.emit(
6955            VPBROADCASTW_GP128RR,
6956            op0.as_operand(),
6957            op1.as_operand(),
6958            &NOREG,
6959            &NOREG,
6960        );
6961    }
6962}
6963
6964impl<'a> VpbroadcastwGpEmitter<Ymm, Gpd> for Assembler<'a> {
6965    fn vpbroadcastw_gp(&mut self, op0: Ymm, op1: Gpd) {
6966        self.emit(
6967            VPBROADCASTW_GP256RR,
6968            op0.as_operand(),
6969            op1.as_operand(),
6970            &NOREG,
6971            &NOREG,
6972        );
6973    }
6974}
6975
6976impl<'a> VpbroadcastwGpEmitter<Zmm, Gpd> for Assembler<'a> {
6977    fn vpbroadcastw_gp(&mut self, op0: Zmm, op1: Gpd) {
6978        self.emit(
6979            VPBROADCASTW_GP512RR,
6980            op0.as_operand(),
6981            op1.as_operand(),
6982            &NOREG,
6983            &NOREG,
6984        );
6985    }
6986}
6987
6988/// `VPBROADCASTW_GP_MASK`.
6989///
6990/// Supported operand variants:
6991///
6992/// ```text
6993/// +---+----------+
6994/// | # | Operands |
6995/// +---+----------+
6996/// | 1 | Xmm, Gpd |
6997/// | 2 | Ymm, Gpd |
6998/// | 3 | Zmm, Gpd |
6999/// +---+----------+
7000/// ```
7001pub trait VpbroadcastwGpMaskEmitter<A, B> {
7002    fn vpbroadcastw_gp_mask(&mut self, op0: A, op1: B);
7003}
7004
7005impl<'a> VpbroadcastwGpMaskEmitter<Xmm, Gpd> for Assembler<'a> {
7006    fn vpbroadcastw_gp_mask(&mut self, op0: Xmm, op1: Gpd) {
7007        self.emit(
7008            VPBROADCASTW_GP128RR_MASK,
7009            op0.as_operand(),
7010            op1.as_operand(),
7011            &NOREG,
7012            &NOREG,
7013        );
7014    }
7015}
7016
7017impl<'a> VpbroadcastwGpMaskEmitter<Ymm, Gpd> for Assembler<'a> {
7018    fn vpbroadcastw_gp_mask(&mut self, op0: Ymm, op1: Gpd) {
7019        self.emit(
7020            VPBROADCASTW_GP256RR_MASK,
7021            op0.as_operand(),
7022            op1.as_operand(),
7023            &NOREG,
7024            &NOREG,
7025        );
7026    }
7027}
7028
7029impl<'a> VpbroadcastwGpMaskEmitter<Zmm, Gpd> for Assembler<'a> {
7030    fn vpbroadcastw_gp_mask(&mut self, op0: Zmm, op1: Gpd) {
7031        self.emit(
7032            VPBROADCASTW_GP512RR_MASK,
7033            op0.as_operand(),
7034            op1.as_operand(),
7035            &NOREG,
7036            &NOREG,
7037        );
7038    }
7039}
7040
7041/// `VPBROADCASTW_GP_MASKZ`.
7042///
7043/// Supported operand variants:
7044///
7045/// ```text
7046/// +---+----------+
7047/// | # | Operands |
7048/// +---+----------+
7049/// | 1 | Xmm, Gpd |
7050/// | 2 | Ymm, Gpd |
7051/// | 3 | Zmm, Gpd |
7052/// +---+----------+
7053/// ```
7054pub trait VpbroadcastwGpMaskzEmitter<A, B> {
7055    fn vpbroadcastw_gp_maskz(&mut self, op0: A, op1: B);
7056}
7057
7058impl<'a> VpbroadcastwGpMaskzEmitter<Xmm, Gpd> for Assembler<'a> {
7059    fn vpbroadcastw_gp_maskz(&mut self, op0: Xmm, op1: Gpd) {
7060        self.emit(
7061            VPBROADCASTW_GP128RR_MASKZ,
7062            op0.as_operand(),
7063            op1.as_operand(),
7064            &NOREG,
7065            &NOREG,
7066        );
7067    }
7068}
7069
7070impl<'a> VpbroadcastwGpMaskzEmitter<Ymm, Gpd> for Assembler<'a> {
7071    fn vpbroadcastw_gp_maskz(&mut self, op0: Ymm, op1: Gpd) {
7072        self.emit(
7073            VPBROADCASTW_GP256RR_MASKZ,
7074            op0.as_operand(),
7075            op1.as_operand(),
7076            &NOREG,
7077            &NOREG,
7078        );
7079    }
7080}
7081
7082impl<'a> VpbroadcastwGpMaskzEmitter<Zmm, Gpd> for Assembler<'a> {
7083    fn vpbroadcastw_gp_maskz(&mut self, op0: Zmm, op1: Gpd) {
7084        self.emit(
7085            VPBROADCASTW_GP512RR_MASKZ,
7086            op0.as_operand(),
7087            op1.as_operand(),
7088            &NOREG,
7089            &NOREG,
7090        );
7091    }
7092}
7093
7094/// `VPBROADCASTW_MASK`.
7095///
7096/// Supported operand variants:
7097///
7098/// ```text
7099/// +---+----------+
7100/// | # | Operands |
7101/// +---+----------+
7102/// | 1 | Xmm, Mem |
7103/// | 2 | Xmm, Xmm |
7104/// | 3 | Ymm, Mem |
7105/// | 4 | Ymm, Xmm |
7106/// | 5 | Zmm, Mem |
7107/// | 6 | Zmm, Xmm |
7108/// +---+----------+
7109/// ```
7110pub trait VpbroadcastwMaskEmitter<A, B> {
7111    fn vpbroadcastw_mask(&mut self, op0: A, op1: B);
7112}
7113
7114impl<'a> VpbroadcastwMaskEmitter<Xmm, Xmm> for Assembler<'a> {
7115    fn vpbroadcastw_mask(&mut self, op0: Xmm, op1: Xmm) {
7116        self.emit(
7117            VPBROADCASTW128RR_MASK,
7118            op0.as_operand(),
7119            op1.as_operand(),
7120            &NOREG,
7121            &NOREG,
7122        );
7123    }
7124}
7125
7126impl<'a> VpbroadcastwMaskEmitter<Xmm, Mem> for Assembler<'a> {
7127    fn vpbroadcastw_mask(&mut self, op0: Xmm, op1: Mem) {
7128        self.emit(
7129            VPBROADCASTW128RM_MASK,
7130            op0.as_operand(),
7131            op1.as_operand(),
7132            &NOREG,
7133            &NOREG,
7134        );
7135    }
7136}
7137
7138impl<'a> VpbroadcastwMaskEmitter<Ymm, Xmm> for Assembler<'a> {
7139    fn vpbroadcastw_mask(&mut self, op0: Ymm, op1: Xmm) {
7140        self.emit(
7141            VPBROADCASTW256RR_MASK,
7142            op0.as_operand(),
7143            op1.as_operand(),
7144            &NOREG,
7145            &NOREG,
7146        );
7147    }
7148}
7149
7150impl<'a> VpbroadcastwMaskEmitter<Ymm, Mem> for Assembler<'a> {
7151    fn vpbroadcastw_mask(&mut self, op0: Ymm, op1: Mem) {
7152        self.emit(
7153            VPBROADCASTW256RM_MASK,
7154            op0.as_operand(),
7155            op1.as_operand(),
7156            &NOREG,
7157            &NOREG,
7158        );
7159    }
7160}
7161
7162impl<'a> VpbroadcastwMaskEmitter<Zmm, Xmm> for Assembler<'a> {
7163    fn vpbroadcastw_mask(&mut self, op0: Zmm, op1: Xmm) {
7164        self.emit(
7165            VPBROADCASTW512RR_MASK,
7166            op0.as_operand(),
7167            op1.as_operand(),
7168            &NOREG,
7169            &NOREG,
7170        );
7171    }
7172}
7173
7174impl<'a> VpbroadcastwMaskEmitter<Zmm, Mem> for Assembler<'a> {
7175    fn vpbroadcastw_mask(&mut self, op0: Zmm, op1: Mem) {
7176        self.emit(
7177            VPBROADCASTW512RM_MASK,
7178            op0.as_operand(),
7179            op1.as_operand(),
7180            &NOREG,
7181            &NOREG,
7182        );
7183    }
7184}
7185
7186/// `VPBROADCASTW_MASKZ`.
7187///
7188/// Supported operand variants:
7189///
7190/// ```text
7191/// +---+----------+
7192/// | # | Operands |
7193/// +---+----------+
7194/// | 1 | Xmm, Mem |
7195/// | 2 | Xmm, Xmm |
7196/// | 3 | Ymm, Mem |
7197/// | 4 | Ymm, Xmm |
7198/// | 5 | Zmm, Mem |
7199/// | 6 | Zmm, Xmm |
7200/// +---+----------+
7201/// ```
7202pub trait VpbroadcastwMaskzEmitter<A, B> {
7203    fn vpbroadcastw_maskz(&mut self, op0: A, op1: B);
7204}
7205
7206impl<'a> VpbroadcastwMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
7207    fn vpbroadcastw_maskz(&mut self, op0: Xmm, op1: Xmm) {
7208        self.emit(
7209            VPBROADCASTW128RR_MASKZ,
7210            op0.as_operand(),
7211            op1.as_operand(),
7212            &NOREG,
7213            &NOREG,
7214        );
7215    }
7216}
7217
7218impl<'a> VpbroadcastwMaskzEmitter<Xmm, Mem> for Assembler<'a> {
7219    fn vpbroadcastw_maskz(&mut self, op0: Xmm, op1: Mem) {
7220        self.emit(
7221            VPBROADCASTW128RM_MASKZ,
7222            op0.as_operand(),
7223            op1.as_operand(),
7224            &NOREG,
7225            &NOREG,
7226        );
7227    }
7228}
7229
7230impl<'a> VpbroadcastwMaskzEmitter<Ymm, Xmm> for Assembler<'a> {
7231    fn vpbroadcastw_maskz(&mut self, op0: Ymm, op1: Xmm) {
7232        self.emit(
7233            VPBROADCASTW256RR_MASKZ,
7234            op0.as_operand(),
7235            op1.as_operand(),
7236            &NOREG,
7237            &NOREG,
7238        );
7239    }
7240}
7241
7242impl<'a> VpbroadcastwMaskzEmitter<Ymm, Mem> for Assembler<'a> {
7243    fn vpbroadcastw_maskz(&mut self, op0: Ymm, op1: Mem) {
7244        self.emit(
7245            VPBROADCASTW256RM_MASKZ,
7246            op0.as_operand(),
7247            op1.as_operand(),
7248            &NOREG,
7249            &NOREG,
7250        );
7251    }
7252}
7253
7254impl<'a> VpbroadcastwMaskzEmitter<Zmm, Xmm> for Assembler<'a> {
7255    fn vpbroadcastw_maskz(&mut self, op0: Zmm, op1: Xmm) {
7256        self.emit(
7257            VPBROADCASTW512RR_MASKZ,
7258            op0.as_operand(),
7259            op1.as_operand(),
7260            &NOREG,
7261            &NOREG,
7262        );
7263    }
7264}
7265
7266impl<'a> VpbroadcastwMaskzEmitter<Zmm, Mem> for Assembler<'a> {
7267    fn vpbroadcastw_maskz(&mut self, op0: Zmm, op1: Mem) {
7268        self.emit(
7269            VPBROADCASTW512RM_MASKZ,
7270            op0.as_operand(),
7271            op1.as_operand(),
7272            &NOREG,
7273            &NOREG,
7274        );
7275    }
7276}
7277
7278/// `VPCMPB`.
7279///
7280/// Supported operand variants:
7281///
7282/// ```text
7283/// +---+---------------------+
7284/// | # | Operands            |
7285/// +---+---------------------+
7286/// | 1 | KReg, Xmm, Mem, Imm |
7287/// | 2 | KReg, Xmm, Xmm, Imm |
7288/// | 3 | KReg, Ymm, Mem, Imm |
7289/// | 4 | KReg, Ymm, Ymm, Imm |
7290/// | 5 | KReg, Zmm, Mem, Imm |
7291/// | 6 | KReg, Zmm, Zmm, Imm |
7292/// +---+---------------------+
7293/// ```
7294pub trait VpcmpbEmitter<A, B, C, D> {
7295    fn vpcmpb(&mut self, op0: A, op1: B, op2: C, op3: D);
7296}
7297
7298impl<'a> VpcmpbEmitter<KReg, Xmm, Xmm, Imm> for Assembler<'a> {
7299    fn vpcmpb(&mut self, op0: KReg, op1: Xmm, op2: Xmm, op3: Imm) {
7300        self.emit(
7301            VPCMPB128KRRI,
7302            op0.as_operand(),
7303            op1.as_operand(),
7304            op2.as_operand(),
7305            op3.as_operand(),
7306        );
7307    }
7308}
7309
7310impl<'a> VpcmpbEmitter<KReg, Xmm, Mem, Imm> for Assembler<'a> {
7311    fn vpcmpb(&mut self, op0: KReg, op1: Xmm, op2: Mem, op3: Imm) {
7312        self.emit(
7313            VPCMPB128KRMI,
7314            op0.as_operand(),
7315            op1.as_operand(),
7316            op2.as_operand(),
7317            op3.as_operand(),
7318        );
7319    }
7320}
7321
7322impl<'a> VpcmpbEmitter<KReg, Ymm, Ymm, Imm> for Assembler<'a> {
7323    fn vpcmpb(&mut self, op0: KReg, op1: Ymm, op2: Ymm, op3: Imm) {
7324        self.emit(
7325            VPCMPB256KRRI,
7326            op0.as_operand(),
7327            op1.as_operand(),
7328            op2.as_operand(),
7329            op3.as_operand(),
7330        );
7331    }
7332}
7333
7334impl<'a> VpcmpbEmitter<KReg, Ymm, Mem, Imm> for Assembler<'a> {
7335    fn vpcmpb(&mut self, op0: KReg, op1: Ymm, op2: Mem, op3: Imm) {
7336        self.emit(
7337            VPCMPB256KRMI,
7338            op0.as_operand(),
7339            op1.as_operand(),
7340            op2.as_operand(),
7341            op3.as_operand(),
7342        );
7343    }
7344}
7345
7346impl<'a> VpcmpbEmitter<KReg, Zmm, Zmm, Imm> for Assembler<'a> {
7347    fn vpcmpb(&mut self, op0: KReg, op1: Zmm, op2: Zmm, op3: Imm) {
7348        self.emit(
7349            VPCMPB512KRRI,
7350            op0.as_operand(),
7351            op1.as_operand(),
7352            op2.as_operand(),
7353            op3.as_operand(),
7354        );
7355    }
7356}
7357
7358impl<'a> VpcmpbEmitter<KReg, Zmm, Mem, Imm> for Assembler<'a> {
7359    fn vpcmpb(&mut self, op0: KReg, op1: Zmm, op2: Mem, op3: Imm) {
7360        self.emit(
7361            VPCMPB512KRMI,
7362            op0.as_operand(),
7363            op1.as_operand(),
7364            op2.as_operand(),
7365            op3.as_operand(),
7366        );
7367    }
7368}
7369
7370/// `VPCMPB_MASK`.
7371///
7372/// Supported operand variants:
7373///
7374/// ```text
7375/// +---+---------------------+
7376/// | # | Operands            |
7377/// +---+---------------------+
7378/// | 1 | KReg, Xmm, Mem, Imm |
7379/// | 2 | KReg, Xmm, Xmm, Imm |
7380/// | 3 | KReg, Ymm, Mem, Imm |
7381/// | 4 | KReg, Ymm, Ymm, Imm |
7382/// | 5 | KReg, Zmm, Mem, Imm |
7383/// | 6 | KReg, Zmm, Zmm, Imm |
7384/// +---+---------------------+
7385/// ```
7386pub trait VpcmpbMaskEmitter<A, B, C, D> {
7387    fn vpcmpb_mask(&mut self, op0: A, op1: B, op2: C, op3: D);
7388}
7389
7390impl<'a> VpcmpbMaskEmitter<KReg, Xmm, Xmm, Imm> for Assembler<'a> {
7391    fn vpcmpb_mask(&mut self, op0: KReg, op1: Xmm, op2: Xmm, op3: Imm) {
7392        self.emit(
7393            VPCMPB128KRRI_MASK,
7394            op0.as_operand(),
7395            op1.as_operand(),
7396            op2.as_operand(),
7397            op3.as_operand(),
7398        );
7399    }
7400}
7401
7402impl<'a> VpcmpbMaskEmitter<KReg, Xmm, Mem, Imm> for Assembler<'a> {
7403    fn vpcmpb_mask(&mut self, op0: KReg, op1: Xmm, op2: Mem, op3: Imm) {
7404        self.emit(
7405            VPCMPB128KRMI_MASK,
7406            op0.as_operand(),
7407            op1.as_operand(),
7408            op2.as_operand(),
7409            op3.as_operand(),
7410        );
7411    }
7412}
7413
7414impl<'a> VpcmpbMaskEmitter<KReg, Ymm, Ymm, Imm> for Assembler<'a> {
7415    fn vpcmpb_mask(&mut self, op0: KReg, op1: Ymm, op2: Ymm, op3: Imm) {
7416        self.emit(
7417            VPCMPB256KRRI_MASK,
7418            op0.as_operand(),
7419            op1.as_operand(),
7420            op2.as_operand(),
7421            op3.as_operand(),
7422        );
7423    }
7424}
7425
7426impl<'a> VpcmpbMaskEmitter<KReg, Ymm, Mem, Imm> for Assembler<'a> {
7427    fn vpcmpb_mask(&mut self, op0: KReg, op1: Ymm, op2: Mem, op3: Imm) {
7428        self.emit(
7429            VPCMPB256KRMI_MASK,
7430            op0.as_operand(),
7431            op1.as_operand(),
7432            op2.as_operand(),
7433            op3.as_operand(),
7434        );
7435    }
7436}
7437
7438impl<'a> VpcmpbMaskEmitter<KReg, Zmm, Zmm, Imm> for Assembler<'a> {
7439    fn vpcmpb_mask(&mut self, op0: KReg, op1: Zmm, op2: Zmm, op3: Imm) {
7440        self.emit(
7441            VPCMPB512KRRI_MASK,
7442            op0.as_operand(),
7443            op1.as_operand(),
7444            op2.as_operand(),
7445            op3.as_operand(),
7446        );
7447    }
7448}
7449
7450impl<'a> VpcmpbMaskEmitter<KReg, Zmm, Mem, Imm> for Assembler<'a> {
7451    fn vpcmpb_mask(&mut self, op0: KReg, op1: Zmm, op2: Mem, op3: Imm) {
7452        self.emit(
7453            VPCMPB512KRMI_MASK,
7454            op0.as_operand(),
7455            op1.as_operand(),
7456            op2.as_operand(),
7457            op3.as_operand(),
7458        );
7459    }
7460}
7461
7462/// `VPCMPUB`.
7463///
7464/// Supported operand variants:
7465///
7466/// ```text
7467/// +---+---------------------+
7468/// | # | Operands            |
7469/// +---+---------------------+
7470/// | 1 | KReg, Xmm, Mem, Imm |
7471/// | 2 | KReg, Xmm, Xmm, Imm |
7472/// | 3 | KReg, Ymm, Mem, Imm |
7473/// | 4 | KReg, Ymm, Ymm, Imm |
7474/// | 5 | KReg, Zmm, Mem, Imm |
7475/// | 6 | KReg, Zmm, Zmm, Imm |
7476/// +---+---------------------+
7477/// ```
7478pub trait VpcmpubEmitter<A, B, C, D> {
7479    fn vpcmpub(&mut self, op0: A, op1: B, op2: C, op3: D);
7480}
7481
7482impl<'a> VpcmpubEmitter<KReg, Xmm, Xmm, Imm> for Assembler<'a> {
7483    fn vpcmpub(&mut self, op0: KReg, op1: Xmm, op2: Xmm, op3: Imm) {
7484        self.emit(
7485            VPCMPUB128KRRI,
7486            op0.as_operand(),
7487            op1.as_operand(),
7488            op2.as_operand(),
7489            op3.as_operand(),
7490        );
7491    }
7492}
7493
7494impl<'a> VpcmpubEmitter<KReg, Xmm, Mem, Imm> for Assembler<'a> {
7495    fn vpcmpub(&mut self, op0: KReg, op1: Xmm, op2: Mem, op3: Imm) {
7496        self.emit(
7497            VPCMPUB128KRMI,
7498            op0.as_operand(),
7499            op1.as_operand(),
7500            op2.as_operand(),
7501            op3.as_operand(),
7502        );
7503    }
7504}
7505
7506impl<'a> VpcmpubEmitter<KReg, Ymm, Ymm, Imm> for Assembler<'a> {
7507    fn vpcmpub(&mut self, op0: KReg, op1: Ymm, op2: Ymm, op3: Imm) {
7508        self.emit(
7509            VPCMPUB256KRRI,
7510            op0.as_operand(),
7511            op1.as_operand(),
7512            op2.as_operand(),
7513            op3.as_operand(),
7514        );
7515    }
7516}
7517
7518impl<'a> VpcmpubEmitter<KReg, Ymm, Mem, Imm> for Assembler<'a> {
7519    fn vpcmpub(&mut self, op0: KReg, op1: Ymm, op2: Mem, op3: Imm) {
7520        self.emit(
7521            VPCMPUB256KRMI,
7522            op0.as_operand(),
7523            op1.as_operand(),
7524            op2.as_operand(),
7525            op3.as_operand(),
7526        );
7527    }
7528}
7529
7530impl<'a> VpcmpubEmitter<KReg, Zmm, Zmm, Imm> for Assembler<'a> {
7531    fn vpcmpub(&mut self, op0: KReg, op1: Zmm, op2: Zmm, op3: Imm) {
7532        self.emit(
7533            VPCMPUB512KRRI,
7534            op0.as_operand(),
7535            op1.as_operand(),
7536            op2.as_operand(),
7537            op3.as_operand(),
7538        );
7539    }
7540}
7541
7542impl<'a> VpcmpubEmitter<KReg, Zmm, Mem, Imm> for Assembler<'a> {
7543    fn vpcmpub(&mut self, op0: KReg, op1: Zmm, op2: Mem, op3: Imm) {
7544        self.emit(
7545            VPCMPUB512KRMI,
7546            op0.as_operand(),
7547            op1.as_operand(),
7548            op2.as_operand(),
7549            op3.as_operand(),
7550        );
7551    }
7552}
7553
7554/// `VPCMPUB_MASK`.
7555///
7556/// Supported operand variants:
7557///
7558/// ```text
7559/// +---+---------------------+
7560/// | # | Operands            |
7561/// +---+---------------------+
7562/// | 1 | KReg, Xmm, Mem, Imm |
7563/// | 2 | KReg, Xmm, Xmm, Imm |
7564/// | 3 | KReg, Ymm, Mem, Imm |
7565/// | 4 | KReg, Ymm, Ymm, Imm |
7566/// | 5 | KReg, Zmm, Mem, Imm |
7567/// | 6 | KReg, Zmm, Zmm, Imm |
7568/// +---+---------------------+
7569/// ```
7570pub trait VpcmpubMaskEmitter<A, B, C, D> {
7571    fn vpcmpub_mask(&mut self, op0: A, op1: B, op2: C, op3: D);
7572}
7573
7574impl<'a> VpcmpubMaskEmitter<KReg, Xmm, Xmm, Imm> for Assembler<'a> {
7575    fn vpcmpub_mask(&mut self, op0: KReg, op1: Xmm, op2: Xmm, op3: Imm) {
7576        self.emit(
7577            VPCMPUB128KRRI_MASK,
7578            op0.as_operand(),
7579            op1.as_operand(),
7580            op2.as_operand(),
7581            op3.as_operand(),
7582        );
7583    }
7584}
7585
7586impl<'a> VpcmpubMaskEmitter<KReg, Xmm, Mem, Imm> for Assembler<'a> {
7587    fn vpcmpub_mask(&mut self, op0: KReg, op1: Xmm, op2: Mem, op3: Imm) {
7588        self.emit(
7589            VPCMPUB128KRMI_MASK,
7590            op0.as_operand(),
7591            op1.as_operand(),
7592            op2.as_operand(),
7593            op3.as_operand(),
7594        );
7595    }
7596}
7597
7598impl<'a> VpcmpubMaskEmitter<KReg, Ymm, Ymm, Imm> for Assembler<'a> {
7599    fn vpcmpub_mask(&mut self, op0: KReg, op1: Ymm, op2: Ymm, op3: Imm) {
7600        self.emit(
7601            VPCMPUB256KRRI_MASK,
7602            op0.as_operand(),
7603            op1.as_operand(),
7604            op2.as_operand(),
7605            op3.as_operand(),
7606        );
7607    }
7608}
7609
7610impl<'a> VpcmpubMaskEmitter<KReg, Ymm, Mem, Imm> for Assembler<'a> {
7611    fn vpcmpub_mask(&mut self, op0: KReg, op1: Ymm, op2: Mem, op3: Imm) {
7612        self.emit(
7613            VPCMPUB256KRMI_MASK,
7614            op0.as_operand(),
7615            op1.as_operand(),
7616            op2.as_operand(),
7617            op3.as_operand(),
7618        );
7619    }
7620}
7621
7622impl<'a> VpcmpubMaskEmitter<KReg, Zmm, Zmm, Imm> for Assembler<'a> {
7623    fn vpcmpub_mask(&mut self, op0: KReg, op1: Zmm, op2: Zmm, op3: Imm) {
7624        self.emit(
7625            VPCMPUB512KRRI_MASK,
7626            op0.as_operand(),
7627            op1.as_operand(),
7628            op2.as_operand(),
7629            op3.as_operand(),
7630        );
7631    }
7632}
7633
7634impl<'a> VpcmpubMaskEmitter<KReg, Zmm, Mem, Imm> for Assembler<'a> {
7635    fn vpcmpub_mask(&mut self, op0: KReg, op1: Zmm, op2: Mem, op3: Imm) {
7636        self.emit(
7637            VPCMPUB512KRMI_MASK,
7638            op0.as_operand(),
7639            op1.as_operand(),
7640            op2.as_operand(),
7641            op3.as_operand(),
7642        );
7643    }
7644}
7645
7646/// `VPCMPUW`.
7647///
7648/// Supported operand variants:
7649///
7650/// ```text
7651/// +---+---------------------+
7652/// | # | Operands            |
7653/// +---+---------------------+
7654/// | 1 | KReg, Xmm, Mem, Imm |
7655/// | 2 | KReg, Xmm, Xmm, Imm |
7656/// | 3 | KReg, Ymm, Mem, Imm |
7657/// | 4 | KReg, Ymm, Ymm, Imm |
7658/// | 5 | KReg, Zmm, Mem, Imm |
7659/// | 6 | KReg, Zmm, Zmm, Imm |
7660/// +---+---------------------+
7661/// ```
7662pub trait VpcmpuwEmitter<A, B, C, D> {
7663    fn vpcmpuw(&mut self, op0: A, op1: B, op2: C, op3: D);
7664}
7665
7666impl<'a> VpcmpuwEmitter<KReg, Xmm, Xmm, Imm> for Assembler<'a> {
7667    fn vpcmpuw(&mut self, op0: KReg, op1: Xmm, op2: Xmm, op3: Imm) {
7668        self.emit(
7669            VPCMPUW128KRRI,
7670            op0.as_operand(),
7671            op1.as_operand(),
7672            op2.as_operand(),
7673            op3.as_operand(),
7674        );
7675    }
7676}
7677
7678impl<'a> VpcmpuwEmitter<KReg, Xmm, Mem, Imm> for Assembler<'a> {
7679    fn vpcmpuw(&mut self, op0: KReg, op1: Xmm, op2: Mem, op3: Imm) {
7680        self.emit(
7681            VPCMPUW128KRMI,
7682            op0.as_operand(),
7683            op1.as_operand(),
7684            op2.as_operand(),
7685            op3.as_operand(),
7686        );
7687    }
7688}
7689
7690impl<'a> VpcmpuwEmitter<KReg, Ymm, Ymm, Imm> for Assembler<'a> {
7691    fn vpcmpuw(&mut self, op0: KReg, op1: Ymm, op2: Ymm, op3: Imm) {
7692        self.emit(
7693            VPCMPUW256KRRI,
7694            op0.as_operand(),
7695            op1.as_operand(),
7696            op2.as_operand(),
7697            op3.as_operand(),
7698        );
7699    }
7700}
7701
7702impl<'a> VpcmpuwEmitter<KReg, Ymm, Mem, Imm> for Assembler<'a> {
7703    fn vpcmpuw(&mut self, op0: KReg, op1: Ymm, op2: Mem, op3: Imm) {
7704        self.emit(
7705            VPCMPUW256KRMI,
7706            op0.as_operand(),
7707            op1.as_operand(),
7708            op2.as_operand(),
7709            op3.as_operand(),
7710        );
7711    }
7712}
7713
7714impl<'a> VpcmpuwEmitter<KReg, Zmm, Zmm, Imm> for Assembler<'a> {
7715    fn vpcmpuw(&mut self, op0: KReg, op1: Zmm, op2: Zmm, op3: Imm) {
7716        self.emit(
7717            VPCMPUW512KRRI,
7718            op0.as_operand(),
7719            op1.as_operand(),
7720            op2.as_operand(),
7721            op3.as_operand(),
7722        );
7723    }
7724}
7725
7726impl<'a> VpcmpuwEmitter<KReg, Zmm, Mem, Imm> for Assembler<'a> {
7727    fn vpcmpuw(&mut self, op0: KReg, op1: Zmm, op2: Mem, op3: Imm) {
7728        self.emit(
7729            VPCMPUW512KRMI,
7730            op0.as_operand(),
7731            op1.as_operand(),
7732            op2.as_operand(),
7733            op3.as_operand(),
7734        );
7735    }
7736}
7737
7738/// `VPCMPUW_MASK`.
7739///
7740/// Supported operand variants:
7741///
7742/// ```text
7743/// +---+---------------------+
7744/// | # | Operands            |
7745/// +---+---------------------+
7746/// | 1 | KReg, Xmm, Mem, Imm |
7747/// | 2 | KReg, Xmm, Xmm, Imm |
7748/// | 3 | KReg, Ymm, Mem, Imm |
7749/// | 4 | KReg, Ymm, Ymm, Imm |
7750/// | 5 | KReg, Zmm, Mem, Imm |
7751/// | 6 | KReg, Zmm, Zmm, Imm |
7752/// +---+---------------------+
7753/// ```
7754pub trait VpcmpuwMaskEmitter<A, B, C, D> {
7755    fn vpcmpuw_mask(&mut self, op0: A, op1: B, op2: C, op3: D);
7756}
7757
7758impl<'a> VpcmpuwMaskEmitter<KReg, Xmm, Xmm, Imm> for Assembler<'a> {
7759    fn vpcmpuw_mask(&mut self, op0: KReg, op1: Xmm, op2: Xmm, op3: Imm) {
7760        self.emit(
7761            VPCMPUW128KRRI_MASK,
7762            op0.as_operand(),
7763            op1.as_operand(),
7764            op2.as_operand(),
7765            op3.as_operand(),
7766        );
7767    }
7768}
7769
7770impl<'a> VpcmpuwMaskEmitter<KReg, Xmm, Mem, Imm> for Assembler<'a> {
7771    fn vpcmpuw_mask(&mut self, op0: KReg, op1: Xmm, op2: Mem, op3: Imm) {
7772        self.emit(
7773            VPCMPUW128KRMI_MASK,
7774            op0.as_operand(),
7775            op1.as_operand(),
7776            op2.as_operand(),
7777            op3.as_operand(),
7778        );
7779    }
7780}
7781
7782impl<'a> VpcmpuwMaskEmitter<KReg, Ymm, Ymm, Imm> for Assembler<'a> {
7783    fn vpcmpuw_mask(&mut self, op0: KReg, op1: Ymm, op2: Ymm, op3: Imm) {
7784        self.emit(
7785            VPCMPUW256KRRI_MASK,
7786            op0.as_operand(),
7787            op1.as_operand(),
7788            op2.as_operand(),
7789            op3.as_operand(),
7790        );
7791    }
7792}
7793
7794impl<'a> VpcmpuwMaskEmitter<KReg, Ymm, Mem, Imm> for Assembler<'a> {
7795    fn vpcmpuw_mask(&mut self, op0: KReg, op1: Ymm, op2: Mem, op3: Imm) {
7796        self.emit(
7797            VPCMPUW256KRMI_MASK,
7798            op0.as_operand(),
7799            op1.as_operand(),
7800            op2.as_operand(),
7801            op3.as_operand(),
7802        );
7803    }
7804}
7805
7806impl<'a> VpcmpuwMaskEmitter<KReg, Zmm, Zmm, Imm> for Assembler<'a> {
7807    fn vpcmpuw_mask(&mut self, op0: KReg, op1: Zmm, op2: Zmm, op3: Imm) {
7808        self.emit(
7809            VPCMPUW512KRRI_MASK,
7810            op0.as_operand(),
7811            op1.as_operand(),
7812            op2.as_operand(),
7813            op3.as_operand(),
7814        );
7815    }
7816}
7817
7818impl<'a> VpcmpuwMaskEmitter<KReg, Zmm, Mem, Imm> for Assembler<'a> {
7819    fn vpcmpuw_mask(&mut self, op0: KReg, op1: Zmm, op2: Mem, op3: Imm) {
7820        self.emit(
7821            VPCMPUW512KRMI_MASK,
7822            op0.as_operand(),
7823            op1.as_operand(),
7824            op2.as_operand(),
7825            op3.as_operand(),
7826        );
7827    }
7828}
7829
7830/// `VPCMPW`.
7831///
7832/// Supported operand variants:
7833///
7834/// ```text
7835/// +---+---------------------+
7836/// | # | Operands            |
7837/// +---+---------------------+
7838/// | 1 | KReg, Xmm, Mem, Imm |
7839/// | 2 | KReg, Xmm, Xmm, Imm |
7840/// | 3 | KReg, Ymm, Mem, Imm |
7841/// | 4 | KReg, Ymm, Ymm, Imm |
7842/// | 5 | KReg, Zmm, Mem, Imm |
7843/// | 6 | KReg, Zmm, Zmm, Imm |
7844/// +---+---------------------+
7845/// ```
7846pub trait VpcmpwEmitter<A, B, C, D> {
7847    fn vpcmpw(&mut self, op0: A, op1: B, op2: C, op3: D);
7848}
7849
7850impl<'a> VpcmpwEmitter<KReg, Xmm, Xmm, Imm> for Assembler<'a> {
7851    fn vpcmpw(&mut self, op0: KReg, op1: Xmm, op2: Xmm, op3: Imm) {
7852        self.emit(
7853            VPCMPW128KRRI,
7854            op0.as_operand(),
7855            op1.as_operand(),
7856            op2.as_operand(),
7857            op3.as_operand(),
7858        );
7859    }
7860}
7861
7862impl<'a> VpcmpwEmitter<KReg, Xmm, Mem, Imm> for Assembler<'a> {
7863    fn vpcmpw(&mut self, op0: KReg, op1: Xmm, op2: Mem, op3: Imm) {
7864        self.emit(
7865            VPCMPW128KRMI,
7866            op0.as_operand(),
7867            op1.as_operand(),
7868            op2.as_operand(),
7869            op3.as_operand(),
7870        );
7871    }
7872}
7873
7874impl<'a> VpcmpwEmitter<KReg, Ymm, Ymm, Imm> for Assembler<'a> {
7875    fn vpcmpw(&mut self, op0: KReg, op1: Ymm, op2: Ymm, op3: Imm) {
7876        self.emit(
7877            VPCMPW256KRRI,
7878            op0.as_operand(),
7879            op1.as_operand(),
7880            op2.as_operand(),
7881            op3.as_operand(),
7882        );
7883    }
7884}
7885
7886impl<'a> VpcmpwEmitter<KReg, Ymm, Mem, Imm> for Assembler<'a> {
7887    fn vpcmpw(&mut self, op0: KReg, op1: Ymm, op2: Mem, op3: Imm) {
7888        self.emit(
7889            VPCMPW256KRMI,
7890            op0.as_operand(),
7891            op1.as_operand(),
7892            op2.as_operand(),
7893            op3.as_operand(),
7894        );
7895    }
7896}
7897
7898impl<'a> VpcmpwEmitter<KReg, Zmm, Zmm, Imm> for Assembler<'a> {
7899    fn vpcmpw(&mut self, op0: KReg, op1: Zmm, op2: Zmm, op3: Imm) {
7900        self.emit(
7901            VPCMPW512KRRI,
7902            op0.as_operand(),
7903            op1.as_operand(),
7904            op2.as_operand(),
7905            op3.as_operand(),
7906        );
7907    }
7908}
7909
7910impl<'a> VpcmpwEmitter<KReg, Zmm, Mem, Imm> for Assembler<'a> {
7911    fn vpcmpw(&mut self, op0: KReg, op1: Zmm, op2: Mem, op3: Imm) {
7912        self.emit(
7913            VPCMPW512KRMI,
7914            op0.as_operand(),
7915            op1.as_operand(),
7916            op2.as_operand(),
7917            op3.as_operand(),
7918        );
7919    }
7920}
7921
7922/// `VPCMPW_MASK`.
7923///
7924/// Supported operand variants:
7925///
7926/// ```text
7927/// +---+---------------------+
7928/// | # | Operands            |
7929/// +---+---------------------+
7930/// | 1 | KReg, Xmm, Mem, Imm |
7931/// | 2 | KReg, Xmm, Xmm, Imm |
7932/// | 3 | KReg, Ymm, Mem, Imm |
7933/// | 4 | KReg, Ymm, Ymm, Imm |
7934/// | 5 | KReg, Zmm, Mem, Imm |
7935/// | 6 | KReg, Zmm, Zmm, Imm |
7936/// +---+---------------------+
7937/// ```
7938pub trait VpcmpwMaskEmitter<A, B, C, D> {
7939    fn vpcmpw_mask(&mut self, op0: A, op1: B, op2: C, op3: D);
7940}
7941
7942impl<'a> VpcmpwMaskEmitter<KReg, Xmm, Xmm, Imm> for Assembler<'a> {
7943    fn vpcmpw_mask(&mut self, op0: KReg, op1: Xmm, op2: Xmm, op3: Imm) {
7944        self.emit(
7945            VPCMPW128KRRI_MASK,
7946            op0.as_operand(),
7947            op1.as_operand(),
7948            op2.as_operand(),
7949            op3.as_operand(),
7950        );
7951    }
7952}
7953
7954impl<'a> VpcmpwMaskEmitter<KReg, Xmm, Mem, Imm> for Assembler<'a> {
7955    fn vpcmpw_mask(&mut self, op0: KReg, op1: Xmm, op2: Mem, op3: Imm) {
7956        self.emit(
7957            VPCMPW128KRMI_MASK,
7958            op0.as_operand(),
7959            op1.as_operand(),
7960            op2.as_operand(),
7961            op3.as_operand(),
7962        );
7963    }
7964}
7965
7966impl<'a> VpcmpwMaskEmitter<KReg, Ymm, Ymm, Imm> for Assembler<'a> {
7967    fn vpcmpw_mask(&mut self, op0: KReg, op1: Ymm, op2: Ymm, op3: Imm) {
7968        self.emit(
7969            VPCMPW256KRRI_MASK,
7970            op0.as_operand(),
7971            op1.as_operand(),
7972            op2.as_operand(),
7973            op3.as_operand(),
7974        );
7975    }
7976}
7977
7978impl<'a> VpcmpwMaskEmitter<KReg, Ymm, Mem, Imm> for Assembler<'a> {
7979    fn vpcmpw_mask(&mut self, op0: KReg, op1: Ymm, op2: Mem, op3: Imm) {
7980        self.emit(
7981            VPCMPW256KRMI_MASK,
7982            op0.as_operand(),
7983            op1.as_operand(),
7984            op2.as_operand(),
7985            op3.as_operand(),
7986        );
7987    }
7988}
7989
7990impl<'a> VpcmpwMaskEmitter<KReg, Zmm, Zmm, Imm> for Assembler<'a> {
7991    fn vpcmpw_mask(&mut self, op0: KReg, op1: Zmm, op2: Zmm, op3: Imm) {
7992        self.emit(
7993            VPCMPW512KRRI_MASK,
7994            op0.as_operand(),
7995            op1.as_operand(),
7996            op2.as_operand(),
7997            op3.as_operand(),
7998        );
7999    }
8000}
8001
8002impl<'a> VpcmpwMaskEmitter<KReg, Zmm, Mem, Imm> for Assembler<'a> {
8003    fn vpcmpw_mask(&mut self, op0: KReg, op1: Zmm, op2: Mem, op3: Imm) {
8004        self.emit(
8005            VPCMPW512KRMI_MASK,
8006            op0.as_operand(),
8007            op1.as_operand(),
8008            op2.as_operand(),
8009            op3.as_operand(),
8010        );
8011    }
8012}
8013
8014/// `VPERMI2W`.
8015///
8016/// Supported operand variants:
8017///
8018/// ```text
8019/// +---+---------------+
8020/// | # | Operands      |
8021/// +---+---------------+
8022/// | 1 | Xmm, Xmm, Mem |
8023/// | 2 | Xmm, Xmm, Xmm |
8024/// | 3 | Ymm, Ymm, Mem |
8025/// | 4 | Ymm, Ymm, Ymm |
8026/// | 5 | Zmm, Zmm, Mem |
8027/// | 6 | Zmm, Zmm, Zmm |
8028/// +---+---------------+
8029/// ```
8030pub trait Vpermi2wEmitter<A, B, C> {
8031    fn vpermi2w(&mut self, op0: A, op1: B, op2: C);
8032}
8033
8034impl<'a> Vpermi2wEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
8035    fn vpermi2w(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
8036        self.emit(
8037            VPERMI2W128RRR,
8038            op0.as_operand(),
8039            op1.as_operand(),
8040            op2.as_operand(),
8041            &NOREG,
8042        );
8043    }
8044}
8045
8046impl<'a> Vpermi2wEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
8047    fn vpermi2w(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
8048        self.emit(
8049            VPERMI2W128RRM,
8050            op0.as_operand(),
8051            op1.as_operand(),
8052            op2.as_operand(),
8053            &NOREG,
8054        );
8055    }
8056}
8057
8058impl<'a> Vpermi2wEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
8059    fn vpermi2w(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
8060        self.emit(
8061            VPERMI2W256RRR,
8062            op0.as_operand(),
8063            op1.as_operand(),
8064            op2.as_operand(),
8065            &NOREG,
8066        );
8067    }
8068}
8069
8070impl<'a> Vpermi2wEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
8071    fn vpermi2w(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
8072        self.emit(
8073            VPERMI2W256RRM,
8074            op0.as_operand(),
8075            op1.as_operand(),
8076            op2.as_operand(),
8077            &NOREG,
8078        );
8079    }
8080}
8081
8082impl<'a> Vpermi2wEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
8083    fn vpermi2w(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
8084        self.emit(
8085            VPERMI2W512RRR,
8086            op0.as_operand(),
8087            op1.as_operand(),
8088            op2.as_operand(),
8089            &NOREG,
8090        );
8091    }
8092}
8093
8094impl<'a> Vpermi2wEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
8095    fn vpermi2w(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
8096        self.emit(
8097            VPERMI2W512RRM,
8098            op0.as_operand(),
8099            op1.as_operand(),
8100            op2.as_operand(),
8101            &NOREG,
8102        );
8103    }
8104}
8105
8106/// `VPERMI2W_MASK`.
8107///
8108/// Supported operand variants:
8109///
8110/// ```text
8111/// +---+---------------+
8112/// | # | Operands      |
8113/// +---+---------------+
8114/// | 1 | Xmm, Xmm, Mem |
8115/// | 2 | Xmm, Xmm, Xmm |
8116/// | 3 | Ymm, Ymm, Mem |
8117/// | 4 | Ymm, Ymm, Ymm |
8118/// | 5 | Zmm, Zmm, Mem |
8119/// | 6 | Zmm, Zmm, Zmm |
8120/// +---+---------------+
8121/// ```
8122pub trait Vpermi2wMaskEmitter<A, B, C> {
8123    fn vpermi2w_mask(&mut self, op0: A, op1: B, op2: C);
8124}
8125
8126impl<'a> Vpermi2wMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
8127    fn vpermi2w_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
8128        self.emit(
8129            VPERMI2W128RRR_MASK,
8130            op0.as_operand(),
8131            op1.as_operand(),
8132            op2.as_operand(),
8133            &NOREG,
8134        );
8135    }
8136}
8137
8138impl<'a> Vpermi2wMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
8139    fn vpermi2w_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
8140        self.emit(
8141            VPERMI2W128RRM_MASK,
8142            op0.as_operand(),
8143            op1.as_operand(),
8144            op2.as_operand(),
8145            &NOREG,
8146        );
8147    }
8148}
8149
8150impl<'a> Vpermi2wMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
8151    fn vpermi2w_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
8152        self.emit(
8153            VPERMI2W256RRR_MASK,
8154            op0.as_operand(),
8155            op1.as_operand(),
8156            op2.as_operand(),
8157            &NOREG,
8158        );
8159    }
8160}
8161
8162impl<'a> Vpermi2wMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
8163    fn vpermi2w_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
8164        self.emit(
8165            VPERMI2W256RRM_MASK,
8166            op0.as_operand(),
8167            op1.as_operand(),
8168            op2.as_operand(),
8169            &NOREG,
8170        );
8171    }
8172}
8173
8174impl<'a> Vpermi2wMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
8175    fn vpermi2w_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
8176        self.emit(
8177            VPERMI2W512RRR_MASK,
8178            op0.as_operand(),
8179            op1.as_operand(),
8180            op2.as_operand(),
8181            &NOREG,
8182        );
8183    }
8184}
8185
8186impl<'a> Vpermi2wMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
8187    fn vpermi2w_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
8188        self.emit(
8189            VPERMI2W512RRM_MASK,
8190            op0.as_operand(),
8191            op1.as_operand(),
8192            op2.as_operand(),
8193            &NOREG,
8194        );
8195    }
8196}
8197
8198/// `VPERMI2W_MASKZ`.
8199///
8200/// Supported operand variants:
8201///
8202/// ```text
8203/// +---+---------------+
8204/// | # | Operands      |
8205/// +---+---------------+
8206/// | 1 | Xmm, Xmm, Mem |
8207/// | 2 | Xmm, Xmm, Xmm |
8208/// | 3 | Ymm, Ymm, Mem |
8209/// | 4 | Ymm, Ymm, Ymm |
8210/// | 5 | Zmm, Zmm, Mem |
8211/// | 6 | Zmm, Zmm, Zmm |
8212/// +---+---------------+
8213/// ```
8214pub trait Vpermi2wMaskzEmitter<A, B, C> {
8215    fn vpermi2w_maskz(&mut self, op0: A, op1: B, op2: C);
8216}
8217
8218impl<'a> Vpermi2wMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
8219    fn vpermi2w_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
8220        self.emit(
8221            VPERMI2W128RRR_MASKZ,
8222            op0.as_operand(),
8223            op1.as_operand(),
8224            op2.as_operand(),
8225            &NOREG,
8226        );
8227    }
8228}
8229
8230impl<'a> Vpermi2wMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
8231    fn vpermi2w_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
8232        self.emit(
8233            VPERMI2W128RRM_MASKZ,
8234            op0.as_operand(),
8235            op1.as_operand(),
8236            op2.as_operand(),
8237            &NOREG,
8238        );
8239    }
8240}
8241
8242impl<'a> Vpermi2wMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
8243    fn vpermi2w_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
8244        self.emit(
8245            VPERMI2W256RRR_MASKZ,
8246            op0.as_operand(),
8247            op1.as_operand(),
8248            op2.as_operand(),
8249            &NOREG,
8250        );
8251    }
8252}
8253
8254impl<'a> Vpermi2wMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
8255    fn vpermi2w_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
8256        self.emit(
8257            VPERMI2W256RRM_MASKZ,
8258            op0.as_operand(),
8259            op1.as_operand(),
8260            op2.as_operand(),
8261            &NOREG,
8262        );
8263    }
8264}
8265
8266impl<'a> Vpermi2wMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
8267    fn vpermi2w_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
8268        self.emit(
8269            VPERMI2W512RRR_MASKZ,
8270            op0.as_operand(),
8271            op1.as_operand(),
8272            op2.as_operand(),
8273            &NOREG,
8274        );
8275    }
8276}
8277
8278impl<'a> Vpermi2wMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
8279    fn vpermi2w_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
8280        self.emit(
8281            VPERMI2W512RRM_MASKZ,
8282            op0.as_operand(),
8283            op1.as_operand(),
8284            op2.as_operand(),
8285            &NOREG,
8286        );
8287    }
8288}
8289
8290/// `VPERMT2W`.
8291///
8292/// Supported operand variants:
8293///
8294/// ```text
8295/// +---+---------------+
8296/// | # | Operands      |
8297/// +---+---------------+
8298/// | 1 | Xmm, Xmm, Mem |
8299/// | 2 | Xmm, Xmm, Xmm |
8300/// | 3 | Ymm, Ymm, Mem |
8301/// | 4 | Ymm, Ymm, Ymm |
8302/// | 5 | Zmm, Zmm, Mem |
8303/// | 6 | Zmm, Zmm, Zmm |
8304/// +---+---------------+
8305/// ```
8306pub trait Vpermt2wEmitter<A, B, C> {
8307    fn vpermt2w(&mut self, op0: A, op1: B, op2: C);
8308}
8309
8310impl<'a> Vpermt2wEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
8311    fn vpermt2w(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
8312        self.emit(
8313            VPERMT2W128RRR,
8314            op0.as_operand(),
8315            op1.as_operand(),
8316            op2.as_operand(),
8317            &NOREG,
8318        );
8319    }
8320}
8321
8322impl<'a> Vpermt2wEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
8323    fn vpermt2w(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
8324        self.emit(
8325            VPERMT2W128RRM,
8326            op0.as_operand(),
8327            op1.as_operand(),
8328            op2.as_operand(),
8329            &NOREG,
8330        );
8331    }
8332}
8333
8334impl<'a> Vpermt2wEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
8335    fn vpermt2w(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
8336        self.emit(
8337            VPERMT2W256RRR,
8338            op0.as_operand(),
8339            op1.as_operand(),
8340            op2.as_operand(),
8341            &NOREG,
8342        );
8343    }
8344}
8345
8346impl<'a> Vpermt2wEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
8347    fn vpermt2w(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
8348        self.emit(
8349            VPERMT2W256RRM,
8350            op0.as_operand(),
8351            op1.as_operand(),
8352            op2.as_operand(),
8353            &NOREG,
8354        );
8355    }
8356}
8357
8358impl<'a> Vpermt2wEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
8359    fn vpermt2w(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
8360        self.emit(
8361            VPERMT2W512RRR,
8362            op0.as_operand(),
8363            op1.as_operand(),
8364            op2.as_operand(),
8365            &NOREG,
8366        );
8367    }
8368}
8369
8370impl<'a> Vpermt2wEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
8371    fn vpermt2w(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
8372        self.emit(
8373            VPERMT2W512RRM,
8374            op0.as_operand(),
8375            op1.as_operand(),
8376            op2.as_operand(),
8377            &NOREG,
8378        );
8379    }
8380}
8381
8382/// `VPERMT2W_MASK`.
8383///
8384/// Supported operand variants:
8385///
8386/// ```text
8387/// +---+---------------+
8388/// | # | Operands      |
8389/// +---+---------------+
8390/// | 1 | Xmm, Xmm, Mem |
8391/// | 2 | Xmm, Xmm, Xmm |
8392/// | 3 | Ymm, Ymm, Mem |
8393/// | 4 | Ymm, Ymm, Ymm |
8394/// | 5 | Zmm, Zmm, Mem |
8395/// | 6 | Zmm, Zmm, Zmm |
8396/// +---+---------------+
8397/// ```
8398pub trait Vpermt2wMaskEmitter<A, B, C> {
8399    fn vpermt2w_mask(&mut self, op0: A, op1: B, op2: C);
8400}
8401
8402impl<'a> Vpermt2wMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
8403    fn vpermt2w_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
8404        self.emit(
8405            VPERMT2W128RRR_MASK,
8406            op0.as_operand(),
8407            op1.as_operand(),
8408            op2.as_operand(),
8409            &NOREG,
8410        );
8411    }
8412}
8413
8414impl<'a> Vpermt2wMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
8415    fn vpermt2w_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
8416        self.emit(
8417            VPERMT2W128RRM_MASK,
8418            op0.as_operand(),
8419            op1.as_operand(),
8420            op2.as_operand(),
8421            &NOREG,
8422        );
8423    }
8424}
8425
8426impl<'a> Vpermt2wMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
8427    fn vpermt2w_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
8428        self.emit(
8429            VPERMT2W256RRR_MASK,
8430            op0.as_operand(),
8431            op1.as_operand(),
8432            op2.as_operand(),
8433            &NOREG,
8434        );
8435    }
8436}
8437
8438impl<'a> Vpermt2wMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
8439    fn vpermt2w_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
8440        self.emit(
8441            VPERMT2W256RRM_MASK,
8442            op0.as_operand(),
8443            op1.as_operand(),
8444            op2.as_operand(),
8445            &NOREG,
8446        );
8447    }
8448}
8449
8450impl<'a> Vpermt2wMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
8451    fn vpermt2w_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
8452        self.emit(
8453            VPERMT2W512RRR_MASK,
8454            op0.as_operand(),
8455            op1.as_operand(),
8456            op2.as_operand(),
8457            &NOREG,
8458        );
8459    }
8460}
8461
8462impl<'a> Vpermt2wMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
8463    fn vpermt2w_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
8464        self.emit(
8465            VPERMT2W512RRM_MASK,
8466            op0.as_operand(),
8467            op1.as_operand(),
8468            op2.as_operand(),
8469            &NOREG,
8470        );
8471    }
8472}
8473
8474/// `VPERMT2W_MASKZ`.
8475///
8476/// Supported operand variants:
8477///
8478/// ```text
8479/// +---+---------------+
8480/// | # | Operands      |
8481/// +---+---------------+
8482/// | 1 | Xmm, Xmm, Mem |
8483/// | 2 | Xmm, Xmm, Xmm |
8484/// | 3 | Ymm, Ymm, Mem |
8485/// | 4 | Ymm, Ymm, Ymm |
8486/// | 5 | Zmm, Zmm, Mem |
8487/// | 6 | Zmm, Zmm, Zmm |
8488/// +---+---------------+
8489/// ```
8490pub trait Vpermt2wMaskzEmitter<A, B, C> {
8491    fn vpermt2w_maskz(&mut self, op0: A, op1: B, op2: C);
8492}
8493
8494impl<'a> Vpermt2wMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
8495    fn vpermt2w_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
8496        self.emit(
8497            VPERMT2W128RRR_MASKZ,
8498            op0.as_operand(),
8499            op1.as_operand(),
8500            op2.as_operand(),
8501            &NOREG,
8502        );
8503    }
8504}
8505
8506impl<'a> Vpermt2wMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
8507    fn vpermt2w_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
8508        self.emit(
8509            VPERMT2W128RRM_MASKZ,
8510            op0.as_operand(),
8511            op1.as_operand(),
8512            op2.as_operand(),
8513            &NOREG,
8514        );
8515    }
8516}
8517
8518impl<'a> Vpermt2wMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
8519    fn vpermt2w_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
8520        self.emit(
8521            VPERMT2W256RRR_MASKZ,
8522            op0.as_operand(),
8523            op1.as_operand(),
8524            op2.as_operand(),
8525            &NOREG,
8526        );
8527    }
8528}
8529
8530impl<'a> Vpermt2wMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
8531    fn vpermt2w_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
8532        self.emit(
8533            VPERMT2W256RRM_MASKZ,
8534            op0.as_operand(),
8535            op1.as_operand(),
8536            op2.as_operand(),
8537            &NOREG,
8538        );
8539    }
8540}
8541
8542impl<'a> Vpermt2wMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
8543    fn vpermt2w_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
8544        self.emit(
8545            VPERMT2W512RRR_MASKZ,
8546            op0.as_operand(),
8547            op1.as_operand(),
8548            op2.as_operand(),
8549            &NOREG,
8550        );
8551    }
8552}
8553
8554impl<'a> Vpermt2wMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
8555    fn vpermt2w_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
8556        self.emit(
8557            VPERMT2W512RRM_MASKZ,
8558            op0.as_operand(),
8559            op1.as_operand(),
8560            op2.as_operand(),
8561            &NOREG,
8562        );
8563    }
8564}
8565
8566/// `VPERMW`.
8567///
8568/// Supported operand variants:
8569///
8570/// ```text
8571/// +---+---------------+
8572/// | # | Operands      |
8573/// +---+---------------+
8574/// | 1 | Xmm, Xmm, Mem |
8575/// | 2 | Xmm, Xmm, Xmm |
8576/// | 3 | Ymm, Ymm, Mem |
8577/// | 4 | Ymm, Ymm, Ymm |
8578/// | 5 | Zmm, Zmm, Mem |
8579/// | 6 | Zmm, Zmm, Zmm |
8580/// +---+---------------+
8581/// ```
8582pub trait VpermwEmitter<A, B, C> {
8583    fn vpermw(&mut self, op0: A, op1: B, op2: C);
8584}
8585
8586impl<'a> VpermwEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
8587    fn vpermw(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
8588        self.emit(
8589            VPERMW128RRR,
8590            op0.as_operand(),
8591            op1.as_operand(),
8592            op2.as_operand(),
8593            &NOREG,
8594        );
8595    }
8596}
8597
8598impl<'a> VpermwEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
8599    fn vpermw(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
8600        self.emit(
8601            VPERMW128RRM,
8602            op0.as_operand(),
8603            op1.as_operand(),
8604            op2.as_operand(),
8605            &NOREG,
8606        );
8607    }
8608}
8609
8610impl<'a> VpermwEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
8611    fn vpermw(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
8612        self.emit(
8613            VPERMW256RRR,
8614            op0.as_operand(),
8615            op1.as_operand(),
8616            op2.as_operand(),
8617            &NOREG,
8618        );
8619    }
8620}
8621
8622impl<'a> VpermwEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
8623    fn vpermw(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
8624        self.emit(
8625            VPERMW256RRM,
8626            op0.as_operand(),
8627            op1.as_operand(),
8628            op2.as_operand(),
8629            &NOREG,
8630        );
8631    }
8632}
8633
8634impl<'a> VpermwEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
8635    fn vpermw(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
8636        self.emit(
8637            VPERMW512RRR,
8638            op0.as_operand(),
8639            op1.as_operand(),
8640            op2.as_operand(),
8641            &NOREG,
8642        );
8643    }
8644}
8645
8646impl<'a> VpermwEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
8647    fn vpermw(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
8648        self.emit(
8649            VPERMW512RRM,
8650            op0.as_operand(),
8651            op1.as_operand(),
8652            op2.as_operand(),
8653            &NOREG,
8654        );
8655    }
8656}
8657
8658/// `VPERMW_MASK`.
8659///
8660/// Supported operand variants:
8661///
8662/// ```text
8663/// +---+---------------+
8664/// | # | Operands      |
8665/// +---+---------------+
8666/// | 1 | Xmm, Xmm, Mem |
8667/// | 2 | Xmm, Xmm, Xmm |
8668/// | 3 | Ymm, Ymm, Mem |
8669/// | 4 | Ymm, Ymm, Ymm |
8670/// | 5 | Zmm, Zmm, Mem |
8671/// | 6 | Zmm, Zmm, Zmm |
8672/// +---+---------------+
8673/// ```
8674pub trait VpermwMaskEmitter<A, B, C> {
8675    fn vpermw_mask(&mut self, op0: A, op1: B, op2: C);
8676}
8677
8678impl<'a> VpermwMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
8679    fn vpermw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
8680        self.emit(
8681            VPERMW128RRR_MASK,
8682            op0.as_operand(),
8683            op1.as_operand(),
8684            op2.as_operand(),
8685            &NOREG,
8686        );
8687    }
8688}
8689
8690impl<'a> VpermwMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
8691    fn vpermw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
8692        self.emit(
8693            VPERMW128RRM_MASK,
8694            op0.as_operand(),
8695            op1.as_operand(),
8696            op2.as_operand(),
8697            &NOREG,
8698        );
8699    }
8700}
8701
8702impl<'a> VpermwMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
8703    fn vpermw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
8704        self.emit(
8705            VPERMW256RRR_MASK,
8706            op0.as_operand(),
8707            op1.as_operand(),
8708            op2.as_operand(),
8709            &NOREG,
8710        );
8711    }
8712}
8713
8714impl<'a> VpermwMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
8715    fn vpermw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
8716        self.emit(
8717            VPERMW256RRM_MASK,
8718            op0.as_operand(),
8719            op1.as_operand(),
8720            op2.as_operand(),
8721            &NOREG,
8722        );
8723    }
8724}
8725
8726impl<'a> VpermwMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
8727    fn vpermw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
8728        self.emit(
8729            VPERMW512RRR_MASK,
8730            op0.as_operand(),
8731            op1.as_operand(),
8732            op2.as_operand(),
8733            &NOREG,
8734        );
8735    }
8736}
8737
8738impl<'a> VpermwMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
8739    fn vpermw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
8740        self.emit(
8741            VPERMW512RRM_MASK,
8742            op0.as_operand(),
8743            op1.as_operand(),
8744            op2.as_operand(),
8745            &NOREG,
8746        );
8747    }
8748}
8749
8750/// `VPERMW_MASKZ`.
8751///
8752/// Supported operand variants:
8753///
8754/// ```text
8755/// +---+---------------+
8756/// | # | Operands      |
8757/// +---+---------------+
8758/// | 1 | Xmm, Xmm, Mem |
8759/// | 2 | Xmm, Xmm, Xmm |
8760/// | 3 | Ymm, Ymm, Mem |
8761/// | 4 | Ymm, Ymm, Ymm |
8762/// | 5 | Zmm, Zmm, Mem |
8763/// | 6 | Zmm, Zmm, Zmm |
8764/// +---+---------------+
8765/// ```
8766pub trait VpermwMaskzEmitter<A, B, C> {
8767    fn vpermw_maskz(&mut self, op0: A, op1: B, op2: C);
8768}
8769
8770impl<'a> VpermwMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
8771    fn vpermw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
8772        self.emit(
8773            VPERMW128RRR_MASKZ,
8774            op0.as_operand(),
8775            op1.as_operand(),
8776            op2.as_operand(),
8777            &NOREG,
8778        );
8779    }
8780}
8781
8782impl<'a> VpermwMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
8783    fn vpermw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
8784        self.emit(
8785            VPERMW128RRM_MASKZ,
8786            op0.as_operand(),
8787            op1.as_operand(),
8788            op2.as_operand(),
8789            &NOREG,
8790        );
8791    }
8792}
8793
8794impl<'a> VpermwMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
8795    fn vpermw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
8796        self.emit(
8797            VPERMW256RRR_MASKZ,
8798            op0.as_operand(),
8799            op1.as_operand(),
8800            op2.as_operand(),
8801            &NOREG,
8802        );
8803    }
8804}
8805
8806impl<'a> VpermwMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
8807    fn vpermw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
8808        self.emit(
8809            VPERMW256RRM_MASKZ,
8810            op0.as_operand(),
8811            op1.as_operand(),
8812            op2.as_operand(),
8813            &NOREG,
8814        );
8815    }
8816}
8817
8818impl<'a> VpermwMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
8819    fn vpermw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
8820        self.emit(
8821            VPERMW512RRR_MASKZ,
8822            op0.as_operand(),
8823            op1.as_operand(),
8824            op2.as_operand(),
8825            &NOREG,
8826        );
8827    }
8828}
8829
8830impl<'a> VpermwMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
8831    fn vpermw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
8832        self.emit(
8833            VPERMW512RRM_MASKZ,
8834            op0.as_operand(),
8835            op1.as_operand(),
8836            op2.as_operand(),
8837            &NOREG,
8838        );
8839    }
8840}
8841
8842/// `VPEXTRB`.
8843///
8844/// Supported operand variants:
8845///
8846/// ```text
8847/// +---+---------------+
8848/// | # | Operands      |
8849/// +---+---------------+
8850/// | 1 | Gpd, Xmm, Imm |
8851/// | 2 | Mem, Xmm, Imm |
8852/// +---+---------------+
8853/// ```
8854pub trait VpextrbEmitter<A, B, C> {
8855    fn vpextrb(&mut self, op0: A, op1: B, op2: C);
8856}
8857
8858impl<'a> VpextrbEmitter<Mem, Xmm, Imm> for Assembler<'a> {
8859    fn vpextrb(&mut self, op0: Mem, op1: Xmm, op2: Imm) {
8860        self.emit(
8861            VPEXTRBMRI,
8862            op0.as_operand(),
8863            op1.as_operand(),
8864            op2.as_operand(),
8865            &NOREG,
8866        );
8867    }
8868}
8869
8870impl<'a> VpextrbEmitter<Gpd, Xmm, Imm> for Assembler<'a> {
8871    fn vpextrb(&mut self, op0: Gpd, op1: Xmm, op2: Imm) {
8872        self.emit(
8873            VPEXTRBRRI,
8874            op0.as_operand(),
8875            op1.as_operand(),
8876            op2.as_operand(),
8877            &NOREG,
8878        );
8879    }
8880}
8881
8882/// `VPEXTRW`.
8883///
8884/// Supported operand variants:
8885///
8886/// ```text
8887/// +---+---------------+
8888/// | # | Operands      |
8889/// +---+---------------+
8890/// | 1 | Gpd, Xmm, Imm |
8891/// | 2 | Mem, Xmm, Imm |
8892/// +---+---------------+
8893/// ```
8894pub trait VpextrwEmitter<A, B, C> {
8895    fn vpextrw(&mut self, op0: A, op1: B, op2: C);
8896}
8897
8898impl<'a> VpextrwEmitter<Gpd, Xmm, Imm> for Assembler<'a> {
8899    fn vpextrw(&mut self, op0: Gpd, op1: Xmm, op2: Imm) {
8900        self.emit(
8901            VPEXTRWRRI,
8902            op0.as_operand(),
8903            op1.as_operand(),
8904            op2.as_operand(),
8905            &NOREG,
8906        );
8907    }
8908}
8909
8910impl<'a> VpextrwEmitter<Mem, Xmm, Imm> for Assembler<'a> {
8911    fn vpextrw(&mut self, op0: Mem, op1: Xmm, op2: Imm) {
8912        self.emit(
8913            VPEXTRWMRI,
8914            op0.as_operand(),
8915            op1.as_operand(),
8916            op2.as_operand(),
8917            &NOREG,
8918        );
8919    }
8920}
8921
8922/// `VPINSRB`.
8923///
8924/// Supported operand variants:
8925///
8926/// ```text
8927/// +---+--------------------+
8928/// | # | Operands           |
8929/// +---+--------------------+
8930/// | 1 | Xmm, Xmm, Gpd, Imm |
8931/// | 2 | Xmm, Xmm, Mem, Imm |
8932/// +---+--------------------+
8933/// ```
8934pub trait VpinsrbEmitter<A, B, C, D> {
8935    fn vpinsrb(&mut self, op0: A, op1: B, op2: C, op3: D);
8936}
8937
8938impl<'a> VpinsrbEmitter<Xmm, Xmm, Gpd, Imm> for Assembler<'a> {
8939    fn vpinsrb(&mut self, op0: Xmm, op1: Xmm, op2: Gpd, op3: Imm) {
8940        self.emit(
8941            VPINSRBRRRI,
8942            op0.as_operand(),
8943            op1.as_operand(),
8944            op2.as_operand(),
8945            op3.as_operand(),
8946        );
8947    }
8948}
8949
8950impl<'a> VpinsrbEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
8951    fn vpinsrb(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
8952        self.emit(
8953            VPINSRBRRMI,
8954            op0.as_operand(),
8955            op1.as_operand(),
8956            op2.as_operand(),
8957            op3.as_operand(),
8958        );
8959    }
8960}
8961
8962/// `VPINSRW`.
8963///
8964/// Supported operand variants:
8965///
8966/// ```text
8967/// +---+--------------------+
8968/// | # | Operands           |
8969/// +---+--------------------+
8970/// | 1 | Xmm, Xmm, Gpd, Imm |
8971/// | 2 | Xmm, Xmm, Mem, Imm |
8972/// +---+--------------------+
8973/// ```
8974pub trait VpinsrwEmitter<A, B, C, D> {
8975    fn vpinsrw(&mut self, op0: A, op1: B, op2: C, op3: D);
8976}
8977
8978impl<'a> VpinsrwEmitter<Xmm, Xmm, Gpd, Imm> for Assembler<'a> {
8979    fn vpinsrw(&mut self, op0: Xmm, op1: Xmm, op2: Gpd, op3: Imm) {
8980        self.emit(
8981            VPINSRWRRRI,
8982            op0.as_operand(),
8983            op1.as_operand(),
8984            op2.as_operand(),
8985            op3.as_operand(),
8986        );
8987    }
8988}
8989
8990impl<'a> VpinsrwEmitter<Xmm, Xmm, Mem, Imm> for Assembler<'a> {
8991    fn vpinsrw(&mut self, op0: Xmm, op1: Xmm, op2: Mem, op3: Imm) {
8992        self.emit(
8993            VPINSRWRRMI,
8994            op0.as_operand(),
8995            op1.as_operand(),
8996            op2.as_operand(),
8997            op3.as_operand(),
8998        );
8999    }
9000}
9001
9002/// `VPMADDUBSW`.
9003///
9004/// Supported operand variants:
9005///
9006/// ```text
9007/// +---+---------------+
9008/// | # | Operands      |
9009/// +---+---------------+
9010/// | 1 | Xmm, Xmm, Mem |
9011/// | 2 | Xmm, Xmm, Xmm |
9012/// | 3 | Ymm, Ymm, Mem |
9013/// | 4 | Ymm, Ymm, Ymm |
9014/// | 5 | Zmm, Zmm, Mem |
9015/// | 6 | Zmm, Zmm, Zmm |
9016/// +---+---------------+
9017/// ```
9018pub trait VpmaddubswEmitter<A, B, C> {
9019    fn vpmaddubsw(&mut self, op0: A, op1: B, op2: C);
9020}
9021
9022impl<'a> VpmaddubswEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
9023    fn vpmaddubsw(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
9024        self.emit(
9025            VPMADDUBSW128RRR,
9026            op0.as_operand(),
9027            op1.as_operand(),
9028            op2.as_operand(),
9029            &NOREG,
9030        );
9031    }
9032}
9033
9034impl<'a> VpmaddubswEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
9035    fn vpmaddubsw(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
9036        self.emit(
9037            VPMADDUBSW128RRM,
9038            op0.as_operand(),
9039            op1.as_operand(),
9040            op2.as_operand(),
9041            &NOREG,
9042        );
9043    }
9044}
9045
9046impl<'a> VpmaddubswEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
9047    fn vpmaddubsw(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
9048        self.emit(
9049            VPMADDUBSW256RRR,
9050            op0.as_operand(),
9051            op1.as_operand(),
9052            op2.as_operand(),
9053            &NOREG,
9054        );
9055    }
9056}
9057
9058impl<'a> VpmaddubswEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
9059    fn vpmaddubsw(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
9060        self.emit(
9061            VPMADDUBSW256RRM,
9062            op0.as_operand(),
9063            op1.as_operand(),
9064            op2.as_operand(),
9065            &NOREG,
9066        );
9067    }
9068}
9069
9070impl<'a> VpmaddubswEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
9071    fn vpmaddubsw(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
9072        self.emit(
9073            VPMADDUBSW512RRR,
9074            op0.as_operand(),
9075            op1.as_operand(),
9076            op2.as_operand(),
9077            &NOREG,
9078        );
9079    }
9080}
9081
9082impl<'a> VpmaddubswEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
9083    fn vpmaddubsw(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
9084        self.emit(
9085            VPMADDUBSW512RRM,
9086            op0.as_operand(),
9087            op1.as_operand(),
9088            op2.as_operand(),
9089            &NOREG,
9090        );
9091    }
9092}
9093
9094/// `VPMADDUBSW_MASK`.
9095///
9096/// Supported operand variants:
9097///
9098/// ```text
9099/// +---+---------------+
9100/// | # | Operands      |
9101/// +---+---------------+
9102/// | 1 | Xmm, Xmm, Mem |
9103/// | 2 | Xmm, Xmm, Xmm |
9104/// | 3 | Ymm, Ymm, Mem |
9105/// | 4 | Ymm, Ymm, Ymm |
9106/// | 5 | Zmm, Zmm, Mem |
9107/// | 6 | Zmm, Zmm, Zmm |
9108/// +---+---------------+
9109/// ```
9110pub trait VpmaddubswMaskEmitter<A, B, C> {
9111    fn vpmaddubsw_mask(&mut self, op0: A, op1: B, op2: C);
9112}
9113
9114impl<'a> VpmaddubswMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
9115    fn vpmaddubsw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
9116        self.emit(
9117            VPMADDUBSW128RRR_MASK,
9118            op0.as_operand(),
9119            op1.as_operand(),
9120            op2.as_operand(),
9121            &NOREG,
9122        );
9123    }
9124}
9125
9126impl<'a> VpmaddubswMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
9127    fn vpmaddubsw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
9128        self.emit(
9129            VPMADDUBSW128RRM_MASK,
9130            op0.as_operand(),
9131            op1.as_operand(),
9132            op2.as_operand(),
9133            &NOREG,
9134        );
9135    }
9136}
9137
9138impl<'a> VpmaddubswMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
9139    fn vpmaddubsw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
9140        self.emit(
9141            VPMADDUBSW256RRR_MASK,
9142            op0.as_operand(),
9143            op1.as_operand(),
9144            op2.as_operand(),
9145            &NOREG,
9146        );
9147    }
9148}
9149
9150impl<'a> VpmaddubswMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
9151    fn vpmaddubsw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
9152        self.emit(
9153            VPMADDUBSW256RRM_MASK,
9154            op0.as_operand(),
9155            op1.as_operand(),
9156            op2.as_operand(),
9157            &NOREG,
9158        );
9159    }
9160}
9161
9162impl<'a> VpmaddubswMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
9163    fn vpmaddubsw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
9164        self.emit(
9165            VPMADDUBSW512RRR_MASK,
9166            op0.as_operand(),
9167            op1.as_operand(),
9168            op2.as_operand(),
9169            &NOREG,
9170        );
9171    }
9172}
9173
9174impl<'a> VpmaddubswMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
9175    fn vpmaddubsw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
9176        self.emit(
9177            VPMADDUBSW512RRM_MASK,
9178            op0.as_operand(),
9179            op1.as_operand(),
9180            op2.as_operand(),
9181            &NOREG,
9182        );
9183    }
9184}
9185
9186/// `VPMADDUBSW_MASKZ`.
9187///
9188/// Supported operand variants:
9189///
9190/// ```text
9191/// +---+---------------+
9192/// | # | Operands      |
9193/// +---+---------------+
9194/// | 1 | Xmm, Xmm, Mem |
9195/// | 2 | Xmm, Xmm, Xmm |
9196/// | 3 | Ymm, Ymm, Mem |
9197/// | 4 | Ymm, Ymm, Ymm |
9198/// | 5 | Zmm, Zmm, Mem |
9199/// | 6 | Zmm, Zmm, Zmm |
9200/// +---+---------------+
9201/// ```
9202pub trait VpmaddubswMaskzEmitter<A, B, C> {
9203    fn vpmaddubsw_maskz(&mut self, op0: A, op1: B, op2: C);
9204}
9205
9206impl<'a> VpmaddubswMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
9207    fn vpmaddubsw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
9208        self.emit(
9209            VPMADDUBSW128RRR_MASKZ,
9210            op0.as_operand(),
9211            op1.as_operand(),
9212            op2.as_operand(),
9213            &NOREG,
9214        );
9215    }
9216}
9217
9218impl<'a> VpmaddubswMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
9219    fn vpmaddubsw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
9220        self.emit(
9221            VPMADDUBSW128RRM_MASKZ,
9222            op0.as_operand(),
9223            op1.as_operand(),
9224            op2.as_operand(),
9225            &NOREG,
9226        );
9227    }
9228}
9229
9230impl<'a> VpmaddubswMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
9231    fn vpmaddubsw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
9232        self.emit(
9233            VPMADDUBSW256RRR_MASKZ,
9234            op0.as_operand(),
9235            op1.as_operand(),
9236            op2.as_operand(),
9237            &NOREG,
9238        );
9239    }
9240}
9241
9242impl<'a> VpmaddubswMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
9243    fn vpmaddubsw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
9244        self.emit(
9245            VPMADDUBSW256RRM_MASKZ,
9246            op0.as_operand(),
9247            op1.as_operand(),
9248            op2.as_operand(),
9249            &NOREG,
9250        );
9251    }
9252}
9253
9254impl<'a> VpmaddubswMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
9255    fn vpmaddubsw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
9256        self.emit(
9257            VPMADDUBSW512RRR_MASKZ,
9258            op0.as_operand(),
9259            op1.as_operand(),
9260            op2.as_operand(),
9261            &NOREG,
9262        );
9263    }
9264}
9265
9266impl<'a> VpmaddubswMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
9267    fn vpmaddubsw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
9268        self.emit(
9269            VPMADDUBSW512RRM_MASKZ,
9270            op0.as_operand(),
9271            op1.as_operand(),
9272            op2.as_operand(),
9273            &NOREG,
9274        );
9275    }
9276}
9277
9278/// `VPMADDWD`.
9279///
9280/// Supported operand variants:
9281///
9282/// ```text
9283/// +---+---------------+
9284/// | # | Operands      |
9285/// +---+---------------+
9286/// | 1 | Xmm, Xmm, Mem |
9287/// | 2 | Xmm, Xmm, Xmm |
9288/// | 3 | Ymm, Ymm, Mem |
9289/// | 4 | Ymm, Ymm, Ymm |
9290/// | 5 | Zmm, Zmm, Mem |
9291/// | 6 | Zmm, Zmm, Zmm |
9292/// +---+---------------+
9293/// ```
9294pub trait VpmaddwdEmitter<A, B, C> {
9295    fn vpmaddwd(&mut self, op0: A, op1: B, op2: C);
9296}
9297
9298impl<'a> VpmaddwdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
9299    fn vpmaddwd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
9300        self.emit(
9301            VPMADDWD128RRR,
9302            op0.as_operand(),
9303            op1.as_operand(),
9304            op2.as_operand(),
9305            &NOREG,
9306        );
9307    }
9308}
9309
9310impl<'a> VpmaddwdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
9311    fn vpmaddwd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
9312        self.emit(
9313            VPMADDWD128RRM,
9314            op0.as_operand(),
9315            op1.as_operand(),
9316            op2.as_operand(),
9317            &NOREG,
9318        );
9319    }
9320}
9321
9322impl<'a> VpmaddwdEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
9323    fn vpmaddwd(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
9324        self.emit(
9325            VPMADDWD256RRR,
9326            op0.as_operand(),
9327            op1.as_operand(),
9328            op2.as_operand(),
9329            &NOREG,
9330        );
9331    }
9332}
9333
9334impl<'a> VpmaddwdEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
9335    fn vpmaddwd(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
9336        self.emit(
9337            VPMADDWD256RRM,
9338            op0.as_operand(),
9339            op1.as_operand(),
9340            op2.as_operand(),
9341            &NOREG,
9342        );
9343    }
9344}
9345
9346impl<'a> VpmaddwdEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
9347    fn vpmaddwd(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
9348        self.emit(
9349            VPMADDWD512RRR,
9350            op0.as_operand(),
9351            op1.as_operand(),
9352            op2.as_operand(),
9353            &NOREG,
9354        );
9355    }
9356}
9357
9358impl<'a> VpmaddwdEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
9359    fn vpmaddwd(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
9360        self.emit(
9361            VPMADDWD512RRM,
9362            op0.as_operand(),
9363            op1.as_operand(),
9364            op2.as_operand(),
9365            &NOREG,
9366        );
9367    }
9368}
9369
9370/// `VPMADDWD_MASK`.
9371///
9372/// Supported operand variants:
9373///
9374/// ```text
9375/// +---+---------------+
9376/// | # | Operands      |
9377/// +---+---------------+
9378/// | 1 | Xmm, Xmm, Mem |
9379/// | 2 | Xmm, Xmm, Xmm |
9380/// | 3 | Ymm, Ymm, Mem |
9381/// | 4 | Ymm, Ymm, Ymm |
9382/// | 5 | Zmm, Zmm, Mem |
9383/// | 6 | Zmm, Zmm, Zmm |
9384/// +---+---------------+
9385/// ```
9386pub trait VpmaddwdMaskEmitter<A, B, C> {
9387    fn vpmaddwd_mask(&mut self, op0: A, op1: B, op2: C);
9388}
9389
9390impl<'a> VpmaddwdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
9391    fn vpmaddwd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
9392        self.emit(
9393            VPMADDWD128RRR_MASK,
9394            op0.as_operand(),
9395            op1.as_operand(),
9396            op2.as_operand(),
9397            &NOREG,
9398        );
9399    }
9400}
9401
9402impl<'a> VpmaddwdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
9403    fn vpmaddwd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
9404        self.emit(
9405            VPMADDWD128RRM_MASK,
9406            op0.as_operand(),
9407            op1.as_operand(),
9408            op2.as_operand(),
9409            &NOREG,
9410        );
9411    }
9412}
9413
9414impl<'a> VpmaddwdMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
9415    fn vpmaddwd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
9416        self.emit(
9417            VPMADDWD256RRR_MASK,
9418            op0.as_operand(),
9419            op1.as_operand(),
9420            op2.as_operand(),
9421            &NOREG,
9422        );
9423    }
9424}
9425
9426impl<'a> VpmaddwdMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
9427    fn vpmaddwd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
9428        self.emit(
9429            VPMADDWD256RRM_MASK,
9430            op0.as_operand(),
9431            op1.as_operand(),
9432            op2.as_operand(),
9433            &NOREG,
9434        );
9435    }
9436}
9437
9438impl<'a> VpmaddwdMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
9439    fn vpmaddwd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
9440        self.emit(
9441            VPMADDWD512RRR_MASK,
9442            op0.as_operand(),
9443            op1.as_operand(),
9444            op2.as_operand(),
9445            &NOREG,
9446        );
9447    }
9448}
9449
9450impl<'a> VpmaddwdMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
9451    fn vpmaddwd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
9452        self.emit(
9453            VPMADDWD512RRM_MASK,
9454            op0.as_operand(),
9455            op1.as_operand(),
9456            op2.as_operand(),
9457            &NOREG,
9458        );
9459    }
9460}
9461
9462/// `VPMADDWD_MASKZ`.
9463///
9464/// Supported operand variants:
9465///
9466/// ```text
9467/// +---+---------------+
9468/// | # | Operands      |
9469/// +---+---------------+
9470/// | 1 | Xmm, Xmm, Mem |
9471/// | 2 | Xmm, Xmm, Xmm |
9472/// | 3 | Ymm, Ymm, Mem |
9473/// | 4 | Ymm, Ymm, Ymm |
9474/// | 5 | Zmm, Zmm, Mem |
9475/// | 6 | Zmm, Zmm, Zmm |
9476/// +---+---------------+
9477/// ```
9478pub trait VpmaddwdMaskzEmitter<A, B, C> {
9479    fn vpmaddwd_maskz(&mut self, op0: A, op1: B, op2: C);
9480}
9481
9482impl<'a> VpmaddwdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
9483    fn vpmaddwd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
9484        self.emit(
9485            VPMADDWD128RRR_MASKZ,
9486            op0.as_operand(),
9487            op1.as_operand(),
9488            op2.as_operand(),
9489            &NOREG,
9490        );
9491    }
9492}
9493
9494impl<'a> VpmaddwdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
9495    fn vpmaddwd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
9496        self.emit(
9497            VPMADDWD128RRM_MASKZ,
9498            op0.as_operand(),
9499            op1.as_operand(),
9500            op2.as_operand(),
9501            &NOREG,
9502        );
9503    }
9504}
9505
9506impl<'a> VpmaddwdMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
9507    fn vpmaddwd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
9508        self.emit(
9509            VPMADDWD256RRR_MASKZ,
9510            op0.as_operand(),
9511            op1.as_operand(),
9512            op2.as_operand(),
9513            &NOREG,
9514        );
9515    }
9516}
9517
9518impl<'a> VpmaddwdMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
9519    fn vpmaddwd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
9520        self.emit(
9521            VPMADDWD256RRM_MASKZ,
9522            op0.as_operand(),
9523            op1.as_operand(),
9524            op2.as_operand(),
9525            &NOREG,
9526        );
9527    }
9528}
9529
9530impl<'a> VpmaddwdMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
9531    fn vpmaddwd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
9532        self.emit(
9533            VPMADDWD512RRR_MASKZ,
9534            op0.as_operand(),
9535            op1.as_operand(),
9536            op2.as_operand(),
9537            &NOREG,
9538        );
9539    }
9540}
9541
9542impl<'a> VpmaddwdMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
9543    fn vpmaddwd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
9544        self.emit(
9545            VPMADDWD512RRM_MASKZ,
9546            op0.as_operand(),
9547            op1.as_operand(),
9548            op2.as_operand(),
9549            &NOREG,
9550        );
9551    }
9552}
9553
9554/// `VPMAXSB`.
9555///
9556/// Supported operand variants:
9557///
9558/// ```text
9559/// +---+---------------+
9560/// | # | Operands      |
9561/// +---+---------------+
9562/// | 1 | Xmm, Xmm, Mem |
9563/// | 2 | Xmm, Xmm, Xmm |
9564/// | 3 | Ymm, Ymm, Mem |
9565/// | 4 | Ymm, Ymm, Ymm |
9566/// | 5 | Zmm, Zmm, Mem |
9567/// | 6 | Zmm, Zmm, Zmm |
9568/// +---+---------------+
9569/// ```
9570pub trait VpmaxsbEmitter<A, B, C> {
9571    fn vpmaxsb(&mut self, op0: A, op1: B, op2: C);
9572}
9573
9574impl<'a> VpmaxsbEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
9575    fn vpmaxsb(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
9576        self.emit(
9577            VPMAXSB128RRR,
9578            op0.as_operand(),
9579            op1.as_operand(),
9580            op2.as_operand(),
9581            &NOREG,
9582        );
9583    }
9584}
9585
9586impl<'a> VpmaxsbEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
9587    fn vpmaxsb(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
9588        self.emit(
9589            VPMAXSB128RRM,
9590            op0.as_operand(),
9591            op1.as_operand(),
9592            op2.as_operand(),
9593            &NOREG,
9594        );
9595    }
9596}
9597
9598impl<'a> VpmaxsbEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
9599    fn vpmaxsb(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
9600        self.emit(
9601            VPMAXSB256RRR,
9602            op0.as_operand(),
9603            op1.as_operand(),
9604            op2.as_operand(),
9605            &NOREG,
9606        );
9607    }
9608}
9609
9610impl<'a> VpmaxsbEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
9611    fn vpmaxsb(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
9612        self.emit(
9613            VPMAXSB256RRM,
9614            op0.as_operand(),
9615            op1.as_operand(),
9616            op2.as_operand(),
9617            &NOREG,
9618        );
9619    }
9620}
9621
9622impl<'a> VpmaxsbEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
9623    fn vpmaxsb(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
9624        self.emit(
9625            VPMAXSB512RRR,
9626            op0.as_operand(),
9627            op1.as_operand(),
9628            op2.as_operand(),
9629            &NOREG,
9630        );
9631    }
9632}
9633
9634impl<'a> VpmaxsbEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
9635    fn vpmaxsb(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
9636        self.emit(
9637            VPMAXSB512RRM,
9638            op0.as_operand(),
9639            op1.as_operand(),
9640            op2.as_operand(),
9641            &NOREG,
9642        );
9643    }
9644}
9645
9646/// `VPMAXSB_MASK`.
9647///
9648/// Supported operand variants:
9649///
9650/// ```text
9651/// +---+---------------+
9652/// | # | Operands      |
9653/// +---+---------------+
9654/// | 1 | Xmm, Xmm, Mem |
9655/// | 2 | Xmm, Xmm, Xmm |
9656/// | 3 | Ymm, Ymm, Mem |
9657/// | 4 | Ymm, Ymm, Ymm |
9658/// | 5 | Zmm, Zmm, Mem |
9659/// | 6 | Zmm, Zmm, Zmm |
9660/// +---+---------------+
9661/// ```
9662pub trait VpmaxsbMaskEmitter<A, B, C> {
9663    fn vpmaxsb_mask(&mut self, op0: A, op1: B, op2: C);
9664}
9665
9666impl<'a> VpmaxsbMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
9667    fn vpmaxsb_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
9668        self.emit(
9669            VPMAXSB128RRR_MASK,
9670            op0.as_operand(),
9671            op1.as_operand(),
9672            op2.as_operand(),
9673            &NOREG,
9674        );
9675    }
9676}
9677
9678impl<'a> VpmaxsbMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
9679    fn vpmaxsb_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
9680        self.emit(
9681            VPMAXSB128RRM_MASK,
9682            op0.as_operand(),
9683            op1.as_operand(),
9684            op2.as_operand(),
9685            &NOREG,
9686        );
9687    }
9688}
9689
9690impl<'a> VpmaxsbMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
9691    fn vpmaxsb_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
9692        self.emit(
9693            VPMAXSB256RRR_MASK,
9694            op0.as_operand(),
9695            op1.as_operand(),
9696            op2.as_operand(),
9697            &NOREG,
9698        );
9699    }
9700}
9701
9702impl<'a> VpmaxsbMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
9703    fn vpmaxsb_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
9704        self.emit(
9705            VPMAXSB256RRM_MASK,
9706            op0.as_operand(),
9707            op1.as_operand(),
9708            op2.as_operand(),
9709            &NOREG,
9710        );
9711    }
9712}
9713
9714impl<'a> VpmaxsbMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
9715    fn vpmaxsb_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
9716        self.emit(
9717            VPMAXSB512RRR_MASK,
9718            op0.as_operand(),
9719            op1.as_operand(),
9720            op2.as_operand(),
9721            &NOREG,
9722        );
9723    }
9724}
9725
9726impl<'a> VpmaxsbMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
9727    fn vpmaxsb_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
9728        self.emit(
9729            VPMAXSB512RRM_MASK,
9730            op0.as_operand(),
9731            op1.as_operand(),
9732            op2.as_operand(),
9733            &NOREG,
9734        );
9735    }
9736}
9737
9738/// `VPMAXSB_MASKZ`.
9739///
9740/// Supported operand variants:
9741///
9742/// ```text
9743/// +---+---------------+
9744/// | # | Operands      |
9745/// +---+---------------+
9746/// | 1 | Xmm, Xmm, Mem |
9747/// | 2 | Xmm, Xmm, Xmm |
9748/// | 3 | Ymm, Ymm, Mem |
9749/// | 4 | Ymm, Ymm, Ymm |
9750/// | 5 | Zmm, Zmm, Mem |
9751/// | 6 | Zmm, Zmm, Zmm |
9752/// +---+---------------+
9753/// ```
9754pub trait VpmaxsbMaskzEmitter<A, B, C> {
9755    fn vpmaxsb_maskz(&mut self, op0: A, op1: B, op2: C);
9756}
9757
9758impl<'a> VpmaxsbMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
9759    fn vpmaxsb_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
9760        self.emit(
9761            VPMAXSB128RRR_MASKZ,
9762            op0.as_operand(),
9763            op1.as_operand(),
9764            op2.as_operand(),
9765            &NOREG,
9766        );
9767    }
9768}
9769
9770impl<'a> VpmaxsbMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
9771    fn vpmaxsb_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
9772        self.emit(
9773            VPMAXSB128RRM_MASKZ,
9774            op0.as_operand(),
9775            op1.as_operand(),
9776            op2.as_operand(),
9777            &NOREG,
9778        );
9779    }
9780}
9781
9782impl<'a> VpmaxsbMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
9783    fn vpmaxsb_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
9784        self.emit(
9785            VPMAXSB256RRR_MASKZ,
9786            op0.as_operand(),
9787            op1.as_operand(),
9788            op2.as_operand(),
9789            &NOREG,
9790        );
9791    }
9792}
9793
9794impl<'a> VpmaxsbMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
9795    fn vpmaxsb_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
9796        self.emit(
9797            VPMAXSB256RRM_MASKZ,
9798            op0.as_operand(),
9799            op1.as_operand(),
9800            op2.as_operand(),
9801            &NOREG,
9802        );
9803    }
9804}
9805
9806impl<'a> VpmaxsbMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
9807    fn vpmaxsb_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
9808        self.emit(
9809            VPMAXSB512RRR_MASKZ,
9810            op0.as_operand(),
9811            op1.as_operand(),
9812            op2.as_operand(),
9813            &NOREG,
9814        );
9815    }
9816}
9817
9818impl<'a> VpmaxsbMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
9819    fn vpmaxsb_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
9820        self.emit(
9821            VPMAXSB512RRM_MASKZ,
9822            op0.as_operand(),
9823            op1.as_operand(),
9824            op2.as_operand(),
9825            &NOREG,
9826        );
9827    }
9828}
9829
9830/// `VPMAXSW`.
9831///
9832/// Supported operand variants:
9833///
9834/// ```text
9835/// +---+---------------+
9836/// | # | Operands      |
9837/// +---+---------------+
9838/// | 1 | Xmm, Xmm, Mem |
9839/// | 2 | Xmm, Xmm, Xmm |
9840/// | 3 | Ymm, Ymm, Mem |
9841/// | 4 | Ymm, Ymm, Ymm |
9842/// | 5 | Zmm, Zmm, Mem |
9843/// | 6 | Zmm, Zmm, Zmm |
9844/// +---+---------------+
9845/// ```
9846pub trait VpmaxswEmitter<A, B, C> {
9847    fn vpmaxsw(&mut self, op0: A, op1: B, op2: C);
9848}
9849
9850impl<'a> VpmaxswEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
9851    fn vpmaxsw(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
9852        self.emit(
9853            VPMAXSW128RRR,
9854            op0.as_operand(),
9855            op1.as_operand(),
9856            op2.as_operand(),
9857            &NOREG,
9858        );
9859    }
9860}
9861
9862impl<'a> VpmaxswEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
9863    fn vpmaxsw(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
9864        self.emit(
9865            VPMAXSW128RRM,
9866            op0.as_operand(),
9867            op1.as_operand(),
9868            op2.as_operand(),
9869            &NOREG,
9870        );
9871    }
9872}
9873
9874impl<'a> VpmaxswEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
9875    fn vpmaxsw(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
9876        self.emit(
9877            VPMAXSW256RRR,
9878            op0.as_operand(),
9879            op1.as_operand(),
9880            op2.as_operand(),
9881            &NOREG,
9882        );
9883    }
9884}
9885
9886impl<'a> VpmaxswEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
9887    fn vpmaxsw(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
9888        self.emit(
9889            VPMAXSW256RRM,
9890            op0.as_operand(),
9891            op1.as_operand(),
9892            op2.as_operand(),
9893            &NOREG,
9894        );
9895    }
9896}
9897
9898impl<'a> VpmaxswEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
9899    fn vpmaxsw(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
9900        self.emit(
9901            VPMAXSW512RRR,
9902            op0.as_operand(),
9903            op1.as_operand(),
9904            op2.as_operand(),
9905            &NOREG,
9906        );
9907    }
9908}
9909
9910impl<'a> VpmaxswEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
9911    fn vpmaxsw(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
9912        self.emit(
9913            VPMAXSW512RRM,
9914            op0.as_operand(),
9915            op1.as_operand(),
9916            op2.as_operand(),
9917            &NOREG,
9918        );
9919    }
9920}
9921
9922/// `VPMAXSW_MASK`.
9923///
9924/// Supported operand variants:
9925///
9926/// ```text
9927/// +---+---------------+
9928/// | # | Operands      |
9929/// +---+---------------+
9930/// | 1 | Xmm, Xmm, Mem |
9931/// | 2 | Xmm, Xmm, Xmm |
9932/// | 3 | Ymm, Ymm, Mem |
9933/// | 4 | Ymm, Ymm, Ymm |
9934/// | 5 | Zmm, Zmm, Mem |
9935/// | 6 | Zmm, Zmm, Zmm |
9936/// +---+---------------+
9937/// ```
9938pub trait VpmaxswMaskEmitter<A, B, C> {
9939    fn vpmaxsw_mask(&mut self, op0: A, op1: B, op2: C);
9940}
9941
9942impl<'a> VpmaxswMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
9943    fn vpmaxsw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
9944        self.emit(
9945            VPMAXSW128RRR_MASK,
9946            op0.as_operand(),
9947            op1.as_operand(),
9948            op2.as_operand(),
9949            &NOREG,
9950        );
9951    }
9952}
9953
9954impl<'a> VpmaxswMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
9955    fn vpmaxsw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
9956        self.emit(
9957            VPMAXSW128RRM_MASK,
9958            op0.as_operand(),
9959            op1.as_operand(),
9960            op2.as_operand(),
9961            &NOREG,
9962        );
9963    }
9964}
9965
9966impl<'a> VpmaxswMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
9967    fn vpmaxsw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
9968        self.emit(
9969            VPMAXSW256RRR_MASK,
9970            op0.as_operand(),
9971            op1.as_operand(),
9972            op2.as_operand(),
9973            &NOREG,
9974        );
9975    }
9976}
9977
9978impl<'a> VpmaxswMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
9979    fn vpmaxsw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
9980        self.emit(
9981            VPMAXSW256RRM_MASK,
9982            op0.as_operand(),
9983            op1.as_operand(),
9984            op2.as_operand(),
9985            &NOREG,
9986        );
9987    }
9988}
9989
9990impl<'a> VpmaxswMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
9991    fn vpmaxsw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
9992        self.emit(
9993            VPMAXSW512RRR_MASK,
9994            op0.as_operand(),
9995            op1.as_operand(),
9996            op2.as_operand(),
9997            &NOREG,
9998        );
9999    }
10000}
10001
10002impl<'a> VpmaxswMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
10003    fn vpmaxsw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
10004        self.emit(
10005            VPMAXSW512RRM_MASK,
10006            op0.as_operand(),
10007            op1.as_operand(),
10008            op2.as_operand(),
10009            &NOREG,
10010        );
10011    }
10012}
10013
10014/// `VPMAXSW_MASKZ`.
10015///
10016/// Supported operand variants:
10017///
10018/// ```text
10019/// +---+---------------+
10020/// | # | Operands      |
10021/// +---+---------------+
10022/// | 1 | Xmm, Xmm, Mem |
10023/// | 2 | Xmm, Xmm, Xmm |
10024/// | 3 | Ymm, Ymm, Mem |
10025/// | 4 | Ymm, Ymm, Ymm |
10026/// | 5 | Zmm, Zmm, Mem |
10027/// | 6 | Zmm, Zmm, Zmm |
10028/// +---+---------------+
10029/// ```
10030pub trait VpmaxswMaskzEmitter<A, B, C> {
10031    fn vpmaxsw_maskz(&mut self, op0: A, op1: B, op2: C);
10032}
10033
10034impl<'a> VpmaxswMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
10035    fn vpmaxsw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
10036        self.emit(
10037            VPMAXSW128RRR_MASKZ,
10038            op0.as_operand(),
10039            op1.as_operand(),
10040            op2.as_operand(),
10041            &NOREG,
10042        );
10043    }
10044}
10045
10046impl<'a> VpmaxswMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
10047    fn vpmaxsw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
10048        self.emit(
10049            VPMAXSW128RRM_MASKZ,
10050            op0.as_operand(),
10051            op1.as_operand(),
10052            op2.as_operand(),
10053            &NOREG,
10054        );
10055    }
10056}
10057
10058impl<'a> VpmaxswMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
10059    fn vpmaxsw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
10060        self.emit(
10061            VPMAXSW256RRR_MASKZ,
10062            op0.as_operand(),
10063            op1.as_operand(),
10064            op2.as_operand(),
10065            &NOREG,
10066        );
10067    }
10068}
10069
10070impl<'a> VpmaxswMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
10071    fn vpmaxsw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
10072        self.emit(
10073            VPMAXSW256RRM_MASKZ,
10074            op0.as_operand(),
10075            op1.as_operand(),
10076            op2.as_operand(),
10077            &NOREG,
10078        );
10079    }
10080}
10081
10082impl<'a> VpmaxswMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
10083    fn vpmaxsw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
10084        self.emit(
10085            VPMAXSW512RRR_MASKZ,
10086            op0.as_operand(),
10087            op1.as_operand(),
10088            op2.as_operand(),
10089            &NOREG,
10090        );
10091    }
10092}
10093
10094impl<'a> VpmaxswMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
10095    fn vpmaxsw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
10096        self.emit(
10097            VPMAXSW512RRM_MASKZ,
10098            op0.as_operand(),
10099            op1.as_operand(),
10100            op2.as_operand(),
10101            &NOREG,
10102        );
10103    }
10104}
10105
10106/// `VPMAXUB`.
10107///
10108/// Supported operand variants:
10109///
10110/// ```text
10111/// +---+---------------+
10112/// | # | Operands      |
10113/// +---+---------------+
10114/// | 1 | Xmm, Xmm, Mem |
10115/// | 2 | Xmm, Xmm, Xmm |
10116/// | 3 | Ymm, Ymm, Mem |
10117/// | 4 | Ymm, Ymm, Ymm |
10118/// | 5 | Zmm, Zmm, Mem |
10119/// | 6 | Zmm, Zmm, Zmm |
10120/// +---+---------------+
10121/// ```
10122pub trait VpmaxubEmitter<A, B, C> {
10123    fn vpmaxub(&mut self, op0: A, op1: B, op2: C);
10124}
10125
10126impl<'a> VpmaxubEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
10127    fn vpmaxub(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
10128        self.emit(
10129            VPMAXUB128RRR,
10130            op0.as_operand(),
10131            op1.as_operand(),
10132            op2.as_operand(),
10133            &NOREG,
10134        );
10135    }
10136}
10137
10138impl<'a> VpmaxubEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
10139    fn vpmaxub(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
10140        self.emit(
10141            VPMAXUB128RRM,
10142            op0.as_operand(),
10143            op1.as_operand(),
10144            op2.as_operand(),
10145            &NOREG,
10146        );
10147    }
10148}
10149
10150impl<'a> VpmaxubEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
10151    fn vpmaxub(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
10152        self.emit(
10153            VPMAXUB256RRR,
10154            op0.as_operand(),
10155            op1.as_operand(),
10156            op2.as_operand(),
10157            &NOREG,
10158        );
10159    }
10160}
10161
10162impl<'a> VpmaxubEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
10163    fn vpmaxub(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
10164        self.emit(
10165            VPMAXUB256RRM,
10166            op0.as_operand(),
10167            op1.as_operand(),
10168            op2.as_operand(),
10169            &NOREG,
10170        );
10171    }
10172}
10173
10174impl<'a> VpmaxubEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
10175    fn vpmaxub(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
10176        self.emit(
10177            VPMAXUB512RRR,
10178            op0.as_operand(),
10179            op1.as_operand(),
10180            op2.as_operand(),
10181            &NOREG,
10182        );
10183    }
10184}
10185
10186impl<'a> VpmaxubEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
10187    fn vpmaxub(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
10188        self.emit(
10189            VPMAXUB512RRM,
10190            op0.as_operand(),
10191            op1.as_operand(),
10192            op2.as_operand(),
10193            &NOREG,
10194        );
10195    }
10196}
10197
10198/// `VPMAXUB_MASK`.
10199///
10200/// Supported operand variants:
10201///
10202/// ```text
10203/// +---+---------------+
10204/// | # | Operands      |
10205/// +---+---------------+
10206/// | 1 | Xmm, Xmm, Mem |
10207/// | 2 | Xmm, Xmm, Xmm |
10208/// | 3 | Ymm, Ymm, Mem |
10209/// | 4 | Ymm, Ymm, Ymm |
10210/// | 5 | Zmm, Zmm, Mem |
10211/// | 6 | Zmm, Zmm, Zmm |
10212/// +---+---------------+
10213/// ```
10214pub trait VpmaxubMaskEmitter<A, B, C> {
10215    fn vpmaxub_mask(&mut self, op0: A, op1: B, op2: C);
10216}
10217
10218impl<'a> VpmaxubMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
10219    fn vpmaxub_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
10220        self.emit(
10221            VPMAXUB128RRR_MASK,
10222            op0.as_operand(),
10223            op1.as_operand(),
10224            op2.as_operand(),
10225            &NOREG,
10226        );
10227    }
10228}
10229
10230impl<'a> VpmaxubMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
10231    fn vpmaxub_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
10232        self.emit(
10233            VPMAXUB128RRM_MASK,
10234            op0.as_operand(),
10235            op1.as_operand(),
10236            op2.as_operand(),
10237            &NOREG,
10238        );
10239    }
10240}
10241
10242impl<'a> VpmaxubMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
10243    fn vpmaxub_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
10244        self.emit(
10245            VPMAXUB256RRR_MASK,
10246            op0.as_operand(),
10247            op1.as_operand(),
10248            op2.as_operand(),
10249            &NOREG,
10250        );
10251    }
10252}
10253
10254impl<'a> VpmaxubMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
10255    fn vpmaxub_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
10256        self.emit(
10257            VPMAXUB256RRM_MASK,
10258            op0.as_operand(),
10259            op1.as_operand(),
10260            op2.as_operand(),
10261            &NOREG,
10262        );
10263    }
10264}
10265
10266impl<'a> VpmaxubMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
10267    fn vpmaxub_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
10268        self.emit(
10269            VPMAXUB512RRR_MASK,
10270            op0.as_operand(),
10271            op1.as_operand(),
10272            op2.as_operand(),
10273            &NOREG,
10274        );
10275    }
10276}
10277
10278impl<'a> VpmaxubMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
10279    fn vpmaxub_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
10280        self.emit(
10281            VPMAXUB512RRM_MASK,
10282            op0.as_operand(),
10283            op1.as_operand(),
10284            op2.as_operand(),
10285            &NOREG,
10286        );
10287    }
10288}
10289
10290/// `VPMAXUB_MASKZ`.
10291///
10292/// Supported operand variants:
10293///
10294/// ```text
10295/// +---+---------------+
10296/// | # | Operands      |
10297/// +---+---------------+
10298/// | 1 | Xmm, Xmm, Mem |
10299/// | 2 | Xmm, Xmm, Xmm |
10300/// | 3 | Ymm, Ymm, Mem |
10301/// | 4 | Ymm, Ymm, Ymm |
10302/// | 5 | Zmm, Zmm, Mem |
10303/// | 6 | Zmm, Zmm, Zmm |
10304/// +---+---------------+
10305/// ```
10306pub trait VpmaxubMaskzEmitter<A, B, C> {
10307    fn vpmaxub_maskz(&mut self, op0: A, op1: B, op2: C);
10308}
10309
10310impl<'a> VpmaxubMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
10311    fn vpmaxub_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
10312        self.emit(
10313            VPMAXUB128RRR_MASKZ,
10314            op0.as_operand(),
10315            op1.as_operand(),
10316            op2.as_operand(),
10317            &NOREG,
10318        );
10319    }
10320}
10321
10322impl<'a> VpmaxubMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
10323    fn vpmaxub_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
10324        self.emit(
10325            VPMAXUB128RRM_MASKZ,
10326            op0.as_operand(),
10327            op1.as_operand(),
10328            op2.as_operand(),
10329            &NOREG,
10330        );
10331    }
10332}
10333
10334impl<'a> VpmaxubMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
10335    fn vpmaxub_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
10336        self.emit(
10337            VPMAXUB256RRR_MASKZ,
10338            op0.as_operand(),
10339            op1.as_operand(),
10340            op2.as_operand(),
10341            &NOREG,
10342        );
10343    }
10344}
10345
10346impl<'a> VpmaxubMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
10347    fn vpmaxub_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
10348        self.emit(
10349            VPMAXUB256RRM_MASKZ,
10350            op0.as_operand(),
10351            op1.as_operand(),
10352            op2.as_operand(),
10353            &NOREG,
10354        );
10355    }
10356}
10357
10358impl<'a> VpmaxubMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
10359    fn vpmaxub_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
10360        self.emit(
10361            VPMAXUB512RRR_MASKZ,
10362            op0.as_operand(),
10363            op1.as_operand(),
10364            op2.as_operand(),
10365            &NOREG,
10366        );
10367    }
10368}
10369
10370impl<'a> VpmaxubMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
10371    fn vpmaxub_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
10372        self.emit(
10373            VPMAXUB512RRM_MASKZ,
10374            op0.as_operand(),
10375            op1.as_operand(),
10376            op2.as_operand(),
10377            &NOREG,
10378        );
10379    }
10380}
10381
10382/// `VPMAXUW`.
10383///
10384/// Supported operand variants:
10385///
10386/// ```text
10387/// +---+---------------+
10388/// | # | Operands      |
10389/// +---+---------------+
10390/// | 1 | Xmm, Xmm, Mem |
10391/// | 2 | Xmm, Xmm, Xmm |
10392/// | 3 | Ymm, Ymm, Mem |
10393/// | 4 | Ymm, Ymm, Ymm |
10394/// | 5 | Zmm, Zmm, Mem |
10395/// | 6 | Zmm, Zmm, Zmm |
10396/// +---+---------------+
10397/// ```
10398pub trait VpmaxuwEmitter<A, B, C> {
10399    fn vpmaxuw(&mut self, op0: A, op1: B, op2: C);
10400}
10401
10402impl<'a> VpmaxuwEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
10403    fn vpmaxuw(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
10404        self.emit(
10405            VPMAXUW128RRR,
10406            op0.as_operand(),
10407            op1.as_operand(),
10408            op2.as_operand(),
10409            &NOREG,
10410        );
10411    }
10412}
10413
10414impl<'a> VpmaxuwEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
10415    fn vpmaxuw(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
10416        self.emit(
10417            VPMAXUW128RRM,
10418            op0.as_operand(),
10419            op1.as_operand(),
10420            op2.as_operand(),
10421            &NOREG,
10422        );
10423    }
10424}
10425
10426impl<'a> VpmaxuwEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
10427    fn vpmaxuw(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
10428        self.emit(
10429            VPMAXUW256RRR,
10430            op0.as_operand(),
10431            op1.as_operand(),
10432            op2.as_operand(),
10433            &NOREG,
10434        );
10435    }
10436}
10437
10438impl<'a> VpmaxuwEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
10439    fn vpmaxuw(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
10440        self.emit(
10441            VPMAXUW256RRM,
10442            op0.as_operand(),
10443            op1.as_operand(),
10444            op2.as_operand(),
10445            &NOREG,
10446        );
10447    }
10448}
10449
10450impl<'a> VpmaxuwEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
10451    fn vpmaxuw(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
10452        self.emit(
10453            VPMAXUW512RRR,
10454            op0.as_operand(),
10455            op1.as_operand(),
10456            op2.as_operand(),
10457            &NOREG,
10458        );
10459    }
10460}
10461
10462impl<'a> VpmaxuwEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
10463    fn vpmaxuw(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
10464        self.emit(
10465            VPMAXUW512RRM,
10466            op0.as_operand(),
10467            op1.as_operand(),
10468            op2.as_operand(),
10469            &NOREG,
10470        );
10471    }
10472}
10473
10474/// `VPMAXUW_MASK`.
10475///
10476/// Supported operand variants:
10477///
10478/// ```text
10479/// +---+---------------+
10480/// | # | Operands      |
10481/// +---+---------------+
10482/// | 1 | Xmm, Xmm, Mem |
10483/// | 2 | Xmm, Xmm, Xmm |
10484/// | 3 | Ymm, Ymm, Mem |
10485/// | 4 | Ymm, Ymm, Ymm |
10486/// | 5 | Zmm, Zmm, Mem |
10487/// | 6 | Zmm, Zmm, Zmm |
10488/// +---+---------------+
10489/// ```
10490pub trait VpmaxuwMaskEmitter<A, B, C> {
10491    fn vpmaxuw_mask(&mut self, op0: A, op1: B, op2: C);
10492}
10493
10494impl<'a> VpmaxuwMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
10495    fn vpmaxuw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
10496        self.emit(
10497            VPMAXUW128RRR_MASK,
10498            op0.as_operand(),
10499            op1.as_operand(),
10500            op2.as_operand(),
10501            &NOREG,
10502        );
10503    }
10504}
10505
10506impl<'a> VpmaxuwMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
10507    fn vpmaxuw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
10508        self.emit(
10509            VPMAXUW128RRM_MASK,
10510            op0.as_operand(),
10511            op1.as_operand(),
10512            op2.as_operand(),
10513            &NOREG,
10514        );
10515    }
10516}
10517
10518impl<'a> VpmaxuwMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
10519    fn vpmaxuw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
10520        self.emit(
10521            VPMAXUW256RRR_MASK,
10522            op0.as_operand(),
10523            op1.as_operand(),
10524            op2.as_operand(),
10525            &NOREG,
10526        );
10527    }
10528}
10529
10530impl<'a> VpmaxuwMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
10531    fn vpmaxuw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
10532        self.emit(
10533            VPMAXUW256RRM_MASK,
10534            op0.as_operand(),
10535            op1.as_operand(),
10536            op2.as_operand(),
10537            &NOREG,
10538        );
10539    }
10540}
10541
10542impl<'a> VpmaxuwMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
10543    fn vpmaxuw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
10544        self.emit(
10545            VPMAXUW512RRR_MASK,
10546            op0.as_operand(),
10547            op1.as_operand(),
10548            op2.as_operand(),
10549            &NOREG,
10550        );
10551    }
10552}
10553
10554impl<'a> VpmaxuwMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
10555    fn vpmaxuw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
10556        self.emit(
10557            VPMAXUW512RRM_MASK,
10558            op0.as_operand(),
10559            op1.as_operand(),
10560            op2.as_operand(),
10561            &NOREG,
10562        );
10563    }
10564}
10565
10566/// `VPMAXUW_MASKZ`.
10567///
10568/// Supported operand variants:
10569///
10570/// ```text
10571/// +---+---------------+
10572/// | # | Operands      |
10573/// +---+---------------+
10574/// | 1 | Xmm, Xmm, Mem |
10575/// | 2 | Xmm, Xmm, Xmm |
10576/// | 3 | Ymm, Ymm, Mem |
10577/// | 4 | Ymm, Ymm, Ymm |
10578/// | 5 | Zmm, Zmm, Mem |
10579/// | 6 | Zmm, Zmm, Zmm |
10580/// +---+---------------+
10581/// ```
10582pub trait VpmaxuwMaskzEmitter<A, B, C> {
10583    fn vpmaxuw_maskz(&mut self, op0: A, op1: B, op2: C);
10584}
10585
10586impl<'a> VpmaxuwMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
10587    fn vpmaxuw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
10588        self.emit(
10589            VPMAXUW128RRR_MASKZ,
10590            op0.as_operand(),
10591            op1.as_operand(),
10592            op2.as_operand(),
10593            &NOREG,
10594        );
10595    }
10596}
10597
10598impl<'a> VpmaxuwMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
10599    fn vpmaxuw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
10600        self.emit(
10601            VPMAXUW128RRM_MASKZ,
10602            op0.as_operand(),
10603            op1.as_operand(),
10604            op2.as_operand(),
10605            &NOREG,
10606        );
10607    }
10608}
10609
10610impl<'a> VpmaxuwMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
10611    fn vpmaxuw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
10612        self.emit(
10613            VPMAXUW256RRR_MASKZ,
10614            op0.as_operand(),
10615            op1.as_operand(),
10616            op2.as_operand(),
10617            &NOREG,
10618        );
10619    }
10620}
10621
10622impl<'a> VpmaxuwMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
10623    fn vpmaxuw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
10624        self.emit(
10625            VPMAXUW256RRM_MASKZ,
10626            op0.as_operand(),
10627            op1.as_operand(),
10628            op2.as_operand(),
10629            &NOREG,
10630        );
10631    }
10632}
10633
10634impl<'a> VpmaxuwMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
10635    fn vpmaxuw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
10636        self.emit(
10637            VPMAXUW512RRR_MASKZ,
10638            op0.as_operand(),
10639            op1.as_operand(),
10640            op2.as_operand(),
10641            &NOREG,
10642        );
10643    }
10644}
10645
10646impl<'a> VpmaxuwMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
10647    fn vpmaxuw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
10648        self.emit(
10649            VPMAXUW512RRM_MASKZ,
10650            op0.as_operand(),
10651            op1.as_operand(),
10652            op2.as_operand(),
10653            &NOREG,
10654        );
10655    }
10656}
10657
10658/// `VPMINSB`.
10659///
10660/// Supported operand variants:
10661///
10662/// ```text
10663/// +---+---------------+
10664/// | # | Operands      |
10665/// +---+---------------+
10666/// | 1 | Xmm, Xmm, Mem |
10667/// | 2 | Xmm, Xmm, Xmm |
10668/// | 3 | Ymm, Ymm, Mem |
10669/// | 4 | Ymm, Ymm, Ymm |
10670/// | 5 | Zmm, Zmm, Mem |
10671/// | 6 | Zmm, Zmm, Zmm |
10672/// +---+---------------+
10673/// ```
10674pub trait VpminsbEmitter<A, B, C> {
10675    fn vpminsb(&mut self, op0: A, op1: B, op2: C);
10676}
10677
10678impl<'a> VpminsbEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
10679    fn vpminsb(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
10680        self.emit(
10681            VPMINSB128RRR,
10682            op0.as_operand(),
10683            op1.as_operand(),
10684            op2.as_operand(),
10685            &NOREG,
10686        );
10687    }
10688}
10689
10690impl<'a> VpminsbEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
10691    fn vpminsb(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
10692        self.emit(
10693            VPMINSB128RRM,
10694            op0.as_operand(),
10695            op1.as_operand(),
10696            op2.as_operand(),
10697            &NOREG,
10698        );
10699    }
10700}
10701
10702impl<'a> VpminsbEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
10703    fn vpminsb(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
10704        self.emit(
10705            VPMINSB256RRR,
10706            op0.as_operand(),
10707            op1.as_operand(),
10708            op2.as_operand(),
10709            &NOREG,
10710        );
10711    }
10712}
10713
10714impl<'a> VpminsbEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
10715    fn vpminsb(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
10716        self.emit(
10717            VPMINSB256RRM,
10718            op0.as_operand(),
10719            op1.as_operand(),
10720            op2.as_operand(),
10721            &NOREG,
10722        );
10723    }
10724}
10725
10726impl<'a> VpminsbEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
10727    fn vpminsb(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
10728        self.emit(
10729            VPMINSB512RRR,
10730            op0.as_operand(),
10731            op1.as_operand(),
10732            op2.as_operand(),
10733            &NOREG,
10734        );
10735    }
10736}
10737
10738impl<'a> VpminsbEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
10739    fn vpminsb(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
10740        self.emit(
10741            VPMINSB512RRM,
10742            op0.as_operand(),
10743            op1.as_operand(),
10744            op2.as_operand(),
10745            &NOREG,
10746        );
10747    }
10748}
10749
10750/// `VPMINSB_MASK`.
10751///
10752/// Supported operand variants:
10753///
10754/// ```text
10755/// +---+---------------+
10756/// | # | Operands      |
10757/// +---+---------------+
10758/// | 1 | Xmm, Xmm, Mem |
10759/// | 2 | Xmm, Xmm, Xmm |
10760/// | 3 | Ymm, Ymm, Mem |
10761/// | 4 | Ymm, Ymm, Ymm |
10762/// | 5 | Zmm, Zmm, Mem |
10763/// | 6 | Zmm, Zmm, Zmm |
10764/// +---+---------------+
10765/// ```
10766pub trait VpminsbMaskEmitter<A, B, C> {
10767    fn vpminsb_mask(&mut self, op0: A, op1: B, op2: C);
10768}
10769
10770impl<'a> VpminsbMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
10771    fn vpminsb_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
10772        self.emit(
10773            VPMINSB128RRR_MASK,
10774            op0.as_operand(),
10775            op1.as_operand(),
10776            op2.as_operand(),
10777            &NOREG,
10778        );
10779    }
10780}
10781
10782impl<'a> VpminsbMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
10783    fn vpminsb_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
10784        self.emit(
10785            VPMINSB128RRM_MASK,
10786            op0.as_operand(),
10787            op1.as_operand(),
10788            op2.as_operand(),
10789            &NOREG,
10790        );
10791    }
10792}
10793
10794impl<'a> VpminsbMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
10795    fn vpminsb_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
10796        self.emit(
10797            VPMINSB256RRR_MASK,
10798            op0.as_operand(),
10799            op1.as_operand(),
10800            op2.as_operand(),
10801            &NOREG,
10802        );
10803    }
10804}
10805
10806impl<'a> VpminsbMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
10807    fn vpminsb_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
10808        self.emit(
10809            VPMINSB256RRM_MASK,
10810            op0.as_operand(),
10811            op1.as_operand(),
10812            op2.as_operand(),
10813            &NOREG,
10814        );
10815    }
10816}
10817
10818impl<'a> VpminsbMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
10819    fn vpminsb_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
10820        self.emit(
10821            VPMINSB512RRR_MASK,
10822            op0.as_operand(),
10823            op1.as_operand(),
10824            op2.as_operand(),
10825            &NOREG,
10826        );
10827    }
10828}
10829
10830impl<'a> VpminsbMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
10831    fn vpminsb_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
10832        self.emit(
10833            VPMINSB512RRM_MASK,
10834            op0.as_operand(),
10835            op1.as_operand(),
10836            op2.as_operand(),
10837            &NOREG,
10838        );
10839    }
10840}
10841
10842/// `VPMINSB_MASKZ`.
10843///
10844/// Supported operand variants:
10845///
10846/// ```text
10847/// +---+---------------+
10848/// | # | Operands      |
10849/// +---+---------------+
10850/// | 1 | Xmm, Xmm, Mem |
10851/// | 2 | Xmm, Xmm, Xmm |
10852/// | 3 | Ymm, Ymm, Mem |
10853/// | 4 | Ymm, Ymm, Ymm |
10854/// | 5 | Zmm, Zmm, Mem |
10855/// | 6 | Zmm, Zmm, Zmm |
10856/// +---+---------------+
10857/// ```
10858pub trait VpminsbMaskzEmitter<A, B, C> {
10859    fn vpminsb_maskz(&mut self, op0: A, op1: B, op2: C);
10860}
10861
10862impl<'a> VpminsbMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
10863    fn vpminsb_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
10864        self.emit(
10865            VPMINSB128RRR_MASKZ,
10866            op0.as_operand(),
10867            op1.as_operand(),
10868            op2.as_operand(),
10869            &NOREG,
10870        );
10871    }
10872}
10873
10874impl<'a> VpminsbMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
10875    fn vpminsb_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
10876        self.emit(
10877            VPMINSB128RRM_MASKZ,
10878            op0.as_operand(),
10879            op1.as_operand(),
10880            op2.as_operand(),
10881            &NOREG,
10882        );
10883    }
10884}
10885
10886impl<'a> VpminsbMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
10887    fn vpminsb_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
10888        self.emit(
10889            VPMINSB256RRR_MASKZ,
10890            op0.as_operand(),
10891            op1.as_operand(),
10892            op2.as_operand(),
10893            &NOREG,
10894        );
10895    }
10896}
10897
10898impl<'a> VpminsbMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
10899    fn vpminsb_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
10900        self.emit(
10901            VPMINSB256RRM_MASKZ,
10902            op0.as_operand(),
10903            op1.as_operand(),
10904            op2.as_operand(),
10905            &NOREG,
10906        );
10907    }
10908}
10909
10910impl<'a> VpminsbMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
10911    fn vpminsb_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
10912        self.emit(
10913            VPMINSB512RRR_MASKZ,
10914            op0.as_operand(),
10915            op1.as_operand(),
10916            op2.as_operand(),
10917            &NOREG,
10918        );
10919    }
10920}
10921
10922impl<'a> VpminsbMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
10923    fn vpminsb_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
10924        self.emit(
10925            VPMINSB512RRM_MASKZ,
10926            op0.as_operand(),
10927            op1.as_operand(),
10928            op2.as_operand(),
10929            &NOREG,
10930        );
10931    }
10932}
10933
10934/// `VPMINSW`.
10935///
10936/// Supported operand variants:
10937///
10938/// ```text
10939/// +---+---------------+
10940/// | # | Operands      |
10941/// +---+---------------+
10942/// | 1 | Xmm, Xmm, Mem |
10943/// | 2 | Xmm, Xmm, Xmm |
10944/// | 3 | Ymm, Ymm, Mem |
10945/// | 4 | Ymm, Ymm, Ymm |
10946/// | 5 | Zmm, Zmm, Mem |
10947/// | 6 | Zmm, Zmm, Zmm |
10948/// +---+---------------+
10949/// ```
10950pub trait VpminswEmitter<A, B, C> {
10951    fn vpminsw(&mut self, op0: A, op1: B, op2: C);
10952}
10953
10954impl<'a> VpminswEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
10955    fn vpminsw(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
10956        self.emit(
10957            VPMINSW128RRR,
10958            op0.as_operand(),
10959            op1.as_operand(),
10960            op2.as_operand(),
10961            &NOREG,
10962        );
10963    }
10964}
10965
10966impl<'a> VpminswEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
10967    fn vpminsw(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
10968        self.emit(
10969            VPMINSW128RRM,
10970            op0.as_operand(),
10971            op1.as_operand(),
10972            op2.as_operand(),
10973            &NOREG,
10974        );
10975    }
10976}
10977
10978impl<'a> VpminswEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
10979    fn vpminsw(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
10980        self.emit(
10981            VPMINSW256RRR,
10982            op0.as_operand(),
10983            op1.as_operand(),
10984            op2.as_operand(),
10985            &NOREG,
10986        );
10987    }
10988}
10989
10990impl<'a> VpminswEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
10991    fn vpminsw(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
10992        self.emit(
10993            VPMINSW256RRM,
10994            op0.as_operand(),
10995            op1.as_operand(),
10996            op2.as_operand(),
10997            &NOREG,
10998        );
10999    }
11000}
11001
11002impl<'a> VpminswEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
11003    fn vpminsw(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
11004        self.emit(
11005            VPMINSW512RRR,
11006            op0.as_operand(),
11007            op1.as_operand(),
11008            op2.as_operand(),
11009            &NOREG,
11010        );
11011    }
11012}
11013
11014impl<'a> VpminswEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
11015    fn vpminsw(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
11016        self.emit(
11017            VPMINSW512RRM,
11018            op0.as_operand(),
11019            op1.as_operand(),
11020            op2.as_operand(),
11021            &NOREG,
11022        );
11023    }
11024}
11025
11026/// `VPMINSW_MASK`.
11027///
11028/// Supported operand variants:
11029///
11030/// ```text
11031/// +---+---------------+
11032/// | # | Operands      |
11033/// +---+---------------+
11034/// | 1 | Xmm, Xmm, Mem |
11035/// | 2 | Xmm, Xmm, Xmm |
11036/// | 3 | Ymm, Ymm, Mem |
11037/// | 4 | Ymm, Ymm, Ymm |
11038/// | 5 | Zmm, Zmm, Mem |
11039/// | 6 | Zmm, Zmm, Zmm |
11040/// +---+---------------+
11041/// ```
11042pub trait VpminswMaskEmitter<A, B, C> {
11043    fn vpminsw_mask(&mut self, op0: A, op1: B, op2: C);
11044}
11045
11046impl<'a> VpminswMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
11047    fn vpminsw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
11048        self.emit(
11049            VPMINSW128RRR_MASK,
11050            op0.as_operand(),
11051            op1.as_operand(),
11052            op2.as_operand(),
11053            &NOREG,
11054        );
11055    }
11056}
11057
11058impl<'a> VpminswMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
11059    fn vpminsw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
11060        self.emit(
11061            VPMINSW128RRM_MASK,
11062            op0.as_operand(),
11063            op1.as_operand(),
11064            op2.as_operand(),
11065            &NOREG,
11066        );
11067    }
11068}
11069
11070impl<'a> VpminswMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
11071    fn vpminsw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
11072        self.emit(
11073            VPMINSW256RRR_MASK,
11074            op0.as_operand(),
11075            op1.as_operand(),
11076            op2.as_operand(),
11077            &NOREG,
11078        );
11079    }
11080}
11081
11082impl<'a> VpminswMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
11083    fn vpminsw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
11084        self.emit(
11085            VPMINSW256RRM_MASK,
11086            op0.as_operand(),
11087            op1.as_operand(),
11088            op2.as_operand(),
11089            &NOREG,
11090        );
11091    }
11092}
11093
11094impl<'a> VpminswMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
11095    fn vpminsw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
11096        self.emit(
11097            VPMINSW512RRR_MASK,
11098            op0.as_operand(),
11099            op1.as_operand(),
11100            op2.as_operand(),
11101            &NOREG,
11102        );
11103    }
11104}
11105
11106impl<'a> VpminswMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
11107    fn vpminsw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
11108        self.emit(
11109            VPMINSW512RRM_MASK,
11110            op0.as_operand(),
11111            op1.as_operand(),
11112            op2.as_operand(),
11113            &NOREG,
11114        );
11115    }
11116}
11117
11118/// `VPMINSW_MASKZ`.
11119///
11120/// Supported operand variants:
11121///
11122/// ```text
11123/// +---+---------------+
11124/// | # | Operands      |
11125/// +---+---------------+
11126/// | 1 | Xmm, Xmm, Mem |
11127/// | 2 | Xmm, Xmm, Xmm |
11128/// | 3 | Ymm, Ymm, Mem |
11129/// | 4 | Ymm, Ymm, Ymm |
11130/// | 5 | Zmm, Zmm, Mem |
11131/// | 6 | Zmm, Zmm, Zmm |
11132/// +---+---------------+
11133/// ```
11134pub trait VpminswMaskzEmitter<A, B, C> {
11135    fn vpminsw_maskz(&mut self, op0: A, op1: B, op2: C);
11136}
11137
11138impl<'a> VpminswMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
11139    fn vpminsw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
11140        self.emit(
11141            VPMINSW128RRR_MASKZ,
11142            op0.as_operand(),
11143            op1.as_operand(),
11144            op2.as_operand(),
11145            &NOREG,
11146        );
11147    }
11148}
11149
11150impl<'a> VpminswMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
11151    fn vpminsw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
11152        self.emit(
11153            VPMINSW128RRM_MASKZ,
11154            op0.as_operand(),
11155            op1.as_operand(),
11156            op2.as_operand(),
11157            &NOREG,
11158        );
11159    }
11160}
11161
11162impl<'a> VpminswMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
11163    fn vpminsw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
11164        self.emit(
11165            VPMINSW256RRR_MASKZ,
11166            op0.as_operand(),
11167            op1.as_operand(),
11168            op2.as_operand(),
11169            &NOREG,
11170        );
11171    }
11172}
11173
11174impl<'a> VpminswMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
11175    fn vpminsw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
11176        self.emit(
11177            VPMINSW256RRM_MASKZ,
11178            op0.as_operand(),
11179            op1.as_operand(),
11180            op2.as_operand(),
11181            &NOREG,
11182        );
11183    }
11184}
11185
11186impl<'a> VpminswMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
11187    fn vpminsw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
11188        self.emit(
11189            VPMINSW512RRR_MASKZ,
11190            op0.as_operand(),
11191            op1.as_operand(),
11192            op2.as_operand(),
11193            &NOREG,
11194        );
11195    }
11196}
11197
11198impl<'a> VpminswMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
11199    fn vpminsw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
11200        self.emit(
11201            VPMINSW512RRM_MASKZ,
11202            op0.as_operand(),
11203            op1.as_operand(),
11204            op2.as_operand(),
11205            &NOREG,
11206        );
11207    }
11208}
11209
11210/// `VPMINUB`.
11211///
11212/// Supported operand variants:
11213///
11214/// ```text
11215/// +---+---------------+
11216/// | # | Operands      |
11217/// +---+---------------+
11218/// | 1 | Xmm, Xmm, Mem |
11219/// | 2 | Xmm, Xmm, Xmm |
11220/// | 3 | Ymm, Ymm, Mem |
11221/// | 4 | Ymm, Ymm, Ymm |
11222/// | 5 | Zmm, Zmm, Mem |
11223/// | 6 | Zmm, Zmm, Zmm |
11224/// +---+---------------+
11225/// ```
11226pub trait VpminubEmitter<A, B, C> {
11227    fn vpminub(&mut self, op0: A, op1: B, op2: C);
11228}
11229
11230impl<'a> VpminubEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
11231    fn vpminub(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
11232        self.emit(
11233            VPMINUB128RRR,
11234            op0.as_operand(),
11235            op1.as_operand(),
11236            op2.as_operand(),
11237            &NOREG,
11238        );
11239    }
11240}
11241
11242impl<'a> VpminubEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
11243    fn vpminub(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
11244        self.emit(
11245            VPMINUB128RRM,
11246            op0.as_operand(),
11247            op1.as_operand(),
11248            op2.as_operand(),
11249            &NOREG,
11250        );
11251    }
11252}
11253
11254impl<'a> VpminubEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
11255    fn vpminub(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
11256        self.emit(
11257            VPMINUB256RRR,
11258            op0.as_operand(),
11259            op1.as_operand(),
11260            op2.as_operand(),
11261            &NOREG,
11262        );
11263    }
11264}
11265
11266impl<'a> VpminubEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
11267    fn vpminub(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
11268        self.emit(
11269            VPMINUB256RRM,
11270            op0.as_operand(),
11271            op1.as_operand(),
11272            op2.as_operand(),
11273            &NOREG,
11274        );
11275    }
11276}
11277
11278impl<'a> VpminubEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
11279    fn vpminub(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
11280        self.emit(
11281            VPMINUB512RRR,
11282            op0.as_operand(),
11283            op1.as_operand(),
11284            op2.as_operand(),
11285            &NOREG,
11286        );
11287    }
11288}
11289
11290impl<'a> VpminubEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
11291    fn vpminub(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
11292        self.emit(
11293            VPMINUB512RRM,
11294            op0.as_operand(),
11295            op1.as_operand(),
11296            op2.as_operand(),
11297            &NOREG,
11298        );
11299    }
11300}
11301
11302/// `VPMINUB_MASK`.
11303///
11304/// Supported operand variants:
11305///
11306/// ```text
11307/// +---+---------------+
11308/// | # | Operands      |
11309/// +---+---------------+
11310/// | 1 | Xmm, Xmm, Mem |
11311/// | 2 | Xmm, Xmm, Xmm |
11312/// | 3 | Ymm, Ymm, Mem |
11313/// | 4 | Ymm, Ymm, Ymm |
11314/// | 5 | Zmm, Zmm, Mem |
11315/// | 6 | Zmm, Zmm, Zmm |
11316/// +---+---------------+
11317/// ```
11318pub trait VpminubMaskEmitter<A, B, C> {
11319    fn vpminub_mask(&mut self, op0: A, op1: B, op2: C);
11320}
11321
11322impl<'a> VpminubMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
11323    fn vpminub_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
11324        self.emit(
11325            VPMINUB128RRR_MASK,
11326            op0.as_operand(),
11327            op1.as_operand(),
11328            op2.as_operand(),
11329            &NOREG,
11330        );
11331    }
11332}
11333
11334impl<'a> VpminubMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
11335    fn vpminub_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
11336        self.emit(
11337            VPMINUB128RRM_MASK,
11338            op0.as_operand(),
11339            op1.as_operand(),
11340            op2.as_operand(),
11341            &NOREG,
11342        );
11343    }
11344}
11345
11346impl<'a> VpminubMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
11347    fn vpminub_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
11348        self.emit(
11349            VPMINUB256RRR_MASK,
11350            op0.as_operand(),
11351            op1.as_operand(),
11352            op2.as_operand(),
11353            &NOREG,
11354        );
11355    }
11356}
11357
11358impl<'a> VpminubMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
11359    fn vpminub_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
11360        self.emit(
11361            VPMINUB256RRM_MASK,
11362            op0.as_operand(),
11363            op1.as_operand(),
11364            op2.as_operand(),
11365            &NOREG,
11366        );
11367    }
11368}
11369
11370impl<'a> VpminubMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
11371    fn vpminub_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
11372        self.emit(
11373            VPMINUB512RRR_MASK,
11374            op0.as_operand(),
11375            op1.as_operand(),
11376            op2.as_operand(),
11377            &NOREG,
11378        );
11379    }
11380}
11381
11382impl<'a> VpminubMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
11383    fn vpminub_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
11384        self.emit(
11385            VPMINUB512RRM_MASK,
11386            op0.as_operand(),
11387            op1.as_operand(),
11388            op2.as_operand(),
11389            &NOREG,
11390        );
11391    }
11392}
11393
11394/// `VPMINUB_MASKZ`.
11395///
11396/// Supported operand variants:
11397///
11398/// ```text
11399/// +---+---------------+
11400/// | # | Operands      |
11401/// +---+---------------+
11402/// | 1 | Xmm, Xmm, Mem |
11403/// | 2 | Xmm, Xmm, Xmm |
11404/// | 3 | Ymm, Ymm, Mem |
11405/// | 4 | Ymm, Ymm, Ymm |
11406/// | 5 | Zmm, Zmm, Mem |
11407/// | 6 | Zmm, Zmm, Zmm |
11408/// +---+---------------+
11409/// ```
11410pub trait VpminubMaskzEmitter<A, B, C> {
11411    fn vpminub_maskz(&mut self, op0: A, op1: B, op2: C);
11412}
11413
11414impl<'a> VpminubMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
11415    fn vpminub_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
11416        self.emit(
11417            VPMINUB128RRR_MASKZ,
11418            op0.as_operand(),
11419            op1.as_operand(),
11420            op2.as_operand(),
11421            &NOREG,
11422        );
11423    }
11424}
11425
11426impl<'a> VpminubMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
11427    fn vpminub_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
11428        self.emit(
11429            VPMINUB128RRM_MASKZ,
11430            op0.as_operand(),
11431            op1.as_operand(),
11432            op2.as_operand(),
11433            &NOREG,
11434        );
11435    }
11436}
11437
11438impl<'a> VpminubMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
11439    fn vpminub_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
11440        self.emit(
11441            VPMINUB256RRR_MASKZ,
11442            op0.as_operand(),
11443            op1.as_operand(),
11444            op2.as_operand(),
11445            &NOREG,
11446        );
11447    }
11448}
11449
11450impl<'a> VpminubMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
11451    fn vpminub_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
11452        self.emit(
11453            VPMINUB256RRM_MASKZ,
11454            op0.as_operand(),
11455            op1.as_operand(),
11456            op2.as_operand(),
11457            &NOREG,
11458        );
11459    }
11460}
11461
11462impl<'a> VpminubMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
11463    fn vpminub_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
11464        self.emit(
11465            VPMINUB512RRR_MASKZ,
11466            op0.as_operand(),
11467            op1.as_operand(),
11468            op2.as_operand(),
11469            &NOREG,
11470        );
11471    }
11472}
11473
11474impl<'a> VpminubMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
11475    fn vpminub_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
11476        self.emit(
11477            VPMINUB512RRM_MASKZ,
11478            op0.as_operand(),
11479            op1.as_operand(),
11480            op2.as_operand(),
11481            &NOREG,
11482        );
11483    }
11484}
11485
11486/// `VPMINUW`.
11487///
11488/// Supported operand variants:
11489///
11490/// ```text
11491/// +---+---------------+
11492/// | # | Operands      |
11493/// +---+---------------+
11494/// | 1 | Xmm, Xmm, Mem |
11495/// | 2 | Xmm, Xmm, Xmm |
11496/// | 3 | Ymm, Ymm, Mem |
11497/// | 4 | Ymm, Ymm, Ymm |
11498/// | 5 | Zmm, Zmm, Mem |
11499/// | 6 | Zmm, Zmm, Zmm |
11500/// +---+---------------+
11501/// ```
11502pub trait VpminuwEmitter<A, B, C> {
11503    fn vpminuw(&mut self, op0: A, op1: B, op2: C);
11504}
11505
11506impl<'a> VpminuwEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
11507    fn vpminuw(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
11508        self.emit(
11509            VPMINUW128RRR,
11510            op0.as_operand(),
11511            op1.as_operand(),
11512            op2.as_operand(),
11513            &NOREG,
11514        );
11515    }
11516}
11517
11518impl<'a> VpminuwEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
11519    fn vpminuw(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
11520        self.emit(
11521            VPMINUW128RRM,
11522            op0.as_operand(),
11523            op1.as_operand(),
11524            op2.as_operand(),
11525            &NOREG,
11526        );
11527    }
11528}
11529
11530impl<'a> VpminuwEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
11531    fn vpminuw(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
11532        self.emit(
11533            VPMINUW256RRR,
11534            op0.as_operand(),
11535            op1.as_operand(),
11536            op2.as_operand(),
11537            &NOREG,
11538        );
11539    }
11540}
11541
11542impl<'a> VpminuwEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
11543    fn vpminuw(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
11544        self.emit(
11545            VPMINUW256RRM,
11546            op0.as_operand(),
11547            op1.as_operand(),
11548            op2.as_operand(),
11549            &NOREG,
11550        );
11551    }
11552}
11553
11554impl<'a> VpminuwEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
11555    fn vpminuw(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
11556        self.emit(
11557            VPMINUW512RRR,
11558            op0.as_operand(),
11559            op1.as_operand(),
11560            op2.as_operand(),
11561            &NOREG,
11562        );
11563    }
11564}
11565
11566impl<'a> VpminuwEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
11567    fn vpminuw(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
11568        self.emit(
11569            VPMINUW512RRM,
11570            op0.as_operand(),
11571            op1.as_operand(),
11572            op2.as_operand(),
11573            &NOREG,
11574        );
11575    }
11576}
11577
11578/// `VPMINUW_MASK`.
11579///
11580/// Supported operand variants:
11581///
11582/// ```text
11583/// +---+---------------+
11584/// | # | Operands      |
11585/// +---+---------------+
11586/// | 1 | Xmm, Xmm, Mem |
11587/// | 2 | Xmm, Xmm, Xmm |
11588/// | 3 | Ymm, Ymm, Mem |
11589/// | 4 | Ymm, Ymm, Ymm |
11590/// | 5 | Zmm, Zmm, Mem |
11591/// | 6 | Zmm, Zmm, Zmm |
11592/// +---+---------------+
11593/// ```
11594pub trait VpminuwMaskEmitter<A, B, C> {
11595    fn vpminuw_mask(&mut self, op0: A, op1: B, op2: C);
11596}
11597
11598impl<'a> VpminuwMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
11599    fn vpminuw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
11600        self.emit(
11601            VPMINUW128RRR_MASK,
11602            op0.as_operand(),
11603            op1.as_operand(),
11604            op2.as_operand(),
11605            &NOREG,
11606        );
11607    }
11608}
11609
11610impl<'a> VpminuwMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
11611    fn vpminuw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
11612        self.emit(
11613            VPMINUW128RRM_MASK,
11614            op0.as_operand(),
11615            op1.as_operand(),
11616            op2.as_operand(),
11617            &NOREG,
11618        );
11619    }
11620}
11621
11622impl<'a> VpminuwMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
11623    fn vpminuw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
11624        self.emit(
11625            VPMINUW256RRR_MASK,
11626            op0.as_operand(),
11627            op1.as_operand(),
11628            op2.as_operand(),
11629            &NOREG,
11630        );
11631    }
11632}
11633
11634impl<'a> VpminuwMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
11635    fn vpminuw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
11636        self.emit(
11637            VPMINUW256RRM_MASK,
11638            op0.as_operand(),
11639            op1.as_operand(),
11640            op2.as_operand(),
11641            &NOREG,
11642        );
11643    }
11644}
11645
11646impl<'a> VpminuwMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
11647    fn vpminuw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
11648        self.emit(
11649            VPMINUW512RRR_MASK,
11650            op0.as_operand(),
11651            op1.as_operand(),
11652            op2.as_operand(),
11653            &NOREG,
11654        );
11655    }
11656}
11657
11658impl<'a> VpminuwMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
11659    fn vpminuw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
11660        self.emit(
11661            VPMINUW512RRM_MASK,
11662            op0.as_operand(),
11663            op1.as_operand(),
11664            op2.as_operand(),
11665            &NOREG,
11666        );
11667    }
11668}
11669
11670/// `VPMINUW_MASKZ`.
11671///
11672/// Supported operand variants:
11673///
11674/// ```text
11675/// +---+---------------+
11676/// | # | Operands      |
11677/// +---+---------------+
11678/// | 1 | Xmm, Xmm, Mem |
11679/// | 2 | Xmm, Xmm, Xmm |
11680/// | 3 | Ymm, Ymm, Mem |
11681/// | 4 | Ymm, Ymm, Ymm |
11682/// | 5 | Zmm, Zmm, Mem |
11683/// | 6 | Zmm, Zmm, Zmm |
11684/// +---+---------------+
11685/// ```
11686pub trait VpminuwMaskzEmitter<A, B, C> {
11687    fn vpminuw_maskz(&mut self, op0: A, op1: B, op2: C);
11688}
11689
11690impl<'a> VpminuwMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
11691    fn vpminuw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
11692        self.emit(
11693            VPMINUW128RRR_MASKZ,
11694            op0.as_operand(),
11695            op1.as_operand(),
11696            op2.as_operand(),
11697            &NOREG,
11698        );
11699    }
11700}
11701
11702impl<'a> VpminuwMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
11703    fn vpminuw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
11704        self.emit(
11705            VPMINUW128RRM_MASKZ,
11706            op0.as_operand(),
11707            op1.as_operand(),
11708            op2.as_operand(),
11709            &NOREG,
11710        );
11711    }
11712}
11713
11714impl<'a> VpminuwMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
11715    fn vpminuw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
11716        self.emit(
11717            VPMINUW256RRR_MASKZ,
11718            op0.as_operand(),
11719            op1.as_operand(),
11720            op2.as_operand(),
11721            &NOREG,
11722        );
11723    }
11724}
11725
11726impl<'a> VpminuwMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
11727    fn vpminuw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
11728        self.emit(
11729            VPMINUW256RRM_MASKZ,
11730            op0.as_operand(),
11731            op1.as_operand(),
11732            op2.as_operand(),
11733            &NOREG,
11734        );
11735    }
11736}
11737
11738impl<'a> VpminuwMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
11739    fn vpminuw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
11740        self.emit(
11741            VPMINUW512RRR_MASKZ,
11742            op0.as_operand(),
11743            op1.as_operand(),
11744            op2.as_operand(),
11745            &NOREG,
11746        );
11747    }
11748}
11749
11750impl<'a> VpminuwMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
11751    fn vpminuw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
11752        self.emit(
11753            VPMINUW512RRM_MASKZ,
11754            op0.as_operand(),
11755            op1.as_operand(),
11756            op2.as_operand(),
11757            &NOREG,
11758        );
11759    }
11760}
11761
11762/// `VPMOVB2M`.
11763///
11764/// Supported operand variants:
11765///
11766/// ```text
11767/// +---+-----------+
11768/// | # | Operands  |
11769/// +---+-----------+
11770/// | 1 | KReg, Xmm |
11771/// | 2 | KReg, Ymm |
11772/// | 3 | KReg, Zmm |
11773/// +---+-----------+
11774/// ```
11775pub trait Vpmovb2mEmitter<A, B> {
11776    fn vpmovb2m(&mut self, op0: A, op1: B);
11777}
11778
11779impl<'a> Vpmovb2mEmitter<KReg, Xmm> for Assembler<'a> {
11780    fn vpmovb2m(&mut self, op0: KReg, op1: Xmm) {
11781        self.emit(
11782            VPMOVB2M128KR,
11783            op0.as_operand(),
11784            op1.as_operand(),
11785            &NOREG,
11786            &NOREG,
11787        );
11788    }
11789}
11790
11791impl<'a> Vpmovb2mEmitter<KReg, Ymm> for Assembler<'a> {
11792    fn vpmovb2m(&mut self, op0: KReg, op1: Ymm) {
11793        self.emit(
11794            VPMOVB2M256KR,
11795            op0.as_operand(),
11796            op1.as_operand(),
11797            &NOREG,
11798            &NOREG,
11799        );
11800    }
11801}
11802
11803impl<'a> Vpmovb2mEmitter<KReg, Zmm> for Assembler<'a> {
11804    fn vpmovb2m(&mut self, op0: KReg, op1: Zmm) {
11805        self.emit(
11806            VPMOVB2M512KR,
11807            op0.as_operand(),
11808            op1.as_operand(),
11809            &NOREG,
11810            &NOREG,
11811        );
11812    }
11813}
11814
11815/// `VPMOVM2B`.
11816///
11817/// Supported operand variants:
11818///
11819/// ```text
11820/// +---+-----------+
11821/// | # | Operands  |
11822/// +---+-----------+
11823/// | 1 | Xmm, KReg |
11824/// | 2 | Ymm, KReg |
11825/// | 3 | Zmm, KReg |
11826/// +---+-----------+
11827/// ```
11828pub trait Vpmovm2bEmitter<A, B> {
11829    fn vpmovm2b(&mut self, op0: A, op1: B);
11830}
11831
11832impl<'a> Vpmovm2bEmitter<Xmm, KReg> for Assembler<'a> {
11833    fn vpmovm2b(&mut self, op0: Xmm, op1: KReg) {
11834        self.emit(
11835            VPMOVM2B128RK,
11836            op0.as_operand(),
11837            op1.as_operand(),
11838            &NOREG,
11839            &NOREG,
11840        );
11841    }
11842}
11843
11844impl<'a> Vpmovm2bEmitter<Ymm, KReg> for Assembler<'a> {
11845    fn vpmovm2b(&mut self, op0: Ymm, op1: KReg) {
11846        self.emit(
11847            VPMOVM2B256RK,
11848            op0.as_operand(),
11849            op1.as_operand(),
11850            &NOREG,
11851            &NOREG,
11852        );
11853    }
11854}
11855
11856impl<'a> Vpmovm2bEmitter<Zmm, KReg> for Assembler<'a> {
11857    fn vpmovm2b(&mut self, op0: Zmm, op1: KReg) {
11858        self.emit(
11859            VPMOVM2B512RK,
11860            op0.as_operand(),
11861            op1.as_operand(),
11862            &NOREG,
11863            &NOREG,
11864        );
11865    }
11866}
11867
11868/// `VPMOVM2W`.
11869///
11870/// Supported operand variants:
11871///
11872/// ```text
11873/// +---+-----------+
11874/// | # | Operands  |
11875/// +---+-----------+
11876/// | 1 | Xmm, KReg |
11877/// | 2 | Ymm, KReg |
11878/// | 3 | Zmm, KReg |
11879/// +---+-----------+
11880/// ```
11881pub trait Vpmovm2wEmitter<A, B> {
11882    fn vpmovm2w(&mut self, op0: A, op1: B);
11883}
11884
11885impl<'a> Vpmovm2wEmitter<Xmm, KReg> for Assembler<'a> {
11886    fn vpmovm2w(&mut self, op0: Xmm, op1: KReg) {
11887        self.emit(
11888            VPMOVM2W128RK,
11889            op0.as_operand(),
11890            op1.as_operand(),
11891            &NOREG,
11892            &NOREG,
11893        );
11894    }
11895}
11896
11897impl<'a> Vpmovm2wEmitter<Ymm, KReg> for Assembler<'a> {
11898    fn vpmovm2w(&mut self, op0: Ymm, op1: KReg) {
11899        self.emit(
11900            VPMOVM2W256RK,
11901            op0.as_operand(),
11902            op1.as_operand(),
11903            &NOREG,
11904            &NOREG,
11905        );
11906    }
11907}
11908
11909impl<'a> Vpmovm2wEmitter<Zmm, KReg> for Assembler<'a> {
11910    fn vpmovm2w(&mut self, op0: Zmm, op1: KReg) {
11911        self.emit(
11912            VPMOVM2W512RK,
11913            op0.as_operand(),
11914            op1.as_operand(),
11915            &NOREG,
11916            &NOREG,
11917        );
11918    }
11919}
11920
11921/// `VPMOVSWB`.
11922///
11923/// Supported operand variants:
11924///
11925/// ```text
11926/// +---+----------+
11927/// | # | Operands |
11928/// +---+----------+
11929/// | 1 | Mem, Xmm |
11930/// | 2 | Mem, Ymm |
11931/// | 3 | Mem, Zmm |
11932/// | 4 | Xmm, Xmm |
11933/// | 5 | Xmm, Ymm |
11934/// | 6 | Ymm, Zmm |
11935/// +---+----------+
11936/// ```
11937pub trait VpmovswbEmitter<A, B> {
11938    fn vpmovswb(&mut self, op0: A, op1: B);
11939}
11940
11941impl<'a> VpmovswbEmitter<Xmm, Xmm> for Assembler<'a> {
11942    fn vpmovswb(&mut self, op0: Xmm, op1: Xmm) {
11943        self.emit(
11944            VPMOVSWB128RR,
11945            op0.as_operand(),
11946            op1.as_operand(),
11947            &NOREG,
11948            &NOREG,
11949        );
11950    }
11951}
11952
11953impl<'a> VpmovswbEmitter<Mem, Xmm> for Assembler<'a> {
11954    fn vpmovswb(&mut self, op0: Mem, op1: Xmm) {
11955        self.emit(
11956            VPMOVSWB128MR,
11957            op0.as_operand(),
11958            op1.as_operand(),
11959            &NOREG,
11960            &NOREG,
11961        );
11962    }
11963}
11964
11965impl<'a> VpmovswbEmitter<Xmm, Ymm> for Assembler<'a> {
11966    fn vpmovswb(&mut self, op0: Xmm, op1: Ymm) {
11967        self.emit(
11968            VPMOVSWB256RR,
11969            op0.as_operand(),
11970            op1.as_operand(),
11971            &NOREG,
11972            &NOREG,
11973        );
11974    }
11975}
11976
11977impl<'a> VpmovswbEmitter<Mem, Ymm> for Assembler<'a> {
11978    fn vpmovswb(&mut self, op0: Mem, op1: Ymm) {
11979        self.emit(
11980            VPMOVSWB256MR,
11981            op0.as_operand(),
11982            op1.as_operand(),
11983            &NOREG,
11984            &NOREG,
11985        );
11986    }
11987}
11988
11989impl<'a> VpmovswbEmitter<Ymm, Zmm> for Assembler<'a> {
11990    fn vpmovswb(&mut self, op0: Ymm, op1: Zmm) {
11991        self.emit(
11992            VPMOVSWB512RR,
11993            op0.as_operand(),
11994            op1.as_operand(),
11995            &NOREG,
11996            &NOREG,
11997        );
11998    }
11999}
12000
12001impl<'a> VpmovswbEmitter<Mem, Zmm> for Assembler<'a> {
12002    fn vpmovswb(&mut self, op0: Mem, op1: Zmm) {
12003        self.emit(
12004            VPMOVSWB512MR,
12005            op0.as_operand(),
12006            op1.as_operand(),
12007            &NOREG,
12008            &NOREG,
12009        );
12010    }
12011}
12012
12013/// `VPMOVSWB_MASK`.
12014///
12015/// Supported operand variants:
12016///
12017/// ```text
12018/// +---+----------+
12019/// | # | Operands |
12020/// +---+----------+
12021/// | 1 | Mem, Xmm |
12022/// | 2 | Mem, Ymm |
12023/// | 3 | Mem, Zmm |
12024/// | 4 | Xmm, Xmm |
12025/// | 5 | Xmm, Ymm |
12026/// | 6 | Ymm, Zmm |
12027/// +---+----------+
12028/// ```
12029pub trait VpmovswbMaskEmitter<A, B> {
12030    fn vpmovswb_mask(&mut self, op0: A, op1: B);
12031}
12032
12033impl<'a> VpmovswbMaskEmitter<Xmm, Xmm> for Assembler<'a> {
12034    fn vpmovswb_mask(&mut self, op0: Xmm, op1: Xmm) {
12035        self.emit(
12036            VPMOVSWB128RR_MASK,
12037            op0.as_operand(),
12038            op1.as_operand(),
12039            &NOREG,
12040            &NOREG,
12041        );
12042    }
12043}
12044
12045impl<'a> VpmovswbMaskEmitter<Mem, Xmm> for Assembler<'a> {
12046    fn vpmovswb_mask(&mut self, op0: Mem, op1: Xmm) {
12047        self.emit(
12048            VPMOVSWB128MR_MASK,
12049            op0.as_operand(),
12050            op1.as_operand(),
12051            &NOREG,
12052            &NOREG,
12053        );
12054    }
12055}
12056
12057impl<'a> VpmovswbMaskEmitter<Xmm, Ymm> for Assembler<'a> {
12058    fn vpmovswb_mask(&mut self, op0: Xmm, op1: Ymm) {
12059        self.emit(
12060            VPMOVSWB256RR_MASK,
12061            op0.as_operand(),
12062            op1.as_operand(),
12063            &NOREG,
12064            &NOREG,
12065        );
12066    }
12067}
12068
12069impl<'a> VpmovswbMaskEmitter<Mem, Ymm> for Assembler<'a> {
12070    fn vpmovswb_mask(&mut self, op0: Mem, op1: Ymm) {
12071        self.emit(
12072            VPMOVSWB256MR_MASK,
12073            op0.as_operand(),
12074            op1.as_operand(),
12075            &NOREG,
12076            &NOREG,
12077        );
12078    }
12079}
12080
12081impl<'a> VpmovswbMaskEmitter<Ymm, Zmm> for Assembler<'a> {
12082    fn vpmovswb_mask(&mut self, op0: Ymm, op1: Zmm) {
12083        self.emit(
12084            VPMOVSWB512RR_MASK,
12085            op0.as_operand(),
12086            op1.as_operand(),
12087            &NOREG,
12088            &NOREG,
12089        );
12090    }
12091}
12092
12093impl<'a> VpmovswbMaskEmitter<Mem, Zmm> for Assembler<'a> {
12094    fn vpmovswb_mask(&mut self, op0: Mem, op1: Zmm) {
12095        self.emit(
12096            VPMOVSWB512MR_MASK,
12097            op0.as_operand(),
12098            op1.as_operand(),
12099            &NOREG,
12100            &NOREG,
12101        );
12102    }
12103}
12104
12105/// `VPMOVSWB_MASKZ`.
12106///
12107/// Supported operand variants:
12108///
12109/// ```text
12110/// +---+----------+
12111/// | # | Operands |
12112/// +---+----------+
12113/// | 1 | Xmm, Xmm |
12114/// | 2 | Xmm, Ymm |
12115/// | 3 | Ymm, Zmm |
12116/// +---+----------+
12117/// ```
12118pub trait VpmovswbMaskzEmitter<A, B> {
12119    fn vpmovswb_maskz(&mut self, op0: A, op1: B);
12120}
12121
12122impl<'a> VpmovswbMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
12123    fn vpmovswb_maskz(&mut self, op0: Xmm, op1: Xmm) {
12124        self.emit(
12125            VPMOVSWB128RR_MASKZ,
12126            op0.as_operand(),
12127            op1.as_operand(),
12128            &NOREG,
12129            &NOREG,
12130        );
12131    }
12132}
12133
12134impl<'a> VpmovswbMaskzEmitter<Xmm, Ymm> for Assembler<'a> {
12135    fn vpmovswb_maskz(&mut self, op0: Xmm, op1: Ymm) {
12136        self.emit(
12137            VPMOVSWB256RR_MASKZ,
12138            op0.as_operand(),
12139            op1.as_operand(),
12140            &NOREG,
12141            &NOREG,
12142        );
12143    }
12144}
12145
12146impl<'a> VpmovswbMaskzEmitter<Ymm, Zmm> for Assembler<'a> {
12147    fn vpmovswb_maskz(&mut self, op0: Ymm, op1: Zmm) {
12148        self.emit(
12149            VPMOVSWB512RR_MASKZ,
12150            op0.as_operand(),
12151            op1.as_operand(),
12152            &NOREG,
12153            &NOREG,
12154        );
12155    }
12156}
12157
12158/// `VPMOVUSWB`.
12159///
12160/// Supported operand variants:
12161///
12162/// ```text
12163/// +---+----------+
12164/// | # | Operands |
12165/// +---+----------+
12166/// | 1 | Mem, Xmm |
12167/// | 2 | Mem, Ymm |
12168/// | 3 | Mem, Zmm |
12169/// | 4 | Xmm, Xmm |
12170/// | 5 | Xmm, Ymm |
12171/// | 6 | Ymm, Zmm |
12172/// +---+----------+
12173/// ```
12174pub trait VpmovuswbEmitter<A, B> {
12175    fn vpmovuswb(&mut self, op0: A, op1: B);
12176}
12177
12178impl<'a> VpmovuswbEmitter<Xmm, Xmm> for Assembler<'a> {
12179    fn vpmovuswb(&mut self, op0: Xmm, op1: Xmm) {
12180        self.emit(
12181            VPMOVUSWB128RR,
12182            op0.as_operand(),
12183            op1.as_operand(),
12184            &NOREG,
12185            &NOREG,
12186        );
12187    }
12188}
12189
12190impl<'a> VpmovuswbEmitter<Mem, Xmm> for Assembler<'a> {
12191    fn vpmovuswb(&mut self, op0: Mem, op1: Xmm) {
12192        self.emit(
12193            VPMOVUSWB128MR,
12194            op0.as_operand(),
12195            op1.as_operand(),
12196            &NOREG,
12197            &NOREG,
12198        );
12199    }
12200}
12201
12202impl<'a> VpmovuswbEmitter<Xmm, Ymm> for Assembler<'a> {
12203    fn vpmovuswb(&mut self, op0: Xmm, op1: Ymm) {
12204        self.emit(
12205            VPMOVUSWB256RR,
12206            op0.as_operand(),
12207            op1.as_operand(),
12208            &NOREG,
12209            &NOREG,
12210        );
12211    }
12212}
12213
12214impl<'a> VpmovuswbEmitter<Mem, Ymm> for Assembler<'a> {
12215    fn vpmovuswb(&mut self, op0: Mem, op1: Ymm) {
12216        self.emit(
12217            VPMOVUSWB256MR,
12218            op0.as_operand(),
12219            op1.as_operand(),
12220            &NOREG,
12221            &NOREG,
12222        );
12223    }
12224}
12225
12226impl<'a> VpmovuswbEmitter<Ymm, Zmm> for Assembler<'a> {
12227    fn vpmovuswb(&mut self, op0: Ymm, op1: Zmm) {
12228        self.emit(
12229            VPMOVUSWB512RR,
12230            op0.as_operand(),
12231            op1.as_operand(),
12232            &NOREG,
12233            &NOREG,
12234        );
12235    }
12236}
12237
12238impl<'a> VpmovuswbEmitter<Mem, Zmm> for Assembler<'a> {
12239    fn vpmovuswb(&mut self, op0: Mem, op1: Zmm) {
12240        self.emit(
12241            VPMOVUSWB512MR,
12242            op0.as_operand(),
12243            op1.as_operand(),
12244            &NOREG,
12245            &NOREG,
12246        );
12247    }
12248}
12249
12250/// `VPMOVUSWB_MASK`.
12251///
12252/// Supported operand variants:
12253///
12254/// ```text
12255/// +---+----------+
12256/// | # | Operands |
12257/// +---+----------+
12258/// | 1 | Mem, Xmm |
12259/// | 2 | Mem, Ymm |
12260/// | 3 | Mem, Zmm |
12261/// | 4 | Xmm, Xmm |
12262/// | 5 | Xmm, Ymm |
12263/// | 6 | Ymm, Zmm |
12264/// +---+----------+
12265/// ```
12266pub trait VpmovuswbMaskEmitter<A, B> {
12267    fn vpmovuswb_mask(&mut self, op0: A, op1: B);
12268}
12269
12270impl<'a> VpmovuswbMaskEmitter<Xmm, Xmm> for Assembler<'a> {
12271    fn vpmovuswb_mask(&mut self, op0: Xmm, op1: Xmm) {
12272        self.emit(
12273            VPMOVUSWB128RR_MASK,
12274            op0.as_operand(),
12275            op1.as_operand(),
12276            &NOREG,
12277            &NOREG,
12278        );
12279    }
12280}
12281
12282impl<'a> VpmovuswbMaskEmitter<Mem, Xmm> for Assembler<'a> {
12283    fn vpmovuswb_mask(&mut self, op0: Mem, op1: Xmm) {
12284        self.emit(
12285            VPMOVUSWB128MR_MASK,
12286            op0.as_operand(),
12287            op1.as_operand(),
12288            &NOREG,
12289            &NOREG,
12290        );
12291    }
12292}
12293
12294impl<'a> VpmovuswbMaskEmitter<Xmm, Ymm> for Assembler<'a> {
12295    fn vpmovuswb_mask(&mut self, op0: Xmm, op1: Ymm) {
12296        self.emit(
12297            VPMOVUSWB256RR_MASK,
12298            op0.as_operand(),
12299            op1.as_operand(),
12300            &NOREG,
12301            &NOREG,
12302        );
12303    }
12304}
12305
12306impl<'a> VpmovuswbMaskEmitter<Mem, Ymm> for Assembler<'a> {
12307    fn vpmovuswb_mask(&mut self, op0: Mem, op1: Ymm) {
12308        self.emit(
12309            VPMOVUSWB256MR_MASK,
12310            op0.as_operand(),
12311            op1.as_operand(),
12312            &NOREG,
12313            &NOREG,
12314        );
12315    }
12316}
12317
12318impl<'a> VpmovuswbMaskEmitter<Ymm, Zmm> for Assembler<'a> {
12319    fn vpmovuswb_mask(&mut self, op0: Ymm, op1: Zmm) {
12320        self.emit(
12321            VPMOVUSWB512RR_MASK,
12322            op0.as_operand(),
12323            op1.as_operand(),
12324            &NOREG,
12325            &NOREG,
12326        );
12327    }
12328}
12329
12330impl<'a> VpmovuswbMaskEmitter<Mem, Zmm> for Assembler<'a> {
12331    fn vpmovuswb_mask(&mut self, op0: Mem, op1: Zmm) {
12332        self.emit(
12333            VPMOVUSWB512MR_MASK,
12334            op0.as_operand(),
12335            op1.as_operand(),
12336            &NOREG,
12337            &NOREG,
12338        );
12339    }
12340}
12341
12342/// `VPMOVUSWB_MASKZ`.
12343///
12344/// Supported operand variants:
12345///
12346/// ```text
12347/// +---+----------+
12348/// | # | Operands |
12349/// +---+----------+
12350/// | 1 | Xmm, Xmm |
12351/// | 2 | Xmm, Ymm |
12352/// | 3 | Ymm, Zmm |
12353/// +---+----------+
12354/// ```
12355pub trait VpmovuswbMaskzEmitter<A, B> {
12356    fn vpmovuswb_maskz(&mut self, op0: A, op1: B);
12357}
12358
12359impl<'a> VpmovuswbMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
12360    fn vpmovuswb_maskz(&mut self, op0: Xmm, op1: Xmm) {
12361        self.emit(
12362            VPMOVUSWB128RR_MASKZ,
12363            op0.as_operand(),
12364            op1.as_operand(),
12365            &NOREG,
12366            &NOREG,
12367        );
12368    }
12369}
12370
12371impl<'a> VpmovuswbMaskzEmitter<Xmm, Ymm> for Assembler<'a> {
12372    fn vpmovuswb_maskz(&mut self, op0: Xmm, op1: Ymm) {
12373        self.emit(
12374            VPMOVUSWB256RR_MASKZ,
12375            op0.as_operand(),
12376            op1.as_operand(),
12377            &NOREG,
12378            &NOREG,
12379        );
12380    }
12381}
12382
12383impl<'a> VpmovuswbMaskzEmitter<Ymm, Zmm> for Assembler<'a> {
12384    fn vpmovuswb_maskz(&mut self, op0: Ymm, op1: Zmm) {
12385        self.emit(
12386            VPMOVUSWB512RR_MASKZ,
12387            op0.as_operand(),
12388            op1.as_operand(),
12389            &NOREG,
12390            &NOREG,
12391        );
12392    }
12393}
12394
12395/// `VPMOVW2M`.
12396///
12397/// Supported operand variants:
12398///
12399/// ```text
12400/// +---+-----------+
12401/// | # | Operands  |
12402/// +---+-----------+
12403/// | 1 | KReg, Xmm |
12404/// | 2 | KReg, Ymm |
12405/// | 3 | KReg, Zmm |
12406/// +---+-----------+
12407/// ```
12408pub trait Vpmovw2mEmitter<A, B> {
12409    fn vpmovw2m(&mut self, op0: A, op1: B);
12410}
12411
12412impl<'a> Vpmovw2mEmitter<KReg, Xmm> for Assembler<'a> {
12413    fn vpmovw2m(&mut self, op0: KReg, op1: Xmm) {
12414        self.emit(
12415            VPMOVW2M128KR,
12416            op0.as_operand(),
12417            op1.as_operand(),
12418            &NOREG,
12419            &NOREG,
12420        );
12421    }
12422}
12423
12424impl<'a> Vpmovw2mEmitter<KReg, Ymm> for Assembler<'a> {
12425    fn vpmovw2m(&mut self, op0: KReg, op1: Ymm) {
12426        self.emit(
12427            VPMOVW2M256KR,
12428            op0.as_operand(),
12429            op1.as_operand(),
12430            &NOREG,
12431            &NOREG,
12432        );
12433    }
12434}
12435
12436impl<'a> Vpmovw2mEmitter<KReg, Zmm> for Assembler<'a> {
12437    fn vpmovw2m(&mut self, op0: KReg, op1: Zmm) {
12438        self.emit(
12439            VPMOVW2M512KR,
12440            op0.as_operand(),
12441            op1.as_operand(),
12442            &NOREG,
12443            &NOREG,
12444        );
12445    }
12446}
12447
12448/// `VPMOVWB`.
12449///
12450/// Supported operand variants:
12451///
12452/// ```text
12453/// +---+----------+
12454/// | # | Operands |
12455/// +---+----------+
12456/// | 1 | Mem, Xmm |
12457/// | 2 | Mem, Ymm |
12458/// | 3 | Mem, Zmm |
12459/// | 4 | Xmm, Xmm |
12460/// | 5 | Xmm, Ymm |
12461/// | 6 | Ymm, Zmm |
12462/// +---+----------+
12463/// ```
12464pub trait VpmovwbEmitter<A, B> {
12465    fn vpmovwb(&mut self, op0: A, op1: B);
12466}
12467
12468impl<'a> VpmovwbEmitter<Xmm, Xmm> for Assembler<'a> {
12469    fn vpmovwb(&mut self, op0: Xmm, op1: Xmm) {
12470        self.emit(
12471            VPMOVWB128RR,
12472            op0.as_operand(),
12473            op1.as_operand(),
12474            &NOREG,
12475            &NOREG,
12476        );
12477    }
12478}
12479
12480impl<'a> VpmovwbEmitter<Mem, Xmm> for Assembler<'a> {
12481    fn vpmovwb(&mut self, op0: Mem, op1: Xmm) {
12482        self.emit(
12483            VPMOVWB128MR,
12484            op0.as_operand(),
12485            op1.as_operand(),
12486            &NOREG,
12487            &NOREG,
12488        );
12489    }
12490}
12491
12492impl<'a> VpmovwbEmitter<Xmm, Ymm> for Assembler<'a> {
12493    fn vpmovwb(&mut self, op0: Xmm, op1: Ymm) {
12494        self.emit(
12495            VPMOVWB256RR,
12496            op0.as_operand(),
12497            op1.as_operand(),
12498            &NOREG,
12499            &NOREG,
12500        );
12501    }
12502}
12503
12504impl<'a> VpmovwbEmitter<Mem, Ymm> for Assembler<'a> {
12505    fn vpmovwb(&mut self, op0: Mem, op1: Ymm) {
12506        self.emit(
12507            VPMOVWB256MR,
12508            op0.as_operand(),
12509            op1.as_operand(),
12510            &NOREG,
12511            &NOREG,
12512        );
12513    }
12514}
12515
12516impl<'a> VpmovwbEmitter<Ymm, Zmm> for Assembler<'a> {
12517    fn vpmovwb(&mut self, op0: Ymm, op1: Zmm) {
12518        self.emit(
12519            VPMOVWB512RR,
12520            op0.as_operand(),
12521            op1.as_operand(),
12522            &NOREG,
12523            &NOREG,
12524        );
12525    }
12526}
12527
12528impl<'a> VpmovwbEmitter<Mem, Zmm> for Assembler<'a> {
12529    fn vpmovwb(&mut self, op0: Mem, op1: Zmm) {
12530        self.emit(
12531            VPMOVWB512MR,
12532            op0.as_operand(),
12533            op1.as_operand(),
12534            &NOREG,
12535            &NOREG,
12536        );
12537    }
12538}
12539
12540/// `VPMOVWB_MASK`.
12541///
12542/// Supported operand variants:
12543///
12544/// ```text
12545/// +---+----------+
12546/// | # | Operands |
12547/// +---+----------+
12548/// | 1 | Mem, Xmm |
12549/// | 2 | Mem, Ymm |
12550/// | 3 | Mem, Zmm |
12551/// | 4 | Xmm, Xmm |
12552/// | 5 | Xmm, Ymm |
12553/// | 6 | Ymm, Zmm |
12554/// +---+----------+
12555/// ```
12556pub trait VpmovwbMaskEmitter<A, B> {
12557    fn vpmovwb_mask(&mut self, op0: A, op1: B);
12558}
12559
12560impl<'a> VpmovwbMaskEmitter<Xmm, Xmm> for Assembler<'a> {
12561    fn vpmovwb_mask(&mut self, op0: Xmm, op1: Xmm) {
12562        self.emit(
12563            VPMOVWB128RR_MASK,
12564            op0.as_operand(),
12565            op1.as_operand(),
12566            &NOREG,
12567            &NOREG,
12568        );
12569    }
12570}
12571
12572impl<'a> VpmovwbMaskEmitter<Mem, Xmm> for Assembler<'a> {
12573    fn vpmovwb_mask(&mut self, op0: Mem, op1: Xmm) {
12574        self.emit(
12575            VPMOVWB128MR_MASK,
12576            op0.as_operand(),
12577            op1.as_operand(),
12578            &NOREG,
12579            &NOREG,
12580        );
12581    }
12582}
12583
12584impl<'a> VpmovwbMaskEmitter<Xmm, Ymm> for Assembler<'a> {
12585    fn vpmovwb_mask(&mut self, op0: Xmm, op1: Ymm) {
12586        self.emit(
12587            VPMOVWB256RR_MASK,
12588            op0.as_operand(),
12589            op1.as_operand(),
12590            &NOREG,
12591            &NOREG,
12592        );
12593    }
12594}
12595
12596impl<'a> VpmovwbMaskEmitter<Mem, Ymm> for Assembler<'a> {
12597    fn vpmovwb_mask(&mut self, op0: Mem, op1: Ymm) {
12598        self.emit(
12599            VPMOVWB256MR_MASK,
12600            op0.as_operand(),
12601            op1.as_operand(),
12602            &NOREG,
12603            &NOREG,
12604        );
12605    }
12606}
12607
12608impl<'a> VpmovwbMaskEmitter<Ymm, Zmm> for Assembler<'a> {
12609    fn vpmovwb_mask(&mut self, op0: Ymm, op1: Zmm) {
12610        self.emit(
12611            VPMOVWB512RR_MASK,
12612            op0.as_operand(),
12613            op1.as_operand(),
12614            &NOREG,
12615            &NOREG,
12616        );
12617    }
12618}
12619
12620impl<'a> VpmovwbMaskEmitter<Mem, Zmm> for Assembler<'a> {
12621    fn vpmovwb_mask(&mut self, op0: Mem, op1: Zmm) {
12622        self.emit(
12623            VPMOVWB512MR_MASK,
12624            op0.as_operand(),
12625            op1.as_operand(),
12626            &NOREG,
12627            &NOREG,
12628        );
12629    }
12630}
12631
12632/// `VPMOVWB_MASKZ`.
12633///
12634/// Supported operand variants:
12635///
12636/// ```text
12637/// +---+----------+
12638/// | # | Operands |
12639/// +---+----------+
12640/// | 1 | Xmm, Xmm |
12641/// | 2 | Xmm, Ymm |
12642/// | 3 | Ymm, Zmm |
12643/// +---+----------+
12644/// ```
12645pub trait VpmovwbMaskzEmitter<A, B> {
12646    fn vpmovwb_maskz(&mut self, op0: A, op1: B);
12647}
12648
12649impl<'a> VpmovwbMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
12650    fn vpmovwb_maskz(&mut self, op0: Xmm, op1: Xmm) {
12651        self.emit(
12652            VPMOVWB128RR_MASKZ,
12653            op0.as_operand(),
12654            op1.as_operand(),
12655            &NOREG,
12656            &NOREG,
12657        );
12658    }
12659}
12660
12661impl<'a> VpmovwbMaskzEmitter<Xmm, Ymm> for Assembler<'a> {
12662    fn vpmovwb_maskz(&mut self, op0: Xmm, op1: Ymm) {
12663        self.emit(
12664            VPMOVWB256RR_MASKZ,
12665            op0.as_operand(),
12666            op1.as_operand(),
12667            &NOREG,
12668            &NOREG,
12669        );
12670    }
12671}
12672
12673impl<'a> VpmovwbMaskzEmitter<Ymm, Zmm> for Assembler<'a> {
12674    fn vpmovwb_maskz(&mut self, op0: Ymm, op1: Zmm) {
12675        self.emit(
12676            VPMOVWB512RR_MASKZ,
12677            op0.as_operand(),
12678            op1.as_operand(),
12679            &NOREG,
12680            &NOREG,
12681        );
12682    }
12683}
12684
12685/// `VPMULHRSW`.
12686///
12687/// Supported operand variants:
12688///
12689/// ```text
12690/// +---+---------------+
12691/// | # | Operands      |
12692/// +---+---------------+
12693/// | 1 | Xmm, Xmm, Mem |
12694/// | 2 | Xmm, Xmm, Xmm |
12695/// | 3 | Ymm, Ymm, Mem |
12696/// | 4 | Ymm, Ymm, Ymm |
12697/// | 5 | Zmm, Zmm, Mem |
12698/// | 6 | Zmm, Zmm, Zmm |
12699/// +---+---------------+
12700/// ```
12701pub trait VpmulhrswEmitter<A, B, C> {
12702    fn vpmulhrsw(&mut self, op0: A, op1: B, op2: C);
12703}
12704
12705impl<'a> VpmulhrswEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
12706    fn vpmulhrsw(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
12707        self.emit(
12708            VPMULHRSW128RRR,
12709            op0.as_operand(),
12710            op1.as_operand(),
12711            op2.as_operand(),
12712            &NOREG,
12713        );
12714    }
12715}
12716
12717impl<'a> VpmulhrswEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
12718    fn vpmulhrsw(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
12719        self.emit(
12720            VPMULHRSW128RRM,
12721            op0.as_operand(),
12722            op1.as_operand(),
12723            op2.as_operand(),
12724            &NOREG,
12725        );
12726    }
12727}
12728
12729impl<'a> VpmulhrswEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
12730    fn vpmulhrsw(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
12731        self.emit(
12732            VPMULHRSW256RRR,
12733            op0.as_operand(),
12734            op1.as_operand(),
12735            op2.as_operand(),
12736            &NOREG,
12737        );
12738    }
12739}
12740
12741impl<'a> VpmulhrswEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
12742    fn vpmulhrsw(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
12743        self.emit(
12744            VPMULHRSW256RRM,
12745            op0.as_operand(),
12746            op1.as_operand(),
12747            op2.as_operand(),
12748            &NOREG,
12749        );
12750    }
12751}
12752
12753impl<'a> VpmulhrswEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
12754    fn vpmulhrsw(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
12755        self.emit(
12756            VPMULHRSW512RRR,
12757            op0.as_operand(),
12758            op1.as_operand(),
12759            op2.as_operand(),
12760            &NOREG,
12761        );
12762    }
12763}
12764
12765impl<'a> VpmulhrswEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
12766    fn vpmulhrsw(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
12767        self.emit(
12768            VPMULHRSW512RRM,
12769            op0.as_operand(),
12770            op1.as_operand(),
12771            op2.as_operand(),
12772            &NOREG,
12773        );
12774    }
12775}
12776
12777/// `VPMULHRSW_MASK`.
12778///
12779/// Supported operand variants:
12780///
12781/// ```text
12782/// +---+---------------+
12783/// | # | Operands      |
12784/// +---+---------------+
12785/// | 1 | Xmm, Xmm, Mem |
12786/// | 2 | Xmm, Xmm, Xmm |
12787/// | 3 | Ymm, Ymm, Mem |
12788/// | 4 | Ymm, Ymm, Ymm |
12789/// | 5 | Zmm, Zmm, Mem |
12790/// | 6 | Zmm, Zmm, Zmm |
12791/// +---+---------------+
12792/// ```
12793pub trait VpmulhrswMaskEmitter<A, B, C> {
12794    fn vpmulhrsw_mask(&mut self, op0: A, op1: B, op2: C);
12795}
12796
12797impl<'a> VpmulhrswMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
12798    fn vpmulhrsw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
12799        self.emit(
12800            VPMULHRSW128RRR_MASK,
12801            op0.as_operand(),
12802            op1.as_operand(),
12803            op2.as_operand(),
12804            &NOREG,
12805        );
12806    }
12807}
12808
12809impl<'a> VpmulhrswMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
12810    fn vpmulhrsw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
12811        self.emit(
12812            VPMULHRSW128RRM_MASK,
12813            op0.as_operand(),
12814            op1.as_operand(),
12815            op2.as_operand(),
12816            &NOREG,
12817        );
12818    }
12819}
12820
12821impl<'a> VpmulhrswMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
12822    fn vpmulhrsw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
12823        self.emit(
12824            VPMULHRSW256RRR_MASK,
12825            op0.as_operand(),
12826            op1.as_operand(),
12827            op2.as_operand(),
12828            &NOREG,
12829        );
12830    }
12831}
12832
12833impl<'a> VpmulhrswMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
12834    fn vpmulhrsw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
12835        self.emit(
12836            VPMULHRSW256RRM_MASK,
12837            op0.as_operand(),
12838            op1.as_operand(),
12839            op2.as_operand(),
12840            &NOREG,
12841        );
12842    }
12843}
12844
12845impl<'a> VpmulhrswMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
12846    fn vpmulhrsw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
12847        self.emit(
12848            VPMULHRSW512RRR_MASK,
12849            op0.as_operand(),
12850            op1.as_operand(),
12851            op2.as_operand(),
12852            &NOREG,
12853        );
12854    }
12855}
12856
12857impl<'a> VpmulhrswMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
12858    fn vpmulhrsw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
12859        self.emit(
12860            VPMULHRSW512RRM_MASK,
12861            op0.as_operand(),
12862            op1.as_operand(),
12863            op2.as_operand(),
12864            &NOREG,
12865        );
12866    }
12867}
12868
12869/// `VPMULHRSW_MASKZ`.
12870///
12871/// Supported operand variants:
12872///
12873/// ```text
12874/// +---+---------------+
12875/// | # | Operands      |
12876/// +---+---------------+
12877/// | 1 | Xmm, Xmm, Mem |
12878/// | 2 | Xmm, Xmm, Xmm |
12879/// | 3 | Ymm, Ymm, Mem |
12880/// | 4 | Ymm, Ymm, Ymm |
12881/// | 5 | Zmm, Zmm, Mem |
12882/// | 6 | Zmm, Zmm, Zmm |
12883/// +---+---------------+
12884/// ```
12885pub trait VpmulhrswMaskzEmitter<A, B, C> {
12886    fn vpmulhrsw_maskz(&mut self, op0: A, op1: B, op2: C);
12887}
12888
12889impl<'a> VpmulhrswMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
12890    fn vpmulhrsw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
12891        self.emit(
12892            VPMULHRSW128RRR_MASKZ,
12893            op0.as_operand(),
12894            op1.as_operand(),
12895            op2.as_operand(),
12896            &NOREG,
12897        );
12898    }
12899}
12900
12901impl<'a> VpmulhrswMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
12902    fn vpmulhrsw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
12903        self.emit(
12904            VPMULHRSW128RRM_MASKZ,
12905            op0.as_operand(),
12906            op1.as_operand(),
12907            op2.as_operand(),
12908            &NOREG,
12909        );
12910    }
12911}
12912
12913impl<'a> VpmulhrswMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
12914    fn vpmulhrsw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
12915        self.emit(
12916            VPMULHRSW256RRR_MASKZ,
12917            op0.as_operand(),
12918            op1.as_operand(),
12919            op2.as_operand(),
12920            &NOREG,
12921        );
12922    }
12923}
12924
12925impl<'a> VpmulhrswMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
12926    fn vpmulhrsw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
12927        self.emit(
12928            VPMULHRSW256RRM_MASKZ,
12929            op0.as_operand(),
12930            op1.as_operand(),
12931            op2.as_operand(),
12932            &NOREG,
12933        );
12934    }
12935}
12936
12937impl<'a> VpmulhrswMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
12938    fn vpmulhrsw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
12939        self.emit(
12940            VPMULHRSW512RRR_MASKZ,
12941            op0.as_operand(),
12942            op1.as_operand(),
12943            op2.as_operand(),
12944            &NOREG,
12945        );
12946    }
12947}
12948
12949impl<'a> VpmulhrswMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
12950    fn vpmulhrsw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
12951        self.emit(
12952            VPMULHRSW512RRM_MASKZ,
12953            op0.as_operand(),
12954            op1.as_operand(),
12955            op2.as_operand(),
12956            &NOREG,
12957        );
12958    }
12959}
12960
12961/// `VPMULHUW`.
12962///
12963/// Supported operand variants:
12964///
12965/// ```text
12966/// +---+---------------+
12967/// | # | Operands      |
12968/// +---+---------------+
12969/// | 1 | Xmm, Xmm, Mem |
12970/// | 2 | Xmm, Xmm, Xmm |
12971/// | 3 | Ymm, Ymm, Mem |
12972/// | 4 | Ymm, Ymm, Ymm |
12973/// | 5 | Zmm, Zmm, Mem |
12974/// | 6 | Zmm, Zmm, Zmm |
12975/// +---+---------------+
12976/// ```
12977pub trait VpmulhuwEmitter<A, B, C> {
12978    fn vpmulhuw(&mut self, op0: A, op1: B, op2: C);
12979}
12980
12981impl<'a> VpmulhuwEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
12982    fn vpmulhuw(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
12983        self.emit(
12984            VPMULHUW128RRR,
12985            op0.as_operand(),
12986            op1.as_operand(),
12987            op2.as_operand(),
12988            &NOREG,
12989        );
12990    }
12991}
12992
12993impl<'a> VpmulhuwEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
12994    fn vpmulhuw(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
12995        self.emit(
12996            VPMULHUW128RRM,
12997            op0.as_operand(),
12998            op1.as_operand(),
12999            op2.as_operand(),
13000            &NOREG,
13001        );
13002    }
13003}
13004
13005impl<'a> VpmulhuwEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
13006    fn vpmulhuw(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
13007        self.emit(
13008            VPMULHUW256RRR,
13009            op0.as_operand(),
13010            op1.as_operand(),
13011            op2.as_operand(),
13012            &NOREG,
13013        );
13014    }
13015}
13016
13017impl<'a> VpmulhuwEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
13018    fn vpmulhuw(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
13019        self.emit(
13020            VPMULHUW256RRM,
13021            op0.as_operand(),
13022            op1.as_operand(),
13023            op2.as_operand(),
13024            &NOREG,
13025        );
13026    }
13027}
13028
13029impl<'a> VpmulhuwEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
13030    fn vpmulhuw(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
13031        self.emit(
13032            VPMULHUW512RRR,
13033            op0.as_operand(),
13034            op1.as_operand(),
13035            op2.as_operand(),
13036            &NOREG,
13037        );
13038    }
13039}
13040
13041impl<'a> VpmulhuwEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
13042    fn vpmulhuw(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
13043        self.emit(
13044            VPMULHUW512RRM,
13045            op0.as_operand(),
13046            op1.as_operand(),
13047            op2.as_operand(),
13048            &NOREG,
13049        );
13050    }
13051}
13052
13053/// `VPMULHUW_MASK`.
13054///
13055/// Supported operand variants:
13056///
13057/// ```text
13058/// +---+---------------+
13059/// | # | Operands      |
13060/// +---+---------------+
13061/// | 1 | Xmm, Xmm, Mem |
13062/// | 2 | Xmm, Xmm, Xmm |
13063/// | 3 | Ymm, Ymm, Mem |
13064/// | 4 | Ymm, Ymm, Ymm |
13065/// | 5 | Zmm, Zmm, Mem |
13066/// | 6 | Zmm, Zmm, Zmm |
13067/// +---+---------------+
13068/// ```
13069pub trait VpmulhuwMaskEmitter<A, B, C> {
13070    fn vpmulhuw_mask(&mut self, op0: A, op1: B, op2: C);
13071}
13072
13073impl<'a> VpmulhuwMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
13074    fn vpmulhuw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
13075        self.emit(
13076            VPMULHUW128RRR_MASK,
13077            op0.as_operand(),
13078            op1.as_operand(),
13079            op2.as_operand(),
13080            &NOREG,
13081        );
13082    }
13083}
13084
13085impl<'a> VpmulhuwMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
13086    fn vpmulhuw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
13087        self.emit(
13088            VPMULHUW128RRM_MASK,
13089            op0.as_operand(),
13090            op1.as_operand(),
13091            op2.as_operand(),
13092            &NOREG,
13093        );
13094    }
13095}
13096
13097impl<'a> VpmulhuwMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
13098    fn vpmulhuw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
13099        self.emit(
13100            VPMULHUW256RRR_MASK,
13101            op0.as_operand(),
13102            op1.as_operand(),
13103            op2.as_operand(),
13104            &NOREG,
13105        );
13106    }
13107}
13108
13109impl<'a> VpmulhuwMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
13110    fn vpmulhuw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
13111        self.emit(
13112            VPMULHUW256RRM_MASK,
13113            op0.as_operand(),
13114            op1.as_operand(),
13115            op2.as_operand(),
13116            &NOREG,
13117        );
13118    }
13119}
13120
13121impl<'a> VpmulhuwMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
13122    fn vpmulhuw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
13123        self.emit(
13124            VPMULHUW512RRR_MASK,
13125            op0.as_operand(),
13126            op1.as_operand(),
13127            op2.as_operand(),
13128            &NOREG,
13129        );
13130    }
13131}
13132
13133impl<'a> VpmulhuwMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
13134    fn vpmulhuw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
13135        self.emit(
13136            VPMULHUW512RRM_MASK,
13137            op0.as_operand(),
13138            op1.as_operand(),
13139            op2.as_operand(),
13140            &NOREG,
13141        );
13142    }
13143}
13144
13145/// `VPMULHUW_MASKZ`.
13146///
13147/// Supported operand variants:
13148///
13149/// ```text
13150/// +---+---------------+
13151/// | # | Operands      |
13152/// +---+---------------+
13153/// | 1 | Xmm, Xmm, Mem |
13154/// | 2 | Xmm, Xmm, Xmm |
13155/// | 3 | Ymm, Ymm, Mem |
13156/// | 4 | Ymm, Ymm, Ymm |
13157/// | 5 | Zmm, Zmm, Mem |
13158/// | 6 | Zmm, Zmm, Zmm |
13159/// +---+---------------+
13160/// ```
13161pub trait VpmulhuwMaskzEmitter<A, B, C> {
13162    fn vpmulhuw_maskz(&mut self, op0: A, op1: B, op2: C);
13163}
13164
13165impl<'a> VpmulhuwMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
13166    fn vpmulhuw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
13167        self.emit(
13168            VPMULHUW128RRR_MASKZ,
13169            op0.as_operand(),
13170            op1.as_operand(),
13171            op2.as_operand(),
13172            &NOREG,
13173        );
13174    }
13175}
13176
13177impl<'a> VpmulhuwMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
13178    fn vpmulhuw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
13179        self.emit(
13180            VPMULHUW128RRM_MASKZ,
13181            op0.as_operand(),
13182            op1.as_operand(),
13183            op2.as_operand(),
13184            &NOREG,
13185        );
13186    }
13187}
13188
13189impl<'a> VpmulhuwMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
13190    fn vpmulhuw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
13191        self.emit(
13192            VPMULHUW256RRR_MASKZ,
13193            op0.as_operand(),
13194            op1.as_operand(),
13195            op2.as_operand(),
13196            &NOREG,
13197        );
13198    }
13199}
13200
13201impl<'a> VpmulhuwMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
13202    fn vpmulhuw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
13203        self.emit(
13204            VPMULHUW256RRM_MASKZ,
13205            op0.as_operand(),
13206            op1.as_operand(),
13207            op2.as_operand(),
13208            &NOREG,
13209        );
13210    }
13211}
13212
13213impl<'a> VpmulhuwMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
13214    fn vpmulhuw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
13215        self.emit(
13216            VPMULHUW512RRR_MASKZ,
13217            op0.as_operand(),
13218            op1.as_operand(),
13219            op2.as_operand(),
13220            &NOREG,
13221        );
13222    }
13223}
13224
13225impl<'a> VpmulhuwMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
13226    fn vpmulhuw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
13227        self.emit(
13228            VPMULHUW512RRM_MASKZ,
13229            op0.as_operand(),
13230            op1.as_operand(),
13231            op2.as_operand(),
13232            &NOREG,
13233        );
13234    }
13235}
13236
13237/// `VPMULHW`.
13238///
13239/// Supported operand variants:
13240///
13241/// ```text
13242/// +---+---------------+
13243/// | # | Operands      |
13244/// +---+---------------+
13245/// | 1 | Xmm, Xmm, Mem |
13246/// | 2 | Xmm, Xmm, Xmm |
13247/// | 3 | Ymm, Ymm, Mem |
13248/// | 4 | Ymm, Ymm, Ymm |
13249/// | 5 | Zmm, Zmm, Mem |
13250/// | 6 | Zmm, Zmm, Zmm |
13251/// +---+---------------+
13252/// ```
13253pub trait VpmulhwEmitter<A, B, C> {
13254    fn vpmulhw(&mut self, op0: A, op1: B, op2: C);
13255}
13256
13257impl<'a> VpmulhwEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
13258    fn vpmulhw(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
13259        self.emit(
13260            VPMULHW128RRR,
13261            op0.as_operand(),
13262            op1.as_operand(),
13263            op2.as_operand(),
13264            &NOREG,
13265        );
13266    }
13267}
13268
13269impl<'a> VpmulhwEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
13270    fn vpmulhw(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
13271        self.emit(
13272            VPMULHW128RRM,
13273            op0.as_operand(),
13274            op1.as_operand(),
13275            op2.as_operand(),
13276            &NOREG,
13277        );
13278    }
13279}
13280
13281impl<'a> VpmulhwEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
13282    fn vpmulhw(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
13283        self.emit(
13284            VPMULHW256RRR,
13285            op0.as_operand(),
13286            op1.as_operand(),
13287            op2.as_operand(),
13288            &NOREG,
13289        );
13290    }
13291}
13292
13293impl<'a> VpmulhwEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
13294    fn vpmulhw(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
13295        self.emit(
13296            VPMULHW256RRM,
13297            op0.as_operand(),
13298            op1.as_operand(),
13299            op2.as_operand(),
13300            &NOREG,
13301        );
13302    }
13303}
13304
13305impl<'a> VpmulhwEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
13306    fn vpmulhw(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
13307        self.emit(
13308            VPMULHW512RRR,
13309            op0.as_operand(),
13310            op1.as_operand(),
13311            op2.as_operand(),
13312            &NOREG,
13313        );
13314    }
13315}
13316
13317impl<'a> VpmulhwEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
13318    fn vpmulhw(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
13319        self.emit(
13320            VPMULHW512RRM,
13321            op0.as_operand(),
13322            op1.as_operand(),
13323            op2.as_operand(),
13324            &NOREG,
13325        );
13326    }
13327}
13328
13329/// `VPMULHW_MASK`.
13330///
13331/// Supported operand variants:
13332///
13333/// ```text
13334/// +---+---------------+
13335/// | # | Operands      |
13336/// +---+---------------+
13337/// | 1 | Xmm, Xmm, Mem |
13338/// | 2 | Xmm, Xmm, Xmm |
13339/// | 3 | Ymm, Ymm, Mem |
13340/// | 4 | Ymm, Ymm, Ymm |
13341/// | 5 | Zmm, Zmm, Mem |
13342/// | 6 | Zmm, Zmm, Zmm |
13343/// +---+---------------+
13344/// ```
13345pub trait VpmulhwMaskEmitter<A, B, C> {
13346    fn vpmulhw_mask(&mut self, op0: A, op1: B, op2: C);
13347}
13348
13349impl<'a> VpmulhwMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
13350    fn vpmulhw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
13351        self.emit(
13352            VPMULHW128RRR_MASK,
13353            op0.as_operand(),
13354            op1.as_operand(),
13355            op2.as_operand(),
13356            &NOREG,
13357        );
13358    }
13359}
13360
13361impl<'a> VpmulhwMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
13362    fn vpmulhw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
13363        self.emit(
13364            VPMULHW128RRM_MASK,
13365            op0.as_operand(),
13366            op1.as_operand(),
13367            op2.as_operand(),
13368            &NOREG,
13369        );
13370    }
13371}
13372
13373impl<'a> VpmulhwMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
13374    fn vpmulhw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
13375        self.emit(
13376            VPMULHW256RRR_MASK,
13377            op0.as_operand(),
13378            op1.as_operand(),
13379            op2.as_operand(),
13380            &NOREG,
13381        );
13382    }
13383}
13384
13385impl<'a> VpmulhwMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
13386    fn vpmulhw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
13387        self.emit(
13388            VPMULHW256RRM_MASK,
13389            op0.as_operand(),
13390            op1.as_operand(),
13391            op2.as_operand(),
13392            &NOREG,
13393        );
13394    }
13395}
13396
13397impl<'a> VpmulhwMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
13398    fn vpmulhw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
13399        self.emit(
13400            VPMULHW512RRR_MASK,
13401            op0.as_operand(),
13402            op1.as_operand(),
13403            op2.as_operand(),
13404            &NOREG,
13405        );
13406    }
13407}
13408
13409impl<'a> VpmulhwMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
13410    fn vpmulhw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
13411        self.emit(
13412            VPMULHW512RRM_MASK,
13413            op0.as_operand(),
13414            op1.as_operand(),
13415            op2.as_operand(),
13416            &NOREG,
13417        );
13418    }
13419}
13420
13421/// `VPMULHW_MASKZ`.
13422///
13423/// Supported operand variants:
13424///
13425/// ```text
13426/// +---+---------------+
13427/// | # | Operands      |
13428/// +---+---------------+
13429/// | 1 | Xmm, Xmm, Mem |
13430/// | 2 | Xmm, Xmm, Xmm |
13431/// | 3 | Ymm, Ymm, Mem |
13432/// | 4 | Ymm, Ymm, Ymm |
13433/// | 5 | Zmm, Zmm, Mem |
13434/// | 6 | Zmm, Zmm, Zmm |
13435/// +---+---------------+
13436/// ```
13437pub trait VpmulhwMaskzEmitter<A, B, C> {
13438    fn vpmulhw_maskz(&mut self, op0: A, op1: B, op2: C);
13439}
13440
13441impl<'a> VpmulhwMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
13442    fn vpmulhw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
13443        self.emit(
13444            VPMULHW128RRR_MASKZ,
13445            op0.as_operand(),
13446            op1.as_operand(),
13447            op2.as_operand(),
13448            &NOREG,
13449        );
13450    }
13451}
13452
13453impl<'a> VpmulhwMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
13454    fn vpmulhw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
13455        self.emit(
13456            VPMULHW128RRM_MASKZ,
13457            op0.as_operand(),
13458            op1.as_operand(),
13459            op2.as_operand(),
13460            &NOREG,
13461        );
13462    }
13463}
13464
13465impl<'a> VpmulhwMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
13466    fn vpmulhw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
13467        self.emit(
13468            VPMULHW256RRR_MASKZ,
13469            op0.as_operand(),
13470            op1.as_operand(),
13471            op2.as_operand(),
13472            &NOREG,
13473        );
13474    }
13475}
13476
13477impl<'a> VpmulhwMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
13478    fn vpmulhw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
13479        self.emit(
13480            VPMULHW256RRM_MASKZ,
13481            op0.as_operand(),
13482            op1.as_operand(),
13483            op2.as_operand(),
13484            &NOREG,
13485        );
13486    }
13487}
13488
13489impl<'a> VpmulhwMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
13490    fn vpmulhw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
13491        self.emit(
13492            VPMULHW512RRR_MASKZ,
13493            op0.as_operand(),
13494            op1.as_operand(),
13495            op2.as_operand(),
13496            &NOREG,
13497        );
13498    }
13499}
13500
13501impl<'a> VpmulhwMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
13502    fn vpmulhw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
13503        self.emit(
13504            VPMULHW512RRM_MASKZ,
13505            op0.as_operand(),
13506            op1.as_operand(),
13507            op2.as_operand(),
13508            &NOREG,
13509        );
13510    }
13511}
13512
13513/// `VPMULLW`.
13514///
13515/// Supported operand variants:
13516///
13517/// ```text
13518/// +---+---------------+
13519/// | # | Operands      |
13520/// +---+---------------+
13521/// | 1 | Xmm, Xmm, Mem |
13522/// | 2 | Xmm, Xmm, Xmm |
13523/// | 3 | Ymm, Ymm, Mem |
13524/// | 4 | Ymm, Ymm, Ymm |
13525/// | 5 | Zmm, Zmm, Mem |
13526/// | 6 | Zmm, Zmm, Zmm |
13527/// +---+---------------+
13528/// ```
13529pub trait VpmullwEmitter<A, B, C> {
13530    fn vpmullw(&mut self, op0: A, op1: B, op2: C);
13531}
13532
13533impl<'a> VpmullwEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
13534    fn vpmullw(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
13535        self.emit(
13536            VPMULLW128RRR,
13537            op0.as_operand(),
13538            op1.as_operand(),
13539            op2.as_operand(),
13540            &NOREG,
13541        );
13542    }
13543}
13544
13545impl<'a> VpmullwEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
13546    fn vpmullw(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
13547        self.emit(
13548            VPMULLW128RRM,
13549            op0.as_operand(),
13550            op1.as_operand(),
13551            op2.as_operand(),
13552            &NOREG,
13553        );
13554    }
13555}
13556
13557impl<'a> VpmullwEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
13558    fn vpmullw(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
13559        self.emit(
13560            VPMULLW256RRR,
13561            op0.as_operand(),
13562            op1.as_operand(),
13563            op2.as_operand(),
13564            &NOREG,
13565        );
13566    }
13567}
13568
13569impl<'a> VpmullwEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
13570    fn vpmullw(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
13571        self.emit(
13572            VPMULLW256RRM,
13573            op0.as_operand(),
13574            op1.as_operand(),
13575            op2.as_operand(),
13576            &NOREG,
13577        );
13578    }
13579}
13580
13581impl<'a> VpmullwEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
13582    fn vpmullw(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
13583        self.emit(
13584            VPMULLW512RRR,
13585            op0.as_operand(),
13586            op1.as_operand(),
13587            op2.as_operand(),
13588            &NOREG,
13589        );
13590    }
13591}
13592
13593impl<'a> VpmullwEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
13594    fn vpmullw(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
13595        self.emit(
13596            VPMULLW512RRM,
13597            op0.as_operand(),
13598            op1.as_operand(),
13599            op2.as_operand(),
13600            &NOREG,
13601        );
13602    }
13603}
13604
13605/// `VPMULLW_MASK`.
13606///
13607/// Supported operand variants:
13608///
13609/// ```text
13610/// +---+---------------+
13611/// | # | Operands      |
13612/// +---+---------------+
13613/// | 1 | Xmm, Xmm, Mem |
13614/// | 2 | Xmm, Xmm, Xmm |
13615/// | 3 | Ymm, Ymm, Mem |
13616/// | 4 | Ymm, Ymm, Ymm |
13617/// | 5 | Zmm, Zmm, Mem |
13618/// | 6 | Zmm, Zmm, Zmm |
13619/// +---+---------------+
13620/// ```
13621pub trait VpmullwMaskEmitter<A, B, C> {
13622    fn vpmullw_mask(&mut self, op0: A, op1: B, op2: C);
13623}
13624
13625impl<'a> VpmullwMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
13626    fn vpmullw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
13627        self.emit(
13628            VPMULLW128RRR_MASK,
13629            op0.as_operand(),
13630            op1.as_operand(),
13631            op2.as_operand(),
13632            &NOREG,
13633        );
13634    }
13635}
13636
13637impl<'a> VpmullwMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
13638    fn vpmullw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
13639        self.emit(
13640            VPMULLW128RRM_MASK,
13641            op0.as_operand(),
13642            op1.as_operand(),
13643            op2.as_operand(),
13644            &NOREG,
13645        );
13646    }
13647}
13648
13649impl<'a> VpmullwMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
13650    fn vpmullw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
13651        self.emit(
13652            VPMULLW256RRR_MASK,
13653            op0.as_operand(),
13654            op1.as_operand(),
13655            op2.as_operand(),
13656            &NOREG,
13657        );
13658    }
13659}
13660
13661impl<'a> VpmullwMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
13662    fn vpmullw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
13663        self.emit(
13664            VPMULLW256RRM_MASK,
13665            op0.as_operand(),
13666            op1.as_operand(),
13667            op2.as_operand(),
13668            &NOREG,
13669        );
13670    }
13671}
13672
13673impl<'a> VpmullwMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
13674    fn vpmullw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
13675        self.emit(
13676            VPMULLW512RRR_MASK,
13677            op0.as_operand(),
13678            op1.as_operand(),
13679            op2.as_operand(),
13680            &NOREG,
13681        );
13682    }
13683}
13684
13685impl<'a> VpmullwMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
13686    fn vpmullw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
13687        self.emit(
13688            VPMULLW512RRM_MASK,
13689            op0.as_operand(),
13690            op1.as_operand(),
13691            op2.as_operand(),
13692            &NOREG,
13693        );
13694    }
13695}
13696
13697/// `VPMULLW_MASKZ`.
13698///
13699/// Supported operand variants:
13700///
13701/// ```text
13702/// +---+---------------+
13703/// | # | Operands      |
13704/// +---+---------------+
13705/// | 1 | Xmm, Xmm, Mem |
13706/// | 2 | Xmm, Xmm, Xmm |
13707/// | 3 | Ymm, Ymm, Mem |
13708/// | 4 | Ymm, Ymm, Ymm |
13709/// | 5 | Zmm, Zmm, Mem |
13710/// | 6 | Zmm, Zmm, Zmm |
13711/// +---+---------------+
13712/// ```
13713pub trait VpmullwMaskzEmitter<A, B, C> {
13714    fn vpmullw_maskz(&mut self, op0: A, op1: B, op2: C);
13715}
13716
13717impl<'a> VpmullwMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
13718    fn vpmullw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
13719        self.emit(
13720            VPMULLW128RRR_MASKZ,
13721            op0.as_operand(),
13722            op1.as_operand(),
13723            op2.as_operand(),
13724            &NOREG,
13725        );
13726    }
13727}
13728
13729impl<'a> VpmullwMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
13730    fn vpmullw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
13731        self.emit(
13732            VPMULLW128RRM_MASKZ,
13733            op0.as_operand(),
13734            op1.as_operand(),
13735            op2.as_operand(),
13736            &NOREG,
13737        );
13738    }
13739}
13740
13741impl<'a> VpmullwMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
13742    fn vpmullw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
13743        self.emit(
13744            VPMULLW256RRR_MASKZ,
13745            op0.as_operand(),
13746            op1.as_operand(),
13747            op2.as_operand(),
13748            &NOREG,
13749        );
13750    }
13751}
13752
13753impl<'a> VpmullwMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
13754    fn vpmullw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
13755        self.emit(
13756            VPMULLW256RRM_MASKZ,
13757            op0.as_operand(),
13758            op1.as_operand(),
13759            op2.as_operand(),
13760            &NOREG,
13761        );
13762    }
13763}
13764
13765impl<'a> VpmullwMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
13766    fn vpmullw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
13767        self.emit(
13768            VPMULLW512RRR_MASKZ,
13769            op0.as_operand(),
13770            op1.as_operand(),
13771            op2.as_operand(),
13772            &NOREG,
13773        );
13774    }
13775}
13776
13777impl<'a> VpmullwMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
13778    fn vpmullw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
13779        self.emit(
13780            VPMULLW512RRM_MASKZ,
13781            op0.as_operand(),
13782            op1.as_operand(),
13783            op2.as_operand(),
13784            &NOREG,
13785        );
13786    }
13787}
13788
13789/// `VPSADBW`.
13790///
13791/// Supported operand variants:
13792///
13793/// ```text
13794/// +---+---------------+
13795/// | # | Operands      |
13796/// +---+---------------+
13797/// | 1 | Xmm, Xmm, Mem |
13798/// | 2 | Xmm, Xmm, Xmm |
13799/// | 3 | Ymm, Ymm, Mem |
13800/// | 4 | Ymm, Ymm, Ymm |
13801/// | 5 | Zmm, Zmm, Mem |
13802/// | 6 | Zmm, Zmm, Zmm |
13803/// +---+---------------+
13804/// ```
13805pub trait VpsadbwEmitter<A, B, C> {
13806    fn vpsadbw(&mut self, op0: A, op1: B, op2: C);
13807}
13808
13809impl<'a> VpsadbwEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
13810    fn vpsadbw(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
13811        self.emit(
13812            VPSADBW128RRR,
13813            op0.as_operand(),
13814            op1.as_operand(),
13815            op2.as_operand(),
13816            &NOREG,
13817        );
13818    }
13819}
13820
13821impl<'a> VpsadbwEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
13822    fn vpsadbw(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
13823        self.emit(
13824            VPSADBW128RRM,
13825            op0.as_operand(),
13826            op1.as_operand(),
13827            op2.as_operand(),
13828            &NOREG,
13829        );
13830    }
13831}
13832
13833impl<'a> VpsadbwEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
13834    fn vpsadbw(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
13835        self.emit(
13836            VPSADBW256RRR,
13837            op0.as_operand(),
13838            op1.as_operand(),
13839            op2.as_operand(),
13840            &NOREG,
13841        );
13842    }
13843}
13844
13845impl<'a> VpsadbwEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
13846    fn vpsadbw(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
13847        self.emit(
13848            VPSADBW256RRM,
13849            op0.as_operand(),
13850            op1.as_operand(),
13851            op2.as_operand(),
13852            &NOREG,
13853        );
13854    }
13855}
13856
13857impl<'a> VpsadbwEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
13858    fn vpsadbw(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
13859        self.emit(
13860            VPSADBW512RRR,
13861            op0.as_operand(),
13862            op1.as_operand(),
13863            op2.as_operand(),
13864            &NOREG,
13865        );
13866    }
13867}
13868
13869impl<'a> VpsadbwEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
13870    fn vpsadbw(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
13871        self.emit(
13872            VPSADBW512RRM,
13873            op0.as_operand(),
13874            op1.as_operand(),
13875            op2.as_operand(),
13876            &NOREG,
13877        );
13878    }
13879}
13880
13881/// `VPSHUFB`.
13882///
13883/// Supported operand variants:
13884///
13885/// ```text
13886/// +---+---------------+
13887/// | # | Operands      |
13888/// +---+---------------+
13889/// | 1 | Xmm, Xmm, Mem |
13890/// | 2 | Xmm, Xmm, Xmm |
13891/// | 3 | Ymm, Ymm, Mem |
13892/// | 4 | Ymm, Ymm, Ymm |
13893/// | 5 | Zmm, Zmm, Mem |
13894/// | 6 | Zmm, Zmm, Zmm |
13895/// +---+---------------+
13896/// ```
13897pub trait VpshufbEmitter<A, B, C> {
13898    fn vpshufb(&mut self, op0: A, op1: B, op2: C);
13899}
13900
13901impl<'a> VpshufbEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
13902    fn vpshufb(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
13903        self.emit(
13904            VPSHUFB128RRR,
13905            op0.as_operand(),
13906            op1.as_operand(),
13907            op2.as_operand(),
13908            &NOREG,
13909        );
13910    }
13911}
13912
13913impl<'a> VpshufbEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
13914    fn vpshufb(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
13915        self.emit(
13916            VPSHUFB128RRM,
13917            op0.as_operand(),
13918            op1.as_operand(),
13919            op2.as_operand(),
13920            &NOREG,
13921        );
13922    }
13923}
13924
13925impl<'a> VpshufbEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
13926    fn vpshufb(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
13927        self.emit(
13928            VPSHUFB256RRR,
13929            op0.as_operand(),
13930            op1.as_operand(),
13931            op2.as_operand(),
13932            &NOREG,
13933        );
13934    }
13935}
13936
13937impl<'a> VpshufbEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
13938    fn vpshufb(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
13939        self.emit(
13940            VPSHUFB256RRM,
13941            op0.as_operand(),
13942            op1.as_operand(),
13943            op2.as_operand(),
13944            &NOREG,
13945        );
13946    }
13947}
13948
13949impl<'a> VpshufbEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
13950    fn vpshufb(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
13951        self.emit(
13952            VPSHUFB512RRR,
13953            op0.as_operand(),
13954            op1.as_operand(),
13955            op2.as_operand(),
13956            &NOREG,
13957        );
13958    }
13959}
13960
13961impl<'a> VpshufbEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
13962    fn vpshufb(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
13963        self.emit(
13964            VPSHUFB512RRM,
13965            op0.as_operand(),
13966            op1.as_operand(),
13967            op2.as_operand(),
13968            &NOREG,
13969        );
13970    }
13971}
13972
13973/// `VPSHUFB_MASK`.
13974///
13975/// Supported operand variants:
13976///
13977/// ```text
13978/// +---+---------------+
13979/// | # | Operands      |
13980/// +---+---------------+
13981/// | 1 | Xmm, Xmm, Mem |
13982/// | 2 | Xmm, Xmm, Xmm |
13983/// | 3 | Ymm, Ymm, Mem |
13984/// | 4 | Ymm, Ymm, Ymm |
13985/// | 5 | Zmm, Zmm, Mem |
13986/// | 6 | Zmm, Zmm, Zmm |
13987/// +---+---------------+
13988/// ```
13989pub trait VpshufbMaskEmitter<A, B, C> {
13990    fn vpshufb_mask(&mut self, op0: A, op1: B, op2: C);
13991}
13992
13993impl<'a> VpshufbMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
13994    fn vpshufb_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
13995        self.emit(
13996            VPSHUFB128RRR_MASK,
13997            op0.as_operand(),
13998            op1.as_operand(),
13999            op2.as_operand(),
14000            &NOREG,
14001        );
14002    }
14003}
14004
14005impl<'a> VpshufbMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
14006    fn vpshufb_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
14007        self.emit(
14008            VPSHUFB128RRM_MASK,
14009            op0.as_operand(),
14010            op1.as_operand(),
14011            op2.as_operand(),
14012            &NOREG,
14013        );
14014    }
14015}
14016
14017impl<'a> VpshufbMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
14018    fn vpshufb_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
14019        self.emit(
14020            VPSHUFB256RRR_MASK,
14021            op0.as_operand(),
14022            op1.as_operand(),
14023            op2.as_operand(),
14024            &NOREG,
14025        );
14026    }
14027}
14028
14029impl<'a> VpshufbMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
14030    fn vpshufb_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
14031        self.emit(
14032            VPSHUFB256RRM_MASK,
14033            op0.as_operand(),
14034            op1.as_operand(),
14035            op2.as_operand(),
14036            &NOREG,
14037        );
14038    }
14039}
14040
14041impl<'a> VpshufbMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
14042    fn vpshufb_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
14043        self.emit(
14044            VPSHUFB512RRR_MASK,
14045            op0.as_operand(),
14046            op1.as_operand(),
14047            op2.as_operand(),
14048            &NOREG,
14049        );
14050    }
14051}
14052
14053impl<'a> VpshufbMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
14054    fn vpshufb_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
14055        self.emit(
14056            VPSHUFB512RRM_MASK,
14057            op0.as_operand(),
14058            op1.as_operand(),
14059            op2.as_operand(),
14060            &NOREG,
14061        );
14062    }
14063}
14064
14065/// `VPSHUFB_MASKZ`.
14066///
14067/// Supported operand variants:
14068///
14069/// ```text
14070/// +---+---------------+
14071/// | # | Operands      |
14072/// +---+---------------+
14073/// | 1 | Xmm, Xmm, Mem |
14074/// | 2 | Xmm, Xmm, Xmm |
14075/// | 3 | Ymm, Ymm, Mem |
14076/// | 4 | Ymm, Ymm, Ymm |
14077/// | 5 | Zmm, Zmm, Mem |
14078/// | 6 | Zmm, Zmm, Zmm |
14079/// +---+---------------+
14080/// ```
14081pub trait VpshufbMaskzEmitter<A, B, C> {
14082    fn vpshufb_maskz(&mut self, op0: A, op1: B, op2: C);
14083}
14084
14085impl<'a> VpshufbMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
14086    fn vpshufb_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
14087        self.emit(
14088            VPSHUFB128RRR_MASKZ,
14089            op0.as_operand(),
14090            op1.as_operand(),
14091            op2.as_operand(),
14092            &NOREG,
14093        );
14094    }
14095}
14096
14097impl<'a> VpshufbMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
14098    fn vpshufb_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
14099        self.emit(
14100            VPSHUFB128RRM_MASKZ,
14101            op0.as_operand(),
14102            op1.as_operand(),
14103            op2.as_operand(),
14104            &NOREG,
14105        );
14106    }
14107}
14108
14109impl<'a> VpshufbMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
14110    fn vpshufb_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
14111        self.emit(
14112            VPSHUFB256RRR_MASKZ,
14113            op0.as_operand(),
14114            op1.as_operand(),
14115            op2.as_operand(),
14116            &NOREG,
14117        );
14118    }
14119}
14120
14121impl<'a> VpshufbMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
14122    fn vpshufb_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
14123        self.emit(
14124            VPSHUFB256RRM_MASKZ,
14125            op0.as_operand(),
14126            op1.as_operand(),
14127            op2.as_operand(),
14128            &NOREG,
14129        );
14130    }
14131}
14132
14133impl<'a> VpshufbMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
14134    fn vpshufb_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
14135        self.emit(
14136            VPSHUFB512RRR_MASKZ,
14137            op0.as_operand(),
14138            op1.as_operand(),
14139            op2.as_operand(),
14140            &NOREG,
14141        );
14142    }
14143}
14144
14145impl<'a> VpshufbMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
14146    fn vpshufb_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
14147        self.emit(
14148            VPSHUFB512RRM_MASKZ,
14149            op0.as_operand(),
14150            op1.as_operand(),
14151            op2.as_operand(),
14152            &NOREG,
14153        );
14154    }
14155}
14156
14157/// `VPSHUFHW`.
14158///
14159/// Supported operand variants:
14160///
14161/// ```text
14162/// +---+---------------+
14163/// | # | Operands      |
14164/// +---+---------------+
14165/// | 1 | Xmm, Mem, Imm |
14166/// | 2 | Xmm, Xmm, Imm |
14167/// | 3 | Ymm, Mem, Imm |
14168/// | 4 | Ymm, Ymm, Imm |
14169/// | 5 | Zmm, Mem, Imm |
14170/// | 6 | Zmm, Zmm, Imm |
14171/// +---+---------------+
14172/// ```
14173pub trait VpshufhwEmitter<A, B, C> {
14174    fn vpshufhw(&mut self, op0: A, op1: B, op2: C);
14175}
14176
14177impl<'a> VpshufhwEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
14178    fn vpshufhw(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
14179        self.emit(
14180            VPSHUFHW128RRI,
14181            op0.as_operand(),
14182            op1.as_operand(),
14183            op2.as_operand(),
14184            &NOREG,
14185        );
14186    }
14187}
14188
14189impl<'a> VpshufhwEmitter<Xmm, Mem, Imm> for Assembler<'a> {
14190    fn vpshufhw(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
14191        self.emit(
14192            VPSHUFHW128RMI,
14193            op0.as_operand(),
14194            op1.as_operand(),
14195            op2.as_operand(),
14196            &NOREG,
14197        );
14198    }
14199}
14200
14201impl<'a> VpshufhwEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
14202    fn vpshufhw(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
14203        self.emit(
14204            VPSHUFHW256RRI,
14205            op0.as_operand(),
14206            op1.as_operand(),
14207            op2.as_operand(),
14208            &NOREG,
14209        );
14210    }
14211}
14212
14213impl<'a> VpshufhwEmitter<Ymm, Mem, Imm> for Assembler<'a> {
14214    fn vpshufhw(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
14215        self.emit(
14216            VPSHUFHW256RMI,
14217            op0.as_operand(),
14218            op1.as_operand(),
14219            op2.as_operand(),
14220            &NOREG,
14221        );
14222    }
14223}
14224
14225impl<'a> VpshufhwEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
14226    fn vpshufhw(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
14227        self.emit(
14228            VPSHUFHW512RRI,
14229            op0.as_operand(),
14230            op1.as_operand(),
14231            op2.as_operand(),
14232            &NOREG,
14233        );
14234    }
14235}
14236
14237impl<'a> VpshufhwEmitter<Zmm, Mem, Imm> for Assembler<'a> {
14238    fn vpshufhw(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
14239        self.emit(
14240            VPSHUFHW512RMI,
14241            op0.as_operand(),
14242            op1.as_operand(),
14243            op2.as_operand(),
14244            &NOREG,
14245        );
14246    }
14247}
14248
14249/// `VPSHUFHW_MASK`.
14250///
14251/// Supported operand variants:
14252///
14253/// ```text
14254/// +---+---------------+
14255/// | # | Operands      |
14256/// +---+---------------+
14257/// | 1 | Xmm, Mem, Imm |
14258/// | 2 | Xmm, Xmm, Imm |
14259/// | 3 | Ymm, Mem, Imm |
14260/// | 4 | Ymm, Ymm, Imm |
14261/// | 5 | Zmm, Mem, Imm |
14262/// | 6 | Zmm, Zmm, Imm |
14263/// +---+---------------+
14264/// ```
14265pub trait VpshufhwMaskEmitter<A, B, C> {
14266    fn vpshufhw_mask(&mut self, op0: A, op1: B, op2: C);
14267}
14268
14269impl<'a> VpshufhwMaskEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
14270    fn vpshufhw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
14271        self.emit(
14272            VPSHUFHW128RRI_MASK,
14273            op0.as_operand(),
14274            op1.as_operand(),
14275            op2.as_operand(),
14276            &NOREG,
14277        );
14278    }
14279}
14280
14281impl<'a> VpshufhwMaskEmitter<Xmm, Mem, Imm> for Assembler<'a> {
14282    fn vpshufhw_mask(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
14283        self.emit(
14284            VPSHUFHW128RMI_MASK,
14285            op0.as_operand(),
14286            op1.as_operand(),
14287            op2.as_operand(),
14288            &NOREG,
14289        );
14290    }
14291}
14292
14293impl<'a> VpshufhwMaskEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
14294    fn vpshufhw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
14295        self.emit(
14296            VPSHUFHW256RRI_MASK,
14297            op0.as_operand(),
14298            op1.as_operand(),
14299            op2.as_operand(),
14300            &NOREG,
14301        );
14302    }
14303}
14304
14305impl<'a> VpshufhwMaskEmitter<Ymm, Mem, Imm> for Assembler<'a> {
14306    fn vpshufhw_mask(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
14307        self.emit(
14308            VPSHUFHW256RMI_MASK,
14309            op0.as_operand(),
14310            op1.as_operand(),
14311            op2.as_operand(),
14312            &NOREG,
14313        );
14314    }
14315}
14316
14317impl<'a> VpshufhwMaskEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
14318    fn vpshufhw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
14319        self.emit(
14320            VPSHUFHW512RRI_MASK,
14321            op0.as_operand(),
14322            op1.as_operand(),
14323            op2.as_operand(),
14324            &NOREG,
14325        );
14326    }
14327}
14328
14329impl<'a> VpshufhwMaskEmitter<Zmm, Mem, Imm> for Assembler<'a> {
14330    fn vpshufhw_mask(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
14331        self.emit(
14332            VPSHUFHW512RMI_MASK,
14333            op0.as_operand(),
14334            op1.as_operand(),
14335            op2.as_operand(),
14336            &NOREG,
14337        );
14338    }
14339}
14340
14341/// `VPSHUFHW_MASKZ`.
14342///
14343/// Supported operand variants:
14344///
14345/// ```text
14346/// +---+---------------+
14347/// | # | Operands      |
14348/// +---+---------------+
14349/// | 1 | Xmm, Mem, Imm |
14350/// | 2 | Xmm, Xmm, Imm |
14351/// | 3 | Ymm, Mem, Imm |
14352/// | 4 | Ymm, Ymm, Imm |
14353/// | 5 | Zmm, Mem, Imm |
14354/// | 6 | Zmm, Zmm, Imm |
14355/// +---+---------------+
14356/// ```
14357pub trait VpshufhwMaskzEmitter<A, B, C> {
14358    fn vpshufhw_maskz(&mut self, op0: A, op1: B, op2: C);
14359}
14360
14361impl<'a> VpshufhwMaskzEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
14362    fn vpshufhw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
14363        self.emit(
14364            VPSHUFHW128RRI_MASKZ,
14365            op0.as_operand(),
14366            op1.as_operand(),
14367            op2.as_operand(),
14368            &NOREG,
14369        );
14370    }
14371}
14372
14373impl<'a> VpshufhwMaskzEmitter<Xmm, Mem, Imm> for Assembler<'a> {
14374    fn vpshufhw_maskz(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
14375        self.emit(
14376            VPSHUFHW128RMI_MASKZ,
14377            op0.as_operand(),
14378            op1.as_operand(),
14379            op2.as_operand(),
14380            &NOREG,
14381        );
14382    }
14383}
14384
14385impl<'a> VpshufhwMaskzEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
14386    fn vpshufhw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
14387        self.emit(
14388            VPSHUFHW256RRI_MASKZ,
14389            op0.as_operand(),
14390            op1.as_operand(),
14391            op2.as_operand(),
14392            &NOREG,
14393        );
14394    }
14395}
14396
14397impl<'a> VpshufhwMaskzEmitter<Ymm, Mem, Imm> for Assembler<'a> {
14398    fn vpshufhw_maskz(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
14399        self.emit(
14400            VPSHUFHW256RMI_MASKZ,
14401            op0.as_operand(),
14402            op1.as_operand(),
14403            op2.as_operand(),
14404            &NOREG,
14405        );
14406    }
14407}
14408
14409impl<'a> VpshufhwMaskzEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
14410    fn vpshufhw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
14411        self.emit(
14412            VPSHUFHW512RRI_MASKZ,
14413            op0.as_operand(),
14414            op1.as_operand(),
14415            op2.as_operand(),
14416            &NOREG,
14417        );
14418    }
14419}
14420
14421impl<'a> VpshufhwMaskzEmitter<Zmm, Mem, Imm> for Assembler<'a> {
14422    fn vpshufhw_maskz(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
14423        self.emit(
14424            VPSHUFHW512RMI_MASKZ,
14425            op0.as_operand(),
14426            op1.as_operand(),
14427            op2.as_operand(),
14428            &NOREG,
14429        );
14430    }
14431}
14432
14433/// `VPSHUFLW`.
14434///
14435/// Supported operand variants:
14436///
14437/// ```text
14438/// +---+---------------+
14439/// | # | Operands      |
14440/// +---+---------------+
14441/// | 1 | Xmm, Mem, Imm |
14442/// | 2 | Xmm, Xmm, Imm |
14443/// | 3 | Ymm, Mem, Imm |
14444/// | 4 | Ymm, Ymm, Imm |
14445/// | 5 | Zmm, Mem, Imm |
14446/// | 6 | Zmm, Zmm, Imm |
14447/// +---+---------------+
14448/// ```
14449pub trait VpshuflwEmitter<A, B, C> {
14450    fn vpshuflw(&mut self, op0: A, op1: B, op2: C);
14451}
14452
14453impl<'a> VpshuflwEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
14454    fn vpshuflw(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
14455        self.emit(
14456            VPSHUFLW128RRI,
14457            op0.as_operand(),
14458            op1.as_operand(),
14459            op2.as_operand(),
14460            &NOREG,
14461        );
14462    }
14463}
14464
14465impl<'a> VpshuflwEmitter<Xmm, Mem, Imm> for Assembler<'a> {
14466    fn vpshuflw(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
14467        self.emit(
14468            VPSHUFLW128RMI,
14469            op0.as_operand(),
14470            op1.as_operand(),
14471            op2.as_operand(),
14472            &NOREG,
14473        );
14474    }
14475}
14476
14477impl<'a> VpshuflwEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
14478    fn vpshuflw(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
14479        self.emit(
14480            VPSHUFLW256RRI,
14481            op0.as_operand(),
14482            op1.as_operand(),
14483            op2.as_operand(),
14484            &NOREG,
14485        );
14486    }
14487}
14488
14489impl<'a> VpshuflwEmitter<Ymm, Mem, Imm> for Assembler<'a> {
14490    fn vpshuflw(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
14491        self.emit(
14492            VPSHUFLW256RMI,
14493            op0.as_operand(),
14494            op1.as_operand(),
14495            op2.as_operand(),
14496            &NOREG,
14497        );
14498    }
14499}
14500
14501impl<'a> VpshuflwEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
14502    fn vpshuflw(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
14503        self.emit(
14504            VPSHUFLW512RRI,
14505            op0.as_operand(),
14506            op1.as_operand(),
14507            op2.as_operand(),
14508            &NOREG,
14509        );
14510    }
14511}
14512
14513impl<'a> VpshuflwEmitter<Zmm, Mem, Imm> for Assembler<'a> {
14514    fn vpshuflw(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
14515        self.emit(
14516            VPSHUFLW512RMI,
14517            op0.as_operand(),
14518            op1.as_operand(),
14519            op2.as_operand(),
14520            &NOREG,
14521        );
14522    }
14523}
14524
14525/// `VPSHUFLW_MASK`.
14526///
14527/// Supported operand variants:
14528///
14529/// ```text
14530/// +---+---------------+
14531/// | # | Operands      |
14532/// +---+---------------+
14533/// | 1 | Xmm, Mem, Imm |
14534/// | 2 | Xmm, Xmm, Imm |
14535/// | 3 | Ymm, Mem, Imm |
14536/// | 4 | Ymm, Ymm, Imm |
14537/// | 5 | Zmm, Mem, Imm |
14538/// | 6 | Zmm, Zmm, Imm |
14539/// +---+---------------+
14540/// ```
14541pub trait VpshuflwMaskEmitter<A, B, C> {
14542    fn vpshuflw_mask(&mut self, op0: A, op1: B, op2: C);
14543}
14544
14545impl<'a> VpshuflwMaskEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
14546    fn vpshuflw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
14547        self.emit(
14548            VPSHUFLW128RRI_MASK,
14549            op0.as_operand(),
14550            op1.as_operand(),
14551            op2.as_operand(),
14552            &NOREG,
14553        );
14554    }
14555}
14556
14557impl<'a> VpshuflwMaskEmitter<Xmm, Mem, Imm> for Assembler<'a> {
14558    fn vpshuflw_mask(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
14559        self.emit(
14560            VPSHUFLW128RMI_MASK,
14561            op0.as_operand(),
14562            op1.as_operand(),
14563            op2.as_operand(),
14564            &NOREG,
14565        );
14566    }
14567}
14568
14569impl<'a> VpshuflwMaskEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
14570    fn vpshuflw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
14571        self.emit(
14572            VPSHUFLW256RRI_MASK,
14573            op0.as_operand(),
14574            op1.as_operand(),
14575            op2.as_operand(),
14576            &NOREG,
14577        );
14578    }
14579}
14580
14581impl<'a> VpshuflwMaskEmitter<Ymm, Mem, Imm> for Assembler<'a> {
14582    fn vpshuflw_mask(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
14583        self.emit(
14584            VPSHUFLW256RMI_MASK,
14585            op0.as_operand(),
14586            op1.as_operand(),
14587            op2.as_operand(),
14588            &NOREG,
14589        );
14590    }
14591}
14592
14593impl<'a> VpshuflwMaskEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
14594    fn vpshuflw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
14595        self.emit(
14596            VPSHUFLW512RRI_MASK,
14597            op0.as_operand(),
14598            op1.as_operand(),
14599            op2.as_operand(),
14600            &NOREG,
14601        );
14602    }
14603}
14604
14605impl<'a> VpshuflwMaskEmitter<Zmm, Mem, Imm> for Assembler<'a> {
14606    fn vpshuflw_mask(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
14607        self.emit(
14608            VPSHUFLW512RMI_MASK,
14609            op0.as_operand(),
14610            op1.as_operand(),
14611            op2.as_operand(),
14612            &NOREG,
14613        );
14614    }
14615}
14616
14617/// `VPSHUFLW_MASKZ`.
14618///
14619/// Supported operand variants:
14620///
14621/// ```text
14622/// +---+---------------+
14623/// | # | Operands      |
14624/// +---+---------------+
14625/// | 1 | Xmm, Mem, Imm |
14626/// | 2 | Xmm, Xmm, Imm |
14627/// | 3 | Ymm, Mem, Imm |
14628/// | 4 | Ymm, Ymm, Imm |
14629/// | 5 | Zmm, Mem, Imm |
14630/// | 6 | Zmm, Zmm, Imm |
14631/// +---+---------------+
14632/// ```
14633pub trait VpshuflwMaskzEmitter<A, B, C> {
14634    fn vpshuflw_maskz(&mut self, op0: A, op1: B, op2: C);
14635}
14636
14637impl<'a> VpshuflwMaskzEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
14638    fn vpshuflw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
14639        self.emit(
14640            VPSHUFLW128RRI_MASKZ,
14641            op0.as_operand(),
14642            op1.as_operand(),
14643            op2.as_operand(),
14644            &NOREG,
14645        );
14646    }
14647}
14648
14649impl<'a> VpshuflwMaskzEmitter<Xmm, Mem, Imm> for Assembler<'a> {
14650    fn vpshuflw_maskz(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
14651        self.emit(
14652            VPSHUFLW128RMI_MASKZ,
14653            op0.as_operand(),
14654            op1.as_operand(),
14655            op2.as_operand(),
14656            &NOREG,
14657        );
14658    }
14659}
14660
14661impl<'a> VpshuflwMaskzEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
14662    fn vpshuflw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
14663        self.emit(
14664            VPSHUFLW256RRI_MASKZ,
14665            op0.as_operand(),
14666            op1.as_operand(),
14667            op2.as_operand(),
14668            &NOREG,
14669        );
14670    }
14671}
14672
14673impl<'a> VpshuflwMaskzEmitter<Ymm, Mem, Imm> for Assembler<'a> {
14674    fn vpshuflw_maskz(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
14675        self.emit(
14676            VPSHUFLW256RMI_MASKZ,
14677            op0.as_operand(),
14678            op1.as_operand(),
14679            op2.as_operand(),
14680            &NOREG,
14681        );
14682    }
14683}
14684
14685impl<'a> VpshuflwMaskzEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
14686    fn vpshuflw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
14687        self.emit(
14688            VPSHUFLW512RRI_MASKZ,
14689            op0.as_operand(),
14690            op1.as_operand(),
14691            op2.as_operand(),
14692            &NOREG,
14693        );
14694    }
14695}
14696
14697impl<'a> VpshuflwMaskzEmitter<Zmm, Mem, Imm> for Assembler<'a> {
14698    fn vpshuflw_maskz(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
14699        self.emit(
14700            VPSHUFLW512RMI_MASKZ,
14701            op0.as_operand(),
14702            op1.as_operand(),
14703            op2.as_operand(),
14704            &NOREG,
14705        );
14706    }
14707}
14708
14709/// `VPSLLDQ`.
14710///
14711/// Supported operand variants:
14712///
14713/// ```text
14714/// +---+---------------+
14715/// | # | Operands      |
14716/// +---+---------------+
14717/// | 1 | Xmm, Mem, Imm |
14718/// | 2 | Xmm, Xmm, Imm |
14719/// | 3 | Ymm, Mem, Imm |
14720/// | 4 | Ymm, Ymm, Imm |
14721/// | 5 | Zmm, Mem, Imm |
14722/// | 6 | Zmm, Zmm, Imm |
14723/// +---+---------------+
14724/// ```
14725pub trait VpslldqEmitter<A, B, C> {
14726    fn vpslldq(&mut self, op0: A, op1: B, op2: C);
14727}
14728
14729impl<'a> VpslldqEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
14730    fn vpslldq(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
14731        self.emit(
14732            VPSLLDQ128RRI,
14733            op0.as_operand(),
14734            op1.as_operand(),
14735            op2.as_operand(),
14736            &NOREG,
14737        );
14738    }
14739}
14740
14741impl<'a> VpslldqEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
14742    fn vpslldq(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
14743        self.emit(
14744            VPSLLDQ256RRI,
14745            op0.as_operand(),
14746            op1.as_operand(),
14747            op2.as_operand(),
14748            &NOREG,
14749        );
14750    }
14751}
14752
14753impl<'a> VpslldqEmitter<Xmm, Mem, Imm> for Assembler<'a> {
14754    fn vpslldq(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
14755        self.emit(
14756            VPSLLDQ128RMI,
14757            op0.as_operand(),
14758            op1.as_operand(),
14759            op2.as_operand(),
14760            &NOREG,
14761        );
14762    }
14763}
14764
14765impl<'a> VpslldqEmitter<Ymm, Mem, Imm> for Assembler<'a> {
14766    fn vpslldq(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
14767        self.emit(
14768            VPSLLDQ256RMI,
14769            op0.as_operand(),
14770            op1.as_operand(),
14771            op2.as_operand(),
14772            &NOREG,
14773        );
14774    }
14775}
14776
14777impl<'a> VpslldqEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
14778    fn vpslldq(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
14779        self.emit(
14780            VPSLLDQ512RRI,
14781            op0.as_operand(),
14782            op1.as_operand(),
14783            op2.as_operand(),
14784            &NOREG,
14785        );
14786    }
14787}
14788
14789impl<'a> VpslldqEmitter<Zmm, Mem, Imm> for Assembler<'a> {
14790    fn vpslldq(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
14791        self.emit(
14792            VPSLLDQ512RMI,
14793            op0.as_operand(),
14794            op1.as_operand(),
14795            op2.as_operand(),
14796            &NOREG,
14797        );
14798    }
14799}
14800
14801/// `VPSLLVW`.
14802///
14803/// Supported operand variants:
14804///
14805/// ```text
14806/// +---+---------------+
14807/// | # | Operands      |
14808/// +---+---------------+
14809/// | 1 | Xmm, Xmm, Mem |
14810/// | 2 | Xmm, Xmm, Xmm |
14811/// | 3 | Ymm, Ymm, Mem |
14812/// | 4 | Ymm, Ymm, Ymm |
14813/// | 5 | Zmm, Zmm, Mem |
14814/// | 6 | Zmm, Zmm, Zmm |
14815/// +---+---------------+
14816/// ```
14817pub trait VpsllvwEmitter<A, B, C> {
14818    fn vpsllvw(&mut self, op0: A, op1: B, op2: C);
14819}
14820
14821impl<'a> VpsllvwEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
14822    fn vpsllvw(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
14823        self.emit(
14824            VPSLLVW128RRR,
14825            op0.as_operand(),
14826            op1.as_operand(),
14827            op2.as_operand(),
14828            &NOREG,
14829        );
14830    }
14831}
14832
14833impl<'a> VpsllvwEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
14834    fn vpsllvw(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
14835        self.emit(
14836            VPSLLVW128RRM,
14837            op0.as_operand(),
14838            op1.as_operand(),
14839            op2.as_operand(),
14840            &NOREG,
14841        );
14842    }
14843}
14844
14845impl<'a> VpsllvwEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
14846    fn vpsllvw(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
14847        self.emit(
14848            VPSLLVW256RRR,
14849            op0.as_operand(),
14850            op1.as_operand(),
14851            op2.as_operand(),
14852            &NOREG,
14853        );
14854    }
14855}
14856
14857impl<'a> VpsllvwEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
14858    fn vpsllvw(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
14859        self.emit(
14860            VPSLLVW256RRM,
14861            op0.as_operand(),
14862            op1.as_operand(),
14863            op2.as_operand(),
14864            &NOREG,
14865        );
14866    }
14867}
14868
14869impl<'a> VpsllvwEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
14870    fn vpsllvw(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
14871        self.emit(
14872            VPSLLVW512RRR,
14873            op0.as_operand(),
14874            op1.as_operand(),
14875            op2.as_operand(),
14876            &NOREG,
14877        );
14878    }
14879}
14880
14881impl<'a> VpsllvwEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
14882    fn vpsllvw(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
14883        self.emit(
14884            VPSLLVW512RRM,
14885            op0.as_operand(),
14886            op1.as_operand(),
14887            op2.as_operand(),
14888            &NOREG,
14889        );
14890    }
14891}
14892
14893/// `VPSLLVW_MASK`.
14894///
14895/// Supported operand variants:
14896///
14897/// ```text
14898/// +---+---------------+
14899/// | # | Operands      |
14900/// +---+---------------+
14901/// | 1 | Xmm, Xmm, Mem |
14902/// | 2 | Xmm, Xmm, Xmm |
14903/// | 3 | Ymm, Ymm, Mem |
14904/// | 4 | Ymm, Ymm, Ymm |
14905/// | 5 | Zmm, Zmm, Mem |
14906/// | 6 | Zmm, Zmm, Zmm |
14907/// +---+---------------+
14908/// ```
14909pub trait VpsllvwMaskEmitter<A, B, C> {
14910    fn vpsllvw_mask(&mut self, op0: A, op1: B, op2: C);
14911}
14912
14913impl<'a> VpsllvwMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
14914    fn vpsllvw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
14915        self.emit(
14916            VPSLLVW128RRR_MASK,
14917            op0.as_operand(),
14918            op1.as_operand(),
14919            op2.as_operand(),
14920            &NOREG,
14921        );
14922    }
14923}
14924
14925impl<'a> VpsllvwMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
14926    fn vpsllvw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
14927        self.emit(
14928            VPSLLVW128RRM_MASK,
14929            op0.as_operand(),
14930            op1.as_operand(),
14931            op2.as_operand(),
14932            &NOREG,
14933        );
14934    }
14935}
14936
14937impl<'a> VpsllvwMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
14938    fn vpsllvw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
14939        self.emit(
14940            VPSLLVW256RRR_MASK,
14941            op0.as_operand(),
14942            op1.as_operand(),
14943            op2.as_operand(),
14944            &NOREG,
14945        );
14946    }
14947}
14948
14949impl<'a> VpsllvwMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
14950    fn vpsllvw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
14951        self.emit(
14952            VPSLLVW256RRM_MASK,
14953            op0.as_operand(),
14954            op1.as_operand(),
14955            op2.as_operand(),
14956            &NOREG,
14957        );
14958    }
14959}
14960
14961impl<'a> VpsllvwMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
14962    fn vpsllvw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
14963        self.emit(
14964            VPSLLVW512RRR_MASK,
14965            op0.as_operand(),
14966            op1.as_operand(),
14967            op2.as_operand(),
14968            &NOREG,
14969        );
14970    }
14971}
14972
14973impl<'a> VpsllvwMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
14974    fn vpsllvw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
14975        self.emit(
14976            VPSLLVW512RRM_MASK,
14977            op0.as_operand(),
14978            op1.as_operand(),
14979            op2.as_operand(),
14980            &NOREG,
14981        );
14982    }
14983}
14984
14985/// `VPSLLVW_MASKZ`.
14986///
14987/// Supported operand variants:
14988///
14989/// ```text
14990/// +---+---------------+
14991/// | # | Operands      |
14992/// +---+---------------+
14993/// | 1 | Xmm, Xmm, Mem |
14994/// | 2 | Xmm, Xmm, Xmm |
14995/// | 3 | Ymm, Ymm, Mem |
14996/// | 4 | Ymm, Ymm, Ymm |
14997/// | 5 | Zmm, Zmm, Mem |
14998/// | 6 | Zmm, Zmm, Zmm |
14999/// +---+---------------+
15000/// ```
15001pub trait VpsllvwMaskzEmitter<A, B, C> {
15002    fn vpsllvw_maskz(&mut self, op0: A, op1: B, op2: C);
15003}
15004
15005impl<'a> VpsllvwMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
15006    fn vpsllvw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
15007        self.emit(
15008            VPSLLVW128RRR_MASKZ,
15009            op0.as_operand(),
15010            op1.as_operand(),
15011            op2.as_operand(),
15012            &NOREG,
15013        );
15014    }
15015}
15016
15017impl<'a> VpsllvwMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
15018    fn vpsllvw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
15019        self.emit(
15020            VPSLLVW128RRM_MASKZ,
15021            op0.as_operand(),
15022            op1.as_operand(),
15023            op2.as_operand(),
15024            &NOREG,
15025        );
15026    }
15027}
15028
15029impl<'a> VpsllvwMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
15030    fn vpsllvw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
15031        self.emit(
15032            VPSLLVW256RRR_MASKZ,
15033            op0.as_operand(),
15034            op1.as_operand(),
15035            op2.as_operand(),
15036            &NOREG,
15037        );
15038    }
15039}
15040
15041impl<'a> VpsllvwMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
15042    fn vpsllvw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
15043        self.emit(
15044            VPSLLVW256RRM_MASKZ,
15045            op0.as_operand(),
15046            op1.as_operand(),
15047            op2.as_operand(),
15048            &NOREG,
15049        );
15050    }
15051}
15052
15053impl<'a> VpsllvwMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
15054    fn vpsllvw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
15055        self.emit(
15056            VPSLLVW512RRR_MASKZ,
15057            op0.as_operand(),
15058            op1.as_operand(),
15059            op2.as_operand(),
15060            &NOREG,
15061        );
15062    }
15063}
15064
15065impl<'a> VpsllvwMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
15066    fn vpsllvw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
15067        self.emit(
15068            VPSLLVW512RRM_MASKZ,
15069            op0.as_operand(),
15070            op1.as_operand(),
15071            op2.as_operand(),
15072            &NOREG,
15073        );
15074    }
15075}
15076
15077/// `VPSLLW`.
15078///
15079/// Supported operand variants:
15080///
15081/// ```text
15082/// +----+---------------+
15083/// | #  | Operands      |
15084/// +----+---------------+
15085/// | 1  | Xmm, Mem, Imm |
15086/// | 2  | Xmm, Xmm, Imm |
15087/// | 3  | Xmm, Xmm, Mem |
15088/// | 4  | Xmm, Xmm, Xmm |
15089/// | 5  | Ymm, Mem, Imm |
15090/// | 6  | Ymm, Ymm, Imm |
15091/// | 7  | Ymm, Ymm, Mem |
15092/// | 8  | Ymm, Ymm, Xmm |
15093/// | 9  | Zmm, Mem, Imm |
15094/// | 10 | Zmm, Zmm, Imm |
15095/// | 11 | Zmm, Zmm, Mem |
15096/// | 12 | Zmm, Zmm, Xmm |
15097/// +----+---------------+
15098/// ```
15099pub trait VpsllwEmitter<A, B, C> {
15100    fn vpsllw(&mut self, op0: A, op1: B, op2: C);
15101}
15102
15103impl<'a> VpsllwEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
15104    fn vpsllw(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
15105        self.emit(
15106            VPSLLW128RRI,
15107            op0.as_operand(),
15108            op1.as_operand(),
15109            op2.as_operand(),
15110            &NOREG,
15111        );
15112    }
15113}
15114
15115impl<'a> VpsllwEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
15116    fn vpsllw(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
15117        self.emit(
15118            VPSLLW256RRI,
15119            op0.as_operand(),
15120            op1.as_operand(),
15121            op2.as_operand(),
15122            &NOREG,
15123        );
15124    }
15125}
15126
15127impl<'a> VpsllwEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
15128    fn vpsllw(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
15129        self.emit(
15130            VPSLLW128RRR,
15131            op0.as_operand(),
15132            op1.as_operand(),
15133            op2.as_operand(),
15134            &NOREG,
15135        );
15136    }
15137}
15138
15139impl<'a> VpsllwEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
15140    fn vpsllw(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
15141        self.emit(
15142            VPSLLW128RRM,
15143            op0.as_operand(),
15144            op1.as_operand(),
15145            op2.as_operand(),
15146            &NOREG,
15147        );
15148    }
15149}
15150
15151impl<'a> VpsllwEmitter<Ymm, Ymm, Xmm> for Assembler<'a> {
15152    fn vpsllw(&mut self, op0: Ymm, op1: Ymm, op2: Xmm) {
15153        self.emit(
15154            VPSLLW256RRR,
15155            op0.as_operand(),
15156            op1.as_operand(),
15157            op2.as_operand(),
15158            &NOREG,
15159        );
15160    }
15161}
15162
15163impl<'a> VpsllwEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
15164    fn vpsllw(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
15165        self.emit(
15166            VPSLLW256RRM,
15167            op0.as_operand(),
15168            op1.as_operand(),
15169            op2.as_operand(),
15170            &NOREG,
15171        );
15172    }
15173}
15174
15175impl<'a> VpsllwEmitter<Xmm, Mem, Imm> for Assembler<'a> {
15176    fn vpsllw(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
15177        self.emit(
15178            VPSLLW128RMI,
15179            op0.as_operand(),
15180            op1.as_operand(),
15181            op2.as_operand(),
15182            &NOREG,
15183        );
15184    }
15185}
15186
15187impl<'a> VpsllwEmitter<Ymm, Mem, Imm> for Assembler<'a> {
15188    fn vpsllw(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
15189        self.emit(
15190            VPSLLW256RMI,
15191            op0.as_operand(),
15192            op1.as_operand(),
15193            op2.as_operand(),
15194            &NOREG,
15195        );
15196    }
15197}
15198
15199impl<'a> VpsllwEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
15200    fn vpsllw(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
15201        self.emit(
15202            VPSLLW512RRI,
15203            op0.as_operand(),
15204            op1.as_operand(),
15205            op2.as_operand(),
15206            &NOREG,
15207        );
15208    }
15209}
15210
15211impl<'a> VpsllwEmitter<Zmm, Mem, Imm> for Assembler<'a> {
15212    fn vpsllw(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
15213        self.emit(
15214            VPSLLW512RMI,
15215            op0.as_operand(),
15216            op1.as_operand(),
15217            op2.as_operand(),
15218            &NOREG,
15219        );
15220    }
15221}
15222
15223impl<'a> VpsllwEmitter<Zmm, Zmm, Xmm> for Assembler<'a> {
15224    fn vpsllw(&mut self, op0: Zmm, op1: Zmm, op2: Xmm) {
15225        self.emit(
15226            VPSLLW512RRR,
15227            op0.as_operand(),
15228            op1.as_operand(),
15229            op2.as_operand(),
15230            &NOREG,
15231        );
15232    }
15233}
15234
15235impl<'a> VpsllwEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
15236    fn vpsllw(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
15237        self.emit(
15238            VPSLLW512RRM,
15239            op0.as_operand(),
15240            op1.as_operand(),
15241            op2.as_operand(),
15242            &NOREG,
15243        );
15244    }
15245}
15246
15247/// `VPSLLW_MASK`.
15248///
15249/// Supported operand variants:
15250///
15251/// ```text
15252/// +----+---------------+
15253/// | #  | Operands      |
15254/// +----+---------------+
15255/// | 1  | Xmm, Mem, Imm |
15256/// | 2  | Xmm, Xmm, Imm |
15257/// | 3  | Xmm, Xmm, Mem |
15258/// | 4  | Xmm, Xmm, Xmm |
15259/// | 5  | Ymm, Mem, Imm |
15260/// | 6  | Ymm, Ymm, Imm |
15261/// | 7  | Ymm, Ymm, Mem |
15262/// | 8  | Ymm, Ymm, Xmm |
15263/// | 9  | Zmm, Mem, Imm |
15264/// | 10 | Zmm, Zmm, Imm |
15265/// | 11 | Zmm, Zmm, Mem |
15266/// | 12 | Zmm, Zmm, Xmm |
15267/// +----+---------------+
15268/// ```
15269pub trait VpsllwMaskEmitter<A, B, C> {
15270    fn vpsllw_mask(&mut self, op0: A, op1: B, op2: C);
15271}
15272
15273impl<'a> VpsllwMaskEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
15274    fn vpsllw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
15275        self.emit(
15276            VPSLLW128RRI_MASK,
15277            op0.as_operand(),
15278            op1.as_operand(),
15279            op2.as_operand(),
15280            &NOREG,
15281        );
15282    }
15283}
15284
15285impl<'a> VpsllwMaskEmitter<Xmm, Mem, Imm> for Assembler<'a> {
15286    fn vpsllw_mask(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
15287        self.emit(
15288            VPSLLW128RMI_MASK,
15289            op0.as_operand(),
15290            op1.as_operand(),
15291            op2.as_operand(),
15292            &NOREG,
15293        );
15294    }
15295}
15296
15297impl<'a> VpsllwMaskEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
15298    fn vpsllw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
15299        self.emit(
15300            VPSLLW256RRI_MASK,
15301            op0.as_operand(),
15302            op1.as_operand(),
15303            op2.as_operand(),
15304            &NOREG,
15305        );
15306    }
15307}
15308
15309impl<'a> VpsllwMaskEmitter<Ymm, Mem, Imm> for Assembler<'a> {
15310    fn vpsllw_mask(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
15311        self.emit(
15312            VPSLLW256RMI_MASK,
15313            op0.as_operand(),
15314            op1.as_operand(),
15315            op2.as_operand(),
15316            &NOREG,
15317        );
15318    }
15319}
15320
15321impl<'a> VpsllwMaskEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
15322    fn vpsllw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
15323        self.emit(
15324            VPSLLW512RRI_MASK,
15325            op0.as_operand(),
15326            op1.as_operand(),
15327            op2.as_operand(),
15328            &NOREG,
15329        );
15330    }
15331}
15332
15333impl<'a> VpsllwMaskEmitter<Zmm, Mem, Imm> for Assembler<'a> {
15334    fn vpsllw_mask(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
15335        self.emit(
15336            VPSLLW512RMI_MASK,
15337            op0.as_operand(),
15338            op1.as_operand(),
15339            op2.as_operand(),
15340            &NOREG,
15341        );
15342    }
15343}
15344
15345impl<'a> VpsllwMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
15346    fn vpsllw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
15347        self.emit(
15348            VPSLLW128RRR_MASK,
15349            op0.as_operand(),
15350            op1.as_operand(),
15351            op2.as_operand(),
15352            &NOREG,
15353        );
15354    }
15355}
15356
15357impl<'a> VpsllwMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
15358    fn vpsllw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
15359        self.emit(
15360            VPSLLW128RRM_MASK,
15361            op0.as_operand(),
15362            op1.as_operand(),
15363            op2.as_operand(),
15364            &NOREG,
15365        );
15366    }
15367}
15368
15369impl<'a> VpsllwMaskEmitter<Ymm, Ymm, Xmm> for Assembler<'a> {
15370    fn vpsllw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Xmm) {
15371        self.emit(
15372            VPSLLW256RRR_MASK,
15373            op0.as_operand(),
15374            op1.as_operand(),
15375            op2.as_operand(),
15376            &NOREG,
15377        );
15378    }
15379}
15380
15381impl<'a> VpsllwMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
15382    fn vpsllw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
15383        self.emit(
15384            VPSLLW256RRM_MASK,
15385            op0.as_operand(),
15386            op1.as_operand(),
15387            op2.as_operand(),
15388            &NOREG,
15389        );
15390    }
15391}
15392
15393impl<'a> VpsllwMaskEmitter<Zmm, Zmm, Xmm> for Assembler<'a> {
15394    fn vpsllw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Xmm) {
15395        self.emit(
15396            VPSLLW512RRR_MASK,
15397            op0.as_operand(),
15398            op1.as_operand(),
15399            op2.as_operand(),
15400            &NOREG,
15401        );
15402    }
15403}
15404
15405impl<'a> VpsllwMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
15406    fn vpsllw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
15407        self.emit(
15408            VPSLLW512RRM_MASK,
15409            op0.as_operand(),
15410            op1.as_operand(),
15411            op2.as_operand(),
15412            &NOREG,
15413        );
15414    }
15415}
15416
15417/// `VPSLLW_MASKZ`.
15418///
15419/// Supported operand variants:
15420///
15421/// ```text
15422/// +----+---------------+
15423/// | #  | Operands      |
15424/// +----+---------------+
15425/// | 1  | Xmm, Mem, Imm |
15426/// | 2  | Xmm, Xmm, Imm |
15427/// | 3  | Xmm, Xmm, Mem |
15428/// | 4  | Xmm, Xmm, Xmm |
15429/// | 5  | Ymm, Mem, Imm |
15430/// | 6  | Ymm, Ymm, Imm |
15431/// | 7  | Ymm, Ymm, Mem |
15432/// | 8  | Ymm, Ymm, Xmm |
15433/// | 9  | Zmm, Mem, Imm |
15434/// | 10 | Zmm, Zmm, Imm |
15435/// | 11 | Zmm, Zmm, Mem |
15436/// | 12 | Zmm, Zmm, Xmm |
15437/// +----+---------------+
15438/// ```
15439pub trait VpsllwMaskzEmitter<A, B, C> {
15440    fn vpsllw_maskz(&mut self, op0: A, op1: B, op2: C);
15441}
15442
15443impl<'a> VpsllwMaskzEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
15444    fn vpsllw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
15445        self.emit(
15446            VPSLLW128RRI_MASKZ,
15447            op0.as_operand(),
15448            op1.as_operand(),
15449            op2.as_operand(),
15450            &NOREG,
15451        );
15452    }
15453}
15454
15455impl<'a> VpsllwMaskzEmitter<Xmm, Mem, Imm> for Assembler<'a> {
15456    fn vpsllw_maskz(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
15457        self.emit(
15458            VPSLLW128RMI_MASKZ,
15459            op0.as_operand(),
15460            op1.as_operand(),
15461            op2.as_operand(),
15462            &NOREG,
15463        );
15464    }
15465}
15466
15467impl<'a> VpsllwMaskzEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
15468    fn vpsllw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
15469        self.emit(
15470            VPSLLW256RRI_MASKZ,
15471            op0.as_operand(),
15472            op1.as_operand(),
15473            op2.as_operand(),
15474            &NOREG,
15475        );
15476    }
15477}
15478
15479impl<'a> VpsllwMaskzEmitter<Ymm, Mem, Imm> for Assembler<'a> {
15480    fn vpsllw_maskz(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
15481        self.emit(
15482            VPSLLW256RMI_MASKZ,
15483            op0.as_operand(),
15484            op1.as_operand(),
15485            op2.as_operand(),
15486            &NOREG,
15487        );
15488    }
15489}
15490
15491impl<'a> VpsllwMaskzEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
15492    fn vpsllw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
15493        self.emit(
15494            VPSLLW512RRI_MASKZ,
15495            op0.as_operand(),
15496            op1.as_operand(),
15497            op2.as_operand(),
15498            &NOREG,
15499        );
15500    }
15501}
15502
15503impl<'a> VpsllwMaskzEmitter<Zmm, Mem, Imm> for Assembler<'a> {
15504    fn vpsllw_maskz(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
15505        self.emit(
15506            VPSLLW512RMI_MASKZ,
15507            op0.as_operand(),
15508            op1.as_operand(),
15509            op2.as_operand(),
15510            &NOREG,
15511        );
15512    }
15513}
15514
15515impl<'a> VpsllwMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
15516    fn vpsllw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
15517        self.emit(
15518            VPSLLW128RRR_MASKZ,
15519            op0.as_operand(),
15520            op1.as_operand(),
15521            op2.as_operand(),
15522            &NOREG,
15523        );
15524    }
15525}
15526
15527impl<'a> VpsllwMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
15528    fn vpsllw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
15529        self.emit(
15530            VPSLLW128RRM_MASKZ,
15531            op0.as_operand(),
15532            op1.as_operand(),
15533            op2.as_operand(),
15534            &NOREG,
15535        );
15536    }
15537}
15538
15539impl<'a> VpsllwMaskzEmitter<Ymm, Ymm, Xmm> for Assembler<'a> {
15540    fn vpsllw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Xmm) {
15541        self.emit(
15542            VPSLLW256RRR_MASKZ,
15543            op0.as_operand(),
15544            op1.as_operand(),
15545            op2.as_operand(),
15546            &NOREG,
15547        );
15548    }
15549}
15550
15551impl<'a> VpsllwMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
15552    fn vpsllw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
15553        self.emit(
15554            VPSLLW256RRM_MASKZ,
15555            op0.as_operand(),
15556            op1.as_operand(),
15557            op2.as_operand(),
15558            &NOREG,
15559        );
15560    }
15561}
15562
15563impl<'a> VpsllwMaskzEmitter<Zmm, Zmm, Xmm> for Assembler<'a> {
15564    fn vpsllw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Xmm) {
15565        self.emit(
15566            VPSLLW512RRR_MASKZ,
15567            op0.as_operand(),
15568            op1.as_operand(),
15569            op2.as_operand(),
15570            &NOREG,
15571        );
15572    }
15573}
15574
15575impl<'a> VpsllwMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
15576    fn vpsllw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
15577        self.emit(
15578            VPSLLW512RRM_MASKZ,
15579            op0.as_operand(),
15580            op1.as_operand(),
15581            op2.as_operand(),
15582            &NOREG,
15583        );
15584    }
15585}
15586
15587/// `VPSRAVW`.
15588///
15589/// Supported operand variants:
15590///
15591/// ```text
15592/// +---+---------------+
15593/// | # | Operands      |
15594/// +---+---------------+
15595/// | 1 | Xmm, Xmm, Mem |
15596/// | 2 | Xmm, Xmm, Xmm |
15597/// | 3 | Ymm, Ymm, Mem |
15598/// | 4 | Ymm, Ymm, Ymm |
15599/// | 5 | Zmm, Zmm, Mem |
15600/// | 6 | Zmm, Zmm, Zmm |
15601/// +---+---------------+
15602/// ```
15603pub trait VpsravwEmitter<A, B, C> {
15604    fn vpsravw(&mut self, op0: A, op1: B, op2: C);
15605}
15606
15607impl<'a> VpsravwEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
15608    fn vpsravw(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
15609        self.emit(
15610            VPSRAVW128RRR,
15611            op0.as_operand(),
15612            op1.as_operand(),
15613            op2.as_operand(),
15614            &NOREG,
15615        );
15616    }
15617}
15618
15619impl<'a> VpsravwEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
15620    fn vpsravw(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
15621        self.emit(
15622            VPSRAVW128RRM,
15623            op0.as_operand(),
15624            op1.as_operand(),
15625            op2.as_operand(),
15626            &NOREG,
15627        );
15628    }
15629}
15630
15631impl<'a> VpsravwEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
15632    fn vpsravw(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
15633        self.emit(
15634            VPSRAVW256RRR,
15635            op0.as_operand(),
15636            op1.as_operand(),
15637            op2.as_operand(),
15638            &NOREG,
15639        );
15640    }
15641}
15642
15643impl<'a> VpsravwEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
15644    fn vpsravw(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
15645        self.emit(
15646            VPSRAVW256RRM,
15647            op0.as_operand(),
15648            op1.as_operand(),
15649            op2.as_operand(),
15650            &NOREG,
15651        );
15652    }
15653}
15654
15655impl<'a> VpsravwEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
15656    fn vpsravw(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
15657        self.emit(
15658            VPSRAVW512RRR,
15659            op0.as_operand(),
15660            op1.as_operand(),
15661            op2.as_operand(),
15662            &NOREG,
15663        );
15664    }
15665}
15666
15667impl<'a> VpsravwEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
15668    fn vpsravw(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
15669        self.emit(
15670            VPSRAVW512RRM,
15671            op0.as_operand(),
15672            op1.as_operand(),
15673            op2.as_operand(),
15674            &NOREG,
15675        );
15676    }
15677}
15678
15679/// `VPSRAVW_MASK`.
15680///
15681/// Supported operand variants:
15682///
15683/// ```text
15684/// +---+---------------+
15685/// | # | Operands      |
15686/// +---+---------------+
15687/// | 1 | Xmm, Xmm, Mem |
15688/// | 2 | Xmm, Xmm, Xmm |
15689/// | 3 | Ymm, Ymm, Mem |
15690/// | 4 | Ymm, Ymm, Ymm |
15691/// | 5 | Zmm, Zmm, Mem |
15692/// | 6 | Zmm, Zmm, Zmm |
15693/// +---+---------------+
15694/// ```
15695pub trait VpsravwMaskEmitter<A, B, C> {
15696    fn vpsravw_mask(&mut self, op0: A, op1: B, op2: C);
15697}
15698
15699impl<'a> VpsravwMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
15700    fn vpsravw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
15701        self.emit(
15702            VPSRAVW128RRR_MASK,
15703            op0.as_operand(),
15704            op1.as_operand(),
15705            op2.as_operand(),
15706            &NOREG,
15707        );
15708    }
15709}
15710
15711impl<'a> VpsravwMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
15712    fn vpsravw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
15713        self.emit(
15714            VPSRAVW128RRM_MASK,
15715            op0.as_operand(),
15716            op1.as_operand(),
15717            op2.as_operand(),
15718            &NOREG,
15719        );
15720    }
15721}
15722
15723impl<'a> VpsravwMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
15724    fn vpsravw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
15725        self.emit(
15726            VPSRAVW256RRR_MASK,
15727            op0.as_operand(),
15728            op1.as_operand(),
15729            op2.as_operand(),
15730            &NOREG,
15731        );
15732    }
15733}
15734
15735impl<'a> VpsravwMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
15736    fn vpsravw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
15737        self.emit(
15738            VPSRAVW256RRM_MASK,
15739            op0.as_operand(),
15740            op1.as_operand(),
15741            op2.as_operand(),
15742            &NOREG,
15743        );
15744    }
15745}
15746
15747impl<'a> VpsravwMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
15748    fn vpsravw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
15749        self.emit(
15750            VPSRAVW512RRR_MASK,
15751            op0.as_operand(),
15752            op1.as_operand(),
15753            op2.as_operand(),
15754            &NOREG,
15755        );
15756    }
15757}
15758
15759impl<'a> VpsravwMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
15760    fn vpsravw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
15761        self.emit(
15762            VPSRAVW512RRM_MASK,
15763            op0.as_operand(),
15764            op1.as_operand(),
15765            op2.as_operand(),
15766            &NOREG,
15767        );
15768    }
15769}
15770
15771/// `VPSRAVW_MASKZ`.
15772///
15773/// Supported operand variants:
15774///
15775/// ```text
15776/// +---+---------------+
15777/// | # | Operands      |
15778/// +---+---------------+
15779/// | 1 | Xmm, Xmm, Mem |
15780/// | 2 | Xmm, Xmm, Xmm |
15781/// | 3 | Ymm, Ymm, Mem |
15782/// | 4 | Ymm, Ymm, Ymm |
15783/// | 5 | Zmm, Zmm, Mem |
15784/// | 6 | Zmm, Zmm, Zmm |
15785/// +---+---------------+
15786/// ```
15787pub trait VpsravwMaskzEmitter<A, B, C> {
15788    fn vpsravw_maskz(&mut self, op0: A, op1: B, op2: C);
15789}
15790
15791impl<'a> VpsravwMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
15792    fn vpsravw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
15793        self.emit(
15794            VPSRAVW128RRR_MASKZ,
15795            op0.as_operand(),
15796            op1.as_operand(),
15797            op2.as_operand(),
15798            &NOREG,
15799        );
15800    }
15801}
15802
15803impl<'a> VpsravwMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
15804    fn vpsravw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
15805        self.emit(
15806            VPSRAVW128RRM_MASKZ,
15807            op0.as_operand(),
15808            op1.as_operand(),
15809            op2.as_operand(),
15810            &NOREG,
15811        );
15812    }
15813}
15814
15815impl<'a> VpsravwMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
15816    fn vpsravw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
15817        self.emit(
15818            VPSRAVW256RRR_MASKZ,
15819            op0.as_operand(),
15820            op1.as_operand(),
15821            op2.as_operand(),
15822            &NOREG,
15823        );
15824    }
15825}
15826
15827impl<'a> VpsravwMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
15828    fn vpsravw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
15829        self.emit(
15830            VPSRAVW256RRM_MASKZ,
15831            op0.as_operand(),
15832            op1.as_operand(),
15833            op2.as_operand(),
15834            &NOREG,
15835        );
15836    }
15837}
15838
15839impl<'a> VpsravwMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
15840    fn vpsravw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
15841        self.emit(
15842            VPSRAVW512RRR_MASKZ,
15843            op0.as_operand(),
15844            op1.as_operand(),
15845            op2.as_operand(),
15846            &NOREG,
15847        );
15848    }
15849}
15850
15851impl<'a> VpsravwMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
15852    fn vpsravw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
15853        self.emit(
15854            VPSRAVW512RRM_MASKZ,
15855            op0.as_operand(),
15856            op1.as_operand(),
15857            op2.as_operand(),
15858            &NOREG,
15859        );
15860    }
15861}
15862
15863/// `VPSRAW`.
15864///
15865/// Supported operand variants:
15866///
15867/// ```text
15868/// +----+---------------+
15869/// | #  | Operands      |
15870/// +----+---------------+
15871/// | 1  | Xmm, Mem, Imm |
15872/// | 2  | Xmm, Xmm, Imm |
15873/// | 3  | Xmm, Xmm, Mem |
15874/// | 4  | Xmm, Xmm, Xmm |
15875/// | 5  | Ymm, Mem, Imm |
15876/// | 6  | Ymm, Ymm, Imm |
15877/// | 7  | Ymm, Ymm, Mem |
15878/// | 8  | Ymm, Ymm, Xmm |
15879/// | 9  | Zmm, Mem, Imm |
15880/// | 10 | Zmm, Zmm, Imm |
15881/// | 11 | Zmm, Zmm, Mem |
15882/// | 12 | Zmm, Zmm, Xmm |
15883/// +----+---------------+
15884/// ```
15885pub trait VpsrawEmitter<A, B, C> {
15886    fn vpsraw(&mut self, op0: A, op1: B, op2: C);
15887}
15888
15889impl<'a> VpsrawEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
15890    fn vpsraw(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
15891        self.emit(
15892            VPSRAW128RRI,
15893            op0.as_operand(),
15894            op1.as_operand(),
15895            op2.as_operand(),
15896            &NOREG,
15897        );
15898    }
15899}
15900
15901impl<'a> VpsrawEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
15902    fn vpsraw(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
15903        self.emit(
15904            VPSRAW256RRI,
15905            op0.as_operand(),
15906            op1.as_operand(),
15907            op2.as_operand(),
15908            &NOREG,
15909        );
15910    }
15911}
15912
15913impl<'a> VpsrawEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
15914    fn vpsraw(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
15915        self.emit(
15916            VPSRAW128RRR,
15917            op0.as_operand(),
15918            op1.as_operand(),
15919            op2.as_operand(),
15920            &NOREG,
15921        );
15922    }
15923}
15924
15925impl<'a> VpsrawEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
15926    fn vpsraw(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
15927        self.emit(
15928            VPSRAW128RRM,
15929            op0.as_operand(),
15930            op1.as_operand(),
15931            op2.as_operand(),
15932            &NOREG,
15933        );
15934    }
15935}
15936
15937impl<'a> VpsrawEmitter<Ymm, Ymm, Xmm> for Assembler<'a> {
15938    fn vpsraw(&mut self, op0: Ymm, op1: Ymm, op2: Xmm) {
15939        self.emit(
15940            VPSRAW256RRR,
15941            op0.as_operand(),
15942            op1.as_operand(),
15943            op2.as_operand(),
15944            &NOREG,
15945        );
15946    }
15947}
15948
15949impl<'a> VpsrawEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
15950    fn vpsraw(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
15951        self.emit(
15952            VPSRAW256RRM,
15953            op0.as_operand(),
15954            op1.as_operand(),
15955            op2.as_operand(),
15956            &NOREG,
15957        );
15958    }
15959}
15960
15961impl<'a> VpsrawEmitter<Xmm, Mem, Imm> for Assembler<'a> {
15962    fn vpsraw(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
15963        self.emit(
15964            VPSRAW128RMI,
15965            op0.as_operand(),
15966            op1.as_operand(),
15967            op2.as_operand(),
15968            &NOREG,
15969        );
15970    }
15971}
15972
15973impl<'a> VpsrawEmitter<Ymm, Mem, Imm> for Assembler<'a> {
15974    fn vpsraw(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
15975        self.emit(
15976            VPSRAW256RMI,
15977            op0.as_operand(),
15978            op1.as_operand(),
15979            op2.as_operand(),
15980            &NOREG,
15981        );
15982    }
15983}
15984
15985impl<'a> VpsrawEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
15986    fn vpsraw(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
15987        self.emit(
15988            VPSRAW512RRI,
15989            op0.as_operand(),
15990            op1.as_operand(),
15991            op2.as_operand(),
15992            &NOREG,
15993        );
15994    }
15995}
15996
15997impl<'a> VpsrawEmitter<Zmm, Mem, Imm> for Assembler<'a> {
15998    fn vpsraw(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
15999        self.emit(
16000            VPSRAW512RMI,
16001            op0.as_operand(),
16002            op1.as_operand(),
16003            op2.as_operand(),
16004            &NOREG,
16005        );
16006    }
16007}
16008
16009impl<'a> VpsrawEmitter<Zmm, Zmm, Xmm> for Assembler<'a> {
16010    fn vpsraw(&mut self, op0: Zmm, op1: Zmm, op2: Xmm) {
16011        self.emit(
16012            VPSRAW512RRR,
16013            op0.as_operand(),
16014            op1.as_operand(),
16015            op2.as_operand(),
16016            &NOREG,
16017        );
16018    }
16019}
16020
16021impl<'a> VpsrawEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
16022    fn vpsraw(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
16023        self.emit(
16024            VPSRAW512RRM,
16025            op0.as_operand(),
16026            op1.as_operand(),
16027            op2.as_operand(),
16028            &NOREG,
16029        );
16030    }
16031}
16032
16033/// `VPSRAW_MASK`.
16034///
16035/// Supported operand variants:
16036///
16037/// ```text
16038/// +----+---------------+
16039/// | #  | Operands      |
16040/// +----+---------------+
16041/// | 1  | Xmm, Mem, Imm |
16042/// | 2  | Xmm, Xmm, Imm |
16043/// | 3  | Xmm, Xmm, Mem |
16044/// | 4  | Xmm, Xmm, Xmm |
16045/// | 5  | Ymm, Mem, Imm |
16046/// | 6  | Ymm, Ymm, Imm |
16047/// | 7  | Ymm, Ymm, Mem |
16048/// | 8  | Ymm, Ymm, Xmm |
16049/// | 9  | Zmm, Mem, Imm |
16050/// | 10 | Zmm, Zmm, Imm |
16051/// | 11 | Zmm, Zmm, Mem |
16052/// | 12 | Zmm, Zmm, Xmm |
16053/// +----+---------------+
16054/// ```
16055pub trait VpsrawMaskEmitter<A, B, C> {
16056    fn vpsraw_mask(&mut self, op0: A, op1: B, op2: C);
16057}
16058
16059impl<'a> VpsrawMaskEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
16060    fn vpsraw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
16061        self.emit(
16062            VPSRAW128RRI_MASK,
16063            op0.as_operand(),
16064            op1.as_operand(),
16065            op2.as_operand(),
16066            &NOREG,
16067        );
16068    }
16069}
16070
16071impl<'a> VpsrawMaskEmitter<Xmm, Mem, Imm> for Assembler<'a> {
16072    fn vpsraw_mask(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
16073        self.emit(
16074            VPSRAW128RMI_MASK,
16075            op0.as_operand(),
16076            op1.as_operand(),
16077            op2.as_operand(),
16078            &NOREG,
16079        );
16080    }
16081}
16082
16083impl<'a> VpsrawMaskEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
16084    fn vpsraw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
16085        self.emit(
16086            VPSRAW256RRI_MASK,
16087            op0.as_operand(),
16088            op1.as_operand(),
16089            op2.as_operand(),
16090            &NOREG,
16091        );
16092    }
16093}
16094
16095impl<'a> VpsrawMaskEmitter<Ymm, Mem, Imm> for Assembler<'a> {
16096    fn vpsraw_mask(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
16097        self.emit(
16098            VPSRAW256RMI_MASK,
16099            op0.as_operand(),
16100            op1.as_operand(),
16101            op2.as_operand(),
16102            &NOREG,
16103        );
16104    }
16105}
16106
16107impl<'a> VpsrawMaskEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
16108    fn vpsraw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
16109        self.emit(
16110            VPSRAW512RRI_MASK,
16111            op0.as_operand(),
16112            op1.as_operand(),
16113            op2.as_operand(),
16114            &NOREG,
16115        );
16116    }
16117}
16118
16119impl<'a> VpsrawMaskEmitter<Zmm, Mem, Imm> for Assembler<'a> {
16120    fn vpsraw_mask(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
16121        self.emit(
16122            VPSRAW512RMI_MASK,
16123            op0.as_operand(),
16124            op1.as_operand(),
16125            op2.as_operand(),
16126            &NOREG,
16127        );
16128    }
16129}
16130
16131impl<'a> VpsrawMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
16132    fn vpsraw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
16133        self.emit(
16134            VPSRAW128RRR_MASK,
16135            op0.as_operand(),
16136            op1.as_operand(),
16137            op2.as_operand(),
16138            &NOREG,
16139        );
16140    }
16141}
16142
16143impl<'a> VpsrawMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
16144    fn vpsraw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
16145        self.emit(
16146            VPSRAW128RRM_MASK,
16147            op0.as_operand(),
16148            op1.as_operand(),
16149            op2.as_operand(),
16150            &NOREG,
16151        );
16152    }
16153}
16154
16155impl<'a> VpsrawMaskEmitter<Ymm, Ymm, Xmm> for Assembler<'a> {
16156    fn vpsraw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Xmm) {
16157        self.emit(
16158            VPSRAW256RRR_MASK,
16159            op0.as_operand(),
16160            op1.as_operand(),
16161            op2.as_operand(),
16162            &NOREG,
16163        );
16164    }
16165}
16166
16167impl<'a> VpsrawMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
16168    fn vpsraw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
16169        self.emit(
16170            VPSRAW256RRM_MASK,
16171            op0.as_operand(),
16172            op1.as_operand(),
16173            op2.as_operand(),
16174            &NOREG,
16175        );
16176    }
16177}
16178
16179impl<'a> VpsrawMaskEmitter<Zmm, Zmm, Xmm> for Assembler<'a> {
16180    fn vpsraw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Xmm) {
16181        self.emit(
16182            VPSRAW512RRR_MASK,
16183            op0.as_operand(),
16184            op1.as_operand(),
16185            op2.as_operand(),
16186            &NOREG,
16187        );
16188    }
16189}
16190
16191impl<'a> VpsrawMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
16192    fn vpsraw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
16193        self.emit(
16194            VPSRAW512RRM_MASK,
16195            op0.as_operand(),
16196            op1.as_operand(),
16197            op2.as_operand(),
16198            &NOREG,
16199        );
16200    }
16201}
16202
16203/// `VPSRAW_MASKZ`.
16204///
16205/// Supported operand variants:
16206///
16207/// ```text
16208/// +----+---------------+
16209/// | #  | Operands      |
16210/// +----+---------------+
16211/// | 1  | Xmm, Mem, Imm |
16212/// | 2  | Xmm, Xmm, Imm |
16213/// | 3  | Xmm, Xmm, Mem |
16214/// | 4  | Xmm, Xmm, Xmm |
16215/// | 5  | Ymm, Mem, Imm |
16216/// | 6  | Ymm, Ymm, Imm |
16217/// | 7  | Ymm, Ymm, Mem |
16218/// | 8  | Ymm, Ymm, Xmm |
16219/// | 9  | Zmm, Mem, Imm |
16220/// | 10 | Zmm, Zmm, Imm |
16221/// | 11 | Zmm, Zmm, Mem |
16222/// | 12 | Zmm, Zmm, Xmm |
16223/// +----+---------------+
16224/// ```
16225pub trait VpsrawMaskzEmitter<A, B, C> {
16226    fn vpsraw_maskz(&mut self, op0: A, op1: B, op2: C);
16227}
16228
16229impl<'a> VpsrawMaskzEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
16230    fn vpsraw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
16231        self.emit(
16232            VPSRAW128RRI_MASKZ,
16233            op0.as_operand(),
16234            op1.as_operand(),
16235            op2.as_operand(),
16236            &NOREG,
16237        );
16238    }
16239}
16240
16241impl<'a> VpsrawMaskzEmitter<Xmm, Mem, Imm> for Assembler<'a> {
16242    fn vpsraw_maskz(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
16243        self.emit(
16244            VPSRAW128RMI_MASKZ,
16245            op0.as_operand(),
16246            op1.as_operand(),
16247            op2.as_operand(),
16248            &NOREG,
16249        );
16250    }
16251}
16252
16253impl<'a> VpsrawMaskzEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
16254    fn vpsraw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
16255        self.emit(
16256            VPSRAW256RRI_MASKZ,
16257            op0.as_operand(),
16258            op1.as_operand(),
16259            op2.as_operand(),
16260            &NOREG,
16261        );
16262    }
16263}
16264
16265impl<'a> VpsrawMaskzEmitter<Ymm, Mem, Imm> for Assembler<'a> {
16266    fn vpsraw_maskz(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
16267        self.emit(
16268            VPSRAW256RMI_MASKZ,
16269            op0.as_operand(),
16270            op1.as_operand(),
16271            op2.as_operand(),
16272            &NOREG,
16273        );
16274    }
16275}
16276
16277impl<'a> VpsrawMaskzEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
16278    fn vpsraw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
16279        self.emit(
16280            VPSRAW512RRI_MASKZ,
16281            op0.as_operand(),
16282            op1.as_operand(),
16283            op2.as_operand(),
16284            &NOREG,
16285        );
16286    }
16287}
16288
16289impl<'a> VpsrawMaskzEmitter<Zmm, Mem, Imm> for Assembler<'a> {
16290    fn vpsraw_maskz(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
16291        self.emit(
16292            VPSRAW512RMI_MASKZ,
16293            op0.as_operand(),
16294            op1.as_operand(),
16295            op2.as_operand(),
16296            &NOREG,
16297        );
16298    }
16299}
16300
16301impl<'a> VpsrawMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
16302    fn vpsraw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
16303        self.emit(
16304            VPSRAW128RRR_MASKZ,
16305            op0.as_operand(),
16306            op1.as_operand(),
16307            op2.as_operand(),
16308            &NOREG,
16309        );
16310    }
16311}
16312
16313impl<'a> VpsrawMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
16314    fn vpsraw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
16315        self.emit(
16316            VPSRAW128RRM_MASKZ,
16317            op0.as_operand(),
16318            op1.as_operand(),
16319            op2.as_operand(),
16320            &NOREG,
16321        );
16322    }
16323}
16324
16325impl<'a> VpsrawMaskzEmitter<Ymm, Ymm, Xmm> for Assembler<'a> {
16326    fn vpsraw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Xmm) {
16327        self.emit(
16328            VPSRAW256RRR_MASKZ,
16329            op0.as_operand(),
16330            op1.as_operand(),
16331            op2.as_operand(),
16332            &NOREG,
16333        );
16334    }
16335}
16336
16337impl<'a> VpsrawMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
16338    fn vpsraw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
16339        self.emit(
16340            VPSRAW256RRM_MASKZ,
16341            op0.as_operand(),
16342            op1.as_operand(),
16343            op2.as_operand(),
16344            &NOREG,
16345        );
16346    }
16347}
16348
16349impl<'a> VpsrawMaskzEmitter<Zmm, Zmm, Xmm> for Assembler<'a> {
16350    fn vpsraw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Xmm) {
16351        self.emit(
16352            VPSRAW512RRR_MASKZ,
16353            op0.as_operand(),
16354            op1.as_operand(),
16355            op2.as_operand(),
16356            &NOREG,
16357        );
16358    }
16359}
16360
16361impl<'a> VpsrawMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
16362    fn vpsraw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
16363        self.emit(
16364            VPSRAW512RRM_MASKZ,
16365            op0.as_operand(),
16366            op1.as_operand(),
16367            op2.as_operand(),
16368            &NOREG,
16369        );
16370    }
16371}
16372
16373/// `VPSRLDQ`.
16374///
16375/// Supported operand variants:
16376///
16377/// ```text
16378/// +---+---------------+
16379/// | # | Operands      |
16380/// +---+---------------+
16381/// | 1 | Xmm, Mem, Imm |
16382/// | 2 | Xmm, Xmm, Imm |
16383/// | 3 | Ymm, Mem, Imm |
16384/// | 4 | Ymm, Ymm, Imm |
16385/// | 5 | Zmm, Mem, Imm |
16386/// | 6 | Zmm, Zmm, Imm |
16387/// +---+---------------+
16388/// ```
16389pub trait VpsrldqEmitter<A, B, C> {
16390    fn vpsrldq(&mut self, op0: A, op1: B, op2: C);
16391}
16392
16393impl<'a> VpsrldqEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
16394    fn vpsrldq(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
16395        self.emit(
16396            VPSRLDQ128RRI,
16397            op0.as_operand(),
16398            op1.as_operand(),
16399            op2.as_operand(),
16400            &NOREG,
16401        );
16402    }
16403}
16404
16405impl<'a> VpsrldqEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
16406    fn vpsrldq(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
16407        self.emit(
16408            VPSRLDQ256RRI,
16409            op0.as_operand(),
16410            op1.as_operand(),
16411            op2.as_operand(),
16412            &NOREG,
16413        );
16414    }
16415}
16416
16417impl<'a> VpsrldqEmitter<Xmm, Mem, Imm> for Assembler<'a> {
16418    fn vpsrldq(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
16419        self.emit(
16420            VPSRLDQ128RMI,
16421            op0.as_operand(),
16422            op1.as_operand(),
16423            op2.as_operand(),
16424            &NOREG,
16425        );
16426    }
16427}
16428
16429impl<'a> VpsrldqEmitter<Ymm, Mem, Imm> for Assembler<'a> {
16430    fn vpsrldq(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
16431        self.emit(
16432            VPSRLDQ256RMI,
16433            op0.as_operand(),
16434            op1.as_operand(),
16435            op2.as_operand(),
16436            &NOREG,
16437        );
16438    }
16439}
16440
16441impl<'a> VpsrldqEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
16442    fn vpsrldq(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
16443        self.emit(
16444            VPSRLDQ512RRI,
16445            op0.as_operand(),
16446            op1.as_operand(),
16447            op2.as_operand(),
16448            &NOREG,
16449        );
16450    }
16451}
16452
16453impl<'a> VpsrldqEmitter<Zmm, Mem, Imm> for Assembler<'a> {
16454    fn vpsrldq(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
16455        self.emit(
16456            VPSRLDQ512RMI,
16457            op0.as_operand(),
16458            op1.as_operand(),
16459            op2.as_operand(),
16460            &NOREG,
16461        );
16462    }
16463}
16464
16465/// `VPSRLVW`.
16466///
16467/// Supported operand variants:
16468///
16469/// ```text
16470/// +---+---------------+
16471/// | # | Operands      |
16472/// +---+---------------+
16473/// | 1 | Xmm, Xmm, Mem |
16474/// | 2 | Xmm, Xmm, Xmm |
16475/// | 3 | Ymm, Ymm, Mem |
16476/// | 4 | Ymm, Ymm, Ymm |
16477/// | 5 | Zmm, Zmm, Mem |
16478/// | 6 | Zmm, Zmm, Zmm |
16479/// +---+---------------+
16480/// ```
16481pub trait VpsrlvwEmitter<A, B, C> {
16482    fn vpsrlvw(&mut self, op0: A, op1: B, op2: C);
16483}
16484
16485impl<'a> VpsrlvwEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
16486    fn vpsrlvw(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
16487        self.emit(
16488            VPSRLVW128RRR,
16489            op0.as_operand(),
16490            op1.as_operand(),
16491            op2.as_operand(),
16492            &NOREG,
16493        );
16494    }
16495}
16496
16497impl<'a> VpsrlvwEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
16498    fn vpsrlvw(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
16499        self.emit(
16500            VPSRLVW128RRM,
16501            op0.as_operand(),
16502            op1.as_operand(),
16503            op2.as_operand(),
16504            &NOREG,
16505        );
16506    }
16507}
16508
16509impl<'a> VpsrlvwEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
16510    fn vpsrlvw(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
16511        self.emit(
16512            VPSRLVW256RRR,
16513            op0.as_operand(),
16514            op1.as_operand(),
16515            op2.as_operand(),
16516            &NOREG,
16517        );
16518    }
16519}
16520
16521impl<'a> VpsrlvwEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
16522    fn vpsrlvw(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
16523        self.emit(
16524            VPSRLVW256RRM,
16525            op0.as_operand(),
16526            op1.as_operand(),
16527            op2.as_operand(),
16528            &NOREG,
16529        );
16530    }
16531}
16532
16533impl<'a> VpsrlvwEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
16534    fn vpsrlvw(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
16535        self.emit(
16536            VPSRLVW512RRR,
16537            op0.as_operand(),
16538            op1.as_operand(),
16539            op2.as_operand(),
16540            &NOREG,
16541        );
16542    }
16543}
16544
16545impl<'a> VpsrlvwEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
16546    fn vpsrlvw(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
16547        self.emit(
16548            VPSRLVW512RRM,
16549            op0.as_operand(),
16550            op1.as_operand(),
16551            op2.as_operand(),
16552            &NOREG,
16553        );
16554    }
16555}
16556
16557/// `VPSRLVW_MASK`.
16558///
16559/// Supported operand variants:
16560///
16561/// ```text
16562/// +---+---------------+
16563/// | # | Operands      |
16564/// +---+---------------+
16565/// | 1 | Xmm, Xmm, Mem |
16566/// | 2 | Xmm, Xmm, Xmm |
16567/// | 3 | Ymm, Ymm, Mem |
16568/// | 4 | Ymm, Ymm, Ymm |
16569/// | 5 | Zmm, Zmm, Mem |
16570/// | 6 | Zmm, Zmm, Zmm |
16571/// +---+---------------+
16572/// ```
16573pub trait VpsrlvwMaskEmitter<A, B, C> {
16574    fn vpsrlvw_mask(&mut self, op0: A, op1: B, op2: C);
16575}
16576
16577impl<'a> VpsrlvwMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
16578    fn vpsrlvw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
16579        self.emit(
16580            VPSRLVW128RRR_MASK,
16581            op0.as_operand(),
16582            op1.as_operand(),
16583            op2.as_operand(),
16584            &NOREG,
16585        );
16586    }
16587}
16588
16589impl<'a> VpsrlvwMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
16590    fn vpsrlvw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
16591        self.emit(
16592            VPSRLVW128RRM_MASK,
16593            op0.as_operand(),
16594            op1.as_operand(),
16595            op2.as_operand(),
16596            &NOREG,
16597        );
16598    }
16599}
16600
16601impl<'a> VpsrlvwMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
16602    fn vpsrlvw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
16603        self.emit(
16604            VPSRLVW256RRR_MASK,
16605            op0.as_operand(),
16606            op1.as_operand(),
16607            op2.as_operand(),
16608            &NOREG,
16609        );
16610    }
16611}
16612
16613impl<'a> VpsrlvwMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
16614    fn vpsrlvw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
16615        self.emit(
16616            VPSRLVW256RRM_MASK,
16617            op0.as_operand(),
16618            op1.as_operand(),
16619            op2.as_operand(),
16620            &NOREG,
16621        );
16622    }
16623}
16624
16625impl<'a> VpsrlvwMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
16626    fn vpsrlvw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
16627        self.emit(
16628            VPSRLVW512RRR_MASK,
16629            op0.as_operand(),
16630            op1.as_operand(),
16631            op2.as_operand(),
16632            &NOREG,
16633        );
16634    }
16635}
16636
16637impl<'a> VpsrlvwMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
16638    fn vpsrlvw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
16639        self.emit(
16640            VPSRLVW512RRM_MASK,
16641            op0.as_operand(),
16642            op1.as_operand(),
16643            op2.as_operand(),
16644            &NOREG,
16645        );
16646    }
16647}
16648
16649/// `VPSRLVW_MASKZ`.
16650///
16651/// Supported operand variants:
16652///
16653/// ```text
16654/// +---+---------------+
16655/// | # | Operands      |
16656/// +---+---------------+
16657/// | 1 | Xmm, Xmm, Mem |
16658/// | 2 | Xmm, Xmm, Xmm |
16659/// | 3 | Ymm, Ymm, Mem |
16660/// | 4 | Ymm, Ymm, Ymm |
16661/// | 5 | Zmm, Zmm, Mem |
16662/// | 6 | Zmm, Zmm, Zmm |
16663/// +---+---------------+
16664/// ```
16665pub trait VpsrlvwMaskzEmitter<A, B, C> {
16666    fn vpsrlvw_maskz(&mut self, op0: A, op1: B, op2: C);
16667}
16668
16669impl<'a> VpsrlvwMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
16670    fn vpsrlvw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
16671        self.emit(
16672            VPSRLVW128RRR_MASKZ,
16673            op0.as_operand(),
16674            op1.as_operand(),
16675            op2.as_operand(),
16676            &NOREG,
16677        );
16678    }
16679}
16680
16681impl<'a> VpsrlvwMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
16682    fn vpsrlvw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
16683        self.emit(
16684            VPSRLVW128RRM_MASKZ,
16685            op0.as_operand(),
16686            op1.as_operand(),
16687            op2.as_operand(),
16688            &NOREG,
16689        );
16690    }
16691}
16692
16693impl<'a> VpsrlvwMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
16694    fn vpsrlvw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
16695        self.emit(
16696            VPSRLVW256RRR_MASKZ,
16697            op0.as_operand(),
16698            op1.as_operand(),
16699            op2.as_operand(),
16700            &NOREG,
16701        );
16702    }
16703}
16704
16705impl<'a> VpsrlvwMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
16706    fn vpsrlvw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
16707        self.emit(
16708            VPSRLVW256RRM_MASKZ,
16709            op0.as_operand(),
16710            op1.as_operand(),
16711            op2.as_operand(),
16712            &NOREG,
16713        );
16714    }
16715}
16716
16717impl<'a> VpsrlvwMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
16718    fn vpsrlvw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
16719        self.emit(
16720            VPSRLVW512RRR_MASKZ,
16721            op0.as_operand(),
16722            op1.as_operand(),
16723            op2.as_operand(),
16724            &NOREG,
16725        );
16726    }
16727}
16728
16729impl<'a> VpsrlvwMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
16730    fn vpsrlvw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
16731        self.emit(
16732            VPSRLVW512RRM_MASKZ,
16733            op0.as_operand(),
16734            op1.as_operand(),
16735            op2.as_operand(),
16736            &NOREG,
16737        );
16738    }
16739}
16740
16741/// `VPSRLW`.
16742///
16743/// Supported operand variants:
16744///
16745/// ```text
16746/// +----+---------------+
16747/// | #  | Operands      |
16748/// +----+---------------+
16749/// | 1  | Xmm, Mem, Imm |
16750/// | 2  | Xmm, Xmm, Imm |
16751/// | 3  | Xmm, Xmm, Mem |
16752/// | 4  | Xmm, Xmm, Xmm |
16753/// | 5  | Ymm, Mem, Imm |
16754/// | 6  | Ymm, Ymm, Imm |
16755/// | 7  | Ymm, Ymm, Mem |
16756/// | 8  | Ymm, Ymm, Xmm |
16757/// | 9  | Zmm, Mem, Imm |
16758/// | 10 | Zmm, Zmm, Imm |
16759/// | 11 | Zmm, Zmm, Mem |
16760/// | 12 | Zmm, Zmm, Xmm |
16761/// +----+---------------+
16762/// ```
16763pub trait VpsrlwEmitter<A, B, C> {
16764    fn vpsrlw(&mut self, op0: A, op1: B, op2: C);
16765}
16766
16767impl<'a> VpsrlwEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
16768    fn vpsrlw(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
16769        self.emit(
16770            VPSRLW128RRI,
16771            op0.as_operand(),
16772            op1.as_operand(),
16773            op2.as_operand(),
16774            &NOREG,
16775        );
16776    }
16777}
16778
16779impl<'a> VpsrlwEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
16780    fn vpsrlw(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
16781        self.emit(
16782            VPSRLW256RRI,
16783            op0.as_operand(),
16784            op1.as_operand(),
16785            op2.as_operand(),
16786            &NOREG,
16787        );
16788    }
16789}
16790
16791impl<'a> VpsrlwEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
16792    fn vpsrlw(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
16793        self.emit(
16794            VPSRLW128RRR,
16795            op0.as_operand(),
16796            op1.as_operand(),
16797            op2.as_operand(),
16798            &NOREG,
16799        );
16800    }
16801}
16802
16803impl<'a> VpsrlwEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
16804    fn vpsrlw(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
16805        self.emit(
16806            VPSRLW128RRM,
16807            op0.as_operand(),
16808            op1.as_operand(),
16809            op2.as_operand(),
16810            &NOREG,
16811        );
16812    }
16813}
16814
16815impl<'a> VpsrlwEmitter<Ymm, Ymm, Xmm> for Assembler<'a> {
16816    fn vpsrlw(&mut self, op0: Ymm, op1: Ymm, op2: Xmm) {
16817        self.emit(
16818            VPSRLW256RRR,
16819            op0.as_operand(),
16820            op1.as_operand(),
16821            op2.as_operand(),
16822            &NOREG,
16823        );
16824    }
16825}
16826
16827impl<'a> VpsrlwEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
16828    fn vpsrlw(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
16829        self.emit(
16830            VPSRLW256RRM,
16831            op0.as_operand(),
16832            op1.as_operand(),
16833            op2.as_operand(),
16834            &NOREG,
16835        );
16836    }
16837}
16838
16839impl<'a> VpsrlwEmitter<Xmm, Mem, Imm> for Assembler<'a> {
16840    fn vpsrlw(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
16841        self.emit(
16842            VPSRLW128RMI,
16843            op0.as_operand(),
16844            op1.as_operand(),
16845            op2.as_operand(),
16846            &NOREG,
16847        );
16848    }
16849}
16850
16851impl<'a> VpsrlwEmitter<Ymm, Mem, Imm> for Assembler<'a> {
16852    fn vpsrlw(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
16853        self.emit(
16854            VPSRLW256RMI,
16855            op0.as_operand(),
16856            op1.as_operand(),
16857            op2.as_operand(),
16858            &NOREG,
16859        );
16860    }
16861}
16862
16863impl<'a> VpsrlwEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
16864    fn vpsrlw(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
16865        self.emit(
16866            VPSRLW512RRI,
16867            op0.as_operand(),
16868            op1.as_operand(),
16869            op2.as_operand(),
16870            &NOREG,
16871        );
16872    }
16873}
16874
16875impl<'a> VpsrlwEmitter<Zmm, Mem, Imm> for Assembler<'a> {
16876    fn vpsrlw(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
16877        self.emit(
16878            VPSRLW512RMI,
16879            op0.as_operand(),
16880            op1.as_operand(),
16881            op2.as_operand(),
16882            &NOREG,
16883        );
16884    }
16885}
16886
16887impl<'a> VpsrlwEmitter<Zmm, Zmm, Xmm> for Assembler<'a> {
16888    fn vpsrlw(&mut self, op0: Zmm, op1: Zmm, op2: Xmm) {
16889        self.emit(
16890            VPSRLW512RRR,
16891            op0.as_operand(),
16892            op1.as_operand(),
16893            op2.as_operand(),
16894            &NOREG,
16895        );
16896    }
16897}
16898
16899impl<'a> VpsrlwEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
16900    fn vpsrlw(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
16901        self.emit(
16902            VPSRLW512RRM,
16903            op0.as_operand(),
16904            op1.as_operand(),
16905            op2.as_operand(),
16906            &NOREG,
16907        );
16908    }
16909}
16910
16911/// `VPSRLW_MASK`.
16912///
16913/// Supported operand variants:
16914///
16915/// ```text
16916/// +----+---------------+
16917/// | #  | Operands      |
16918/// +----+---------------+
16919/// | 1  | Xmm, Mem, Imm |
16920/// | 2  | Xmm, Xmm, Imm |
16921/// | 3  | Xmm, Xmm, Mem |
16922/// | 4  | Xmm, Xmm, Xmm |
16923/// | 5  | Ymm, Mem, Imm |
16924/// | 6  | Ymm, Ymm, Imm |
16925/// | 7  | Ymm, Ymm, Mem |
16926/// | 8  | Ymm, Ymm, Xmm |
16927/// | 9  | Zmm, Mem, Imm |
16928/// | 10 | Zmm, Zmm, Imm |
16929/// | 11 | Zmm, Zmm, Mem |
16930/// | 12 | Zmm, Zmm, Xmm |
16931/// +----+---------------+
16932/// ```
16933pub trait VpsrlwMaskEmitter<A, B, C> {
16934    fn vpsrlw_mask(&mut self, op0: A, op1: B, op2: C);
16935}
16936
16937impl<'a> VpsrlwMaskEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
16938    fn vpsrlw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
16939        self.emit(
16940            VPSRLW128RRI_MASK,
16941            op0.as_operand(),
16942            op1.as_operand(),
16943            op2.as_operand(),
16944            &NOREG,
16945        );
16946    }
16947}
16948
16949impl<'a> VpsrlwMaskEmitter<Xmm, Mem, Imm> for Assembler<'a> {
16950    fn vpsrlw_mask(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
16951        self.emit(
16952            VPSRLW128RMI_MASK,
16953            op0.as_operand(),
16954            op1.as_operand(),
16955            op2.as_operand(),
16956            &NOREG,
16957        );
16958    }
16959}
16960
16961impl<'a> VpsrlwMaskEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
16962    fn vpsrlw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
16963        self.emit(
16964            VPSRLW256RRI_MASK,
16965            op0.as_operand(),
16966            op1.as_operand(),
16967            op2.as_operand(),
16968            &NOREG,
16969        );
16970    }
16971}
16972
16973impl<'a> VpsrlwMaskEmitter<Ymm, Mem, Imm> for Assembler<'a> {
16974    fn vpsrlw_mask(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
16975        self.emit(
16976            VPSRLW256RMI_MASK,
16977            op0.as_operand(),
16978            op1.as_operand(),
16979            op2.as_operand(),
16980            &NOREG,
16981        );
16982    }
16983}
16984
16985impl<'a> VpsrlwMaskEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
16986    fn vpsrlw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
16987        self.emit(
16988            VPSRLW512RRI_MASK,
16989            op0.as_operand(),
16990            op1.as_operand(),
16991            op2.as_operand(),
16992            &NOREG,
16993        );
16994    }
16995}
16996
16997impl<'a> VpsrlwMaskEmitter<Zmm, Mem, Imm> for Assembler<'a> {
16998    fn vpsrlw_mask(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
16999        self.emit(
17000            VPSRLW512RMI_MASK,
17001            op0.as_operand(),
17002            op1.as_operand(),
17003            op2.as_operand(),
17004            &NOREG,
17005        );
17006    }
17007}
17008
17009impl<'a> VpsrlwMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
17010    fn vpsrlw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
17011        self.emit(
17012            VPSRLW128RRR_MASK,
17013            op0.as_operand(),
17014            op1.as_operand(),
17015            op2.as_operand(),
17016            &NOREG,
17017        );
17018    }
17019}
17020
17021impl<'a> VpsrlwMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
17022    fn vpsrlw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
17023        self.emit(
17024            VPSRLW128RRM_MASK,
17025            op0.as_operand(),
17026            op1.as_operand(),
17027            op2.as_operand(),
17028            &NOREG,
17029        );
17030    }
17031}
17032
17033impl<'a> VpsrlwMaskEmitter<Ymm, Ymm, Xmm> for Assembler<'a> {
17034    fn vpsrlw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Xmm) {
17035        self.emit(
17036            VPSRLW256RRR_MASK,
17037            op0.as_operand(),
17038            op1.as_operand(),
17039            op2.as_operand(),
17040            &NOREG,
17041        );
17042    }
17043}
17044
17045impl<'a> VpsrlwMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
17046    fn vpsrlw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
17047        self.emit(
17048            VPSRLW256RRM_MASK,
17049            op0.as_operand(),
17050            op1.as_operand(),
17051            op2.as_operand(),
17052            &NOREG,
17053        );
17054    }
17055}
17056
17057impl<'a> VpsrlwMaskEmitter<Zmm, Zmm, Xmm> for Assembler<'a> {
17058    fn vpsrlw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Xmm) {
17059        self.emit(
17060            VPSRLW512RRR_MASK,
17061            op0.as_operand(),
17062            op1.as_operand(),
17063            op2.as_operand(),
17064            &NOREG,
17065        );
17066    }
17067}
17068
17069impl<'a> VpsrlwMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
17070    fn vpsrlw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
17071        self.emit(
17072            VPSRLW512RRM_MASK,
17073            op0.as_operand(),
17074            op1.as_operand(),
17075            op2.as_operand(),
17076            &NOREG,
17077        );
17078    }
17079}
17080
17081/// `VPSRLW_MASKZ`.
17082///
17083/// Supported operand variants:
17084///
17085/// ```text
17086/// +----+---------------+
17087/// | #  | Operands      |
17088/// +----+---------------+
17089/// | 1  | Xmm, Mem, Imm |
17090/// | 2  | Xmm, Xmm, Imm |
17091/// | 3  | Xmm, Xmm, Mem |
17092/// | 4  | Xmm, Xmm, Xmm |
17093/// | 5  | Ymm, Mem, Imm |
17094/// | 6  | Ymm, Ymm, Imm |
17095/// | 7  | Ymm, Ymm, Mem |
17096/// | 8  | Ymm, Ymm, Xmm |
17097/// | 9  | Zmm, Mem, Imm |
17098/// | 10 | Zmm, Zmm, Imm |
17099/// | 11 | Zmm, Zmm, Mem |
17100/// | 12 | Zmm, Zmm, Xmm |
17101/// +----+---------------+
17102/// ```
17103pub trait VpsrlwMaskzEmitter<A, B, C> {
17104    fn vpsrlw_maskz(&mut self, op0: A, op1: B, op2: C);
17105}
17106
17107impl<'a> VpsrlwMaskzEmitter<Xmm, Xmm, Imm> for Assembler<'a> {
17108    fn vpsrlw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Imm) {
17109        self.emit(
17110            VPSRLW128RRI_MASKZ,
17111            op0.as_operand(),
17112            op1.as_operand(),
17113            op2.as_operand(),
17114            &NOREG,
17115        );
17116    }
17117}
17118
17119impl<'a> VpsrlwMaskzEmitter<Xmm, Mem, Imm> for Assembler<'a> {
17120    fn vpsrlw_maskz(&mut self, op0: Xmm, op1: Mem, op2: Imm) {
17121        self.emit(
17122            VPSRLW128RMI_MASKZ,
17123            op0.as_operand(),
17124            op1.as_operand(),
17125            op2.as_operand(),
17126            &NOREG,
17127        );
17128    }
17129}
17130
17131impl<'a> VpsrlwMaskzEmitter<Ymm, Ymm, Imm> for Assembler<'a> {
17132    fn vpsrlw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Imm) {
17133        self.emit(
17134            VPSRLW256RRI_MASKZ,
17135            op0.as_operand(),
17136            op1.as_operand(),
17137            op2.as_operand(),
17138            &NOREG,
17139        );
17140    }
17141}
17142
17143impl<'a> VpsrlwMaskzEmitter<Ymm, Mem, Imm> for Assembler<'a> {
17144    fn vpsrlw_maskz(&mut self, op0: Ymm, op1: Mem, op2: Imm) {
17145        self.emit(
17146            VPSRLW256RMI_MASKZ,
17147            op0.as_operand(),
17148            op1.as_operand(),
17149            op2.as_operand(),
17150            &NOREG,
17151        );
17152    }
17153}
17154
17155impl<'a> VpsrlwMaskzEmitter<Zmm, Zmm, Imm> for Assembler<'a> {
17156    fn vpsrlw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Imm) {
17157        self.emit(
17158            VPSRLW512RRI_MASKZ,
17159            op0.as_operand(),
17160            op1.as_operand(),
17161            op2.as_operand(),
17162            &NOREG,
17163        );
17164    }
17165}
17166
17167impl<'a> VpsrlwMaskzEmitter<Zmm, Mem, Imm> for Assembler<'a> {
17168    fn vpsrlw_maskz(&mut self, op0: Zmm, op1: Mem, op2: Imm) {
17169        self.emit(
17170            VPSRLW512RMI_MASKZ,
17171            op0.as_operand(),
17172            op1.as_operand(),
17173            op2.as_operand(),
17174            &NOREG,
17175        );
17176    }
17177}
17178
17179impl<'a> VpsrlwMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
17180    fn vpsrlw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
17181        self.emit(
17182            VPSRLW128RRR_MASKZ,
17183            op0.as_operand(),
17184            op1.as_operand(),
17185            op2.as_operand(),
17186            &NOREG,
17187        );
17188    }
17189}
17190
17191impl<'a> VpsrlwMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
17192    fn vpsrlw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
17193        self.emit(
17194            VPSRLW128RRM_MASKZ,
17195            op0.as_operand(),
17196            op1.as_operand(),
17197            op2.as_operand(),
17198            &NOREG,
17199        );
17200    }
17201}
17202
17203impl<'a> VpsrlwMaskzEmitter<Ymm, Ymm, Xmm> for Assembler<'a> {
17204    fn vpsrlw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Xmm) {
17205        self.emit(
17206            VPSRLW256RRR_MASKZ,
17207            op0.as_operand(),
17208            op1.as_operand(),
17209            op2.as_operand(),
17210            &NOREG,
17211        );
17212    }
17213}
17214
17215impl<'a> VpsrlwMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
17216    fn vpsrlw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
17217        self.emit(
17218            VPSRLW256RRM_MASKZ,
17219            op0.as_operand(),
17220            op1.as_operand(),
17221            op2.as_operand(),
17222            &NOREG,
17223        );
17224    }
17225}
17226
17227impl<'a> VpsrlwMaskzEmitter<Zmm, Zmm, Xmm> for Assembler<'a> {
17228    fn vpsrlw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Xmm) {
17229        self.emit(
17230            VPSRLW512RRR_MASKZ,
17231            op0.as_operand(),
17232            op1.as_operand(),
17233            op2.as_operand(),
17234            &NOREG,
17235        );
17236    }
17237}
17238
17239impl<'a> VpsrlwMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
17240    fn vpsrlw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
17241        self.emit(
17242            VPSRLW512RRM_MASKZ,
17243            op0.as_operand(),
17244            op1.as_operand(),
17245            op2.as_operand(),
17246            &NOREG,
17247        );
17248    }
17249}
17250
17251/// `VPSUBB`.
17252///
17253/// Supported operand variants:
17254///
17255/// ```text
17256/// +---+---------------+
17257/// | # | Operands      |
17258/// +---+---------------+
17259/// | 1 | Xmm, Xmm, Mem |
17260/// | 2 | Xmm, Xmm, Xmm |
17261/// | 3 | Ymm, Ymm, Mem |
17262/// | 4 | Ymm, Ymm, Ymm |
17263/// | 5 | Zmm, Zmm, Mem |
17264/// | 6 | Zmm, Zmm, Zmm |
17265/// +---+---------------+
17266/// ```
17267pub trait VpsubbEmitter<A, B, C> {
17268    fn vpsubb(&mut self, op0: A, op1: B, op2: C);
17269}
17270
17271impl<'a> VpsubbEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
17272    fn vpsubb(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
17273        self.emit(
17274            VPSUBB128RRR,
17275            op0.as_operand(),
17276            op1.as_operand(),
17277            op2.as_operand(),
17278            &NOREG,
17279        );
17280    }
17281}
17282
17283impl<'a> VpsubbEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
17284    fn vpsubb(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
17285        self.emit(
17286            VPSUBB128RRM,
17287            op0.as_operand(),
17288            op1.as_operand(),
17289            op2.as_operand(),
17290            &NOREG,
17291        );
17292    }
17293}
17294
17295impl<'a> VpsubbEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
17296    fn vpsubb(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
17297        self.emit(
17298            VPSUBB256RRR,
17299            op0.as_operand(),
17300            op1.as_operand(),
17301            op2.as_operand(),
17302            &NOREG,
17303        );
17304    }
17305}
17306
17307impl<'a> VpsubbEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
17308    fn vpsubb(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
17309        self.emit(
17310            VPSUBB256RRM,
17311            op0.as_operand(),
17312            op1.as_operand(),
17313            op2.as_operand(),
17314            &NOREG,
17315        );
17316    }
17317}
17318
17319impl<'a> VpsubbEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
17320    fn vpsubb(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
17321        self.emit(
17322            VPSUBB512RRR,
17323            op0.as_operand(),
17324            op1.as_operand(),
17325            op2.as_operand(),
17326            &NOREG,
17327        );
17328    }
17329}
17330
17331impl<'a> VpsubbEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
17332    fn vpsubb(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
17333        self.emit(
17334            VPSUBB512RRM,
17335            op0.as_operand(),
17336            op1.as_operand(),
17337            op2.as_operand(),
17338            &NOREG,
17339        );
17340    }
17341}
17342
17343/// `VPSUBB_MASK`.
17344///
17345/// Supported operand variants:
17346///
17347/// ```text
17348/// +---+---------------+
17349/// | # | Operands      |
17350/// +---+---------------+
17351/// | 1 | Xmm, Xmm, Mem |
17352/// | 2 | Xmm, Xmm, Xmm |
17353/// | 3 | Ymm, Ymm, Mem |
17354/// | 4 | Ymm, Ymm, Ymm |
17355/// | 5 | Zmm, Zmm, Mem |
17356/// | 6 | Zmm, Zmm, Zmm |
17357/// +---+---------------+
17358/// ```
17359pub trait VpsubbMaskEmitter<A, B, C> {
17360    fn vpsubb_mask(&mut self, op0: A, op1: B, op2: C);
17361}
17362
17363impl<'a> VpsubbMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
17364    fn vpsubb_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
17365        self.emit(
17366            VPSUBB128RRR_MASK,
17367            op0.as_operand(),
17368            op1.as_operand(),
17369            op2.as_operand(),
17370            &NOREG,
17371        );
17372    }
17373}
17374
17375impl<'a> VpsubbMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
17376    fn vpsubb_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
17377        self.emit(
17378            VPSUBB128RRM_MASK,
17379            op0.as_operand(),
17380            op1.as_operand(),
17381            op2.as_operand(),
17382            &NOREG,
17383        );
17384    }
17385}
17386
17387impl<'a> VpsubbMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
17388    fn vpsubb_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
17389        self.emit(
17390            VPSUBB256RRR_MASK,
17391            op0.as_operand(),
17392            op1.as_operand(),
17393            op2.as_operand(),
17394            &NOREG,
17395        );
17396    }
17397}
17398
17399impl<'a> VpsubbMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
17400    fn vpsubb_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
17401        self.emit(
17402            VPSUBB256RRM_MASK,
17403            op0.as_operand(),
17404            op1.as_operand(),
17405            op2.as_operand(),
17406            &NOREG,
17407        );
17408    }
17409}
17410
17411impl<'a> VpsubbMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
17412    fn vpsubb_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
17413        self.emit(
17414            VPSUBB512RRR_MASK,
17415            op0.as_operand(),
17416            op1.as_operand(),
17417            op2.as_operand(),
17418            &NOREG,
17419        );
17420    }
17421}
17422
17423impl<'a> VpsubbMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
17424    fn vpsubb_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
17425        self.emit(
17426            VPSUBB512RRM_MASK,
17427            op0.as_operand(),
17428            op1.as_operand(),
17429            op2.as_operand(),
17430            &NOREG,
17431        );
17432    }
17433}
17434
17435/// `VPSUBB_MASKZ`.
17436///
17437/// Supported operand variants:
17438///
17439/// ```text
17440/// +---+---------------+
17441/// | # | Operands      |
17442/// +---+---------------+
17443/// | 1 | Xmm, Xmm, Mem |
17444/// | 2 | Xmm, Xmm, Xmm |
17445/// | 3 | Ymm, Ymm, Mem |
17446/// | 4 | Ymm, Ymm, Ymm |
17447/// | 5 | Zmm, Zmm, Mem |
17448/// | 6 | Zmm, Zmm, Zmm |
17449/// +---+---------------+
17450/// ```
17451pub trait VpsubbMaskzEmitter<A, B, C> {
17452    fn vpsubb_maskz(&mut self, op0: A, op1: B, op2: C);
17453}
17454
17455impl<'a> VpsubbMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
17456    fn vpsubb_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
17457        self.emit(
17458            VPSUBB128RRR_MASKZ,
17459            op0.as_operand(),
17460            op1.as_operand(),
17461            op2.as_operand(),
17462            &NOREG,
17463        );
17464    }
17465}
17466
17467impl<'a> VpsubbMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
17468    fn vpsubb_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
17469        self.emit(
17470            VPSUBB128RRM_MASKZ,
17471            op0.as_operand(),
17472            op1.as_operand(),
17473            op2.as_operand(),
17474            &NOREG,
17475        );
17476    }
17477}
17478
17479impl<'a> VpsubbMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
17480    fn vpsubb_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
17481        self.emit(
17482            VPSUBB256RRR_MASKZ,
17483            op0.as_operand(),
17484            op1.as_operand(),
17485            op2.as_operand(),
17486            &NOREG,
17487        );
17488    }
17489}
17490
17491impl<'a> VpsubbMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
17492    fn vpsubb_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
17493        self.emit(
17494            VPSUBB256RRM_MASKZ,
17495            op0.as_operand(),
17496            op1.as_operand(),
17497            op2.as_operand(),
17498            &NOREG,
17499        );
17500    }
17501}
17502
17503impl<'a> VpsubbMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
17504    fn vpsubb_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
17505        self.emit(
17506            VPSUBB512RRR_MASKZ,
17507            op0.as_operand(),
17508            op1.as_operand(),
17509            op2.as_operand(),
17510            &NOREG,
17511        );
17512    }
17513}
17514
17515impl<'a> VpsubbMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
17516    fn vpsubb_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
17517        self.emit(
17518            VPSUBB512RRM_MASKZ,
17519            op0.as_operand(),
17520            op1.as_operand(),
17521            op2.as_operand(),
17522            &NOREG,
17523        );
17524    }
17525}
17526
17527/// `VPSUBSB`.
17528///
17529/// Supported operand variants:
17530///
17531/// ```text
17532/// +---+---------------+
17533/// | # | Operands      |
17534/// +---+---------------+
17535/// | 1 | Xmm, Xmm, Mem |
17536/// | 2 | Xmm, Xmm, Xmm |
17537/// | 3 | Ymm, Ymm, Mem |
17538/// | 4 | Ymm, Ymm, Ymm |
17539/// | 5 | Zmm, Zmm, Mem |
17540/// | 6 | Zmm, Zmm, Zmm |
17541/// +---+---------------+
17542/// ```
17543pub trait VpsubsbEmitter<A, B, C> {
17544    fn vpsubsb(&mut self, op0: A, op1: B, op2: C);
17545}
17546
17547impl<'a> VpsubsbEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
17548    fn vpsubsb(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
17549        self.emit(
17550            VPSUBSB128RRR,
17551            op0.as_operand(),
17552            op1.as_operand(),
17553            op2.as_operand(),
17554            &NOREG,
17555        );
17556    }
17557}
17558
17559impl<'a> VpsubsbEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
17560    fn vpsubsb(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
17561        self.emit(
17562            VPSUBSB128RRM,
17563            op0.as_operand(),
17564            op1.as_operand(),
17565            op2.as_operand(),
17566            &NOREG,
17567        );
17568    }
17569}
17570
17571impl<'a> VpsubsbEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
17572    fn vpsubsb(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
17573        self.emit(
17574            VPSUBSB256RRR,
17575            op0.as_operand(),
17576            op1.as_operand(),
17577            op2.as_operand(),
17578            &NOREG,
17579        );
17580    }
17581}
17582
17583impl<'a> VpsubsbEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
17584    fn vpsubsb(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
17585        self.emit(
17586            VPSUBSB256RRM,
17587            op0.as_operand(),
17588            op1.as_operand(),
17589            op2.as_operand(),
17590            &NOREG,
17591        );
17592    }
17593}
17594
17595impl<'a> VpsubsbEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
17596    fn vpsubsb(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
17597        self.emit(
17598            VPSUBSB512RRR,
17599            op0.as_operand(),
17600            op1.as_operand(),
17601            op2.as_operand(),
17602            &NOREG,
17603        );
17604    }
17605}
17606
17607impl<'a> VpsubsbEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
17608    fn vpsubsb(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
17609        self.emit(
17610            VPSUBSB512RRM,
17611            op0.as_operand(),
17612            op1.as_operand(),
17613            op2.as_operand(),
17614            &NOREG,
17615        );
17616    }
17617}
17618
17619/// `VPSUBSB_MASK`.
17620///
17621/// Supported operand variants:
17622///
17623/// ```text
17624/// +---+---------------+
17625/// | # | Operands      |
17626/// +---+---------------+
17627/// | 1 | Xmm, Xmm, Mem |
17628/// | 2 | Xmm, Xmm, Xmm |
17629/// | 3 | Ymm, Ymm, Mem |
17630/// | 4 | Ymm, Ymm, Ymm |
17631/// | 5 | Zmm, Zmm, Mem |
17632/// | 6 | Zmm, Zmm, Zmm |
17633/// +---+---------------+
17634/// ```
17635pub trait VpsubsbMaskEmitter<A, B, C> {
17636    fn vpsubsb_mask(&mut self, op0: A, op1: B, op2: C);
17637}
17638
17639impl<'a> VpsubsbMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
17640    fn vpsubsb_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
17641        self.emit(
17642            VPSUBSB128RRR_MASK,
17643            op0.as_operand(),
17644            op1.as_operand(),
17645            op2.as_operand(),
17646            &NOREG,
17647        );
17648    }
17649}
17650
17651impl<'a> VpsubsbMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
17652    fn vpsubsb_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
17653        self.emit(
17654            VPSUBSB128RRM_MASK,
17655            op0.as_operand(),
17656            op1.as_operand(),
17657            op2.as_operand(),
17658            &NOREG,
17659        );
17660    }
17661}
17662
17663impl<'a> VpsubsbMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
17664    fn vpsubsb_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
17665        self.emit(
17666            VPSUBSB256RRR_MASK,
17667            op0.as_operand(),
17668            op1.as_operand(),
17669            op2.as_operand(),
17670            &NOREG,
17671        );
17672    }
17673}
17674
17675impl<'a> VpsubsbMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
17676    fn vpsubsb_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
17677        self.emit(
17678            VPSUBSB256RRM_MASK,
17679            op0.as_operand(),
17680            op1.as_operand(),
17681            op2.as_operand(),
17682            &NOREG,
17683        );
17684    }
17685}
17686
17687impl<'a> VpsubsbMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
17688    fn vpsubsb_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
17689        self.emit(
17690            VPSUBSB512RRR_MASK,
17691            op0.as_operand(),
17692            op1.as_operand(),
17693            op2.as_operand(),
17694            &NOREG,
17695        );
17696    }
17697}
17698
17699impl<'a> VpsubsbMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
17700    fn vpsubsb_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
17701        self.emit(
17702            VPSUBSB512RRM_MASK,
17703            op0.as_operand(),
17704            op1.as_operand(),
17705            op2.as_operand(),
17706            &NOREG,
17707        );
17708    }
17709}
17710
17711/// `VPSUBSB_MASKZ`.
17712///
17713/// Supported operand variants:
17714///
17715/// ```text
17716/// +---+---------------+
17717/// | # | Operands      |
17718/// +---+---------------+
17719/// | 1 | Xmm, Xmm, Mem |
17720/// | 2 | Xmm, Xmm, Xmm |
17721/// | 3 | Ymm, Ymm, Mem |
17722/// | 4 | Ymm, Ymm, Ymm |
17723/// | 5 | Zmm, Zmm, Mem |
17724/// | 6 | Zmm, Zmm, Zmm |
17725/// +---+---------------+
17726/// ```
17727pub trait VpsubsbMaskzEmitter<A, B, C> {
17728    fn vpsubsb_maskz(&mut self, op0: A, op1: B, op2: C);
17729}
17730
17731impl<'a> VpsubsbMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
17732    fn vpsubsb_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
17733        self.emit(
17734            VPSUBSB128RRR_MASKZ,
17735            op0.as_operand(),
17736            op1.as_operand(),
17737            op2.as_operand(),
17738            &NOREG,
17739        );
17740    }
17741}
17742
17743impl<'a> VpsubsbMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
17744    fn vpsubsb_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
17745        self.emit(
17746            VPSUBSB128RRM_MASKZ,
17747            op0.as_operand(),
17748            op1.as_operand(),
17749            op2.as_operand(),
17750            &NOREG,
17751        );
17752    }
17753}
17754
17755impl<'a> VpsubsbMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
17756    fn vpsubsb_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
17757        self.emit(
17758            VPSUBSB256RRR_MASKZ,
17759            op0.as_operand(),
17760            op1.as_operand(),
17761            op2.as_operand(),
17762            &NOREG,
17763        );
17764    }
17765}
17766
17767impl<'a> VpsubsbMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
17768    fn vpsubsb_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
17769        self.emit(
17770            VPSUBSB256RRM_MASKZ,
17771            op0.as_operand(),
17772            op1.as_operand(),
17773            op2.as_operand(),
17774            &NOREG,
17775        );
17776    }
17777}
17778
17779impl<'a> VpsubsbMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
17780    fn vpsubsb_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
17781        self.emit(
17782            VPSUBSB512RRR_MASKZ,
17783            op0.as_operand(),
17784            op1.as_operand(),
17785            op2.as_operand(),
17786            &NOREG,
17787        );
17788    }
17789}
17790
17791impl<'a> VpsubsbMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
17792    fn vpsubsb_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
17793        self.emit(
17794            VPSUBSB512RRM_MASKZ,
17795            op0.as_operand(),
17796            op1.as_operand(),
17797            op2.as_operand(),
17798            &NOREG,
17799        );
17800    }
17801}
17802
17803/// `VPSUBSW`.
17804///
17805/// Supported operand variants:
17806///
17807/// ```text
17808/// +---+---------------+
17809/// | # | Operands      |
17810/// +---+---------------+
17811/// | 1 | Xmm, Xmm, Mem |
17812/// | 2 | Xmm, Xmm, Xmm |
17813/// | 3 | Ymm, Ymm, Mem |
17814/// | 4 | Ymm, Ymm, Ymm |
17815/// | 5 | Zmm, Zmm, Mem |
17816/// | 6 | Zmm, Zmm, Zmm |
17817/// +---+---------------+
17818/// ```
17819pub trait VpsubswEmitter<A, B, C> {
17820    fn vpsubsw(&mut self, op0: A, op1: B, op2: C);
17821}
17822
17823impl<'a> VpsubswEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
17824    fn vpsubsw(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
17825        self.emit(
17826            VPSUBSW128RRR,
17827            op0.as_operand(),
17828            op1.as_operand(),
17829            op2.as_operand(),
17830            &NOREG,
17831        );
17832    }
17833}
17834
17835impl<'a> VpsubswEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
17836    fn vpsubsw(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
17837        self.emit(
17838            VPSUBSW128RRM,
17839            op0.as_operand(),
17840            op1.as_operand(),
17841            op2.as_operand(),
17842            &NOREG,
17843        );
17844    }
17845}
17846
17847impl<'a> VpsubswEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
17848    fn vpsubsw(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
17849        self.emit(
17850            VPSUBSW256RRR,
17851            op0.as_operand(),
17852            op1.as_operand(),
17853            op2.as_operand(),
17854            &NOREG,
17855        );
17856    }
17857}
17858
17859impl<'a> VpsubswEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
17860    fn vpsubsw(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
17861        self.emit(
17862            VPSUBSW256RRM,
17863            op0.as_operand(),
17864            op1.as_operand(),
17865            op2.as_operand(),
17866            &NOREG,
17867        );
17868    }
17869}
17870
17871impl<'a> VpsubswEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
17872    fn vpsubsw(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
17873        self.emit(
17874            VPSUBSW512RRR,
17875            op0.as_operand(),
17876            op1.as_operand(),
17877            op2.as_operand(),
17878            &NOREG,
17879        );
17880    }
17881}
17882
17883impl<'a> VpsubswEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
17884    fn vpsubsw(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
17885        self.emit(
17886            VPSUBSW512RRM,
17887            op0.as_operand(),
17888            op1.as_operand(),
17889            op2.as_operand(),
17890            &NOREG,
17891        );
17892    }
17893}
17894
17895/// `VPSUBSW_MASK`.
17896///
17897/// Supported operand variants:
17898///
17899/// ```text
17900/// +---+---------------+
17901/// | # | Operands      |
17902/// +---+---------------+
17903/// | 1 | Xmm, Xmm, Mem |
17904/// | 2 | Xmm, Xmm, Xmm |
17905/// | 3 | Ymm, Ymm, Mem |
17906/// | 4 | Ymm, Ymm, Ymm |
17907/// | 5 | Zmm, Zmm, Mem |
17908/// | 6 | Zmm, Zmm, Zmm |
17909/// +---+---------------+
17910/// ```
17911pub trait VpsubswMaskEmitter<A, B, C> {
17912    fn vpsubsw_mask(&mut self, op0: A, op1: B, op2: C);
17913}
17914
17915impl<'a> VpsubswMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
17916    fn vpsubsw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
17917        self.emit(
17918            VPSUBSW128RRR_MASK,
17919            op0.as_operand(),
17920            op1.as_operand(),
17921            op2.as_operand(),
17922            &NOREG,
17923        );
17924    }
17925}
17926
17927impl<'a> VpsubswMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
17928    fn vpsubsw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
17929        self.emit(
17930            VPSUBSW128RRM_MASK,
17931            op0.as_operand(),
17932            op1.as_operand(),
17933            op2.as_operand(),
17934            &NOREG,
17935        );
17936    }
17937}
17938
17939impl<'a> VpsubswMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
17940    fn vpsubsw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
17941        self.emit(
17942            VPSUBSW256RRR_MASK,
17943            op0.as_operand(),
17944            op1.as_operand(),
17945            op2.as_operand(),
17946            &NOREG,
17947        );
17948    }
17949}
17950
17951impl<'a> VpsubswMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
17952    fn vpsubsw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
17953        self.emit(
17954            VPSUBSW256RRM_MASK,
17955            op0.as_operand(),
17956            op1.as_operand(),
17957            op2.as_operand(),
17958            &NOREG,
17959        );
17960    }
17961}
17962
17963impl<'a> VpsubswMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
17964    fn vpsubsw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
17965        self.emit(
17966            VPSUBSW512RRR_MASK,
17967            op0.as_operand(),
17968            op1.as_operand(),
17969            op2.as_operand(),
17970            &NOREG,
17971        );
17972    }
17973}
17974
17975impl<'a> VpsubswMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
17976    fn vpsubsw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
17977        self.emit(
17978            VPSUBSW512RRM_MASK,
17979            op0.as_operand(),
17980            op1.as_operand(),
17981            op2.as_operand(),
17982            &NOREG,
17983        );
17984    }
17985}
17986
17987/// `VPSUBSW_MASKZ`.
17988///
17989/// Supported operand variants:
17990///
17991/// ```text
17992/// +---+---------------+
17993/// | # | Operands      |
17994/// +---+---------------+
17995/// | 1 | Xmm, Xmm, Mem |
17996/// | 2 | Xmm, Xmm, Xmm |
17997/// | 3 | Ymm, Ymm, Mem |
17998/// | 4 | Ymm, Ymm, Ymm |
17999/// | 5 | Zmm, Zmm, Mem |
18000/// | 6 | Zmm, Zmm, Zmm |
18001/// +---+---------------+
18002/// ```
18003pub trait VpsubswMaskzEmitter<A, B, C> {
18004    fn vpsubsw_maskz(&mut self, op0: A, op1: B, op2: C);
18005}
18006
18007impl<'a> VpsubswMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
18008    fn vpsubsw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
18009        self.emit(
18010            VPSUBSW128RRR_MASKZ,
18011            op0.as_operand(),
18012            op1.as_operand(),
18013            op2.as_operand(),
18014            &NOREG,
18015        );
18016    }
18017}
18018
18019impl<'a> VpsubswMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
18020    fn vpsubsw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
18021        self.emit(
18022            VPSUBSW128RRM_MASKZ,
18023            op0.as_operand(),
18024            op1.as_operand(),
18025            op2.as_operand(),
18026            &NOREG,
18027        );
18028    }
18029}
18030
18031impl<'a> VpsubswMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
18032    fn vpsubsw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
18033        self.emit(
18034            VPSUBSW256RRR_MASKZ,
18035            op0.as_operand(),
18036            op1.as_operand(),
18037            op2.as_operand(),
18038            &NOREG,
18039        );
18040    }
18041}
18042
18043impl<'a> VpsubswMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
18044    fn vpsubsw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
18045        self.emit(
18046            VPSUBSW256RRM_MASKZ,
18047            op0.as_operand(),
18048            op1.as_operand(),
18049            op2.as_operand(),
18050            &NOREG,
18051        );
18052    }
18053}
18054
18055impl<'a> VpsubswMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
18056    fn vpsubsw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
18057        self.emit(
18058            VPSUBSW512RRR_MASKZ,
18059            op0.as_operand(),
18060            op1.as_operand(),
18061            op2.as_operand(),
18062            &NOREG,
18063        );
18064    }
18065}
18066
18067impl<'a> VpsubswMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
18068    fn vpsubsw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
18069        self.emit(
18070            VPSUBSW512RRM_MASKZ,
18071            op0.as_operand(),
18072            op1.as_operand(),
18073            op2.as_operand(),
18074            &NOREG,
18075        );
18076    }
18077}
18078
18079/// `VPSUBUSB`.
18080///
18081/// Supported operand variants:
18082///
18083/// ```text
18084/// +---+---------------+
18085/// | # | Operands      |
18086/// +---+---------------+
18087/// | 1 | Xmm, Xmm, Mem |
18088/// | 2 | Xmm, Xmm, Xmm |
18089/// | 3 | Ymm, Ymm, Mem |
18090/// | 4 | Ymm, Ymm, Ymm |
18091/// | 5 | Zmm, Zmm, Mem |
18092/// | 6 | Zmm, Zmm, Zmm |
18093/// +---+---------------+
18094/// ```
18095pub trait VpsubusbEmitter<A, B, C> {
18096    fn vpsubusb(&mut self, op0: A, op1: B, op2: C);
18097}
18098
18099impl<'a> VpsubusbEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
18100    fn vpsubusb(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
18101        self.emit(
18102            VPSUBUSB128RRR,
18103            op0.as_operand(),
18104            op1.as_operand(),
18105            op2.as_operand(),
18106            &NOREG,
18107        );
18108    }
18109}
18110
18111impl<'a> VpsubusbEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
18112    fn vpsubusb(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
18113        self.emit(
18114            VPSUBUSB128RRM,
18115            op0.as_operand(),
18116            op1.as_operand(),
18117            op2.as_operand(),
18118            &NOREG,
18119        );
18120    }
18121}
18122
18123impl<'a> VpsubusbEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
18124    fn vpsubusb(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
18125        self.emit(
18126            VPSUBUSB256RRR,
18127            op0.as_operand(),
18128            op1.as_operand(),
18129            op2.as_operand(),
18130            &NOREG,
18131        );
18132    }
18133}
18134
18135impl<'a> VpsubusbEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
18136    fn vpsubusb(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
18137        self.emit(
18138            VPSUBUSB256RRM,
18139            op0.as_operand(),
18140            op1.as_operand(),
18141            op2.as_operand(),
18142            &NOREG,
18143        );
18144    }
18145}
18146
18147impl<'a> VpsubusbEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
18148    fn vpsubusb(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
18149        self.emit(
18150            VPSUBUSB512RRR,
18151            op0.as_operand(),
18152            op1.as_operand(),
18153            op2.as_operand(),
18154            &NOREG,
18155        );
18156    }
18157}
18158
18159impl<'a> VpsubusbEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
18160    fn vpsubusb(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
18161        self.emit(
18162            VPSUBUSB512RRM,
18163            op0.as_operand(),
18164            op1.as_operand(),
18165            op2.as_operand(),
18166            &NOREG,
18167        );
18168    }
18169}
18170
18171/// `VPSUBUSB_MASK`.
18172///
18173/// Supported operand variants:
18174///
18175/// ```text
18176/// +---+---------------+
18177/// | # | Operands      |
18178/// +---+---------------+
18179/// | 1 | Xmm, Xmm, Mem |
18180/// | 2 | Xmm, Xmm, Xmm |
18181/// | 3 | Ymm, Ymm, Mem |
18182/// | 4 | Ymm, Ymm, Ymm |
18183/// | 5 | Zmm, Zmm, Mem |
18184/// | 6 | Zmm, Zmm, Zmm |
18185/// +---+---------------+
18186/// ```
18187pub trait VpsubusbMaskEmitter<A, B, C> {
18188    fn vpsubusb_mask(&mut self, op0: A, op1: B, op2: C);
18189}
18190
18191impl<'a> VpsubusbMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
18192    fn vpsubusb_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
18193        self.emit(
18194            VPSUBUSB128RRR_MASK,
18195            op0.as_operand(),
18196            op1.as_operand(),
18197            op2.as_operand(),
18198            &NOREG,
18199        );
18200    }
18201}
18202
18203impl<'a> VpsubusbMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
18204    fn vpsubusb_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
18205        self.emit(
18206            VPSUBUSB128RRM_MASK,
18207            op0.as_operand(),
18208            op1.as_operand(),
18209            op2.as_operand(),
18210            &NOREG,
18211        );
18212    }
18213}
18214
18215impl<'a> VpsubusbMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
18216    fn vpsubusb_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
18217        self.emit(
18218            VPSUBUSB256RRR_MASK,
18219            op0.as_operand(),
18220            op1.as_operand(),
18221            op2.as_operand(),
18222            &NOREG,
18223        );
18224    }
18225}
18226
18227impl<'a> VpsubusbMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
18228    fn vpsubusb_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
18229        self.emit(
18230            VPSUBUSB256RRM_MASK,
18231            op0.as_operand(),
18232            op1.as_operand(),
18233            op2.as_operand(),
18234            &NOREG,
18235        );
18236    }
18237}
18238
18239impl<'a> VpsubusbMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
18240    fn vpsubusb_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
18241        self.emit(
18242            VPSUBUSB512RRR_MASK,
18243            op0.as_operand(),
18244            op1.as_operand(),
18245            op2.as_operand(),
18246            &NOREG,
18247        );
18248    }
18249}
18250
18251impl<'a> VpsubusbMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
18252    fn vpsubusb_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
18253        self.emit(
18254            VPSUBUSB512RRM_MASK,
18255            op0.as_operand(),
18256            op1.as_operand(),
18257            op2.as_operand(),
18258            &NOREG,
18259        );
18260    }
18261}
18262
18263/// `VPSUBUSB_MASKZ`.
18264///
18265/// Supported operand variants:
18266///
18267/// ```text
18268/// +---+---------------+
18269/// | # | Operands      |
18270/// +---+---------------+
18271/// | 1 | Xmm, Xmm, Mem |
18272/// | 2 | Xmm, Xmm, Xmm |
18273/// | 3 | Ymm, Ymm, Mem |
18274/// | 4 | Ymm, Ymm, Ymm |
18275/// | 5 | Zmm, Zmm, Mem |
18276/// | 6 | Zmm, Zmm, Zmm |
18277/// +---+---------------+
18278/// ```
18279pub trait VpsubusbMaskzEmitter<A, B, C> {
18280    fn vpsubusb_maskz(&mut self, op0: A, op1: B, op2: C);
18281}
18282
18283impl<'a> VpsubusbMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
18284    fn vpsubusb_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
18285        self.emit(
18286            VPSUBUSB128RRR_MASKZ,
18287            op0.as_operand(),
18288            op1.as_operand(),
18289            op2.as_operand(),
18290            &NOREG,
18291        );
18292    }
18293}
18294
18295impl<'a> VpsubusbMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
18296    fn vpsubusb_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
18297        self.emit(
18298            VPSUBUSB128RRM_MASKZ,
18299            op0.as_operand(),
18300            op1.as_operand(),
18301            op2.as_operand(),
18302            &NOREG,
18303        );
18304    }
18305}
18306
18307impl<'a> VpsubusbMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
18308    fn vpsubusb_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
18309        self.emit(
18310            VPSUBUSB256RRR_MASKZ,
18311            op0.as_operand(),
18312            op1.as_operand(),
18313            op2.as_operand(),
18314            &NOREG,
18315        );
18316    }
18317}
18318
18319impl<'a> VpsubusbMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
18320    fn vpsubusb_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
18321        self.emit(
18322            VPSUBUSB256RRM_MASKZ,
18323            op0.as_operand(),
18324            op1.as_operand(),
18325            op2.as_operand(),
18326            &NOREG,
18327        );
18328    }
18329}
18330
18331impl<'a> VpsubusbMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
18332    fn vpsubusb_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
18333        self.emit(
18334            VPSUBUSB512RRR_MASKZ,
18335            op0.as_operand(),
18336            op1.as_operand(),
18337            op2.as_operand(),
18338            &NOREG,
18339        );
18340    }
18341}
18342
18343impl<'a> VpsubusbMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
18344    fn vpsubusb_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
18345        self.emit(
18346            VPSUBUSB512RRM_MASKZ,
18347            op0.as_operand(),
18348            op1.as_operand(),
18349            op2.as_operand(),
18350            &NOREG,
18351        );
18352    }
18353}
18354
18355/// `VPSUBUSW`.
18356///
18357/// Supported operand variants:
18358///
18359/// ```text
18360/// +---+---------------+
18361/// | # | Operands      |
18362/// +---+---------------+
18363/// | 1 | Xmm, Xmm, Mem |
18364/// | 2 | Xmm, Xmm, Xmm |
18365/// | 3 | Ymm, Ymm, Mem |
18366/// | 4 | Ymm, Ymm, Ymm |
18367/// | 5 | Zmm, Zmm, Mem |
18368/// | 6 | Zmm, Zmm, Zmm |
18369/// +---+---------------+
18370/// ```
18371pub trait VpsubuswEmitter<A, B, C> {
18372    fn vpsubusw(&mut self, op0: A, op1: B, op2: C);
18373}
18374
18375impl<'a> VpsubuswEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
18376    fn vpsubusw(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
18377        self.emit(
18378            VPSUBUSW128RRR,
18379            op0.as_operand(),
18380            op1.as_operand(),
18381            op2.as_operand(),
18382            &NOREG,
18383        );
18384    }
18385}
18386
18387impl<'a> VpsubuswEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
18388    fn vpsubusw(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
18389        self.emit(
18390            VPSUBUSW128RRM,
18391            op0.as_operand(),
18392            op1.as_operand(),
18393            op2.as_operand(),
18394            &NOREG,
18395        );
18396    }
18397}
18398
18399impl<'a> VpsubuswEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
18400    fn vpsubusw(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
18401        self.emit(
18402            VPSUBUSW256RRR,
18403            op0.as_operand(),
18404            op1.as_operand(),
18405            op2.as_operand(),
18406            &NOREG,
18407        );
18408    }
18409}
18410
18411impl<'a> VpsubuswEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
18412    fn vpsubusw(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
18413        self.emit(
18414            VPSUBUSW256RRM,
18415            op0.as_operand(),
18416            op1.as_operand(),
18417            op2.as_operand(),
18418            &NOREG,
18419        );
18420    }
18421}
18422
18423impl<'a> VpsubuswEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
18424    fn vpsubusw(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
18425        self.emit(
18426            VPSUBUSW512RRR,
18427            op0.as_operand(),
18428            op1.as_operand(),
18429            op2.as_operand(),
18430            &NOREG,
18431        );
18432    }
18433}
18434
18435impl<'a> VpsubuswEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
18436    fn vpsubusw(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
18437        self.emit(
18438            VPSUBUSW512RRM,
18439            op0.as_operand(),
18440            op1.as_operand(),
18441            op2.as_operand(),
18442            &NOREG,
18443        );
18444    }
18445}
18446
18447/// `VPSUBUSW_MASK`.
18448///
18449/// Supported operand variants:
18450///
18451/// ```text
18452/// +---+---------------+
18453/// | # | Operands      |
18454/// +---+---------------+
18455/// | 1 | Xmm, Xmm, Mem |
18456/// | 2 | Xmm, Xmm, Xmm |
18457/// | 3 | Ymm, Ymm, Mem |
18458/// | 4 | Ymm, Ymm, Ymm |
18459/// | 5 | Zmm, Zmm, Mem |
18460/// | 6 | Zmm, Zmm, Zmm |
18461/// +---+---------------+
18462/// ```
18463pub trait VpsubuswMaskEmitter<A, B, C> {
18464    fn vpsubusw_mask(&mut self, op0: A, op1: B, op2: C);
18465}
18466
18467impl<'a> VpsubuswMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
18468    fn vpsubusw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
18469        self.emit(
18470            VPSUBUSW128RRR_MASK,
18471            op0.as_operand(),
18472            op1.as_operand(),
18473            op2.as_operand(),
18474            &NOREG,
18475        );
18476    }
18477}
18478
18479impl<'a> VpsubuswMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
18480    fn vpsubusw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
18481        self.emit(
18482            VPSUBUSW128RRM_MASK,
18483            op0.as_operand(),
18484            op1.as_operand(),
18485            op2.as_operand(),
18486            &NOREG,
18487        );
18488    }
18489}
18490
18491impl<'a> VpsubuswMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
18492    fn vpsubusw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
18493        self.emit(
18494            VPSUBUSW256RRR_MASK,
18495            op0.as_operand(),
18496            op1.as_operand(),
18497            op2.as_operand(),
18498            &NOREG,
18499        );
18500    }
18501}
18502
18503impl<'a> VpsubuswMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
18504    fn vpsubusw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
18505        self.emit(
18506            VPSUBUSW256RRM_MASK,
18507            op0.as_operand(),
18508            op1.as_operand(),
18509            op2.as_operand(),
18510            &NOREG,
18511        );
18512    }
18513}
18514
18515impl<'a> VpsubuswMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
18516    fn vpsubusw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
18517        self.emit(
18518            VPSUBUSW512RRR_MASK,
18519            op0.as_operand(),
18520            op1.as_operand(),
18521            op2.as_operand(),
18522            &NOREG,
18523        );
18524    }
18525}
18526
18527impl<'a> VpsubuswMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
18528    fn vpsubusw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
18529        self.emit(
18530            VPSUBUSW512RRM_MASK,
18531            op0.as_operand(),
18532            op1.as_operand(),
18533            op2.as_operand(),
18534            &NOREG,
18535        );
18536    }
18537}
18538
18539/// `VPSUBUSW_MASKZ`.
18540///
18541/// Supported operand variants:
18542///
18543/// ```text
18544/// +---+---------------+
18545/// | # | Operands      |
18546/// +---+---------------+
18547/// | 1 | Xmm, Xmm, Mem |
18548/// | 2 | Xmm, Xmm, Xmm |
18549/// | 3 | Ymm, Ymm, Mem |
18550/// | 4 | Ymm, Ymm, Ymm |
18551/// | 5 | Zmm, Zmm, Mem |
18552/// | 6 | Zmm, Zmm, Zmm |
18553/// +---+---------------+
18554/// ```
18555pub trait VpsubuswMaskzEmitter<A, B, C> {
18556    fn vpsubusw_maskz(&mut self, op0: A, op1: B, op2: C);
18557}
18558
18559impl<'a> VpsubuswMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
18560    fn vpsubusw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
18561        self.emit(
18562            VPSUBUSW128RRR_MASKZ,
18563            op0.as_operand(),
18564            op1.as_operand(),
18565            op2.as_operand(),
18566            &NOREG,
18567        );
18568    }
18569}
18570
18571impl<'a> VpsubuswMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
18572    fn vpsubusw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
18573        self.emit(
18574            VPSUBUSW128RRM_MASKZ,
18575            op0.as_operand(),
18576            op1.as_operand(),
18577            op2.as_operand(),
18578            &NOREG,
18579        );
18580    }
18581}
18582
18583impl<'a> VpsubuswMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
18584    fn vpsubusw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
18585        self.emit(
18586            VPSUBUSW256RRR_MASKZ,
18587            op0.as_operand(),
18588            op1.as_operand(),
18589            op2.as_operand(),
18590            &NOREG,
18591        );
18592    }
18593}
18594
18595impl<'a> VpsubuswMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
18596    fn vpsubusw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
18597        self.emit(
18598            VPSUBUSW256RRM_MASKZ,
18599            op0.as_operand(),
18600            op1.as_operand(),
18601            op2.as_operand(),
18602            &NOREG,
18603        );
18604    }
18605}
18606
18607impl<'a> VpsubuswMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
18608    fn vpsubusw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
18609        self.emit(
18610            VPSUBUSW512RRR_MASKZ,
18611            op0.as_operand(),
18612            op1.as_operand(),
18613            op2.as_operand(),
18614            &NOREG,
18615        );
18616    }
18617}
18618
18619impl<'a> VpsubuswMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
18620    fn vpsubusw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
18621        self.emit(
18622            VPSUBUSW512RRM_MASKZ,
18623            op0.as_operand(),
18624            op1.as_operand(),
18625            op2.as_operand(),
18626            &NOREG,
18627        );
18628    }
18629}
18630
18631/// `VPSUBW`.
18632///
18633/// Supported operand variants:
18634///
18635/// ```text
18636/// +---+---------------+
18637/// | # | Operands      |
18638/// +---+---------------+
18639/// | 1 | Xmm, Xmm, Mem |
18640/// | 2 | Xmm, Xmm, Xmm |
18641/// | 3 | Ymm, Ymm, Mem |
18642/// | 4 | Ymm, Ymm, Ymm |
18643/// | 5 | Zmm, Zmm, Mem |
18644/// | 6 | Zmm, Zmm, Zmm |
18645/// +---+---------------+
18646/// ```
18647pub trait VpsubwEmitter<A, B, C> {
18648    fn vpsubw(&mut self, op0: A, op1: B, op2: C);
18649}
18650
18651impl<'a> VpsubwEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
18652    fn vpsubw(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
18653        self.emit(
18654            VPSUBW128RRR,
18655            op0.as_operand(),
18656            op1.as_operand(),
18657            op2.as_operand(),
18658            &NOREG,
18659        );
18660    }
18661}
18662
18663impl<'a> VpsubwEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
18664    fn vpsubw(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
18665        self.emit(
18666            VPSUBW128RRM,
18667            op0.as_operand(),
18668            op1.as_operand(),
18669            op2.as_operand(),
18670            &NOREG,
18671        );
18672    }
18673}
18674
18675impl<'a> VpsubwEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
18676    fn vpsubw(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
18677        self.emit(
18678            VPSUBW256RRR,
18679            op0.as_operand(),
18680            op1.as_operand(),
18681            op2.as_operand(),
18682            &NOREG,
18683        );
18684    }
18685}
18686
18687impl<'a> VpsubwEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
18688    fn vpsubw(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
18689        self.emit(
18690            VPSUBW256RRM,
18691            op0.as_operand(),
18692            op1.as_operand(),
18693            op2.as_operand(),
18694            &NOREG,
18695        );
18696    }
18697}
18698
18699impl<'a> VpsubwEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
18700    fn vpsubw(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
18701        self.emit(
18702            VPSUBW512RRR,
18703            op0.as_operand(),
18704            op1.as_operand(),
18705            op2.as_operand(),
18706            &NOREG,
18707        );
18708    }
18709}
18710
18711impl<'a> VpsubwEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
18712    fn vpsubw(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
18713        self.emit(
18714            VPSUBW512RRM,
18715            op0.as_operand(),
18716            op1.as_operand(),
18717            op2.as_operand(),
18718            &NOREG,
18719        );
18720    }
18721}
18722
18723/// `VPSUBW_MASK`.
18724///
18725/// Supported operand variants:
18726///
18727/// ```text
18728/// +---+---------------+
18729/// | # | Operands      |
18730/// +---+---------------+
18731/// | 1 | Xmm, Xmm, Mem |
18732/// | 2 | Xmm, Xmm, Xmm |
18733/// | 3 | Ymm, Ymm, Mem |
18734/// | 4 | Ymm, Ymm, Ymm |
18735/// | 5 | Zmm, Zmm, Mem |
18736/// | 6 | Zmm, Zmm, Zmm |
18737/// +---+---------------+
18738/// ```
18739pub trait VpsubwMaskEmitter<A, B, C> {
18740    fn vpsubw_mask(&mut self, op0: A, op1: B, op2: C);
18741}
18742
18743impl<'a> VpsubwMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
18744    fn vpsubw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
18745        self.emit(
18746            VPSUBW128RRR_MASK,
18747            op0.as_operand(),
18748            op1.as_operand(),
18749            op2.as_operand(),
18750            &NOREG,
18751        );
18752    }
18753}
18754
18755impl<'a> VpsubwMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
18756    fn vpsubw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
18757        self.emit(
18758            VPSUBW128RRM_MASK,
18759            op0.as_operand(),
18760            op1.as_operand(),
18761            op2.as_operand(),
18762            &NOREG,
18763        );
18764    }
18765}
18766
18767impl<'a> VpsubwMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
18768    fn vpsubw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
18769        self.emit(
18770            VPSUBW256RRR_MASK,
18771            op0.as_operand(),
18772            op1.as_operand(),
18773            op2.as_operand(),
18774            &NOREG,
18775        );
18776    }
18777}
18778
18779impl<'a> VpsubwMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
18780    fn vpsubw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
18781        self.emit(
18782            VPSUBW256RRM_MASK,
18783            op0.as_operand(),
18784            op1.as_operand(),
18785            op2.as_operand(),
18786            &NOREG,
18787        );
18788    }
18789}
18790
18791impl<'a> VpsubwMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
18792    fn vpsubw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
18793        self.emit(
18794            VPSUBW512RRR_MASK,
18795            op0.as_operand(),
18796            op1.as_operand(),
18797            op2.as_operand(),
18798            &NOREG,
18799        );
18800    }
18801}
18802
18803impl<'a> VpsubwMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
18804    fn vpsubw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
18805        self.emit(
18806            VPSUBW512RRM_MASK,
18807            op0.as_operand(),
18808            op1.as_operand(),
18809            op2.as_operand(),
18810            &NOREG,
18811        );
18812    }
18813}
18814
18815/// `VPSUBW_MASKZ`.
18816///
18817/// Supported operand variants:
18818///
18819/// ```text
18820/// +---+---------------+
18821/// | # | Operands      |
18822/// +---+---------------+
18823/// | 1 | Xmm, Xmm, Mem |
18824/// | 2 | Xmm, Xmm, Xmm |
18825/// | 3 | Ymm, Ymm, Mem |
18826/// | 4 | Ymm, Ymm, Ymm |
18827/// | 5 | Zmm, Zmm, Mem |
18828/// | 6 | Zmm, Zmm, Zmm |
18829/// +---+---------------+
18830/// ```
18831pub trait VpsubwMaskzEmitter<A, B, C> {
18832    fn vpsubw_maskz(&mut self, op0: A, op1: B, op2: C);
18833}
18834
18835impl<'a> VpsubwMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
18836    fn vpsubw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
18837        self.emit(
18838            VPSUBW128RRR_MASKZ,
18839            op0.as_operand(),
18840            op1.as_operand(),
18841            op2.as_operand(),
18842            &NOREG,
18843        );
18844    }
18845}
18846
18847impl<'a> VpsubwMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
18848    fn vpsubw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
18849        self.emit(
18850            VPSUBW128RRM_MASKZ,
18851            op0.as_operand(),
18852            op1.as_operand(),
18853            op2.as_operand(),
18854            &NOREG,
18855        );
18856    }
18857}
18858
18859impl<'a> VpsubwMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
18860    fn vpsubw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
18861        self.emit(
18862            VPSUBW256RRR_MASKZ,
18863            op0.as_operand(),
18864            op1.as_operand(),
18865            op2.as_operand(),
18866            &NOREG,
18867        );
18868    }
18869}
18870
18871impl<'a> VpsubwMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
18872    fn vpsubw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
18873        self.emit(
18874            VPSUBW256RRM_MASKZ,
18875            op0.as_operand(),
18876            op1.as_operand(),
18877            op2.as_operand(),
18878            &NOREG,
18879        );
18880    }
18881}
18882
18883impl<'a> VpsubwMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
18884    fn vpsubw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
18885        self.emit(
18886            VPSUBW512RRR_MASKZ,
18887            op0.as_operand(),
18888            op1.as_operand(),
18889            op2.as_operand(),
18890            &NOREG,
18891        );
18892    }
18893}
18894
18895impl<'a> VpsubwMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
18896    fn vpsubw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
18897        self.emit(
18898            VPSUBW512RRM_MASKZ,
18899            op0.as_operand(),
18900            op1.as_operand(),
18901            op2.as_operand(),
18902            &NOREG,
18903        );
18904    }
18905}
18906
18907/// `VPTESTMB`.
18908///
18909/// Supported operand variants:
18910///
18911/// ```text
18912/// +---+----------------+
18913/// | # | Operands       |
18914/// +---+----------------+
18915/// | 1 | KReg, Xmm, Mem |
18916/// | 2 | KReg, Xmm, Xmm |
18917/// | 3 | KReg, Ymm, Mem |
18918/// | 4 | KReg, Ymm, Ymm |
18919/// | 5 | KReg, Zmm, Mem |
18920/// | 6 | KReg, Zmm, Zmm |
18921/// +---+----------------+
18922/// ```
18923pub trait VptestmbEmitter<A, B, C> {
18924    fn vptestmb(&mut self, op0: A, op1: B, op2: C);
18925}
18926
18927impl<'a> VptestmbEmitter<KReg, Xmm, Xmm> for Assembler<'a> {
18928    fn vptestmb(&mut self, op0: KReg, op1: Xmm, op2: Xmm) {
18929        self.emit(
18930            VPTESTMB128KRR,
18931            op0.as_operand(),
18932            op1.as_operand(),
18933            op2.as_operand(),
18934            &NOREG,
18935        );
18936    }
18937}
18938
18939impl<'a> VptestmbEmitter<KReg, Xmm, Mem> for Assembler<'a> {
18940    fn vptestmb(&mut self, op0: KReg, op1: Xmm, op2: Mem) {
18941        self.emit(
18942            VPTESTMB128KRM,
18943            op0.as_operand(),
18944            op1.as_operand(),
18945            op2.as_operand(),
18946            &NOREG,
18947        );
18948    }
18949}
18950
18951impl<'a> VptestmbEmitter<KReg, Ymm, Ymm> for Assembler<'a> {
18952    fn vptestmb(&mut self, op0: KReg, op1: Ymm, op2: Ymm) {
18953        self.emit(
18954            VPTESTMB256KRR,
18955            op0.as_operand(),
18956            op1.as_operand(),
18957            op2.as_operand(),
18958            &NOREG,
18959        );
18960    }
18961}
18962
18963impl<'a> VptestmbEmitter<KReg, Ymm, Mem> for Assembler<'a> {
18964    fn vptestmb(&mut self, op0: KReg, op1: Ymm, op2: Mem) {
18965        self.emit(
18966            VPTESTMB256KRM,
18967            op0.as_operand(),
18968            op1.as_operand(),
18969            op2.as_operand(),
18970            &NOREG,
18971        );
18972    }
18973}
18974
18975impl<'a> VptestmbEmitter<KReg, Zmm, Zmm> for Assembler<'a> {
18976    fn vptestmb(&mut self, op0: KReg, op1: Zmm, op2: Zmm) {
18977        self.emit(
18978            VPTESTMB512KRR,
18979            op0.as_operand(),
18980            op1.as_operand(),
18981            op2.as_operand(),
18982            &NOREG,
18983        );
18984    }
18985}
18986
18987impl<'a> VptestmbEmitter<KReg, Zmm, Mem> for Assembler<'a> {
18988    fn vptestmb(&mut self, op0: KReg, op1: Zmm, op2: Mem) {
18989        self.emit(
18990            VPTESTMB512KRM,
18991            op0.as_operand(),
18992            op1.as_operand(),
18993            op2.as_operand(),
18994            &NOREG,
18995        );
18996    }
18997}
18998
18999/// `VPTESTMB_MASK`.
19000///
19001/// Supported operand variants:
19002///
19003/// ```text
19004/// +---+----------------+
19005/// | # | Operands       |
19006/// +---+----------------+
19007/// | 1 | KReg, Xmm, Mem |
19008/// | 2 | KReg, Xmm, Xmm |
19009/// | 3 | KReg, Ymm, Mem |
19010/// | 4 | KReg, Ymm, Ymm |
19011/// | 5 | KReg, Zmm, Mem |
19012/// | 6 | KReg, Zmm, Zmm |
19013/// +---+----------------+
19014/// ```
19015pub trait VptestmbMaskEmitter<A, B, C> {
19016    fn vptestmb_mask(&mut self, op0: A, op1: B, op2: C);
19017}
19018
19019impl<'a> VptestmbMaskEmitter<KReg, Xmm, Xmm> for Assembler<'a> {
19020    fn vptestmb_mask(&mut self, op0: KReg, op1: Xmm, op2: Xmm) {
19021        self.emit(
19022            VPTESTMB128KRR_MASK,
19023            op0.as_operand(),
19024            op1.as_operand(),
19025            op2.as_operand(),
19026            &NOREG,
19027        );
19028    }
19029}
19030
19031impl<'a> VptestmbMaskEmitter<KReg, Xmm, Mem> for Assembler<'a> {
19032    fn vptestmb_mask(&mut self, op0: KReg, op1: Xmm, op2: Mem) {
19033        self.emit(
19034            VPTESTMB128KRM_MASK,
19035            op0.as_operand(),
19036            op1.as_operand(),
19037            op2.as_operand(),
19038            &NOREG,
19039        );
19040    }
19041}
19042
19043impl<'a> VptestmbMaskEmitter<KReg, Ymm, Ymm> for Assembler<'a> {
19044    fn vptestmb_mask(&mut self, op0: KReg, op1: Ymm, op2: Ymm) {
19045        self.emit(
19046            VPTESTMB256KRR_MASK,
19047            op0.as_operand(),
19048            op1.as_operand(),
19049            op2.as_operand(),
19050            &NOREG,
19051        );
19052    }
19053}
19054
19055impl<'a> VptestmbMaskEmitter<KReg, Ymm, Mem> for Assembler<'a> {
19056    fn vptestmb_mask(&mut self, op0: KReg, op1: Ymm, op2: Mem) {
19057        self.emit(
19058            VPTESTMB256KRM_MASK,
19059            op0.as_operand(),
19060            op1.as_operand(),
19061            op2.as_operand(),
19062            &NOREG,
19063        );
19064    }
19065}
19066
19067impl<'a> VptestmbMaskEmitter<KReg, Zmm, Zmm> for Assembler<'a> {
19068    fn vptestmb_mask(&mut self, op0: KReg, op1: Zmm, op2: Zmm) {
19069        self.emit(
19070            VPTESTMB512KRR_MASK,
19071            op0.as_operand(),
19072            op1.as_operand(),
19073            op2.as_operand(),
19074            &NOREG,
19075        );
19076    }
19077}
19078
19079impl<'a> VptestmbMaskEmitter<KReg, Zmm, Mem> for Assembler<'a> {
19080    fn vptestmb_mask(&mut self, op0: KReg, op1: Zmm, op2: Mem) {
19081        self.emit(
19082            VPTESTMB512KRM_MASK,
19083            op0.as_operand(),
19084            op1.as_operand(),
19085            op2.as_operand(),
19086            &NOREG,
19087        );
19088    }
19089}
19090
19091/// `VPTESTMW`.
19092///
19093/// Supported operand variants:
19094///
19095/// ```text
19096/// +---+----------------+
19097/// | # | Operands       |
19098/// +---+----------------+
19099/// | 1 | KReg, Xmm, Mem |
19100/// | 2 | KReg, Xmm, Xmm |
19101/// | 3 | KReg, Ymm, Mem |
19102/// | 4 | KReg, Ymm, Ymm |
19103/// | 5 | KReg, Zmm, Mem |
19104/// | 6 | KReg, Zmm, Zmm |
19105/// +---+----------------+
19106/// ```
19107pub trait VptestmwEmitter<A, B, C> {
19108    fn vptestmw(&mut self, op0: A, op1: B, op2: C);
19109}
19110
19111impl<'a> VptestmwEmitter<KReg, Xmm, Xmm> for Assembler<'a> {
19112    fn vptestmw(&mut self, op0: KReg, op1: Xmm, op2: Xmm) {
19113        self.emit(
19114            VPTESTMW128KRR,
19115            op0.as_operand(),
19116            op1.as_operand(),
19117            op2.as_operand(),
19118            &NOREG,
19119        );
19120    }
19121}
19122
19123impl<'a> VptestmwEmitter<KReg, Xmm, Mem> for Assembler<'a> {
19124    fn vptestmw(&mut self, op0: KReg, op1: Xmm, op2: Mem) {
19125        self.emit(
19126            VPTESTMW128KRM,
19127            op0.as_operand(),
19128            op1.as_operand(),
19129            op2.as_operand(),
19130            &NOREG,
19131        );
19132    }
19133}
19134
19135impl<'a> VptestmwEmitter<KReg, Ymm, Ymm> for Assembler<'a> {
19136    fn vptestmw(&mut self, op0: KReg, op1: Ymm, op2: Ymm) {
19137        self.emit(
19138            VPTESTMW256KRR,
19139            op0.as_operand(),
19140            op1.as_operand(),
19141            op2.as_operand(),
19142            &NOREG,
19143        );
19144    }
19145}
19146
19147impl<'a> VptestmwEmitter<KReg, Ymm, Mem> for Assembler<'a> {
19148    fn vptestmw(&mut self, op0: KReg, op1: Ymm, op2: Mem) {
19149        self.emit(
19150            VPTESTMW256KRM,
19151            op0.as_operand(),
19152            op1.as_operand(),
19153            op2.as_operand(),
19154            &NOREG,
19155        );
19156    }
19157}
19158
19159impl<'a> VptestmwEmitter<KReg, Zmm, Zmm> for Assembler<'a> {
19160    fn vptestmw(&mut self, op0: KReg, op1: Zmm, op2: Zmm) {
19161        self.emit(
19162            VPTESTMW512KRR,
19163            op0.as_operand(),
19164            op1.as_operand(),
19165            op2.as_operand(),
19166            &NOREG,
19167        );
19168    }
19169}
19170
19171impl<'a> VptestmwEmitter<KReg, Zmm, Mem> for Assembler<'a> {
19172    fn vptestmw(&mut self, op0: KReg, op1: Zmm, op2: Mem) {
19173        self.emit(
19174            VPTESTMW512KRM,
19175            op0.as_operand(),
19176            op1.as_operand(),
19177            op2.as_operand(),
19178            &NOREG,
19179        );
19180    }
19181}
19182
19183/// `VPTESTMW_MASK`.
19184///
19185/// Supported operand variants:
19186///
19187/// ```text
19188/// +---+----------------+
19189/// | # | Operands       |
19190/// +---+----------------+
19191/// | 1 | KReg, Xmm, Mem |
19192/// | 2 | KReg, Xmm, Xmm |
19193/// | 3 | KReg, Ymm, Mem |
19194/// | 4 | KReg, Ymm, Ymm |
19195/// | 5 | KReg, Zmm, Mem |
19196/// | 6 | KReg, Zmm, Zmm |
19197/// +---+----------------+
19198/// ```
19199pub trait VptestmwMaskEmitter<A, B, C> {
19200    fn vptestmw_mask(&mut self, op0: A, op1: B, op2: C);
19201}
19202
19203impl<'a> VptestmwMaskEmitter<KReg, Xmm, Xmm> for Assembler<'a> {
19204    fn vptestmw_mask(&mut self, op0: KReg, op1: Xmm, op2: Xmm) {
19205        self.emit(
19206            VPTESTMW128KRR_MASK,
19207            op0.as_operand(),
19208            op1.as_operand(),
19209            op2.as_operand(),
19210            &NOREG,
19211        );
19212    }
19213}
19214
19215impl<'a> VptestmwMaskEmitter<KReg, Xmm, Mem> for Assembler<'a> {
19216    fn vptestmw_mask(&mut self, op0: KReg, op1: Xmm, op2: Mem) {
19217        self.emit(
19218            VPTESTMW128KRM_MASK,
19219            op0.as_operand(),
19220            op1.as_operand(),
19221            op2.as_operand(),
19222            &NOREG,
19223        );
19224    }
19225}
19226
19227impl<'a> VptestmwMaskEmitter<KReg, Ymm, Ymm> for Assembler<'a> {
19228    fn vptestmw_mask(&mut self, op0: KReg, op1: Ymm, op2: Ymm) {
19229        self.emit(
19230            VPTESTMW256KRR_MASK,
19231            op0.as_operand(),
19232            op1.as_operand(),
19233            op2.as_operand(),
19234            &NOREG,
19235        );
19236    }
19237}
19238
19239impl<'a> VptestmwMaskEmitter<KReg, Ymm, Mem> for Assembler<'a> {
19240    fn vptestmw_mask(&mut self, op0: KReg, op1: Ymm, op2: Mem) {
19241        self.emit(
19242            VPTESTMW256KRM_MASK,
19243            op0.as_operand(),
19244            op1.as_operand(),
19245            op2.as_operand(),
19246            &NOREG,
19247        );
19248    }
19249}
19250
19251impl<'a> VptestmwMaskEmitter<KReg, Zmm, Zmm> for Assembler<'a> {
19252    fn vptestmw_mask(&mut self, op0: KReg, op1: Zmm, op2: Zmm) {
19253        self.emit(
19254            VPTESTMW512KRR_MASK,
19255            op0.as_operand(),
19256            op1.as_operand(),
19257            op2.as_operand(),
19258            &NOREG,
19259        );
19260    }
19261}
19262
19263impl<'a> VptestmwMaskEmitter<KReg, Zmm, Mem> for Assembler<'a> {
19264    fn vptestmw_mask(&mut self, op0: KReg, op1: Zmm, op2: Mem) {
19265        self.emit(
19266            VPTESTMW512KRM_MASK,
19267            op0.as_operand(),
19268            op1.as_operand(),
19269            op2.as_operand(),
19270            &NOREG,
19271        );
19272    }
19273}
19274
19275/// `VPTESTNMB`.
19276///
19277/// Supported operand variants:
19278///
19279/// ```text
19280/// +---+----------------+
19281/// | # | Operands       |
19282/// +---+----------------+
19283/// | 1 | KReg, Xmm, Mem |
19284/// | 2 | KReg, Xmm, Xmm |
19285/// | 3 | KReg, Ymm, Mem |
19286/// | 4 | KReg, Ymm, Ymm |
19287/// | 5 | KReg, Zmm, Mem |
19288/// | 6 | KReg, Zmm, Zmm |
19289/// +---+----------------+
19290/// ```
19291pub trait VptestnmbEmitter<A, B, C> {
19292    fn vptestnmb(&mut self, op0: A, op1: B, op2: C);
19293}
19294
19295impl<'a> VptestnmbEmitter<KReg, Xmm, Xmm> for Assembler<'a> {
19296    fn vptestnmb(&mut self, op0: KReg, op1: Xmm, op2: Xmm) {
19297        self.emit(
19298            VPTESTNMB128KRR,
19299            op0.as_operand(),
19300            op1.as_operand(),
19301            op2.as_operand(),
19302            &NOREG,
19303        );
19304    }
19305}
19306
19307impl<'a> VptestnmbEmitter<KReg, Xmm, Mem> for Assembler<'a> {
19308    fn vptestnmb(&mut self, op0: KReg, op1: Xmm, op2: Mem) {
19309        self.emit(
19310            VPTESTNMB128KRM,
19311            op0.as_operand(),
19312            op1.as_operand(),
19313            op2.as_operand(),
19314            &NOREG,
19315        );
19316    }
19317}
19318
19319impl<'a> VptestnmbEmitter<KReg, Ymm, Ymm> for Assembler<'a> {
19320    fn vptestnmb(&mut self, op0: KReg, op1: Ymm, op2: Ymm) {
19321        self.emit(
19322            VPTESTNMB256KRR,
19323            op0.as_operand(),
19324            op1.as_operand(),
19325            op2.as_operand(),
19326            &NOREG,
19327        );
19328    }
19329}
19330
19331impl<'a> VptestnmbEmitter<KReg, Ymm, Mem> for Assembler<'a> {
19332    fn vptestnmb(&mut self, op0: KReg, op1: Ymm, op2: Mem) {
19333        self.emit(
19334            VPTESTNMB256KRM,
19335            op0.as_operand(),
19336            op1.as_operand(),
19337            op2.as_operand(),
19338            &NOREG,
19339        );
19340    }
19341}
19342
19343impl<'a> VptestnmbEmitter<KReg, Zmm, Zmm> for Assembler<'a> {
19344    fn vptestnmb(&mut self, op0: KReg, op1: Zmm, op2: Zmm) {
19345        self.emit(
19346            VPTESTNMB512KRR,
19347            op0.as_operand(),
19348            op1.as_operand(),
19349            op2.as_operand(),
19350            &NOREG,
19351        );
19352    }
19353}
19354
19355impl<'a> VptestnmbEmitter<KReg, Zmm, Mem> for Assembler<'a> {
19356    fn vptestnmb(&mut self, op0: KReg, op1: Zmm, op2: Mem) {
19357        self.emit(
19358            VPTESTNMB512KRM,
19359            op0.as_operand(),
19360            op1.as_operand(),
19361            op2.as_operand(),
19362            &NOREG,
19363        );
19364    }
19365}
19366
19367/// `VPTESTNMB_MASK`.
19368///
19369/// Supported operand variants:
19370///
19371/// ```text
19372/// +---+----------------+
19373/// | # | Operands       |
19374/// +---+----------------+
19375/// | 1 | KReg, Xmm, Mem |
19376/// | 2 | KReg, Xmm, Xmm |
19377/// | 3 | KReg, Ymm, Mem |
19378/// | 4 | KReg, Ymm, Ymm |
19379/// | 5 | KReg, Zmm, Mem |
19380/// | 6 | KReg, Zmm, Zmm |
19381/// +---+----------------+
19382/// ```
19383pub trait VptestnmbMaskEmitter<A, B, C> {
19384    fn vptestnmb_mask(&mut self, op0: A, op1: B, op2: C);
19385}
19386
19387impl<'a> VptestnmbMaskEmitter<KReg, Xmm, Xmm> for Assembler<'a> {
19388    fn vptestnmb_mask(&mut self, op0: KReg, op1: Xmm, op2: Xmm) {
19389        self.emit(
19390            VPTESTNMB128KRR_MASK,
19391            op0.as_operand(),
19392            op1.as_operand(),
19393            op2.as_operand(),
19394            &NOREG,
19395        );
19396    }
19397}
19398
19399impl<'a> VptestnmbMaskEmitter<KReg, Xmm, Mem> for Assembler<'a> {
19400    fn vptestnmb_mask(&mut self, op0: KReg, op1: Xmm, op2: Mem) {
19401        self.emit(
19402            VPTESTNMB128KRM_MASK,
19403            op0.as_operand(),
19404            op1.as_operand(),
19405            op2.as_operand(),
19406            &NOREG,
19407        );
19408    }
19409}
19410
19411impl<'a> VptestnmbMaskEmitter<KReg, Ymm, Ymm> for Assembler<'a> {
19412    fn vptestnmb_mask(&mut self, op0: KReg, op1: Ymm, op2: Ymm) {
19413        self.emit(
19414            VPTESTNMB256KRR_MASK,
19415            op0.as_operand(),
19416            op1.as_operand(),
19417            op2.as_operand(),
19418            &NOREG,
19419        );
19420    }
19421}
19422
19423impl<'a> VptestnmbMaskEmitter<KReg, Ymm, Mem> for Assembler<'a> {
19424    fn vptestnmb_mask(&mut self, op0: KReg, op1: Ymm, op2: Mem) {
19425        self.emit(
19426            VPTESTNMB256KRM_MASK,
19427            op0.as_operand(),
19428            op1.as_operand(),
19429            op2.as_operand(),
19430            &NOREG,
19431        );
19432    }
19433}
19434
19435impl<'a> VptestnmbMaskEmitter<KReg, Zmm, Zmm> for Assembler<'a> {
19436    fn vptestnmb_mask(&mut self, op0: KReg, op1: Zmm, op2: Zmm) {
19437        self.emit(
19438            VPTESTNMB512KRR_MASK,
19439            op0.as_operand(),
19440            op1.as_operand(),
19441            op2.as_operand(),
19442            &NOREG,
19443        );
19444    }
19445}
19446
19447impl<'a> VptestnmbMaskEmitter<KReg, Zmm, Mem> for Assembler<'a> {
19448    fn vptestnmb_mask(&mut self, op0: KReg, op1: Zmm, op2: Mem) {
19449        self.emit(
19450            VPTESTNMB512KRM_MASK,
19451            op0.as_operand(),
19452            op1.as_operand(),
19453            op2.as_operand(),
19454            &NOREG,
19455        );
19456    }
19457}
19458
19459/// `VPTESTNMW`.
19460///
19461/// Supported operand variants:
19462///
19463/// ```text
19464/// +---+----------------+
19465/// | # | Operands       |
19466/// +---+----------------+
19467/// | 1 | KReg, Xmm, Mem |
19468/// | 2 | KReg, Xmm, Xmm |
19469/// | 3 | KReg, Ymm, Mem |
19470/// | 4 | KReg, Ymm, Ymm |
19471/// | 5 | KReg, Zmm, Mem |
19472/// | 6 | KReg, Zmm, Zmm |
19473/// +---+----------------+
19474/// ```
19475pub trait VptestnmwEmitter<A, B, C> {
19476    fn vptestnmw(&mut self, op0: A, op1: B, op2: C);
19477}
19478
19479impl<'a> VptestnmwEmitter<KReg, Xmm, Xmm> for Assembler<'a> {
19480    fn vptestnmw(&mut self, op0: KReg, op1: Xmm, op2: Xmm) {
19481        self.emit(
19482            VPTESTNMW128KRR,
19483            op0.as_operand(),
19484            op1.as_operand(),
19485            op2.as_operand(),
19486            &NOREG,
19487        );
19488    }
19489}
19490
19491impl<'a> VptestnmwEmitter<KReg, Xmm, Mem> for Assembler<'a> {
19492    fn vptestnmw(&mut self, op0: KReg, op1: Xmm, op2: Mem) {
19493        self.emit(
19494            VPTESTNMW128KRM,
19495            op0.as_operand(),
19496            op1.as_operand(),
19497            op2.as_operand(),
19498            &NOREG,
19499        );
19500    }
19501}
19502
19503impl<'a> VptestnmwEmitter<KReg, Ymm, Ymm> for Assembler<'a> {
19504    fn vptestnmw(&mut self, op0: KReg, op1: Ymm, op2: Ymm) {
19505        self.emit(
19506            VPTESTNMW256KRR,
19507            op0.as_operand(),
19508            op1.as_operand(),
19509            op2.as_operand(),
19510            &NOREG,
19511        );
19512    }
19513}
19514
19515impl<'a> VptestnmwEmitter<KReg, Ymm, Mem> for Assembler<'a> {
19516    fn vptestnmw(&mut self, op0: KReg, op1: Ymm, op2: Mem) {
19517        self.emit(
19518            VPTESTNMW256KRM,
19519            op0.as_operand(),
19520            op1.as_operand(),
19521            op2.as_operand(),
19522            &NOREG,
19523        );
19524    }
19525}
19526
19527impl<'a> VptestnmwEmitter<KReg, Zmm, Zmm> for Assembler<'a> {
19528    fn vptestnmw(&mut self, op0: KReg, op1: Zmm, op2: Zmm) {
19529        self.emit(
19530            VPTESTNMW512KRR,
19531            op0.as_operand(),
19532            op1.as_operand(),
19533            op2.as_operand(),
19534            &NOREG,
19535        );
19536    }
19537}
19538
19539impl<'a> VptestnmwEmitter<KReg, Zmm, Mem> for Assembler<'a> {
19540    fn vptestnmw(&mut self, op0: KReg, op1: Zmm, op2: Mem) {
19541        self.emit(
19542            VPTESTNMW512KRM,
19543            op0.as_operand(),
19544            op1.as_operand(),
19545            op2.as_operand(),
19546            &NOREG,
19547        );
19548    }
19549}
19550
19551/// `VPTESTNMW_MASK`.
19552///
19553/// Supported operand variants:
19554///
19555/// ```text
19556/// +---+----------------+
19557/// | # | Operands       |
19558/// +---+----------------+
19559/// | 1 | KReg, Xmm, Mem |
19560/// | 2 | KReg, Xmm, Xmm |
19561/// | 3 | KReg, Ymm, Mem |
19562/// | 4 | KReg, Ymm, Ymm |
19563/// | 5 | KReg, Zmm, Mem |
19564/// | 6 | KReg, Zmm, Zmm |
19565/// +---+----------------+
19566/// ```
19567pub trait VptestnmwMaskEmitter<A, B, C> {
19568    fn vptestnmw_mask(&mut self, op0: A, op1: B, op2: C);
19569}
19570
19571impl<'a> VptestnmwMaskEmitter<KReg, Xmm, Xmm> for Assembler<'a> {
19572    fn vptestnmw_mask(&mut self, op0: KReg, op1: Xmm, op2: Xmm) {
19573        self.emit(
19574            VPTESTNMW128KRR_MASK,
19575            op0.as_operand(),
19576            op1.as_operand(),
19577            op2.as_operand(),
19578            &NOREG,
19579        );
19580    }
19581}
19582
19583impl<'a> VptestnmwMaskEmitter<KReg, Xmm, Mem> for Assembler<'a> {
19584    fn vptestnmw_mask(&mut self, op0: KReg, op1: Xmm, op2: Mem) {
19585        self.emit(
19586            VPTESTNMW128KRM_MASK,
19587            op0.as_operand(),
19588            op1.as_operand(),
19589            op2.as_operand(),
19590            &NOREG,
19591        );
19592    }
19593}
19594
19595impl<'a> VptestnmwMaskEmitter<KReg, Ymm, Ymm> for Assembler<'a> {
19596    fn vptestnmw_mask(&mut self, op0: KReg, op1: Ymm, op2: Ymm) {
19597        self.emit(
19598            VPTESTNMW256KRR_MASK,
19599            op0.as_operand(),
19600            op1.as_operand(),
19601            op2.as_operand(),
19602            &NOREG,
19603        );
19604    }
19605}
19606
19607impl<'a> VptestnmwMaskEmitter<KReg, Ymm, Mem> for Assembler<'a> {
19608    fn vptestnmw_mask(&mut self, op0: KReg, op1: Ymm, op2: Mem) {
19609        self.emit(
19610            VPTESTNMW256KRM_MASK,
19611            op0.as_operand(),
19612            op1.as_operand(),
19613            op2.as_operand(),
19614            &NOREG,
19615        );
19616    }
19617}
19618
19619impl<'a> VptestnmwMaskEmitter<KReg, Zmm, Zmm> for Assembler<'a> {
19620    fn vptestnmw_mask(&mut self, op0: KReg, op1: Zmm, op2: Zmm) {
19621        self.emit(
19622            VPTESTNMW512KRR_MASK,
19623            op0.as_operand(),
19624            op1.as_operand(),
19625            op2.as_operand(),
19626            &NOREG,
19627        );
19628    }
19629}
19630
19631impl<'a> VptestnmwMaskEmitter<KReg, Zmm, Mem> for Assembler<'a> {
19632    fn vptestnmw_mask(&mut self, op0: KReg, op1: Zmm, op2: Mem) {
19633        self.emit(
19634            VPTESTNMW512KRM_MASK,
19635            op0.as_operand(),
19636            op1.as_operand(),
19637            op2.as_operand(),
19638            &NOREG,
19639        );
19640    }
19641}
19642
19643/// `VPUNPCKHBW`.
19644///
19645/// Supported operand variants:
19646///
19647/// ```text
19648/// +---+---------------+
19649/// | # | Operands      |
19650/// +---+---------------+
19651/// | 1 | Xmm, Xmm, Mem |
19652/// | 2 | Xmm, Xmm, Xmm |
19653/// | 3 | Ymm, Ymm, Mem |
19654/// | 4 | Ymm, Ymm, Ymm |
19655/// | 5 | Zmm, Zmm, Mem |
19656/// | 6 | Zmm, Zmm, Zmm |
19657/// +---+---------------+
19658/// ```
19659pub trait VpunpckhbwEmitter<A, B, C> {
19660    fn vpunpckhbw(&mut self, op0: A, op1: B, op2: C);
19661}
19662
19663impl<'a> VpunpckhbwEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
19664    fn vpunpckhbw(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
19665        self.emit(
19666            VPUNPCKHBW128RRR,
19667            op0.as_operand(),
19668            op1.as_operand(),
19669            op2.as_operand(),
19670            &NOREG,
19671        );
19672    }
19673}
19674
19675impl<'a> VpunpckhbwEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
19676    fn vpunpckhbw(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
19677        self.emit(
19678            VPUNPCKHBW128RRM,
19679            op0.as_operand(),
19680            op1.as_operand(),
19681            op2.as_operand(),
19682            &NOREG,
19683        );
19684    }
19685}
19686
19687impl<'a> VpunpckhbwEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
19688    fn vpunpckhbw(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
19689        self.emit(
19690            VPUNPCKHBW256RRR,
19691            op0.as_operand(),
19692            op1.as_operand(),
19693            op2.as_operand(),
19694            &NOREG,
19695        );
19696    }
19697}
19698
19699impl<'a> VpunpckhbwEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
19700    fn vpunpckhbw(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
19701        self.emit(
19702            VPUNPCKHBW256RRM,
19703            op0.as_operand(),
19704            op1.as_operand(),
19705            op2.as_operand(),
19706            &NOREG,
19707        );
19708    }
19709}
19710
19711impl<'a> VpunpckhbwEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
19712    fn vpunpckhbw(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
19713        self.emit(
19714            VPUNPCKHBW512RRR,
19715            op0.as_operand(),
19716            op1.as_operand(),
19717            op2.as_operand(),
19718            &NOREG,
19719        );
19720    }
19721}
19722
19723impl<'a> VpunpckhbwEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
19724    fn vpunpckhbw(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
19725        self.emit(
19726            VPUNPCKHBW512RRM,
19727            op0.as_operand(),
19728            op1.as_operand(),
19729            op2.as_operand(),
19730            &NOREG,
19731        );
19732    }
19733}
19734
19735/// `VPUNPCKHBW_MASK`.
19736///
19737/// Supported operand variants:
19738///
19739/// ```text
19740/// +---+---------------+
19741/// | # | Operands      |
19742/// +---+---------------+
19743/// | 1 | Xmm, Xmm, Mem |
19744/// | 2 | Xmm, Xmm, Xmm |
19745/// | 3 | Ymm, Ymm, Mem |
19746/// | 4 | Ymm, Ymm, Ymm |
19747/// | 5 | Zmm, Zmm, Mem |
19748/// | 6 | Zmm, Zmm, Zmm |
19749/// +---+---------------+
19750/// ```
19751pub trait VpunpckhbwMaskEmitter<A, B, C> {
19752    fn vpunpckhbw_mask(&mut self, op0: A, op1: B, op2: C);
19753}
19754
19755impl<'a> VpunpckhbwMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
19756    fn vpunpckhbw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
19757        self.emit(
19758            VPUNPCKHBW128RRR_MASK,
19759            op0.as_operand(),
19760            op1.as_operand(),
19761            op2.as_operand(),
19762            &NOREG,
19763        );
19764    }
19765}
19766
19767impl<'a> VpunpckhbwMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
19768    fn vpunpckhbw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
19769        self.emit(
19770            VPUNPCKHBW128RRM_MASK,
19771            op0.as_operand(),
19772            op1.as_operand(),
19773            op2.as_operand(),
19774            &NOREG,
19775        );
19776    }
19777}
19778
19779impl<'a> VpunpckhbwMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
19780    fn vpunpckhbw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
19781        self.emit(
19782            VPUNPCKHBW256RRR_MASK,
19783            op0.as_operand(),
19784            op1.as_operand(),
19785            op2.as_operand(),
19786            &NOREG,
19787        );
19788    }
19789}
19790
19791impl<'a> VpunpckhbwMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
19792    fn vpunpckhbw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
19793        self.emit(
19794            VPUNPCKHBW256RRM_MASK,
19795            op0.as_operand(),
19796            op1.as_operand(),
19797            op2.as_operand(),
19798            &NOREG,
19799        );
19800    }
19801}
19802
19803impl<'a> VpunpckhbwMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
19804    fn vpunpckhbw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
19805        self.emit(
19806            VPUNPCKHBW512RRR_MASK,
19807            op0.as_operand(),
19808            op1.as_operand(),
19809            op2.as_operand(),
19810            &NOREG,
19811        );
19812    }
19813}
19814
19815impl<'a> VpunpckhbwMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
19816    fn vpunpckhbw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
19817        self.emit(
19818            VPUNPCKHBW512RRM_MASK,
19819            op0.as_operand(),
19820            op1.as_operand(),
19821            op2.as_operand(),
19822            &NOREG,
19823        );
19824    }
19825}
19826
19827/// `VPUNPCKHBW_MASKZ`.
19828///
19829/// Supported operand variants:
19830///
19831/// ```text
19832/// +---+---------------+
19833/// | # | Operands      |
19834/// +---+---------------+
19835/// | 1 | Xmm, Xmm, Mem |
19836/// | 2 | Xmm, Xmm, Xmm |
19837/// | 3 | Ymm, Ymm, Mem |
19838/// | 4 | Ymm, Ymm, Ymm |
19839/// | 5 | Zmm, Zmm, Mem |
19840/// | 6 | Zmm, Zmm, Zmm |
19841/// +---+---------------+
19842/// ```
19843pub trait VpunpckhbwMaskzEmitter<A, B, C> {
19844    fn vpunpckhbw_maskz(&mut self, op0: A, op1: B, op2: C);
19845}
19846
19847impl<'a> VpunpckhbwMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
19848    fn vpunpckhbw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
19849        self.emit(
19850            VPUNPCKHBW128RRR_MASKZ,
19851            op0.as_operand(),
19852            op1.as_operand(),
19853            op2.as_operand(),
19854            &NOREG,
19855        );
19856    }
19857}
19858
19859impl<'a> VpunpckhbwMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
19860    fn vpunpckhbw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
19861        self.emit(
19862            VPUNPCKHBW128RRM_MASKZ,
19863            op0.as_operand(),
19864            op1.as_operand(),
19865            op2.as_operand(),
19866            &NOREG,
19867        );
19868    }
19869}
19870
19871impl<'a> VpunpckhbwMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
19872    fn vpunpckhbw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
19873        self.emit(
19874            VPUNPCKHBW256RRR_MASKZ,
19875            op0.as_operand(),
19876            op1.as_operand(),
19877            op2.as_operand(),
19878            &NOREG,
19879        );
19880    }
19881}
19882
19883impl<'a> VpunpckhbwMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
19884    fn vpunpckhbw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
19885        self.emit(
19886            VPUNPCKHBW256RRM_MASKZ,
19887            op0.as_operand(),
19888            op1.as_operand(),
19889            op2.as_operand(),
19890            &NOREG,
19891        );
19892    }
19893}
19894
19895impl<'a> VpunpckhbwMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
19896    fn vpunpckhbw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
19897        self.emit(
19898            VPUNPCKHBW512RRR_MASKZ,
19899            op0.as_operand(),
19900            op1.as_operand(),
19901            op2.as_operand(),
19902            &NOREG,
19903        );
19904    }
19905}
19906
19907impl<'a> VpunpckhbwMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
19908    fn vpunpckhbw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
19909        self.emit(
19910            VPUNPCKHBW512RRM_MASKZ,
19911            op0.as_operand(),
19912            op1.as_operand(),
19913            op2.as_operand(),
19914            &NOREG,
19915        );
19916    }
19917}
19918
19919/// `VPUNPCKHWD`.
19920///
19921/// Supported operand variants:
19922///
19923/// ```text
19924/// +---+---------------+
19925/// | # | Operands      |
19926/// +---+---------------+
19927/// | 1 | Xmm, Xmm, Mem |
19928/// | 2 | Xmm, Xmm, Xmm |
19929/// | 3 | Ymm, Ymm, Mem |
19930/// | 4 | Ymm, Ymm, Ymm |
19931/// | 5 | Zmm, Zmm, Mem |
19932/// | 6 | Zmm, Zmm, Zmm |
19933/// +---+---------------+
19934/// ```
19935pub trait VpunpckhwdEmitter<A, B, C> {
19936    fn vpunpckhwd(&mut self, op0: A, op1: B, op2: C);
19937}
19938
19939impl<'a> VpunpckhwdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
19940    fn vpunpckhwd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
19941        self.emit(
19942            VPUNPCKHWD128RRR,
19943            op0.as_operand(),
19944            op1.as_operand(),
19945            op2.as_operand(),
19946            &NOREG,
19947        );
19948    }
19949}
19950
19951impl<'a> VpunpckhwdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
19952    fn vpunpckhwd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
19953        self.emit(
19954            VPUNPCKHWD128RRM,
19955            op0.as_operand(),
19956            op1.as_operand(),
19957            op2.as_operand(),
19958            &NOREG,
19959        );
19960    }
19961}
19962
19963impl<'a> VpunpckhwdEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
19964    fn vpunpckhwd(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
19965        self.emit(
19966            VPUNPCKHWD256RRR,
19967            op0.as_operand(),
19968            op1.as_operand(),
19969            op2.as_operand(),
19970            &NOREG,
19971        );
19972    }
19973}
19974
19975impl<'a> VpunpckhwdEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
19976    fn vpunpckhwd(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
19977        self.emit(
19978            VPUNPCKHWD256RRM,
19979            op0.as_operand(),
19980            op1.as_operand(),
19981            op2.as_operand(),
19982            &NOREG,
19983        );
19984    }
19985}
19986
19987impl<'a> VpunpckhwdEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
19988    fn vpunpckhwd(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
19989        self.emit(
19990            VPUNPCKHWD512RRR,
19991            op0.as_operand(),
19992            op1.as_operand(),
19993            op2.as_operand(),
19994            &NOREG,
19995        );
19996    }
19997}
19998
19999impl<'a> VpunpckhwdEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
20000    fn vpunpckhwd(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
20001        self.emit(
20002            VPUNPCKHWD512RRM,
20003            op0.as_operand(),
20004            op1.as_operand(),
20005            op2.as_operand(),
20006            &NOREG,
20007        );
20008    }
20009}
20010
20011/// `VPUNPCKHWD_MASK`.
20012///
20013/// Supported operand variants:
20014///
20015/// ```text
20016/// +---+---------------+
20017/// | # | Operands      |
20018/// +---+---------------+
20019/// | 1 | Xmm, Xmm, Mem |
20020/// | 2 | Xmm, Xmm, Xmm |
20021/// | 3 | Ymm, Ymm, Mem |
20022/// | 4 | Ymm, Ymm, Ymm |
20023/// | 5 | Zmm, Zmm, Mem |
20024/// | 6 | Zmm, Zmm, Zmm |
20025/// +---+---------------+
20026/// ```
20027pub trait VpunpckhwdMaskEmitter<A, B, C> {
20028    fn vpunpckhwd_mask(&mut self, op0: A, op1: B, op2: C);
20029}
20030
20031impl<'a> VpunpckhwdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
20032    fn vpunpckhwd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
20033        self.emit(
20034            VPUNPCKHWD128RRR_MASK,
20035            op0.as_operand(),
20036            op1.as_operand(),
20037            op2.as_operand(),
20038            &NOREG,
20039        );
20040    }
20041}
20042
20043impl<'a> VpunpckhwdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
20044    fn vpunpckhwd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
20045        self.emit(
20046            VPUNPCKHWD128RRM_MASK,
20047            op0.as_operand(),
20048            op1.as_operand(),
20049            op2.as_operand(),
20050            &NOREG,
20051        );
20052    }
20053}
20054
20055impl<'a> VpunpckhwdMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
20056    fn vpunpckhwd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
20057        self.emit(
20058            VPUNPCKHWD256RRR_MASK,
20059            op0.as_operand(),
20060            op1.as_operand(),
20061            op2.as_operand(),
20062            &NOREG,
20063        );
20064    }
20065}
20066
20067impl<'a> VpunpckhwdMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
20068    fn vpunpckhwd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
20069        self.emit(
20070            VPUNPCKHWD256RRM_MASK,
20071            op0.as_operand(),
20072            op1.as_operand(),
20073            op2.as_operand(),
20074            &NOREG,
20075        );
20076    }
20077}
20078
20079impl<'a> VpunpckhwdMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
20080    fn vpunpckhwd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
20081        self.emit(
20082            VPUNPCKHWD512RRR_MASK,
20083            op0.as_operand(),
20084            op1.as_operand(),
20085            op2.as_operand(),
20086            &NOREG,
20087        );
20088    }
20089}
20090
20091impl<'a> VpunpckhwdMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
20092    fn vpunpckhwd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
20093        self.emit(
20094            VPUNPCKHWD512RRM_MASK,
20095            op0.as_operand(),
20096            op1.as_operand(),
20097            op2.as_operand(),
20098            &NOREG,
20099        );
20100    }
20101}
20102
20103/// `VPUNPCKHWD_MASKZ`.
20104///
20105/// Supported operand variants:
20106///
20107/// ```text
20108/// +---+---------------+
20109/// | # | Operands      |
20110/// +---+---------------+
20111/// | 1 | Xmm, Xmm, Mem |
20112/// | 2 | Xmm, Xmm, Xmm |
20113/// | 3 | Ymm, Ymm, Mem |
20114/// | 4 | Ymm, Ymm, Ymm |
20115/// | 5 | Zmm, Zmm, Mem |
20116/// | 6 | Zmm, Zmm, Zmm |
20117/// +---+---------------+
20118/// ```
20119pub trait VpunpckhwdMaskzEmitter<A, B, C> {
20120    fn vpunpckhwd_maskz(&mut self, op0: A, op1: B, op2: C);
20121}
20122
20123impl<'a> VpunpckhwdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
20124    fn vpunpckhwd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
20125        self.emit(
20126            VPUNPCKHWD128RRR_MASKZ,
20127            op0.as_operand(),
20128            op1.as_operand(),
20129            op2.as_operand(),
20130            &NOREG,
20131        );
20132    }
20133}
20134
20135impl<'a> VpunpckhwdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
20136    fn vpunpckhwd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
20137        self.emit(
20138            VPUNPCKHWD128RRM_MASKZ,
20139            op0.as_operand(),
20140            op1.as_operand(),
20141            op2.as_operand(),
20142            &NOREG,
20143        );
20144    }
20145}
20146
20147impl<'a> VpunpckhwdMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
20148    fn vpunpckhwd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
20149        self.emit(
20150            VPUNPCKHWD256RRR_MASKZ,
20151            op0.as_operand(),
20152            op1.as_operand(),
20153            op2.as_operand(),
20154            &NOREG,
20155        );
20156    }
20157}
20158
20159impl<'a> VpunpckhwdMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
20160    fn vpunpckhwd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
20161        self.emit(
20162            VPUNPCKHWD256RRM_MASKZ,
20163            op0.as_operand(),
20164            op1.as_operand(),
20165            op2.as_operand(),
20166            &NOREG,
20167        );
20168    }
20169}
20170
20171impl<'a> VpunpckhwdMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
20172    fn vpunpckhwd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
20173        self.emit(
20174            VPUNPCKHWD512RRR_MASKZ,
20175            op0.as_operand(),
20176            op1.as_operand(),
20177            op2.as_operand(),
20178            &NOREG,
20179        );
20180    }
20181}
20182
20183impl<'a> VpunpckhwdMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
20184    fn vpunpckhwd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
20185        self.emit(
20186            VPUNPCKHWD512RRM_MASKZ,
20187            op0.as_operand(),
20188            op1.as_operand(),
20189            op2.as_operand(),
20190            &NOREG,
20191        );
20192    }
20193}
20194
20195/// `VPUNPCKLBW`.
20196///
20197/// Supported operand variants:
20198///
20199/// ```text
20200/// +---+---------------+
20201/// | # | Operands      |
20202/// +---+---------------+
20203/// | 1 | Xmm, Xmm, Mem |
20204/// | 2 | Xmm, Xmm, Xmm |
20205/// | 3 | Ymm, Ymm, Mem |
20206/// | 4 | Ymm, Ymm, Ymm |
20207/// | 5 | Zmm, Zmm, Mem |
20208/// | 6 | Zmm, Zmm, Zmm |
20209/// +---+---------------+
20210/// ```
20211pub trait VpunpcklbwEmitter<A, B, C> {
20212    fn vpunpcklbw(&mut self, op0: A, op1: B, op2: C);
20213}
20214
20215impl<'a> VpunpcklbwEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
20216    fn vpunpcklbw(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
20217        self.emit(
20218            VPUNPCKLBW128RRR,
20219            op0.as_operand(),
20220            op1.as_operand(),
20221            op2.as_operand(),
20222            &NOREG,
20223        );
20224    }
20225}
20226
20227impl<'a> VpunpcklbwEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
20228    fn vpunpcklbw(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
20229        self.emit(
20230            VPUNPCKLBW128RRM,
20231            op0.as_operand(),
20232            op1.as_operand(),
20233            op2.as_operand(),
20234            &NOREG,
20235        );
20236    }
20237}
20238
20239impl<'a> VpunpcklbwEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
20240    fn vpunpcklbw(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
20241        self.emit(
20242            VPUNPCKLBW256RRR,
20243            op0.as_operand(),
20244            op1.as_operand(),
20245            op2.as_operand(),
20246            &NOREG,
20247        );
20248    }
20249}
20250
20251impl<'a> VpunpcklbwEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
20252    fn vpunpcklbw(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
20253        self.emit(
20254            VPUNPCKLBW256RRM,
20255            op0.as_operand(),
20256            op1.as_operand(),
20257            op2.as_operand(),
20258            &NOREG,
20259        );
20260    }
20261}
20262
20263impl<'a> VpunpcklbwEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
20264    fn vpunpcklbw(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
20265        self.emit(
20266            VPUNPCKLBW512RRR,
20267            op0.as_operand(),
20268            op1.as_operand(),
20269            op2.as_operand(),
20270            &NOREG,
20271        );
20272    }
20273}
20274
20275impl<'a> VpunpcklbwEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
20276    fn vpunpcklbw(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
20277        self.emit(
20278            VPUNPCKLBW512RRM,
20279            op0.as_operand(),
20280            op1.as_operand(),
20281            op2.as_operand(),
20282            &NOREG,
20283        );
20284    }
20285}
20286
20287/// `VPUNPCKLBW_MASK`.
20288///
20289/// Supported operand variants:
20290///
20291/// ```text
20292/// +---+---------------+
20293/// | # | Operands      |
20294/// +---+---------------+
20295/// | 1 | Xmm, Xmm, Mem |
20296/// | 2 | Xmm, Xmm, Xmm |
20297/// | 3 | Ymm, Ymm, Mem |
20298/// | 4 | Ymm, Ymm, Ymm |
20299/// | 5 | Zmm, Zmm, Mem |
20300/// | 6 | Zmm, Zmm, Zmm |
20301/// +---+---------------+
20302/// ```
20303pub trait VpunpcklbwMaskEmitter<A, B, C> {
20304    fn vpunpcklbw_mask(&mut self, op0: A, op1: B, op2: C);
20305}
20306
20307impl<'a> VpunpcklbwMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
20308    fn vpunpcklbw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
20309        self.emit(
20310            VPUNPCKLBW128RRR_MASK,
20311            op0.as_operand(),
20312            op1.as_operand(),
20313            op2.as_operand(),
20314            &NOREG,
20315        );
20316    }
20317}
20318
20319impl<'a> VpunpcklbwMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
20320    fn vpunpcklbw_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
20321        self.emit(
20322            VPUNPCKLBW128RRM_MASK,
20323            op0.as_operand(),
20324            op1.as_operand(),
20325            op2.as_operand(),
20326            &NOREG,
20327        );
20328    }
20329}
20330
20331impl<'a> VpunpcklbwMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
20332    fn vpunpcklbw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
20333        self.emit(
20334            VPUNPCKLBW256RRR_MASK,
20335            op0.as_operand(),
20336            op1.as_operand(),
20337            op2.as_operand(),
20338            &NOREG,
20339        );
20340    }
20341}
20342
20343impl<'a> VpunpcklbwMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
20344    fn vpunpcklbw_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
20345        self.emit(
20346            VPUNPCKLBW256RRM_MASK,
20347            op0.as_operand(),
20348            op1.as_operand(),
20349            op2.as_operand(),
20350            &NOREG,
20351        );
20352    }
20353}
20354
20355impl<'a> VpunpcklbwMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
20356    fn vpunpcklbw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
20357        self.emit(
20358            VPUNPCKLBW512RRR_MASK,
20359            op0.as_operand(),
20360            op1.as_operand(),
20361            op2.as_operand(),
20362            &NOREG,
20363        );
20364    }
20365}
20366
20367impl<'a> VpunpcklbwMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
20368    fn vpunpcklbw_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
20369        self.emit(
20370            VPUNPCKLBW512RRM_MASK,
20371            op0.as_operand(),
20372            op1.as_operand(),
20373            op2.as_operand(),
20374            &NOREG,
20375        );
20376    }
20377}
20378
20379/// `VPUNPCKLBW_MASKZ`.
20380///
20381/// Supported operand variants:
20382///
20383/// ```text
20384/// +---+---------------+
20385/// | # | Operands      |
20386/// +---+---------------+
20387/// | 1 | Xmm, Xmm, Mem |
20388/// | 2 | Xmm, Xmm, Xmm |
20389/// | 3 | Ymm, Ymm, Mem |
20390/// | 4 | Ymm, Ymm, Ymm |
20391/// | 5 | Zmm, Zmm, Mem |
20392/// | 6 | Zmm, Zmm, Zmm |
20393/// +---+---------------+
20394/// ```
20395pub trait VpunpcklbwMaskzEmitter<A, B, C> {
20396    fn vpunpcklbw_maskz(&mut self, op0: A, op1: B, op2: C);
20397}
20398
20399impl<'a> VpunpcklbwMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
20400    fn vpunpcklbw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
20401        self.emit(
20402            VPUNPCKLBW128RRR_MASKZ,
20403            op0.as_operand(),
20404            op1.as_operand(),
20405            op2.as_operand(),
20406            &NOREG,
20407        );
20408    }
20409}
20410
20411impl<'a> VpunpcklbwMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
20412    fn vpunpcklbw_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
20413        self.emit(
20414            VPUNPCKLBW128RRM_MASKZ,
20415            op0.as_operand(),
20416            op1.as_operand(),
20417            op2.as_operand(),
20418            &NOREG,
20419        );
20420    }
20421}
20422
20423impl<'a> VpunpcklbwMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
20424    fn vpunpcklbw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
20425        self.emit(
20426            VPUNPCKLBW256RRR_MASKZ,
20427            op0.as_operand(),
20428            op1.as_operand(),
20429            op2.as_operand(),
20430            &NOREG,
20431        );
20432    }
20433}
20434
20435impl<'a> VpunpcklbwMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
20436    fn vpunpcklbw_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
20437        self.emit(
20438            VPUNPCKLBW256RRM_MASKZ,
20439            op0.as_operand(),
20440            op1.as_operand(),
20441            op2.as_operand(),
20442            &NOREG,
20443        );
20444    }
20445}
20446
20447impl<'a> VpunpcklbwMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
20448    fn vpunpcklbw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
20449        self.emit(
20450            VPUNPCKLBW512RRR_MASKZ,
20451            op0.as_operand(),
20452            op1.as_operand(),
20453            op2.as_operand(),
20454            &NOREG,
20455        );
20456    }
20457}
20458
20459impl<'a> VpunpcklbwMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
20460    fn vpunpcklbw_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
20461        self.emit(
20462            VPUNPCKLBW512RRM_MASKZ,
20463            op0.as_operand(),
20464            op1.as_operand(),
20465            op2.as_operand(),
20466            &NOREG,
20467        );
20468    }
20469}
20470
20471/// `VPUNPCKLWD`.
20472///
20473/// Supported operand variants:
20474///
20475/// ```text
20476/// +---+---------------+
20477/// | # | Operands      |
20478/// +---+---------------+
20479/// | 1 | Xmm, Xmm, Mem |
20480/// | 2 | Xmm, Xmm, Xmm |
20481/// | 3 | Ymm, Ymm, Mem |
20482/// | 4 | Ymm, Ymm, Ymm |
20483/// | 5 | Zmm, Zmm, Mem |
20484/// | 6 | Zmm, Zmm, Zmm |
20485/// +---+---------------+
20486/// ```
20487pub trait VpunpcklwdEmitter<A, B, C> {
20488    fn vpunpcklwd(&mut self, op0: A, op1: B, op2: C);
20489}
20490
20491impl<'a> VpunpcklwdEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
20492    fn vpunpcklwd(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
20493        self.emit(
20494            VPUNPCKLWD128RRR,
20495            op0.as_operand(),
20496            op1.as_operand(),
20497            op2.as_operand(),
20498            &NOREG,
20499        );
20500    }
20501}
20502
20503impl<'a> VpunpcklwdEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
20504    fn vpunpcklwd(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
20505        self.emit(
20506            VPUNPCKLWD128RRM,
20507            op0.as_operand(),
20508            op1.as_operand(),
20509            op2.as_operand(),
20510            &NOREG,
20511        );
20512    }
20513}
20514
20515impl<'a> VpunpcklwdEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
20516    fn vpunpcklwd(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
20517        self.emit(
20518            VPUNPCKLWD256RRR,
20519            op0.as_operand(),
20520            op1.as_operand(),
20521            op2.as_operand(),
20522            &NOREG,
20523        );
20524    }
20525}
20526
20527impl<'a> VpunpcklwdEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
20528    fn vpunpcklwd(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
20529        self.emit(
20530            VPUNPCKLWD256RRM,
20531            op0.as_operand(),
20532            op1.as_operand(),
20533            op2.as_operand(),
20534            &NOREG,
20535        );
20536    }
20537}
20538
20539impl<'a> VpunpcklwdEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
20540    fn vpunpcklwd(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
20541        self.emit(
20542            VPUNPCKLWD512RRR,
20543            op0.as_operand(),
20544            op1.as_operand(),
20545            op2.as_operand(),
20546            &NOREG,
20547        );
20548    }
20549}
20550
20551impl<'a> VpunpcklwdEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
20552    fn vpunpcklwd(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
20553        self.emit(
20554            VPUNPCKLWD512RRM,
20555            op0.as_operand(),
20556            op1.as_operand(),
20557            op2.as_operand(),
20558            &NOREG,
20559        );
20560    }
20561}
20562
20563/// `VPUNPCKLWD_MASK`.
20564///
20565/// Supported operand variants:
20566///
20567/// ```text
20568/// +---+---------------+
20569/// | # | Operands      |
20570/// +---+---------------+
20571/// | 1 | Xmm, Xmm, Mem |
20572/// | 2 | Xmm, Xmm, Xmm |
20573/// | 3 | Ymm, Ymm, Mem |
20574/// | 4 | Ymm, Ymm, Ymm |
20575/// | 5 | Zmm, Zmm, Mem |
20576/// | 6 | Zmm, Zmm, Zmm |
20577/// +---+---------------+
20578/// ```
20579pub trait VpunpcklwdMaskEmitter<A, B, C> {
20580    fn vpunpcklwd_mask(&mut self, op0: A, op1: B, op2: C);
20581}
20582
20583impl<'a> VpunpcklwdMaskEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
20584    fn vpunpcklwd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
20585        self.emit(
20586            VPUNPCKLWD128RRR_MASK,
20587            op0.as_operand(),
20588            op1.as_operand(),
20589            op2.as_operand(),
20590            &NOREG,
20591        );
20592    }
20593}
20594
20595impl<'a> VpunpcklwdMaskEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
20596    fn vpunpcklwd_mask(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
20597        self.emit(
20598            VPUNPCKLWD128RRM_MASK,
20599            op0.as_operand(),
20600            op1.as_operand(),
20601            op2.as_operand(),
20602            &NOREG,
20603        );
20604    }
20605}
20606
20607impl<'a> VpunpcklwdMaskEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
20608    fn vpunpcklwd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
20609        self.emit(
20610            VPUNPCKLWD256RRR_MASK,
20611            op0.as_operand(),
20612            op1.as_operand(),
20613            op2.as_operand(),
20614            &NOREG,
20615        );
20616    }
20617}
20618
20619impl<'a> VpunpcklwdMaskEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
20620    fn vpunpcklwd_mask(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
20621        self.emit(
20622            VPUNPCKLWD256RRM_MASK,
20623            op0.as_operand(),
20624            op1.as_operand(),
20625            op2.as_operand(),
20626            &NOREG,
20627        );
20628    }
20629}
20630
20631impl<'a> VpunpcklwdMaskEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
20632    fn vpunpcklwd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
20633        self.emit(
20634            VPUNPCKLWD512RRR_MASK,
20635            op0.as_operand(),
20636            op1.as_operand(),
20637            op2.as_operand(),
20638            &NOREG,
20639        );
20640    }
20641}
20642
20643impl<'a> VpunpcklwdMaskEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
20644    fn vpunpcklwd_mask(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
20645        self.emit(
20646            VPUNPCKLWD512RRM_MASK,
20647            op0.as_operand(),
20648            op1.as_operand(),
20649            op2.as_operand(),
20650            &NOREG,
20651        );
20652    }
20653}
20654
20655/// `VPUNPCKLWD_MASKZ`.
20656///
20657/// Supported operand variants:
20658///
20659/// ```text
20660/// +---+---------------+
20661/// | # | Operands      |
20662/// +---+---------------+
20663/// | 1 | Xmm, Xmm, Mem |
20664/// | 2 | Xmm, Xmm, Xmm |
20665/// | 3 | Ymm, Ymm, Mem |
20666/// | 4 | Ymm, Ymm, Ymm |
20667/// | 5 | Zmm, Zmm, Mem |
20668/// | 6 | Zmm, Zmm, Zmm |
20669/// +---+---------------+
20670/// ```
20671pub trait VpunpcklwdMaskzEmitter<A, B, C> {
20672    fn vpunpcklwd_maskz(&mut self, op0: A, op1: B, op2: C);
20673}
20674
20675impl<'a> VpunpcklwdMaskzEmitter<Xmm, Xmm, Xmm> for Assembler<'a> {
20676    fn vpunpcklwd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Xmm) {
20677        self.emit(
20678            VPUNPCKLWD128RRR_MASKZ,
20679            op0.as_operand(),
20680            op1.as_operand(),
20681            op2.as_operand(),
20682            &NOREG,
20683        );
20684    }
20685}
20686
20687impl<'a> VpunpcklwdMaskzEmitter<Xmm, Xmm, Mem> for Assembler<'a> {
20688    fn vpunpcklwd_maskz(&mut self, op0: Xmm, op1: Xmm, op2: Mem) {
20689        self.emit(
20690            VPUNPCKLWD128RRM_MASKZ,
20691            op0.as_operand(),
20692            op1.as_operand(),
20693            op2.as_operand(),
20694            &NOREG,
20695        );
20696    }
20697}
20698
20699impl<'a> VpunpcklwdMaskzEmitter<Ymm, Ymm, Ymm> for Assembler<'a> {
20700    fn vpunpcklwd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Ymm) {
20701        self.emit(
20702            VPUNPCKLWD256RRR_MASKZ,
20703            op0.as_operand(),
20704            op1.as_operand(),
20705            op2.as_operand(),
20706            &NOREG,
20707        );
20708    }
20709}
20710
20711impl<'a> VpunpcklwdMaskzEmitter<Ymm, Ymm, Mem> for Assembler<'a> {
20712    fn vpunpcklwd_maskz(&mut self, op0: Ymm, op1: Ymm, op2: Mem) {
20713        self.emit(
20714            VPUNPCKLWD256RRM_MASKZ,
20715            op0.as_operand(),
20716            op1.as_operand(),
20717            op2.as_operand(),
20718            &NOREG,
20719        );
20720    }
20721}
20722
20723impl<'a> VpunpcklwdMaskzEmitter<Zmm, Zmm, Zmm> for Assembler<'a> {
20724    fn vpunpcklwd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Zmm) {
20725        self.emit(
20726            VPUNPCKLWD512RRR_MASKZ,
20727            op0.as_operand(),
20728            op1.as_operand(),
20729            op2.as_operand(),
20730            &NOREG,
20731        );
20732    }
20733}
20734
20735impl<'a> VpunpcklwdMaskzEmitter<Zmm, Zmm, Mem> for Assembler<'a> {
20736    fn vpunpcklwd_maskz(&mut self, op0: Zmm, op1: Zmm, op2: Mem) {
20737        self.emit(
20738            VPUNPCKLWD512RRM_MASKZ,
20739            op0.as_operand(),
20740            op1.as_operand(),
20741            op2.as_operand(),
20742            &NOREG,
20743        );
20744    }
20745}
20746
20747impl<'a> Assembler<'a> {
20748    /// `KADDD`.
20749    ///
20750    /// Supported operand variants:
20751    ///
20752    /// ```text
20753    /// +---+------------------+
20754    /// | # | Operands         |
20755    /// +---+------------------+
20756    /// | 1 | KReg, KReg, KReg |
20757    /// +---+------------------+
20758    /// ```
20759    #[inline]
20760    pub fn kaddd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
20761    where
20762        Assembler<'a>: KadddEmitter<A, B, C>,
20763    {
20764        <Self as KadddEmitter<A, B, C>>::kaddd(self, op0, op1, op2);
20765    }
20766    /// `KADDQ`.
20767    ///
20768    /// Supported operand variants:
20769    ///
20770    /// ```text
20771    /// +---+------------------+
20772    /// | # | Operands         |
20773    /// +---+------------------+
20774    /// | 1 | KReg, KReg, KReg |
20775    /// +---+------------------+
20776    /// ```
20777    #[inline]
20778    pub fn kaddq<A, B, C>(&mut self, op0: A, op1: B, op2: C)
20779    where
20780        Assembler<'a>: KaddqEmitter<A, B, C>,
20781    {
20782        <Self as KaddqEmitter<A, B, C>>::kaddq(self, op0, op1, op2);
20783    }
20784    /// `KANDD`.
20785    ///
20786    /// Supported operand variants:
20787    ///
20788    /// ```text
20789    /// +---+------------------+
20790    /// | # | Operands         |
20791    /// +---+------------------+
20792    /// | 1 | KReg, KReg, KReg |
20793    /// +---+------------------+
20794    /// ```
20795    #[inline]
20796    pub fn kandd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
20797    where
20798        Assembler<'a>: KanddEmitter<A, B, C>,
20799    {
20800        <Self as KanddEmitter<A, B, C>>::kandd(self, op0, op1, op2);
20801    }
20802    /// `KANDND`.
20803    ///
20804    /// Supported operand variants:
20805    ///
20806    /// ```text
20807    /// +---+------------------+
20808    /// | # | Operands         |
20809    /// +---+------------------+
20810    /// | 1 | KReg, KReg, KReg |
20811    /// +---+------------------+
20812    /// ```
20813    #[inline]
20814    pub fn kandnd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
20815    where
20816        Assembler<'a>: KandndEmitter<A, B, C>,
20817    {
20818        <Self as KandndEmitter<A, B, C>>::kandnd(self, op0, op1, op2);
20819    }
20820    /// `KANDNQ`.
20821    ///
20822    /// Supported operand variants:
20823    ///
20824    /// ```text
20825    /// +---+------------------+
20826    /// | # | Operands         |
20827    /// +---+------------------+
20828    /// | 1 | KReg, KReg, KReg |
20829    /// +---+------------------+
20830    /// ```
20831    #[inline]
20832    pub fn kandnq<A, B, C>(&mut self, op0: A, op1: B, op2: C)
20833    where
20834        Assembler<'a>: KandnqEmitter<A, B, C>,
20835    {
20836        <Self as KandnqEmitter<A, B, C>>::kandnq(self, op0, op1, op2);
20837    }
20838    /// `KANDQ`.
20839    ///
20840    /// Supported operand variants:
20841    ///
20842    /// ```text
20843    /// +---+------------------+
20844    /// | # | Operands         |
20845    /// +---+------------------+
20846    /// | 1 | KReg, KReg, KReg |
20847    /// +---+------------------+
20848    /// ```
20849    #[inline]
20850    pub fn kandq<A, B, C>(&mut self, op0: A, op1: B, op2: C)
20851    where
20852        Assembler<'a>: KandqEmitter<A, B, C>,
20853    {
20854        <Self as KandqEmitter<A, B, C>>::kandq(self, op0, op1, op2);
20855    }
20856    /// `KMOVD`.
20857    ///
20858    /// Supported operand variants:
20859    ///
20860    /// ```text
20861    /// +---+------------+
20862    /// | # | Operands   |
20863    /// +---+------------+
20864    /// | 1 | Gpd, KReg  |
20865    /// | 2 | KReg, Gpd  |
20866    /// | 3 | KReg, KReg |
20867    /// | 4 | KReg, Mem  |
20868    /// | 5 | Mem, KReg  |
20869    /// +---+------------+
20870    /// ```
20871    #[inline]
20872    pub fn kmovd<A, B>(&mut self, op0: A, op1: B)
20873    where
20874        Assembler<'a>: KmovdEmitter<A, B>,
20875    {
20876        <Self as KmovdEmitter<A, B>>::kmovd(self, op0, op1);
20877    }
20878    /// `KMOVQ`.
20879    ///
20880    /// Supported operand variants:
20881    ///
20882    /// ```text
20883    /// +---+------------+
20884    /// | # | Operands   |
20885    /// +---+------------+
20886    /// | 1 | Gpd, KReg  |
20887    /// | 2 | KReg, Gpd  |
20888    /// | 3 | KReg, KReg |
20889    /// | 4 | KReg, Mem  |
20890    /// | 5 | Mem, KReg  |
20891    /// +---+------------+
20892    /// ```
20893    #[inline]
20894    pub fn kmovq<A, B>(&mut self, op0: A, op1: B)
20895    where
20896        Assembler<'a>: KmovqEmitter<A, B>,
20897    {
20898        <Self as KmovqEmitter<A, B>>::kmovq(self, op0, op1);
20899    }
20900    /// `KNOTD`.
20901    ///
20902    /// Supported operand variants:
20903    ///
20904    /// ```text
20905    /// +---+------------+
20906    /// | # | Operands   |
20907    /// +---+------------+
20908    /// | 1 | KReg, KReg |
20909    /// +---+------------+
20910    /// ```
20911    #[inline]
20912    pub fn knotd<A, B>(&mut self, op0: A, op1: B)
20913    where
20914        Assembler<'a>: KnotdEmitter<A, B>,
20915    {
20916        <Self as KnotdEmitter<A, B>>::knotd(self, op0, op1);
20917    }
20918    /// `KNOTQ`.
20919    ///
20920    /// Supported operand variants:
20921    ///
20922    /// ```text
20923    /// +---+------------+
20924    /// | # | Operands   |
20925    /// +---+------------+
20926    /// | 1 | KReg, KReg |
20927    /// +---+------------+
20928    /// ```
20929    #[inline]
20930    pub fn knotq<A, B>(&mut self, op0: A, op1: B)
20931    where
20932        Assembler<'a>: KnotqEmitter<A, B>,
20933    {
20934        <Self as KnotqEmitter<A, B>>::knotq(self, op0, op1);
20935    }
20936    /// `KORD`.
20937    ///
20938    /// Supported operand variants:
20939    ///
20940    /// ```text
20941    /// +---+------------------+
20942    /// | # | Operands         |
20943    /// +---+------------------+
20944    /// | 1 | KReg, KReg, KReg |
20945    /// +---+------------------+
20946    /// ```
20947    #[inline]
20948    pub fn kord<A, B, C>(&mut self, op0: A, op1: B, op2: C)
20949    where
20950        Assembler<'a>: KordEmitter<A, B, C>,
20951    {
20952        <Self as KordEmitter<A, B, C>>::kord(self, op0, op1, op2);
20953    }
20954    /// `KORQ`.
20955    ///
20956    /// Supported operand variants:
20957    ///
20958    /// ```text
20959    /// +---+------------------+
20960    /// | # | Operands         |
20961    /// +---+------------------+
20962    /// | 1 | KReg, KReg, KReg |
20963    /// +---+------------------+
20964    /// ```
20965    #[inline]
20966    pub fn korq<A, B, C>(&mut self, op0: A, op1: B, op2: C)
20967    where
20968        Assembler<'a>: KorqEmitter<A, B, C>,
20969    {
20970        <Self as KorqEmitter<A, B, C>>::korq(self, op0, op1, op2);
20971    }
20972    /// `KORTESTD`.
20973    ///
20974    /// Supported operand variants:
20975    ///
20976    /// ```text
20977    /// +---+------------+
20978    /// | # | Operands   |
20979    /// +---+------------+
20980    /// | 1 | KReg, KReg |
20981    /// +---+------------+
20982    /// ```
20983    #[inline]
20984    pub fn kortestd<A, B>(&mut self, op0: A, op1: B)
20985    where
20986        Assembler<'a>: KortestdEmitter<A, B>,
20987    {
20988        <Self as KortestdEmitter<A, B>>::kortestd(self, op0, op1);
20989    }
20990    /// `KORTESTQ`.
20991    ///
20992    /// Supported operand variants:
20993    ///
20994    /// ```text
20995    /// +---+------------+
20996    /// | # | Operands   |
20997    /// +---+------------+
20998    /// | 1 | KReg, KReg |
20999    /// +---+------------+
21000    /// ```
21001    #[inline]
21002    pub fn kortestq<A, B>(&mut self, op0: A, op1: B)
21003    where
21004        Assembler<'a>: KortestqEmitter<A, B>,
21005    {
21006        <Self as KortestqEmitter<A, B>>::kortestq(self, op0, op1);
21007    }
21008    /// `KSHIFTLD`.
21009    ///
21010    /// Supported operand variants:
21011    ///
21012    /// ```text
21013    /// +---+-----------------+
21014    /// | # | Operands        |
21015    /// +---+-----------------+
21016    /// | 1 | KReg, KReg, Imm |
21017    /// +---+-----------------+
21018    /// ```
21019    #[inline]
21020    pub fn kshiftld<A, B, C>(&mut self, op0: A, op1: B, op2: C)
21021    where
21022        Assembler<'a>: KshiftldEmitter<A, B, C>,
21023    {
21024        <Self as KshiftldEmitter<A, B, C>>::kshiftld(self, op0, op1, op2);
21025    }
21026    /// `KSHIFTLQ`.
21027    ///
21028    /// Supported operand variants:
21029    ///
21030    /// ```text
21031    /// +---+-----------------+
21032    /// | # | Operands        |
21033    /// +---+-----------------+
21034    /// | 1 | KReg, KReg, Imm |
21035    /// +---+-----------------+
21036    /// ```
21037    #[inline]
21038    pub fn kshiftlq<A, B, C>(&mut self, op0: A, op1: B, op2: C)
21039    where
21040        Assembler<'a>: KshiftlqEmitter<A, B, C>,
21041    {
21042        <Self as KshiftlqEmitter<A, B, C>>::kshiftlq(self, op0, op1, op2);
21043    }
21044    /// `KSHIFTRD`.
21045    ///
21046    /// Supported operand variants:
21047    ///
21048    /// ```text
21049    /// +---+-----------------+
21050    /// | # | Operands        |
21051    /// +---+-----------------+
21052    /// | 1 | KReg, KReg, Imm |
21053    /// +---+-----------------+
21054    /// ```
21055    #[inline]
21056    pub fn kshiftrd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
21057    where
21058        Assembler<'a>: KshiftrdEmitter<A, B, C>,
21059    {
21060        <Self as KshiftrdEmitter<A, B, C>>::kshiftrd(self, op0, op1, op2);
21061    }
21062    /// `KSHIFTRQ`.
21063    ///
21064    /// Supported operand variants:
21065    ///
21066    /// ```text
21067    /// +---+-----------------+
21068    /// | # | Operands        |
21069    /// +---+-----------------+
21070    /// | 1 | KReg, KReg, Imm |
21071    /// +---+-----------------+
21072    /// ```
21073    #[inline]
21074    pub fn kshiftrq<A, B, C>(&mut self, op0: A, op1: B, op2: C)
21075    where
21076        Assembler<'a>: KshiftrqEmitter<A, B, C>,
21077    {
21078        <Self as KshiftrqEmitter<A, B, C>>::kshiftrq(self, op0, op1, op2);
21079    }
21080    /// `KTESTD`.
21081    ///
21082    /// Supported operand variants:
21083    ///
21084    /// ```text
21085    /// +---+------------+
21086    /// | # | Operands   |
21087    /// +---+------------+
21088    /// | 1 | KReg, KReg |
21089    /// +---+------------+
21090    /// ```
21091    #[inline]
21092    pub fn ktestd<A, B>(&mut self, op0: A, op1: B)
21093    where
21094        Assembler<'a>: KtestdEmitter<A, B>,
21095    {
21096        <Self as KtestdEmitter<A, B>>::ktestd(self, op0, op1);
21097    }
21098    /// `KTESTQ`.
21099    ///
21100    /// Supported operand variants:
21101    ///
21102    /// ```text
21103    /// +---+------------+
21104    /// | # | Operands   |
21105    /// +---+------------+
21106    /// | 1 | KReg, KReg |
21107    /// +---+------------+
21108    /// ```
21109    #[inline]
21110    pub fn ktestq<A, B>(&mut self, op0: A, op1: B)
21111    where
21112        Assembler<'a>: KtestqEmitter<A, B>,
21113    {
21114        <Self as KtestqEmitter<A, B>>::ktestq(self, op0, op1);
21115    }
21116    /// `KUNPCKDQ`.
21117    ///
21118    /// Supported operand variants:
21119    ///
21120    /// ```text
21121    /// +---+------------------+
21122    /// | # | Operands         |
21123    /// +---+------------------+
21124    /// | 1 | KReg, KReg, KReg |
21125    /// +---+------------------+
21126    /// ```
21127    #[inline]
21128    pub fn kunpckdq<A, B, C>(&mut self, op0: A, op1: B, op2: C)
21129    where
21130        Assembler<'a>: KunpckdqEmitter<A, B, C>,
21131    {
21132        <Self as KunpckdqEmitter<A, B, C>>::kunpckdq(self, op0, op1, op2);
21133    }
21134    /// `KUNPCKWD`.
21135    ///
21136    /// Supported operand variants:
21137    ///
21138    /// ```text
21139    /// +---+------------------+
21140    /// | # | Operands         |
21141    /// +---+------------------+
21142    /// | 1 | KReg, KReg, KReg |
21143    /// +---+------------------+
21144    /// ```
21145    #[inline]
21146    pub fn kunpckwd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
21147    where
21148        Assembler<'a>: KunpckwdEmitter<A, B, C>,
21149    {
21150        <Self as KunpckwdEmitter<A, B, C>>::kunpckwd(self, op0, op1, op2);
21151    }
21152    /// `KXNORD`.
21153    ///
21154    /// Supported operand variants:
21155    ///
21156    /// ```text
21157    /// +---+------------------+
21158    /// | # | Operands         |
21159    /// +---+------------------+
21160    /// | 1 | KReg, KReg, KReg |
21161    /// +---+------------------+
21162    /// ```
21163    #[inline]
21164    pub fn kxnord<A, B, C>(&mut self, op0: A, op1: B, op2: C)
21165    where
21166        Assembler<'a>: KxnordEmitter<A, B, C>,
21167    {
21168        <Self as KxnordEmitter<A, B, C>>::kxnord(self, op0, op1, op2);
21169    }
21170    /// `KXNORQ`.
21171    ///
21172    /// Supported operand variants:
21173    ///
21174    /// ```text
21175    /// +---+------------------+
21176    /// | # | Operands         |
21177    /// +---+------------------+
21178    /// | 1 | KReg, KReg, KReg |
21179    /// +---+------------------+
21180    /// ```
21181    #[inline]
21182    pub fn kxnorq<A, B, C>(&mut self, op0: A, op1: B, op2: C)
21183    where
21184        Assembler<'a>: KxnorqEmitter<A, B, C>,
21185    {
21186        <Self as KxnorqEmitter<A, B, C>>::kxnorq(self, op0, op1, op2);
21187    }
21188    /// `KXORD`.
21189    ///
21190    /// Supported operand variants:
21191    ///
21192    /// ```text
21193    /// +---+------------------+
21194    /// | # | Operands         |
21195    /// +---+------------------+
21196    /// | 1 | KReg, KReg, KReg |
21197    /// +---+------------------+
21198    /// ```
21199    #[inline]
21200    pub fn kxord<A, B, C>(&mut self, op0: A, op1: B, op2: C)
21201    where
21202        Assembler<'a>: KxordEmitter<A, B, C>,
21203    {
21204        <Self as KxordEmitter<A, B, C>>::kxord(self, op0, op1, op2);
21205    }
21206    /// `KXORQ`.
21207    ///
21208    /// Supported operand variants:
21209    ///
21210    /// ```text
21211    /// +---+------------------+
21212    /// | # | Operands         |
21213    /// +---+------------------+
21214    /// | 1 | KReg, KReg, KReg |
21215    /// +---+------------------+
21216    /// ```
21217    #[inline]
21218    pub fn kxorq<A, B, C>(&mut self, op0: A, op1: B, op2: C)
21219    where
21220        Assembler<'a>: KxorqEmitter<A, B, C>,
21221    {
21222        <Self as KxorqEmitter<A, B, C>>::kxorq(self, op0, op1, op2);
21223    }
21224    /// `VDBPSADBW`.
21225    ///
21226    /// Supported operand variants:
21227    ///
21228    /// ```text
21229    /// +---+--------------------+
21230    /// | # | Operands           |
21231    /// +---+--------------------+
21232    /// | 1 | Xmm, Xmm, Mem, Imm |
21233    /// | 2 | Xmm, Xmm, Xmm, Imm |
21234    /// | 3 | Ymm, Ymm, Mem, Imm |
21235    /// | 4 | Ymm, Ymm, Ymm, Imm |
21236    /// | 5 | Zmm, Zmm, Mem, Imm |
21237    /// | 6 | Zmm, Zmm, Zmm, Imm |
21238    /// +---+--------------------+
21239    /// ```
21240    #[inline]
21241    pub fn vdbpsadbw<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
21242    where
21243        Assembler<'a>: VdbpsadbwEmitter<A, B, C, D>,
21244    {
21245        <Self as VdbpsadbwEmitter<A, B, C, D>>::vdbpsadbw(self, op0, op1, op2, op3);
21246    }
21247    /// `VDBPSADBW_MASK`.
21248    ///
21249    /// Supported operand variants:
21250    ///
21251    /// ```text
21252    /// +---+--------------------+
21253    /// | # | Operands           |
21254    /// +---+--------------------+
21255    /// | 1 | Xmm, Xmm, Mem, Imm |
21256    /// | 2 | Xmm, Xmm, Xmm, Imm |
21257    /// | 3 | Ymm, Ymm, Mem, Imm |
21258    /// | 4 | Ymm, Ymm, Ymm, Imm |
21259    /// | 5 | Zmm, Zmm, Mem, Imm |
21260    /// | 6 | Zmm, Zmm, Zmm, Imm |
21261    /// +---+--------------------+
21262    /// ```
21263    #[inline]
21264    pub fn vdbpsadbw_mask<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
21265    where
21266        Assembler<'a>: VdbpsadbwMaskEmitter<A, B, C, D>,
21267    {
21268        <Self as VdbpsadbwMaskEmitter<A, B, C, D>>::vdbpsadbw_mask(self, op0, op1, op2, op3);
21269    }
21270    /// `VDBPSADBW_MASKZ`.
21271    ///
21272    /// Supported operand variants:
21273    ///
21274    /// ```text
21275    /// +---+--------------------+
21276    /// | # | Operands           |
21277    /// +---+--------------------+
21278    /// | 1 | Xmm, Xmm, Mem, Imm |
21279    /// | 2 | Xmm, Xmm, Xmm, Imm |
21280    /// | 3 | Ymm, Ymm, Mem, Imm |
21281    /// | 4 | Ymm, Ymm, Ymm, Imm |
21282    /// | 5 | Zmm, Zmm, Mem, Imm |
21283    /// | 6 | Zmm, Zmm, Zmm, Imm |
21284    /// +---+--------------------+
21285    /// ```
21286    #[inline]
21287    pub fn vdbpsadbw_maskz<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
21288    where
21289        Assembler<'a>: VdbpsadbwMaskzEmitter<A, B, C, D>,
21290    {
21291        <Self as VdbpsadbwMaskzEmitter<A, B, C, D>>::vdbpsadbw_maskz(self, op0, op1, op2, op3);
21292    }
21293    /// `VMOVDQU16`.
21294    ///
21295    /// Supported operand variants:
21296    ///
21297    /// ```text
21298    /// +---+----------+
21299    /// | # | Operands |
21300    /// +---+----------+
21301    /// | 1 | Mem, Xmm |
21302    /// | 2 | Mem, Ymm |
21303    /// | 3 | Mem, Zmm |
21304    /// | 4 | Xmm, Mem |
21305    /// | 5 | Xmm, Xmm |
21306    /// | 6 | Ymm, Mem |
21307    /// | 7 | Ymm, Ymm |
21308    /// | 8 | Zmm, Mem |
21309    /// | 9 | Zmm, Zmm |
21310    /// +---+----------+
21311    /// ```
21312    #[inline]
21313    pub fn vmovdqu16<A, B>(&mut self, op0: A, op1: B)
21314    where
21315        Assembler<'a>: Vmovdqu16Emitter<A, B>,
21316    {
21317        <Self as Vmovdqu16Emitter<A, B>>::vmovdqu16(self, op0, op1);
21318    }
21319    /// `VMOVDQU16_MASK`.
21320    ///
21321    /// Supported operand variants:
21322    ///
21323    /// ```text
21324    /// +---+----------+
21325    /// | # | Operands |
21326    /// +---+----------+
21327    /// | 1 | Mem, Xmm |
21328    /// | 2 | Mem, Ymm |
21329    /// | 3 | Mem, Zmm |
21330    /// | 4 | Xmm, Mem |
21331    /// | 5 | Xmm, Xmm |
21332    /// | 6 | Ymm, Mem |
21333    /// | 7 | Ymm, Ymm |
21334    /// | 8 | Zmm, Mem |
21335    /// | 9 | Zmm, Zmm |
21336    /// +---+----------+
21337    /// ```
21338    #[inline]
21339    pub fn vmovdqu16_mask<A, B>(&mut self, op0: A, op1: B)
21340    where
21341        Assembler<'a>: Vmovdqu16MaskEmitter<A, B>,
21342    {
21343        <Self as Vmovdqu16MaskEmitter<A, B>>::vmovdqu16_mask(self, op0, op1);
21344    }
21345    /// `VMOVDQU16_MASKZ`.
21346    ///
21347    /// Supported operand variants:
21348    ///
21349    /// ```text
21350    /// +---+----------+
21351    /// | # | Operands |
21352    /// +---+----------+
21353    /// | 1 | Xmm, Mem |
21354    /// | 2 | Xmm, Xmm |
21355    /// | 3 | Ymm, Mem |
21356    /// | 4 | Ymm, Ymm |
21357    /// | 5 | Zmm, Mem |
21358    /// | 6 | Zmm, Zmm |
21359    /// +---+----------+
21360    /// ```
21361    #[inline]
21362    pub fn vmovdqu16_maskz<A, B>(&mut self, op0: A, op1: B)
21363    where
21364        Assembler<'a>: Vmovdqu16MaskzEmitter<A, B>,
21365    {
21366        <Self as Vmovdqu16MaskzEmitter<A, B>>::vmovdqu16_maskz(self, op0, op1);
21367    }
21368    /// `VMOVDQU8`.
21369    ///
21370    /// Supported operand variants:
21371    ///
21372    /// ```text
21373    /// +---+----------+
21374    /// | # | Operands |
21375    /// +---+----------+
21376    /// | 1 | Mem, Xmm |
21377    /// | 2 | Mem, Ymm |
21378    /// | 3 | Mem, Zmm |
21379    /// | 4 | Xmm, Mem |
21380    /// | 5 | Xmm, Xmm |
21381    /// | 6 | Ymm, Mem |
21382    /// | 7 | Ymm, Ymm |
21383    /// | 8 | Zmm, Mem |
21384    /// | 9 | Zmm, Zmm |
21385    /// +---+----------+
21386    /// ```
21387    #[inline]
21388    pub fn vmovdqu8<A, B>(&mut self, op0: A, op1: B)
21389    where
21390        Assembler<'a>: Vmovdqu8Emitter<A, B>,
21391    {
21392        <Self as Vmovdqu8Emitter<A, B>>::vmovdqu8(self, op0, op1);
21393    }
21394    /// `VMOVDQU8_MASK`.
21395    ///
21396    /// Supported operand variants:
21397    ///
21398    /// ```text
21399    /// +---+----------+
21400    /// | # | Operands |
21401    /// +---+----------+
21402    /// | 1 | Mem, Xmm |
21403    /// | 2 | Mem, Ymm |
21404    /// | 3 | Mem, Zmm |
21405    /// | 4 | Xmm, Mem |
21406    /// | 5 | Xmm, Xmm |
21407    /// | 6 | Ymm, Mem |
21408    /// | 7 | Ymm, Ymm |
21409    /// | 8 | Zmm, Mem |
21410    /// | 9 | Zmm, Zmm |
21411    /// +---+----------+
21412    /// ```
21413    #[inline]
21414    pub fn vmovdqu8_mask<A, B>(&mut self, op0: A, op1: B)
21415    where
21416        Assembler<'a>: Vmovdqu8MaskEmitter<A, B>,
21417    {
21418        <Self as Vmovdqu8MaskEmitter<A, B>>::vmovdqu8_mask(self, op0, op1);
21419    }
21420    /// `VMOVDQU8_MASKZ`.
21421    ///
21422    /// Supported operand variants:
21423    ///
21424    /// ```text
21425    /// +---+----------+
21426    /// | # | Operands |
21427    /// +---+----------+
21428    /// | 1 | Xmm, Mem |
21429    /// | 2 | Xmm, Xmm |
21430    /// | 3 | Ymm, Mem |
21431    /// | 4 | Ymm, Ymm |
21432    /// | 5 | Zmm, Mem |
21433    /// | 6 | Zmm, Zmm |
21434    /// +---+----------+
21435    /// ```
21436    #[inline]
21437    pub fn vmovdqu8_maskz<A, B>(&mut self, op0: A, op1: B)
21438    where
21439        Assembler<'a>: Vmovdqu8MaskzEmitter<A, B>,
21440    {
21441        <Self as Vmovdqu8MaskzEmitter<A, B>>::vmovdqu8_maskz(self, op0, op1);
21442    }
21443    /// `VPABSB`.
21444    ///
21445    /// Supported operand variants:
21446    ///
21447    /// ```text
21448    /// +---+----------+
21449    /// | # | Operands |
21450    /// +---+----------+
21451    /// | 1 | Xmm, Mem |
21452    /// | 2 | Xmm, Xmm |
21453    /// | 3 | Ymm, Mem |
21454    /// | 4 | Ymm, Ymm |
21455    /// | 5 | Zmm, Mem |
21456    /// | 6 | Zmm, Zmm |
21457    /// +---+----------+
21458    /// ```
21459    #[inline]
21460    pub fn vpabsb<A, B>(&mut self, op0: A, op1: B)
21461    where
21462        Assembler<'a>: VpabsbEmitter<A, B>,
21463    {
21464        <Self as VpabsbEmitter<A, B>>::vpabsb(self, op0, op1);
21465    }
21466    /// `VPABSB_MASK`.
21467    ///
21468    /// Supported operand variants:
21469    ///
21470    /// ```text
21471    /// +---+----------+
21472    /// | # | Operands |
21473    /// +---+----------+
21474    /// | 1 | Xmm, Mem |
21475    /// | 2 | Xmm, Xmm |
21476    /// | 3 | Ymm, Mem |
21477    /// | 4 | Ymm, Ymm |
21478    /// | 5 | Zmm, Mem |
21479    /// | 6 | Zmm, Zmm |
21480    /// +---+----------+
21481    /// ```
21482    #[inline]
21483    pub fn vpabsb_mask<A, B>(&mut self, op0: A, op1: B)
21484    where
21485        Assembler<'a>: VpabsbMaskEmitter<A, B>,
21486    {
21487        <Self as VpabsbMaskEmitter<A, B>>::vpabsb_mask(self, op0, op1);
21488    }
21489    /// `VPABSB_MASKZ`.
21490    ///
21491    /// Supported operand variants:
21492    ///
21493    /// ```text
21494    /// +---+----------+
21495    /// | # | Operands |
21496    /// +---+----------+
21497    /// | 1 | Xmm, Mem |
21498    /// | 2 | Xmm, Xmm |
21499    /// | 3 | Ymm, Mem |
21500    /// | 4 | Ymm, Ymm |
21501    /// | 5 | Zmm, Mem |
21502    /// | 6 | Zmm, Zmm |
21503    /// +---+----------+
21504    /// ```
21505    #[inline]
21506    pub fn vpabsb_maskz<A, B>(&mut self, op0: A, op1: B)
21507    where
21508        Assembler<'a>: VpabsbMaskzEmitter<A, B>,
21509    {
21510        <Self as VpabsbMaskzEmitter<A, B>>::vpabsb_maskz(self, op0, op1);
21511    }
21512    /// `VPABSW`.
21513    ///
21514    /// Supported operand variants:
21515    ///
21516    /// ```text
21517    /// +---+----------+
21518    /// | # | Operands |
21519    /// +---+----------+
21520    /// | 1 | Xmm, Mem |
21521    /// | 2 | Xmm, Xmm |
21522    /// | 3 | Ymm, Mem |
21523    /// | 4 | Ymm, Ymm |
21524    /// | 5 | Zmm, Mem |
21525    /// | 6 | Zmm, Zmm |
21526    /// +---+----------+
21527    /// ```
21528    #[inline]
21529    pub fn vpabsw<A, B>(&mut self, op0: A, op1: B)
21530    where
21531        Assembler<'a>: VpabswEmitter<A, B>,
21532    {
21533        <Self as VpabswEmitter<A, B>>::vpabsw(self, op0, op1);
21534    }
21535    /// `VPABSW_MASK`.
21536    ///
21537    /// Supported operand variants:
21538    ///
21539    /// ```text
21540    /// +---+----------+
21541    /// | # | Operands |
21542    /// +---+----------+
21543    /// | 1 | Xmm, Mem |
21544    /// | 2 | Xmm, Xmm |
21545    /// | 3 | Ymm, Mem |
21546    /// | 4 | Ymm, Ymm |
21547    /// | 5 | Zmm, Mem |
21548    /// | 6 | Zmm, Zmm |
21549    /// +---+----------+
21550    /// ```
21551    #[inline]
21552    pub fn vpabsw_mask<A, B>(&mut self, op0: A, op1: B)
21553    where
21554        Assembler<'a>: VpabswMaskEmitter<A, B>,
21555    {
21556        <Self as VpabswMaskEmitter<A, B>>::vpabsw_mask(self, op0, op1);
21557    }
21558    /// `VPABSW_MASKZ`.
21559    ///
21560    /// Supported operand variants:
21561    ///
21562    /// ```text
21563    /// +---+----------+
21564    /// | # | Operands |
21565    /// +---+----------+
21566    /// | 1 | Xmm, Mem |
21567    /// | 2 | Xmm, Xmm |
21568    /// | 3 | Ymm, Mem |
21569    /// | 4 | Ymm, Ymm |
21570    /// | 5 | Zmm, Mem |
21571    /// | 6 | Zmm, Zmm |
21572    /// +---+----------+
21573    /// ```
21574    #[inline]
21575    pub fn vpabsw_maskz<A, B>(&mut self, op0: A, op1: B)
21576    where
21577        Assembler<'a>: VpabswMaskzEmitter<A, B>,
21578    {
21579        <Self as VpabswMaskzEmitter<A, B>>::vpabsw_maskz(self, op0, op1);
21580    }
21581    /// `VPACKSSDW`.
21582    ///
21583    /// Supported operand variants:
21584    ///
21585    /// ```text
21586    /// +---+---------------+
21587    /// | # | Operands      |
21588    /// +---+---------------+
21589    /// | 1 | Xmm, Xmm, Mem |
21590    /// | 2 | Xmm, Xmm, Xmm |
21591    /// | 3 | Ymm, Ymm, Mem |
21592    /// | 4 | Ymm, Ymm, Ymm |
21593    /// | 5 | Zmm, Zmm, Mem |
21594    /// | 6 | Zmm, Zmm, Zmm |
21595    /// +---+---------------+
21596    /// ```
21597    #[inline]
21598    pub fn vpackssdw<A, B, C>(&mut self, op0: A, op1: B, op2: C)
21599    where
21600        Assembler<'a>: VpackssdwEmitter<A, B, C>,
21601    {
21602        <Self as VpackssdwEmitter<A, B, C>>::vpackssdw(self, op0, op1, op2);
21603    }
21604    /// `VPACKSSDW_MASK`.
21605    ///
21606    /// Supported operand variants:
21607    ///
21608    /// ```text
21609    /// +---+---------------+
21610    /// | # | Operands      |
21611    /// +---+---------------+
21612    /// | 1 | Xmm, Xmm, Mem |
21613    /// | 2 | Xmm, Xmm, Xmm |
21614    /// | 3 | Ymm, Ymm, Mem |
21615    /// | 4 | Ymm, Ymm, Ymm |
21616    /// | 5 | Zmm, Zmm, Mem |
21617    /// | 6 | Zmm, Zmm, Zmm |
21618    /// +---+---------------+
21619    /// ```
21620    #[inline]
21621    pub fn vpackssdw_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
21622    where
21623        Assembler<'a>: VpackssdwMaskEmitter<A, B, C>,
21624    {
21625        <Self as VpackssdwMaskEmitter<A, B, C>>::vpackssdw_mask(self, op0, op1, op2);
21626    }
21627    /// `VPACKSSDW_MASKZ`.
21628    ///
21629    /// Supported operand variants:
21630    ///
21631    /// ```text
21632    /// +---+---------------+
21633    /// | # | Operands      |
21634    /// +---+---------------+
21635    /// | 1 | Xmm, Xmm, Mem |
21636    /// | 2 | Xmm, Xmm, Xmm |
21637    /// | 3 | Ymm, Ymm, Mem |
21638    /// | 4 | Ymm, Ymm, Ymm |
21639    /// | 5 | Zmm, Zmm, Mem |
21640    /// | 6 | Zmm, Zmm, Zmm |
21641    /// +---+---------------+
21642    /// ```
21643    #[inline]
21644    pub fn vpackssdw_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
21645    where
21646        Assembler<'a>: VpackssdwMaskzEmitter<A, B, C>,
21647    {
21648        <Self as VpackssdwMaskzEmitter<A, B, C>>::vpackssdw_maskz(self, op0, op1, op2);
21649    }
21650    /// `VPACKSSWB`.
21651    ///
21652    /// Supported operand variants:
21653    ///
21654    /// ```text
21655    /// +---+---------------+
21656    /// | # | Operands      |
21657    /// +---+---------------+
21658    /// | 1 | Xmm, Xmm, Mem |
21659    /// | 2 | Xmm, Xmm, Xmm |
21660    /// | 3 | Ymm, Ymm, Mem |
21661    /// | 4 | Ymm, Ymm, Ymm |
21662    /// | 5 | Zmm, Zmm, Mem |
21663    /// | 6 | Zmm, Zmm, Zmm |
21664    /// +---+---------------+
21665    /// ```
21666    #[inline]
21667    pub fn vpacksswb<A, B, C>(&mut self, op0: A, op1: B, op2: C)
21668    where
21669        Assembler<'a>: VpacksswbEmitter<A, B, C>,
21670    {
21671        <Self as VpacksswbEmitter<A, B, C>>::vpacksswb(self, op0, op1, op2);
21672    }
21673    /// `VPACKSSWB_MASK`.
21674    ///
21675    /// Supported operand variants:
21676    ///
21677    /// ```text
21678    /// +---+---------------+
21679    /// | # | Operands      |
21680    /// +---+---------------+
21681    /// | 1 | Xmm, Xmm, Mem |
21682    /// | 2 | Xmm, Xmm, Xmm |
21683    /// | 3 | Ymm, Ymm, Mem |
21684    /// | 4 | Ymm, Ymm, Ymm |
21685    /// | 5 | Zmm, Zmm, Mem |
21686    /// | 6 | Zmm, Zmm, Zmm |
21687    /// +---+---------------+
21688    /// ```
21689    #[inline]
21690    pub fn vpacksswb_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
21691    where
21692        Assembler<'a>: VpacksswbMaskEmitter<A, B, C>,
21693    {
21694        <Self as VpacksswbMaskEmitter<A, B, C>>::vpacksswb_mask(self, op0, op1, op2);
21695    }
21696    /// `VPACKSSWB_MASKZ`.
21697    ///
21698    /// Supported operand variants:
21699    ///
21700    /// ```text
21701    /// +---+---------------+
21702    /// | # | Operands      |
21703    /// +---+---------------+
21704    /// | 1 | Xmm, Xmm, Mem |
21705    /// | 2 | Xmm, Xmm, Xmm |
21706    /// | 3 | Ymm, Ymm, Mem |
21707    /// | 4 | Ymm, Ymm, Ymm |
21708    /// | 5 | Zmm, Zmm, Mem |
21709    /// | 6 | Zmm, Zmm, Zmm |
21710    /// +---+---------------+
21711    /// ```
21712    #[inline]
21713    pub fn vpacksswb_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
21714    where
21715        Assembler<'a>: VpacksswbMaskzEmitter<A, B, C>,
21716    {
21717        <Self as VpacksswbMaskzEmitter<A, B, C>>::vpacksswb_maskz(self, op0, op1, op2);
21718    }
21719    /// `VPACKUSDW`.
21720    ///
21721    /// Supported operand variants:
21722    ///
21723    /// ```text
21724    /// +---+---------------+
21725    /// | # | Operands      |
21726    /// +---+---------------+
21727    /// | 1 | Xmm, Xmm, Mem |
21728    /// | 2 | Xmm, Xmm, Xmm |
21729    /// | 3 | Ymm, Ymm, Mem |
21730    /// | 4 | Ymm, Ymm, Ymm |
21731    /// | 5 | Zmm, Zmm, Mem |
21732    /// | 6 | Zmm, Zmm, Zmm |
21733    /// +---+---------------+
21734    /// ```
21735    #[inline]
21736    pub fn vpackusdw<A, B, C>(&mut self, op0: A, op1: B, op2: C)
21737    where
21738        Assembler<'a>: VpackusdwEmitter<A, B, C>,
21739    {
21740        <Self as VpackusdwEmitter<A, B, C>>::vpackusdw(self, op0, op1, op2);
21741    }
21742    /// `VPACKUSDW_MASK`.
21743    ///
21744    /// Supported operand variants:
21745    ///
21746    /// ```text
21747    /// +---+---------------+
21748    /// | # | Operands      |
21749    /// +---+---------------+
21750    /// | 1 | Xmm, Xmm, Mem |
21751    /// | 2 | Xmm, Xmm, Xmm |
21752    /// | 3 | Ymm, Ymm, Mem |
21753    /// | 4 | Ymm, Ymm, Ymm |
21754    /// | 5 | Zmm, Zmm, Mem |
21755    /// | 6 | Zmm, Zmm, Zmm |
21756    /// +---+---------------+
21757    /// ```
21758    #[inline]
21759    pub fn vpackusdw_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
21760    where
21761        Assembler<'a>: VpackusdwMaskEmitter<A, B, C>,
21762    {
21763        <Self as VpackusdwMaskEmitter<A, B, C>>::vpackusdw_mask(self, op0, op1, op2);
21764    }
21765    /// `VPACKUSDW_MASKZ`.
21766    ///
21767    /// Supported operand variants:
21768    ///
21769    /// ```text
21770    /// +---+---------------+
21771    /// | # | Operands      |
21772    /// +---+---------------+
21773    /// | 1 | Xmm, Xmm, Mem |
21774    /// | 2 | Xmm, Xmm, Xmm |
21775    /// | 3 | Ymm, Ymm, Mem |
21776    /// | 4 | Ymm, Ymm, Ymm |
21777    /// | 5 | Zmm, Zmm, Mem |
21778    /// | 6 | Zmm, Zmm, Zmm |
21779    /// +---+---------------+
21780    /// ```
21781    #[inline]
21782    pub fn vpackusdw_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
21783    where
21784        Assembler<'a>: VpackusdwMaskzEmitter<A, B, C>,
21785    {
21786        <Self as VpackusdwMaskzEmitter<A, B, C>>::vpackusdw_maskz(self, op0, op1, op2);
21787    }
21788    /// `VPACKUSWB`.
21789    ///
21790    /// Supported operand variants:
21791    ///
21792    /// ```text
21793    /// +---+---------------+
21794    /// | # | Operands      |
21795    /// +---+---------------+
21796    /// | 1 | Xmm, Xmm, Mem |
21797    /// | 2 | Xmm, Xmm, Xmm |
21798    /// | 3 | Ymm, Ymm, Mem |
21799    /// | 4 | Ymm, Ymm, Ymm |
21800    /// | 5 | Zmm, Zmm, Mem |
21801    /// | 6 | Zmm, Zmm, Zmm |
21802    /// +---+---------------+
21803    /// ```
21804    #[inline]
21805    pub fn vpackuswb<A, B, C>(&mut self, op0: A, op1: B, op2: C)
21806    where
21807        Assembler<'a>: VpackuswbEmitter<A, B, C>,
21808    {
21809        <Self as VpackuswbEmitter<A, B, C>>::vpackuswb(self, op0, op1, op2);
21810    }
21811    /// `VPACKUSWB_MASK`.
21812    ///
21813    /// Supported operand variants:
21814    ///
21815    /// ```text
21816    /// +---+---------------+
21817    /// | # | Operands      |
21818    /// +---+---------------+
21819    /// | 1 | Xmm, Xmm, Mem |
21820    /// | 2 | Xmm, Xmm, Xmm |
21821    /// | 3 | Ymm, Ymm, Mem |
21822    /// | 4 | Ymm, Ymm, Ymm |
21823    /// | 5 | Zmm, Zmm, Mem |
21824    /// | 6 | Zmm, Zmm, Zmm |
21825    /// +---+---------------+
21826    /// ```
21827    #[inline]
21828    pub fn vpackuswb_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
21829    where
21830        Assembler<'a>: VpackuswbMaskEmitter<A, B, C>,
21831    {
21832        <Self as VpackuswbMaskEmitter<A, B, C>>::vpackuswb_mask(self, op0, op1, op2);
21833    }
21834    /// `VPACKUSWB_MASKZ`.
21835    ///
21836    /// Supported operand variants:
21837    ///
21838    /// ```text
21839    /// +---+---------------+
21840    /// | # | Operands      |
21841    /// +---+---------------+
21842    /// | 1 | Xmm, Xmm, Mem |
21843    /// | 2 | Xmm, Xmm, Xmm |
21844    /// | 3 | Ymm, Ymm, Mem |
21845    /// | 4 | Ymm, Ymm, Ymm |
21846    /// | 5 | Zmm, Zmm, Mem |
21847    /// | 6 | Zmm, Zmm, Zmm |
21848    /// +---+---------------+
21849    /// ```
21850    #[inline]
21851    pub fn vpackuswb_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
21852    where
21853        Assembler<'a>: VpackuswbMaskzEmitter<A, B, C>,
21854    {
21855        <Self as VpackuswbMaskzEmitter<A, B, C>>::vpackuswb_maskz(self, op0, op1, op2);
21856    }
21857    /// `VPADDB`.
21858    ///
21859    /// Supported operand variants:
21860    ///
21861    /// ```text
21862    /// +---+---------------+
21863    /// | # | Operands      |
21864    /// +---+---------------+
21865    /// | 1 | Xmm, Xmm, Mem |
21866    /// | 2 | Xmm, Xmm, Xmm |
21867    /// | 3 | Ymm, Ymm, Mem |
21868    /// | 4 | Ymm, Ymm, Ymm |
21869    /// | 5 | Zmm, Zmm, Mem |
21870    /// | 6 | Zmm, Zmm, Zmm |
21871    /// +---+---------------+
21872    /// ```
21873    #[inline]
21874    pub fn vpaddb<A, B, C>(&mut self, op0: A, op1: B, op2: C)
21875    where
21876        Assembler<'a>: VpaddbEmitter<A, B, C>,
21877    {
21878        <Self as VpaddbEmitter<A, B, C>>::vpaddb(self, op0, op1, op2);
21879    }
21880    /// `VPADDB_MASK`.
21881    ///
21882    /// Supported operand variants:
21883    ///
21884    /// ```text
21885    /// +---+---------------+
21886    /// | # | Operands      |
21887    /// +---+---------------+
21888    /// | 1 | Xmm, Xmm, Mem |
21889    /// | 2 | Xmm, Xmm, Xmm |
21890    /// | 3 | Ymm, Ymm, Mem |
21891    /// | 4 | Ymm, Ymm, Ymm |
21892    /// | 5 | Zmm, Zmm, Mem |
21893    /// | 6 | Zmm, Zmm, Zmm |
21894    /// +---+---------------+
21895    /// ```
21896    #[inline]
21897    pub fn vpaddb_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
21898    where
21899        Assembler<'a>: VpaddbMaskEmitter<A, B, C>,
21900    {
21901        <Self as VpaddbMaskEmitter<A, B, C>>::vpaddb_mask(self, op0, op1, op2);
21902    }
21903    /// `VPADDB_MASKZ`.
21904    ///
21905    /// Supported operand variants:
21906    ///
21907    /// ```text
21908    /// +---+---------------+
21909    /// | # | Operands      |
21910    /// +---+---------------+
21911    /// | 1 | Xmm, Xmm, Mem |
21912    /// | 2 | Xmm, Xmm, Xmm |
21913    /// | 3 | Ymm, Ymm, Mem |
21914    /// | 4 | Ymm, Ymm, Ymm |
21915    /// | 5 | Zmm, Zmm, Mem |
21916    /// | 6 | Zmm, Zmm, Zmm |
21917    /// +---+---------------+
21918    /// ```
21919    #[inline]
21920    pub fn vpaddb_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
21921    where
21922        Assembler<'a>: VpaddbMaskzEmitter<A, B, C>,
21923    {
21924        <Self as VpaddbMaskzEmitter<A, B, C>>::vpaddb_maskz(self, op0, op1, op2);
21925    }
21926    /// `VPADDSB`.
21927    ///
21928    /// Supported operand variants:
21929    ///
21930    /// ```text
21931    /// +---+---------------+
21932    /// | # | Operands      |
21933    /// +---+---------------+
21934    /// | 1 | Xmm, Xmm, Mem |
21935    /// | 2 | Xmm, Xmm, Xmm |
21936    /// | 3 | Ymm, Ymm, Mem |
21937    /// | 4 | Ymm, Ymm, Ymm |
21938    /// | 5 | Zmm, Zmm, Mem |
21939    /// | 6 | Zmm, Zmm, Zmm |
21940    /// +---+---------------+
21941    /// ```
21942    #[inline]
21943    pub fn vpaddsb<A, B, C>(&mut self, op0: A, op1: B, op2: C)
21944    where
21945        Assembler<'a>: VpaddsbEmitter<A, B, C>,
21946    {
21947        <Self as VpaddsbEmitter<A, B, C>>::vpaddsb(self, op0, op1, op2);
21948    }
21949    /// `VPADDSB_MASK`.
21950    ///
21951    /// Supported operand variants:
21952    ///
21953    /// ```text
21954    /// +---+---------------+
21955    /// | # | Operands      |
21956    /// +---+---------------+
21957    /// | 1 | Xmm, Xmm, Mem |
21958    /// | 2 | Xmm, Xmm, Xmm |
21959    /// | 3 | Ymm, Ymm, Mem |
21960    /// | 4 | Ymm, Ymm, Ymm |
21961    /// | 5 | Zmm, Zmm, Mem |
21962    /// | 6 | Zmm, Zmm, Zmm |
21963    /// +---+---------------+
21964    /// ```
21965    #[inline]
21966    pub fn vpaddsb_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
21967    where
21968        Assembler<'a>: VpaddsbMaskEmitter<A, B, C>,
21969    {
21970        <Self as VpaddsbMaskEmitter<A, B, C>>::vpaddsb_mask(self, op0, op1, op2);
21971    }
21972    /// `VPADDSB_MASKZ`.
21973    ///
21974    /// Supported operand variants:
21975    ///
21976    /// ```text
21977    /// +---+---------------+
21978    /// | # | Operands      |
21979    /// +---+---------------+
21980    /// | 1 | Xmm, Xmm, Mem |
21981    /// | 2 | Xmm, Xmm, Xmm |
21982    /// | 3 | Ymm, Ymm, Mem |
21983    /// | 4 | Ymm, Ymm, Ymm |
21984    /// | 5 | Zmm, Zmm, Mem |
21985    /// | 6 | Zmm, Zmm, Zmm |
21986    /// +---+---------------+
21987    /// ```
21988    #[inline]
21989    pub fn vpaddsb_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
21990    where
21991        Assembler<'a>: VpaddsbMaskzEmitter<A, B, C>,
21992    {
21993        <Self as VpaddsbMaskzEmitter<A, B, C>>::vpaddsb_maskz(self, op0, op1, op2);
21994    }
21995    /// `VPADDSW`.
21996    ///
21997    /// Supported operand variants:
21998    ///
21999    /// ```text
22000    /// +---+---------------+
22001    /// | # | Operands      |
22002    /// +---+---------------+
22003    /// | 1 | Xmm, Xmm, Mem |
22004    /// | 2 | Xmm, Xmm, Xmm |
22005    /// | 3 | Ymm, Ymm, Mem |
22006    /// | 4 | Ymm, Ymm, Ymm |
22007    /// | 5 | Zmm, Zmm, Mem |
22008    /// | 6 | Zmm, Zmm, Zmm |
22009    /// +---+---------------+
22010    /// ```
22011    #[inline]
22012    pub fn vpaddsw<A, B, C>(&mut self, op0: A, op1: B, op2: C)
22013    where
22014        Assembler<'a>: VpaddswEmitter<A, B, C>,
22015    {
22016        <Self as VpaddswEmitter<A, B, C>>::vpaddsw(self, op0, op1, op2);
22017    }
22018    /// `VPADDSW_MASK`.
22019    ///
22020    /// Supported operand variants:
22021    ///
22022    /// ```text
22023    /// +---+---------------+
22024    /// | # | Operands      |
22025    /// +---+---------------+
22026    /// | 1 | Xmm, Xmm, Mem |
22027    /// | 2 | Xmm, Xmm, Xmm |
22028    /// | 3 | Ymm, Ymm, Mem |
22029    /// | 4 | Ymm, Ymm, Ymm |
22030    /// | 5 | Zmm, Zmm, Mem |
22031    /// | 6 | Zmm, Zmm, Zmm |
22032    /// +---+---------------+
22033    /// ```
22034    #[inline]
22035    pub fn vpaddsw_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
22036    where
22037        Assembler<'a>: VpaddswMaskEmitter<A, B, C>,
22038    {
22039        <Self as VpaddswMaskEmitter<A, B, C>>::vpaddsw_mask(self, op0, op1, op2);
22040    }
22041    /// `VPADDSW_MASKZ`.
22042    ///
22043    /// Supported operand variants:
22044    ///
22045    /// ```text
22046    /// +---+---------------+
22047    /// | # | Operands      |
22048    /// +---+---------------+
22049    /// | 1 | Xmm, Xmm, Mem |
22050    /// | 2 | Xmm, Xmm, Xmm |
22051    /// | 3 | Ymm, Ymm, Mem |
22052    /// | 4 | Ymm, Ymm, Ymm |
22053    /// | 5 | Zmm, Zmm, Mem |
22054    /// | 6 | Zmm, Zmm, Zmm |
22055    /// +---+---------------+
22056    /// ```
22057    #[inline]
22058    pub fn vpaddsw_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
22059    where
22060        Assembler<'a>: VpaddswMaskzEmitter<A, B, C>,
22061    {
22062        <Self as VpaddswMaskzEmitter<A, B, C>>::vpaddsw_maskz(self, op0, op1, op2);
22063    }
22064    /// `VPADDUSB`.
22065    ///
22066    /// Supported operand variants:
22067    ///
22068    /// ```text
22069    /// +---+---------------+
22070    /// | # | Operands      |
22071    /// +---+---------------+
22072    /// | 1 | Xmm, Xmm, Mem |
22073    /// | 2 | Xmm, Xmm, Xmm |
22074    /// | 3 | Ymm, Ymm, Mem |
22075    /// | 4 | Ymm, Ymm, Ymm |
22076    /// | 5 | Zmm, Zmm, Mem |
22077    /// | 6 | Zmm, Zmm, Zmm |
22078    /// +---+---------------+
22079    /// ```
22080    #[inline]
22081    pub fn vpaddusb<A, B, C>(&mut self, op0: A, op1: B, op2: C)
22082    where
22083        Assembler<'a>: VpaddusbEmitter<A, B, C>,
22084    {
22085        <Self as VpaddusbEmitter<A, B, C>>::vpaddusb(self, op0, op1, op2);
22086    }
22087    /// `VPADDUSB_MASK`.
22088    ///
22089    /// Supported operand variants:
22090    ///
22091    /// ```text
22092    /// +---+---------------+
22093    /// | # | Operands      |
22094    /// +---+---------------+
22095    /// | 1 | Xmm, Xmm, Mem |
22096    /// | 2 | Xmm, Xmm, Xmm |
22097    /// | 3 | Ymm, Ymm, Mem |
22098    /// | 4 | Ymm, Ymm, Ymm |
22099    /// | 5 | Zmm, Zmm, Mem |
22100    /// | 6 | Zmm, Zmm, Zmm |
22101    /// +---+---------------+
22102    /// ```
22103    #[inline]
22104    pub fn vpaddusb_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
22105    where
22106        Assembler<'a>: VpaddusbMaskEmitter<A, B, C>,
22107    {
22108        <Self as VpaddusbMaskEmitter<A, B, C>>::vpaddusb_mask(self, op0, op1, op2);
22109    }
22110    /// `VPADDUSB_MASKZ`.
22111    ///
22112    /// Supported operand variants:
22113    ///
22114    /// ```text
22115    /// +---+---------------+
22116    /// | # | Operands      |
22117    /// +---+---------------+
22118    /// | 1 | Xmm, Xmm, Mem |
22119    /// | 2 | Xmm, Xmm, Xmm |
22120    /// | 3 | Ymm, Ymm, Mem |
22121    /// | 4 | Ymm, Ymm, Ymm |
22122    /// | 5 | Zmm, Zmm, Mem |
22123    /// | 6 | Zmm, Zmm, Zmm |
22124    /// +---+---------------+
22125    /// ```
22126    #[inline]
22127    pub fn vpaddusb_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
22128    where
22129        Assembler<'a>: VpaddusbMaskzEmitter<A, B, C>,
22130    {
22131        <Self as VpaddusbMaskzEmitter<A, B, C>>::vpaddusb_maskz(self, op0, op1, op2);
22132    }
22133    /// `VPADDUSW`.
22134    ///
22135    /// Supported operand variants:
22136    ///
22137    /// ```text
22138    /// +---+---------------+
22139    /// | # | Operands      |
22140    /// +---+---------------+
22141    /// | 1 | Xmm, Xmm, Mem |
22142    /// | 2 | Xmm, Xmm, Xmm |
22143    /// | 3 | Ymm, Ymm, Mem |
22144    /// | 4 | Ymm, Ymm, Ymm |
22145    /// | 5 | Zmm, Zmm, Mem |
22146    /// | 6 | Zmm, Zmm, Zmm |
22147    /// +---+---------------+
22148    /// ```
22149    #[inline]
22150    pub fn vpaddusw<A, B, C>(&mut self, op0: A, op1: B, op2: C)
22151    where
22152        Assembler<'a>: VpadduswEmitter<A, B, C>,
22153    {
22154        <Self as VpadduswEmitter<A, B, C>>::vpaddusw(self, op0, op1, op2);
22155    }
22156    /// `VPADDUSW_MASK`.
22157    ///
22158    /// Supported operand variants:
22159    ///
22160    /// ```text
22161    /// +---+---------------+
22162    /// | # | Operands      |
22163    /// +---+---------------+
22164    /// | 1 | Xmm, Xmm, Mem |
22165    /// | 2 | Xmm, Xmm, Xmm |
22166    /// | 3 | Ymm, Ymm, Mem |
22167    /// | 4 | Ymm, Ymm, Ymm |
22168    /// | 5 | Zmm, Zmm, Mem |
22169    /// | 6 | Zmm, Zmm, Zmm |
22170    /// +---+---------------+
22171    /// ```
22172    #[inline]
22173    pub fn vpaddusw_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
22174    where
22175        Assembler<'a>: VpadduswMaskEmitter<A, B, C>,
22176    {
22177        <Self as VpadduswMaskEmitter<A, B, C>>::vpaddusw_mask(self, op0, op1, op2);
22178    }
22179    /// `VPADDUSW_MASKZ`.
22180    ///
22181    /// Supported operand variants:
22182    ///
22183    /// ```text
22184    /// +---+---------------+
22185    /// | # | Operands      |
22186    /// +---+---------------+
22187    /// | 1 | Xmm, Xmm, Mem |
22188    /// | 2 | Xmm, Xmm, Xmm |
22189    /// | 3 | Ymm, Ymm, Mem |
22190    /// | 4 | Ymm, Ymm, Ymm |
22191    /// | 5 | Zmm, Zmm, Mem |
22192    /// | 6 | Zmm, Zmm, Zmm |
22193    /// +---+---------------+
22194    /// ```
22195    #[inline]
22196    pub fn vpaddusw_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
22197    where
22198        Assembler<'a>: VpadduswMaskzEmitter<A, B, C>,
22199    {
22200        <Self as VpadduswMaskzEmitter<A, B, C>>::vpaddusw_maskz(self, op0, op1, op2);
22201    }
22202    /// `VPADDW`.
22203    ///
22204    /// Supported operand variants:
22205    ///
22206    /// ```text
22207    /// +---+---------------+
22208    /// | # | Operands      |
22209    /// +---+---------------+
22210    /// | 1 | Xmm, Xmm, Mem |
22211    /// | 2 | Xmm, Xmm, Xmm |
22212    /// | 3 | Ymm, Ymm, Mem |
22213    /// | 4 | Ymm, Ymm, Ymm |
22214    /// | 5 | Zmm, Zmm, Mem |
22215    /// | 6 | Zmm, Zmm, Zmm |
22216    /// +---+---------------+
22217    /// ```
22218    #[inline]
22219    pub fn vpaddw<A, B, C>(&mut self, op0: A, op1: B, op2: C)
22220    where
22221        Assembler<'a>: VpaddwEmitter<A, B, C>,
22222    {
22223        <Self as VpaddwEmitter<A, B, C>>::vpaddw(self, op0, op1, op2);
22224    }
22225    /// `VPADDW_MASK`.
22226    ///
22227    /// Supported operand variants:
22228    ///
22229    /// ```text
22230    /// +---+---------------+
22231    /// | # | Operands      |
22232    /// +---+---------------+
22233    /// | 1 | Xmm, Xmm, Mem |
22234    /// | 2 | Xmm, Xmm, Xmm |
22235    /// | 3 | Ymm, Ymm, Mem |
22236    /// | 4 | Ymm, Ymm, Ymm |
22237    /// | 5 | Zmm, Zmm, Mem |
22238    /// | 6 | Zmm, Zmm, Zmm |
22239    /// +---+---------------+
22240    /// ```
22241    #[inline]
22242    pub fn vpaddw_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
22243    where
22244        Assembler<'a>: VpaddwMaskEmitter<A, B, C>,
22245    {
22246        <Self as VpaddwMaskEmitter<A, B, C>>::vpaddw_mask(self, op0, op1, op2);
22247    }
22248    /// `VPADDW_MASKZ`.
22249    ///
22250    /// Supported operand variants:
22251    ///
22252    /// ```text
22253    /// +---+---------------+
22254    /// | # | Operands      |
22255    /// +---+---------------+
22256    /// | 1 | Xmm, Xmm, Mem |
22257    /// | 2 | Xmm, Xmm, Xmm |
22258    /// | 3 | Ymm, Ymm, Mem |
22259    /// | 4 | Ymm, Ymm, Ymm |
22260    /// | 5 | Zmm, Zmm, Mem |
22261    /// | 6 | Zmm, Zmm, Zmm |
22262    /// +---+---------------+
22263    /// ```
22264    #[inline]
22265    pub fn vpaddw_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
22266    where
22267        Assembler<'a>: VpaddwMaskzEmitter<A, B, C>,
22268    {
22269        <Self as VpaddwMaskzEmitter<A, B, C>>::vpaddw_maskz(self, op0, op1, op2);
22270    }
22271    /// `VPALIGNR`.
22272    ///
22273    /// Supported operand variants:
22274    ///
22275    /// ```text
22276    /// +---+--------------------+
22277    /// | # | Operands           |
22278    /// +---+--------------------+
22279    /// | 1 | Xmm, Xmm, Mem, Imm |
22280    /// | 2 | Xmm, Xmm, Xmm, Imm |
22281    /// | 3 | Ymm, Ymm, Mem, Imm |
22282    /// | 4 | Ymm, Ymm, Ymm, Imm |
22283    /// | 5 | Zmm, Zmm, Mem, Imm |
22284    /// | 6 | Zmm, Zmm, Zmm, Imm |
22285    /// +---+--------------------+
22286    /// ```
22287    #[inline]
22288    pub fn vpalignr<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
22289    where
22290        Assembler<'a>: VpalignrEmitter<A, B, C, D>,
22291    {
22292        <Self as VpalignrEmitter<A, B, C, D>>::vpalignr(self, op0, op1, op2, op3);
22293    }
22294    /// `VPALIGNR_MASK`.
22295    ///
22296    /// Supported operand variants:
22297    ///
22298    /// ```text
22299    /// +---+--------------------+
22300    /// | # | Operands           |
22301    /// +---+--------------------+
22302    /// | 1 | Xmm, Xmm, Mem, Imm |
22303    /// | 2 | Xmm, Xmm, Xmm, Imm |
22304    /// | 3 | Ymm, Ymm, Mem, Imm |
22305    /// | 4 | Ymm, Ymm, Ymm, Imm |
22306    /// | 5 | Zmm, Zmm, Mem, Imm |
22307    /// | 6 | Zmm, Zmm, Zmm, Imm |
22308    /// +---+--------------------+
22309    /// ```
22310    #[inline]
22311    pub fn vpalignr_mask<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
22312    where
22313        Assembler<'a>: VpalignrMaskEmitter<A, B, C, D>,
22314    {
22315        <Self as VpalignrMaskEmitter<A, B, C, D>>::vpalignr_mask(self, op0, op1, op2, op3);
22316    }
22317    /// `VPALIGNR_MASKZ`.
22318    ///
22319    /// Supported operand variants:
22320    ///
22321    /// ```text
22322    /// +---+--------------------+
22323    /// | # | Operands           |
22324    /// +---+--------------------+
22325    /// | 1 | Xmm, Xmm, Mem, Imm |
22326    /// | 2 | Xmm, Xmm, Xmm, Imm |
22327    /// | 3 | Ymm, Ymm, Mem, Imm |
22328    /// | 4 | Ymm, Ymm, Ymm, Imm |
22329    /// | 5 | Zmm, Zmm, Mem, Imm |
22330    /// | 6 | Zmm, Zmm, Zmm, Imm |
22331    /// +---+--------------------+
22332    /// ```
22333    #[inline]
22334    pub fn vpalignr_maskz<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
22335    where
22336        Assembler<'a>: VpalignrMaskzEmitter<A, B, C, D>,
22337    {
22338        <Self as VpalignrMaskzEmitter<A, B, C, D>>::vpalignr_maskz(self, op0, op1, op2, op3);
22339    }
22340    /// `VPAVGB`.
22341    ///
22342    /// Supported operand variants:
22343    ///
22344    /// ```text
22345    /// +---+---------------+
22346    /// | # | Operands      |
22347    /// +---+---------------+
22348    /// | 1 | Xmm, Xmm, Mem |
22349    /// | 2 | Xmm, Xmm, Xmm |
22350    /// | 3 | Ymm, Ymm, Mem |
22351    /// | 4 | Ymm, Ymm, Ymm |
22352    /// | 5 | Zmm, Zmm, Mem |
22353    /// | 6 | Zmm, Zmm, Zmm |
22354    /// +---+---------------+
22355    /// ```
22356    #[inline]
22357    pub fn vpavgb<A, B, C>(&mut self, op0: A, op1: B, op2: C)
22358    where
22359        Assembler<'a>: VpavgbEmitter<A, B, C>,
22360    {
22361        <Self as VpavgbEmitter<A, B, C>>::vpavgb(self, op0, op1, op2);
22362    }
22363    /// `VPAVGB_MASK`.
22364    ///
22365    /// Supported operand variants:
22366    ///
22367    /// ```text
22368    /// +---+---------------+
22369    /// | # | Operands      |
22370    /// +---+---------------+
22371    /// | 1 | Xmm, Xmm, Mem |
22372    /// | 2 | Xmm, Xmm, Xmm |
22373    /// | 3 | Ymm, Ymm, Mem |
22374    /// | 4 | Ymm, Ymm, Ymm |
22375    /// | 5 | Zmm, Zmm, Mem |
22376    /// | 6 | Zmm, Zmm, Zmm |
22377    /// +---+---------------+
22378    /// ```
22379    #[inline]
22380    pub fn vpavgb_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
22381    where
22382        Assembler<'a>: VpavgbMaskEmitter<A, B, C>,
22383    {
22384        <Self as VpavgbMaskEmitter<A, B, C>>::vpavgb_mask(self, op0, op1, op2);
22385    }
22386    /// `VPAVGB_MASKZ`.
22387    ///
22388    /// Supported operand variants:
22389    ///
22390    /// ```text
22391    /// +---+---------------+
22392    /// | # | Operands      |
22393    /// +---+---------------+
22394    /// | 1 | Xmm, Xmm, Mem |
22395    /// | 2 | Xmm, Xmm, Xmm |
22396    /// | 3 | Ymm, Ymm, Mem |
22397    /// | 4 | Ymm, Ymm, Ymm |
22398    /// | 5 | Zmm, Zmm, Mem |
22399    /// | 6 | Zmm, Zmm, Zmm |
22400    /// +---+---------------+
22401    /// ```
22402    #[inline]
22403    pub fn vpavgb_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
22404    where
22405        Assembler<'a>: VpavgbMaskzEmitter<A, B, C>,
22406    {
22407        <Self as VpavgbMaskzEmitter<A, B, C>>::vpavgb_maskz(self, op0, op1, op2);
22408    }
22409    /// `VPAVGW`.
22410    ///
22411    /// Supported operand variants:
22412    ///
22413    /// ```text
22414    /// +---+---------------+
22415    /// | # | Operands      |
22416    /// +---+---------------+
22417    /// | 1 | Xmm, Xmm, Mem |
22418    /// | 2 | Xmm, Xmm, Xmm |
22419    /// | 3 | Ymm, Ymm, Mem |
22420    /// | 4 | Ymm, Ymm, Ymm |
22421    /// | 5 | Zmm, Zmm, Mem |
22422    /// | 6 | Zmm, Zmm, Zmm |
22423    /// +---+---------------+
22424    /// ```
22425    #[inline]
22426    pub fn vpavgw<A, B, C>(&mut self, op0: A, op1: B, op2: C)
22427    where
22428        Assembler<'a>: VpavgwEmitter<A, B, C>,
22429    {
22430        <Self as VpavgwEmitter<A, B, C>>::vpavgw(self, op0, op1, op2);
22431    }
22432    /// `VPAVGW_MASK`.
22433    ///
22434    /// Supported operand variants:
22435    ///
22436    /// ```text
22437    /// +---+---------------+
22438    /// | # | Operands      |
22439    /// +---+---------------+
22440    /// | 1 | Xmm, Xmm, Mem |
22441    /// | 2 | Xmm, Xmm, Xmm |
22442    /// | 3 | Ymm, Ymm, Mem |
22443    /// | 4 | Ymm, Ymm, Ymm |
22444    /// | 5 | Zmm, Zmm, Mem |
22445    /// | 6 | Zmm, Zmm, Zmm |
22446    /// +---+---------------+
22447    /// ```
22448    #[inline]
22449    pub fn vpavgw_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
22450    where
22451        Assembler<'a>: VpavgwMaskEmitter<A, B, C>,
22452    {
22453        <Self as VpavgwMaskEmitter<A, B, C>>::vpavgw_mask(self, op0, op1, op2);
22454    }
22455    /// `VPAVGW_MASKZ`.
22456    ///
22457    /// Supported operand variants:
22458    ///
22459    /// ```text
22460    /// +---+---------------+
22461    /// | # | Operands      |
22462    /// +---+---------------+
22463    /// | 1 | Xmm, Xmm, Mem |
22464    /// | 2 | Xmm, Xmm, Xmm |
22465    /// | 3 | Ymm, Ymm, Mem |
22466    /// | 4 | Ymm, Ymm, Ymm |
22467    /// | 5 | Zmm, Zmm, Mem |
22468    /// | 6 | Zmm, Zmm, Zmm |
22469    /// +---+---------------+
22470    /// ```
22471    #[inline]
22472    pub fn vpavgw_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
22473    where
22474        Assembler<'a>: VpavgwMaskzEmitter<A, B, C>,
22475    {
22476        <Self as VpavgwMaskzEmitter<A, B, C>>::vpavgw_maskz(self, op0, op1, op2);
22477    }
22478    /// `VPBLENDMB`.
22479    ///
22480    /// Supported operand variants:
22481    ///
22482    /// ```text
22483    /// +---+---------------+
22484    /// | # | Operands      |
22485    /// +---+---------------+
22486    /// | 1 | Xmm, Xmm, Mem |
22487    /// | 2 | Xmm, Xmm, Xmm |
22488    /// | 3 | Ymm, Ymm, Mem |
22489    /// | 4 | Ymm, Ymm, Ymm |
22490    /// | 5 | Zmm, Zmm, Mem |
22491    /// | 6 | Zmm, Zmm, Zmm |
22492    /// +---+---------------+
22493    /// ```
22494    #[inline]
22495    pub fn vpblendmb<A, B, C>(&mut self, op0: A, op1: B, op2: C)
22496    where
22497        Assembler<'a>: VpblendmbEmitter<A, B, C>,
22498    {
22499        <Self as VpblendmbEmitter<A, B, C>>::vpblendmb(self, op0, op1, op2);
22500    }
22501    /// `VPBLENDMB_MASK`.
22502    ///
22503    /// Supported operand variants:
22504    ///
22505    /// ```text
22506    /// +---+---------------+
22507    /// | # | Operands      |
22508    /// +---+---------------+
22509    /// | 1 | Xmm, Xmm, Mem |
22510    /// | 2 | Xmm, Xmm, Xmm |
22511    /// | 3 | Ymm, Ymm, Mem |
22512    /// | 4 | Ymm, Ymm, Ymm |
22513    /// | 5 | Zmm, Zmm, Mem |
22514    /// | 6 | Zmm, Zmm, Zmm |
22515    /// +---+---------------+
22516    /// ```
22517    #[inline]
22518    pub fn vpblendmb_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
22519    where
22520        Assembler<'a>: VpblendmbMaskEmitter<A, B, C>,
22521    {
22522        <Self as VpblendmbMaskEmitter<A, B, C>>::vpblendmb_mask(self, op0, op1, op2);
22523    }
22524    /// `VPBLENDMB_MASKZ`.
22525    ///
22526    /// Supported operand variants:
22527    ///
22528    /// ```text
22529    /// +---+---------------+
22530    /// | # | Operands      |
22531    /// +---+---------------+
22532    /// | 1 | Xmm, Xmm, Mem |
22533    /// | 2 | Xmm, Xmm, Xmm |
22534    /// | 3 | Ymm, Ymm, Mem |
22535    /// | 4 | Ymm, Ymm, Ymm |
22536    /// | 5 | Zmm, Zmm, Mem |
22537    /// | 6 | Zmm, Zmm, Zmm |
22538    /// +---+---------------+
22539    /// ```
22540    #[inline]
22541    pub fn vpblendmb_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
22542    where
22543        Assembler<'a>: VpblendmbMaskzEmitter<A, B, C>,
22544    {
22545        <Self as VpblendmbMaskzEmitter<A, B, C>>::vpblendmb_maskz(self, op0, op1, op2);
22546    }
22547    /// `VPBLENDMW`.
22548    ///
22549    /// Supported operand variants:
22550    ///
22551    /// ```text
22552    /// +---+---------------+
22553    /// | # | Operands      |
22554    /// +---+---------------+
22555    /// | 1 | Xmm, Xmm, Mem |
22556    /// | 2 | Xmm, Xmm, Xmm |
22557    /// | 3 | Ymm, Ymm, Mem |
22558    /// | 4 | Ymm, Ymm, Ymm |
22559    /// | 5 | Zmm, Zmm, Mem |
22560    /// | 6 | Zmm, Zmm, Zmm |
22561    /// +---+---------------+
22562    /// ```
22563    #[inline]
22564    pub fn vpblendmw<A, B, C>(&mut self, op0: A, op1: B, op2: C)
22565    where
22566        Assembler<'a>: VpblendmwEmitter<A, B, C>,
22567    {
22568        <Self as VpblendmwEmitter<A, B, C>>::vpblendmw(self, op0, op1, op2);
22569    }
22570    /// `VPBLENDMW_MASK`.
22571    ///
22572    /// Supported operand variants:
22573    ///
22574    /// ```text
22575    /// +---+---------------+
22576    /// | # | Operands      |
22577    /// +---+---------------+
22578    /// | 1 | Xmm, Xmm, Mem |
22579    /// | 2 | Xmm, Xmm, Xmm |
22580    /// | 3 | Ymm, Ymm, Mem |
22581    /// | 4 | Ymm, Ymm, Ymm |
22582    /// | 5 | Zmm, Zmm, Mem |
22583    /// | 6 | Zmm, Zmm, Zmm |
22584    /// +---+---------------+
22585    /// ```
22586    #[inline]
22587    pub fn vpblendmw_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
22588    where
22589        Assembler<'a>: VpblendmwMaskEmitter<A, B, C>,
22590    {
22591        <Self as VpblendmwMaskEmitter<A, B, C>>::vpblendmw_mask(self, op0, op1, op2);
22592    }
22593    /// `VPBLENDMW_MASKZ`.
22594    ///
22595    /// Supported operand variants:
22596    ///
22597    /// ```text
22598    /// +---+---------------+
22599    /// | # | Operands      |
22600    /// +---+---------------+
22601    /// | 1 | Xmm, Xmm, Mem |
22602    /// | 2 | Xmm, Xmm, Xmm |
22603    /// | 3 | Ymm, Ymm, Mem |
22604    /// | 4 | Ymm, Ymm, Ymm |
22605    /// | 5 | Zmm, Zmm, Mem |
22606    /// | 6 | Zmm, Zmm, Zmm |
22607    /// +---+---------------+
22608    /// ```
22609    #[inline]
22610    pub fn vpblendmw_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
22611    where
22612        Assembler<'a>: VpblendmwMaskzEmitter<A, B, C>,
22613    {
22614        <Self as VpblendmwMaskzEmitter<A, B, C>>::vpblendmw_maskz(self, op0, op1, op2);
22615    }
22616    /// `VPBROADCASTB`.
22617    ///
22618    /// Supported operand variants:
22619    ///
22620    /// ```text
22621    /// +---+----------+
22622    /// | # | Operands |
22623    /// +---+----------+
22624    /// | 1 | Xmm, Mem |
22625    /// | 2 | Xmm, Xmm |
22626    /// | 3 | Ymm, Mem |
22627    /// | 4 | Ymm, Xmm |
22628    /// | 5 | Zmm, Mem |
22629    /// | 6 | Zmm, Xmm |
22630    /// +---+----------+
22631    /// ```
22632    #[inline]
22633    pub fn vpbroadcastb<A, B>(&mut self, op0: A, op1: B)
22634    where
22635        Assembler<'a>: VpbroadcastbEmitter<A, B>,
22636    {
22637        <Self as VpbroadcastbEmitter<A, B>>::vpbroadcastb(self, op0, op1);
22638    }
22639    /// `VPBROADCASTB_GP`.
22640    ///
22641    /// Supported operand variants:
22642    ///
22643    /// ```text
22644    /// +---+----------+
22645    /// | # | Operands |
22646    /// +---+----------+
22647    /// | 1 | Xmm, Gpd |
22648    /// | 2 | Ymm, Gpd |
22649    /// | 3 | Zmm, Gpd |
22650    /// +---+----------+
22651    /// ```
22652    #[inline]
22653    pub fn vpbroadcastb_gp<A, B>(&mut self, op0: A, op1: B)
22654    where
22655        Assembler<'a>: VpbroadcastbGpEmitter<A, B>,
22656    {
22657        <Self as VpbroadcastbGpEmitter<A, B>>::vpbroadcastb_gp(self, op0, op1);
22658    }
22659    /// `VPBROADCASTB_GP_MASK`.
22660    ///
22661    /// Supported operand variants:
22662    ///
22663    /// ```text
22664    /// +---+----------+
22665    /// | # | Operands |
22666    /// +---+----------+
22667    /// | 1 | Xmm, Gpd |
22668    /// | 2 | Ymm, Gpd |
22669    /// | 3 | Zmm, Gpd |
22670    /// +---+----------+
22671    /// ```
22672    #[inline]
22673    pub fn vpbroadcastb_gp_mask<A, B>(&mut self, op0: A, op1: B)
22674    where
22675        Assembler<'a>: VpbroadcastbGpMaskEmitter<A, B>,
22676    {
22677        <Self as VpbroadcastbGpMaskEmitter<A, B>>::vpbroadcastb_gp_mask(self, op0, op1);
22678    }
22679    /// `VPBROADCASTB_GP_MASKZ`.
22680    ///
22681    /// Supported operand variants:
22682    ///
22683    /// ```text
22684    /// +---+----------+
22685    /// | # | Operands |
22686    /// +---+----------+
22687    /// | 1 | Xmm, Gpd |
22688    /// | 2 | Ymm, Gpd |
22689    /// | 3 | Zmm, Gpd |
22690    /// +---+----------+
22691    /// ```
22692    #[inline]
22693    pub fn vpbroadcastb_gp_maskz<A, B>(&mut self, op0: A, op1: B)
22694    where
22695        Assembler<'a>: VpbroadcastbGpMaskzEmitter<A, B>,
22696    {
22697        <Self as VpbroadcastbGpMaskzEmitter<A, B>>::vpbroadcastb_gp_maskz(self, op0, op1);
22698    }
22699    /// `VPBROADCASTB_MASK`.
22700    ///
22701    /// Supported operand variants:
22702    ///
22703    /// ```text
22704    /// +---+----------+
22705    /// | # | Operands |
22706    /// +---+----------+
22707    /// | 1 | Xmm, Mem |
22708    /// | 2 | Xmm, Xmm |
22709    /// | 3 | Ymm, Mem |
22710    /// | 4 | Ymm, Xmm |
22711    /// | 5 | Zmm, Mem |
22712    /// | 6 | Zmm, Xmm |
22713    /// +---+----------+
22714    /// ```
22715    #[inline]
22716    pub fn vpbroadcastb_mask<A, B>(&mut self, op0: A, op1: B)
22717    where
22718        Assembler<'a>: VpbroadcastbMaskEmitter<A, B>,
22719    {
22720        <Self as VpbroadcastbMaskEmitter<A, B>>::vpbroadcastb_mask(self, op0, op1);
22721    }
22722    /// `VPBROADCASTB_MASKZ`.
22723    ///
22724    /// Supported operand variants:
22725    ///
22726    /// ```text
22727    /// +---+----------+
22728    /// | # | Operands |
22729    /// +---+----------+
22730    /// | 1 | Xmm, Mem |
22731    /// | 2 | Xmm, Xmm |
22732    /// | 3 | Ymm, Mem |
22733    /// | 4 | Ymm, Xmm |
22734    /// | 5 | Zmm, Mem |
22735    /// | 6 | Zmm, Xmm |
22736    /// +---+----------+
22737    /// ```
22738    #[inline]
22739    pub fn vpbroadcastb_maskz<A, B>(&mut self, op0: A, op1: B)
22740    where
22741        Assembler<'a>: VpbroadcastbMaskzEmitter<A, B>,
22742    {
22743        <Self as VpbroadcastbMaskzEmitter<A, B>>::vpbroadcastb_maskz(self, op0, op1);
22744    }
22745    /// `VPBROADCASTW`.
22746    ///
22747    /// Supported operand variants:
22748    ///
22749    /// ```text
22750    /// +---+----------+
22751    /// | # | Operands |
22752    /// +---+----------+
22753    /// | 1 | Xmm, Mem |
22754    /// | 2 | Xmm, Xmm |
22755    /// | 3 | Ymm, Mem |
22756    /// | 4 | Ymm, Xmm |
22757    /// | 5 | Zmm, Mem |
22758    /// | 6 | Zmm, Xmm |
22759    /// +---+----------+
22760    /// ```
22761    #[inline]
22762    pub fn vpbroadcastw<A, B>(&mut self, op0: A, op1: B)
22763    where
22764        Assembler<'a>: VpbroadcastwEmitter<A, B>,
22765    {
22766        <Self as VpbroadcastwEmitter<A, B>>::vpbroadcastw(self, op0, op1);
22767    }
22768    /// `VPBROADCASTW_GP`.
22769    ///
22770    /// Supported operand variants:
22771    ///
22772    /// ```text
22773    /// +---+----------+
22774    /// | # | Operands |
22775    /// +---+----------+
22776    /// | 1 | Xmm, Gpd |
22777    /// | 2 | Ymm, Gpd |
22778    /// | 3 | Zmm, Gpd |
22779    /// +---+----------+
22780    /// ```
22781    #[inline]
22782    pub fn vpbroadcastw_gp<A, B>(&mut self, op0: A, op1: B)
22783    where
22784        Assembler<'a>: VpbroadcastwGpEmitter<A, B>,
22785    {
22786        <Self as VpbroadcastwGpEmitter<A, B>>::vpbroadcastw_gp(self, op0, op1);
22787    }
22788    /// `VPBROADCASTW_GP_MASK`.
22789    ///
22790    /// Supported operand variants:
22791    ///
22792    /// ```text
22793    /// +---+----------+
22794    /// | # | Operands |
22795    /// +---+----------+
22796    /// | 1 | Xmm, Gpd |
22797    /// | 2 | Ymm, Gpd |
22798    /// | 3 | Zmm, Gpd |
22799    /// +---+----------+
22800    /// ```
22801    #[inline]
22802    pub fn vpbroadcastw_gp_mask<A, B>(&mut self, op0: A, op1: B)
22803    where
22804        Assembler<'a>: VpbroadcastwGpMaskEmitter<A, B>,
22805    {
22806        <Self as VpbroadcastwGpMaskEmitter<A, B>>::vpbroadcastw_gp_mask(self, op0, op1);
22807    }
22808    /// `VPBROADCASTW_GP_MASKZ`.
22809    ///
22810    /// Supported operand variants:
22811    ///
22812    /// ```text
22813    /// +---+----------+
22814    /// | # | Operands |
22815    /// +---+----------+
22816    /// | 1 | Xmm, Gpd |
22817    /// | 2 | Ymm, Gpd |
22818    /// | 3 | Zmm, Gpd |
22819    /// +---+----------+
22820    /// ```
22821    #[inline]
22822    pub fn vpbroadcastw_gp_maskz<A, B>(&mut self, op0: A, op1: B)
22823    where
22824        Assembler<'a>: VpbroadcastwGpMaskzEmitter<A, B>,
22825    {
22826        <Self as VpbroadcastwGpMaskzEmitter<A, B>>::vpbroadcastw_gp_maskz(self, op0, op1);
22827    }
22828    /// `VPBROADCASTW_MASK`.
22829    ///
22830    /// Supported operand variants:
22831    ///
22832    /// ```text
22833    /// +---+----------+
22834    /// | # | Operands |
22835    /// +---+----------+
22836    /// | 1 | Xmm, Mem |
22837    /// | 2 | Xmm, Xmm |
22838    /// | 3 | Ymm, Mem |
22839    /// | 4 | Ymm, Xmm |
22840    /// | 5 | Zmm, Mem |
22841    /// | 6 | Zmm, Xmm |
22842    /// +---+----------+
22843    /// ```
22844    #[inline]
22845    pub fn vpbroadcastw_mask<A, B>(&mut self, op0: A, op1: B)
22846    where
22847        Assembler<'a>: VpbroadcastwMaskEmitter<A, B>,
22848    {
22849        <Self as VpbroadcastwMaskEmitter<A, B>>::vpbroadcastw_mask(self, op0, op1);
22850    }
22851    /// `VPBROADCASTW_MASKZ`.
22852    ///
22853    /// Supported operand variants:
22854    ///
22855    /// ```text
22856    /// +---+----------+
22857    /// | # | Operands |
22858    /// +---+----------+
22859    /// | 1 | Xmm, Mem |
22860    /// | 2 | Xmm, Xmm |
22861    /// | 3 | Ymm, Mem |
22862    /// | 4 | Ymm, Xmm |
22863    /// | 5 | Zmm, Mem |
22864    /// | 6 | Zmm, Xmm |
22865    /// +---+----------+
22866    /// ```
22867    #[inline]
22868    pub fn vpbroadcastw_maskz<A, B>(&mut self, op0: A, op1: B)
22869    where
22870        Assembler<'a>: VpbroadcastwMaskzEmitter<A, B>,
22871    {
22872        <Self as VpbroadcastwMaskzEmitter<A, B>>::vpbroadcastw_maskz(self, op0, op1);
22873    }
22874    /// `VPCMPB`.
22875    ///
22876    /// Supported operand variants:
22877    ///
22878    /// ```text
22879    /// +---+---------------------+
22880    /// | # | Operands            |
22881    /// +---+---------------------+
22882    /// | 1 | KReg, Xmm, Mem, Imm |
22883    /// | 2 | KReg, Xmm, Xmm, Imm |
22884    /// | 3 | KReg, Ymm, Mem, Imm |
22885    /// | 4 | KReg, Ymm, Ymm, Imm |
22886    /// | 5 | KReg, Zmm, Mem, Imm |
22887    /// | 6 | KReg, Zmm, Zmm, Imm |
22888    /// +---+---------------------+
22889    /// ```
22890    #[inline]
22891    pub fn vpcmpb<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
22892    where
22893        Assembler<'a>: VpcmpbEmitter<A, B, C, D>,
22894    {
22895        <Self as VpcmpbEmitter<A, B, C, D>>::vpcmpb(self, op0, op1, op2, op3);
22896    }
22897    /// `VPCMPB_MASK`.
22898    ///
22899    /// Supported operand variants:
22900    ///
22901    /// ```text
22902    /// +---+---------------------+
22903    /// | # | Operands            |
22904    /// +---+---------------------+
22905    /// | 1 | KReg, Xmm, Mem, Imm |
22906    /// | 2 | KReg, Xmm, Xmm, Imm |
22907    /// | 3 | KReg, Ymm, Mem, Imm |
22908    /// | 4 | KReg, Ymm, Ymm, Imm |
22909    /// | 5 | KReg, Zmm, Mem, Imm |
22910    /// | 6 | KReg, Zmm, Zmm, Imm |
22911    /// +---+---------------------+
22912    /// ```
22913    #[inline]
22914    pub fn vpcmpb_mask<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
22915    where
22916        Assembler<'a>: VpcmpbMaskEmitter<A, B, C, D>,
22917    {
22918        <Self as VpcmpbMaskEmitter<A, B, C, D>>::vpcmpb_mask(self, op0, op1, op2, op3);
22919    }
22920    /// `VPCMPUB`.
22921    ///
22922    /// Supported operand variants:
22923    ///
22924    /// ```text
22925    /// +---+---------------------+
22926    /// | # | Operands            |
22927    /// +---+---------------------+
22928    /// | 1 | KReg, Xmm, Mem, Imm |
22929    /// | 2 | KReg, Xmm, Xmm, Imm |
22930    /// | 3 | KReg, Ymm, Mem, Imm |
22931    /// | 4 | KReg, Ymm, Ymm, Imm |
22932    /// | 5 | KReg, Zmm, Mem, Imm |
22933    /// | 6 | KReg, Zmm, Zmm, Imm |
22934    /// +---+---------------------+
22935    /// ```
22936    #[inline]
22937    pub fn vpcmpub<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
22938    where
22939        Assembler<'a>: VpcmpubEmitter<A, B, C, D>,
22940    {
22941        <Self as VpcmpubEmitter<A, B, C, D>>::vpcmpub(self, op0, op1, op2, op3);
22942    }
22943    /// `VPCMPUB_MASK`.
22944    ///
22945    /// Supported operand variants:
22946    ///
22947    /// ```text
22948    /// +---+---------------------+
22949    /// | # | Operands            |
22950    /// +---+---------------------+
22951    /// | 1 | KReg, Xmm, Mem, Imm |
22952    /// | 2 | KReg, Xmm, Xmm, Imm |
22953    /// | 3 | KReg, Ymm, Mem, Imm |
22954    /// | 4 | KReg, Ymm, Ymm, Imm |
22955    /// | 5 | KReg, Zmm, Mem, Imm |
22956    /// | 6 | KReg, Zmm, Zmm, Imm |
22957    /// +---+---------------------+
22958    /// ```
22959    #[inline]
22960    pub fn vpcmpub_mask<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
22961    where
22962        Assembler<'a>: VpcmpubMaskEmitter<A, B, C, D>,
22963    {
22964        <Self as VpcmpubMaskEmitter<A, B, C, D>>::vpcmpub_mask(self, op0, op1, op2, op3);
22965    }
22966    /// `VPCMPUW`.
22967    ///
22968    /// Supported operand variants:
22969    ///
22970    /// ```text
22971    /// +---+---------------------+
22972    /// | # | Operands            |
22973    /// +---+---------------------+
22974    /// | 1 | KReg, Xmm, Mem, Imm |
22975    /// | 2 | KReg, Xmm, Xmm, Imm |
22976    /// | 3 | KReg, Ymm, Mem, Imm |
22977    /// | 4 | KReg, Ymm, Ymm, Imm |
22978    /// | 5 | KReg, Zmm, Mem, Imm |
22979    /// | 6 | KReg, Zmm, Zmm, Imm |
22980    /// +---+---------------------+
22981    /// ```
22982    #[inline]
22983    pub fn vpcmpuw<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
22984    where
22985        Assembler<'a>: VpcmpuwEmitter<A, B, C, D>,
22986    {
22987        <Self as VpcmpuwEmitter<A, B, C, D>>::vpcmpuw(self, op0, op1, op2, op3);
22988    }
22989    /// `VPCMPUW_MASK`.
22990    ///
22991    /// Supported operand variants:
22992    ///
22993    /// ```text
22994    /// +---+---------------------+
22995    /// | # | Operands            |
22996    /// +---+---------------------+
22997    /// | 1 | KReg, Xmm, Mem, Imm |
22998    /// | 2 | KReg, Xmm, Xmm, Imm |
22999    /// | 3 | KReg, Ymm, Mem, Imm |
23000    /// | 4 | KReg, Ymm, Ymm, Imm |
23001    /// | 5 | KReg, Zmm, Mem, Imm |
23002    /// | 6 | KReg, Zmm, Zmm, Imm |
23003    /// +---+---------------------+
23004    /// ```
23005    #[inline]
23006    pub fn vpcmpuw_mask<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
23007    where
23008        Assembler<'a>: VpcmpuwMaskEmitter<A, B, C, D>,
23009    {
23010        <Self as VpcmpuwMaskEmitter<A, B, C, D>>::vpcmpuw_mask(self, op0, op1, op2, op3);
23011    }
23012    /// `VPCMPW`.
23013    ///
23014    /// Supported operand variants:
23015    ///
23016    /// ```text
23017    /// +---+---------------------+
23018    /// | # | Operands            |
23019    /// +---+---------------------+
23020    /// | 1 | KReg, Xmm, Mem, Imm |
23021    /// | 2 | KReg, Xmm, Xmm, Imm |
23022    /// | 3 | KReg, Ymm, Mem, Imm |
23023    /// | 4 | KReg, Ymm, Ymm, Imm |
23024    /// | 5 | KReg, Zmm, Mem, Imm |
23025    /// | 6 | KReg, Zmm, Zmm, Imm |
23026    /// +---+---------------------+
23027    /// ```
23028    #[inline]
23029    pub fn vpcmpw<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
23030    where
23031        Assembler<'a>: VpcmpwEmitter<A, B, C, D>,
23032    {
23033        <Self as VpcmpwEmitter<A, B, C, D>>::vpcmpw(self, op0, op1, op2, op3);
23034    }
23035    /// `VPCMPW_MASK`.
23036    ///
23037    /// Supported operand variants:
23038    ///
23039    /// ```text
23040    /// +---+---------------------+
23041    /// | # | Operands            |
23042    /// +---+---------------------+
23043    /// | 1 | KReg, Xmm, Mem, Imm |
23044    /// | 2 | KReg, Xmm, Xmm, Imm |
23045    /// | 3 | KReg, Ymm, Mem, Imm |
23046    /// | 4 | KReg, Ymm, Ymm, Imm |
23047    /// | 5 | KReg, Zmm, Mem, Imm |
23048    /// | 6 | KReg, Zmm, Zmm, Imm |
23049    /// +---+---------------------+
23050    /// ```
23051    #[inline]
23052    pub fn vpcmpw_mask<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
23053    where
23054        Assembler<'a>: VpcmpwMaskEmitter<A, B, C, D>,
23055    {
23056        <Self as VpcmpwMaskEmitter<A, B, C, D>>::vpcmpw_mask(self, op0, op1, op2, op3);
23057    }
23058    /// `VPERMI2W`.
23059    ///
23060    /// Supported operand variants:
23061    ///
23062    /// ```text
23063    /// +---+---------------+
23064    /// | # | Operands      |
23065    /// +---+---------------+
23066    /// | 1 | Xmm, Xmm, Mem |
23067    /// | 2 | Xmm, Xmm, Xmm |
23068    /// | 3 | Ymm, Ymm, Mem |
23069    /// | 4 | Ymm, Ymm, Ymm |
23070    /// | 5 | Zmm, Zmm, Mem |
23071    /// | 6 | Zmm, Zmm, Zmm |
23072    /// +---+---------------+
23073    /// ```
23074    #[inline]
23075    pub fn vpermi2w<A, B, C>(&mut self, op0: A, op1: B, op2: C)
23076    where
23077        Assembler<'a>: Vpermi2wEmitter<A, B, C>,
23078    {
23079        <Self as Vpermi2wEmitter<A, B, C>>::vpermi2w(self, op0, op1, op2);
23080    }
23081    /// `VPERMI2W_MASK`.
23082    ///
23083    /// Supported operand variants:
23084    ///
23085    /// ```text
23086    /// +---+---------------+
23087    /// | # | Operands      |
23088    /// +---+---------------+
23089    /// | 1 | Xmm, Xmm, Mem |
23090    /// | 2 | Xmm, Xmm, Xmm |
23091    /// | 3 | Ymm, Ymm, Mem |
23092    /// | 4 | Ymm, Ymm, Ymm |
23093    /// | 5 | Zmm, Zmm, Mem |
23094    /// | 6 | Zmm, Zmm, Zmm |
23095    /// +---+---------------+
23096    /// ```
23097    #[inline]
23098    pub fn vpermi2w_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
23099    where
23100        Assembler<'a>: Vpermi2wMaskEmitter<A, B, C>,
23101    {
23102        <Self as Vpermi2wMaskEmitter<A, B, C>>::vpermi2w_mask(self, op0, op1, op2);
23103    }
23104    /// `VPERMI2W_MASKZ`.
23105    ///
23106    /// Supported operand variants:
23107    ///
23108    /// ```text
23109    /// +---+---------------+
23110    /// | # | Operands      |
23111    /// +---+---------------+
23112    /// | 1 | Xmm, Xmm, Mem |
23113    /// | 2 | Xmm, Xmm, Xmm |
23114    /// | 3 | Ymm, Ymm, Mem |
23115    /// | 4 | Ymm, Ymm, Ymm |
23116    /// | 5 | Zmm, Zmm, Mem |
23117    /// | 6 | Zmm, Zmm, Zmm |
23118    /// +---+---------------+
23119    /// ```
23120    #[inline]
23121    pub fn vpermi2w_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
23122    where
23123        Assembler<'a>: Vpermi2wMaskzEmitter<A, B, C>,
23124    {
23125        <Self as Vpermi2wMaskzEmitter<A, B, C>>::vpermi2w_maskz(self, op0, op1, op2);
23126    }
23127    /// `VPERMT2W`.
23128    ///
23129    /// Supported operand variants:
23130    ///
23131    /// ```text
23132    /// +---+---------------+
23133    /// | # | Operands      |
23134    /// +---+---------------+
23135    /// | 1 | Xmm, Xmm, Mem |
23136    /// | 2 | Xmm, Xmm, Xmm |
23137    /// | 3 | Ymm, Ymm, Mem |
23138    /// | 4 | Ymm, Ymm, Ymm |
23139    /// | 5 | Zmm, Zmm, Mem |
23140    /// | 6 | Zmm, Zmm, Zmm |
23141    /// +---+---------------+
23142    /// ```
23143    #[inline]
23144    pub fn vpermt2w<A, B, C>(&mut self, op0: A, op1: B, op2: C)
23145    where
23146        Assembler<'a>: Vpermt2wEmitter<A, B, C>,
23147    {
23148        <Self as Vpermt2wEmitter<A, B, C>>::vpermt2w(self, op0, op1, op2);
23149    }
23150    /// `VPERMT2W_MASK`.
23151    ///
23152    /// Supported operand variants:
23153    ///
23154    /// ```text
23155    /// +---+---------------+
23156    /// | # | Operands      |
23157    /// +---+---------------+
23158    /// | 1 | Xmm, Xmm, Mem |
23159    /// | 2 | Xmm, Xmm, Xmm |
23160    /// | 3 | Ymm, Ymm, Mem |
23161    /// | 4 | Ymm, Ymm, Ymm |
23162    /// | 5 | Zmm, Zmm, Mem |
23163    /// | 6 | Zmm, Zmm, Zmm |
23164    /// +---+---------------+
23165    /// ```
23166    #[inline]
23167    pub fn vpermt2w_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
23168    where
23169        Assembler<'a>: Vpermt2wMaskEmitter<A, B, C>,
23170    {
23171        <Self as Vpermt2wMaskEmitter<A, B, C>>::vpermt2w_mask(self, op0, op1, op2);
23172    }
23173    /// `VPERMT2W_MASKZ`.
23174    ///
23175    /// Supported operand variants:
23176    ///
23177    /// ```text
23178    /// +---+---------------+
23179    /// | # | Operands      |
23180    /// +---+---------------+
23181    /// | 1 | Xmm, Xmm, Mem |
23182    /// | 2 | Xmm, Xmm, Xmm |
23183    /// | 3 | Ymm, Ymm, Mem |
23184    /// | 4 | Ymm, Ymm, Ymm |
23185    /// | 5 | Zmm, Zmm, Mem |
23186    /// | 6 | Zmm, Zmm, Zmm |
23187    /// +---+---------------+
23188    /// ```
23189    #[inline]
23190    pub fn vpermt2w_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
23191    where
23192        Assembler<'a>: Vpermt2wMaskzEmitter<A, B, C>,
23193    {
23194        <Self as Vpermt2wMaskzEmitter<A, B, C>>::vpermt2w_maskz(self, op0, op1, op2);
23195    }
23196    /// `VPERMW`.
23197    ///
23198    /// Supported operand variants:
23199    ///
23200    /// ```text
23201    /// +---+---------------+
23202    /// | # | Operands      |
23203    /// +---+---------------+
23204    /// | 1 | Xmm, Xmm, Mem |
23205    /// | 2 | Xmm, Xmm, Xmm |
23206    /// | 3 | Ymm, Ymm, Mem |
23207    /// | 4 | Ymm, Ymm, Ymm |
23208    /// | 5 | Zmm, Zmm, Mem |
23209    /// | 6 | Zmm, Zmm, Zmm |
23210    /// +---+---------------+
23211    /// ```
23212    #[inline]
23213    pub fn vpermw<A, B, C>(&mut self, op0: A, op1: B, op2: C)
23214    where
23215        Assembler<'a>: VpermwEmitter<A, B, C>,
23216    {
23217        <Self as VpermwEmitter<A, B, C>>::vpermw(self, op0, op1, op2);
23218    }
23219    /// `VPERMW_MASK`.
23220    ///
23221    /// Supported operand variants:
23222    ///
23223    /// ```text
23224    /// +---+---------------+
23225    /// | # | Operands      |
23226    /// +---+---------------+
23227    /// | 1 | Xmm, Xmm, Mem |
23228    /// | 2 | Xmm, Xmm, Xmm |
23229    /// | 3 | Ymm, Ymm, Mem |
23230    /// | 4 | Ymm, Ymm, Ymm |
23231    /// | 5 | Zmm, Zmm, Mem |
23232    /// | 6 | Zmm, Zmm, Zmm |
23233    /// +---+---------------+
23234    /// ```
23235    #[inline]
23236    pub fn vpermw_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
23237    where
23238        Assembler<'a>: VpermwMaskEmitter<A, B, C>,
23239    {
23240        <Self as VpermwMaskEmitter<A, B, C>>::vpermw_mask(self, op0, op1, op2);
23241    }
23242    /// `VPERMW_MASKZ`.
23243    ///
23244    /// Supported operand variants:
23245    ///
23246    /// ```text
23247    /// +---+---------------+
23248    /// | # | Operands      |
23249    /// +---+---------------+
23250    /// | 1 | Xmm, Xmm, Mem |
23251    /// | 2 | Xmm, Xmm, Xmm |
23252    /// | 3 | Ymm, Ymm, Mem |
23253    /// | 4 | Ymm, Ymm, Ymm |
23254    /// | 5 | Zmm, Zmm, Mem |
23255    /// | 6 | Zmm, Zmm, Zmm |
23256    /// +---+---------------+
23257    /// ```
23258    #[inline]
23259    pub fn vpermw_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
23260    where
23261        Assembler<'a>: VpermwMaskzEmitter<A, B, C>,
23262    {
23263        <Self as VpermwMaskzEmitter<A, B, C>>::vpermw_maskz(self, op0, op1, op2);
23264    }
23265    /// `VPEXTRB`.
23266    ///
23267    /// Supported operand variants:
23268    ///
23269    /// ```text
23270    /// +---+---------------+
23271    /// | # | Operands      |
23272    /// +---+---------------+
23273    /// | 1 | Gpd, Xmm, Imm |
23274    /// | 2 | Mem, Xmm, Imm |
23275    /// +---+---------------+
23276    /// ```
23277    #[inline]
23278    pub fn vpextrb<A, B, C>(&mut self, op0: A, op1: B, op2: C)
23279    where
23280        Assembler<'a>: VpextrbEmitter<A, B, C>,
23281    {
23282        <Self as VpextrbEmitter<A, B, C>>::vpextrb(self, op0, op1, op2);
23283    }
23284    /// `VPEXTRW`.
23285    ///
23286    /// Supported operand variants:
23287    ///
23288    /// ```text
23289    /// +---+---------------+
23290    /// | # | Operands      |
23291    /// +---+---------------+
23292    /// | 1 | Gpd, Xmm, Imm |
23293    /// | 2 | Mem, Xmm, Imm |
23294    /// +---+---------------+
23295    /// ```
23296    #[inline]
23297    pub fn vpextrw<A, B, C>(&mut self, op0: A, op1: B, op2: C)
23298    where
23299        Assembler<'a>: VpextrwEmitter<A, B, C>,
23300    {
23301        <Self as VpextrwEmitter<A, B, C>>::vpextrw(self, op0, op1, op2);
23302    }
23303    /// `VPINSRB`.
23304    ///
23305    /// Supported operand variants:
23306    ///
23307    /// ```text
23308    /// +---+--------------------+
23309    /// | # | Operands           |
23310    /// +---+--------------------+
23311    /// | 1 | Xmm, Xmm, Gpd, Imm |
23312    /// | 2 | Xmm, Xmm, Mem, Imm |
23313    /// +---+--------------------+
23314    /// ```
23315    #[inline]
23316    pub fn vpinsrb<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
23317    where
23318        Assembler<'a>: VpinsrbEmitter<A, B, C, D>,
23319    {
23320        <Self as VpinsrbEmitter<A, B, C, D>>::vpinsrb(self, op0, op1, op2, op3);
23321    }
23322    /// `VPINSRW`.
23323    ///
23324    /// Supported operand variants:
23325    ///
23326    /// ```text
23327    /// +---+--------------------+
23328    /// | # | Operands           |
23329    /// +---+--------------------+
23330    /// | 1 | Xmm, Xmm, Gpd, Imm |
23331    /// | 2 | Xmm, Xmm, Mem, Imm |
23332    /// +---+--------------------+
23333    /// ```
23334    #[inline]
23335    pub fn vpinsrw<A, B, C, D>(&mut self, op0: A, op1: B, op2: C, op3: D)
23336    where
23337        Assembler<'a>: VpinsrwEmitter<A, B, C, D>,
23338    {
23339        <Self as VpinsrwEmitter<A, B, C, D>>::vpinsrw(self, op0, op1, op2, op3);
23340    }
23341    /// `VPMADDUBSW`.
23342    ///
23343    /// Supported operand variants:
23344    ///
23345    /// ```text
23346    /// +---+---------------+
23347    /// | # | Operands      |
23348    /// +---+---------------+
23349    /// | 1 | Xmm, Xmm, Mem |
23350    /// | 2 | Xmm, Xmm, Xmm |
23351    /// | 3 | Ymm, Ymm, Mem |
23352    /// | 4 | Ymm, Ymm, Ymm |
23353    /// | 5 | Zmm, Zmm, Mem |
23354    /// | 6 | Zmm, Zmm, Zmm |
23355    /// +---+---------------+
23356    /// ```
23357    #[inline]
23358    pub fn vpmaddubsw<A, B, C>(&mut self, op0: A, op1: B, op2: C)
23359    where
23360        Assembler<'a>: VpmaddubswEmitter<A, B, C>,
23361    {
23362        <Self as VpmaddubswEmitter<A, B, C>>::vpmaddubsw(self, op0, op1, op2);
23363    }
23364    /// `VPMADDUBSW_MASK`.
23365    ///
23366    /// Supported operand variants:
23367    ///
23368    /// ```text
23369    /// +---+---------------+
23370    /// | # | Operands      |
23371    /// +---+---------------+
23372    /// | 1 | Xmm, Xmm, Mem |
23373    /// | 2 | Xmm, Xmm, Xmm |
23374    /// | 3 | Ymm, Ymm, Mem |
23375    /// | 4 | Ymm, Ymm, Ymm |
23376    /// | 5 | Zmm, Zmm, Mem |
23377    /// | 6 | Zmm, Zmm, Zmm |
23378    /// +---+---------------+
23379    /// ```
23380    #[inline]
23381    pub fn vpmaddubsw_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
23382    where
23383        Assembler<'a>: VpmaddubswMaskEmitter<A, B, C>,
23384    {
23385        <Self as VpmaddubswMaskEmitter<A, B, C>>::vpmaddubsw_mask(self, op0, op1, op2);
23386    }
23387    /// `VPMADDUBSW_MASKZ`.
23388    ///
23389    /// Supported operand variants:
23390    ///
23391    /// ```text
23392    /// +---+---------------+
23393    /// | # | Operands      |
23394    /// +---+---------------+
23395    /// | 1 | Xmm, Xmm, Mem |
23396    /// | 2 | Xmm, Xmm, Xmm |
23397    /// | 3 | Ymm, Ymm, Mem |
23398    /// | 4 | Ymm, Ymm, Ymm |
23399    /// | 5 | Zmm, Zmm, Mem |
23400    /// | 6 | Zmm, Zmm, Zmm |
23401    /// +---+---------------+
23402    /// ```
23403    #[inline]
23404    pub fn vpmaddubsw_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
23405    where
23406        Assembler<'a>: VpmaddubswMaskzEmitter<A, B, C>,
23407    {
23408        <Self as VpmaddubswMaskzEmitter<A, B, C>>::vpmaddubsw_maskz(self, op0, op1, op2);
23409    }
23410    /// `VPMADDWD`.
23411    ///
23412    /// Supported operand variants:
23413    ///
23414    /// ```text
23415    /// +---+---------------+
23416    /// | # | Operands      |
23417    /// +---+---------------+
23418    /// | 1 | Xmm, Xmm, Mem |
23419    /// | 2 | Xmm, Xmm, Xmm |
23420    /// | 3 | Ymm, Ymm, Mem |
23421    /// | 4 | Ymm, Ymm, Ymm |
23422    /// | 5 | Zmm, Zmm, Mem |
23423    /// | 6 | Zmm, Zmm, Zmm |
23424    /// +---+---------------+
23425    /// ```
23426    #[inline]
23427    pub fn vpmaddwd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
23428    where
23429        Assembler<'a>: VpmaddwdEmitter<A, B, C>,
23430    {
23431        <Self as VpmaddwdEmitter<A, B, C>>::vpmaddwd(self, op0, op1, op2);
23432    }
23433    /// `VPMADDWD_MASK`.
23434    ///
23435    /// Supported operand variants:
23436    ///
23437    /// ```text
23438    /// +---+---------------+
23439    /// | # | Operands      |
23440    /// +---+---------------+
23441    /// | 1 | Xmm, Xmm, Mem |
23442    /// | 2 | Xmm, Xmm, Xmm |
23443    /// | 3 | Ymm, Ymm, Mem |
23444    /// | 4 | Ymm, Ymm, Ymm |
23445    /// | 5 | Zmm, Zmm, Mem |
23446    /// | 6 | Zmm, Zmm, Zmm |
23447    /// +---+---------------+
23448    /// ```
23449    #[inline]
23450    pub fn vpmaddwd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
23451    where
23452        Assembler<'a>: VpmaddwdMaskEmitter<A, B, C>,
23453    {
23454        <Self as VpmaddwdMaskEmitter<A, B, C>>::vpmaddwd_mask(self, op0, op1, op2);
23455    }
23456    /// `VPMADDWD_MASKZ`.
23457    ///
23458    /// Supported operand variants:
23459    ///
23460    /// ```text
23461    /// +---+---------------+
23462    /// | # | Operands      |
23463    /// +---+---------------+
23464    /// | 1 | Xmm, Xmm, Mem |
23465    /// | 2 | Xmm, Xmm, Xmm |
23466    /// | 3 | Ymm, Ymm, Mem |
23467    /// | 4 | Ymm, Ymm, Ymm |
23468    /// | 5 | Zmm, Zmm, Mem |
23469    /// | 6 | Zmm, Zmm, Zmm |
23470    /// +---+---------------+
23471    /// ```
23472    #[inline]
23473    pub fn vpmaddwd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
23474    where
23475        Assembler<'a>: VpmaddwdMaskzEmitter<A, B, C>,
23476    {
23477        <Self as VpmaddwdMaskzEmitter<A, B, C>>::vpmaddwd_maskz(self, op0, op1, op2);
23478    }
23479    /// `VPMAXSB`.
23480    ///
23481    /// Supported operand variants:
23482    ///
23483    /// ```text
23484    /// +---+---------------+
23485    /// | # | Operands      |
23486    /// +---+---------------+
23487    /// | 1 | Xmm, Xmm, Mem |
23488    /// | 2 | Xmm, Xmm, Xmm |
23489    /// | 3 | Ymm, Ymm, Mem |
23490    /// | 4 | Ymm, Ymm, Ymm |
23491    /// | 5 | Zmm, Zmm, Mem |
23492    /// | 6 | Zmm, Zmm, Zmm |
23493    /// +---+---------------+
23494    /// ```
23495    #[inline]
23496    pub fn vpmaxsb<A, B, C>(&mut self, op0: A, op1: B, op2: C)
23497    where
23498        Assembler<'a>: VpmaxsbEmitter<A, B, C>,
23499    {
23500        <Self as VpmaxsbEmitter<A, B, C>>::vpmaxsb(self, op0, op1, op2);
23501    }
23502    /// `VPMAXSB_MASK`.
23503    ///
23504    /// Supported operand variants:
23505    ///
23506    /// ```text
23507    /// +---+---------------+
23508    /// | # | Operands      |
23509    /// +---+---------------+
23510    /// | 1 | Xmm, Xmm, Mem |
23511    /// | 2 | Xmm, Xmm, Xmm |
23512    /// | 3 | Ymm, Ymm, Mem |
23513    /// | 4 | Ymm, Ymm, Ymm |
23514    /// | 5 | Zmm, Zmm, Mem |
23515    /// | 6 | Zmm, Zmm, Zmm |
23516    /// +---+---------------+
23517    /// ```
23518    #[inline]
23519    pub fn vpmaxsb_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
23520    where
23521        Assembler<'a>: VpmaxsbMaskEmitter<A, B, C>,
23522    {
23523        <Self as VpmaxsbMaskEmitter<A, B, C>>::vpmaxsb_mask(self, op0, op1, op2);
23524    }
23525    /// `VPMAXSB_MASKZ`.
23526    ///
23527    /// Supported operand variants:
23528    ///
23529    /// ```text
23530    /// +---+---------------+
23531    /// | # | Operands      |
23532    /// +---+---------------+
23533    /// | 1 | Xmm, Xmm, Mem |
23534    /// | 2 | Xmm, Xmm, Xmm |
23535    /// | 3 | Ymm, Ymm, Mem |
23536    /// | 4 | Ymm, Ymm, Ymm |
23537    /// | 5 | Zmm, Zmm, Mem |
23538    /// | 6 | Zmm, Zmm, Zmm |
23539    /// +---+---------------+
23540    /// ```
23541    #[inline]
23542    pub fn vpmaxsb_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
23543    where
23544        Assembler<'a>: VpmaxsbMaskzEmitter<A, B, C>,
23545    {
23546        <Self as VpmaxsbMaskzEmitter<A, B, C>>::vpmaxsb_maskz(self, op0, op1, op2);
23547    }
23548    /// `VPMAXSW`.
23549    ///
23550    /// Supported operand variants:
23551    ///
23552    /// ```text
23553    /// +---+---------------+
23554    /// | # | Operands      |
23555    /// +---+---------------+
23556    /// | 1 | Xmm, Xmm, Mem |
23557    /// | 2 | Xmm, Xmm, Xmm |
23558    /// | 3 | Ymm, Ymm, Mem |
23559    /// | 4 | Ymm, Ymm, Ymm |
23560    /// | 5 | Zmm, Zmm, Mem |
23561    /// | 6 | Zmm, Zmm, Zmm |
23562    /// +---+---------------+
23563    /// ```
23564    #[inline]
23565    pub fn vpmaxsw<A, B, C>(&mut self, op0: A, op1: B, op2: C)
23566    where
23567        Assembler<'a>: VpmaxswEmitter<A, B, C>,
23568    {
23569        <Self as VpmaxswEmitter<A, B, C>>::vpmaxsw(self, op0, op1, op2);
23570    }
23571    /// `VPMAXSW_MASK`.
23572    ///
23573    /// Supported operand variants:
23574    ///
23575    /// ```text
23576    /// +---+---------------+
23577    /// | # | Operands      |
23578    /// +---+---------------+
23579    /// | 1 | Xmm, Xmm, Mem |
23580    /// | 2 | Xmm, Xmm, Xmm |
23581    /// | 3 | Ymm, Ymm, Mem |
23582    /// | 4 | Ymm, Ymm, Ymm |
23583    /// | 5 | Zmm, Zmm, Mem |
23584    /// | 6 | Zmm, Zmm, Zmm |
23585    /// +---+---------------+
23586    /// ```
23587    #[inline]
23588    pub fn vpmaxsw_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
23589    where
23590        Assembler<'a>: VpmaxswMaskEmitter<A, B, C>,
23591    {
23592        <Self as VpmaxswMaskEmitter<A, B, C>>::vpmaxsw_mask(self, op0, op1, op2);
23593    }
23594    /// `VPMAXSW_MASKZ`.
23595    ///
23596    /// Supported operand variants:
23597    ///
23598    /// ```text
23599    /// +---+---------------+
23600    /// | # | Operands      |
23601    /// +---+---------------+
23602    /// | 1 | Xmm, Xmm, Mem |
23603    /// | 2 | Xmm, Xmm, Xmm |
23604    /// | 3 | Ymm, Ymm, Mem |
23605    /// | 4 | Ymm, Ymm, Ymm |
23606    /// | 5 | Zmm, Zmm, Mem |
23607    /// | 6 | Zmm, Zmm, Zmm |
23608    /// +---+---------------+
23609    /// ```
23610    #[inline]
23611    pub fn vpmaxsw_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
23612    where
23613        Assembler<'a>: VpmaxswMaskzEmitter<A, B, C>,
23614    {
23615        <Self as VpmaxswMaskzEmitter<A, B, C>>::vpmaxsw_maskz(self, op0, op1, op2);
23616    }
23617    /// `VPMAXUB`.
23618    ///
23619    /// Supported operand variants:
23620    ///
23621    /// ```text
23622    /// +---+---------------+
23623    /// | # | Operands      |
23624    /// +---+---------------+
23625    /// | 1 | Xmm, Xmm, Mem |
23626    /// | 2 | Xmm, Xmm, Xmm |
23627    /// | 3 | Ymm, Ymm, Mem |
23628    /// | 4 | Ymm, Ymm, Ymm |
23629    /// | 5 | Zmm, Zmm, Mem |
23630    /// | 6 | Zmm, Zmm, Zmm |
23631    /// +---+---------------+
23632    /// ```
23633    #[inline]
23634    pub fn vpmaxub<A, B, C>(&mut self, op0: A, op1: B, op2: C)
23635    where
23636        Assembler<'a>: VpmaxubEmitter<A, B, C>,
23637    {
23638        <Self as VpmaxubEmitter<A, B, C>>::vpmaxub(self, op0, op1, op2);
23639    }
23640    /// `VPMAXUB_MASK`.
23641    ///
23642    /// Supported operand variants:
23643    ///
23644    /// ```text
23645    /// +---+---------------+
23646    /// | # | Operands      |
23647    /// +---+---------------+
23648    /// | 1 | Xmm, Xmm, Mem |
23649    /// | 2 | Xmm, Xmm, Xmm |
23650    /// | 3 | Ymm, Ymm, Mem |
23651    /// | 4 | Ymm, Ymm, Ymm |
23652    /// | 5 | Zmm, Zmm, Mem |
23653    /// | 6 | Zmm, Zmm, Zmm |
23654    /// +---+---------------+
23655    /// ```
23656    #[inline]
23657    pub fn vpmaxub_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
23658    where
23659        Assembler<'a>: VpmaxubMaskEmitter<A, B, C>,
23660    {
23661        <Self as VpmaxubMaskEmitter<A, B, C>>::vpmaxub_mask(self, op0, op1, op2);
23662    }
23663    /// `VPMAXUB_MASKZ`.
23664    ///
23665    /// Supported operand variants:
23666    ///
23667    /// ```text
23668    /// +---+---------------+
23669    /// | # | Operands      |
23670    /// +---+---------------+
23671    /// | 1 | Xmm, Xmm, Mem |
23672    /// | 2 | Xmm, Xmm, Xmm |
23673    /// | 3 | Ymm, Ymm, Mem |
23674    /// | 4 | Ymm, Ymm, Ymm |
23675    /// | 5 | Zmm, Zmm, Mem |
23676    /// | 6 | Zmm, Zmm, Zmm |
23677    /// +---+---------------+
23678    /// ```
23679    #[inline]
23680    pub fn vpmaxub_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
23681    where
23682        Assembler<'a>: VpmaxubMaskzEmitter<A, B, C>,
23683    {
23684        <Self as VpmaxubMaskzEmitter<A, B, C>>::vpmaxub_maskz(self, op0, op1, op2);
23685    }
23686    /// `VPMAXUW`.
23687    ///
23688    /// Supported operand variants:
23689    ///
23690    /// ```text
23691    /// +---+---------------+
23692    /// | # | Operands      |
23693    /// +---+---------------+
23694    /// | 1 | Xmm, Xmm, Mem |
23695    /// | 2 | Xmm, Xmm, Xmm |
23696    /// | 3 | Ymm, Ymm, Mem |
23697    /// | 4 | Ymm, Ymm, Ymm |
23698    /// | 5 | Zmm, Zmm, Mem |
23699    /// | 6 | Zmm, Zmm, Zmm |
23700    /// +---+---------------+
23701    /// ```
23702    #[inline]
23703    pub fn vpmaxuw<A, B, C>(&mut self, op0: A, op1: B, op2: C)
23704    where
23705        Assembler<'a>: VpmaxuwEmitter<A, B, C>,
23706    {
23707        <Self as VpmaxuwEmitter<A, B, C>>::vpmaxuw(self, op0, op1, op2);
23708    }
23709    /// `VPMAXUW_MASK`.
23710    ///
23711    /// Supported operand variants:
23712    ///
23713    /// ```text
23714    /// +---+---------------+
23715    /// | # | Operands      |
23716    /// +---+---------------+
23717    /// | 1 | Xmm, Xmm, Mem |
23718    /// | 2 | Xmm, Xmm, Xmm |
23719    /// | 3 | Ymm, Ymm, Mem |
23720    /// | 4 | Ymm, Ymm, Ymm |
23721    /// | 5 | Zmm, Zmm, Mem |
23722    /// | 6 | Zmm, Zmm, Zmm |
23723    /// +---+---------------+
23724    /// ```
23725    #[inline]
23726    pub fn vpmaxuw_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
23727    where
23728        Assembler<'a>: VpmaxuwMaskEmitter<A, B, C>,
23729    {
23730        <Self as VpmaxuwMaskEmitter<A, B, C>>::vpmaxuw_mask(self, op0, op1, op2);
23731    }
23732    /// `VPMAXUW_MASKZ`.
23733    ///
23734    /// Supported operand variants:
23735    ///
23736    /// ```text
23737    /// +---+---------------+
23738    /// | # | Operands      |
23739    /// +---+---------------+
23740    /// | 1 | Xmm, Xmm, Mem |
23741    /// | 2 | Xmm, Xmm, Xmm |
23742    /// | 3 | Ymm, Ymm, Mem |
23743    /// | 4 | Ymm, Ymm, Ymm |
23744    /// | 5 | Zmm, Zmm, Mem |
23745    /// | 6 | Zmm, Zmm, Zmm |
23746    /// +---+---------------+
23747    /// ```
23748    #[inline]
23749    pub fn vpmaxuw_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
23750    where
23751        Assembler<'a>: VpmaxuwMaskzEmitter<A, B, C>,
23752    {
23753        <Self as VpmaxuwMaskzEmitter<A, B, C>>::vpmaxuw_maskz(self, op0, op1, op2);
23754    }
23755    /// `VPMINSB`.
23756    ///
23757    /// Supported operand variants:
23758    ///
23759    /// ```text
23760    /// +---+---------------+
23761    /// | # | Operands      |
23762    /// +---+---------------+
23763    /// | 1 | Xmm, Xmm, Mem |
23764    /// | 2 | Xmm, Xmm, Xmm |
23765    /// | 3 | Ymm, Ymm, Mem |
23766    /// | 4 | Ymm, Ymm, Ymm |
23767    /// | 5 | Zmm, Zmm, Mem |
23768    /// | 6 | Zmm, Zmm, Zmm |
23769    /// +---+---------------+
23770    /// ```
23771    #[inline]
23772    pub fn vpminsb<A, B, C>(&mut self, op0: A, op1: B, op2: C)
23773    where
23774        Assembler<'a>: VpminsbEmitter<A, B, C>,
23775    {
23776        <Self as VpminsbEmitter<A, B, C>>::vpminsb(self, op0, op1, op2);
23777    }
23778    /// `VPMINSB_MASK`.
23779    ///
23780    /// Supported operand variants:
23781    ///
23782    /// ```text
23783    /// +---+---------------+
23784    /// | # | Operands      |
23785    /// +---+---------------+
23786    /// | 1 | Xmm, Xmm, Mem |
23787    /// | 2 | Xmm, Xmm, Xmm |
23788    /// | 3 | Ymm, Ymm, Mem |
23789    /// | 4 | Ymm, Ymm, Ymm |
23790    /// | 5 | Zmm, Zmm, Mem |
23791    /// | 6 | Zmm, Zmm, Zmm |
23792    /// +---+---------------+
23793    /// ```
23794    #[inline]
23795    pub fn vpminsb_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
23796    where
23797        Assembler<'a>: VpminsbMaskEmitter<A, B, C>,
23798    {
23799        <Self as VpminsbMaskEmitter<A, B, C>>::vpminsb_mask(self, op0, op1, op2);
23800    }
23801    /// `VPMINSB_MASKZ`.
23802    ///
23803    /// Supported operand variants:
23804    ///
23805    /// ```text
23806    /// +---+---------------+
23807    /// | # | Operands      |
23808    /// +---+---------------+
23809    /// | 1 | Xmm, Xmm, Mem |
23810    /// | 2 | Xmm, Xmm, Xmm |
23811    /// | 3 | Ymm, Ymm, Mem |
23812    /// | 4 | Ymm, Ymm, Ymm |
23813    /// | 5 | Zmm, Zmm, Mem |
23814    /// | 6 | Zmm, Zmm, Zmm |
23815    /// +---+---------------+
23816    /// ```
23817    #[inline]
23818    pub fn vpminsb_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
23819    where
23820        Assembler<'a>: VpminsbMaskzEmitter<A, B, C>,
23821    {
23822        <Self as VpminsbMaskzEmitter<A, B, C>>::vpminsb_maskz(self, op0, op1, op2);
23823    }
23824    /// `VPMINSW`.
23825    ///
23826    /// Supported operand variants:
23827    ///
23828    /// ```text
23829    /// +---+---------------+
23830    /// | # | Operands      |
23831    /// +---+---------------+
23832    /// | 1 | Xmm, Xmm, Mem |
23833    /// | 2 | Xmm, Xmm, Xmm |
23834    /// | 3 | Ymm, Ymm, Mem |
23835    /// | 4 | Ymm, Ymm, Ymm |
23836    /// | 5 | Zmm, Zmm, Mem |
23837    /// | 6 | Zmm, Zmm, Zmm |
23838    /// +---+---------------+
23839    /// ```
23840    #[inline]
23841    pub fn vpminsw<A, B, C>(&mut self, op0: A, op1: B, op2: C)
23842    where
23843        Assembler<'a>: VpminswEmitter<A, B, C>,
23844    {
23845        <Self as VpminswEmitter<A, B, C>>::vpminsw(self, op0, op1, op2);
23846    }
23847    /// `VPMINSW_MASK`.
23848    ///
23849    /// Supported operand variants:
23850    ///
23851    /// ```text
23852    /// +---+---------------+
23853    /// | # | Operands      |
23854    /// +---+---------------+
23855    /// | 1 | Xmm, Xmm, Mem |
23856    /// | 2 | Xmm, Xmm, Xmm |
23857    /// | 3 | Ymm, Ymm, Mem |
23858    /// | 4 | Ymm, Ymm, Ymm |
23859    /// | 5 | Zmm, Zmm, Mem |
23860    /// | 6 | Zmm, Zmm, Zmm |
23861    /// +---+---------------+
23862    /// ```
23863    #[inline]
23864    pub fn vpminsw_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
23865    where
23866        Assembler<'a>: VpminswMaskEmitter<A, B, C>,
23867    {
23868        <Self as VpminswMaskEmitter<A, B, C>>::vpminsw_mask(self, op0, op1, op2);
23869    }
23870    /// `VPMINSW_MASKZ`.
23871    ///
23872    /// Supported operand variants:
23873    ///
23874    /// ```text
23875    /// +---+---------------+
23876    /// | # | Operands      |
23877    /// +---+---------------+
23878    /// | 1 | Xmm, Xmm, Mem |
23879    /// | 2 | Xmm, Xmm, Xmm |
23880    /// | 3 | Ymm, Ymm, Mem |
23881    /// | 4 | Ymm, Ymm, Ymm |
23882    /// | 5 | Zmm, Zmm, Mem |
23883    /// | 6 | Zmm, Zmm, Zmm |
23884    /// +---+---------------+
23885    /// ```
23886    #[inline]
23887    pub fn vpminsw_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
23888    where
23889        Assembler<'a>: VpminswMaskzEmitter<A, B, C>,
23890    {
23891        <Self as VpminswMaskzEmitter<A, B, C>>::vpminsw_maskz(self, op0, op1, op2);
23892    }
23893    /// `VPMINUB`.
23894    ///
23895    /// Supported operand variants:
23896    ///
23897    /// ```text
23898    /// +---+---------------+
23899    /// | # | Operands      |
23900    /// +---+---------------+
23901    /// | 1 | Xmm, Xmm, Mem |
23902    /// | 2 | Xmm, Xmm, Xmm |
23903    /// | 3 | Ymm, Ymm, Mem |
23904    /// | 4 | Ymm, Ymm, Ymm |
23905    /// | 5 | Zmm, Zmm, Mem |
23906    /// | 6 | Zmm, Zmm, Zmm |
23907    /// +---+---------------+
23908    /// ```
23909    #[inline]
23910    pub fn vpminub<A, B, C>(&mut self, op0: A, op1: B, op2: C)
23911    where
23912        Assembler<'a>: VpminubEmitter<A, B, C>,
23913    {
23914        <Self as VpminubEmitter<A, B, C>>::vpminub(self, op0, op1, op2);
23915    }
23916    /// `VPMINUB_MASK`.
23917    ///
23918    /// Supported operand variants:
23919    ///
23920    /// ```text
23921    /// +---+---------------+
23922    /// | # | Operands      |
23923    /// +---+---------------+
23924    /// | 1 | Xmm, Xmm, Mem |
23925    /// | 2 | Xmm, Xmm, Xmm |
23926    /// | 3 | Ymm, Ymm, Mem |
23927    /// | 4 | Ymm, Ymm, Ymm |
23928    /// | 5 | Zmm, Zmm, Mem |
23929    /// | 6 | Zmm, Zmm, Zmm |
23930    /// +---+---------------+
23931    /// ```
23932    #[inline]
23933    pub fn vpminub_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
23934    where
23935        Assembler<'a>: VpminubMaskEmitter<A, B, C>,
23936    {
23937        <Self as VpminubMaskEmitter<A, B, C>>::vpminub_mask(self, op0, op1, op2);
23938    }
23939    /// `VPMINUB_MASKZ`.
23940    ///
23941    /// Supported operand variants:
23942    ///
23943    /// ```text
23944    /// +---+---------------+
23945    /// | # | Operands      |
23946    /// +---+---------------+
23947    /// | 1 | Xmm, Xmm, Mem |
23948    /// | 2 | Xmm, Xmm, Xmm |
23949    /// | 3 | Ymm, Ymm, Mem |
23950    /// | 4 | Ymm, Ymm, Ymm |
23951    /// | 5 | Zmm, Zmm, Mem |
23952    /// | 6 | Zmm, Zmm, Zmm |
23953    /// +---+---------------+
23954    /// ```
23955    #[inline]
23956    pub fn vpminub_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
23957    where
23958        Assembler<'a>: VpminubMaskzEmitter<A, B, C>,
23959    {
23960        <Self as VpminubMaskzEmitter<A, B, C>>::vpminub_maskz(self, op0, op1, op2);
23961    }
23962    /// `VPMINUW`.
23963    ///
23964    /// Supported operand variants:
23965    ///
23966    /// ```text
23967    /// +---+---------------+
23968    /// | # | Operands      |
23969    /// +---+---------------+
23970    /// | 1 | Xmm, Xmm, Mem |
23971    /// | 2 | Xmm, Xmm, Xmm |
23972    /// | 3 | Ymm, Ymm, Mem |
23973    /// | 4 | Ymm, Ymm, Ymm |
23974    /// | 5 | Zmm, Zmm, Mem |
23975    /// | 6 | Zmm, Zmm, Zmm |
23976    /// +---+---------------+
23977    /// ```
23978    #[inline]
23979    pub fn vpminuw<A, B, C>(&mut self, op0: A, op1: B, op2: C)
23980    where
23981        Assembler<'a>: VpminuwEmitter<A, B, C>,
23982    {
23983        <Self as VpminuwEmitter<A, B, C>>::vpminuw(self, op0, op1, op2);
23984    }
23985    /// `VPMINUW_MASK`.
23986    ///
23987    /// Supported operand variants:
23988    ///
23989    /// ```text
23990    /// +---+---------------+
23991    /// | # | Operands      |
23992    /// +---+---------------+
23993    /// | 1 | Xmm, Xmm, Mem |
23994    /// | 2 | Xmm, Xmm, Xmm |
23995    /// | 3 | Ymm, Ymm, Mem |
23996    /// | 4 | Ymm, Ymm, Ymm |
23997    /// | 5 | Zmm, Zmm, Mem |
23998    /// | 6 | Zmm, Zmm, Zmm |
23999    /// +---+---------------+
24000    /// ```
24001    #[inline]
24002    pub fn vpminuw_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
24003    where
24004        Assembler<'a>: VpminuwMaskEmitter<A, B, C>,
24005    {
24006        <Self as VpminuwMaskEmitter<A, B, C>>::vpminuw_mask(self, op0, op1, op2);
24007    }
24008    /// `VPMINUW_MASKZ`.
24009    ///
24010    /// Supported operand variants:
24011    ///
24012    /// ```text
24013    /// +---+---------------+
24014    /// | # | Operands      |
24015    /// +---+---------------+
24016    /// | 1 | Xmm, Xmm, Mem |
24017    /// | 2 | Xmm, Xmm, Xmm |
24018    /// | 3 | Ymm, Ymm, Mem |
24019    /// | 4 | Ymm, Ymm, Ymm |
24020    /// | 5 | Zmm, Zmm, Mem |
24021    /// | 6 | Zmm, Zmm, Zmm |
24022    /// +---+---------------+
24023    /// ```
24024    #[inline]
24025    pub fn vpminuw_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
24026    where
24027        Assembler<'a>: VpminuwMaskzEmitter<A, B, C>,
24028    {
24029        <Self as VpminuwMaskzEmitter<A, B, C>>::vpminuw_maskz(self, op0, op1, op2);
24030    }
24031    /// `VPMOVB2M`.
24032    ///
24033    /// Supported operand variants:
24034    ///
24035    /// ```text
24036    /// +---+-----------+
24037    /// | # | Operands  |
24038    /// +---+-----------+
24039    /// | 1 | KReg, Xmm |
24040    /// | 2 | KReg, Ymm |
24041    /// | 3 | KReg, Zmm |
24042    /// +---+-----------+
24043    /// ```
24044    #[inline]
24045    pub fn vpmovb2m<A, B>(&mut self, op0: A, op1: B)
24046    where
24047        Assembler<'a>: Vpmovb2mEmitter<A, B>,
24048    {
24049        <Self as Vpmovb2mEmitter<A, B>>::vpmovb2m(self, op0, op1);
24050    }
24051    /// `VPMOVM2B`.
24052    ///
24053    /// Supported operand variants:
24054    ///
24055    /// ```text
24056    /// +---+-----------+
24057    /// | # | Operands  |
24058    /// +---+-----------+
24059    /// | 1 | Xmm, KReg |
24060    /// | 2 | Ymm, KReg |
24061    /// | 3 | Zmm, KReg |
24062    /// +---+-----------+
24063    /// ```
24064    #[inline]
24065    pub fn vpmovm2b<A, B>(&mut self, op0: A, op1: B)
24066    where
24067        Assembler<'a>: Vpmovm2bEmitter<A, B>,
24068    {
24069        <Self as Vpmovm2bEmitter<A, B>>::vpmovm2b(self, op0, op1);
24070    }
24071    /// `VPMOVM2W`.
24072    ///
24073    /// Supported operand variants:
24074    ///
24075    /// ```text
24076    /// +---+-----------+
24077    /// | # | Operands  |
24078    /// +---+-----------+
24079    /// | 1 | Xmm, KReg |
24080    /// | 2 | Ymm, KReg |
24081    /// | 3 | Zmm, KReg |
24082    /// +---+-----------+
24083    /// ```
24084    #[inline]
24085    pub fn vpmovm2w<A, B>(&mut self, op0: A, op1: B)
24086    where
24087        Assembler<'a>: Vpmovm2wEmitter<A, B>,
24088    {
24089        <Self as Vpmovm2wEmitter<A, B>>::vpmovm2w(self, op0, op1);
24090    }
24091    /// `VPMOVSWB`.
24092    ///
24093    /// Supported operand variants:
24094    ///
24095    /// ```text
24096    /// +---+----------+
24097    /// | # | Operands |
24098    /// +---+----------+
24099    /// | 1 | Mem, Xmm |
24100    /// | 2 | Mem, Ymm |
24101    /// | 3 | Mem, Zmm |
24102    /// | 4 | Xmm, Xmm |
24103    /// | 5 | Xmm, Ymm |
24104    /// | 6 | Ymm, Zmm |
24105    /// +---+----------+
24106    /// ```
24107    #[inline]
24108    pub fn vpmovswb<A, B>(&mut self, op0: A, op1: B)
24109    where
24110        Assembler<'a>: VpmovswbEmitter<A, B>,
24111    {
24112        <Self as VpmovswbEmitter<A, B>>::vpmovswb(self, op0, op1);
24113    }
24114    /// `VPMOVSWB_MASK`.
24115    ///
24116    /// Supported operand variants:
24117    ///
24118    /// ```text
24119    /// +---+----------+
24120    /// | # | Operands |
24121    /// +---+----------+
24122    /// | 1 | Mem, Xmm |
24123    /// | 2 | Mem, Ymm |
24124    /// | 3 | Mem, Zmm |
24125    /// | 4 | Xmm, Xmm |
24126    /// | 5 | Xmm, Ymm |
24127    /// | 6 | Ymm, Zmm |
24128    /// +---+----------+
24129    /// ```
24130    #[inline]
24131    pub fn vpmovswb_mask<A, B>(&mut self, op0: A, op1: B)
24132    where
24133        Assembler<'a>: VpmovswbMaskEmitter<A, B>,
24134    {
24135        <Self as VpmovswbMaskEmitter<A, B>>::vpmovswb_mask(self, op0, op1);
24136    }
24137    /// `VPMOVSWB_MASKZ`.
24138    ///
24139    /// Supported operand variants:
24140    ///
24141    /// ```text
24142    /// +---+----------+
24143    /// | # | Operands |
24144    /// +---+----------+
24145    /// | 1 | Xmm, Xmm |
24146    /// | 2 | Xmm, Ymm |
24147    /// | 3 | Ymm, Zmm |
24148    /// +---+----------+
24149    /// ```
24150    #[inline]
24151    pub fn vpmovswb_maskz<A, B>(&mut self, op0: A, op1: B)
24152    where
24153        Assembler<'a>: VpmovswbMaskzEmitter<A, B>,
24154    {
24155        <Self as VpmovswbMaskzEmitter<A, B>>::vpmovswb_maskz(self, op0, op1);
24156    }
24157    /// `VPMOVUSWB`.
24158    ///
24159    /// Supported operand variants:
24160    ///
24161    /// ```text
24162    /// +---+----------+
24163    /// | # | Operands |
24164    /// +---+----------+
24165    /// | 1 | Mem, Xmm |
24166    /// | 2 | Mem, Ymm |
24167    /// | 3 | Mem, Zmm |
24168    /// | 4 | Xmm, Xmm |
24169    /// | 5 | Xmm, Ymm |
24170    /// | 6 | Ymm, Zmm |
24171    /// +---+----------+
24172    /// ```
24173    #[inline]
24174    pub fn vpmovuswb<A, B>(&mut self, op0: A, op1: B)
24175    where
24176        Assembler<'a>: VpmovuswbEmitter<A, B>,
24177    {
24178        <Self as VpmovuswbEmitter<A, B>>::vpmovuswb(self, op0, op1);
24179    }
24180    /// `VPMOVUSWB_MASK`.
24181    ///
24182    /// Supported operand variants:
24183    ///
24184    /// ```text
24185    /// +---+----------+
24186    /// | # | Operands |
24187    /// +---+----------+
24188    /// | 1 | Mem, Xmm |
24189    /// | 2 | Mem, Ymm |
24190    /// | 3 | Mem, Zmm |
24191    /// | 4 | Xmm, Xmm |
24192    /// | 5 | Xmm, Ymm |
24193    /// | 6 | Ymm, Zmm |
24194    /// +---+----------+
24195    /// ```
24196    #[inline]
24197    pub fn vpmovuswb_mask<A, B>(&mut self, op0: A, op1: B)
24198    where
24199        Assembler<'a>: VpmovuswbMaskEmitter<A, B>,
24200    {
24201        <Self as VpmovuswbMaskEmitter<A, B>>::vpmovuswb_mask(self, op0, op1);
24202    }
24203    /// `VPMOVUSWB_MASKZ`.
24204    ///
24205    /// Supported operand variants:
24206    ///
24207    /// ```text
24208    /// +---+----------+
24209    /// | # | Operands |
24210    /// +---+----------+
24211    /// | 1 | Xmm, Xmm |
24212    /// | 2 | Xmm, Ymm |
24213    /// | 3 | Ymm, Zmm |
24214    /// +---+----------+
24215    /// ```
24216    #[inline]
24217    pub fn vpmovuswb_maskz<A, B>(&mut self, op0: A, op1: B)
24218    where
24219        Assembler<'a>: VpmovuswbMaskzEmitter<A, B>,
24220    {
24221        <Self as VpmovuswbMaskzEmitter<A, B>>::vpmovuswb_maskz(self, op0, op1);
24222    }
24223    /// `VPMOVW2M`.
24224    ///
24225    /// Supported operand variants:
24226    ///
24227    /// ```text
24228    /// +---+-----------+
24229    /// | # | Operands  |
24230    /// +---+-----------+
24231    /// | 1 | KReg, Xmm |
24232    /// | 2 | KReg, Ymm |
24233    /// | 3 | KReg, Zmm |
24234    /// +---+-----------+
24235    /// ```
24236    #[inline]
24237    pub fn vpmovw2m<A, B>(&mut self, op0: A, op1: B)
24238    where
24239        Assembler<'a>: Vpmovw2mEmitter<A, B>,
24240    {
24241        <Self as Vpmovw2mEmitter<A, B>>::vpmovw2m(self, op0, op1);
24242    }
24243    /// `VPMOVWB`.
24244    ///
24245    /// Supported operand variants:
24246    ///
24247    /// ```text
24248    /// +---+----------+
24249    /// | # | Operands |
24250    /// +---+----------+
24251    /// | 1 | Mem, Xmm |
24252    /// | 2 | Mem, Ymm |
24253    /// | 3 | Mem, Zmm |
24254    /// | 4 | Xmm, Xmm |
24255    /// | 5 | Xmm, Ymm |
24256    /// | 6 | Ymm, Zmm |
24257    /// +---+----------+
24258    /// ```
24259    #[inline]
24260    pub fn vpmovwb<A, B>(&mut self, op0: A, op1: B)
24261    where
24262        Assembler<'a>: VpmovwbEmitter<A, B>,
24263    {
24264        <Self as VpmovwbEmitter<A, B>>::vpmovwb(self, op0, op1);
24265    }
24266    /// `VPMOVWB_MASK`.
24267    ///
24268    /// Supported operand variants:
24269    ///
24270    /// ```text
24271    /// +---+----------+
24272    /// | # | Operands |
24273    /// +---+----------+
24274    /// | 1 | Mem, Xmm |
24275    /// | 2 | Mem, Ymm |
24276    /// | 3 | Mem, Zmm |
24277    /// | 4 | Xmm, Xmm |
24278    /// | 5 | Xmm, Ymm |
24279    /// | 6 | Ymm, Zmm |
24280    /// +---+----------+
24281    /// ```
24282    #[inline]
24283    pub fn vpmovwb_mask<A, B>(&mut self, op0: A, op1: B)
24284    where
24285        Assembler<'a>: VpmovwbMaskEmitter<A, B>,
24286    {
24287        <Self as VpmovwbMaskEmitter<A, B>>::vpmovwb_mask(self, op0, op1);
24288    }
24289    /// `VPMOVWB_MASKZ`.
24290    ///
24291    /// Supported operand variants:
24292    ///
24293    /// ```text
24294    /// +---+----------+
24295    /// | # | Operands |
24296    /// +---+----------+
24297    /// | 1 | Xmm, Xmm |
24298    /// | 2 | Xmm, Ymm |
24299    /// | 3 | Ymm, Zmm |
24300    /// +---+----------+
24301    /// ```
24302    #[inline]
24303    pub fn vpmovwb_maskz<A, B>(&mut self, op0: A, op1: B)
24304    where
24305        Assembler<'a>: VpmovwbMaskzEmitter<A, B>,
24306    {
24307        <Self as VpmovwbMaskzEmitter<A, B>>::vpmovwb_maskz(self, op0, op1);
24308    }
24309    /// `VPMULHRSW`.
24310    ///
24311    /// Supported operand variants:
24312    ///
24313    /// ```text
24314    /// +---+---------------+
24315    /// | # | Operands      |
24316    /// +---+---------------+
24317    /// | 1 | Xmm, Xmm, Mem |
24318    /// | 2 | Xmm, Xmm, Xmm |
24319    /// | 3 | Ymm, Ymm, Mem |
24320    /// | 4 | Ymm, Ymm, Ymm |
24321    /// | 5 | Zmm, Zmm, Mem |
24322    /// | 6 | Zmm, Zmm, Zmm |
24323    /// +---+---------------+
24324    /// ```
24325    #[inline]
24326    pub fn vpmulhrsw<A, B, C>(&mut self, op0: A, op1: B, op2: C)
24327    where
24328        Assembler<'a>: VpmulhrswEmitter<A, B, C>,
24329    {
24330        <Self as VpmulhrswEmitter<A, B, C>>::vpmulhrsw(self, op0, op1, op2);
24331    }
24332    /// `VPMULHRSW_MASK`.
24333    ///
24334    /// Supported operand variants:
24335    ///
24336    /// ```text
24337    /// +---+---------------+
24338    /// | # | Operands      |
24339    /// +---+---------------+
24340    /// | 1 | Xmm, Xmm, Mem |
24341    /// | 2 | Xmm, Xmm, Xmm |
24342    /// | 3 | Ymm, Ymm, Mem |
24343    /// | 4 | Ymm, Ymm, Ymm |
24344    /// | 5 | Zmm, Zmm, Mem |
24345    /// | 6 | Zmm, Zmm, Zmm |
24346    /// +---+---------------+
24347    /// ```
24348    #[inline]
24349    pub fn vpmulhrsw_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
24350    where
24351        Assembler<'a>: VpmulhrswMaskEmitter<A, B, C>,
24352    {
24353        <Self as VpmulhrswMaskEmitter<A, B, C>>::vpmulhrsw_mask(self, op0, op1, op2);
24354    }
24355    /// `VPMULHRSW_MASKZ`.
24356    ///
24357    /// Supported operand variants:
24358    ///
24359    /// ```text
24360    /// +---+---------------+
24361    /// | # | Operands      |
24362    /// +---+---------------+
24363    /// | 1 | Xmm, Xmm, Mem |
24364    /// | 2 | Xmm, Xmm, Xmm |
24365    /// | 3 | Ymm, Ymm, Mem |
24366    /// | 4 | Ymm, Ymm, Ymm |
24367    /// | 5 | Zmm, Zmm, Mem |
24368    /// | 6 | Zmm, Zmm, Zmm |
24369    /// +---+---------------+
24370    /// ```
24371    #[inline]
24372    pub fn vpmulhrsw_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
24373    where
24374        Assembler<'a>: VpmulhrswMaskzEmitter<A, B, C>,
24375    {
24376        <Self as VpmulhrswMaskzEmitter<A, B, C>>::vpmulhrsw_maskz(self, op0, op1, op2);
24377    }
24378    /// `VPMULHUW`.
24379    ///
24380    /// Supported operand variants:
24381    ///
24382    /// ```text
24383    /// +---+---------------+
24384    /// | # | Operands      |
24385    /// +---+---------------+
24386    /// | 1 | Xmm, Xmm, Mem |
24387    /// | 2 | Xmm, Xmm, Xmm |
24388    /// | 3 | Ymm, Ymm, Mem |
24389    /// | 4 | Ymm, Ymm, Ymm |
24390    /// | 5 | Zmm, Zmm, Mem |
24391    /// | 6 | Zmm, Zmm, Zmm |
24392    /// +---+---------------+
24393    /// ```
24394    #[inline]
24395    pub fn vpmulhuw<A, B, C>(&mut self, op0: A, op1: B, op2: C)
24396    where
24397        Assembler<'a>: VpmulhuwEmitter<A, B, C>,
24398    {
24399        <Self as VpmulhuwEmitter<A, B, C>>::vpmulhuw(self, op0, op1, op2);
24400    }
24401    /// `VPMULHUW_MASK`.
24402    ///
24403    /// Supported operand variants:
24404    ///
24405    /// ```text
24406    /// +---+---------------+
24407    /// | # | Operands      |
24408    /// +---+---------------+
24409    /// | 1 | Xmm, Xmm, Mem |
24410    /// | 2 | Xmm, Xmm, Xmm |
24411    /// | 3 | Ymm, Ymm, Mem |
24412    /// | 4 | Ymm, Ymm, Ymm |
24413    /// | 5 | Zmm, Zmm, Mem |
24414    /// | 6 | Zmm, Zmm, Zmm |
24415    /// +---+---------------+
24416    /// ```
24417    #[inline]
24418    pub fn vpmulhuw_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
24419    where
24420        Assembler<'a>: VpmulhuwMaskEmitter<A, B, C>,
24421    {
24422        <Self as VpmulhuwMaskEmitter<A, B, C>>::vpmulhuw_mask(self, op0, op1, op2);
24423    }
24424    /// `VPMULHUW_MASKZ`.
24425    ///
24426    /// Supported operand variants:
24427    ///
24428    /// ```text
24429    /// +---+---------------+
24430    /// | # | Operands      |
24431    /// +---+---------------+
24432    /// | 1 | Xmm, Xmm, Mem |
24433    /// | 2 | Xmm, Xmm, Xmm |
24434    /// | 3 | Ymm, Ymm, Mem |
24435    /// | 4 | Ymm, Ymm, Ymm |
24436    /// | 5 | Zmm, Zmm, Mem |
24437    /// | 6 | Zmm, Zmm, Zmm |
24438    /// +---+---------------+
24439    /// ```
24440    #[inline]
24441    pub fn vpmulhuw_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
24442    where
24443        Assembler<'a>: VpmulhuwMaskzEmitter<A, B, C>,
24444    {
24445        <Self as VpmulhuwMaskzEmitter<A, B, C>>::vpmulhuw_maskz(self, op0, op1, op2);
24446    }
24447    /// `VPMULHW`.
24448    ///
24449    /// Supported operand variants:
24450    ///
24451    /// ```text
24452    /// +---+---------------+
24453    /// | # | Operands      |
24454    /// +---+---------------+
24455    /// | 1 | Xmm, Xmm, Mem |
24456    /// | 2 | Xmm, Xmm, Xmm |
24457    /// | 3 | Ymm, Ymm, Mem |
24458    /// | 4 | Ymm, Ymm, Ymm |
24459    /// | 5 | Zmm, Zmm, Mem |
24460    /// | 6 | Zmm, Zmm, Zmm |
24461    /// +---+---------------+
24462    /// ```
24463    #[inline]
24464    pub fn vpmulhw<A, B, C>(&mut self, op0: A, op1: B, op2: C)
24465    where
24466        Assembler<'a>: VpmulhwEmitter<A, B, C>,
24467    {
24468        <Self as VpmulhwEmitter<A, B, C>>::vpmulhw(self, op0, op1, op2);
24469    }
24470    /// `VPMULHW_MASK`.
24471    ///
24472    /// Supported operand variants:
24473    ///
24474    /// ```text
24475    /// +---+---------------+
24476    /// | # | Operands      |
24477    /// +---+---------------+
24478    /// | 1 | Xmm, Xmm, Mem |
24479    /// | 2 | Xmm, Xmm, Xmm |
24480    /// | 3 | Ymm, Ymm, Mem |
24481    /// | 4 | Ymm, Ymm, Ymm |
24482    /// | 5 | Zmm, Zmm, Mem |
24483    /// | 6 | Zmm, Zmm, Zmm |
24484    /// +---+---------------+
24485    /// ```
24486    #[inline]
24487    pub fn vpmulhw_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
24488    where
24489        Assembler<'a>: VpmulhwMaskEmitter<A, B, C>,
24490    {
24491        <Self as VpmulhwMaskEmitter<A, B, C>>::vpmulhw_mask(self, op0, op1, op2);
24492    }
24493    /// `VPMULHW_MASKZ`.
24494    ///
24495    /// Supported operand variants:
24496    ///
24497    /// ```text
24498    /// +---+---------------+
24499    /// | # | Operands      |
24500    /// +---+---------------+
24501    /// | 1 | Xmm, Xmm, Mem |
24502    /// | 2 | Xmm, Xmm, Xmm |
24503    /// | 3 | Ymm, Ymm, Mem |
24504    /// | 4 | Ymm, Ymm, Ymm |
24505    /// | 5 | Zmm, Zmm, Mem |
24506    /// | 6 | Zmm, Zmm, Zmm |
24507    /// +---+---------------+
24508    /// ```
24509    #[inline]
24510    pub fn vpmulhw_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
24511    where
24512        Assembler<'a>: VpmulhwMaskzEmitter<A, B, C>,
24513    {
24514        <Self as VpmulhwMaskzEmitter<A, B, C>>::vpmulhw_maskz(self, op0, op1, op2);
24515    }
24516    /// `VPMULLW`.
24517    ///
24518    /// Supported operand variants:
24519    ///
24520    /// ```text
24521    /// +---+---------------+
24522    /// | # | Operands      |
24523    /// +---+---------------+
24524    /// | 1 | Xmm, Xmm, Mem |
24525    /// | 2 | Xmm, Xmm, Xmm |
24526    /// | 3 | Ymm, Ymm, Mem |
24527    /// | 4 | Ymm, Ymm, Ymm |
24528    /// | 5 | Zmm, Zmm, Mem |
24529    /// | 6 | Zmm, Zmm, Zmm |
24530    /// +---+---------------+
24531    /// ```
24532    #[inline]
24533    pub fn vpmullw<A, B, C>(&mut self, op0: A, op1: B, op2: C)
24534    where
24535        Assembler<'a>: VpmullwEmitter<A, B, C>,
24536    {
24537        <Self as VpmullwEmitter<A, B, C>>::vpmullw(self, op0, op1, op2);
24538    }
24539    /// `VPMULLW_MASK`.
24540    ///
24541    /// Supported operand variants:
24542    ///
24543    /// ```text
24544    /// +---+---------------+
24545    /// | # | Operands      |
24546    /// +---+---------------+
24547    /// | 1 | Xmm, Xmm, Mem |
24548    /// | 2 | Xmm, Xmm, Xmm |
24549    /// | 3 | Ymm, Ymm, Mem |
24550    /// | 4 | Ymm, Ymm, Ymm |
24551    /// | 5 | Zmm, Zmm, Mem |
24552    /// | 6 | Zmm, Zmm, Zmm |
24553    /// +---+---------------+
24554    /// ```
24555    #[inline]
24556    pub fn vpmullw_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
24557    where
24558        Assembler<'a>: VpmullwMaskEmitter<A, B, C>,
24559    {
24560        <Self as VpmullwMaskEmitter<A, B, C>>::vpmullw_mask(self, op0, op1, op2);
24561    }
24562    /// `VPMULLW_MASKZ`.
24563    ///
24564    /// Supported operand variants:
24565    ///
24566    /// ```text
24567    /// +---+---------------+
24568    /// | # | Operands      |
24569    /// +---+---------------+
24570    /// | 1 | Xmm, Xmm, Mem |
24571    /// | 2 | Xmm, Xmm, Xmm |
24572    /// | 3 | Ymm, Ymm, Mem |
24573    /// | 4 | Ymm, Ymm, Ymm |
24574    /// | 5 | Zmm, Zmm, Mem |
24575    /// | 6 | Zmm, Zmm, Zmm |
24576    /// +---+---------------+
24577    /// ```
24578    #[inline]
24579    pub fn vpmullw_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
24580    where
24581        Assembler<'a>: VpmullwMaskzEmitter<A, B, C>,
24582    {
24583        <Self as VpmullwMaskzEmitter<A, B, C>>::vpmullw_maskz(self, op0, op1, op2);
24584    }
24585    /// `VPSADBW`.
24586    ///
24587    /// Supported operand variants:
24588    ///
24589    /// ```text
24590    /// +---+---------------+
24591    /// | # | Operands      |
24592    /// +---+---------------+
24593    /// | 1 | Xmm, Xmm, Mem |
24594    /// | 2 | Xmm, Xmm, Xmm |
24595    /// | 3 | Ymm, Ymm, Mem |
24596    /// | 4 | Ymm, Ymm, Ymm |
24597    /// | 5 | Zmm, Zmm, Mem |
24598    /// | 6 | Zmm, Zmm, Zmm |
24599    /// +---+---------------+
24600    /// ```
24601    #[inline]
24602    pub fn vpsadbw<A, B, C>(&mut self, op0: A, op1: B, op2: C)
24603    where
24604        Assembler<'a>: VpsadbwEmitter<A, B, C>,
24605    {
24606        <Self as VpsadbwEmitter<A, B, C>>::vpsadbw(self, op0, op1, op2);
24607    }
24608    /// `VPSHUFB`.
24609    ///
24610    /// Supported operand variants:
24611    ///
24612    /// ```text
24613    /// +---+---------------+
24614    /// | # | Operands      |
24615    /// +---+---------------+
24616    /// | 1 | Xmm, Xmm, Mem |
24617    /// | 2 | Xmm, Xmm, Xmm |
24618    /// | 3 | Ymm, Ymm, Mem |
24619    /// | 4 | Ymm, Ymm, Ymm |
24620    /// | 5 | Zmm, Zmm, Mem |
24621    /// | 6 | Zmm, Zmm, Zmm |
24622    /// +---+---------------+
24623    /// ```
24624    #[inline]
24625    pub fn vpshufb<A, B, C>(&mut self, op0: A, op1: B, op2: C)
24626    where
24627        Assembler<'a>: VpshufbEmitter<A, B, C>,
24628    {
24629        <Self as VpshufbEmitter<A, B, C>>::vpshufb(self, op0, op1, op2);
24630    }
24631    /// `VPSHUFB_MASK`.
24632    ///
24633    /// Supported operand variants:
24634    ///
24635    /// ```text
24636    /// +---+---------------+
24637    /// | # | Operands      |
24638    /// +---+---------------+
24639    /// | 1 | Xmm, Xmm, Mem |
24640    /// | 2 | Xmm, Xmm, Xmm |
24641    /// | 3 | Ymm, Ymm, Mem |
24642    /// | 4 | Ymm, Ymm, Ymm |
24643    /// | 5 | Zmm, Zmm, Mem |
24644    /// | 6 | Zmm, Zmm, Zmm |
24645    /// +---+---------------+
24646    /// ```
24647    #[inline]
24648    pub fn vpshufb_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
24649    where
24650        Assembler<'a>: VpshufbMaskEmitter<A, B, C>,
24651    {
24652        <Self as VpshufbMaskEmitter<A, B, C>>::vpshufb_mask(self, op0, op1, op2);
24653    }
24654    /// `VPSHUFB_MASKZ`.
24655    ///
24656    /// Supported operand variants:
24657    ///
24658    /// ```text
24659    /// +---+---------------+
24660    /// | # | Operands      |
24661    /// +---+---------------+
24662    /// | 1 | Xmm, Xmm, Mem |
24663    /// | 2 | Xmm, Xmm, Xmm |
24664    /// | 3 | Ymm, Ymm, Mem |
24665    /// | 4 | Ymm, Ymm, Ymm |
24666    /// | 5 | Zmm, Zmm, Mem |
24667    /// | 6 | Zmm, Zmm, Zmm |
24668    /// +---+---------------+
24669    /// ```
24670    #[inline]
24671    pub fn vpshufb_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
24672    where
24673        Assembler<'a>: VpshufbMaskzEmitter<A, B, C>,
24674    {
24675        <Self as VpshufbMaskzEmitter<A, B, C>>::vpshufb_maskz(self, op0, op1, op2);
24676    }
24677    /// `VPSHUFHW`.
24678    ///
24679    /// Supported operand variants:
24680    ///
24681    /// ```text
24682    /// +---+---------------+
24683    /// | # | Operands      |
24684    /// +---+---------------+
24685    /// | 1 | Xmm, Mem, Imm |
24686    /// | 2 | Xmm, Xmm, Imm |
24687    /// | 3 | Ymm, Mem, Imm |
24688    /// | 4 | Ymm, Ymm, Imm |
24689    /// | 5 | Zmm, Mem, Imm |
24690    /// | 6 | Zmm, Zmm, Imm |
24691    /// +---+---------------+
24692    /// ```
24693    #[inline]
24694    pub fn vpshufhw<A, B, C>(&mut self, op0: A, op1: B, op2: C)
24695    where
24696        Assembler<'a>: VpshufhwEmitter<A, B, C>,
24697    {
24698        <Self as VpshufhwEmitter<A, B, C>>::vpshufhw(self, op0, op1, op2);
24699    }
24700    /// `VPSHUFHW_MASK`.
24701    ///
24702    /// Supported operand variants:
24703    ///
24704    /// ```text
24705    /// +---+---------------+
24706    /// | # | Operands      |
24707    /// +---+---------------+
24708    /// | 1 | Xmm, Mem, Imm |
24709    /// | 2 | Xmm, Xmm, Imm |
24710    /// | 3 | Ymm, Mem, Imm |
24711    /// | 4 | Ymm, Ymm, Imm |
24712    /// | 5 | Zmm, Mem, Imm |
24713    /// | 6 | Zmm, Zmm, Imm |
24714    /// +---+---------------+
24715    /// ```
24716    #[inline]
24717    pub fn vpshufhw_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
24718    where
24719        Assembler<'a>: VpshufhwMaskEmitter<A, B, C>,
24720    {
24721        <Self as VpshufhwMaskEmitter<A, B, C>>::vpshufhw_mask(self, op0, op1, op2);
24722    }
24723    /// `VPSHUFHW_MASKZ`.
24724    ///
24725    /// Supported operand variants:
24726    ///
24727    /// ```text
24728    /// +---+---------------+
24729    /// | # | Operands      |
24730    /// +---+---------------+
24731    /// | 1 | Xmm, Mem, Imm |
24732    /// | 2 | Xmm, Xmm, Imm |
24733    /// | 3 | Ymm, Mem, Imm |
24734    /// | 4 | Ymm, Ymm, Imm |
24735    /// | 5 | Zmm, Mem, Imm |
24736    /// | 6 | Zmm, Zmm, Imm |
24737    /// +---+---------------+
24738    /// ```
24739    #[inline]
24740    pub fn vpshufhw_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
24741    where
24742        Assembler<'a>: VpshufhwMaskzEmitter<A, B, C>,
24743    {
24744        <Self as VpshufhwMaskzEmitter<A, B, C>>::vpshufhw_maskz(self, op0, op1, op2);
24745    }
24746    /// `VPSHUFLW`.
24747    ///
24748    /// Supported operand variants:
24749    ///
24750    /// ```text
24751    /// +---+---------------+
24752    /// | # | Operands      |
24753    /// +---+---------------+
24754    /// | 1 | Xmm, Mem, Imm |
24755    /// | 2 | Xmm, Xmm, Imm |
24756    /// | 3 | Ymm, Mem, Imm |
24757    /// | 4 | Ymm, Ymm, Imm |
24758    /// | 5 | Zmm, Mem, Imm |
24759    /// | 6 | Zmm, Zmm, Imm |
24760    /// +---+---------------+
24761    /// ```
24762    #[inline]
24763    pub fn vpshuflw<A, B, C>(&mut self, op0: A, op1: B, op2: C)
24764    where
24765        Assembler<'a>: VpshuflwEmitter<A, B, C>,
24766    {
24767        <Self as VpshuflwEmitter<A, B, C>>::vpshuflw(self, op0, op1, op2);
24768    }
24769    /// `VPSHUFLW_MASK`.
24770    ///
24771    /// Supported operand variants:
24772    ///
24773    /// ```text
24774    /// +---+---------------+
24775    /// | # | Operands      |
24776    /// +---+---------------+
24777    /// | 1 | Xmm, Mem, Imm |
24778    /// | 2 | Xmm, Xmm, Imm |
24779    /// | 3 | Ymm, Mem, Imm |
24780    /// | 4 | Ymm, Ymm, Imm |
24781    /// | 5 | Zmm, Mem, Imm |
24782    /// | 6 | Zmm, Zmm, Imm |
24783    /// +---+---------------+
24784    /// ```
24785    #[inline]
24786    pub fn vpshuflw_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
24787    where
24788        Assembler<'a>: VpshuflwMaskEmitter<A, B, C>,
24789    {
24790        <Self as VpshuflwMaskEmitter<A, B, C>>::vpshuflw_mask(self, op0, op1, op2);
24791    }
24792    /// `VPSHUFLW_MASKZ`.
24793    ///
24794    /// Supported operand variants:
24795    ///
24796    /// ```text
24797    /// +---+---------------+
24798    /// | # | Operands      |
24799    /// +---+---------------+
24800    /// | 1 | Xmm, Mem, Imm |
24801    /// | 2 | Xmm, Xmm, Imm |
24802    /// | 3 | Ymm, Mem, Imm |
24803    /// | 4 | Ymm, Ymm, Imm |
24804    /// | 5 | Zmm, Mem, Imm |
24805    /// | 6 | Zmm, Zmm, Imm |
24806    /// +---+---------------+
24807    /// ```
24808    #[inline]
24809    pub fn vpshuflw_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
24810    where
24811        Assembler<'a>: VpshuflwMaskzEmitter<A, B, C>,
24812    {
24813        <Self as VpshuflwMaskzEmitter<A, B, C>>::vpshuflw_maskz(self, op0, op1, op2);
24814    }
24815    /// `VPSLLDQ`.
24816    ///
24817    /// Supported operand variants:
24818    ///
24819    /// ```text
24820    /// +---+---------------+
24821    /// | # | Operands      |
24822    /// +---+---------------+
24823    /// | 1 | Xmm, Mem, Imm |
24824    /// | 2 | Xmm, Xmm, Imm |
24825    /// | 3 | Ymm, Mem, Imm |
24826    /// | 4 | Ymm, Ymm, Imm |
24827    /// | 5 | Zmm, Mem, Imm |
24828    /// | 6 | Zmm, Zmm, Imm |
24829    /// +---+---------------+
24830    /// ```
24831    #[inline]
24832    pub fn vpslldq<A, B, C>(&mut self, op0: A, op1: B, op2: C)
24833    where
24834        Assembler<'a>: VpslldqEmitter<A, B, C>,
24835    {
24836        <Self as VpslldqEmitter<A, B, C>>::vpslldq(self, op0, op1, op2);
24837    }
24838    /// `VPSLLVW`.
24839    ///
24840    /// Supported operand variants:
24841    ///
24842    /// ```text
24843    /// +---+---------------+
24844    /// | # | Operands      |
24845    /// +---+---------------+
24846    /// | 1 | Xmm, Xmm, Mem |
24847    /// | 2 | Xmm, Xmm, Xmm |
24848    /// | 3 | Ymm, Ymm, Mem |
24849    /// | 4 | Ymm, Ymm, Ymm |
24850    /// | 5 | Zmm, Zmm, Mem |
24851    /// | 6 | Zmm, Zmm, Zmm |
24852    /// +---+---------------+
24853    /// ```
24854    #[inline]
24855    pub fn vpsllvw<A, B, C>(&mut self, op0: A, op1: B, op2: C)
24856    where
24857        Assembler<'a>: VpsllvwEmitter<A, B, C>,
24858    {
24859        <Self as VpsllvwEmitter<A, B, C>>::vpsllvw(self, op0, op1, op2);
24860    }
24861    /// `VPSLLVW_MASK`.
24862    ///
24863    /// Supported operand variants:
24864    ///
24865    /// ```text
24866    /// +---+---------------+
24867    /// | # | Operands      |
24868    /// +---+---------------+
24869    /// | 1 | Xmm, Xmm, Mem |
24870    /// | 2 | Xmm, Xmm, Xmm |
24871    /// | 3 | Ymm, Ymm, Mem |
24872    /// | 4 | Ymm, Ymm, Ymm |
24873    /// | 5 | Zmm, Zmm, Mem |
24874    /// | 6 | Zmm, Zmm, Zmm |
24875    /// +---+---------------+
24876    /// ```
24877    #[inline]
24878    pub fn vpsllvw_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
24879    where
24880        Assembler<'a>: VpsllvwMaskEmitter<A, B, C>,
24881    {
24882        <Self as VpsllvwMaskEmitter<A, B, C>>::vpsllvw_mask(self, op0, op1, op2);
24883    }
24884    /// `VPSLLVW_MASKZ`.
24885    ///
24886    /// Supported operand variants:
24887    ///
24888    /// ```text
24889    /// +---+---------------+
24890    /// | # | Operands      |
24891    /// +---+---------------+
24892    /// | 1 | Xmm, Xmm, Mem |
24893    /// | 2 | Xmm, Xmm, Xmm |
24894    /// | 3 | Ymm, Ymm, Mem |
24895    /// | 4 | Ymm, Ymm, Ymm |
24896    /// | 5 | Zmm, Zmm, Mem |
24897    /// | 6 | Zmm, Zmm, Zmm |
24898    /// +---+---------------+
24899    /// ```
24900    #[inline]
24901    pub fn vpsllvw_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
24902    where
24903        Assembler<'a>: VpsllvwMaskzEmitter<A, B, C>,
24904    {
24905        <Self as VpsllvwMaskzEmitter<A, B, C>>::vpsllvw_maskz(self, op0, op1, op2);
24906    }
24907    /// `VPSLLW`.
24908    ///
24909    /// Supported operand variants:
24910    ///
24911    /// ```text
24912    /// +----+---------------+
24913    /// | #  | Operands      |
24914    /// +----+---------------+
24915    /// | 1  | Xmm, Mem, Imm |
24916    /// | 2  | Xmm, Xmm, Imm |
24917    /// | 3  | Xmm, Xmm, Mem |
24918    /// | 4  | Xmm, Xmm, Xmm |
24919    /// | 5  | Ymm, Mem, Imm |
24920    /// | 6  | Ymm, Ymm, Imm |
24921    /// | 7  | Ymm, Ymm, Mem |
24922    /// | 8  | Ymm, Ymm, Xmm |
24923    /// | 9  | Zmm, Mem, Imm |
24924    /// | 10 | Zmm, Zmm, Imm |
24925    /// | 11 | Zmm, Zmm, Mem |
24926    /// | 12 | Zmm, Zmm, Xmm |
24927    /// +----+---------------+
24928    /// ```
24929    #[inline]
24930    pub fn vpsllw<A, B, C>(&mut self, op0: A, op1: B, op2: C)
24931    where
24932        Assembler<'a>: VpsllwEmitter<A, B, C>,
24933    {
24934        <Self as VpsllwEmitter<A, B, C>>::vpsllw(self, op0, op1, op2);
24935    }
24936    /// `VPSLLW_MASK`.
24937    ///
24938    /// Supported operand variants:
24939    ///
24940    /// ```text
24941    /// +----+---------------+
24942    /// | #  | Operands      |
24943    /// +----+---------------+
24944    /// | 1  | Xmm, Mem, Imm |
24945    /// | 2  | Xmm, Xmm, Imm |
24946    /// | 3  | Xmm, Xmm, Mem |
24947    /// | 4  | Xmm, Xmm, Xmm |
24948    /// | 5  | Ymm, Mem, Imm |
24949    /// | 6  | Ymm, Ymm, Imm |
24950    /// | 7  | Ymm, Ymm, Mem |
24951    /// | 8  | Ymm, Ymm, Xmm |
24952    /// | 9  | Zmm, Mem, Imm |
24953    /// | 10 | Zmm, Zmm, Imm |
24954    /// | 11 | Zmm, Zmm, Mem |
24955    /// | 12 | Zmm, Zmm, Xmm |
24956    /// +----+---------------+
24957    /// ```
24958    #[inline]
24959    pub fn vpsllw_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
24960    where
24961        Assembler<'a>: VpsllwMaskEmitter<A, B, C>,
24962    {
24963        <Self as VpsllwMaskEmitter<A, B, C>>::vpsllw_mask(self, op0, op1, op2);
24964    }
24965    /// `VPSLLW_MASKZ`.
24966    ///
24967    /// Supported operand variants:
24968    ///
24969    /// ```text
24970    /// +----+---------------+
24971    /// | #  | Operands      |
24972    /// +----+---------------+
24973    /// | 1  | Xmm, Mem, Imm |
24974    /// | 2  | Xmm, Xmm, Imm |
24975    /// | 3  | Xmm, Xmm, Mem |
24976    /// | 4  | Xmm, Xmm, Xmm |
24977    /// | 5  | Ymm, Mem, Imm |
24978    /// | 6  | Ymm, Ymm, Imm |
24979    /// | 7  | Ymm, Ymm, Mem |
24980    /// | 8  | Ymm, Ymm, Xmm |
24981    /// | 9  | Zmm, Mem, Imm |
24982    /// | 10 | Zmm, Zmm, Imm |
24983    /// | 11 | Zmm, Zmm, Mem |
24984    /// | 12 | Zmm, Zmm, Xmm |
24985    /// +----+---------------+
24986    /// ```
24987    #[inline]
24988    pub fn vpsllw_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
24989    where
24990        Assembler<'a>: VpsllwMaskzEmitter<A, B, C>,
24991    {
24992        <Self as VpsllwMaskzEmitter<A, B, C>>::vpsllw_maskz(self, op0, op1, op2);
24993    }
24994    /// `VPSRAVW`.
24995    ///
24996    /// Supported operand variants:
24997    ///
24998    /// ```text
24999    /// +---+---------------+
25000    /// | # | Operands      |
25001    /// +---+---------------+
25002    /// | 1 | Xmm, Xmm, Mem |
25003    /// | 2 | Xmm, Xmm, Xmm |
25004    /// | 3 | Ymm, Ymm, Mem |
25005    /// | 4 | Ymm, Ymm, Ymm |
25006    /// | 5 | Zmm, Zmm, Mem |
25007    /// | 6 | Zmm, Zmm, Zmm |
25008    /// +---+---------------+
25009    /// ```
25010    #[inline]
25011    pub fn vpsravw<A, B, C>(&mut self, op0: A, op1: B, op2: C)
25012    where
25013        Assembler<'a>: VpsravwEmitter<A, B, C>,
25014    {
25015        <Self as VpsravwEmitter<A, B, C>>::vpsravw(self, op0, op1, op2);
25016    }
25017    /// `VPSRAVW_MASK`.
25018    ///
25019    /// Supported operand variants:
25020    ///
25021    /// ```text
25022    /// +---+---------------+
25023    /// | # | Operands      |
25024    /// +---+---------------+
25025    /// | 1 | Xmm, Xmm, Mem |
25026    /// | 2 | Xmm, Xmm, Xmm |
25027    /// | 3 | Ymm, Ymm, Mem |
25028    /// | 4 | Ymm, Ymm, Ymm |
25029    /// | 5 | Zmm, Zmm, Mem |
25030    /// | 6 | Zmm, Zmm, Zmm |
25031    /// +---+---------------+
25032    /// ```
25033    #[inline]
25034    pub fn vpsravw_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
25035    where
25036        Assembler<'a>: VpsravwMaskEmitter<A, B, C>,
25037    {
25038        <Self as VpsravwMaskEmitter<A, B, C>>::vpsravw_mask(self, op0, op1, op2);
25039    }
25040    /// `VPSRAVW_MASKZ`.
25041    ///
25042    /// Supported operand variants:
25043    ///
25044    /// ```text
25045    /// +---+---------------+
25046    /// | # | Operands      |
25047    /// +---+---------------+
25048    /// | 1 | Xmm, Xmm, Mem |
25049    /// | 2 | Xmm, Xmm, Xmm |
25050    /// | 3 | Ymm, Ymm, Mem |
25051    /// | 4 | Ymm, Ymm, Ymm |
25052    /// | 5 | Zmm, Zmm, Mem |
25053    /// | 6 | Zmm, Zmm, Zmm |
25054    /// +---+---------------+
25055    /// ```
25056    #[inline]
25057    pub fn vpsravw_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
25058    where
25059        Assembler<'a>: VpsravwMaskzEmitter<A, B, C>,
25060    {
25061        <Self as VpsravwMaskzEmitter<A, B, C>>::vpsravw_maskz(self, op0, op1, op2);
25062    }
25063    /// `VPSRAW`.
25064    ///
25065    /// Supported operand variants:
25066    ///
25067    /// ```text
25068    /// +----+---------------+
25069    /// | #  | Operands      |
25070    /// +----+---------------+
25071    /// | 1  | Xmm, Mem, Imm |
25072    /// | 2  | Xmm, Xmm, Imm |
25073    /// | 3  | Xmm, Xmm, Mem |
25074    /// | 4  | Xmm, Xmm, Xmm |
25075    /// | 5  | Ymm, Mem, Imm |
25076    /// | 6  | Ymm, Ymm, Imm |
25077    /// | 7  | Ymm, Ymm, Mem |
25078    /// | 8  | Ymm, Ymm, Xmm |
25079    /// | 9  | Zmm, Mem, Imm |
25080    /// | 10 | Zmm, Zmm, Imm |
25081    /// | 11 | Zmm, Zmm, Mem |
25082    /// | 12 | Zmm, Zmm, Xmm |
25083    /// +----+---------------+
25084    /// ```
25085    #[inline]
25086    pub fn vpsraw<A, B, C>(&mut self, op0: A, op1: B, op2: C)
25087    where
25088        Assembler<'a>: VpsrawEmitter<A, B, C>,
25089    {
25090        <Self as VpsrawEmitter<A, B, C>>::vpsraw(self, op0, op1, op2);
25091    }
25092    /// `VPSRAW_MASK`.
25093    ///
25094    /// Supported operand variants:
25095    ///
25096    /// ```text
25097    /// +----+---------------+
25098    /// | #  | Operands      |
25099    /// +----+---------------+
25100    /// | 1  | Xmm, Mem, Imm |
25101    /// | 2  | Xmm, Xmm, Imm |
25102    /// | 3  | Xmm, Xmm, Mem |
25103    /// | 4  | Xmm, Xmm, Xmm |
25104    /// | 5  | Ymm, Mem, Imm |
25105    /// | 6  | Ymm, Ymm, Imm |
25106    /// | 7  | Ymm, Ymm, Mem |
25107    /// | 8  | Ymm, Ymm, Xmm |
25108    /// | 9  | Zmm, Mem, Imm |
25109    /// | 10 | Zmm, Zmm, Imm |
25110    /// | 11 | Zmm, Zmm, Mem |
25111    /// | 12 | Zmm, Zmm, Xmm |
25112    /// +----+---------------+
25113    /// ```
25114    #[inline]
25115    pub fn vpsraw_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
25116    where
25117        Assembler<'a>: VpsrawMaskEmitter<A, B, C>,
25118    {
25119        <Self as VpsrawMaskEmitter<A, B, C>>::vpsraw_mask(self, op0, op1, op2);
25120    }
25121    /// `VPSRAW_MASKZ`.
25122    ///
25123    /// Supported operand variants:
25124    ///
25125    /// ```text
25126    /// +----+---------------+
25127    /// | #  | Operands      |
25128    /// +----+---------------+
25129    /// | 1  | Xmm, Mem, Imm |
25130    /// | 2  | Xmm, Xmm, Imm |
25131    /// | 3  | Xmm, Xmm, Mem |
25132    /// | 4  | Xmm, Xmm, Xmm |
25133    /// | 5  | Ymm, Mem, Imm |
25134    /// | 6  | Ymm, Ymm, Imm |
25135    /// | 7  | Ymm, Ymm, Mem |
25136    /// | 8  | Ymm, Ymm, Xmm |
25137    /// | 9  | Zmm, Mem, Imm |
25138    /// | 10 | Zmm, Zmm, Imm |
25139    /// | 11 | Zmm, Zmm, Mem |
25140    /// | 12 | Zmm, Zmm, Xmm |
25141    /// +----+---------------+
25142    /// ```
25143    #[inline]
25144    pub fn vpsraw_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
25145    where
25146        Assembler<'a>: VpsrawMaskzEmitter<A, B, C>,
25147    {
25148        <Self as VpsrawMaskzEmitter<A, B, C>>::vpsraw_maskz(self, op0, op1, op2);
25149    }
25150    /// `VPSRLDQ`.
25151    ///
25152    /// Supported operand variants:
25153    ///
25154    /// ```text
25155    /// +---+---------------+
25156    /// | # | Operands      |
25157    /// +---+---------------+
25158    /// | 1 | Xmm, Mem, Imm |
25159    /// | 2 | Xmm, Xmm, Imm |
25160    /// | 3 | Ymm, Mem, Imm |
25161    /// | 4 | Ymm, Ymm, Imm |
25162    /// | 5 | Zmm, Mem, Imm |
25163    /// | 6 | Zmm, Zmm, Imm |
25164    /// +---+---------------+
25165    /// ```
25166    #[inline]
25167    pub fn vpsrldq<A, B, C>(&mut self, op0: A, op1: B, op2: C)
25168    where
25169        Assembler<'a>: VpsrldqEmitter<A, B, C>,
25170    {
25171        <Self as VpsrldqEmitter<A, B, C>>::vpsrldq(self, op0, op1, op2);
25172    }
25173    /// `VPSRLVW`.
25174    ///
25175    /// Supported operand variants:
25176    ///
25177    /// ```text
25178    /// +---+---------------+
25179    /// | # | Operands      |
25180    /// +---+---------------+
25181    /// | 1 | Xmm, Xmm, Mem |
25182    /// | 2 | Xmm, Xmm, Xmm |
25183    /// | 3 | Ymm, Ymm, Mem |
25184    /// | 4 | Ymm, Ymm, Ymm |
25185    /// | 5 | Zmm, Zmm, Mem |
25186    /// | 6 | Zmm, Zmm, Zmm |
25187    /// +---+---------------+
25188    /// ```
25189    #[inline]
25190    pub fn vpsrlvw<A, B, C>(&mut self, op0: A, op1: B, op2: C)
25191    where
25192        Assembler<'a>: VpsrlvwEmitter<A, B, C>,
25193    {
25194        <Self as VpsrlvwEmitter<A, B, C>>::vpsrlvw(self, op0, op1, op2);
25195    }
25196    /// `VPSRLVW_MASK`.
25197    ///
25198    /// Supported operand variants:
25199    ///
25200    /// ```text
25201    /// +---+---------------+
25202    /// | # | Operands      |
25203    /// +---+---------------+
25204    /// | 1 | Xmm, Xmm, Mem |
25205    /// | 2 | Xmm, Xmm, Xmm |
25206    /// | 3 | Ymm, Ymm, Mem |
25207    /// | 4 | Ymm, Ymm, Ymm |
25208    /// | 5 | Zmm, Zmm, Mem |
25209    /// | 6 | Zmm, Zmm, Zmm |
25210    /// +---+---------------+
25211    /// ```
25212    #[inline]
25213    pub fn vpsrlvw_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
25214    where
25215        Assembler<'a>: VpsrlvwMaskEmitter<A, B, C>,
25216    {
25217        <Self as VpsrlvwMaskEmitter<A, B, C>>::vpsrlvw_mask(self, op0, op1, op2);
25218    }
25219    /// `VPSRLVW_MASKZ`.
25220    ///
25221    /// Supported operand variants:
25222    ///
25223    /// ```text
25224    /// +---+---------------+
25225    /// | # | Operands      |
25226    /// +---+---------------+
25227    /// | 1 | Xmm, Xmm, Mem |
25228    /// | 2 | Xmm, Xmm, Xmm |
25229    /// | 3 | Ymm, Ymm, Mem |
25230    /// | 4 | Ymm, Ymm, Ymm |
25231    /// | 5 | Zmm, Zmm, Mem |
25232    /// | 6 | Zmm, Zmm, Zmm |
25233    /// +---+---------------+
25234    /// ```
25235    #[inline]
25236    pub fn vpsrlvw_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
25237    where
25238        Assembler<'a>: VpsrlvwMaskzEmitter<A, B, C>,
25239    {
25240        <Self as VpsrlvwMaskzEmitter<A, B, C>>::vpsrlvw_maskz(self, op0, op1, op2);
25241    }
25242    /// `VPSRLW`.
25243    ///
25244    /// Supported operand variants:
25245    ///
25246    /// ```text
25247    /// +----+---------------+
25248    /// | #  | Operands      |
25249    /// +----+---------------+
25250    /// | 1  | Xmm, Mem, Imm |
25251    /// | 2  | Xmm, Xmm, Imm |
25252    /// | 3  | Xmm, Xmm, Mem |
25253    /// | 4  | Xmm, Xmm, Xmm |
25254    /// | 5  | Ymm, Mem, Imm |
25255    /// | 6  | Ymm, Ymm, Imm |
25256    /// | 7  | Ymm, Ymm, Mem |
25257    /// | 8  | Ymm, Ymm, Xmm |
25258    /// | 9  | Zmm, Mem, Imm |
25259    /// | 10 | Zmm, Zmm, Imm |
25260    /// | 11 | Zmm, Zmm, Mem |
25261    /// | 12 | Zmm, Zmm, Xmm |
25262    /// +----+---------------+
25263    /// ```
25264    #[inline]
25265    pub fn vpsrlw<A, B, C>(&mut self, op0: A, op1: B, op2: C)
25266    where
25267        Assembler<'a>: VpsrlwEmitter<A, B, C>,
25268    {
25269        <Self as VpsrlwEmitter<A, B, C>>::vpsrlw(self, op0, op1, op2);
25270    }
25271    /// `VPSRLW_MASK`.
25272    ///
25273    /// Supported operand variants:
25274    ///
25275    /// ```text
25276    /// +----+---------------+
25277    /// | #  | Operands      |
25278    /// +----+---------------+
25279    /// | 1  | Xmm, Mem, Imm |
25280    /// | 2  | Xmm, Xmm, Imm |
25281    /// | 3  | Xmm, Xmm, Mem |
25282    /// | 4  | Xmm, Xmm, Xmm |
25283    /// | 5  | Ymm, Mem, Imm |
25284    /// | 6  | Ymm, Ymm, Imm |
25285    /// | 7  | Ymm, Ymm, Mem |
25286    /// | 8  | Ymm, Ymm, Xmm |
25287    /// | 9  | Zmm, Mem, Imm |
25288    /// | 10 | Zmm, Zmm, Imm |
25289    /// | 11 | Zmm, Zmm, Mem |
25290    /// | 12 | Zmm, Zmm, Xmm |
25291    /// +----+---------------+
25292    /// ```
25293    #[inline]
25294    pub fn vpsrlw_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
25295    where
25296        Assembler<'a>: VpsrlwMaskEmitter<A, B, C>,
25297    {
25298        <Self as VpsrlwMaskEmitter<A, B, C>>::vpsrlw_mask(self, op0, op1, op2);
25299    }
25300    /// `VPSRLW_MASKZ`.
25301    ///
25302    /// Supported operand variants:
25303    ///
25304    /// ```text
25305    /// +----+---------------+
25306    /// | #  | Operands      |
25307    /// +----+---------------+
25308    /// | 1  | Xmm, Mem, Imm |
25309    /// | 2  | Xmm, Xmm, Imm |
25310    /// | 3  | Xmm, Xmm, Mem |
25311    /// | 4  | Xmm, Xmm, Xmm |
25312    /// | 5  | Ymm, Mem, Imm |
25313    /// | 6  | Ymm, Ymm, Imm |
25314    /// | 7  | Ymm, Ymm, Mem |
25315    /// | 8  | Ymm, Ymm, Xmm |
25316    /// | 9  | Zmm, Mem, Imm |
25317    /// | 10 | Zmm, Zmm, Imm |
25318    /// | 11 | Zmm, Zmm, Mem |
25319    /// | 12 | Zmm, Zmm, Xmm |
25320    /// +----+---------------+
25321    /// ```
25322    #[inline]
25323    pub fn vpsrlw_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
25324    where
25325        Assembler<'a>: VpsrlwMaskzEmitter<A, B, C>,
25326    {
25327        <Self as VpsrlwMaskzEmitter<A, B, C>>::vpsrlw_maskz(self, op0, op1, op2);
25328    }
25329    /// `VPSUBB`.
25330    ///
25331    /// Supported operand variants:
25332    ///
25333    /// ```text
25334    /// +---+---------------+
25335    /// | # | Operands      |
25336    /// +---+---------------+
25337    /// | 1 | Xmm, Xmm, Mem |
25338    /// | 2 | Xmm, Xmm, Xmm |
25339    /// | 3 | Ymm, Ymm, Mem |
25340    /// | 4 | Ymm, Ymm, Ymm |
25341    /// | 5 | Zmm, Zmm, Mem |
25342    /// | 6 | Zmm, Zmm, Zmm |
25343    /// +---+---------------+
25344    /// ```
25345    #[inline]
25346    pub fn vpsubb<A, B, C>(&mut self, op0: A, op1: B, op2: C)
25347    where
25348        Assembler<'a>: VpsubbEmitter<A, B, C>,
25349    {
25350        <Self as VpsubbEmitter<A, B, C>>::vpsubb(self, op0, op1, op2);
25351    }
25352    /// `VPSUBB_MASK`.
25353    ///
25354    /// Supported operand variants:
25355    ///
25356    /// ```text
25357    /// +---+---------------+
25358    /// | # | Operands      |
25359    /// +---+---------------+
25360    /// | 1 | Xmm, Xmm, Mem |
25361    /// | 2 | Xmm, Xmm, Xmm |
25362    /// | 3 | Ymm, Ymm, Mem |
25363    /// | 4 | Ymm, Ymm, Ymm |
25364    /// | 5 | Zmm, Zmm, Mem |
25365    /// | 6 | Zmm, Zmm, Zmm |
25366    /// +---+---------------+
25367    /// ```
25368    #[inline]
25369    pub fn vpsubb_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
25370    where
25371        Assembler<'a>: VpsubbMaskEmitter<A, B, C>,
25372    {
25373        <Self as VpsubbMaskEmitter<A, B, C>>::vpsubb_mask(self, op0, op1, op2);
25374    }
25375    /// `VPSUBB_MASKZ`.
25376    ///
25377    /// Supported operand variants:
25378    ///
25379    /// ```text
25380    /// +---+---------------+
25381    /// | # | Operands      |
25382    /// +---+---------------+
25383    /// | 1 | Xmm, Xmm, Mem |
25384    /// | 2 | Xmm, Xmm, Xmm |
25385    /// | 3 | Ymm, Ymm, Mem |
25386    /// | 4 | Ymm, Ymm, Ymm |
25387    /// | 5 | Zmm, Zmm, Mem |
25388    /// | 6 | Zmm, Zmm, Zmm |
25389    /// +---+---------------+
25390    /// ```
25391    #[inline]
25392    pub fn vpsubb_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
25393    where
25394        Assembler<'a>: VpsubbMaskzEmitter<A, B, C>,
25395    {
25396        <Self as VpsubbMaskzEmitter<A, B, C>>::vpsubb_maskz(self, op0, op1, op2);
25397    }
25398    /// `VPSUBSB`.
25399    ///
25400    /// Supported operand variants:
25401    ///
25402    /// ```text
25403    /// +---+---------------+
25404    /// | # | Operands      |
25405    /// +---+---------------+
25406    /// | 1 | Xmm, Xmm, Mem |
25407    /// | 2 | Xmm, Xmm, Xmm |
25408    /// | 3 | Ymm, Ymm, Mem |
25409    /// | 4 | Ymm, Ymm, Ymm |
25410    /// | 5 | Zmm, Zmm, Mem |
25411    /// | 6 | Zmm, Zmm, Zmm |
25412    /// +---+---------------+
25413    /// ```
25414    #[inline]
25415    pub fn vpsubsb<A, B, C>(&mut self, op0: A, op1: B, op2: C)
25416    where
25417        Assembler<'a>: VpsubsbEmitter<A, B, C>,
25418    {
25419        <Self as VpsubsbEmitter<A, B, C>>::vpsubsb(self, op0, op1, op2);
25420    }
25421    /// `VPSUBSB_MASK`.
25422    ///
25423    /// Supported operand variants:
25424    ///
25425    /// ```text
25426    /// +---+---------------+
25427    /// | # | Operands      |
25428    /// +---+---------------+
25429    /// | 1 | Xmm, Xmm, Mem |
25430    /// | 2 | Xmm, Xmm, Xmm |
25431    /// | 3 | Ymm, Ymm, Mem |
25432    /// | 4 | Ymm, Ymm, Ymm |
25433    /// | 5 | Zmm, Zmm, Mem |
25434    /// | 6 | Zmm, Zmm, Zmm |
25435    /// +---+---------------+
25436    /// ```
25437    #[inline]
25438    pub fn vpsubsb_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
25439    where
25440        Assembler<'a>: VpsubsbMaskEmitter<A, B, C>,
25441    {
25442        <Self as VpsubsbMaskEmitter<A, B, C>>::vpsubsb_mask(self, op0, op1, op2);
25443    }
25444    /// `VPSUBSB_MASKZ`.
25445    ///
25446    /// Supported operand variants:
25447    ///
25448    /// ```text
25449    /// +---+---------------+
25450    /// | # | Operands      |
25451    /// +---+---------------+
25452    /// | 1 | Xmm, Xmm, Mem |
25453    /// | 2 | Xmm, Xmm, Xmm |
25454    /// | 3 | Ymm, Ymm, Mem |
25455    /// | 4 | Ymm, Ymm, Ymm |
25456    /// | 5 | Zmm, Zmm, Mem |
25457    /// | 6 | Zmm, Zmm, Zmm |
25458    /// +---+---------------+
25459    /// ```
25460    #[inline]
25461    pub fn vpsubsb_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
25462    where
25463        Assembler<'a>: VpsubsbMaskzEmitter<A, B, C>,
25464    {
25465        <Self as VpsubsbMaskzEmitter<A, B, C>>::vpsubsb_maskz(self, op0, op1, op2);
25466    }
25467    /// `VPSUBSW`.
25468    ///
25469    /// Supported operand variants:
25470    ///
25471    /// ```text
25472    /// +---+---------------+
25473    /// | # | Operands      |
25474    /// +---+---------------+
25475    /// | 1 | Xmm, Xmm, Mem |
25476    /// | 2 | Xmm, Xmm, Xmm |
25477    /// | 3 | Ymm, Ymm, Mem |
25478    /// | 4 | Ymm, Ymm, Ymm |
25479    /// | 5 | Zmm, Zmm, Mem |
25480    /// | 6 | Zmm, Zmm, Zmm |
25481    /// +---+---------------+
25482    /// ```
25483    #[inline]
25484    pub fn vpsubsw<A, B, C>(&mut self, op0: A, op1: B, op2: C)
25485    where
25486        Assembler<'a>: VpsubswEmitter<A, B, C>,
25487    {
25488        <Self as VpsubswEmitter<A, B, C>>::vpsubsw(self, op0, op1, op2);
25489    }
25490    /// `VPSUBSW_MASK`.
25491    ///
25492    /// Supported operand variants:
25493    ///
25494    /// ```text
25495    /// +---+---------------+
25496    /// | # | Operands      |
25497    /// +---+---------------+
25498    /// | 1 | Xmm, Xmm, Mem |
25499    /// | 2 | Xmm, Xmm, Xmm |
25500    /// | 3 | Ymm, Ymm, Mem |
25501    /// | 4 | Ymm, Ymm, Ymm |
25502    /// | 5 | Zmm, Zmm, Mem |
25503    /// | 6 | Zmm, Zmm, Zmm |
25504    /// +---+---------------+
25505    /// ```
25506    #[inline]
25507    pub fn vpsubsw_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
25508    where
25509        Assembler<'a>: VpsubswMaskEmitter<A, B, C>,
25510    {
25511        <Self as VpsubswMaskEmitter<A, B, C>>::vpsubsw_mask(self, op0, op1, op2);
25512    }
25513    /// `VPSUBSW_MASKZ`.
25514    ///
25515    /// Supported operand variants:
25516    ///
25517    /// ```text
25518    /// +---+---------------+
25519    /// | # | Operands      |
25520    /// +---+---------------+
25521    /// | 1 | Xmm, Xmm, Mem |
25522    /// | 2 | Xmm, Xmm, Xmm |
25523    /// | 3 | Ymm, Ymm, Mem |
25524    /// | 4 | Ymm, Ymm, Ymm |
25525    /// | 5 | Zmm, Zmm, Mem |
25526    /// | 6 | Zmm, Zmm, Zmm |
25527    /// +---+---------------+
25528    /// ```
25529    #[inline]
25530    pub fn vpsubsw_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
25531    where
25532        Assembler<'a>: VpsubswMaskzEmitter<A, B, C>,
25533    {
25534        <Self as VpsubswMaskzEmitter<A, B, C>>::vpsubsw_maskz(self, op0, op1, op2);
25535    }
25536    /// `VPSUBUSB`.
25537    ///
25538    /// Supported operand variants:
25539    ///
25540    /// ```text
25541    /// +---+---------------+
25542    /// | # | Operands      |
25543    /// +---+---------------+
25544    /// | 1 | Xmm, Xmm, Mem |
25545    /// | 2 | Xmm, Xmm, Xmm |
25546    /// | 3 | Ymm, Ymm, Mem |
25547    /// | 4 | Ymm, Ymm, Ymm |
25548    /// | 5 | Zmm, Zmm, Mem |
25549    /// | 6 | Zmm, Zmm, Zmm |
25550    /// +---+---------------+
25551    /// ```
25552    #[inline]
25553    pub fn vpsubusb<A, B, C>(&mut self, op0: A, op1: B, op2: C)
25554    where
25555        Assembler<'a>: VpsubusbEmitter<A, B, C>,
25556    {
25557        <Self as VpsubusbEmitter<A, B, C>>::vpsubusb(self, op0, op1, op2);
25558    }
25559    /// `VPSUBUSB_MASK`.
25560    ///
25561    /// Supported operand variants:
25562    ///
25563    /// ```text
25564    /// +---+---------------+
25565    /// | # | Operands      |
25566    /// +---+---------------+
25567    /// | 1 | Xmm, Xmm, Mem |
25568    /// | 2 | Xmm, Xmm, Xmm |
25569    /// | 3 | Ymm, Ymm, Mem |
25570    /// | 4 | Ymm, Ymm, Ymm |
25571    /// | 5 | Zmm, Zmm, Mem |
25572    /// | 6 | Zmm, Zmm, Zmm |
25573    /// +---+---------------+
25574    /// ```
25575    #[inline]
25576    pub fn vpsubusb_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
25577    where
25578        Assembler<'a>: VpsubusbMaskEmitter<A, B, C>,
25579    {
25580        <Self as VpsubusbMaskEmitter<A, B, C>>::vpsubusb_mask(self, op0, op1, op2);
25581    }
25582    /// `VPSUBUSB_MASKZ`.
25583    ///
25584    /// Supported operand variants:
25585    ///
25586    /// ```text
25587    /// +---+---------------+
25588    /// | # | Operands      |
25589    /// +---+---------------+
25590    /// | 1 | Xmm, Xmm, Mem |
25591    /// | 2 | Xmm, Xmm, Xmm |
25592    /// | 3 | Ymm, Ymm, Mem |
25593    /// | 4 | Ymm, Ymm, Ymm |
25594    /// | 5 | Zmm, Zmm, Mem |
25595    /// | 6 | Zmm, Zmm, Zmm |
25596    /// +---+---------------+
25597    /// ```
25598    #[inline]
25599    pub fn vpsubusb_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
25600    where
25601        Assembler<'a>: VpsubusbMaskzEmitter<A, B, C>,
25602    {
25603        <Self as VpsubusbMaskzEmitter<A, B, C>>::vpsubusb_maskz(self, op0, op1, op2);
25604    }
25605    /// `VPSUBUSW`.
25606    ///
25607    /// Supported operand variants:
25608    ///
25609    /// ```text
25610    /// +---+---------------+
25611    /// | # | Operands      |
25612    /// +---+---------------+
25613    /// | 1 | Xmm, Xmm, Mem |
25614    /// | 2 | Xmm, Xmm, Xmm |
25615    /// | 3 | Ymm, Ymm, Mem |
25616    /// | 4 | Ymm, Ymm, Ymm |
25617    /// | 5 | Zmm, Zmm, Mem |
25618    /// | 6 | Zmm, Zmm, Zmm |
25619    /// +---+---------------+
25620    /// ```
25621    #[inline]
25622    pub fn vpsubusw<A, B, C>(&mut self, op0: A, op1: B, op2: C)
25623    where
25624        Assembler<'a>: VpsubuswEmitter<A, B, C>,
25625    {
25626        <Self as VpsubuswEmitter<A, B, C>>::vpsubusw(self, op0, op1, op2);
25627    }
25628    /// `VPSUBUSW_MASK`.
25629    ///
25630    /// Supported operand variants:
25631    ///
25632    /// ```text
25633    /// +---+---------------+
25634    /// | # | Operands      |
25635    /// +---+---------------+
25636    /// | 1 | Xmm, Xmm, Mem |
25637    /// | 2 | Xmm, Xmm, Xmm |
25638    /// | 3 | Ymm, Ymm, Mem |
25639    /// | 4 | Ymm, Ymm, Ymm |
25640    /// | 5 | Zmm, Zmm, Mem |
25641    /// | 6 | Zmm, Zmm, Zmm |
25642    /// +---+---------------+
25643    /// ```
25644    #[inline]
25645    pub fn vpsubusw_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
25646    where
25647        Assembler<'a>: VpsubuswMaskEmitter<A, B, C>,
25648    {
25649        <Self as VpsubuswMaskEmitter<A, B, C>>::vpsubusw_mask(self, op0, op1, op2);
25650    }
25651    /// `VPSUBUSW_MASKZ`.
25652    ///
25653    /// Supported operand variants:
25654    ///
25655    /// ```text
25656    /// +---+---------------+
25657    /// | # | Operands      |
25658    /// +---+---------------+
25659    /// | 1 | Xmm, Xmm, Mem |
25660    /// | 2 | Xmm, Xmm, Xmm |
25661    /// | 3 | Ymm, Ymm, Mem |
25662    /// | 4 | Ymm, Ymm, Ymm |
25663    /// | 5 | Zmm, Zmm, Mem |
25664    /// | 6 | Zmm, Zmm, Zmm |
25665    /// +---+---------------+
25666    /// ```
25667    #[inline]
25668    pub fn vpsubusw_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
25669    where
25670        Assembler<'a>: VpsubuswMaskzEmitter<A, B, C>,
25671    {
25672        <Self as VpsubuswMaskzEmitter<A, B, C>>::vpsubusw_maskz(self, op0, op1, op2);
25673    }
25674    /// `VPSUBW`.
25675    ///
25676    /// Supported operand variants:
25677    ///
25678    /// ```text
25679    /// +---+---------------+
25680    /// | # | Operands      |
25681    /// +---+---------------+
25682    /// | 1 | Xmm, Xmm, Mem |
25683    /// | 2 | Xmm, Xmm, Xmm |
25684    /// | 3 | Ymm, Ymm, Mem |
25685    /// | 4 | Ymm, Ymm, Ymm |
25686    /// | 5 | Zmm, Zmm, Mem |
25687    /// | 6 | Zmm, Zmm, Zmm |
25688    /// +---+---------------+
25689    /// ```
25690    #[inline]
25691    pub fn vpsubw<A, B, C>(&mut self, op0: A, op1: B, op2: C)
25692    where
25693        Assembler<'a>: VpsubwEmitter<A, B, C>,
25694    {
25695        <Self as VpsubwEmitter<A, B, C>>::vpsubw(self, op0, op1, op2);
25696    }
25697    /// `VPSUBW_MASK`.
25698    ///
25699    /// Supported operand variants:
25700    ///
25701    /// ```text
25702    /// +---+---------------+
25703    /// | # | Operands      |
25704    /// +---+---------------+
25705    /// | 1 | Xmm, Xmm, Mem |
25706    /// | 2 | Xmm, Xmm, Xmm |
25707    /// | 3 | Ymm, Ymm, Mem |
25708    /// | 4 | Ymm, Ymm, Ymm |
25709    /// | 5 | Zmm, Zmm, Mem |
25710    /// | 6 | Zmm, Zmm, Zmm |
25711    /// +---+---------------+
25712    /// ```
25713    #[inline]
25714    pub fn vpsubw_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
25715    where
25716        Assembler<'a>: VpsubwMaskEmitter<A, B, C>,
25717    {
25718        <Self as VpsubwMaskEmitter<A, B, C>>::vpsubw_mask(self, op0, op1, op2);
25719    }
25720    /// `VPSUBW_MASKZ`.
25721    ///
25722    /// Supported operand variants:
25723    ///
25724    /// ```text
25725    /// +---+---------------+
25726    /// | # | Operands      |
25727    /// +---+---------------+
25728    /// | 1 | Xmm, Xmm, Mem |
25729    /// | 2 | Xmm, Xmm, Xmm |
25730    /// | 3 | Ymm, Ymm, Mem |
25731    /// | 4 | Ymm, Ymm, Ymm |
25732    /// | 5 | Zmm, Zmm, Mem |
25733    /// | 6 | Zmm, Zmm, Zmm |
25734    /// +---+---------------+
25735    /// ```
25736    #[inline]
25737    pub fn vpsubw_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
25738    where
25739        Assembler<'a>: VpsubwMaskzEmitter<A, B, C>,
25740    {
25741        <Self as VpsubwMaskzEmitter<A, B, C>>::vpsubw_maskz(self, op0, op1, op2);
25742    }
25743    /// `VPTESTMB`.
25744    ///
25745    /// Supported operand variants:
25746    ///
25747    /// ```text
25748    /// +---+----------------+
25749    /// | # | Operands       |
25750    /// +---+----------------+
25751    /// | 1 | KReg, Xmm, Mem |
25752    /// | 2 | KReg, Xmm, Xmm |
25753    /// | 3 | KReg, Ymm, Mem |
25754    /// | 4 | KReg, Ymm, Ymm |
25755    /// | 5 | KReg, Zmm, Mem |
25756    /// | 6 | KReg, Zmm, Zmm |
25757    /// +---+----------------+
25758    /// ```
25759    #[inline]
25760    pub fn vptestmb<A, B, C>(&mut self, op0: A, op1: B, op2: C)
25761    where
25762        Assembler<'a>: VptestmbEmitter<A, B, C>,
25763    {
25764        <Self as VptestmbEmitter<A, B, C>>::vptestmb(self, op0, op1, op2);
25765    }
25766    /// `VPTESTMB_MASK`.
25767    ///
25768    /// Supported operand variants:
25769    ///
25770    /// ```text
25771    /// +---+----------------+
25772    /// | # | Operands       |
25773    /// +---+----------------+
25774    /// | 1 | KReg, Xmm, Mem |
25775    /// | 2 | KReg, Xmm, Xmm |
25776    /// | 3 | KReg, Ymm, Mem |
25777    /// | 4 | KReg, Ymm, Ymm |
25778    /// | 5 | KReg, Zmm, Mem |
25779    /// | 6 | KReg, Zmm, Zmm |
25780    /// +---+----------------+
25781    /// ```
25782    #[inline]
25783    pub fn vptestmb_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
25784    where
25785        Assembler<'a>: VptestmbMaskEmitter<A, B, C>,
25786    {
25787        <Self as VptestmbMaskEmitter<A, B, C>>::vptestmb_mask(self, op0, op1, op2);
25788    }
25789    /// `VPTESTMW`.
25790    ///
25791    /// Supported operand variants:
25792    ///
25793    /// ```text
25794    /// +---+----------------+
25795    /// | # | Operands       |
25796    /// +---+----------------+
25797    /// | 1 | KReg, Xmm, Mem |
25798    /// | 2 | KReg, Xmm, Xmm |
25799    /// | 3 | KReg, Ymm, Mem |
25800    /// | 4 | KReg, Ymm, Ymm |
25801    /// | 5 | KReg, Zmm, Mem |
25802    /// | 6 | KReg, Zmm, Zmm |
25803    /// +---+----------------+
25804    /// ```
25805    #[inline]
25806    pub fn vptestmw<A, B, C>(&mut self, op0: A, op1: B, op2: C)
25807    where
25808        Assembler<'a>: VptestmwEmitter<A, B, C>,
25809    {
25810        <Self as VptestmwEmitter<A, B, C>>::vptestmw(self, op0, op1, op2);
25811    }
25812    /// `VPTESTMW_MASK`.
25813    ///
25814    /// Supported operand variants:
25815    ///
25816    /// ```text
25817    /// +---+----------------+
25818    /// | # | Operands       |
25819    /// +---+----------------+
25820    /// | 1 | KReg, Xmm, Mem |
25821    /// | 2 | KReg, Xmm, Xmm |
25822    /// | 3 | KReg, Ymm, Mem |
25823    /// | 4 | KReg, Ymm, Ymm |
25824    /// | 5 | KReg, Zmm, Mem |
25825    /// | 6 | KReg, Zmm, Zmm |
25826    /// +---+----------------+
25827    /// ```
25828    #[inline]
25829    pub fn vptestmw_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
25830    where
25831        Assembler<'a>: VptestmwMaskEmitter<A, B, C>,
25832    {
25833        <Self as VptestmwMaskEmitter<A, B, C>>::vptestmw_mask(self, op0, op1, op2);
25834    }
25835    /// `VPTESTNMB`.
25836    ///
25837    /// Supported operand variants:
25838    ///
25839    /// ```text
25840    /// +---+----------------+
25841    /// | # | Operands       |
25842    /// +---+----------------+
25843    /// | 1 | KReg, Xmm, Mem |
25844    /// | 2 | KReg, Xmm, Xmm |
25845    /// | 3 | KReg, Ymm, Mem |
25846    /// | 4 | KReg, Ymm, Ymm |
25847    /// | 5 | KReg, Zmm, Mem |
25848    /// | 6 | KReg, Zmm, Zmm |
25849    /// +---+----------------+
25850    /// ```
25851    #[inline]
25852    pub fn vptestnmb<A, B, C>(&mut self, op0: A, op1: B, op2: C)
25853    where
25854        Assembler<'a>: VptestnmbEmitter<A, B, C>,
25855    {
25856        <Self as VptestnmbEmitter<A, B, C>>::vptestnmb(self, op0, op1, op2);
25857    }
25858    /// `VPTESTNMB_MASK`.
25859    ///
25860    /// Supported operand variants:
25861    ///
25862    /// ```text
25863    /// +---+----------------+
25864    /// | # | Operands       |
25865    /// +---+----------------+
25866    /// | 1 | KReg, Xmm, Mem |
25867    /// | 2 | KReg, Xmm, Xmm |
25868    /// | 3 | KReg, Ymm, Mem |
25869    /// | 4 | KReg, Ymm, Ymm |
25870    /// | 5 | KReg, Zmm, Mem |
25871    /// | 6 | KReg, Zmm, Zmm |
25872    /// +---+----------------+
25873    /// ```
25874    #[inline]
25875    pub fn vptestnmb_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
25876    where
25877        Assembler<'a>: VptestnmbMaskEmitter<A, B, C>,
25878    {
25879        <Self as VptestnmbMaskEmitter<A, B, C>>::vptestnmb_mask(self, op0, op1, op2);
25880    }
25881    /// `VPTESTNMW`.
25882    ///
25883    /// Supported operand variants:
25884    ///
25885    /// ```text
25886    /// +---+----------------+
25887    /// | # | Operands       |
25888    /// +---+----------------+
25889    /// | 1 | KReg, Xmm, Mem |
25890    /// | 2 | KReg, Xmm, Xmm |
25891    /// | 3 | KReg, Ymm, Mem |
25892    /// | 4 | KReg, Ymm, Ymm |
25893    /// | 5 | KReg, Zmm, Mem |
25894    /// | 6 | KReg, Zmm, Zmm |
25895    /// +---+----------------+
25896    /// ```
25897    #[inline]
25898    pub fn vptestnmw<A, B, C>(&mut self, op0: A, op1: B, op2: C)
25899    where
25900        Assembler<'a>: VptestnmwEmitter<A, B, C>,
25901    {
25902        <Self as VptestnmwEmitter<A, B, C>>::vptestnmw(self, op0, op1, op2);
25903    }
25904    /// `VPTESTNMW_MASK`.
25905    ///
25906    /// Supported operand variants:
25907    ///
25908    /// ```text
25909    /// +---+----------------+
25910    /// | # | Operands       |
25911    /// +---+----------------+
25912    /// | 1 | KReg, Xmm, Mem |
25913    /// | 2 | KReg, Xmm, Xmm |
25914    /// | 3 | KReg, Ymm, Mem |
25915    /// | 4 | KReg, Ymm, Ymm |
25916    /// | 5 | KReg, Zmm, Mem |
25917    /// | 6 | KReg, Zmm, Zmm |
25918    /// +---+----------------+
25919    /// ```
25920    #[inline]
25921    pub fn vptestnmw_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
25922    where
25923        Assembler<'a>: VptestnmwMaskEmitter<A, B, C>,
25924    {
25925        <Self as VptestnmwMaskEmitter<A, B, C>>::vptestnmw_mask(self, op0, op1, op2);
25926    }
25927    /// `VPUNPCKHBW`.
25928    ///
25929    /// Supported operand variants:
25930    ///
25931    /// ```text
25932    /// +---+---------------+
25933    /// | # | Operands      |
25934    /// +---+---------------+
25935    /// | 1 | Xmm, Xmm, Mem |
25936    /// | 2 | Xmm, Xmm, Xmm |
25937    /// | 3 | Ymm, Ymm, Mem |
25938    /// | 4 | Ymm, Ymm, Ymm |
25939    /// | 5 | Zmm, Zmm, Mem |
25940    /// | 6 | Zmm, Zmm, Zmm |
25941    /// +---+---------------+
25942    /// ```
25943    #[inline]
25944    pub fn vpunpckhbw<A, B, C>(&mut self, op0: A, op1: B, op2: C)
25945    where
25946        Assembler<'a>: VpunpckhbwEmitter<A, B, C>,
25947    {
25948        <Self as VpunpckhbwEmitter<A, B, C>>::vpunpckhbw(self, op0, op1, op2);
25949    }
25950    /// `VPUNPCKHBW_MASK`.
25951    ///
25952    /// Supported operand variants:
25953    ///
25954    /// ```text
25955    /// +---+---------------+
25956    /// | # | Operands      |
25957    /// +---+---------------+
25958    /// | 1 | Xmm, Xmm, Mem |
25959    /// | 2 | Xmm, Xmm, Xmm |
25960    /// | 3 | Ymm, Ymm, Mem |
25961    /// | 4 | Ymm, Ymm, Ymm |
25962    /// | 5 | Zmm, Zmm, Mem |
25963    /// | 6 | Zmm, Zmm, Zmm |
25964    /// +---+---------------+
25965    /// ```
25966    #[inline]
25967    pub fn vpunpckhbw_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
25968    where
25969        Assembler<'a>: VpunpckhbwMaskEmitter<A, B, C>,
25970    {
25971        <Self as VpunpckhbwMaskEmitter<A, B, C>>::vpunpckhbw_mask(self, op0, op1, op2);
25972    }
25973    /// `VPUNPCKHBW_MASKZ`.
25974    ///
25975    /// Supported operand variants:
25976    ///
25977    /// ```text
25978    /// +---+---------------+
25979    /// | # | Operands      |
25980    /// +---+---------------+
25981    /// | 1 | Xmm, Xmm, Mem |
25982    /// | 2 | Xmm, Xmm, Xmm |
25983    /// | 3 | Ymm, Ymm, Mem |
25984    /// | 4 | Ymm, Ymm, Ymm |
25985    /// | 5 | Zmm, Zmm, Mem |
25986    /// | 6 | Zmm, Zmm, Zmm |
25987    /// +---+---------------+
25988    /// ```
25989    #[inline]
25990    pub fn vpunpckhbw_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
25991    where
25992        Assembler<'a>: VpunpckhbwMaskzEmitter<A, B, C>,
25993    {
25994        <Self as VpunpckhbwMaskzEmitter<A, B, C>>::vpunpckhbw_maskz(self, op0, op1, op2);
25995    }
25996    /// `VPUNPCKHWD`.
25997    ///
25998    /// Supported operand variants:
25999    ///
26000    /// ```text
26001    /// +---+---------------+
26002    /// | # | Operands      |
26003    /// +---+---------------+
26004    /// | 1 | Xmm, Xmm, Mem |
26005    /// | 2 | Xmm, Xmm, Xmm |
26006    /// | 3 | Ymm, Ymm, Mem |
26007    /// | 4 | Ymm, Ymm, Ymm |
26008    /// | 5 | Zmm, Zmm, Mem |
26009    /// | 6 | Zmm, Zmm, Zmm |
26010    /// +---+---------------+
26011    /// ```
26012    #[inline]
26013    pub fn vpunpckhwd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
26014    where
26015        Assembler<'a>: VpunpckhwdEmitter<A, B, C>,
26016    {
26017        <Self as VpunpckhwdEmitter<A, B, C>>::vpunpckhwd(self, op0, op1, op2);
26018    }
26019    /// `VPUNPCKHWD_MASK`.
26020    ///
26021    /// Supported operand variants:
26022    ///
26023    /// ```text
26024    /// +---+---------------+
26025    /// | # | Operands      |
26026    /// +---+---------------+
26027    /// | 1 | Xmm, Xmm, Mem |
26028    /// | 2 | Xmm, Xmm, Xmm |
26029    /// | 3 | Ymm, Ymm, Mem |
26030    /// | 4 | Ymm, Ymm, Ymm |
26031    /// | 5 | Zmm, Zmm, Mem |
26032    /// | 6 | Zmm, Zmm, Zmm |
26033    /// +---+---------------+
26034    /// ```
26035    #[inline]
26036    pub fn vpunpckhwd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
26037    where
26038        Assembler<'a>: VpunpckhwdMaskEmitter<A, B, C>,
26039    {
26040        <Self as VpunpckhwdMaskEmitter<A, B, C>>::vpunpckhwd_mask(self, op0, op1, op2);
26041    }
26042    /// `VPUNPCKHWD_MASKZ`.
26043    ///
26044    /// Supported operand variants:
26045    ///
26046    /// ```text
26047    /// +---+---------------+
26048    /// | # | Operands      |
26049    /// +---+---------------+
26050    /// | 1 | Xmm, Xmm, Mem |
26051    /// | 2 | Xmm, Xmm, Xmm |
26052    /// | 3 | Ymm, Ymm, Mem |
26053    /// | 4 | Ymm, Ymm, Ymm |
26054    /// | 5 | Zmm, Zmm, Mem |
26055    /// | 6 | Zmm, Zmm, Zmm |
26056    /// +---+---------------+
26057    /// ```
26058    #[inline]
26059    pub fn vpunpckhwd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
26060    where
26061        Assembler<'a>: VpunpckhwdMaskzEmitter<A, B, C>,
26062    {
26063        <Self as VpunpckhwdMaskzEmitter<A, B, C>>::vpunpckhwd_maskz(self, op0, op1, op2);
26064    }
26065    /// `VPUNPCKLBW`.
26066    ///
26067    /// Supported operand variants:
26068    ///
26069    /// ```text
26070    /// +---+---------------+
26071    /// | # | Operands      |
26072    /// +---+---------------+
26073    /// | 1 | Xmm, Xmm, Mem |
26074    /// | 2 | Xmm, Xmm, Xmm |
26075    /// | 3 | Ymm, Ymm, Mem |
26076    /// | 4 | Ymm, Ymm, Ymm |
26077    /// | 5 | Zmm, Zmm, Mem |
26078    /// | 6 | Zmm, Zmm, Zmm |
26079    /// +---+---------------+
26080    /// ```
26081    #[inline]
26082    pub fn vpunpcklbw<A, B, C>(&mut self, op0: A, op1: B, op2: C)
26083    where
26084        Assembler<'a>: VpunpcklbwEmitter<A, B, C>,
26085    {
26086        <Self as VpunpcklbwEmitter<A, B, C>>::vpunpcklbw(self, op0, op1, op2);
26087    }
26088    /// `VPUNPCKLBW_MASK`.
26089    ///
26090    /// Supported operand variants:
26091    ///
26092    /// ```text
26093    /// +---+---------------+
26094    /// | # | Operands      |
26095    /// +---+---------------+
26096    /// | 1 | Xmm, Xmm, Mem |
26097    /// | 2 | Xmm, Xmm, Xmm |
26098    /// | 3 | Ymm, Ymm, Mem |
26099    /// | 4 | Ymm, Ymm, Ymm |
26100    /// | 5 | Zmm, Zmm, Mem |
26101    /// | 6 | Zmm, Zmm, Zmm |
26102    /// +---+---------------+
26103    /// ```
26104    #[inline]
26105    pub fn vpunpcklbw_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
26106    where
26107        Assembler<'a>: VpunpcklbwMaskEmitter<A, B, C>,
26108    {
26109        <Self as VpunpcklbwMaskEmitter<A, B, C>>::vpunpcklbw_mask(self, op0, op1, op2);
26110    }
26111    /// `VPUNPCKLBW_MASKZ`.
26112    ///
26113    /// Supported operand variants:
26114    ///
26115    /// ```text
26116    /// +---+---------------+
26117    /// | # | Operands      |
26118    /// +---+---------------+
26119    /// | 1 | Xmm, Xmm, Mem |
26120    /// | 2 | Xmm, Xmm, Xmm |
26121    /// | 3 | Ymm, Ymm, Mem |
26122    /// | 4 | Ymm, Ymm, Ymm |
26123    /// | 5 | Zmm, Zmm, Mem |
26124    /// | 6 | Zmm, Zmm, Zmm |
26125    /// +---+---------------+
26126    /// ```
26127    #[inline]
26128    pub fn vpunpcklbw_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
26129    where
26130        Assembler<'a>: VpunpcklbwMaskzEmitter<A, B, C>,
26131    {
26132        <Self as VpunpcklbwMaskzEmitter<A, B, C>>::vpunpcklbw_maskz(self, op0, op1, op2);
26133    }
26134    /// `VPUNPCKLWD`.
26135    ///
26136    /// Supported operand variants:
26137    ///
26138    /// ```text
26139    /// +---+---------------+
26140    /// | # | Operands      |
26141    /// +---+---------------+
26142    /// | 1 | Xmm, Xmm, Mem |
26143    /// | 2 | Xmm, Xmm, Xmm |
26144    /// | 3 | Ymm, Ymm, Mem |
26145    /// | 4 | Ymm, Ymm, Ymm |
26146    /// | 5 | Zmm, Zmm, Mem |
26147    /// | 6 | Zmm, Zmm, Zmm |
26148    /// +---+---------------+
26149    /// ```
26150    #[inline]
26151    pub fn vpunpcklwd<A, B, C>(&mut self, op0: A, op1: B, op2: C)
26152    where
26153        Assembler<'a>: VpunpcklwdEmitter<A, B, C>,
26154    {
26155        <Self as VpunpcklwdEmitter<A, B, C>>::vpunpcklwd(self, op0, op1, op2);
26156    }
26157    /// `VPUNPCKLWD_MASK`.
26158    ///
26159    /// Supported operand variants:
26160    ///
26161    /// ```text
26162    /// +---+---------------+
26163    /// | # | Operands      |
26164    /// +---+---------------+
26165    /// | 1 | Xmm, Xmm, Mem |
26166    /// | 2 | Xmm, Xmm, Xmm |
26167    /// | 3 | Ymm, Ymm, Mem |
26168    /// | 4 | Ymm, Ymm, Ymm |
26169    /// | 5 | Zmm, Zmm, Mem |
26170    /// | 6 | Zmm, Zmm, Zmm |
26171    /// +---+---------------+
26172    /// ```
26173    #[inline]
26174    pub fn vpunpcklwd_mask<A, B, C>(&mut self, op0: A, op1: B, op2: C)
26175    where
26176        Assembler<'a>: VpunpcklwdMaskEmitter<A, B, C>,
26177    {
26178        <Self as VpunpcklwdMaskEmitter<A, B, C>>::vpunpcklwd_mask(self, op0, op1, op2);
26179    }
26180    /// `VPUNPCKLWD_MASKZ`.
26181    ///
26182    /// Supported operand variants:
26183    ///
26184    /// ```text
26185    /// +---+---------------+
26186    /// | # | Operands      |
26187    /// +---+---------------+
26188    /// | 1 | Xmm, Xmm, Mem |
26189    /// | 2 | Xmm, Xmm, Xmm |
26190    /// | 3 | Ymm, Ymm, Mem |
26191    /// | 4 | Ymm, Ymm, Ymm |
26192    /// | 5 | Zmm, Zmm, Mem |
26193    /// | 6 | Zmm, Zmm, Zmm |
26194    /// +---+---------------+
26195    /// ```
26196    #[inline]
26197    pub fn vpunpcklwd_maskz<A, B, C>(&mut self, op0: A, op1: B, op2: C)
26198    where
26199        Assembler<'a>: VpunpcklwdMaskzEmitter<A, B, C>,
26200    {
26201        <Self as VpunpcklwdMaskzEmitter<A, B, C>>::vpunpcklwd_maskz(self, op0, op1, op2);
26202    }
26203}
asmkit/x86/features/AVX512BW.rs

asmkit/x86/features/
AVX512BW.rs
