asic_rs/data/device/
mod.rs

1#[cfg(feature = "python")]
2use pyo3::prelude::*;
3use std::fmt::Display;
4use std::str::FromStr;
5
6use serde::{Deserialize, Serialize};
7use strum::Display;
8
9pub mod models;
10pub use models::MinerModel;
11
12#[cfg_attr(feature = "python", pyclass(str, module = "asic_rs"))]
13#[derive(Debug, PartialEq, Eq, Clone, Copy, Hash, Serialize, Deserialize, Display)]
14pub enum MinerFirmware {
15    #[serde(rename = "Stock")]
16    Stock,
17    #[serde(rename = "BraiinsOS")]
18    BraiinsOS,
19    #[serde(rename = "VNish")]
20    VNish,
21    #[serde(rename = "ePIC")]
22    EPic,
23    #[serde(rename = "HiveOS")]
24    HiveOS,
25    #[serde(rename = "LuxOS")]
26    LuxOS,
27    #[serde(rename = "Marathon")]
28    Marathon,
29    #[serde(rename = "MSKMiner")]
30    MSKMiner,
31}
32
33#[cfg_attr(feature = "python", pyclass(str, module = "asic_rs"))]
34#[derive(Debug, PartialEq, Eq, Clone, Copy, Hash, Serialize, Deserialize, Display)]
35pub enum MinerMake {
36    #[serde(rename = "AntMiner")]
37    AntMiner,
38    #[serde(rename = "WhatsMiner")]
39    WhatsMiner,
40    #[serde(rename = "AvalonMiner")]
41    AvalonMiner,
42    #[serde(rename = "ePIC")]
43    EPic,
44    #[serde(rename = "Braiins")]
45    Braiins,
46    #[serde(rename = "Bitaxe")]
47    Bitaxe,
48}
49
50#[cfg_attr(feature = "python", pyclass(str, module = "asic_rs"))]
51#[derive(Debug, PartialEq, Eq, Clone, Copy, Hash, Serialize, Deserialize, Display)]
52pub enum HashAlgorithm {
53    #[serde(rename = "SHA256")]
54    SHA256,
55    #[serde(rename = "Scrypt")]
56    Scrypt,
57    #[serde(rename = "X11")]
58    X11,
59    #[serde(rename = "Blake2S256")]
60    Blake2S256,
61    #[serde(rename = "Kadena")]
62    Kadena,
63}
64
65#[cfg_attr(feature = "python", pyclass(get_all, module = "asic_rs"))]
66#[derive(Debug, PartialEq, Eq, Clone, Copy, Hash, Serialize, Deserialize)]
67pub struct DeviceInfo {
68    pub make: MinerMake,
69    pub model: MinerModel,
70    pub hardware: MinerHardware,
71    pub firmware: MinerFirmware,
72    pub algo: HashAlgorithm,
73}
74
75impl DeviceInfo {
76    pub(crate) fn new(
77        make: MinerMake,
78        model: MinerModel,
79        firmware: MinerFirmware,
80        algo: HashAlgorithm,
81    ) -> Self {
82        Self {
83            make,
84            hardware: MinerHardware::from(&model),
85            model,
86            firmware,
87            algo,
88        }
89    }
90}
91
92#[cfg_attr(feature = "python", pyclass(get_all, module = "asic_rs"))]
93#[derive(Debug, PartialEq, Eq, Clone, Copy, Hash, Serialize, Deserialize)]
94pub struct MinerHardware {
95    pub chips: Option<u16>,
96    pub fans: Option<u8>,
97    pub boards: Option<u8>,
98}
99
100impl From<&MinerModel> for MinerHardware {
101    fn from(model: &MinerModel) -> Self {
102        match model {
103            MinerModel::AntMiner(model_name) => Self::from(model_name),
104            MinerModel::WhatsMiner(model_name) => Self::from(model_name),
105            MinerModel::Braiins(model_name) => Self::from(model_name),
106            MinerModel::Bitaxe(model_name) => Self::from(model_name),
107            MinerModel::EPic(model_name) => Self::from(model_name),
108            MinerModel::AvalonMiner(model_name) => Self::from(model_name),
109        }
110    }
111}
112
113#[derive(Debug, PartialEq, Eq, Clone, Hash, Serialize, Deserialize, Display)]
114pub enum MinerControlBoard {
115    // Antminer control boards
116    #[serde(rename = "Xilinx")]
117    Xilinx,
118    #[serde(rename = "BeagleBoneBlack")]
119    BeagleBoneBlack,
120    #[serde(rename = "AMLogic")]
121    AMLogic,
122    #[serde(rename = "CVITek")]
123    CVITek,
124    // Whatsminer control boards
125    #[serde(rename = "H3")]
126    H3,
127    #[serde(rename = "H6")]
128    H6,
129    #[serde(rename = "H6OS")]
130    H6OS,
131    #[serde(rename = "H616")]
132    H616,
133    // Avalon control boards
134    #[serde(rename = "MM3v2X3")]
135    MM3v2X3,
136    #[serde(rename = "MM3v1X3")]
137    MM3v1X3,
138    #[serde(rename = "MM3v1")]
139    MM3v1,
140    // Bitaxe control boards
141    #[serde(rename = "B102")]
142    B102,
143    #[serde(rename = "B201")]
144    B201,
145    #[serde(rename = "B202")]
146    B202,
147    #[serde(rename = "B203")]
148    B203,
149    #[serde(rename = "B204")]
150    B204,
151    #[serde(rename = "B205")]
152    B205,
153    #[serde(rename = "B207")]
154    B207,
155    #[serde(rename = "B401")]
156    B401,
157    #[serde(rename = "B402")]
158    B402,
159    #[serde(rename = "B403")]
160    B403,
161    #[serde(rename = "B601")]
162    B601,
163    #[serde(rename = "B602")]
164    B602,
165    #[serde(rename = "B800")]
166    B800,
167    // Custom control boards
168    #[serde(rename = "BraiinsCB")]
169    BraiinsCB,
170    #[serde(rename = "ePIC UMC")]
171    EPicUMC,
172    #[serde(rename = "MaraCB")]
173    MaraCB,
174    // Unknown
175    Unknown(String),
176}
177
178#[derive(Debug, Clone)]
179pub struct ControlBoardParseError;
180
181impl Display for ControlBoardParseError {
182    fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
183        write!(f, "Failed to parse control board type")
184    }
185}
186
187impl FromStr for MinerControlBoard {
188    type Err = String;
189
190    fn from_str(s: &str) -> Result<Self, Self::Err> {
191        let cb_model = s.trim().replace(" ", "").to_uppercase();
192        match cb_model.as_ref() {
193            "XILINX" => Ok(Self::Xilinx),
194            "BBB" => Ok(Self::BeagleBoneBlack),
195            "BB" => Ok(Self::BeagleBoneBlack),
196            "BEAGLEBONE" => Ok(Self::BeagleBoneBlack),
197            "BEAGLEBONEBLACK" => Ok(Self::BeagleBoneBlack),
198            "CVITEK" => Ok(Self::CVITek),
199            "CVCTRL" => Ok(Self::CVITek),
200            "AMLOGIC" => Ok(Self::AMLogic),
201            "AML" => Ok(Self::AMLogic),
202            "H3" => Ok(Self::H3),
203            "H6" => Ok(Self::H6),
204            "H6OS" => Ok(Self::H6OS),
205            "H616" => Ok(Self::H616),
206            "MM3V2_X3" => Ok(Self::MM3v2X3),
207            "MM3V1_X3" => Ok(Self::MM3v1X3),
208            "MM3V1" => Ok(Self::MM3v1),
209            "B102" => Ok(Self::B102),
210            "B201" => Ok(Self::B201),
211            "B202" => Ok(Self::B202),
212            "B203" => Ok(Self::B203),
213            "B204" => Ok(Self::B204),
214            "B205" => Ok(Self::B205),
215            "B207" => Ok(Self::B207),
216            "B401" => Ok(Self::B401),
217            "B402" => Ok(Self::B402),
218            "B403" => Ok(Self::B403),
219            "B601" => Ok(Self::B601),
220            "B602" => Ok(Self::B602),
221            "B800" => Ok(Self::B800),
222            "BraiinsCB" => Ok(Self::BraiinsCB),
223            "ePIC UMC" => Ok(Self::EPicUMC),
224            _ => Ok(Self::Unknown(s.to_string())),
225        }
226    }
227}
asic_rs/data/device/mod.rs

asic_rs/data/device/
mod.rs
