arm_gicv2/
lib.rs

1#![no_std]
2#![feature(const_option)]
3#![feature(const_nonnull_new)]
4#![doc = include_str!("../README.md")]
5
6use core::ops::Range;
7
8mod gic_v2;
9
10pub use gic_v2::{GicCpuInterface, GicDistributor};
11
12/// Interrupt ID 0-15 are used for SGIs (Software-generated interrupt).
13///
14/// SGI is an interrupt generated by software writing to a GICD_SGIR register in
15/// the GIC. The system uses SGIs for interprocessor communication.
16pub const SGI_RANGE: Range<usize> = 0..16;
17
18/// Interrupt ID 16-31 are used for PPIs (Private Peripheral Interrupt).
19///
20/// PPI is a peripheral interrupt that is specific to a single processor.
21pub const PPI_RANGE: Range<usize> = 16..32;
22
23/// Interrupt ID 32-1019 are used for SPIs (Shared Peripheral Interrupt).
24///
25/// SPI is a peripheral interrupt that the Distributor can route to any of a
26/// specified combination of processors.
27pub const SPI_RANGE: Range<usize> = 32..1020;
28
29/// Maximum number of interrupts supported by the GIC.
30pub const GIC_MAX_IRQ: usize = 1024;
31
32/// Interrupt trigger mode.
33pub enum TriggerMode {
34    /// Edge-triggered.
35    ///
36    /// This is an interrupt that is asserted on detection of a rising edge of
37    /// an interrupt signal and then, regardless of the state of the signal,
38    /// remains asserted until it is cleared by the conditions defined by this
39    /// specification.
40    Edge = 0,
41    /// Level-sensitive.
42    ///
43    /// This is an interrupt that is asserted whenever the interrupt signal
44    /// level is active, and deasserted whenever the level is not active.
45    Level = 1,
46}
47
48/// Different types of interrupt that the GIC handles.
49pub enum InterruptType {
50    /// Software-generated interrupt.
51    ///
52    /// SGIs are typically used for inter-processor communication and are
53    /// generated by a write to an SGI register in the GIC.
54    SGI,
55    /// Private Peripheral Interrupt.
56    ///
57    /// Peripheral interrupts that are private to one core.
58    PPI,
59    /// Shared Peripheral Interrupt.
60    ///
61    /// Peripheral interrupts that can delivered to any connected core.
62    SPI,
63}
64
65/// Translate an interrupt of a given type to a GIC INTID.
66pub const fn translate_irq(id: usize, int_type: InterruptType) -> Option<usize> {
67    match int_type {
68        InterruptType::SGI => {
69            if id < SGI_RANGE.end {
70                Some(id)
71            } else {
72                None
73            }
74        }
75        InterruptType::PPI => {
76            if id < PPI_RANGE.end - PPI_RANGE.start {
77                Some(id + PPI_RANGE.start)
78            } else {
79                None
80            }
81        }
82        InterruptType::SPI => {
83            if id < SPI_RANGE.end - SPI_RANGE.start {
84                Some(id + SPI_RANGE.start)
85            } else {
86                None
87            }
88        }
89    }
90}
arm_gicv2/lib.rs

arm_gicv2/
lib.rs
