arm_tzc/fail.rs
1// SPDX-FileCopyrightText: Copyright The arm-tzc Contributors.
2// SPDX-License-Identifier: MIT OR Apache-2.0
3
4use safe_mmio::{SharedMmioPointer, field_shared, fields::ReadPure};
5use zerocopy::{FromBytes, Immutable, IntoBytes, KnownLayout};
6
7use crate::utils::{concatenate_address_parts, extract_bits, get_bit};
8
9#[derive(Debug, Clone, Copy, Eq, FromBytes, Immutable, IntoBytes, KnownLayout, PartialEq)]
10/// Each filter unit has a fail control register which contains the control status information of
11/// the first access that failed a region permission check in the associated filter unit. This
12/// occurs even if the [`ActionRegister`][crate::ActionRegister] is set to not drive the interrupt
13/// signal.
14///
15/// The first failing access is defined as the first permission failure in the associated filter
16/// unit after one of the following occurs:
17///
18/// - Reset.
19/// - The last clearance of an interrupt using the
20/// [`InterruptClearRegister`][crate::InterruptClearRegister].
21#[repr(transparent)]
22pub struct FailControlRegister(u32);
23
24#[derive(Clone, Copy, Debug, Eq, PartialEq)]
25/// See [`FailControlRegister::direction`].
26pub enum FailAccessDirection {
27 /// Attempted access was a read.
28 Read,
29 /// Attempted access was a write.
30 Write,
31}
32
33impl FailControlRegister {
34 /// If a region permission check fails or a region overlap occurs, this field indicates whether
35 /// the failed access was a read or write access attempt.
36 ///
37 /// You must clear the associated interrupt status before this field can return the direction of
38 /// accesses of subsequent permission checks or region overlap failures.
39 ///
40 /// If the status flag for the filter unit in the
41 /// [`InterruptStatusRegister`][crate::InterruptStatusRegister] is already set, new region
42 /// permission check failures in the same filter unit do not update the associated fail status
43 /// group of registers.
44 pub const fn direction(&self) -> FailAccessDirection {
45 if get_bit(self.0, 24) {
46 FailAccessDirection::Write
47 } else {
48 FailAccessDirection::Read
49 }
50 }
51
52 /// If a region permission check fails or a region overlap occurs, this field indicates whether
53 /// it was a Secure (`false`) or Non-secure (`true`) access attempt.
54 ///
55 /// You must clear the associated interrupt status before this field can return the direction of
56 /// accesses of subsequent permission checks or region overlap failures.
57 ///
58 /// If the status flag for the filter unit in the
59 /// [`InterruptStatusRegister`][crate::InterruptStatusRegister] is already set, new region
60 /// permission check failures in the same filter unit do not update the associated fail status
61 /// group of registers.
62 pub const fn non_secure(&self) -> bool {
63 get_bit(self.0, 21)
64 }
65
66 /// If a region permission check fails or a region overlap occurs, this field indicates whether
67 /// it was a privileged (`true`) or unprivileged (`false`) access attempt.
68 ///
69 /// You must clear the associated interrupt status before this field can return the direction of
70 /// accesses of subsequent permission checks or region overlap failures.
71 ///
72 /// If the status flag for the filter unit in the
73 /// [`InterruptStatusRegister`][crate::InterruptStatusRegister] is already set, new region
74 /// permission check failures in the same filter unit do not update the associated fail status
75 /// group of registers.
76 pub const fn privileged(&self) -> bool {
77 get_bit(self.0, 20)
78 }
79}
80
81#[derive(Debug, Clone, Copy, Eq, FromBytes, Immutable, IntoBytes, KnownLayout, PartialEq)]
82/// Each filter unit has a fail id register which contains the master ACE-Lite ARID or AWID of the
83/// first access that failed a region permission check in the associated filter unit. This occurs
84/// even if the [`ActionRegister`][crate::ActionRegister] is set to not drive the interrupt signal.
85///
86/// The first failing access is defined as the first permission failure in the associated filter
87/// unit after one of the following occurs:
88///
89/// - Reset.
90/// - The last clearance of an interrupt using the
91/// [`InterruptClearRegister`][crate::InterruptClearRegister].
92#[repr(transparent)]
93pub struct FailIDRegister(u32);
94
95impl FailIDRegister {
96 /// If a region permission check fails or a region overlap occurs, this field returns the VN
97 /// number of the first failed access, from either ARVNET<x> or AWVNET<x> as
98 /// appropriate. If the status flag for the filter unit in the
99 /// [`InterruptStatusRegister`][crate::InterruptStatusRegister] already set, new region
100 /// permission check failures in the same filter unit do not update the associated fail status
101 /// group of registers.
102 pub const fn vnet(&self) -> u32 {
103 extract_bits(self.0, 27, 24)
104 }
105
106 /// If a region permission check fails or a region overlap occurs, this field returns the
107 /// ACE-Lite ID values of the first failed access.
108 ///
109 /// If the status flag for the filter unit in the
110 /// [`InterruptStatusRegister`][crate::InterruptStatusRegister] is already set, new region
111 /// permission check failures in the same filter unit do not update the associated fail status
112 /// group of registers.
113 pub const fn id(&self) -> u32 {
114 // TODO: use AID_WIDTH - 1 as upper bound.
115 extract_bits(self.0, 23, 0)
116 }
117}
118
119#[derive(Debug, Clone, Eq, FromBytes, Immutable, IntoBytes, KnownLayout, PartialEq)]
120#[repr(C, align(4))]
121pub(crate) struct FailRegisters {
122 /// 0x020 + (0x10 * x): Fail address low register.
123 fail_address_low: ReadPure<u32>,
124 /// 0x024 + (0x10 * x): Fail address high register.
125 fail_address_high: ReadPure<u32>,
126 /// 0x028 + (0x10 * x): Fail control register.
127 fail_control: ReadPure<FailControlRegister>,
128 /// 0x02C + (0x10 * x): Fail ID register.
129 fail_id: ReadPure<FailIDRegister>, /* TODO: size depends on configuration: https://developer.arm.com/documentation/ddi0504/c/programmers-model/register-summary?lang=en, footnote d. */
130}
131/// Wrapper structure to allow reading registers detailing the last failure of a filter unit. See
132/// also [`Tzc::fail`][crate::Tzc::filter_failure].
133pub struct TzcFail<'regs> {
134 pub(crate) regs: SharedMmioPointer<'regs, FailRegisters>,
135}
136
137impl<'a> TzcFail<'a> {
138 /// Returns the address of the first access that failed a region permission check in the
139 /// associated filter unit. This occurs even if the [`ActionRegister`][crate::ActionRegister] is
140 /// set to not drive the interrupt signal. See Action register.
141 ///
142 /// The first failing access is defined as the first permission failure in the associated filter
143 /// unit after one of the following occurs:
144 /// - Reset.
145 /// - The last clearance of an interrupt using the
146 /// [`InterruptClearRegister`][crate::InterruptClearRegister].
147 pub fn fail_address(&self) -> u64 {
148 concatenate_address_parts(
149 field_shared!(self.regs, fail_address_low).read(),
150 field_shared!(self.regs, fail_address_high).read(),
151 )
152 }
153
154 /// Returns the [`FailControlRegister`] of this filter.
155 pub fn fail_control(&self) -> FailControlRegister {
156 field_shared!(self.regs, fail_control).read()
157 }
158
159 /// Returns the [`FailIDRegister`] of this filter.
160 pub fn fail_id(&self) -> FailIDRegister {
161 field_shared!(self.regs, fail_id).read()
162 }
163}
164
165#[cfg(test)]
166mod tests {
167 use crate::{tests::FakeTZCRegisters, *};
168
169 #[test]
170 fn fail_oob() {
171 let mut regs = FakeTZCRegisters::new();
172 regs.reg_write(0x008, 0b0000_0000_0000_0010_0000_0000_0000_0000);
173 let tzc = regs.tzc_for_test();
174
175 assert!(tzc.filter_failure(2).is_none());
176 assert!(tzc.filter_failure(3).is_none());
177 assert!(tzc.filter_failure(4).is_none());
178 assert!(tzc.filter_failure(18).is_none());
179 }
180
181 #[test]
182 pub fn fail_address() {
183 let mut regs = FakeTZCRegisters::new();
184 regs.reg_write(0x000, 0b0000_0011_0000_0000_0010_1111_0000_1000);
185 for i in 0..4 {
186 regs.reg_write(0x020 + i * 0x10, 0xabcd_0000);
187 regs.reg_write(0x024 + i * 0x10, 0xfc00 | i as u32);
188 }
189
190 let tzc = regs.tzc_for_test();
191
192 for i in 0..4 {
193 assert_eq!(
194 tzc.filter_failure(i).unwrap().fail_address(),
195 0xfc00_abcd_0000 | ((i as u64) << 32),
196 );
197 }
198 }
199
200 #[test]
201 fn fail_control() {
202 let mut regs = FakeTZCRegisters::new();
203 regs.reg_write(0x000, 0b0000_0011_0000_0000_0010_1111_0000_1000);
204 regs.reg_write(0x028, 0b0000_0001_0010_0000_0000_0000_0000_0000);
205 regs.reg_write(0x038, 0b0000_0000_0011_0000_0000_0000_0000_0000);
206 regs.reg_write(0x048, 0b0000_0001_0000_0000_0000_0000_0000_0000);
207 regs.reg_write(0x058, 0b0000_0000_0001_0000_0000_0000_0000_0000);
208 let tzc = regs.tzc_for_test();
209
210 let fc0 = tzc.filter_failure(0).unwrap().fail_control();
211 let fc1 = tzc.filter_failure(1).unwrap().fail_control();
212 let fc2 = tzc.filter_failure(2).unwrap().fail_control();
213 let fc3 = tzc.filter_failure(3).unwrap().fail_control();
214
215 assert_eq!(fc0.direction(), FailAccessDirection::Write);
216 assert!(!fc0.privileged());
217 assert!(fc0.non_secure());
218
219 assert_eq!(fc1.direction(), FailAccessDirection::Read);
220 assert!(fc1.privileged());
221 assert!(fc1.non_secure());
222
223 assert_eq!(fc2.direction(), FailAccessDirection::Write);
224 assert!(!fc2.privileged());
225 assert!(!fc2.non_secure());
226
227 assert_eq!(fc3.direction(), FailAccessDirection::Read);
228 assert!(fc3.privileged());
229 assert!(!fc3.non_secure());
230 }
231
232 #[test]
233 fn fail_id() {
234 let mut regs = FakeTZCRegisters::new();
235 regs.reg_write(0x000, 0b0000_0011_0000_0000_0010_1111_0000_1000);
236 regs.reg_write(0x02C, 0x05_00_be_ef);
237 regs.reg_write(0x03C, 0x02_de_ad_00);
238 regs.reg_write(0x04C, 0x08_ab_cd_ef);
239 regs.reg_write(0x05C, 0x0f_fe_d0_af);
240 let tzc = regs.tzc_for_test();
241
242 let fid0 = tzc.filter_failure(0).unwrap().fail_id();
243 let fid1 = tzc.filter_failure(1).unwrap().fail_id();
244 let fid2 = tzc.filter_failure(2).unwrap().fail_id();
245 let fid3 = tzc.filter_failure(3).unwrap().fail_id();
246
247 assert_eq!(fid0.vnet(), 5);
248 assert_eq!(fid0.id(), 0xbeef);
249
250 assert_eq!(fid1.vnet(), 2);
251 assert_eq!(fid1.id(), 0xdead00);
252
253 assert_eq!(fid2.vnet(), 8);
254 assert_eq!(fid2.id(), 0xabcdef);
255
256 assert_eq!(fid3.vnet(), 15);
257 assert_eq!(fid3.id(), 0xfed0af);
258 }
259}