Crate arm_pl011_uart

Crate arm_pl011_uart 

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§Arm PrimeCell UART (PL011) driver

Driver implementation for the PL011 UART peripheral.

The driver is designed to function regardless of whether a Memory Management Unit (MMU) is present. The primary role of the OwnedMmioPointer is to manage the lifetime of the peripheral, ensuring proper resource handling. In a system that includes an MMU, the peripheral’s lifetime is dynamic because it is mapped into memory rather than having a fixed address. In a system without an MMU, the OwnedMmioPointer can be instantiated directly from the physical address of the register block, providing access to the peripheral without requiring memory mapping.

§Implemented features

  • Enabling/disabling UART peripheral which includes configuring the data bit number, parity settings, stop bit count and baudrate
  • Checking various status flags
  • Non-blocking read/write functions
  • Handling UART errors
  • Reading UART identification structure
  • 98% unit test coverage
  • Setting FIFO level of RX/TX interrupts
  • Reading, masking and clearing interrupts
  • Implementing various traits
    • embedded_hal_nb::serial::{Write, Read} (optional, behind the embedded-hal-nb feature flag)
    • embedded_io::{Write, Read} (optional, behind the embedded-io feature flag)
    • core::fmt::Write

§Feature flags

  • embedded-hal-nb: Adds implementations of embedded-hal-nb traits for the UART driver.
  • embedded-io: Adds implementations of embedded-io traits for the UART driver.

§Future plans

  • Handling modem control and status signals
  • Adding peripheral testing

§License

The project is MIT and Apache-2.0 dual licensed, see LICENSE-APACHE and LICENSE-MIT.

§Maintainers

arm-pl011-uart is a trustedfirmware.org maintained project. All contributions are ultimately merged by the maintainers listed below.

§Contributing

Please follow the directions of the Trusted Firmware Processes

Contributions are handled through review.trustedfirmware.org.

§Arm trademark notice

Arm is a registered trademark of Arm Limited (or its subsidiaries or affiliates).

This project uses some of the Arm product, service or technology trademarks, as listed in the Trademark List, in accordance with the Arm Trademark Use Guidelines.

Subsequent uses of these trademarks throughout this repository do not need to be prefixed with the Arm word trademark.

Copyright The arm-pl011-uart Contributors.

§Example

use arm_pl011_uart::{DataBits, LineConfig, Parity, PL011Registers, StopBits, Uart, UniqueMmioPointer};
use core::{fmt::Write, ptr::NonNull};

// SAFETY: `UART_ADDRESS` is the base address of a PL011 UART register block. It remains valid for
// the lifetime of the application and nothing else references this address range.
let uart_pointer = unsafe { UniqueMmioPointer::new(NonNull::new(UART_ADDRESS).unwrap()) };

// Create driver instance
let mut uart = Uart::new(uart_pointer);

// Configure and enable UART
let line_config = LineConfig {
    data_bits: DataBits::Bits8,
    parity: Parity::None,
    stop_bits: StopBits::One,
};
uart.enable(line_config, 115_200, 16_000_000);

// Send and receive data
uart.write_word(0x5a);
uart.write_str("Hello Uart!");
println!("{:?}", uart.read_word());

Structs§

Identification
UART peripheral identification structure
Interrupts
Set of interrupts. This is used for the interrupt status registers (UARTRIS and UARTMIS), interrupt mask register (UARTIMSC) and and interrupt clear register (UARTICR).
LineConfig
UART line config structure
PL011Registers
PL011 register map
Uart
PL011 UART implementation
UniqueMmioPointer
A unique owned pointer to the registers of some MMIO device.

Enums§

DataBits
Data bit count
Error
PL011 UART error type
FifoLevel
RX/TX interrupt FIFO levels
Parity
Parity
StopBits
Stop bit count