Crate arm_gic 

Driver for the Arm Generic Interrupt Controller version 2, 3 or 4, on aarch64.

This top level module contains functions that are not specific to any particular interrupt controller, as support for other GIC versions may be added in future.

Example

Using a GICv3 on a single-core aarch64 system:

use arm_gic::{
    IntId,
    UniqueMmioPointer,
    gicv3::{
        GicCpuInterface, GicV3, SgiTarget, SgiTargetGroup,
        registers::{Gicd, GicrSgi},
    },
    irq_enable,
};
use core::ptr::NonNull;

// Base addresses of the GICv3 distributor and redistributor.
const GICD_BASE_ADDRESS: *mut Gicd = 0x800_0000 as _;
const GICR_BASE_ADDRESS: *mut GicrSgi = 0x80A_0000 as _;

let gicd = unsafe { UniqueMmioPointer::new(NonNull::new(GICD_BASE_ADDRESS).unwrap()) };
let gicr = unsafe { NonNull::new(GICR_BASE_ADDRESS).unwrap() };

// Initialise the GIC.
let mut gic = unsafe { GicV3::new(gicd, gicr, 1, false) };
gic.setup(0);

// Configure an SGI and then send it to ourself.
let sgi_intid = IntId::sgi(3);
GicCpuInterface::set_priority_mask(0xff);
gic.set_interrupt_priority(sgi_intid, Some(0), 0x80);
gic.enable_interrupt(sgi_intid, Some(0), true);
irq_enable();
GicCpuInterface::send_sgi(
    sgi_intid,
    SgiTarget::List {
        affinity3: 0,
        affinity2: 0,
        affinity1: 0,
        target_list: 0b1,
    },
    SgiTargetGroup::CurrentGroup1,
);

Modules

gicv2

Driver for the Arm Generic Interrupt Controller version 2.

gicv3

Driver for the Arm Generic Interrupt Controller version 3 (or 4).

Structs

IntId

An interrupt ID.

UniqueMmioPointer

A unique owned pointer to the registers of some MMIO device.

Enums

Trigger

The trigger configuration for an interrupt.

Functions

irq_disable

Disables debug, SError, IRQ and FIQ exceptions.

irq_enable

Enables debug, SError, IRQ and FIQ exceptions.

wfi

Waits for an interrupt.