Crate arm_generic_timer

Source
Expand description

§Arm Generic Timer driver

Driver implementation for the memory mapped Generic Timer peripheral of the Arm A-profile architecture. The implementation is based on the following sections of the Arm Architecture Reference Manual for A-profile architecture.

  • I2.2.3 Counter module control and status register summary
  • I2.3 Memory-mapped timer components
  • I5.6 Generic Timer memory-mapped registers overview
  • I5.7 Generic Timer memory-mapped register descriptions

§Implemented features

  • Register descriptions and drivers for the following frames:
    • CNTControlBase
    • CNTCTLBase
    • CNTReadBase
    • CNTBaseN
    • CNTEL0BaseN
  • Blocking and interrupt based timer wait functions.

§License

The project is MIT and Apache-2.0 dual licensed, see LICENSE-APACHE and LICENSE-MIT.

§Maintainers

arm-generic-timer is a trustedfirmware.org maintained project. All contributions are ultimately merged by the maintainers listed below.

§Contributing

Please follow the directions of the Trusted Firmware Processes

Contributions are handled through review.trustedfirmware.org.

§Arm trademark notice

Arm is a registered trademark of Arm Limited (or its subsidiaries or affiliates).

This project uses some of the Arm product, service or technology trademarks, as listed in the Trademark List, in accordance with the Arm Trademark Use Guidelines.

Subsequent uses of these trademarks throughout this repository do not need to be prefixed with the Arm word trademark.

Copyright The arm-generic-timer Contributors.

Structs§

CntAcr
Counter-timer Access Control Register.
CntBase
Table I2-4 CNTBaseN memory map
CntControlBase
Table I2-1 CNTControlBase memory map
CntCr
Counter Control Register
CntCtlBase
Table I2-3 CNTCTLBase memory map
CntEl0Acr
Counter-timer EL0 Access Control Register.
CntEl0Base
CntEl0Base frame is identical to the CntBase frame, except that CNTVOFF, CNTEL0ACR registers are never visible and CNTEL0ACR of the corresponding CntBase controls the access of the physical and virtual timer registers.
CntId
Counter Identification Register.
CntReadBase
Table I2-2 CNTReadBase memory map
CntSr
Counter Status Register
Features
Timer feature bits, defined at I5.7.16 CNTTIDR, Counter-timer Timer ID Register description.
GenericTimerCnt
Driver for the CNTBase timer block.
GenericTimerCntEl0
Driver for the CNTEL0Base timer block.
GenericTimerControl
Driver for the CNTControlBase block.
GenericTimerCtl
Driver for the CNTCTLBase block.
Timer
Driver for the physical or virtual timer instance of the CNTBase block.
TimerControl
Common control register of the physical and virtual timers. Defined at I5.7.10 CNTP_CTL, Counter-timer Physical Timer Control and at CNTV_CTL, Counter-timer Virtual Timer Control.
TimerRegs
Repeated subset of register that describe a physical or virtual timer in the CntBase or CntEl0Base blocks.