Module memory_mapped 

Memory mapped timer driver implementations.

See I5.6 Generic Timer memory-mapped registers overview.

Structs

CntAcr

Counter-timer Access Control Register.

CntBase

Table I2-4 CNTBaseN memory map

CntControlBase

Table I2-1 CNTControlBase memory map

CntCr

Counter Control Register

CntCtlBase

Table I2-3 CNTCTLBase memory map

CntEl0Acr

Counter-timer EL0 Access Control Register.

CntEl0Base

CntEl0Base frame is identical to the CntBase frame, except that CNTVOFF, CNTEL0ACR registers are never visible and CNTEL0ACR of the corresponding CntBase controls the access of the physical and virtual timer registers.

CntId

Counter Identification Register.

CntReadBase

Table I2-2 CNTReadBase memory map

CntSr

Counter Status Register

Features

Timer feature bits, defined at I5.7.16 CNTTIDR, Counter-timer Timer ID Register description.

GenericTimerCnt

Driver for the CNTBase timer block.

GenericTimerCntEl0

Driver for the CNTEL0Base timer block.

GenericTimerControl

Driver for the CNTControlBase block.

GenericTimerCtl

Driver for the CNTCTLBase block.

MmioTimer

TimerInterface implementation of the MMIO based physical or virtual timer instance of the CNTBase block.

TimerControl

Common control register of the physical and virtual timers. Defined at I5.7.10 CNTP_CTL, Counter-timer Physical Timer Control and at CNTV_CTL, Counter-timer Virtual Timer Control.

TimerRegs

Repeated subset of register that describe a physical or virtual timer in the CntBase or CntEl0Base blocks.