Expand description
§Arm CoreLink CCI-5x0 Cache Coherent Interconnect driver
Driver implementation for the CCI-500 and CCI-550 peripherals.
The Arm CCI-500 and CCI-550 interconnects enable coherent data sharing between multiple processor clusters and I/O coherency with peripherals, ensuring efficient memory access and system performance. The driver facilitates the components of the SoC to enter or exit coherency.
§Implemented features
- Enter and exit coherency
§License
The project is MIT and Apache-2.0 dual licensed, see LICENSE-APACHE
and LICENSE-MIT
.
§Maintainers
arm-cci is a trustedfirmware.org maintained project. All contributions are ultimately merged by the maintainers listed below.
- Bálint Dobszay balint.dobszay@arm.com balint-dobszay-arm
- Imre Kis imre.kis@arm.com imre-kis-arm
- Sandrine Afsa sandrine.afsa@arm.com sandrine-bailleux-arm
§Contributing
Please follow the directions of the Trusted Firmware Processes
Contributions are handled through review.trustedfirmware.org.
§Arm trademark notice
Arm is a registered trademark of Arm Limited (or its subsidiaries or affiliates).
This project uses some of the Arm product, service or technology trademarks, as listed in the Trademark List, in accordance with the Arm Trademark Use Guidelines.
Subsequent uses of these trademarks throughout this repository do not need to be prefixed with the Arm word trademark.
Copyright The arm-cci Contributors.
Structs§
- Cci5x0
- CCI-500/CCI-550 driver.
- Cci5x0
Registers - CCI-500/CCI-550 registers
- CciBase
Registers - CCI base registers
- CciMaster
Interface Monitor Registers - Master Interface Monitor Registers
- CciPerformance
Counter Registers - Performance counter registers
- CciSlave
Interface Monitor Registers - Slave Interface Monitor Registers
- CciSlave
Registers - Slave interface registers
- Control
Override Register - Control Override Register
- Secure
Access Register - Secure Access Register
- Snoop
Control Register - Snoop Control Register
- Status
Register - Status Register
- Unique
Mmio Pointer - A unique owned pointer to the registers of some MMIO device.