Crate andes_riscv 

Low level access to Andes’ AndeStar V5 RISC-V processors

Re-exports

pub use riscv;

Modules

dsp

Andes V5 DSP (P-extension) intrinsics — complete set.

l1c

L1C, level 1 cache

plic

register

The register module provides access to the processor’s registers