ambiq_apollo4p_pac/gpu/
interruptctrl.rs

1#[doc = "Register `INTERRUPTCTRL` reader"]
2pub type R = crate::R<InterruptctrlSpec>;
3#[doc = "Register `INTERRUPTCTRL` writer"]
4pub type W = crate::W<InterruptctrlSpec>;
5#[doc = "Field `IRQACTIVE` reader - if set to zero IRQ is active high, if set to one IRQ is active low"]
6pub type IrqactiveR = crate::BitReader;
7#[doc = "Field `IRQACTIVE` writer - if set to zero IRQ is active high, if set to one IRQ is active low"]
8pub type IrqactiveW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `INTCMDEND` reader - if set, signals interrupt at the end of command list"]
10pub type IntcmdendR = crate::BitReader;
11#[doc = "Field `INTCMDEND` writer - if set, signals interrupt at the end of command list"]
12pub type IntcmdendW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `INTDRAWEND` reader - if set, signals interrupt at the end of drawing command"]
14pub type IntdrawendR = crate::BitReader;
15#[doc = "Field `INTDRAWEND` writer - if set, signals interrupt at the end of drawing command"]
16pub type IntdrawendW<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `AUTOCLR` reader - if set, auto clears interrupt"]
18pub type AutoclrR = crate::BitReader;
19#[doc = "Field `AUTOCLR` writer - if set, auto clears interrupt"]
20pub type AutoclrW<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `RSVD` reader - This bitfield is reserved."]
22pub type RsvdR = crate::FieldReader<u32>;
23#[doc = "Field `RSVD` writer - This bitfield is reserved."]
24pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 26, u32>;
25#[doc = "Field `CHANGEFREQ` reader - change frequency of asynchronous clock"]
26pub type ChangefreqR = crate::FieldReader;
27#[doc = "Field `CHANGEFREQ` writer - change frequency of asynchronous clock"]
28pub type ChangefreqW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
29impl R {
30    #[doc = "Bit 0 - if set to zero IRQ is active high, if set to one IRQ is active low"]
31    #[inline(always)]
32    pub fn irqactive(&self) -> IrqactiveR {
33        IrqactiveR::new((self.bits & 1) != 0)
34    }
35    #[doc = "Bit 1 - if set, signals interrupt at the end of command list"]
36    #[inline(always)]
37    pub fn intcmdend(&self) -> IntcmdendR {
38        IntcmdendR::new(((self.bits >> 1) & 1) != 0)
39    }
40    #[doc = "Bit 2 - if set, signals interrupt at the end of drawing command"]
41    #[inline(always)]
42    pub fn intdrawend(&self) -> IntdrawendR {
43        IntdrawendR::new(((self.bits >> 2) & 1) != 0)
44    }
45    #[doc = "Bit 3 - if set, auto clears interrupt"]
46    #[inline(always)]
47    pub fn autoclr(&self) -> AutoclrR {
48        AutoclrR::new(((self.bits >> 3) & 1) != 0)
49    }
50    #[doc = "Bits 4:29 - This bitfield is reserved."]
51    #[inline(always)]
52    pub fn rsvd(&self) -> RsvdR {
53        RsvdR::new((self.bits >> 4) & 0x03ff_ffff)
54    }
55    #[doc = "Bits 30:31 - change frequency of asynchronous clock"]
56    #[inline(always)]
57    pub fn changefreq(&self) -> ChangefreqR {
58        ChangefreqR::new(((self.bits >> 30) & 3) as u8)
59    }
60}
61impl W {
62    #[doc = "Bit 0 - if set to zero IRQ is active high, if set to one IRQ is active low"]
63    #[inline(always)]
64    #[must_use]
65    pub fn irqactive(&mut self) -> IrqactiveW<InterruptctrlSpec> {
66        IrqactiveW::new(self, 0)
67    }
68    #[doc = "Bit 1 - if set, signals interrupt at the end of command list"]
69    #[inline(always)]
70    #[must_use]
71    pub fn intcmdend(&mut self) -> IntcmdendW<InterruptctrlSpec> {
72        IntcmdendW::new(self, 1)
73    }
74    #[doc = "Bit 2 - if set, signals interrupt at the end of drawing command"]
75    #[inline(always)]
76    #[must_use]
77    pub fn intdrawend(&mut self) -> IntdrawendW<InterruptctrlSpec> {
78        IntdrawendW::new(self, 2)
79    }
80    #[doc = "Bit 3 - if set, auto clears interrupt"]
81    #[inline(always)]
82    #[must_use]
83    pub fn autoclr(&mut self) -> AutoclrW<InterruptctrlSpec> {
84        AutoclrW::new(self, 3)
85    }
86    #[doc = "Bits 4:29 - This bitfield is reserved."]
87    #[inline(always)]
88    #[must_use]
89    pub fn rsvd(&mut self) -> RsvdW<InterruptctrlSpec> {
90        RsvdW::new(self, 4)
91    }
92    #[doc = "Bits 30:31 - change frequency of asynchronous clock"]
93    #[inline(always)]
94    #[must_use]
95    pub fn changefreq(&mut self) -> ChangefreqW<InterruptctrlSpec> {
96        ChangefreqW::new(self, 30)
97    }
98}
99#[doc = "On write, clears the IRQ (CHECK address!).\n\nYou can [`read`](crate::Reg::read) this register and get [`interruptctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interruptctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
100pub struct InterruptctrlSpec;
101impl crate::RegisterSpec for InterruptctrlSpec {
102    type Ux = u32;
103}
104#[doc = "`read()` method returns [`interruptctrl::R`](R) reader structure"]
105impl crate::Readable for InterruptctrlSpec {}
106#[doc = "`write(|w| ..)` method takes [`interruptctrl::W`](W) writer structure"]
107impl crate::Writable for InterruptctrlSpec {
108    type Safety = crate::Unsafe;
109    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
110    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
111}
112#[doc = "`reset()` method sets INTERRUPTCTRL to value 0"]
113impl crate::Resettable for InterruptctrlSpec {
114    const RESET_VALUE: u32 = 0;
115}
ambiq_apollo4p_pac/gpu/interruptctrl.rs

ambiq_apollo4p_pac/gpu/
interruptctrl.rs
