ambiq_apollo4p_pac/cpu/
cachectrl.rs

1#[doc = "Register `CACHECTRL` reader"]
2pub type R = crate::R<CachectrlSpec>;
3#[doc = "Register `CACHECTRL` writer"]
4pub type W = crate::W<CachectrlSpec>;
5#[doc = "Field `INVALIDATE` reader - Writing a 1 to this bitfield invalidates the CM4 cache contents."]
6pub type InvalidateR = crate::BitReader;
7#[doc = "Field `INVALIDATE` writer - Writing a 1 to this bitfield invalidates the CM4 cache contents."]
8pub type InvalidateW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Reset Cache Statistics. When written to a 1, the cache monitor counters will be cleared. The monitor counters can be reset only when the CACHECFG.ENABLE_MONITOR bit is set.\n\nValue on reset: 0"]
10#[derive(Clone, Copy, Debug, PartialEq, Eq)]
11pub enum Resetstat {
12    #[doc = "1: Clear Cache Stats"]
13    Clear = 1,
14    #[doc = "0: default Cache Stats"]
15    Default = 0,
16}
17impl From<Resetstat> for bool {
18    #[inline(always)]
19    fn from(variant: Resetstat) -> Self {
20        variant as u8 != 0
21    }
22}
23#[doc = "Field `RESETSTAT` reader - Reset Cache Statistics. When written to a 1, the cache monitor counters will be cleared. The monitor counters can be reset only when the CACHECFG.ENABLE_MONITOR bit is set."]
24pub type ResetstatR = crate::BitReader<Resetstat>;
25impl ResetstatR {
26    #[doc = "Get enumerated values variant"]
27    #[inline(always)]
28    pub const fn variant(&self) -> Resetstat {
29        match self.bits {
30            true => Resetstat::Clear,
31            false => Resetstat::Default,
32        }
33    }
34    #[doc = "Clear Cache Stats"]
35    #[inline(always)]
36    pub fn is_clear(&self) -> bool {
37        *self == Resetstat::Clear
38    }
39    #[doc = "default Cache Stats"]
40    #[inline(always)]
41    pub fn is_default(&self) -> bool {
42        *self == Resetstat::Default
43    }
44}
45#[doc = "Field `RESETSTAT` writer - Reset Cache Statistics. When written to a 1, the cache monitor counters will be cleared. The monitor counters can be reset only when the CACHECFG.ENABLE_MONITOR bit is set."]
46pub type ResetstatW<'a, REG> = crate::BitWriter<'a, REG, Resetstat>;
47impl<'a, REG> ResetstatW<'a, REG>
48where
49    REG: crate::Writable + crate::RegisterSpec,
50{
51    #[doc = "Clear Cache Stats"]
52    #[inline(always)]
53    pub fn clear(self) -> &'a mut crate::W<REG> {
54        self.variant(Resetstat::Clear)
55    }
56    #[doc = "default Cache Stats"]
57    #[inline(always)]
58    pub fn default(self) -> &'a mut crate::W<REG> {
59        self.variant(Resetstat::Default)
60    }
61}
62#[doc = "Field `CACHEREADY` reader - Cache Ready Status (enabled and not processing an invalidate operation)"]
63pub type CachereadyR = crate::BitReader;
64#[doc = "Field `CACHEREADY` writer - Cache Ready Status (enabled and not processing an invalidate operation)"]
65pub type CachereadyW<'a, REG> = crate::BitWriter<'a, REG>;
66impl R {
67    #[doc = "Bit 0 - Writing a 1 to this bitfield invalidates the CM4 cache contents."]
68    #[inline(always)]
69    pub fn invalidate(&self) -> InvalidateR {
70        InvalidateR::new((self.bits & 1) != 0)
71    }
72    #[doc = "Bit 1 - Reset Cache Statistics. When written to a 1, the cache monitor counters will be cleared. The monitor counters can be reset only when the CACHECFG.ENABLE_MONITOR bit is set."]
73    #[inline(always)]
74    pub fn resetstat(&self) -> ResetstatR {
75        ResetstatR::new(((self.bits >> 1) & 1) != 0)
76    }
77    #[doc = "Bit 2 - Cache Ready Status (enabled and not processing an invalidate operation)"]
78    #[inline(always)]
79    pub fn cacheready(&self) -> CachereadyR {
80        CachereadyR::new(((self.bits >> 2) & 1) != 0)
81    }
82}
83impl W {
84    #[doc = "Bit 0 - Writing a 1 to this bitfield invalidates the CM4 cache contents."]
85    #[inline(always)]
86    #[must_use]
87    pub fn invalidate(&mut self) -> InvalidateW<CachectrlSpec> {
88        InvalidateW::new(self, 0)
89    }
90    #[doc = "Bit 1 - Reset Cache Statistics. When written to a 1, the cache monitor counters will be cleared. The monitor counters can be reset only when the CACHECFG.ENABLE_MONITOR bit is set."]
91    #[inline(always)]
92    #[must_use]
93    pub fn resetstat(&mut self) -> ResetstatW<CachectrlSpec> {
94        ResetstatW::new(self, 1)
95    }
96    #[doc = "Bit 2 - Cache Ready Status (enabled and not processing an invalidate operation)"]
97    #[inline(always)]
98    #[must_use]
99    pub fn cacheready(&mut self) -> CachereadyW<CachectrlSpec> {
100        CachereadyW::new(self, 2)
101    }
102}
103#[doc = "Cache Control\n\nYou can [`read`](crate::Reg::read) this register and get [`cachectrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cachectrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
104pub struct CachectrlSpec;
105impl crate::RegisterSpec for CachectrlSpec {
106    type Ux = u32;
107}
108#[doc = "`read()` method returns [`cachectrl::R`](R) reader structure"]
109impl crate::Readable for CachectrlSpec {}
110#[doc = "`write(|w| ..)` method takes [`cachectrl::W`](W) writer structure"]
111impl crate::Writable for CachectrlSpec {
112    type Safety = crate::Unsafe;
113    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
114    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
115}
116#[doc = "`reset()` method sets CACHECTRL to value 0"]
117impl crate::Resettable for CachectrlSpec {
118    const RESET_VALUE: u32 = 0;
119}
ambiq_apollo4p_pac/cpu/cachectrl.rs

ambiq_apollo4p_pac/cpu/
cachectrl.rs
