Struct ambiq_apollo3p_pac::generic::W

pub struct W<U, REG> { /* fields omitted */ }

Register writer

Used as an argument to the closures in the write and modify methods of the register

Methods

impl<U, REG> W<U, REG>

pub unsafe fn bits(&mut self, bits: U) -> &mut Self

Writes raw bits to the register

impl W<u32, Reg<u32, _CFG>>

pub fn clksel(&mut self) -> CLKSEL_W

Bits 24:25 - Select the source and frequency for the ADC clock. All values not enumerated below are undefined.

pub fn trigpol(&mut self) -> TRIGPOL_W

Bit 19 - This bit selects the ADC trigger polarity for external off chip triggers.

pub fn trigsel(&mut self) -> TRIGSEL_W

Bits 16:18 - Select the ADC trigger source.

pub fn dfiforden(&mut self) -> DFIFORDEN_W

Bit 12 - Destructive FIFO Read Enable. Setting this will enable FIFO pop upon reading the FIFOPR register.

pub fn refsel(&mut self) -> REFSEL_W

Bits 8:9 - Select the ADC reference voltage.

pub fn ckmode(&mut self) -> CKMODE_W

Bit 4 - Clock mode register

pub fn lpmode(&mut self) -> LPMODE_W

Bit 3 - Select power mode to enter between active scans.

pub fn rpten(&mut self) -> RPTEN_W

Bit 2 - This bit enables Repeating Scan Mode.

pub fn adcen(&mut self) -> ADCEN_W

Bit 0 - This bit enables the ADC module. While the ADC is enabled, the ADCCFG and SLOT Configuration register settings must remain stable and unchanged. All configuration register settings, slot configuration settings and window comparison settings should be written prior to setting the ADCEN bit to '1'.

impl W<u32, Reg<u32, _STAT>>

pub fn pwdstat(&mut self) -> PWDSTAT_W

Bit 0 - Indicates the power-status of the ADC.

impl W<u32, Reg<u32, _SWT>>

pub fn swt(&mut self) -> SWT_W

Bits 0:7 - Writing 0x37 to this register generates a software trigger.

impl W<u32, Reg<u32, _SL0CFG>>

pub fn adsel0(&mut self) -> ADSEL0_W

Bits 24:26 - Select the number of measurements to average in the accumulate divide module for this slot.

pub fn prmode0(&mut self) -> PRMODE0_W

Bits 16:17 - Set the Precision Mode For Slot.

pub fn chsel0(&mut self) -> CHSEL0_W

Bits 8:11 - Select one of the 14 channel inputs for this slot.

pub fn wcen0(&mut self) -> WCEN0_W

Bit 1 - This bit enables the window compare function for slot 0.

pub fn slen0(&mut self) -> SLEN0_W

Bit 0 - This bit enables slot 0 for ADC conversions.

impl W<u32, Reg<u32, _SL1CFG>>

pub fn adsel1(&mut self) -> ADSEL1_W

Bits 24:26 - Select the number of measurements to average in the accumulate divide module for this slot.

pub fn prmode1(&mut self) -> PRMODE1_W

Bits 16:17 - Set the Precision Mode For Slot.

pub fn chsel1(&mut self) -> CHSEL1_W

Bits 8:11 - Select one of the 14 channel inputs for this slot.

pub fn wcen1(&mut self) -> WCEN1_W

Bit 1 - This bit enables the window compare function for slot 1.

pub fn slen1(&mut self) -> SLEN1_W

Bit 0 - This bit enables slot 1 for ADC conversions.

impl W<u32, Reg<u32, _SL2CFG>>

pub fn adsel2(&mut self) -> ADSEL2_W

Bits 24:26 - Select the number of measurements to average in the accumulate divide module for this slot.

pub fn prmode2(&mut self) -> PRMODE2_W

Bits 16:17 - Set the Precision Mode For Slot.

pub fn chsel2(&mut self) -> CHSEL2_W

Bits 8:11 - Select one of the 14 channel inputs for this slot.

pub fn wcen2(&mut self) -> WCEN2_W

Bit 1 - This bit enables the window compare function for slot 2.

pub fn slen2(&mut self) -> SLEN2_W

Bit 0 - This bit enables slot 2 for ADC conversions.

impl W<u32, Reg<u32, _SL3CFG>>

pub fn adsel3(&mut self) -> ADSEL3_W

Bits 24:26 - Select the number of measurements to average in the accumulate divide module for this slot.

pub fn prmode3(&mut self) -> PRMODE3_W

Bits 16:17 - Set the Precision Mode For Slot.

pub fn chsel3(&mut self) -> CHSEL3_W

Bits 8:11 - Select one of the 14 channel inputs for this slot.

pub fn wcen3(&mut self) -> WCEN3_W

Bit 1 - This bit enables the window compare function for slot 3.

pub fn slen3(&mut self) -> SLEN3_W

Bit 0 - This bit enables slot 3 for ADC conversions.

impl W<u32, Reg<u32, _SL4CFG>>

pub fn adsel4(&mut self) -> ADSEL4_W

Bits 24:26 - Select the number of measurements to average in the accumulate divide module for this slot.

pub fn prmode4(&mut self) -> PRMODE4_W

Bits 16:17 - Set the Precision Mode For Slot.

pub fn chsel4(&mut self) -> CHSEL4_W

Bits 8:11 - Select one of the 14 channel inputs for this slot.

pub fn wcen4(&mut self) -> WCEN4_W

Bit 1 - This bit enables the window compare function for slot 4.

pub fn slen4(&mut self) -> SLEN4_W

Bit 0 - This bit enables slot 4 for ADC conversions.

impl W<u32, Reg<u32, _SL5CFG>>

pub fn adsel5(&mut self) -> ADSEL5_W

Bits 24:26 - Select number of measurements to average in the accumulate divide module for this slot.

pub fn prmode5(&mut self) -> PRMODE5_W

Bits 16:17 - Set the Precision Mode For Slot.

pub fn chsel5(&mut self) -> CHSEL5_W

Bits 8:11 - Select one of the 14 channel inputs for this slot.

pub fn wcen5(&mut self) -> WCEN5_W

Bit 1 - This bit enables the window compare function for slot 5.

pub fn slen5(&mut self) -> SLEN5_W

Bit 0 - This bit enables slot 5 for ADC conversions.

impl W<u32, Reg<u32, _SL6CFG>>

pub fn adsel6(&mut self) -> ADSEL6_W

Bits 24:26 - Select the number of measurements to average in the accumulate divide module for this slot.

pub fn prmode6(&mut self) -> PRMODE6_W

Bits 16:17 - Set the Precision Mode For Slot.

pub fn chsel6(&mut self) -> CHSEL6_W

Bits 8:11 - Select one of the 14 channel inputs for this slot.

pub fn wcen6(&mut self) -> WCEN6_W

Bit 1 - This bit enables the window compare function for slot 6.

pub fn slen6(&mut self) -> SLEN6_W

Bit 0 - This bit enables slot 6 for ADC conversions.

impl W<u32, Reg<u32, _SL7CFG>>

pub fn adsel7(&mut self) -> ADSEL7_W

Bits 24:26 - Select the number of measurements to average in the accumulate divide module for this slot.

pub fn prmode7(&mut self) -> PRMODE7_W

Bits 16:17 - Set the Precision Mode For Slot.

pub fn chsel7(&mut self) -> CHSEL7_W

Bits 8:11 - Select one of the 14 channel inputs for this slot.

pub fn wcen7(&mut self) -> WCEN7_W

Bit 1 - This bit enables the window compare function for slot 7.

pub fn slen7(&mut self) -> SLEN7_W

Bit 0 - This bit enables slot 7 for ADC conversions.

impl W<u32, Reg<u32, _WULIM>>

pub fn ulim(&mut self) -> ULIM_W

Bits 0:19 - Sets the upper limit for the window comparator.

impl W<u32, Reg<u32, _WLLIM>>

pub fn llim(&mut self) -> LLIM_W

Bits 0:19 - Sets the lower limit for the window comparator.

impl W<u32, Reg<u32, _SCWLIM>>

pub fn scwlimen(&mut self) -> SCWLIMEN_W

Bit 0 - Scale the window limits compare values per precision mode. When set to 0x0 (default), the values in the 20-bit limits registers will compare directly with the FIFO values regardless of the precision mode the slot is configured to. When set to 0x1, the compare values will be divided by the difference in precision bits while performing the window limit comparisons.

impl W<u32, Reg<u32, _FIFO>>

pub fn rsvd(&mut self) -> RSVD_W

Bit 31 - RESERVED.

pub fn slotnum(&mut self) -> SLOTNUM_W

Bits 28:30 - Slot number associated with this FIFO data.

pub fn count(&mut self) -> COUNT_W

Bits 20:27 - Number of valid entries in the ADC FIFO.

pub fn data(&mut self) -> DATA_W

Bits 0:19 - Oldest data in the FIFO.

impl W<u32, Reg<u32, _FIFOPR>>

pub fn rsvdpr(&mut self) -> RSVDPR_W

Bit 31 - RESERVED.

pub fn slotnumpr(&mut self) -> SLOTNUMPR_W

Bits 28:30 - Slot number associated with this FIFO data.

pub fn count(&mut self) -> COUNT_W

Bits 20:27 - Number of valid entries in the ADC FIFO.

pub fn data(&mut self) -> DATA_W

Bits 0:19 - Oldest data in the FIFO.

impl W<u32, Reg<u32, _INTEN>>

pub fn derr(&mut self) -> DERR_W

Bit 7 - DMA Error Condition

pub fn dcmp(&mut self) -> DCMP_W

Bit 6 - DMA Transfer Complete

pub fn wcinc(&mut self) -> WCINC_W

Bit 5 - Window comparator voltage incursion interrupt.

pub fn wcexc(&mut self) -> WCEXC_W

Bit 4 - Window comparator voltage excursion interrupt.

pub fn fifoovr2(&mut self) -> FIFOOVR2_W

Bit 3 - FIFO 100 percent full interrupt.

pub fn fifoovr1(&mut self) -> FIFOOVR1_W

Bit 2 - FIFO 75 percent full interrupt.

pub fn scncmp(&mut self) -> SCNCMP_W

Bit 1 - ADC scan complete interrupt.

pub fn cnvcmp(&mut self) -> CNVCMP_W

Bit 0 - ADC conversion complete interrupt.

impl W<u32, Reg<u32, _INTSTAT>>

pub fn derr(&mut self) -> DERR_W

Bit 7 - DMA Error Condition

pub fn dcmp(&mut self) -> DCMP_W

Bit 6 - DMA Transfer Complete

pub fn wcinc(&mut self) -> WCINC_W

Bit 5 - Window comparator voltage incursion interrupt.

pub fn wcexc(&mut self) -> WCEXC_W

Bit 4 - Window comparator voltage excursion interrupt.

pub fn fifoovr2(&mut self) -> FIFOOVR2_W

Bit 3 - FIFO 100 percent full interrupt.

pub fn fifoovr1(&mut self) -> FIFOOVR1_W

Bit 2 - FIFO 75 percent full interrupt.

pub fn scncmp(&mut self) -> SCNCMP_W

Bit 1 - ADC scan complete interrupt.

pub fn cnvcmp(&mut self) -> CNVCMP_W

Bit 0 - ADC conversion complete interrupt.

impl W<u32, Reg<u32, _INTCLR>>

pub fn derr(&mut self) -> DERR_W

Bit 7 - DMA Error Condition

pub fn dcmp(&mut self) -> DCMP_W

Bit 6 - DMA Transfer Complete

pub fn wcinc(&mut self) -> WCINC_W

Bit 5 - Window comparator voltage incursion interrupt.

pub fn wcexc(&mut self) -> WCEXC_W

Bit 4 - Window comparator voltage excursion interrupt.

pub fn fifoovr2(&mut self) -> FIFOOVR2_W

Bit 3 - FIFO 100 percent full interrupt.

pub fn fifoovr1(&mut self) -> FIFOOVR1_W

Bit 2 - FIFO 75 percent full interrupt.

pub fn scncmp(&mut self) -> SCNCMP_W

Bit 1 - ADC scan complete interrupt.

pub fn cnvcmp(&mut self) -> CNVCMP_W

Bit 0 - ADC conversion complete interrupt.

impl W<u32, Reg<u32, _INTSET>>

pub fn derr(&mut self) -> DERR_W

Bit 7 - DMA Error Condition

pub fn dcmp(&mut self) -> DCMP_W

Bit 6 - DMA Transfer Complete

pub fn wcinc(&mut self) -> WCINC_W

Bit 5 - Window comparator voltage incursion interrupt.

pub fn wcexc(&mut self) -> WCEXC_W

Bit 4 - Window comparator voltage excursion interrupt.

pub fn fifoovr2(&mut self) -> FIFOOVR2_W

Bit 3 - FIFO 100 percent full interrupt.

pub fn fifoovr1(&mut self) -> FIFOOVR1_W

Bit 2 - FIFO 75 percent full interrupt.

pub fn scncmp(&mut self) -> SCNCMP_W

Bit 1 - ADC scan complete interrupt.

pub fn cnvcmp(&mut self) -> CNVCMP_W

Bit 0 - ADC conversion complete interrupt.

impl W<u32, Reg<u32, _DMATRIGEN>>

pub fn dfifofull(&mut self) -> DFIFOFULL_W

Bit 1 - Trigger DMA upon FIFO 100 percent Full

pub fn dfifo75(&mut self) -> DFIFO75_W

Bit 0 - Trigger DMA upon FIFO 75 percent Full

impl W<u32, Reg<u32, _DMATRIGSTAT>>

pub fn dfullstat(&mut self) -> DFULLSTAT_W

Bit 1 - Triggered DMA from FIFO 100 percent Full

pub fn d75stat(&mut self) -> D75STAT_W

Bit 0 - Triggered DMA from FIFO 75 percent Full

impl W<u32, Reg<u32, _DMACFG>>

pub fn dpwroff(&mut self) -> DPWROFF_W

Bit 18 - Power Off the ADC System upon DMACPL.

pub fn dmamsk(&mut self) -> DMAMSK_W

Bit 17 - Mask the FIFOCNT and SLOTNUM when transferring FIFO contents to memory

pub fn dmahonstat(&mut self) -> DMAHONSTAT_W

Bit 16 - Halt New ADC conversions until DMA Status DMAERR and DMACPL Cleared.

pub fn dmadynpri(&mut self) -> DMADYNPRI_W

Bit 9 - Enables dynamic priority based on FIFO fullness. When FIFO is full, priority is automatically set to HIGH. Otherwise, DMAPRI is used.

pub fn dmapri(&mut self) -> DMAPRI_W

Bit 8 - Sets the Priority of the DMA request

pub fn dmadir(&mut self) -> DMADIR_W

Bit 2 - Direction

pub fn dmaen(&mut self) -> DMAEN_W

Bit 0 - DMA Enable

impl W<u32, Reg<u32, _DMATOTCOUNT>>

pub fn totcount(&mut self) -> TOTCOUNT_W

Bits 2:17 - Total Transfer Count

impl W<u32, Reg<u32, _DMATARGADDR>>

pub fn utargaddr(&mut self) -> UTARGADDR_W

Bits 20:31 - SRAM Target

pub fn ltargaddr(&mut self) -> LTARGADDR_W

Bits 0:19 - DMA Target Address

impl W<u32, Reg<u32, _DMASTAT>>

pub fn dmaerr(&mut self) -> DMAERR_W

Bit 2 - DMA Error

pub fn dmacpl(&mut self) -> DMACPL_W

Bit 1 - DMA Transfer Complete

pub fn dmatip(&mut self) -> DMATIP_W

Bit 0 - DMA Transfer In Progress

impl W<u32, Reg<u32, _BBVALUE>>

pub fn pin(&mut self) -> PIN_W

Bits 16:23 - PIO values

pub fn dataout(&mut self) -> DATAOUT_W

Bits 0:7 - Data Output Values

impl W<u32, Reg<u32, _BBSETCLEAR>>

pub fn clear(&mut self) -> CLEAR_W

Bits 16:23 - Write 1 to clear PIO value

pub fn set(&mut self) -> SET_W

Bits 0:7 - Write 1 to set PIO value (set higher priority then clear if both bits are set)

impl W<u32, Reg<u32, _BBINPUT>>

pub fn datain(&mut self) -> DATAIN_W

Bits 0:7 - PIO values

impl W<u32, Reg<u32, _DEBUGDATA>>

pub fn debugdata(&mut self) -> DEBUGDATA_W

Bits 0:31 - Debug Data

impl W<u32, Reg<u32, _DEBUG>>

pub fn debugen(&mut self) -> DEBUGEN_W

Bits 0:3 - Debug Enable

impl W<u32, Reg<u32, _FIFO>>

pub fn fifo(&mut self) -> FIFO_W

Bits 0:31 - FIFO direct access. Only locations 0 - 3F will return valid information.

impl W<u32, Reg<u32, _FIFOPTR>>

pub fn fifo1rem(&mut self) -> FIFO1REM_W

Bits 24:31 - The number of remaining data bytes slots currently in FIFO 1 (written by interface, read by MCU)

pub fn fifo1siz(&mut self) -> FIFO1SIZ_W

Bits 16:23 - The number of valid data bytes currently in FIFO 1 (written by interface, read by MCU)

pub fn fifo0rem(&mut self) -> FIFO0REM_W

Bits 8:15 - The number of remaining data bytes slots currently in FIFO 0 (written by MCU, read by interface)

pub fn fifo0siz(&mut self) -> FIFO0SIZ_W

Bits 0:7 - The number of valid data bytes currently in the FIFO 0 (written by MCU, read by interface)

impl W<u32, Reg<u32, _FIFOTHR>>

pub fn fifowthr(&mut self) -> FIFOWTHR_W

Bits 8:13 - FIFO write threshold in bytes. A value of 0 will disable the write FIFO level from activating the threshold interrupt. If this field is non-zero, it will trigger a threshold interrupt when the write FIFO contains FIFOWTHR free bytes, as indicated by the FIFO0REM field. This is intended to signal when a transfer of FIFOWTHR bytes can be done from the host to the IOM write FIFO to support large IOM write operations.

pub fn fiforthr(&mut self) -> FIFORTHR_W

Bits 0:5 - FIFO read threshold in bytes. A value of 0 will disable the read FIFO level from activating the threshold interrupt. If this field is non-zero, it will trigger a threshold interrupt when the read FIFO contains FIFORTHR valid bytes of data, as indicated by the FIFO1SIZ field. This is intended to signal when a data transfer of FIFORTHR bytes can be done from the IOM module to the host via the read FIFO to support large IOM read operations.

impl W<u32, Reg<u32, _FIFOPOP>>

pub fn fifodout(&mut self) -> FIFODOUT_W

Bits 0:31 - This register will return the read data indicated by the current read pointer on reads. If the POPWR control bit in the FIFOCTRL register is reset (0), the FIFO read pointer will be advanced by one word as a result of the read. If the POPWR bit is set (1), the FIFO read pointer will only be advanced after a write operation to this register. The write data is ignored for this register. If less than a even word multiple is available, and the command is completed, the module will return the word containing these bytes and undetermined data in the unused fields of the word.

impl W<u32, Reg<u32, _FIFOPUSH>>

pub fn fifodin(&mut self) -> FIFODIN_W

Bits 0:31 - This register is used to write the FIFORAM in FIFO mode and will cause a push event to occur to the next open slot within the FIFORAM. Writing to this register will cause the write point to increment by 1 word(4 bytes).

impl W<u32, Reg<u32, _FIFOCTRL>>

pub fn fiforstn(&mut self) -> FIFORSTN_W

Bit 1 - Active low manual reset of the FIFO. Write to 0 to reset FIFO, and then write to 1 to remove the reset.

pub fn popwr(&mut self) -> POPWR_W

Bit 0 - Selects the mode in which 'pop' events are done for the FIFO read operations. A value of '1' will prevent a pop event on a read operation, and will require a write to the FIFOPOP register to create a pop event. A value of '0' in this register will allow a pop event to occur on the read of the FIFOPOP register, and may cause inadvertent FIFO pops when used in a debugging mode.

impl W<u32, Reg<u32, _FIFOLOC>>

pub fn fiforptr(&mut self) -> FIFORPTR_W

Bits 8:11 - Current FIFO read pointer. Used to index into the incoming FIFO (FIFO1), which is used to store read data returned from external devices during a read operation.

pub fn fifowptr(&mut self) -> FIFOWPTR_W

Bits 0:3 - Current FIFO write pointer. Value is the index into the outgoing FIFO (FIFO0), which is used during write operations to external devices.

impl W<u32, Reg<u32, _CLKCFG>>

pub fn div3(&mut self) -> DIV3_W

Bit 12 - Enable of the divide by 3 of the source IOCLK.

pub fn clk32ken(&mut self) -> CLK32KEN_W

Bit 11 - Enable for the 32Khz clock to the BLE module

pub fn fsel(&mut self) -> FSEL_W

Bits 8:10 - Select the input clock frequency.

pub fn ioclken(&mut self) -> IOCLKEN_W

Bit 0 - Enable for the interface clock. Must be enabled prior to executing any IO operations.

impl W<u32, Reg<u32, _CMD>>

pub fn offsetlo(&mut self) -> OFFSETLO_W

Bits 24:31 - This register holds the low order byte of offset to be used in the transaction. The number of offset bytes to use is set with bits 1:0 of the command. Offset bytes are transferred starting from the highest byte first.

pub fn cmdsel(&mut self) -> CMDSEL_W

Bits 20:21 - Command Specific selection information

pub fn tsize(&mut self) -> TSIZE_W

Bits 8:19 - Defines the transaction size in bytes. The offset transfer is not included in this size.

pub fn cont(&mut self) -> CONT_W

Bit 7 - Continue to hold the bus after the current transaction if set to a 1 with a new command issued.

pub fn offsetcnt(&mut self) -> OFFSETCNT_W

Bits 5:6 - Number of offset bytes to use for the command - 0, 1, 2, 3 are valid selections. The second (byte 1) and third byte (byte 2) are read from the OFFSETHI register, and the low order byte is pulled from this register in the OFFSETLO field. Offset bytes are transmitted highest byte first. E.g., if OFFSETCNT == 3, OFFSETHI[15:8] will be transmitted first, then OFFSETHI[7:0] then OFFSETLO. If OFFSETCNT == 2, OFFSETHI[7:0] will be transmitted, then OFFSETLO. If OFFSETCNT == 1, only OFFSETLO will be transmitted. Offset bytes are always transmitted MSB first, regardless of the value of the LSB control bit within the module configuration.

pub fn cmd(&mut self) -> CMD_W

Bits 0:4 - Command for submodule.

impl W<u32, Reg<u32, _CMDRPT>>

pub fn cmdrpt(&mut self) -> CMDRPT_W

Bits 0:4 - Count of number of times to repeat the next command.

impl W<u32, Reg<u32, _OFFSETHI>>

pub fn offsethi(&mut self) -> OFFSETHI_W

Bits 0:15 - Holds the high order bytes of the 2 or 3 byte offset phase of a transaction.

impl W<u32, Reg<u32, _CMDSTAT>>

pub fn ctsize(&mut self) -> CTSIZE_W

Bits 8:19 - The current number of bytes still to be transferred with this command. This field will count down to zero.

pub fn cmdstat(&mut self) -> CMDSTAT_W

Bits 5:7 - The current status of the command execution.

pub fn ccmd(&mut self) -> CCMD_W

Bits 0:4 - current command that is being executed

impl W<u32, Reg<u32, _INTEN>>

pub fn b2mshutdn(&mut self) -> B2MSHUTDN_W

Bit 16 - Revision A: The B2M_STATE from the BLE Core transitioned into shutdown state Revision B: Falling BLE Core Status signal. Asserted when the BLE_STATUS signal from the BLE Core is deasserted (1 -> 0)

pub fn b2mactive(&mut self) -> B2MACTIVE_W

Bit 15 - Revision A: The B2M_STATE from the BLE Core transitioned into the active state Revision B: Falling BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is deasserted (1 -> 0)

pub fn b2msleep(&mut self) -> B2MSLEEP_W

Bit 14 - The B2M_STATE from the BLE Core transitioned into the sleep state

pub fn cqerr(&mut self) -> CQERR_W

Bit 13 - Command queue error during processing. When an error occurs, the system will stop processing and halt operations to allow software to take recovery actions

pub fn cqupd(&mut self) -> CQUPD_W

Bit 12 - Command queue write operation executed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the CQ operation.

pub fn cqpaused(&mut self) -> CQPAUSED_W

Bit 11 - Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register, the mask is active in the CQIRQMASK field and the event occurs.

pub fn derr(&mut self) -> DERR_W

Bit 10 - DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified.

pub fn dcmp(&mut self) -> DCMP_W

Bit 9 - DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state

pub fn blecsstat(&mut self) -> BLECSSTAT_W

Bit 8 - BLE Core SPI Status interrupt. Asserted when the SPI_STATUS signal from the BLE Core is asserted, indicating that SPI writes can be done to the BLE Core. Transfers to the BLE Core should only be done when this signal is high.

pub fn blecirq(&mut self) -> BLECIRQ_W

Bit 7 - BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is asserted, indicating the availability of read data from the BLE Core.

pub fn icmd(&mut self) -> ICMD_W

Bit 6 - illegal command interrupt. Asserted when a command is written when an active command is in progress.

pub fn iacc(&mut self) -> IACC_W

Bit 5 - illegal FIFO access interrupt. Asserted when there is a overflow or underflow event

pub fn b2mst(&mut self) -> B2MST_W

Bit 4 - B2M State change interrupt. Asserted on any change in the B2M_STATE signal from the BLE Core.

pub fn fovfl(&mut self) -> FOVFL_W

Bit 3 - Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop.

pub fn fundfl(&mut self) -> FUNDFL_W

Bit 2 - Read FIFO Underflow interrupt. Asserted when a pop operation is done to a empty read FIFO.

pub fn thr(&mut self) -> THR_W

Bit 1 - FIFO Threshold interrupt. For write operations, asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field. For read operations, asserted when the number of valid bytes in the read FIFO equals of exceeds the value set in the RTHR field.

pub fn cmdcmp(&mut self) -> CMDCMP_W

Bit 0 - Command Complete interrupt. Asserted when the current operation has completed. For repeated commands, this will only be asserted when the final repeated command is completed.

impl W<u32, Reg<u32, _INTSTAT>>

pub fn b2mshutdn(&mut self) -> B2MSHUTDN_W

Bit 16 - Revision A: The B2M_STATE from the BLE Core transitioned into shutdown state Revision B: Falling BLE Core Status signal. Asserted when the BLE_STATUS signal from the BLE Core is deasserted (1 -> 0)

pub fn b2mactive(&mut self) -> B2MACTIVE_W

Bit 15 - Revision A: The B2M_STATE from the BLE Core transitioned into the active state Revision B: Falling BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is deasserted (1 -> 0)

pub fn b2msleep(&mut self) -> B2MSLEEP_W

Bit 14 - The B2M_STATE from the BLE Core transitioned into the sleep state

pub fn cqerr(&mut self) -> CQERR_W

Bit 13 - Command queue error during processing. When an error occurs, the system will stop processing and halt operations to allow software to take recovery actions

pub fn cqupd(&mut self) -> CQUPD_W

Bit 12 - Command queue write operation executed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the CQ operation.

pub fn cqpaused(&mut self) -> CQPAUSED_W

Bit 11 - Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register, the mask is active in the CQIRQMASK field and the event occurs.

pub fn derr(&mut self) -> DERR_W

Bit 10 - DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified.

pub fn dcmp(&mut self) -> DCMP_W

Bit 9 - DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state

pub fn blecsstat(&mut self) -> BLECSSTAT_W

Bit 8 - BLE Core SPI Status interrupt. Asserted when the SPI_STATUS signal from the BLE Core is asserted, indicating that SPI writes can be done to the BLE Core. Transfers to the BLE Core should only be done when this signal is high.

pub fn blecirq(&mut self) -> BLECIRQ_W

Bit 7 - BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is asserted, indicating the availability of read data from the BLE Core.

pub fn icmd(&mut self) -> ICMD_W

Bit 6 - illegal command interrupt. Asserted when a command is written when an active command is in progress.

pub fn iacc(&mut self) -> IACC_W

Bit 5 - illegal FIFO access interrupt. Asserted when there is a overflow or underflow event

pub fn b2mst(&mut self) -> B2MST_W

Bit 4 - B2M State change interrupt. Asserted on any change in the B2M_STATE signal from the BLE Core.

pub fn fovfl(&mut self) -> FOVFL_W

Bit 3 - Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop.

pub fn fundfl(&mut self) -> FUNDFL_W

Bit 2 - Read FIFO Underflow interrupt. Asserted when a pop operation is done to a empty read FIFO.

pub fn thr(&mut self) -> THR_W

Bit 1 - FIFO Threshold interrupt. For write operations, asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field. For read operations, asserted when the number of valid bytes in the read FIFO equals of exceeds the value set in the RTHR field.

pub fn cmdcmp(&mut self) -> CMDCMP_W

Bit 0 - Command Complete interrupt. Asserted when the current operation has completed. For repeated commands, this will only be asserted when the final repeated command is completed.

impl W<u32, Reg<u32, _INTCLR>>

pub fn b2mshutdn(&mut self) -> B2MSHUTDN_W

Bit 16 - Revision A: The B2M_STATE from the BLE Core transitioned into shutdown state Revision B: Falling BLE Core Status signal. Asserted when the BLE_STATUS signal from the BLE Core is deasserted (1 -> 0)

pub fn b2mactive(&mut self) -> B2MACTIVE_W

Bit 15 - Revision A: The B2M_STATE from the BLE Core transitioned into the active state Revision B: Falling BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is deasserted (1 -> 0)

pub fn b2msleep(&mut self) -> B2MSLEEP_W

Bit 14 - The B2M_STATE from the BLE Core transitioned into the sleep state

pub fn cqerr(&mut self) -> CQERR_W

Bit 13 - Command queue error during processing. When an error occurs, the system will stop processing and halt operations to allow software to take recovery actions

pub fn cqupd(&mut self) -> CQUPD_W

Bit 12 - Command queue write operation executed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the CQ operation.

pub fn cqpaused(&mut self) -> CQPAUSED_W

Bit 11 - Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register, the mask is active in the CQIRQMASK field and the event occurs.

pub fn derr(&mut self) -> DERR_W

Bit 10 - DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified.

pub fn dcmp(&mut self) -> DCMP_W

Bit 9 - DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state

pub fn blecsstat(&mut self) -> BLECSSTAT_W

Bit 8 - BLE Core SPI Status interrupt. Asserted when the SPI_STATUS signal from the BLE Core is asserted, indicating that SPI writes can be done to the BLE Core. Transfers to the BLE Core should only be done when this signal is high.

pub fn blecirq(&mut self) -> BLECIRQ_W

Bit 7 - BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is asserted, indicating the availability of read data from the BLE Core.

pub fn icmd(&mut self) -> ICMD_W

Bit 6 - illegal command interrupt. Asserted when a command is written when an active command is in progress.

pub fn iacc(&mut self) -> IACC_W

Bit 5 - illegal FIFO access interrupt. Asserted when there is a overflow or underflow event

pub fn b2mst(&mut self) -> B2MST_W

Bit 4 - B2M State change interrupt. Asserted on any change in the B2M_STATE signal from the BLE Core.

pub fn fovfl(&mut self) -> FOVFL_W

Bit 3 - Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop.

pub fn fundfl(&mut self) -> FUNDFL_W

Bit 2 - Read FIFO Underflow interrupt. Asserted when a pop operation is done to a empty read FIFO.

pub fn thr(&mut self) -> THR_W

Bit 1 - FIFO Threshold interrupt. For write operations, asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field. For read operations, asserted when the number of valid bytes in the read FIFO equals of exceeds the value set in the RTHR field.

pub fn cmdcmp(&mut self) -> CMDCMP_W

Bit 0 - Command Complete interrupt. Asserted when the current operation has completed. For repeated commands, this will only be asserted when the final repeated command is completed.

impl W<u32, Reg<u32, _INTSET>>

pub fn b2mshutdn(&mut self) -> B2MSHUTDN_W

Bit 16 - Revision A: The B2M_STATE from the BLE Core transitioned into shutdown state Revision B: Falling BLE Core Status signal. Asserted when the BLE_STATUS signal from the BLE Core is deasserted (1 -> 0)

pub fn b2mactive(&mut self) -> B2MACTIVE_W

Bit 15 - Revision A: The B2M_STATE from the BLE Core transitioned into the active state Revision B: Falling BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is deasserted (1 -> 0)

pub fn b2msleep(&mut self) -> B2MSLEEP_W

Bit 14 - The B2M_STATE from the BLE Core transitioned into the sleep state

pub fn cqerr(&mut self) -> CQERR_W

Bit 13 - Command queue error during processing. When an error occurs, the system will stop processing and halt operations to allow software to take recovery actions

pub fn cqupd(&mut self) -> CQUPD_W

Bit 12 - Command queue write operation executed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the CQ operation.

pub fn cqpaused(&mut self) -> CQPAUSED_W

Bit 11 - Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register, the mask is active in the CQIRQMASK field and the event occurs.

pub fn derr(&mut self) -> DERR_W

Bit 10 - DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified.

pub fn dcmp(&mut self) -> DCMP_W

Bit 9 - DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state

pub fn blecsstat(&mut self) -> BLECSSTAT_W

Bit 8 - BLE Core SPI Status interrupt. Asserted when the SPI_STATUS signal from the BLE Core is asserted, indicating that SPI writes can be done to the BLE Core. Transfers to the BLE Core should only be done when this signal is high.

pub fn blecirq(&mut self) -> BLECIRQ_W

Bit 7 - BLE Core IRQ signal. Asserted when the BLE_IRQ signal from the BLE Core is asserted, indicating the availability of read data from the BLE Core.

pub fn icmd(&mut self) -> ICMD_W

Bit 6 - illegal command interrupt. Asserted when a command is written when an active command is in progress.

pub fn iacc(&mut self) -> IACC_W

Bit 5 - illegal FIFO access interrupt. Asserted when there is a overflow or underflow event

pub fn b2mst(&mut self) -> B2MST_W

Bit 4 - B2M State change interrupt. Asserted on any change in the B2M_STATE signal from the BLE Core.

pub fn fovfl(&mut self) -> FOVFL_W

Bit 3 - Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop.

pub fn fundfl(&mut self) -> FUNDFL_W

Bit 2 - Read FIFO Underflow interrupt. Asserted when a pop operation is done to a empty read FIFO.

pub fn thr(&mut self) -> THR_W

Bit 1 - FIFO Threshold interrupt. For write operations, asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field. For read operations, asserted when the number of valid bytes in the read FIFO equals of exceeds the value set in the RTHR field.

pub fn cmdcmp(&mut self) -> CMDCMP_W

Bit 0 - Command Complete interrupt. Asserted when the current operation has completed. For repeated commands, this will only be asserted when the final repeated command is completed.

impl W<u32, Reg<u32, _DMATRIGEN>>

pub fn dthren(&mut self) -> DTHREN_W

Bit 1 - Trigger DMA upon THR level reached. For M2P DMA operations (IOM writes), the trigger will assert when the write FIFO has (WTHR/4) number of words free in the write FIFO, and will transfer (WTHR/4) number of words or, if the number of words left to transfer is less than the WTHR value, will transfer the remaining byte count. For P2M DMA operations, the trigger will assert when the read FIFO has (RTHR/4) words available in the read FIFO, and will transfer (RTHR/4) words to SRAM. This trigger will NOT assert when the transaction completes and there are less than RTHR bytes left in the FIFO, since the RTHR has not been reached. In this case, enabling the CMDCMP trigger will transfer the remaining data from the command. If the CMDCMP trigger is not enabled, the module will initiate a transfer when the amount of data in the FIFO is equal to or greater than the remaining data in the DMA. In cases where one DMA setup covers multiple commands, this will only occur at the end of the last transaction when the DMA is near complete.

pub fn dcmdcmpen(&mut self) -> DCMDCMPEN_W

Bit 0 - Trigger DMA upon command complete. Enables the trigger of the DMA when a command is completed. When this event is triggered, the number of words transferred will be the lesser of the remaining TOTCOUNT bytes, or the number of bytes in the FIFO when the command completed. If this is disabled, and the number of bytes in the FIFO is equal or greater than the TOTCOUNT bytes, a transfer of TOTCOUNT bytes will be done to ensure read data is stored when the DMA is completed.

impl W<u32, Reg<u32, _DMATRIGSTAT>>

pub fn dtotcmp(&mut self) -> DTOTCMP_W

Bit 2 - DMA triggered when DCMDCMP = 0, and the amount of data in the FIFO was enough to complete the DMA operation (greater than or equal to current TOTCOUNT) when the command completed. This trigger is default active when the DCMDCMP trigger is disabled and there is enough data in the FIFO to complete the DMA operation.

pub fn dthr(&mut self) -> DTHR_W

Bit 1 - Triggered DMA from THR event. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA.

pub fn dcmdcmp(&mut self) -> DCMDCMP_W

Bit 0 - Triggered DMA from Command complete event. Bit is read only and can be cleared by disabling the DCMDCMP trigger enable or by disabling DMA.

impl W<u32, Reg<u32, _DMACFG>>

pub fn dmapri(&mut self) -> DMAPRI_W

Bit 8 - Sets the Priority of the DMA request

pub fn dmadir(&mut self) -> DMADIR_W

Bit 1 - Direction

pub fn dmaen(&mut self) -> DMAEN_W

Bit 0 - DMA Enable. Setting this bit to EN will start the DMA operation. This should be the last DMA related register set prior to issuing the command

impl W<u32, Reg<u32, _DMATOTCOUNT>>

pub fn totcount(&mut self) -> TOTCOUNT_W

Bits 0:11 - Triggered DMA from Command complete event occurred. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA.

impl W<u32, Reg<u32, _DMATARGADDR>>

pub fn targaddr28(&mut self) -> TARGADDR28_W

Bit 28 - Bit 28 of the target byte address for source of DMA (either read or write). In cases of non-word aligned addresses, the DMA logic will take care for ensuring only the target bytes are read/written. Setting to '1' will select the SRAM. Setting to '0' will select the flash

pub fn targaddr(&mut self) -> TARGADDR_W

Bits 0:20 - Bits [19:0] of the target byte address for source of DMA (either read or write). The address can be any byte alignment, and does not have to be word aligned. In cases of non-word aligned addresses, the DMA logic will take care for ensuring only the target bytes are read/written.

impl W<u32, Reg<u32, _DMASTAT>>

pub fn dmaerr(&mut self) -> DMAERR_W

Bit 2 - DMA Error. This active high bit signals that an error was encountered during the DMA operation.

pub fn dmacpl(&mut self) -> DMACPL_W

Bit 1 - DMA Transfer Complete. This signals the end of the DMA operation. This bit can be cleared by writing to 0.

pub fn dmatip(&mut self) -> DMATIP_W

Bit 0 - DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data, transferring data, or waiting for priority. All of these will be indicated with a 1. A 0 will indicate that the DMA is fully complete and no further transactions will be done. This bit is read only.

impl W<u32, Reg<u32, _CQCFG>>

pub fn cqpri(&mut self) -> CQPRI_W

Bit 1 - Sets the Priority of the command queue DMA request.

pub fn cqen(&mut self) -> CQEN_W

Bit 0 - Command queue enable. When set, will enable the processing of the command queue and fetches of address/data pairs will proceed from the word address within the CQADDR register. Can be disabled using a CQ executed write to this bit as well.

impl W<u32, Reg<u32, _CQADDR>>

pub fn cqaddr28(&mut self) -> CQADDR28_W

Bit 28 - Bit 28 of target byte address for source of CQ (read only). Used to denote Flash (0) or SRAM (1) access

pub fn cqaddr(&mut self) -> CQADDR_W

Bits 2:20 - Bits 19:2 of target byte address for source of CQ (read only). The buffer must be aligned on a word boundary

impl W<u32, Reg<u32, _CQSTAT>>

pub fn cqerr(&mut self) -> CQERR_W

Bit 2 - Command queue processing error. This active high bit signals that an error was encountered during the CQ operation.

pub fn cqpaused(&mut self) -> CQPAUSED_W

Bit 1 - Command queue operation is currently paused.

pub fn cqtip(&mut self) -> CQTIP_W

Bit 0 - Command queue Transfer In Progress indicator. 1 will indicate that a CQ transfer is active and this will remain active even when paused waiting for external event.

impl W<u32, Reg<u32, _CQFLAGS>>

pub fn cqirqmask(&mut self) -> CQIRQMASK_W

Bits 16:31 - Provides for a per-bit mask of the flags used to invoke an interrupt. A '1' in the bit position will enable the pause event to trigger the interrupt, if the CQWT_int interrupt is enabled. Bits definitions are the same as CQPAUSE

pub fn cqflags(&mut self) -> CQFLAGS_W

Bits 0:15 - Current flag status (read-only). Bits [7:0] are software controllable and bits [15:8] are hardware status.

impl W<u32, Reg<u32, _CQSETCLEAR>>

pub fn cqfclr(&mut self) -> CQFCLR_W

Bits 16:23 - Clear CQFlag status bits. Will clear to 0 any SWFLAG with a '1' in the corresponding bit position of this field

pub fn cqftgl(&mut self) -> CQFTGL_W

Bits 8:15 - Toggle the indicated bit. Will toggle the value of any SWFLAG with a '1' in the corresponding bit position of this field

pub fn cqfset(&mut self) -> CQFSET_W

Bits 0:7 - Set CQFlag status bits. Will set to 1 the value of any SWFLAG with a '1' in the corresponding bit position of this field

impl W<u32, Reg<u32, _CQPAUSEEN>>

pub fn cqpen(&mut self) -> CQPEN_W

Bits 0:15 - Enables the specified event to pause command processing when active

impl W<u32, Reg<u32, _CQCURIDX>>

pub fn cqcuridx(&mut self) -> CQCURIDX_W

Bits 0:7 - Holds 8 bits of data that will be compared with the CQENDIX register field. If the values match, the IDXEQ pause event will be activated, which will cause the pausing of command queue operation if the IDXEQ bit is enabled in CQPAUSEEN.

impl W<u32, Reg<u32, _CQENDIDX>>

pub fn cqendidx(&mut self) -> CQENDIDX_W

Bits 0:7 - Holds 8 bits of data that will be compared with the CQCURIX register field. If the values match, the IDXEQ pause event will be activated, which will cause the pausing of command queue operation if the IDXEQ bit is enabled in CQPAUSEEN.

impl W<u32, Reg<u32, _STATUS>>

pub fn idlest(&mut self) -> IDLEST_W

Bit 2 - indicates if the active I/O state machine is IDLE. Note - The state machine could be in idle state due to hold-offs from data availability, or as the command gets propagated into the logic from the registers.

pub fn cmdact(&mut self) -> CMDACT_W

Bit 1 - Indicates if the active I/O Command is currently processing a transaction, or command is complete, but the FIFO pointers are still synchronizing internally. This bit will go high at the start of the transaction, and will go low when the command is complete, and the data and pointers within the FIFO have been synchronized.

pub fn err(&mut self) -> ERR_W

Bit 0 - Bit has been deprecated. Please refer to the other error indicators. This will always return 0.

impl W<u32, Reg<u32, _MSPICFG>>

pub fn mspirst(&mut self) -> MSPIRST_W

Bit 30 - Bit is deprecated. setting it will have no effect.

pub fn doutdly(&mut self) -> DOUTDLY_W

Bits 27:29 - Delay tap to use for the output signal (MOSI). This give more hold time on the output data.

pub fn dindly(&mut self) -> DINDLY_W

Bits 24:26 - Delay tap to use for the input signal (MISO). This gives more hold time on the input data.

pub fn spilsb(&mut self) -> SPILSB_W

Bit 23 - Selects data transfer as MSB first (0) or LSB first (1) for the data portion of the SPI transaction. The offset bytes are always transmitted MSB first.

pub fn rdfcpol(&mut self) -> RDFCPOL_W

Bit 22 - Selects the read flow control signal polarity. When set, the clock will be held low until the flow control is deasserted.

pub fn wtfcpol(&mut self) -> WTFCPOL_W

Bit 21 - Selects the write flow control signal polarity. The transfers are halted when the selected flow control signal is OPPOSITE polarity of this bit. (For example: WTFCPOL = 0 will allow a SPI_STATUS=1 to pause transfers).

pub fn rdfc(&mut self) -> RDFC_W

Bit 17 - Enables flow control of new read transactions based on the SPI_STATUS signal from the BLE Core.

pub fn wtfc(&mut self) -> WTFC_W

Bit 16 - Enables flow control of new write transactions based on the SPI_STATUS signal from the BLE Core.

pub fn fulldup(&mut self) -> FULLDUP_W

Bit 2 - Full Duplex mode. Capture read data during writes operations

pub fn spha(&mut self) -> SPHA_W

Bit 1 - Selects the SPI phase; When 1, will shift the sampling edge by 1/2 clock.

pub fn spol(&mut self) -> SPOL_W

Bit 0 - This bit selects SPI polarity.

impl W<u32, Reg<u32, _BLECFG>>

pub fn spiisoctl(&mut self) -> SPIISOCTL_W

Bits 14:15 - Configuration of BLEH isolation controls for SPI related signals.

pub fn pwrisoctl(&mut self) -> PWRISOCTL_W

Bits 12:13 - Configuration of BLEH isolation control for power related signals.

pub fn stayasleep(&mut self) -> STAYASLEEP_W

Bit 11 - Set to prevent the BLE power control module from waking up the BLE Core after going into power down. To be used for graceful shutdown, set by software prior to powering off and will allow assertion of reset from sleep state.

pub fn frcclk(&mut self) -> FRCCLK_W

Bit 10 - Force the clock in the BLEIF to be always running

pub fn mcufrcslp(&mut self) -> MCUFRCSLP_W

Bit 9 - Force power state machine to go to the sleep state. Intended for debug only. Has no effect on the actual BLE Core state, only the state of the BLEIF interface state machine.

pub fn wt4actoff(&mut self) -> WT4ACTOFF_W

Bit 8 - Debug control of BLEIF power state machine. Allows transition into the active state in the BLEIF state without waiting for DCDC request from BLE Core.

pub fn blehreqctl(&mut self) -> BLEHREQCTL_W

Bits 6:7 - BLEH power on request override. The value of this field will be sent to the BLE Core when the PWRSM is off. Otherwise, the value is supplied from internal logic.

pub fn dcdcflgctl(&mut self) -> DCDCFLGCTL_W

Bits 4:5 - DCDCFLG signal override. The value of this field will be sent to the BLE Core when the PWRSM is off. Otherwise, the value is supplied from internal logic.

pub fn wakeupctl(&mut self) -> WAKEUPCTL_W

Bits 2:3 - WAKE signal override. Controls the source of the WAKE signal to the BLE Core.

pub fn blerstn(&mut self) -> BLERSTN_W

Bit 1 - Reset line to the BLE Core. This will reset the BLE core when asserted ('0') and must be written to '1' prior to performing any BTLE related operations to the core.

pub fn pwrsmen(&mut self) -> PWRSMEN_W

Bit 0 - Enable the power state machine for automatic sequencing and control of power states of the BLE Core module.

impl W<u32, Reg<u32, _PWRCMD>>

pub fn restart(&mut self) -> RESTART_W

Bit 1 - Restart the BLE Core after going into the shutdown state. Only valid when in the shutdown state.

pub fn wakereq(&mut self) -> WAKEREQ_W

Bit 0 - Wake request from the MCU. When asserted (1), the BLE Interface logic will assert the wakeup request signal to the BLE Core. Only recognized when in the sleep state

impl W<u32, Reg<u32, _BSTATUS>>

pub fn blehreq(&mut self) -> BLEHREQ_W

Bit 12 - Value of the BLEHREQ signal to the power control unit. The BLEHREQ signal is sent from the BLEIF module to the power control module to request the BLEH power up. When the BLEHACK signal is asserted, BLEH power is stable and ready for use.

pub fn blehack(&mut self) -> BLEHACK_W

Bit 11 - Value of the BLEHACK signal from the power control unit. If the signal is '1', the BLEH power is active and ready for use.

pub fn pwrst(&mut self) -> PWRST_W

Bits 8:10 - Current status of the power state machine

pub fn bleirq(&mut self) -> BLEIRQ_W

Bit 7 - Status of the BLEIRQ signal from the BLE Core. A value of 1 indicates that read data is available in the core and a read operation needs to be performed.

pub fn wakeup(&mut self) -> WAKEUP_W

Bit 6 - Value of the WAKEUP signal to the BLE Core . The WAKEUP signals is sent from the BLEIF to the BLECORE to request the BLE Core transition from sleep state to active state.

pub fn dcdcflag(&mut self) -> DCDCFLAG_W

Bit 5 - Value of the DCDCFLAG signal to the BLE Core. The DCDCFLAG is a signal to the BLE Core indicating that the BLEH power is active.

pub fn dcdcreq(&mut self) -> DCDCREQ_W

Bit 4 - Value of the DCDCREQ signal from the BLE Core. The DCDCREQ signal is sent from the core to the BLEIF module when the BLE core requires BLEH power to be active. When activated, this is indicated by DCDCFLAG going to 1.

pub fn spistatus(&mut self) -> SPISTATUS_W

Bit 3 - Value of the SPISTATUS signal from the BLE Core. The signal is asserted when the BLE Core is able to accept write data via the SPI interface. Data should be transmitted to the BLE core only when this signal is 1. The hardware will automatically wait for this signal prior to performing a write operation if flow control is active.

pub fn b2mstate(&mut self) -> B2MSTATE_W

Bits 0:2 - State of the BLE Core logic.

impl W<u32, Reg<u32, _BLEDBG>>

pub fn dbgdata(&mut self) -> DBGDATA_W

Bits 3:31 - Debug data

pub fn apbclkon(&mut self) -> APBCLKON_W

Bit 2 - APBCLK debug clock control. Enable APB_CLK to be active when this bit is '1'. Otherwise, the clock is controlled with gating from the logic as needed.

pub fn ioclkon(&mut self) -> IOCLKON_W

Bit 1 - IOCLK debug clock control. Enable IO_CLK to be active when this bit is '1'. Otherwise, the clock is controlled with gating from the logic as needed.

pub fn dbgen(&mut self) -> DBGEN_W

Bit 0 - Debug Enable. Setting this bit will enable the update of data within this register, otherwise it is clock gated for power savings

impl W<u32, Reg<u32, _CACHECFG>>

pub fn enable_monitor(&mut self) -> ENABLE_MONITOR_W

Bit 24 - Enable Cache Monitoring Stats. Cache monitoring consumes additional power and should only be enabled when profiling code and counters will increment when this bit is set. Counter values will be retained when this is set to 0, allowing software to enable/disable counting for multiple code segments.

pub fn data_clkgate(&mut self) -> DATA_CLKGATE_W

Bit 20 - Enable aggressive clock gating of entire data array. This bit should be set to 1 for optimal power efficiency.

pub fn cache_ls(&mut self) -> CACHE_LS_W

Bit 11 - Enable LS (light sleep) of cache RAMs. Software should DISABLE this bit since cache activity is too high to benefit from LS usage.

pub fn cache_clkgate(&mut self) -> CACHE_CLKGATE_W

Bit 10 - Enable clock gating of cache TAG RAM. Software should enable this bit for optimal power efficiency.

pub fn dcache_enable(&mut self) -> DCACHE_ENABLE_W

Bit 9 - Enable FLASH Data Caching

pub fn icache_enable(&mut self) -> ICACHE_ENABLE_W

Bit 8 - Enable FLASH Instruction Caching

pub fn config(&mut self) -> CONFIG_W

Bits 4:7 - Sets the cache configuration

pub fn enable_nc1(&mut self) -> ENABLE_NC1_W

Bit 3 - Enable Non-cacheable region 1. See NCR1 registers to define the region.

pub fn enable_nc0(&mut self) -> ENABLE_NC0_W

Bit 2 - Enable Non-cacheable region 0. See NCR0 registers to define the region.

pub fn lru(&mut self) -> LRU_W

Bit 1 - Sets the cache replacement policy. 0=LRR (least recently replaced), 1=LRU (least recently used). LRR minimizes writes to the TAG SRAM.

pub fn enable(&mut self) -> ENABLE_W

Bit 0 - Enables the FLASH cache controller and enables power to the cache SRAMs. The ICACHE_ENABLE and DCACHE_ENABLE should be set to enable caching for each type of access.

impl W<u32, Reg<u32, _CTRL>>

pub fn flash3_slm_enable(&mut self) -> FLASH3_SLM_ENABLE_W

Bit 18 - Enable FLASH Sleep Mode. Write to 1 to put FLASH1 into sleep mode. NOTE: there is a 5 us latency after waking FLASH until the first access will be returned.

pub fn flash3_slm_disable(&mut self) -> FLASH3_SLM_DISABLE_W

Bit 17 - Disable FLASH Sleep Mode. Write 1 to wake FLASH1 from sleep mode (reading the array will also automatically wake it).

pub fn flash3_slm_status(&mut self) -> FLASH3_SLM_STATUS_W

Bit 16 - FLASH Sleep Mode Status. 1 indicates that FLASH1 is in sleep mode, 0 indicates FLASH1 is in normal mode.

pub fn flash2_slm_enable(&mut self) -> FLASH2_SLM_ENABLE_W

Bit 14 - Enable FLASH Sleep Mode. Write to 1 to put FLASH1 into sleep mode. NOTE: there is a 5 us latency after waking FLASH until the first access will be returned.

pub fn flash2_slm_disable(&mut self) -> FLASH2_SLM_DISABLE_W

Bit 13 - Disable FLASH Sleep Mode. Write 1 to wake FLASH2 from sleep mode (reading the array will also automatically wake it).

pub fn flash2_slm_status(&mut self) -> FLASH2_SLM_STATUS_W

Bit 12 - FLASH Sleep Mode Status. 1 indicates that FLASH2 is in sleep mode, 0 indicates FLASH2 is in normal mode.

pub fn flash1_slm_enable(&mut self) -> FLASH1_SLM_ENABLE_W

Bit 10 - Enable FLASH Sleep Mode. Write to 1 to put FLASH1 into sleep mode. NOTE: there is a 5 us latency after waking FLASH until the first access will be returned.

pub fn flash1_slm_disable(&mut self) -> FLASH1_SLM_DISABLE_W

Bit 9 - Disable FLASH Sleep Mode. Write 1 to wake FLASH1 from sleep mode (reading the array will also automatically wake it).

pub fn flash1_slm_status(&mut self) -> FLASH1_SLM_STATUS_W

Bit 8 - FLASH Sleep Mode Status. 1 indicates that FLASH1 is in sleep mode, 0 indicates FLASH1 is in normal mode.

pub fn flash0_slm_enable(&mut self) -> FLASH0_SLM_ENABLE_W

Bit 6 - Enable FLASH Sleep Mode. Write to 1 to put FLASH0 into sleep mode. NOTE: there is a 5 us latency after waking FLASH until the first access will be returned.

pub fn flash0_slm_disable(&mut self) -> FLASH0_SLM_DISABLE_W

Bit 5 - Disable FLASH Sleep Mode. Write 1 to wake FLASH0 from sleep mode (reading the array will also automatically wake it).

pub fn flash0_slm_status(&mut self) -> FLASH0_SLM_STATUS_W

Bit 4 - FLASH Sleep Mode Status. 1 indicates that FLASH0 is in sleep mode, 0 indicates FLASH0 is in normal mode.

pub fn cache_ready(&mut self) -> CACHE_READY_W

Bit 2 - Cache Ready Status (enabled and not processing an invalidate operation)

pub fn reset_stat(&mut self) -> RESET_STAT_W

Bit 1 - Reset Cache Statistics. When written to a 1, the cache monitor counters will be cleared. The monitor counters can be reset only when the CACHECFG.ENABLE_MONITOR bit is set.

pub fn invalidate(&mut self) -> INVALIDATE_W

Bit 0 - Writing a 1 to this bit field invalidates the FLASH cache contents.

impl W<u32, Reg<u32, _NCR0START>>

pub fn addr(&mut self) -> ADDR_W

Bits 4:26 - Start address for non-cacheable region 0

impl W<u32, Reg<u32, _NCR0END>>

pub fn addr(&mut self) -> ADDR_W

Bits 4:26 - End address for non-cacheable region 0

impl W<u32, Reg<u32, _NCR1START>>

pub fn addr(&mut self) -> ADDR_W

Bits 4:26 - Start address for non-cacheable region 1

impl W<u32, Reg<u32, _NCR1END>>

pub fn addr(&mut self) -> ADDR_W

Bits 4:26 - End address for non-cacheable region 1

impl W<u32, Reg<u32, _DMON0>>

pub fn daccess_count(&mut self) -> DACCESS_COUNT_W

Bits 0:31 - Total accesses to data cache. All performance metrics should be relative to the number of accesses performed.

impl W<u32, Reg<u32, _DMON1>>

pub fn dlookup_count(&mut self) -> DLOOKUP_COUNT_W

Bits 0:31 - Total tag lookups from data cache.

impl W<u32, Reg<u32, _DMON2>>

pub fn dhit_count(&mut self) -> DHIT_COUNT_W

Bits 0:31 - Cache hits from lookup operations.

impl W<u32, Reg<u32, _DMON3>>

pub fn dline_count(&mut self) -> DLINE_COUNT_W

Bits 0:31 - Cache hits from line cache

impl W<u32, Reg<u32, _IMON0>>

pub fn iaccess_count(&mut self) -> IACCESS_COUNT_W

Bits 0:31 - Total accesses to Instruction cache

impl W<u32, Reg<u32, _IMON1>>

pub fn ilookup_count(&mut self) -> ILOOKUP_COUNT_W

Bits 0:31 - Total tag lookups from Instruction cache

impl W<u32, Reg<u32, _IMON2>>

pub fn ihit_count(&mut self) -> IHIT_COUNT_W

Bits 0:31 - Cache hits from lookup operations

impl W<u32, Reg<u32, _IMON3>>

pub fn iline_count(&mut self) -> ILINE_COUNT_W

Bits 0:31 - Cache hits from line cache

impl W<u32, Reg<u32, _FLASH0CFG>>

pub fn lpmmode0(&mut self) -> LPMMODE0_W

Bits 12:13 - Controls FLASH low power modes (control of LPM pin).

pub fn lpmrdwait0(&mut self) -> LPMRDWAIT0_W

Bits 8:11 - Sets FLASH wait states when in LPM Mode 2 (RD_WAIT in LPM mode 2 only)

pub fn sedelay0(&mut self) -> SEDELAY0_W

Bits 4:6 - Sets SE delay (FLASH address setup). A value of 5 is recommended.

pub fn rdwait0(&mut self) -> RDWAIT0_W

Bits 0:3 - Sets read wait states for normal (fast) operation. A value of 1 is recommended.

impl W<u32, Reg<u32, _FLASH1CFG>>

pub fn lpmmode1(&mut self) -> LPMMODE1_W

Bits 12:13 - Controls FLASH low power modes (control of LPM pin).

pub fn lpmrdwait1(&mut self) -> LPMRDWAIT1_W

Bits 8:11 - Sets FLASH wait states when in LPM Mode 2 (RD_WAIT in LPM mode 2 only)

pub fn sedelay1(&mut self) -> SEDELAY1_W

Bits 4:6 - Sets SE delay (FLASH address setup). A value of 5 is recommended.

pub fn rdwait1(&mut self) -> RDWAIT1_W

Bits 0:3 - Sets read wait states for normal (fast) operation. A value of 1 is recommended.

impl W<u32, Reg<u32, _FLASH2CFG>>

pub fn lpmmode2(&mut self) -> LPMMODE2_W

Bits 12:13 - Controls FLASH low power modes (control of LPM pin).

pub fn lpmrdwait2(&mut self) -> LPMRDWAIT2_W

Bits 8:11 - Sets FLASH wait states when in LPM Mode 2 (RD_WAIT in LPM mode 2 only)

pub fn sedelay2(&mut self) -> SEDELAY2_W

Bits 4:6 - Sets SE delay (FLASH address setup). A value of 5 is recommended.

pub fn rdwait2(&mut self) -> RDWAIT2_W

Bits 0:3 - Sets read wait states for normal (fast) operation. A value of 1 is recommended.

impl W<u32, Reg<u32, _FLASH3CFG>>

pub fn lpmmode3(&mut self) -> LPMMODE3_W

Bits 12:13 - Controls FLASH low power modes (control of LPM pin).

pub fn lpmrdwait3(&mut self) -> LPMRDWAIT3_W

Bits 8:11 - Sets FLASH wait states when in LPM Mode 2 (RD_WAIT in LPM mode 2 only)

pub fn sedelay3(&mut self) -> SEDELAY3_W

Bits 4:6 - Sets SE delay (FLASH address setup). A value of 5 is recommended.

pub fn rdwait3(&mut self) -> RDWAIT3_W

Bits 0:3 - Sets read wait states for normal (fast) operation. A value of 1 is recommended.

impl W<u32, Reg<u32, _CALXT>>

pub fn calxt(&mut self) -> CALXT_W

Bits 0:10 - XT Oscillator calibration value. This register will enable the hardware to increase or decrease the number of cycles in a 16KHz clock derived from the original 32KHz version. The most significant bit is the sign. A '1' is a reduction, and a '0' is an addition. This calibration value will add or reduce the number of cycles programmed here across a 32 second interval. The maximum value that is effective is from -1024 to 1023.

impl W<u32, Reg<u32, _CALRC>>

pub fn calrc(&mut self) -> CALRC_W

Bits 0:17 - LFRC Oscillator calibration value. This register will enable the hardware to increase or decrease the number of cycles in a 512 Hz clock derived from the original 1024 version. The most significant bit is the sign. A '1' is a reduction, and a '0' is an addition. This calibration value will add or reduce the number of cycles programmed here across a 32 second interval. The range is from -131072 (decimal) to 131071 (decimal). This register is normally used in conjunction with ACALCTR register. The CALRC register will load the ACALCTR register (bits 17:0) if the ACALCTR register is set to measure the LFRC with the XT clock.

impl W<u32, Reg<u32, _ACALCTR>>

pub fn acalctr(&mut self) -> ACALCTR_W

Bits 0:23 - Autocalibration Counter result. Bits 17 down to 0 of this is feed directly to the CALRC register if ACAL register in OCTRL register is set to 1024SEC or 512SEC.

impl W<u32, Reg<u32, _OCTRL>>

pub fn acal(&mut self) -> ACAL_W

Bits 8:10 - Autocalibration control. This selects the source to be used in the autocalibration flow. This flow can also be used to measure an internal clock against an external clock source, with the external clock normally used as the reference.

pub fn osel(&mut self) -> OSEL_W

Bit 7 - Selects the RTC oscillator (1 => LFRC, 0 => XT)

pub fn fos(&mut self) -> FOS_W

Bit 6 - Oscillator switch on failure function. If this is set, then LFRC clock source will switch from XT to RC.

pub fn stoprc(&mut self) -> STOPRC_W

Bit 1 - Stop the LFRC Oscillator to the RTC

pub fn stopxt(&mut self) -> STOPXT_W

Bit 0 - Stop the XT Oscillator to the RTC

impl W<u32, Reg<u32, _CLKOUT>>

pub fn cken(&mut self) -> CKEN_W

Bit 7 - Enable the CLKOUT signal

pub fn cksel(&mut self) -> CKSEL_W

Bits 0:5 - CLKOUT signal select

impl W<u32, Reg<u32, _CLKKEY>>

pub fn clkkey(&mut self) -> CLKKEY_W

Bits 0:31 - Key register value.

impl W<u32, Reg<u32, _CCTRL>>

pub fn coresel(&mut self) -> CORESEL_W

Bit 0 - Core Clock divisor

impl W<u32, Reg<u32, _STATUS>>

pub fn oscf(&mut self) -> OSCF_W

Bit 1 - XT Oscillator is enabled but not oscillating

pub fn omode(&mut self) -> OMODE_W

Bit 0 - Current RTC oscillator (1 => LFRC, 0 => XT). After an RTC oscillator change, it may take up to 2 seconds for this field to reflect the new oscillator.

impl W<u32, Reg<u32, _HFADJ>>

pub fn hfadjgain(&mut self) -> HFADJGAIN_W

Bits 21:23 - Gain control for HFRC adjustment

pub fn hfwarmup(&mut self) -> HFWARMUP_W

Bit 20 - XT warm-up period for HFRC adjustment

pub fn hfxtadj(&mut self) -> HFXTADJ_W

Bits 8:19 - Target HFRC adjustment value.

pub fn hfadjck(&mut self) -> HFADJCK_W

Bits 1:3 - Repeat period for HFRC adjustment

pub fn hfadjen(&mut self) -> HFADJEN_W

Bit 0 - HFRC adjustment control

impl W<u32, Reg<u32, _CLOCKENSTAT>>

pub fn clockenstat(&mut self) -> CLOCKENSTAT_W

Bits 0:31 - Clock enable status

impl W<u32, Reg<u32, _CLOCKEN2STAT>>

pub fn clocken2stat(&mut self) -> CLOCKEN2STAT_W

Bits 0:31 - Clock enable status 2

impl W<u32, Reg<u32, _CLOCKEN3STAT>>

pub fn clocken3stat(&mut self) -> CLOCKEN3STAT_W

Bits 0:31 - Clock enable status 3

impl W<u32, Reg<u32, _FREQCTRL>>

pub fn burststatus(&mut self) -> BURSTSTATUS_W

Bit 2 - This represents frequency burst status.

pub fn burstack(&mut self) -> BURSTACK_W

Bit 1 - Frequency Burst Request Acknowledge. Frequency burst requested is always acknowledged whether burst is granted or not depending on feature enable.

pub fn burstreq(&mut self) -> BURSTREQ_W

Bit 0 - Frequency Burst Enable Request

impl W<u32, Reg<u32, _BLEBUCKTONADJ>>

pub fn zerolendetecten(&mut self) -> ZEROLENDETECTEN_W

Bit 27 - BLEBUCK ZERO LENGTH DETECT ENABLE

pub fn zerolendetecttrim(&mut self) -> ZEROLENDETECTTRIM_W

Bits 23:26 - BLEBUCK ZERO LENGTH DETECT TRIM

pub fn tonadjusten(&mut self) -> TONADJUSTEN_W

Bit 22 - TON ADJUST ENABLE

pub fn tonadjustperiod(&mut self) -> TONADJUSTPERIOD_W

Bits 20:21 - TON ADJUST PERIOD

pub fn tonhighthreshold(&mut self) -> TONHIGHTHRESHOLD_W

Bits 10:19 - TON ADJUST HIGH THRESHOLD. Suggested values are #15(94KHz) #2A(47Khz) #A6(12Khz) #29A(3Khz)

pub fn tonlowthreshold(&mut self) -> TONLOWTHRESHOLD_W

Bits 0:9 - TON ADJUST LOW THRESHOLD. Suggested values are #A(94KHz) #15(47KHz) #53(12Khz) #14D(3Khz)

impl W<u32, Reg<u32, _INTRPTEN>>

pub fn of(&mut self) -> OF_W

Bit 2 - XT Oscillator Fail interrupt

pub fn acc(&mut self) -> ACC_W

Bit 1 - Autocalibration Complete interrupt

pub fn acf(&mut self) -> ACF_W

Bit 0 - Autocalibration Fail interrupt

impl W<u32, Reg<u32, _INTRPTSTAT>>

pub fn of(&mut self) -> OF_W

Bit 2 - XT Oscillator Fail interrupt

pub fn acc(&mut self) -> ACC_W

Bit 1 - Autocalibration Complete interrupt

pub fn acf(&mut self) -> ACF_W

Bit 0 - Autocalibration Fail interrupt

impl W<u32, Reg<u32, _INTRPTCLR>>

pub fn of(&mut self) -> OF_W

Bit 2 - XT Oscillator Fail interrupt

pub fn acc(&mut self) -> ACC_W

Bit 1 - Autocalibration Complete interrupt

pub fn acf(&mut self) -> ACF_W

Bit 0 - Autocalibration Fail interrupt

impl W<u32, Reg<u32, _INTRPTSET>>

pub fn of(&mut self) -> OF_W

Bit 2 - XT Oscillator Fail interrupt

pub fn acc(&mut self) -> ACC_W

Bit 1 - Autocalibration Complete interrupt

pub fn acf(&mut self) -> ACF_W

Bit 0 - Autocalibration Fail interrupt

impl W<u32, Reg<u32, _TMR0>>

pub fn cttmrb0(&mut self) -> CTTMRB0_W

Bits 16:31 - Counter/Timer B0.

pub fn cttmra0(&mut self) -> CTTMRA0_W

Bits 0:15 - Counter/Timer A0.

impl W<u32, Reg<u32, _CMPRA0>>

pub fn cmpr1a0(&mut self) -> CMPR1A0_W

Bits 16:31 - Counter/Timer A0 Compare Register 1. Holds the upper limit for timer half A.

pub fn cmpr0a0(&mut self) -> CMPR0A0_W

Bits 0:15 - Counter/Timer A0 Compare Register 0. Holds the lower limit for timer half A.

impl W<u32, Reg<u32, _CMPRB0>>

pub fn cmpr1b0(&mut self) -> CMPR1B0_W

Bits 16:31 - Counter/Timer B0 Compare Register 1. Holds the upper limit for timer half B.

pub fn cmpr0b0(&mut self) -> CMPR0B0_W

Bits 0:15 - Counter/Timer B0 Compare Register 0. Holds the lower limit for timer half B.

impl W<u32, Reg<u32, _CTRL0>>

pub fn ctlink0(&mut self) -> CTLINK0_W

Bit 31 - Counter/Timer A0/B0 Link bit.

pub fn tmrb0pol(&mut self) -> TMRB0POL_W

Bit 28 - Counter/Timer B0 output polarity.

pub fn tmrb0clr(&mut self) -> TMRB0CLR_W

Bit 27 - Counter/Timer B0 Clear bit.

pub fn tmrb0ie1(&mut self) -> TMRB0IE1_W

Bit 26 - Counter/Timer B0 Interrupt Enable bit for COMPR1.

pub fn tmrb0ie0(&mut self) -> TMRB0IE0_W

Bit 25 - Counter/Timer B0 Interrupt Enable bit for COMPR0.

pub fn tmrb0fn(&mut self) -> TMRB0FN_W

Bits 22:24 - Counter/Timer B0 Function Select.

pub fn tmrb0clk(&mut self) -> TMRB0CLK_W

Bits 17:21 - Counter/Timer B0 Clock Select.

pub fn tmrb0en(&mut self) -> TMRB0EN_W

Bit 16 - Counter/Timer B0 Enable bit.

pub fn tmra0pol(&mut self) -> TMRA0POL_W

Bit 12 - Counter/Timer A0 output polarity.

pub fn tmra0clr(&mut self) -> TMRA0CLR_W

Bit 11 - Counter/Timer A0 Clear bit.

pub fn tmra0ie1(&mut self) -> TMRA0IE1_W

Bit 10 - Counter/Timer A0 Interrupt Enable bit based on COMPR1.

pub fn tmra0ie0(&mut self) -> TMRA0IE0_W

Bit 9 - Counter/Timer A0 Interrupt Enable bit based on COMPR0.

pub fn tmra0fn(&mut self) -> TMRA0FN_W

Bits 6:8 - Counter/Timer A0 Function Select.

pub fn tmra0clk(&mut self) -> TMRA0CLK_W

Bits 1:5 - Counter/Timer A0 Clock Select.

pub fn tmra0en(&mut self) -> TMRA0EN_W

Bit 0 - Counter/Timer A0 Enable bit.

impl W<u32, Reg<u32, _CMPRAUXA0>>

pub fn cmpr3a0(&mut self) -> CMPR3A0_W

Bits 16:31 - Counter/Timer A0 Compare Register 3. Holds the upper limit for timer half A.

pub fn cmpr2a0(&mut self) -> CMPR2A0_W

Bits 0:15 - Counter/Timer A0 Compare Register 2. Holds the lower limit for timer half A.

impl W<u32, Reg<u32, _CMPRAUXB0>>

pub fn cmpr3b0(&mut self) -> CMPR3B0_W

Bits 16:31 - Counter/Timer B0 Compare Register 3. Holds the upper limit for timer half B.

pub fn cmpr2b0(&mut self) -> CMPR2B0_W

Bits 0:15 - Counter/Timer B0 Compare Register 2. Holds the lower limit for timer half B.

impl W<u32, Reg<u32, _AUX0>>

pub fn tmrb0en23(&mut self) -> TMRB0EN23_W

Bit 30 - Counter/Timer B0 Upper compare enable.

pub fn tmrb0pol23(&mut self) -> TMRB0POL23_W

Bit 29 - Upper output polarity

pub fn tmrb0tinv(&mut self) -> TMRB0TINV_W

Bit 28 - Counter/Timer B0 Invert on trigger.

pub fn tmrb0nosync(&mut self) -> TMRB0NOSYNC_W

Bit 27 - Source clock synchronization control.

pub fn tmrb0trig(&mut self) -> TMRB0TRIG_W

Bits 23:26 - Counter/Timer B0 Trigger Select.

pub fn tmrb0lmt(&mut self) -> TMRB0LMT_W

Bits 16:21 - Counter/Timer B0 Pattern Limit Count.

pub fn tmra0en23(&mut self) -> TMRA0EN23_W

Bit 14 - Counter/Timer A0 Upper compare enable.

pub fn tmra0pol23(&mut self) -> TMRA0POL23_W

Bit 13 - Counter/Timer A0 Upper output polarity

pub fn tmra0tinv(&mut self) -> TMRA0TINV_W

Bit 12 - Counter/Timer A0 Invert on trigger.

pub fn tmra0nosync(&mut self) -> TMRA0NOSYNC_W

Bit 11 - Source clock synchronization control.

pub fn tmra0trig(&mut self) -> TMRA0TRIG_W

Bits 7:10 - Counter/Timer A0 Trigger Select.

pub fn tmra0lmt(&mut self) -> TMRA0LMT_W

Bits 0:6 - Counter/Timer A0 Pattern Limit Count.

impl W<u32, Reg<u32, _TMR1>>

pub fn cttmrb1(&mut self) -> CTTMRB1_W

Bits 16:31 - Counter/Timer B1.

pub fn cttmra1(&mut self) -> CTTMRA1_W

Bits 0:15 - Counter/Timer A1.

impl W<u32, Reg<u32, _CMPRA1>>

pub fn cmpr1a1(&mut self) -> CMPR1A1_W

Bits 16:31 - Counter/Timer A1 Compare Register 1.

pub fn cmpr0a1(&mut self) -> CMPR0A1_W

Bits 0:15 - Counter/Timer A1 Compare Register 0.

impl W<u32, Reg<u32, _CMPRB1>>

pub fn cmpr1b1(&mut self) -> CMPR1B1_W

Bits 16:31 - Counter/Timer B1 Compare Register 1.

pub fn cmpr0b1(&mut self) -> CMPR0B1_W

Bits 0:15 - Counter/Timer B1 Compare Register 0.

impl W<u32, Reg<u32, _CTRL1>>

pub fn ctlink1(&mut self) -> CTLINK1_W

Bit 31 - Counter/Timer A1/B1 Link bit.

pub fn tmrb1pol(&mut self) -> TMRB1POL_W

Bit 28 - Counter/Timer B1 output polarity.

pub fn tmrb1clr(&mut self) -> TMRB1CLR_W

Bit 27 - Counter/Timer B1 Clear bit.

pub fn tmrb1ie1(&mut self) -> TMRB1IE1_W

Bit 26 - Counter/Timer B1 Interrupt Enable bit for COMPR1.

pub fn tmrb1ie0(&mut self) -> TMRB1IE0_W

Bit 25 - Counter/Timer B1 Interrupt Enable bit for COMPR0.

pub fn tmrb1fn(&mut self) -> TMRB1FN_W

Bits 22:24 - Counter/Timer B1 Function Select.

pub fn tmrb1clk(&mut self) -> TMRB1CLK_W

Bits 17:21 - Counter/Timer B1 Clock Select.

pub fn tmrb1en(&mut self) -> TMRB1EN_W

Bit 16 - Counter/Timer B1 Enable bit.

pub fn tmra1pol(&mut self) -> TMRA1POL_W

Bit 12 - Counter/Timer A1 output polarity.

pub fn tmra1clr(&mut self) -> TMRA1CLR_W

Bit 11 - Counter/Timer A1 Clear bit.

pub fn tmra1ie1(&mut self) -> TMRA1IE1_W

Bit 10 - Counter/Timer A1 Interrupt Enable bit based on COMPR1.

pub fn tmra1ie0(&mut self) -> TMRA1IE0_W

Bit 9 - Counter/Timer A1 Interrupt Enable bit based on COMPR0.

pub fn tmra1fn(&mut self) -> TMRA1FN_W

Bits 6:8 - Counter/Timer A1 Function Select.

pub fn tmra1clk(&mut self) -> TMRA1CLK_W

Bits 1:5 - Counter/Timer A1 Clock Select.

pub fn tmra1en(&mut self) -> TMRA1EN_W

Bit 0 - Counter/Timer A1 Enable bit.

impl W<u32, Reg<u32, _CMPRAUXA1>>

pub fn cmpr3a1(&mut self) -> CMPR3A1_W

Bits 16:31 - Counter/Timer A1 Compare Register 3. Holds the upper limit for timer half A.

pub fn cmpr2a1(&mut self) -> CMPR2A1_W

Bits 0:15 - Counter/Timer A1 Compare Register 2. Holds the lower limit for timer half A.

impl W<u32, Reg<u32, _CMPRAUXB1>>

pub fn cmpr3b1(&mut self) -> CMPR3B1_W

Bits 16:31 - Counter/Timer B1 Compare Register 3. Holds the upper limit for timer half B.

pub fn cmpr2b1(&mut self) -> CMPR2B1_W

Bits 0:15 - Counter/Timer B1 Compare Register 2. Holds the lower limit for timer half B.

impl W<u32, Reg<u32, _AUX1>>

pub fn tmrb1en23(&mut self) -> TMRB1EN23_W

Bit 30 - Counter/Timer B1 Upper compare enable.

pub fn tmrb1pol23(&mut self) -> TMRB1POL23_W

Bit 29 - Upper output polarity

pub fn tmrb1tinv(&mut self) -> TMRB1TINV_W

Bit 28 - Counter/Timer B1 Invert on trigger.

pub fn tmrb1nosync(&mut self) -> TMRB1NOSYNC_W

Bit 27 - Source clock synchronization control.

pub fn tmrb1trig(&mut self) -> TMRB1TRIG_W

Bits 23:26 - Counter/Timer B1 Trigger Select.

pub fn tmrb1lmt(&mut self) -> TMRB1LMT_W

Bits 16:21 - Counter/Timer B1 Pattern Limit Count.

pub fn tmra1en23(&mut self) -> TMRA1EN23_W

Bit 14 - Counter/Timer A1 Upper compare enable.

pub fn tmra1pol23(&mut self) -> TMRA1POL23_W

Bit 13 - Counter/Timer A1 Upper output polarity

pub fn tmra1tinv(&mut self) -> TMRA1TINV_W

Bit 12 - Counter/Timer A1 Invert on trigger.

pub fn tmra1nosync(&mut self) -> TMRA1NOSYNC_W

Bit 11 - Source clock synchronization control.

pub fn tmra1trig(&mut self) -> TMRA1TRIG_W

Bits 7:10 - Counter/Timer A1 Trigger Select.

pub fn tmra1lmt(&mut self) -> TMRA1LMT_W

Bits 0:6 - Counter/Timer A1 Pattern Limit Count.

impl W<u32, Reg<u32, _TMR2>>

pub fn cttmrb2(&mut self) -> CTTMRB2_W

Bits 16:31 - Counter/Timer B2.

pub fn cttmra2(&mut self) -> CTTMRA2_W

Bits 0:15 - Counter/Timer A2.

impl W<u32, Reg<u32, _CMPRA2>>

pub fn cmpr1a2(&mut self) -> CMPR1A2_W

Bits 16:31 - Counter/Timer A2 Compare Register 1.

pub fn cmpr0a2(&mut self) -> CMPR0A2_W

Bits 0:15 - Counter/Timer A2 Compare Register 0.

impl W<u32, Reg<u32, _CMPRB2>>

pub fn cmpr1b2(&mut self) -> CMPR1B2_W

Bits 16:31 - Counter/Timer B2 Compare Register 1.

pub fn cmpr0b2(&mut self) -> CMPR0B2_W

Bits 0:15 - Counter/Timer B2 Compare Register 0.

impl W<u32, Reg<u32, _CTRL2>>

pub fn ctlink2(&mut self) -> CTLINK2_W

Bit 31 - Counter/Timer A2/B2 Link bit.

pub fn tmrb2pol(&mut self) -> TMRB2POL_W

Bit 28 - Counter/Timer B2 output polarity.

pub fn tmrb2clr(&mut self) -> TMRB2CLR_W

Bit 27 - Counter/Timer B2 Clear bit.

pub fn tmrb2ie1(&mut self) -> TMRB2IE1_W

Bit 26 - Counter/Timer B2 Interrupt Enable bit for COMPR1.

pub fn tmrb2ie0(&mut self) -> TMRB2IE0_W

Bit 25 - Counter/Timer B2 Interrupt Enable bit for COMPR0.

pub fn tmrb2fn(&mut self) -> TMRB2FN_W

Bits 22:24 - Counter/Timer B2 Function Select.

pub fn tmrb2clk(&mut self) -> TMRB2CLK_W

Bits 17:21 - Counter/Timer B2 Clock Select.

pub fn tmrb2en(&mut self) -> TMRB2EN_W

Bit 16 - Counter/Timer B2 Enable bit.

pub fn tmra2pol(&mut self) -> TMRA2POL_W

Bit 12 - Counter/Timer A2 output polarity.

pub fn tmra2clr(&mut self) -> TMRA2CLR_W

Bit 11 - Counter/Timer A2 Clear bit.

pub fn tmra2ie1(&mut self) -> TMRA2IE1_W

Bit 10 - Counter/Timer A2 Interrupt Enable bit based on COMPR1.

pub fn tmra2ie0(&mut self) -> TMRA2IE0_W

Bit 9 - Counter/Timer A2 Interrupt Enable bit based on COMPR0.

pub fn tmra2fn(&mut self) -> TMRA2FN_W

Bits 6:8 - Counter/Timer A2 Function Select.

pub fn tmra2clk(&mut self) -> TMRA2CLK_W

Bits 1:5 - Counter/Timer A2 Clock Select.

pub fn tmra2en(&mut self) -> TMRA2EN_W

Bit 0 - Counter/Timer A2 Enable bit.

impl W<u32, Reg<u32, _CMPRAUXA2>>

pub fn cmpr3a2(&mut self) -> CMPR3A2_W

Bits 16:31 - Counter/Timer A2 Compare Register 3. Holds the upper limit for timer half A.

pub fn cmpr2a2(&mut self) -> CMPR2A2_W

Bits 0:15 - Counter/Timer A2 Compare Register 2. Holds the lower limit for timer half A.

impl W<u32, Reg<u32, _CMPRAUXB2>>

pub fn cmpr3b2(&mut self) -> CMPR3B2_W

Bits 16:31 - Counter/Timer B2 Compare Register 3. Holds the upper limit for timer half B.

pub fn cmpr2b2(&mut self) -> CMPR2B2_W

Bits 0:15 - Counter/Timer B2 Compare Register 2. Holds the lower limit for timer half B.

impl W<u32, Reg<u32, _AUX2>>

pub fn tmrb2en23(&mut self) -> TMRB2EN23_W

Bit 30 - Counter/Timer B2 Upper compare enable.

pub fn tmrb2pol23(&mut self) -> TMRB2POL23_W

Bit 29 - Upper output polarity

pub fn tmrb2tinv(&mut self) -> TMRB2TINV_W

Bit 28 - Counter/Timer B2 Invert on trigger.

pub fn tmrb2nosync(&mut self) -> TMRB2NOSYNC_W

Bit 27 - Source clock synchronization control.

pub fn tmrb2trig(&mut self) -> TMRB2TRIG_W

Bits 23:26 - Counter/Timer B2 Trigger Select.

pub fn tmrb2lmt(&mut self) -> TMRB2LMT_W

Bits 16:21 - Counter/Timer B2 Pattern Limit Count.

pub fn tmra2en23(&mut self) -> TMRA2EN23_W

Bit 14 - Counter/Timer A2 Upper compare enable.

pub fn tmra2pol23(&mut self) -> TMRA2POL23_W

Bit 13 - Counter/Timer A2 Upper output polarity

pub fn tmra2tinv(&mut self) -> TMRA2TINV_W

Bit 12 - Counter/Timer A2 Invert on trigger.

pub fn tmra2nosync(&mut self) -> TMRA2NOSYNC_W

Bit 11 - Source clock synchronization control.

pub fn tmra2trig(&mut self) -> TMRA2TRIG_W

Bits 7:10 - Counter/Timer A2 Trigger Select.

pub fn tmra2lmt(&mut self) -> TMRA2LMT_W

Bits 0:6 - Counter/Timer A2 Pattern Limit Count.

impl W<u32, Reg<u32, _TMR3>>

pub fn cttmrb3(&mut self) -> CTTMRB3_W

Bits 16:31 - Counter/Timer B3.

pub fn cttmra3(&mut self) -> CTTMRA3_W

Bits 0:15 - Counter/Timer A3.

impl W<u32, Reg<u32, _CMPRA3>>

pub fn cmpr1a3(&mut self) -> CMPR1A3_W

Bits 16:31 - Counter/Timer A3 Compare Register 1.

pub fn cmpr0a3(&mut self) -> CMPR0A3_W

Bits 0:15 - Counter/Timer A3 Compare Register 0.

impl W<u32, Reg<u32, _CMPRB3>>

pub fn cmpr1b3(&mut self) -> CMPR1B3_W

Bits 16:31 - Counter/Timer B3 Compare Register 1.

pub fn cmpr0b3(&mut self) -> CMPR0B3_W

Bits 0:15 - Counter/Timer B3 Compare Register 0.

impl W<u32, Reg<u32, _CTRL3>>

pub fn ctlink3(&mut self) -> CTLINK3_W

Bit 31 - Counter/Timer A3/B3 Link bit.

pub fn tmrb3pol(&mut self) -> TMRB3POL_W

Bit 28 - Counter/Timer B3 output polarity.

pub fn tmrb3clr(&mut self) -> TMRB3CLR_W

Bit 27 - Counter/Timer B3 Clear bit.

pub fn tmrb3ie1(&mut self) -> TMRB3IE1_W

Bit 26 - Counter/Timer B3 Interrupt Enable bit for COMPR1.

pub fn tmrb3ie0(&mut self) -> TMRB3IE0_W

Bit 25 - Counter/Timer B3 Interrupt Enable bit for COMPR0.

pub fn tmrb3fn(&mut self) -> TMRB3FN_W

Bits 22:24 - Counter/Timer B3 Function Select.

pub fn tmrb3clk(&mut self) -> TMRB3CLK_W

Bits 17:21 - Counter/Timer B3 Clock Select.

pub fn tmrb3en(&mut self) -> TMRB3EN_W

Bit 16 - Counter/Timer B3 Enable bit.

pub fn adcen(&mut self) -> ADCEN_W

Bit 15 - Special Timer A3 enable for ADC function.

pub fn tmra3pol(&mut self) -> TMRA3POL_W

Bit 12 - Counter/Timer A3 output polarity.

pub fn tmra3clr(&mut self) -> TMRA3CLR_W

Bit 11 - Counter/Timer A3 Clear bit.

pub fn tmra3ie1(&mut self) -> TMRA3IE1_W

Bit 10 - Counter/Timer A3 Interrupt Enable bit based on COMPR1.

pub fn tmra3ie0(&mut self) -> TMRA3IE0_W

Bit 9 - Counter/Timer A3 Interrupt Enable bit based on COMPR0.

pub fn tmra3fn(&mut self) -> TMRA3FN_W

Bits 6:8 - Counter/Timer A3 Function Select.

pub fn tmra3clk(&mut self) -> TMRA3CLK_W

Bits 1:5 - Counter/Timer A3 Clock Select.

pub fn tmra3en(&mut self) -> TMRA3EN_W

Bit 0 - Counter/Timer A3 Enable bit.

impl W<u32, Reg<u32, _CMPRAUXA3>>

pub fn cmpr3a3(&mut self) -> CMPR3A3_W

Bits 16:31 - Counter/Timer A3 Compare Register 3. Holds the upper limit for timer half A.

pub fn cmpr2a3(&mut self) -> CMPR2A3_W

Bits 0:15 - Counter/Timer A3 Compare Register 2. Holds the lower limit for timer half A.

impl W<u32, Reg<u32, _CMPRAUXB3>>

pub fn cmpr3b3(&mut self) -> CMPR3B3_W

Bits 16:31 - Counter/Timer B3 Compare Register 3. Holds the upper limit for timer half B.

pub fn cmpr2b3(&mut self) -> CMPR2B3_W

Bits 0:15 - Counter/Timer B3 Compare Register 2. Holds the lower limit for timer half B.

impl W<u32, Reg<u32, _AUX3>>

pub fn tmrb3en23(&mut self) -> TMRB3EN23_W

Bit 30 - Counter/Timer B3 Upper compare enable.

pub fn tmrb3pol23(&mut self) -> TMRB3POL23_W

Bit 29 - Upper output polarity

pub fn tmrb3tinv(&mut self) -> TMRB3TINV_W

Bit 28 - Counter/Timer B3 Invert on trigger.

pub fn tmrb3nosync(&mut self) -> TMRB3NOSYNC_W

Bit 27 - Source clock synchronization control.

pub fn tmrb3trig(&mut self) -> TMRB3TRIG_W

Bits 23:26 - Counter/Timer B3 Trigger Select.

pub fn tmrb3lmt(&mut self) -> TMRB3LMT_W

Bits 16:21 - Counter/Timer B3 Pattern Limit Count.

pub fn tmra3en23(&mut self) -> TMRA3EN23_W

Bit 14 - Counter/Timer A3 Upper compare enable.

pub fn tmra3pol23(&mut self) -> TMRA3POL23_W

Bit 13 - Counter/Timer A3 Upper output polarity

pub fn tmra3tinv(&mut self) -> TMRA3TINV_W

Bit 12 - Counter/Timer A3 Invert on trigger.

pub fn tmra3nosync(&mut self) -> TMRA3NOSYNC_W

Bit 11 - Source clock synchronization control.

pub fn tmra3trig(&mut self) -> TMRA3TRIG_W

Bits 7:10 - Counter/Timer A3 Trigger Select.

pub fn tmra3lmt(&mut self) -> TMRA3LMT_W

Bits 0:6 - Counter/Timer A3 Pattern Limit Count.

impl W<u32, Reg<u32, _TMR4>>

pub fn cttmrb4(&mut self) -> CTTMRB4_W

Bits 16:31 - Counter/Timer B4.

pub fn cttmra4(&mut self) -> CTTMRA4_W

Bits 0:15 - Counter/Timer A4.

impl W<u32, Reg<u32, _CMPRA4>>

pub fn cmpr1a4(&mut self) -> CMPR1A4_W

Bits 16:31 - Counter/Timer A4 Compare Register 1. Holds the upper limit for timer half A.

pub fn cmpr0a4(&mut self) -> CMPR0A4_W

Bits 0:15 - Counter/Timer A4 Compare Register 0. Holds the lower limit for timer half A.

impl W<u32, Reg<u32, _CMPRB4>>

pub fn cmpr1b4(&mut self) -> CMPR1B4_W

Bits 16:31 - Counter/Timer B4 Compare Register 1. Holds the upper limit for timer half B.

pub fn cmpr0b4(&mut self) -> CMPR0B4_W

Bits 0:15 - Counter/Timer B4 Compare Register 0. Holds the lower limit for timer half B.

impl W<u32, Reg<u32, _CTRL4>>

pub fn ctlink4(&mut self) -> CTLINK4_W

Bit 31 - Counter/Timer A4/B4 Link bit.

pub fn tmrb4pol(&mut self) -> TMRB4POL_W

Bit 28 - Counter/Timer B4 output polarity.

pub fn tmrb4clr(&mut self) -> TMRB4CLR_W

Bit 27 - Counter/Timer B4 Clear bit.

pub fn tmrb4ie1(&mut self) -> TMRB4IE1_W

Bit 26 - Counter/Timer B4 Interrupt Enable bit for COMPR1.

pub fn tmrb4ie0(&mut self) -> TMRB4IE0_W

Bit 25 - Counter/Timer B4 Interrupt Enable bit for COMPR0.

pub fn tmrb4fn(&mut self) -> TMRB4FN_W

Bits 22:24 - Counter/Timer B4 Function Select.

pub fn tmrb4clk(&mut self) -> TMRB4CLK_W

Bits 17:21 - Counter/Timer B4 Clock Select.

pub fn tmrb4en(&mut self) -> TMRB4EN_W

Bit 16 - Counter/Timer B4 Enable bit.

pub fn tmra4pol(&mut self) -> TMRA4POL_W

Bit 12 - Counter/Timer A4 output polarity.

pub fn tmra4clr(&mut self) -> TMRA4CLR_W

Bit 11 - Counter/Timer A4 Clear bit.

pub fn tmra4ie1(&mut self) -> TMRA4IE1_W

Bit 10 - Counter/Timer A4 Interrupt Enable bit based on COMPR1.

pub fn tmra4ie0(&mut self) -> TMRA4IE0_W

Bit 9 - Counter/Timer A4 Interrupt Enable bit based on COMPR0.

pub fn tmra4fn(&mut self) -> TMRA4FN_W

Bits 6:8 - Counter/Timer A4 Function Select.

pub fn tmra4clk(&mut self) -> TMRA4CLK_W

Bits 1:5 - Counter/Timer A4 Clock Select.

pub fn tmra4en(&mut self) -> TMRA4EN_W

Bit 0 - Counter/Timer A4 Enable bit.

impl W<u32, Reg<u32, _CMPRAUXA4>>

pub fn cmpr3a4(&mut self) -> CMPR3A4_W

Bits 16:31 - Counter/Timer A4 Compare Register 3. Holds the upper limit for timer half A.

pub fn cmpr2a4(&mut self) -> CMPR2A4_W

Bits 0:15 - Counter/Timer A4 Compare Register 2. Holds the lower limit for timer half A.

impl W<u32, Reg<u32, _CMPRAUXB4>>

pub fn cmpr3b4(&mut self) -> CMPR3B4_W

Bits 16:31 - Counter/Timer B4 Compare Register 3. Holds the upper limit for timer half B.

pub fn cmpr2b4(&mut self) -> CMPR2B4_W

Bits 0:15 - Counter/Timer B4 Compare Register 2. Holds the lower limit for timer half B.

impl W<u32, Reg<u32, _AUX4>>

pub fn tmrb4en23(&mut self) -> TMRB4EN23_W

Bit 30 - Counter/Timer B4 Upper compare enable.

pub fn tmrb4pol23(&mut self) -> TMRB4POL23_W

Bit 29 - Upper output polarity

pub fn tmrb4tinv(&mut self) -> TMRB4TINV_W

Bit 28 - Counter/Timer B4 Invert on trigger.

pub fn tmrb4nosync(&mut self) -> TMRB4NOSYNC_W

Bit 27 - Source clock synchronization control.

pub fn tmrb4trig(&mut self) -> TMRB4TRIG_W

Bits 23:26 - Counter/Timer B4 Trigger Select.

pub fn tmrb4lmt(&mut self) -> TMRB4LMT_W

Bits 16:21 - Counter/Timer B4 Pattern Limit Count.

pub fn tmra4en23(&mut self) -> TMRA4EN23_W

Bit 14 - Counter/Timer A4 Upper compare enable.

pub fn tmra4pol23(&mut self) -> TMRA4POL23_W

Bit 13 - Counter/Timer A4 Upper output polarity

pub fn tmra4tinv(&mut self) -> TMRA4TINV_W

Bit 12 - Counter/Timer A4 Invert on trigger.

pub fn tmra4nosync(&mut self) -> TMRA4NOSYNC_W

Bit 11 - Source clock synchronization control.

pub fn tmra4trig(&mut self) -> TMRA4TRIG_W

Bits 7:10 - Counter/Timer A4 Trigger Select.

pub fn tmra4lmt(&mut self) -> TMRA4LMT_W

Bits 0:6 - Counter/Timer A4 Pattern Limit Count.

impl W<u32, Reg<u32, _TMR5>>

pub fn cttmrb5(&mut self) -> CTTMRB5_W

Bits 16:31 - Counter/Timer B5.

pub fn cttmra5(&mut self) -> CTTMRA5_W

Bits 0:15 - Counter/Timer A5.

impl W<u32, Reg<u32, _CMPRA5>>

pub fn cmpr1a5(&mut self) -> CMPR1A5_W

Bits 16:31 - Counter/Timer A5 Compare Register 1.

pub fn cmpr0a5(&mut self) -> CMPR0A5_W

Bits 0:15 - Counter/Timer A5 Compare Register 0.

impl W<u32, Reg<u32, _CMPRB5>>

pub fn cmpr1b5(&mut self) -> CMPR1B5_W

Bits 16:31 - Counter/Timer B5 Compare Register 1.

pub fn cmpr0b5(&mut self) -> CMPR0B5_W

Bits 0:15 - Counter/Timer B5 Compare Register 0.

impl W<u32, Reg<u32, _CTRL5>>

pub fn ctlink5(&mut self) -> CTLINK5_W

Bit 31 - Counter/Timer A5/B5 Link bit.

pub fn tmrb5pol(&mut self) -> TMRB5POL_W

Bit 28 - Counter/Timer B5 output polarity.

pub fn tmrb5clr(&mut self) -> TMRB5CLR_W

Bit 27 - Counter/Timer B5 Clear bit.

pub fn tmrb5ie1(&mut self) -> TMRB5IE1_W

Bit 26 - Counter/Timer B5 Interrupt Enable bit for COMPR1.

pub fn tmrb5ie0(&mut self) -> TMRB5IE0_W

Bit 25 - Counter/Timer B5 Interrupt Enable bit for COMPR0.

pub fn tmrb5fn(&mut self) -> TMRB5FN_W

Bits 22:24 - Counter/Timer B5 Function Select.

pub fn tmrb5clk(&mut self) -> TMRB5CLK_W

Bits 17:21 - Counter/Timer B5 Clock Select.

pub fn tmrb5en(&mut self) -> TMRB5EN_W

Bit 16 - Counter/Timer B5 Enable bit.

pub fn tmra5pol(&mut self) -> TMRA5POL_W

Bit 12 - Counter/Timer A5 output polarity.

pub fn tmra5clr(&mut self) -> TMRA5CLR_W

Bit 11 - Counter/Timer A5 Clear bit.

pub fn tmra5ie1(&mut self) -> TMRA5IE1_W

Bit 10 - Counter/Timer A5 Interrupt Enable bit based on COMPR1.

pub fn tmra5ie0(&mut self) -> TMRA5IE0_W

Bit 9 - Counter/Timer A5 Interrupt Enable bit based on COMPR0.

pub fn tmra5fn(&mut self) -> TMRA5FN_W

Bits 6:8 - Counter/Timer A5 Function Select.

pub fn tmra5clk(&mut self) -> TMRA5CLK_W

Bits 1:5 - Counter/Timer A5 Clock Select.

pub fn tmra5en(&mut self) -> TMRA5EN_W

Bit 0 - Counter/Timer A5 Enable bit.

impl W<u32, Reg<u32, _CMPRAUXA5>>

pub fn cmpr3a5(&mut self) -> CMPR3A5_W

Bits 16:31 - Counter/Timer A5 Compare Register 3. Holds the upper limit for timer half A.

pub fn cmpr2a5(&mut self) -> CMPR2A5_W

Bits 0:15 - Counter/Timer A5 Compare Register 2. Holds the lower limit for timer half A.

impl W<u32, Reg<u32, _CMPRAUXB5>>

pub fn cmpr3b5(&mut self) -> CMPR3B5_W

Bits 16:31 - Counter/Timer B5 Compare Register 3. Holds the upper limit for timer half B.

pub fn cmpr2b5(&mut self) -> CMPR2B5_W

Bits 0:15 - Counter/Timer B5 Compare Register 2. Holds the lower limit for timer half B.

impl W<u32, Reg<u32, _AUX5>>

pub fn tmrb5en23(&mut self) -> TMRB5EN23_W

Bit 30 - Counter/Timer B5 Upper compare enable.

pub fn tmrb5pol23(&mut self) -> TMRB5POL23_W

Bit 29 - Upper output polarity

pub fn tmrb5tinv(&mut self) -> TMRB5TINV_W

Bit 28 - Counter/Timer B5 Invert on trigger.

pub fn tmrb5nosync(&mut self) -> TMRB5NOSYNC_W

Bit 27 - Source clock synchronization control.

pub fn tmrb5trig(&mut self) -> TMRB5TRIG_W

Bits 23:26 - Counter/Timer B5 Trigger Select.

pub fn tmrb5lmt(&mut self) -> TMRB5LMT_W

Bits 16:21 - Counter/Timer B5 Pattern Limit Count.

pub fn tmra5en23(&mut self) -> TMRA5EN23_W

Bit 14 - Counter/Timer A5 Upper compare enable.

pub fn tmra5pol23(&mut self) -> TMRA5POL23_W

Bit 13 - Counter/Timer A5 Upper output polarity

pub fn tmra5tinv(&mut self) -> TMRA5TINV_W

Bit 12 - Counter/Timer A5 Invert on trigger.

pub fn tmra5nosync(&mut self) -> TMRA5NOSYNC_W

Bit 11 - Source clock synchronization control.

pub fn tmra5trig(&mut self) -> TMRA5TRIG_W

Bits 7:10 - Counter/Timer A5 Trigger Select.

pub fn tmra5lmt(&mut self) -> TMRA5LMT_W

Bits 0:6 - Counter/Timer A5 Pattern Limit Count.

impl W<u32, Reg<u32, _TMR6>>

pub fn cttmrb6(&mut self) -> CTTMRB6_W

Bits 16:31 - Counter/Timer B6.

pub fn cttmra6(&mut self) -> CTTMRA6_W

Bits 0:15 - Counter/Timer A6.

impl W<u32, Reg<u32, _CMPRA6>>

pub fn cmpr1a6(&mut self) -> CMPR1A6_W

Bits 16:31 - Counter/Timer A6 Compare Register 1.

pub fn cmpr0a6(&mut self) -> CMPR0A6_W

Bits 0:15 - Counter/Timer A6 Compare Register 0.

impl W<u32, Reg<u32, _CMPRB6>>

pub fn cmpr1b6(&mut self) -> CMPR1B6_W

Bits 16:31 - Counter/Timer B6 Compare Register 1.

pub fn cmpr0b6(&mut self) -> CMPR0B6_W

Bits 0:15 - Counter/Timer B6 Compare Register 0.

impl W<u32, Reg<u32, _CTRL6>>

pub fn ctlink6(&mut self) -> CTLINK6_W

Bit 31 - Counter/Timer A6/B6 Link bit.

pub fn tmrb6pol(&mut self) -> TMRB6POL_W

Bit 28 - Counter/Timer B6 output polarity.

pub fn tmrb6clr(&mut self) -> TMRB6CLR_W

Bit 27 - Counter/Timer B6 Clear bit.

pub fn tmrb6ie1(&mut self) -> TMRB6IE1_W

Bit 26 - Counter/Timer B6 Interrupt Enable bit for COMPR1.

pub fn tmrb6ie0(&mut self) -> TMRB6IE0_W

Bit 25 - Counter/Timer B6 Interrupt Enable bit for COMPR0.

pub fn tmrb6fn(&mut self) -> TMRB6FN_W

Bits 22:24 - Counter/Timer B6 Function Select.

pub fn tmrb6clk(&mut self) -> TMRB6CLK_W

Bits 17:21 - Counter/Timer B6 Clock Select.

pub fn tmrb6en(&mut self) -> TMRB6EN_W

Bit 16 - Counter/Timer B6 Enable bit.

pub fn tmra6pol(&mut self) -> TMRA6POL_W

Bit 12 - Counter/Timer A6 output polarity.

pub fn tmra6clr(&mut self) -> TMRA6CLR_W

Bit 11 - Counter/Timer A6 Clear bit.

pub fn tmra6ie1(&mut self) -> TMRA6IE1_W

Bit 10 - Counter/Timer A6 Interrupt Enable bit based on COMPR1.

pub fn tmra6ie0(&mut self) -> TMRA6IE0_W

Bit 9 - Counter/Timer A6 Interrupt Enable bit based on COMPR0.

pub fn tmra6fn(&mut self) -> TMRA6FN_W

Bits 6:8 - Counter/Timer A6 Function Select.

pub fn tmra6clk(&mut self) -> TMRA6CLK_W

Bits 1:5 - Counter/Timer A6 Clock Select.

pub fn tmra6en(&mut self) -> TMRA6EN_W

Bit 0 - Counter/Timer A6 Enable bit.

impl W<u32, Reg<u32, _CMPRAUXA6>>

pub fn cmpr3a6(&mut self) -> CMPR3A6_W

Bits 16:31 - Counter/Timer A6 Compare Register 3. Holds the upper limit for timer half A.

pub fn cmpr2a6(&mut self) -> CMPR2A6_W

Bits 0:15 - Counter/Timer A6 Compare Register 2. Holds the lower limit for timer half A.

impl W<u32, Reg<u32, _CMPRAUXB6>>

pub fn cmpr3b6(&mut self) -> CMPR3B6_W

Bits 16:31 - Counter/Timer B6 Compare Register 3. Holds the upper limit for timer half B.

pub fn cmpr2b6(&mut self) -> CMPR2B6_W

Bits 0:15 - Counter/Timer B6 Compare Register 2. Holds the lower limit for timer half B.

impl W<u32, Reg<u32, _AUX6>>

pub fn tmrb6en23(&mut self) -> TMRB6EN23_W

Bit 30 - Counter/Timer B6 Upper compare enable.

pub fn tmrb6pol23(&mut self) -> TMRB6POL23_W

Bit 29 - Upper output polarity

pub fn tmrb6tinv(&mut self) -> TMRB6TINV_W

Bit 28 - Counter/Timer B6 Invert on trigger.

pub fn tmrb6nosync(&mut self) -> TMRB6NOSYNC_W

Bit 27 - Source clock synchronization control.

pub fn tmrb6trig(&mut self) -> TMRB6TRIG_W

Bits 23:26 - Counter/Timer B6 Trigger Select.

pub fn tmrb6lmt(&mut self) -> TMRB6LMT_W

Bits 16:21 - Counter/Timer B6 Pattern Limit Count.

pub fn tmra6en23(&mut self) -> TMRA6EN23_W

Bit 14 - Counter/Timer A6 Upper compare enable.

pub fn tmra6pol23(&mut self) -> TMRA6POL23_W

Bit 13 - Counter/Timer A6 Upper output polarity

pub fn tmra6tinv(&mut self) -> TMRA6TINV_W

Bit 12 - Counter/Timer A6 Invert on trigger.

pub fn tmra6nosync(&mut self) -> TMRA6NOSYNC_W

Bit 11 - Source clock synchronization control.

pub fn tmra6trig(&mut self) -> TMRA6TRIG_W

Bits 7:10 - Counter/Timer A6 Trigger Select.

pub fn tmra6lmt(&mut self) -> TMRA6LMT_W

Bits 0:6 - Counter/Timer A6 Pattern Limit Count.

impl W<u32, Reg<u32, _TMR7>>

pub fn cttmrb7(&mut self) -> CTTMRB7_W

Bits 16:31 - Counter/Timer B7.

pub fn cttmra7(&mut self) -> CTTMRA7_W

Bits 0:15 - Counter/Timer A7.

impl W<u32, Reg<u32, _CMPRA7>>

pub fn cmpr1a7(&mut self) -> CMPR1A7_W

Bits 16:31 - Counter/Timer A7 Compare Register 1.

pub fn cmpr0a7(&mut self) -> CMPR0A7_W

Bits 0:15 - Counter/Timer A7 Compare Register 0.

impl W<u32, Reg<u32, _CMPRB7>>

pub fn cmpr1b7(&mut self) -> CMPR1B7_W

Bits 16:31 - Counter/Timer B3 Compare Register 1.

pub fn cmpr0b7(&mut self) -> CMPR0B7_W

Bits 0:15 - Counter/Timer B3 Compare Register 0.

impl W<u32, Reg<u32, _CTRL7>>

pub fn ctlink7(&mut self) -> CTLINK7_W

Bit 31 - Counter/Timer A7/B7 Link bit.

pub fn tmrb7pol(&mut self) -> TMRB7POL_W

Bit 28 - Counter/Timer B7 output polarity.

pub fn tmrb7clr(&mut self) -> TMRB7CLR_W

Bit 27 - Counter/Timer B7 Clear bit.

pub fn tmrb7ie1(&mut self) -> TMRB7IE1_W

Bit 26 - Counter/Timer B7 Interrupt Enable bit for COMPR1.

pub fn tmrb7ie0(&mut self) -> TMRB7IE0_W

Bit 25 - Counter/Timer B7 Interrupt Enable bit for COMPR0.

pub fn tmrb7fn(&mut self) -> TMRB7FN_W

Bits 22:24 - Counter/Timer B7 Function Select.

pub fn tmrb7clk(&mut self) -> TMRB7CLK_W

Bits 17:21 - Counter/Timer B7 Clock Select.

pub fn tmrb7en(&mut self) -> TMRB7EN_W

Bit 16 - Counter/Timer B7 Enable bit.

pub fn tmra7pol(&mut self) -> TMRA7POL_W

Bit 12 - Counter/Timer A7 output polarity.

pub fn tmra7clr(&mut self) -> TMRA7CLR_W

Bit 11 - Counter/Timer A7 Clear bit.

pub fn tmra7ie1(&mut self) -> TMRA7IE1_W

Bit 10 - Counter/Timer A7 Interrupt Enable bit based on COMPR1.

pub fn tmra7ie0(&mut self) -> TMRA7IE0_W

Bit 9 - Counter/Timer A7 Interrupt Enable bit based on COMPR0.

pub fn tmra7fn(&mut self) -> TMRA7FN_W

Bits 6:8 - Counter/Timer A7 Function Select.

pub fn tmra7clk(&mut self) -> TMRA7CLK_W

Bits 1:5 - Counter/Timer A7 Clock Select.

pub fn tmra7en(&mut self) -> TMRA7EN_W

Bit 0 - Counter/Timer A7 Enable bit.

impl W<u32, Reg<u32, _CMPRAUXA7>>

pub fn cmpr3a7(&mut self) -> CMPR3A7_W

Bits 16:31 - Counter/Timer A7 Compare Register 3. Holds the upper limit for timer half A.

pub fn cmpr2a7(&mut self) -> CMPR2A7_W

Bits 0:15 - Counter/Timer A7 Compare Register 2. Holds the lower limit for timer half A.

impl W<u32, Reg<u32, _CMPRAUXB7>>

pub fn cmpr3b7(&mut self) -> CMPR3B7_W

Bits 16:31 - Counter/Timer B7 Compare Register 3. Holds the upper limit for timer half B.

pub fn cmpr2b7(&mut self) -> CMPR2B7_W

Bits 0:15 - Counter/Timer B7 Compare Register 2. Holds the lower limit for timer half B.

impl W<u32, Reg<u32, _AUX7>>

pub fn tmrb7en23(&mut self) -> TMRB7EN23_W

Bit 30 - Counter/Timer B7 Upper compare enable.

pub fn tmrb7pol23(&mut self) -> TMRB7POL23_W

Bit 29 - Upper output polarity

pub fn tmrb7tinv(&mut self) -> TMRB7TINV_W

Bit 28 - Counter/Timer B7 Invert on trigger.

pub fn tmrb7nosync(&mut self) -> TMRB7NOSYNC_W

Bit 27 - Source clock synchronization control.

pub fn tmrb7trig(&mut self) -> TMRB7TRIG_W

Bits 23:26 - Counter/Timer B7 Trigger Select.

pub fn tmrb7lmt(&mut self) -> TMRB7LMT_W

Bits 16:21 - Counter/Timer B7 Pattern Limit Count.

pub fn tmra7en23(&mut self) -> TMRA7EN23_W

Bit 14 - Counter/Timer A7 Upper compare enable.

pub fn tmra7pol23(&mut self) -> TMRA7POL23_W

Bit 13 - Counter/Timer A7 Upper output polarity

pub fn tmra7tinv(&mut self) -> TMRA7TINV_W

Bit 12 - Counter/Timer A7 Invert on trigger.

pub fn tmra7nosync(&mut self) -> TMRA7NOSYNC_W

Bit 11 - Source clock synchronization control.

pub fn tmra7trig(&mut self) -> TMRA7TRIG_W

Bits 7:10 - Counter/Timer A7 Trigger Select.

pub fn tmra7lmt(&mut self) -> TMRA7LMT_W

Bits 0:6 - Counter/Timer A7 Pattern Limit Count.

impl W<u32, Reg<u32, _GLOBEN>>

pub fn enb7(&mut self) -> ENB7_W

Bit 15 - Alternate enable for B7.

pub fn ena7(&mut self) -> ENA7_W

Bit 14 - Alternate enable for A7

pub fn enb6(&mut self) -> ENB6_W

Bit 13 - Alternate enable for B6

pub fn ena6(&mut self) -> ENA6_W

Bit 12 - Alternate enable for A6

pub fn enb5(&mut self) -> ENB5_W

Bit 11 - Alternate enable for B5

pub fn ena5(&mut self) -> ENA5_W

Bit 10 - Alternate enable for A5

pub fn enb4(&mut self) -> ENB4_W

Bit 9 - Alternate enable for B4

pub fn ena4(&mut self) -> ENA4_W

Bit 8 - Alternate enable for A4

pub fn enb3(&mut self) -> ENB3_W

Bit 7 - Alternate enable for B3.

pub fn ena3(&mut self) -> ENA3_W

Bit 6 - Alternate enable for A3

pub fn enb2(&mut self) -> ENB2_W

Bit 5 - Alternate enable for B2

pub fn ena2(&mut self) -> ENA2_W

Bit 4 - Alternate enable for A2

pub fn enb1(&mut self) -> ENB1_W

Bit 3 - Alternate enable for B1

pub fn ena1(&mut self) -> ENA1_W

Bit 2 - Alternate enable for A1

pub fn enb0(&mut self) -> ENB0_W

Bit 1 - Alternate enable for B0

pub fn ena0(&mut self) -> ENA0_W

Bit 0 - Alternate enable for A0

impl W<u32, Reg<u32, _OUTCFG0>>

pub fn cfg9(&mut self) -> CFG9_W

Bits 28:30 - Pad output 9 configuration

pub fn cfg8(&mut self) -> CFG8_W

Bits 25:27 - Pad output 8 configuration

pub fn cfg7(&mut self) -> CFG7_W

Bits 22:24 - Pad output 7 configuration

pub fn cfg6(&mut self) -> CFG6_W

Bits 19:21 - Pad output 6 configuration

pub fn cfg5(&mut self) -> CFG5_W

Bits 16:18 - Pad output 5 configuration

pub fn cfg4(&mut self) -> CFG4_W

Bits 12:14 - Pad output 4 configuration

pub fn cfg3(&mut self) -> CFG3_W

Bits 9:11 - Pad output 3 configuration

pub fn cfg2(&mut self) -> CFG2_W

Bits 6:8 - Pad output 2 configuration

pub fn cfg1(&mut self) -> CFG1_W

Bits 3:5 - Pad output 1 configuration

pub fn cfg0(&mut self) -> CFG0_W

Bits 0:2 - Pad output 0 configuration

impl W<u32, Reg<u32, _OUTCFG1>>

pub fn cfg19(&mut self) -> CFG19_W

Bits 28:30 - Pad output 19 configuration

pub fn cfg18(&mut self) -> CFG18_W

Bits 25:27 - Pad output 18 configuration

pub fn cfg17(&mut self) -> CFG17_W

Bits 22:24 - Pad output 17 configuration

pub fn cfg16(&mut self) -> CFG16_W

Bits 19:21 - Pad output 16 configuration

pub fn cfg15(&mut self) -> CFG15_W

Bits 16:18 - Pad output 15 configuration

pub fn cfg14(&mut self) -> CFG14_W

Bits 12:14 - Pad output 14 configuration

pub fn cfg13(&mut self) -> CFG13_W

Bits 9:11 - Pad output 13 configuration

pub fn cfg12(&mut self) -> CFG12_W

Bits 6:8 - Pad output 12 configuration

pub fn cfg11(&mut self) -> CFG11_W

Bits 3:5 - Pad output 11 configuration

pub fn cfg10(&mut self) -> CFG10_W

Bits 0:2 - Pad output 10 configuration

impl W<u32, Reg<u32, _OUTCFG2>>

pub fn cfg29(&mut self) -> CFG29_W

Bits 28:30 - Pad output 29 configuration

pub fn cfg28(&mut self) -> CFG28_W

Bits 25:27 - Pad output 28 configuration

pub fn cfg27(&mut self) -> CFG27_W

Bits 22:24 - Pad output 27 configuration

pub fn cfg26(&mut self) -> CFG26_W

Bits 19:21 - Pad output 26 configuration

pub fn cfg25(&mut self) -> CFG25_W

Bits 16:18 - Pad output 25 configuration

pub fn cfg24(&mut self) -> CFG24_W

Bits 12:14 - Pad output 24 configuration

pub fn cfg23(&mut self) -> CFG23_W

Bits 9:11 - Pad output 23 configuration

pub fn cfg22(&mut self) -> CFG22_W

Bits 6:8 - Pad output 22 configuration

pub fn cfg21(&mut self) -> CFG21_W

Bits 3:5 - Pad output 21 configuration

pub fn cfg20(&mut self) -> CFG20_W

Bits 0:2 - Pad output 20 configuration

impl W<u32, Reg<u32, _OUTCFG3>>

pub fn cfg31(&mut self) -> CFG31_W

Bits 3:5 - Pad output 31 configuration

pub fn cfg30(&mut self) -> CFG30_W

Bits 0:2 - Pad output 30 configuration

impl W<u32, Reg<u32, _INCFG>>

pub fn cfgb7(&mut self) -> CFGB7_W

Bit 15 - CTIMER B7 input configuration

pub fn cfga7(&mut self) -> CFGA7_W

Bit 14 - CTIMER A7 input configuration

pub fn cfgb6(&mut self) -> CFGB6_W

Bit 13 - CTIMER B6 input configuration

pub fn cfga6(&mut self) -> CFGA6_W

Bit 12 - CTIMER A6 input configuration

pub fn cfgb5(&mut self) -> CFGB5_W

Bit 11 - CTIMER B5 input configuration

pub fn cfga5(&mut self) -> CFGA5_W

Bit 10 - CTIMER A5 input configuration

pub fn cfgb4(&mut self) -> CFGB4_W

Bit 9 - CTIMER B4 input configuration

pub fn cfga4(&mut self) -> CFGA4_W

Bit 8 - CTIMER A4 input configuration

pub fn cfgb3(&mut self) -> CFGB3_W

Bit 7 - CTIMER B3 input configuration

pub fn cfga3(&mut self) -> CFGA3_W

Bit 6 - CTIMER A3 input configuration

pub fn cfgb2(&mut self) -> CFGB2_W

Bit 5 - CTIMER B2 input configuration

pub fn cfga2(&mut self) -> CFGA2_W

Bit 4 - CTIMER A2 input configuration

pub fn cfgb1(&mut self) -> CFGB1_W

Bit 3 - CTIMER B1 input configuration

pub fn cfga1(&mut self) -> CFGA1_W

Bit 2 - CTIMER A1 input configuration

pub fn cfgb0(&mut self) -> CFGB0_W

Bit 1 - CTIMER B0 input configuration

pub fn cfga0(&mut self) -> CFGA0_W

Bit 0 - CTIMER A0 input configuration

impl W<u32, Reg<u32, _STCFG>>

pub fn freeze(&mut self) -> FREEZE_W

Bit 31 - Set this bit to one to freeze the clock input to the COUNTER register. Once frozen, the value can be safely written from the MCU. Unfreeze to resume.

pub fn clear(&mut self) -> CLEAR_W

Bit 30 - Set this bit to one to clear the System Timer register. If this bit is set to '1', the system timer register will stay cleared. It needs to be set to '0' for the system timer to start running.

pub fn compare_h_en(&mut self) -> COMPARE_H_EN_W

Bit 15 - Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparison is met.

pub fn compare_g_en(&mut self) -> COMPARE_G_EN_W

Bit 14 - Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparison is met.

pub fn compare_f_en(&mut self) -> COMPARE_F_EN_W

Bit 13 - Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparison is met.

pub fn compare_e_en(&mut self) -> COMPARE_E_EN_W

Bit 12 - Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparison is met.

pub fn compare_d_en(&mut self) -> COMPARE_D_EN_W

Bit 11 - Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparison is met.

pub fn compare_c_en(&mut self) -> COMPARE_C_EN_W

Bit 10 - Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparison is met.

pub fn compare_b_en(&mut self) -> COMPARE_B_EN_W

Bit 9 - Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparison is met.

pub fn compare_a_en(&mut self) -> COMPARE_A_EN_W

Bit 8 - Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparison is met.

pub fn clksel(&mut self) -> CLKSEL_W

Bits 0:3 - Selects an appropriate clock source and divider to use for the System Timer clock.

impl W<u32, Reg<u32, _STTMR>>

pub fn sttmr(&mut self) -> STTMR_W

Bits 0:31 - Value of the 32-bit counter as it ticks over.

impl W<u32, Reg<u32, _CAPTURECONTROL>>

pub fn capture3(&mut self) -> CAPTURE3_W

Bit 3 - Selects whether capture is enabled for the specified capture register.

pub fn capture2(&mut self) -> CAPTURE2_W

Bit 2 - Selects whether capture is enabled for the specified capture register.

pub fn capture1(&mut self) -> CAPTURE1_W

Bit 1 - Selects whether capture is enabled for the specified capture register.

pub fn capture0(&mut self) -> CAPTURE0_W

Bit 0 - Selects whether capture is enabled for the specified capture register.

impl W<u32, Reg<u32, _SCMPR0>>

pub fn scmpr0(&mut self) -> SCMPR0_W

Bits 0:31 - Compare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_A_EN bit in the REG_CTIMER_STCGF register.

impl W<u32, Reg<u32, _SCMPR1>>

pub fn scmpr1(&mut self) -> SCMPR1_W

Bits 0:31 - Compare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_B_EN bit in the REG_CTIMER_STCGF register.

impl W<u32, Reg<u32, _SCMPR2>>

pub fn scmpr2(&mut self) -> SCMPR2_W

Bits 0:31 - Compare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_C_EN bit in the REG_CTIMER_STCGF register.

impl W<u32, Reg<u32, _SCMPR3>>

pub fn scmpr3(&mut self) -> SCMPR3_W

Bits 0:31 - Compare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_D_EN bit in the REG_CTIMER_STCGF register.

impl W<u32, Reg<u32, _SCMPR4>>

pub fn scmpr4(&mut self) -> SCMPR4_W

Bits 0:31 - Compare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_E_EN bit in the REG_CTIMER_STCGF register.

impl W<u32, Reg<u32, _SCMPR5>>

pub fn scmpr5(&mut self) -> SCMPR5_W

Bits 0:31 - Compare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_F_EN bit in the REG_CTIMER_STCGF register.

impl W<u32, Reg<u32, _SCMPR6>>

pub fn scmpr6(&mut self) -> SCMPR6_W

Bits 0:31 - Compare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_G_EN bit in the REG_CTIMER_STCGF register.

impl W<u32, Reg<u32, _SCMPR7>>

pub fn scmpr7(&mut self) -> SCMPR7_W

Bits 0:31 - Compare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_H_EN bit in the REG_CTIMER_STCGF register.

impl W<u32, Reg<u32, _SCAPT0>>

pub fn scapt0(&mut self) -> SCAPT0_W

Bits 0:31 - Whenever the event is detected, the value in the COUNTER is copied into this register and the corresponding interrupt status bit is set.

impl W<u32, Reg<u32, _SCAPT1>>

pub fn scapt1(&mut self) -> SCAPT1_W

Bits 0:31 - Whenever the event is detected, the value in the COUNTER is copied into this register and the corresponding interrupt status bit is set.

impl W<u32, Reg<u32, _SCAPT2>>

pub fn scapt2(&mut self) -> SCAPT2_W

Bits 0:31 - Whenever the event is detected, the value in the COUNTER is copied into this register and the corresponding interrupt status bit is set.

impl W<u32, Reg<u32, _SCAPT3>>

pub fn scapt3(&mut self) -> SCAPT3_W

Bits 0:31 - Whenever the event is detected, the value in the COUNTER is copied into this register and the corresponding interrupt status bit is set.

impl W<u32, Reg<u32, _SNVR0>>

pub fn snvr0(&mut self) -> SNVR0_W

Bits 0:31 - Value of the 32-bit counter as it ticks over.

impl W<u32, Reg<u32, _SNVR1>>

pub fn snvr1(&mut self) -> SNVR1_W

Bits 0:31 - Value of the 32-bit counter as it ticks over.

impl W<u32, Reg<u32, _SNVR2>>

pub fn snvr2(&mut self) -> SNVR2_W

Bits 0:31 - Value of the 32-bit counter as it ticks over.

impl W<u32, Reg<u32, _SNVR3>>

pub fn snvr3(&mut self) -> SNVR3_W

Bits 0:31 - Value of the 32-bit counter as it ticks over.

impl W<u32, Reg<u32, _INTEN>>

pub fn ctmrb7c1int(&mut self) -> CTMRB7C1INT_W

Bit 31 - Counter/Timer B7 interrupt based on COMPR1.

pub fn ctmra7c1int(&mut self) -> CTMRA7C1INT_W

Bit 30 - Counter/Timer A7 interrupt based on COMPR1.

pub fn ctmrb6c1int(&mut self) -> CTMRB6C1INT_W

Bit 29 - Counter/Timer B6 interrupt based on COMPR1.

pub fn ctmra6c1int(&mut self) -> CTMRA6C1INT_W

Bit 28 - Counter/Timer A6 interrupt based on COMPR1.

pub fn ctmrb5c1int(&mut self) -> CTMRB5C1INT_W

Bit 27 - Counter/Timer B5 interrupt based on COMPR1.

pub fn ctmra5c1int(&mut self) -> CTMRA5C1INT_W

Bit 26 - Counter/Timer A5 interrupt based on COMPR1.

pub fn ctmrb4c1int(&mut self) -> CTMRB4C1INT_W

Bit 25 - Counter/Timer B4 interrupt based on COMPR1.

pub fn ctmra4c1int(&mut self) -> CTMRA4C1INT_W

Bit 24 - Counter/Timer A4 interrupt based on COMPR1.

pub fn ctmrb3c1int(&mut self) -> CTMRB3C1INT_W

Bit 23 - Counter/Timer B3 interrupt based on COMPR1.

pub fn ctmra3c1int(&mut self) -> CTMRA3C1INT_W

Bit 22 - Counter/Timer A3 interrupt based on COMPR1.

pub fn ctmrb2c1int(&mut self) -> CTMRB2C1INT_W

Bit 21 - Counter/Timer B2 interrupt based on COMPR1.

pub fn ctmra2c1int(&mut self) -> CTMRA2C1INT_W

Bit 20 - Counter/Timer A2 interrupt based on COMPR1.

pub fn ctmrb1c1int(&mut self) -> CTMRB1C1INT_W

Bit 19 - Counter/Timer B1 interrupt based on COMPR1.

pub fn ctmra1c1int(&mut self) -> CTMRA1C1INT_W

Bit 18 - Counter/Timer A1 interrupt based on COMPR1.

pub fn ctmrb0c1int(&mut self) -> CTMRB0C1INT_W

Bit 17 - Counter/Timer B0 interrupt based on COMPR1.

pub fn ctmra0c1int(&mut self) -> CTMRA0C1INT_W

Bit 16 - Counter/Timer A0 interrupt based on COMPR1.

pub fn ctmrb7c0int(&mut self) -> CTMRB7C0INT_W

Bit 15 - Counter/Timer B7 interrupt based on COMPR0.

pub fn ctmra7c0int(&mut self) -> CTMRA7C0INT_W

Bit 14 - Counter/Timer A7 interrupt based on COMPR0.

pub fn ctmrb6c0int(&mut self) -> CTMRB6C0INT_W

Bit 13 - Counter/Timer B6 interrupt based on COMPR0.

pub fn ctmra6c0int(&mut self) -> CTMRA6C0INT_W

Bit 12 - Counter/Timer A6 interrupt based on COMPR0.

pub fn ctmrb5c0int(&mut self) -> CTMRB5C0INT_W

Bit 11 - Counter/Timer B5 interrupt based on COMPR0.

pub fn ctmra5c0int(&mut self) -> CTMRA5C0INT_W

Bit 10 - Counter/Timer A5 interrupt based on COMPR0.

pub fn ctmrb4c0int(&mut self) -> CTMRB4C0INT_W

Bit 9 - Counter/Timer B4 interrupt based on COMPR0.

pub fn ctmra4c0int(&mut self) -> CTMRA4C0INT_W

Bit 8 - Counter/Timer A4 interrupt based on COMPR0.

pub fn ctmrb3c0int(&mut self) -> CTMRB3C0INT_W

Bit 7 - Counter/Timer B3 interrupt based on COMPR0.

pub fn ctmra3c0int(&mut self) -> CTMRA3C0INT_W

Bit 6 - Counter/Timer A3 interrupt based on COMPR0.

pub fn ctmrb2c0int(&mut self) -> CTMRB2C0INT_W

Bit 5 - Counter/Timer B2 interrupt based on COMPR0.

pub fn ctmra2c0int(&mut self) -> CTMRA2C0INT_W

Bit 4 - Counter/Timer A2 interrupt based on COMPR0.

pub fn ctmrb1c0int(&mut self) -> CTMRB1C0INT_W

Bit 3 - Counter/Timer B1 interrupt based on COMPR0.

pub fn ctmra1c0int(&mut self) -> CTMRA1C0INT_W

Bit 2 - Counter/Timer A1 interrupt based on COMPR0.

pub fn ctmrb0c0int(&mut self) -> CTMRB0C0INT_W

Bit 1 - Counter/Timer B0 interrupt based on COMPR0.

pub fn ctmra0c0int(&mut self) -> CTMRA0C0INT_W

Bit 0 - Counter/Timer A0 interrupt based on COMPR0.

impl W<u32, Reg<u32, _INTSTAT>>

pub fn ctmrb7c1int(&mut self) -> CTMRB7C1INT_W

Bit 31 - Counter/Timer B7 interrupt based on COMPR1.

pub fn ctmra7c1int(&mut self) -> CTMRA7C1INT_W

Bit 30 - Counter/Timer A7 interrupt based on COMPR1.

pub fn ctmrb6c1int(&mut self) -> CTMRB6C1INT_W

Bit 29 - Counter/Timer B6 interrupt based on COMPR1.

pub fn ctmra6c1int(&mut self) -> CTMRA6C1INT_W

Bit 28 - Counter/Timer A6 interrupt based on COMPR1.

pub fn ctmrb5c1int(&mut self) -> CTMRB5C1INT_W

Bit 27 - Counter/Timer B5 interrupt based on COMPR1.

pub fn ctmra5c1int(&mut self) -> CTMRA5C1INT_W

Bit 26 - Counter/Timer A5 interrupt based on COMPR1.

pub fn ctmrb4c1int(&mut self) -> CTMRB4C1INT_W

Bit 25 - Counter/Timer B4 interrupt based on COMPR1.

pub fn ctmra4c1int(&mut self) -> CTMRA4C1INT_W

Bit 24 - Counter/Timer A4 interrupt based on COMPR1.

pub fn ctmrb3c1int(&mut self) -> CTMRB3C1INT_W

Bit 23 - Counter/Timer B3 interrupt based on COMPR1.

pub fn ctmra3c1int(&mut self) -> CTMRA3C1INT_W

Bit 22 - Counter/Timer A3 interrupt based on COMPR1.

pub fn ctmrb2c1int(&mut self) -> CTMRB2C1INT_W

Bit 21 - Counter/Timer B2 interrupt based on COMPR1.

pub fn ctmra2c1int(&mut self) -> CTMRA2C1INT_W

Bit 20 - Counter/Timer A2 interrupt based on COMPR1.

pub fn ctmrb1c1int(&mut self) -> CTMRB1C1INT_W

Bit 19 - Counter/Timer B1 interrupt based on COMPR1.

pub fn ctmra1c1int(&mut self) -> CTMRA1C1INT_W

Bit 18 - Counter/Timer A1 interrupt based on COMPR1.

pub fn ctmrb0c1int(&mut self) -> CTMRB0C1INT_W

Bit 17 - Counter/Timer B0 interrupt based on COMPR1.

pub fn ctmra0c1int(&mut self) -> CTMRA0C1INT_W

Bit 16 - Counter/Timer A0 interrupt based on COMPR1.

pub fn ctmrb7c0int(&mut self) -> CTMRB7C0INT_W

Bit 15 - Counter/Timer B7 interrupt based on COMPR0.

pub fn ctmra7c0int(&mut self) -> CTMRA7C0INT_W

Bit 14 - Counter/Timer A7 interrupt based on COMPR0.

pub fn ctmrb6c0int(&mut self) -> CTMRB6C0INT_W

Bit 13 - Counter/Timer B6 interrupt based on COMPR0.

pub fn ctmra6c0int(&mut self) -> CTMRA6C0INT_W

Bit 12 - Counter/Timer A6 interrupt based on COMPR0.

pub fn ctmrb5c0int(&mut self) -> CTMRB5C0INT_W

Bit 11 - Counter/Timer B5 interrupt based on COMPR0.

pub fn ctmra5c0int(&mut self) -> CTMRA5C0INT_W

Bit 10 - Counter/Timer A5 interrupt based on COMPR0.

pub fn ctmrb4c0int(&mut self) -> CTMRB4C0INT_W

Bit 9 - Counter/Timer B4 interrupt based on COMPR0.

pub fn ctmra4c0int(&mut self) -> CTMRA4C0INT_W

Bit 8 - Counter/Timer A4 interrupt based on COMPR0.

pub fn ctmrb3c0int(&mut self) -> CTMRB3C0INT_W

Bit 7 - Counter/Timer B3 interrupt based on COMPR0.

pub fn ctmra3c0int(&mut self) -> CTMRA3C0INT_W

Bit 6 - Counter/Timer A3 interrupt based on COMPR0.

pub fn ctmrb2c0int(&mut self) -> CTMRB2C0INT_W

Bit 5 - Counter/Timer B2 interrupt based on COMPR0.

pub fn ctmra2c0int(&mut self) -> CTMRA2C0INT_W

Bit 4 - Counter/Timer A2 interrupt based on COMPR0.

pub fn ctmrb1c0int(&mut self) -> CTMRB1C0INT_W

Bit 3 - Counter/Timer B1 interrupt based on COMPR0.

pub fn ctmra1c0int(&mut self) -> CTMRA1C0INT_W

Bit 2 - Counter/Timer A1 interrupt based on COMPR0.

pub fn ctmrb0c0int(&mut self) -> CTMRB0C0INT_W

Bit 1 - Counter/Timer B0 interrupt based on COMPR0.

pub fn ctmra0c0int(&mut self) -> CTMRA0C0INT_W

Bit 0 - Counter/Timer A0 interrupt based on COMPR0.

impl W<u32, Reg<u32, _INTCLR>>

pub fn ctmrb7c1int(&mut self) -> CTMRB7C1INT_W

Bit 31 - Counter/Timer B7 interrupt based on COMPR1.

pub fn ctmra7c1int(&mut self) -> CTMRA7C1INT_W

Bit 30 - Counter/Timer A7 interrupt based on COMPR1.

pub fn ctmrb6c1int(&mut self) -> CTMRB6C1INT_W

Bit 29 - Counter/Timer B6 interrupt based on COMPR1.

pub fn ctmra6c1int(&mut self) -> CTMRA6C1INT_W

Bit 28 - Counter/Timer A6 interrupt based on COMPR1.

pub fn ctmrb5c1int(&mut self) -> CTMRB5C1INT_W

Bit 27 - Counter/Timer B5 interrupt based on COMPR1.

pub fn ctmra5c1int(&mut self) -> CTMRA5C1INT_W

Bit 26 - Counter/Timer A5 interrupt based on COMPR1.

pub fn ctmrb4c1int(&mut self) -> CTMRB4C1INT_W

Bit 25 - Counter/Timer B4 interrupt based on COMPR1.

pub fn ctmra4c1int(&mut self) -> CTMRA4C1INT_W

Bit 24 - Counter/Timer A4 interrupt based on COMPR1.

pub fn ctmrb3c1int(&mut self) -> CTMRB3C1INT_W

Bit 23 - Counter/Timer B3 interrupt based on COMPR1.

pub fn ctmra3c1int(&mut self) -> CTMRA3C1INT_W

Bit 22 - Counter/Timer A3 interrupt based on COMPR1.

pub fn ctmrb2c1int(&mut self) -> CTMRB2C1INT_W

Bit 21 - Counter/Timer B2 interrupt based on COMPR1.

pub fn ctmra2c1int(&mut self) -> CTMRA2C1INT_W

Bit 20 - Counter/Timer A2 interrupt based on COMPR1.

pub fn ctmrb1c1int(&mut self) -> CTMRB1C1INT_W

Bit 19 - Counter/Timer B1 interrupt based on COMPR1.

pub fn ctmra1c1int(&mut self) -> CTMRA1C1INT_W

Bit 18 - Counter/Timer A1 interrupt based on COMPR1.

pub fn ctmrb0c1int(&mut self) -> CTMRB0C1INT_W

Bit 17 - Counter/Timer B0 interrupt based on COMPR1.

pub fn ctmra0c1int(&mut self) -> CTMRA0C1INT_W

Bit 16 - Counter/Timer A0 interrupt based on COMPR1.

pub fn ctmrb7c0int(&mut self) -> CTMRB7C0INT_W

Bit 15 - Counter/Timer B7 interrupt based on COMPR0.

pub fn ctmra7c0int(&mut self) -> CTMRA7C0INT_W

Bit 14 - Counter/Timer A7 interrupt based on COMPR0.

pub fn ctmrb6c0int(&mut self) -> CTMRB6C0INT_W

Bit 13 - Counter/Timer B6 interrupt based on COMPR0.

pub fn ctmra6c0int(&mut self) -> CTMRA6C0INT_W

Bit 12 - Counter/Timer A6 interrupt based on COMPR0.

pub fn ctmrb5c0int(&mut self) -> CTMRB5C0INT_W

Bit 11 - Counter/Timer B5 interrupt based on COMPR0.

pub fn ctmra5c0int(&mut self) -> CTMRA5C0INT_W

Bit 10 - Counter/Timer A5 interrupt based on COMPR0.

pub fn ctmrb4c0int(&mut self) -> CTMRB4C0INT_W

Bit 9 - Counter/Timer B4 interrupt based on COMPR0.

pub fn ctmra4c0int(&mut self) -> CTMRA4C0INT_W

Bit 8 - Counter/Timer A4 interrupt based on COMPR0.

pub fn ctmrb3c0int(&mut self) -> CTMRB3C0INT_W

Bit 7 - Counter/Timer B3 interrupt based on COMPR0.

pub fn ctmra3c0int(&mut self) -> CTMRA3C0INT_W

Bit 6 - Counter/Timer A3 interrupt based on COMPR0.

pub fn ctmrb2c0int(&mut self) -> CTMRB2C0INT_W

Bit 5 - Counter/Timer B2 interrupt based on COMPR0.

pub fn ctmra2c0int(&mut self) -> CTMRA2C0INT_W

Bit 4 - Counter/Timer A2 interrupt based on COMPR0.

pub fn ctmrb1c0int(&mut self) -> CTMRB1C0INT_W

Bit 3 - Counter/Timer B1 interrupt based on COMPR0.

pub fn ctmra1c0int(&mut self) -> CTMRA1C0INT_W

Bit 2 - Counter/Timer A1 interrupt based on COMPR0.

pub fn ctmrb0c0int(&mut self) -> CTMRB0C0INT_W

Bit 1 - Counter/Timer B0 interrupt based on COMPR0.

pub fn ctmra0c0int(&mut self) -> CTMRA0C0INT_W

Bit 0 - Counter/Timer A0 interrupt based on COMPR0.

impl W<u32, Reg<u32, _INTSET>>

pub fn ctmrb7c1int(&mut self) -> CTMRB7C1INT_W

Bit 31 - Counter/Timer B7 interrupt based on COMPR1.

pub fn ctmra7c1int(&mut self) -> CTMRA7C1INT_W

Bit 30 - Counter/Timer A7 interrupt based on COMPR1.

pub fn ctmrb6c1int(&mut self) -> CTMRB6C1INT_W

Bit 29 - Counter/Timer B6 interrupt based on COMPR1.

pub fn ctmra6c1int(&mut self) -> CTMRA6C1INT_W

Bit 28 - Counter/Timer A6 interrupt based on COMPR1.

pub fn ctmrb5c1int(&mut self) -> CTMRB5C1INT_W

Bit 27 - Counter/Timer B5 interrupt based on COMPR1.

pub fn ctmra5c1int(&mut self) -> CTMRA5C1INT_W

Bit 26 - Counter/Timer A5 interrupt based on COMPR1.

pub fn ctmrb4c1int(&mut self) -> CTMRB4C1INT_W

Bit 25 - Counter/Timer B4 interrupt based on COMPR1.

pub fn ctmra4c1int(&mut self) -> CTMRA4C1INT_W

Bit 24 - Counter/Timer A4 interrupt based on COMPR1.

pub fn ctmrb3c1int(&mut self) -> CTMRB3C1INT_W

Bit 23 - Counter/Timer B3 interrupt based on COMPR1.

pub fn ctmra3c1int(&mut self) -> CTMRA3C1INT_W

Bit 22 - Counter/Timer A3 interrupt based on COMPR1.

pub fn ctmrb2c1int(&mut self) -> CTMRB2C1INT_W

Bit 21 - Counter/Timer B2 interrupt based on COMPR1.

pub fn ctmra2c1int(&mut self) -> CTMRA2C1INT_W

Bit 20 - Counter/Timer A2 interrupt based on COMPR1.

pub fn ctmrb1c1int(&mut self) -> CTMRB1C1INT_W

Bit 19 - Counter/Timer B1 interrupt based on COMPR1.

pub fn ctmra1c1int(&mut self) -> CTMRA1C1INT_W

Bit 18 - Counter/Timer A1 interrupt based on COMPR1.

pub fn ctmrb0c1int(&mut self) -> CTMRB0C1INT_W

Bit 17 - Counter/Timer B0 interrupt based on COMPR1.

pub fn ctmra0c1int(&mut self) -> CTMRA0C1INT_W

Bit 16 - Counter/Timer A0 interrupt based on COMPR1.

pub fn ctmrb7c0int(&mut self) -> CTMRB7C0INT_W

Bit 15 - Counter/Timer B7 interrupt based on COMPR0.

pub fn ctmra7c0int(&mut self) -> CTMRA7C0INT_W

Bit 14 - Counter/Timer A7 interrupt based on COMPR0.

pub fn ctmrb6c0int(&mut self) -> CTMRB6C0INT_W

Bit 13 - Counter/Timer B6 interrupt based on COMPR0.

pub fn ctmra6c0int(&mut self) -> CTMRA6C0INT_W

Bit 12 - Counter/Timer A6 interrupt based on COMPR0.

pub fn ctmrb5c0int(&mut self) -> CTMRB5C0INT_W

Bit 11 - Counter/Timer B5 interrupt based on COMPR0.

pub fn ctmra5c0int(&mut self) -> CTMRA5C0INT_W

Bit 10 - Counter/Timer A5 interrupt based on COMPR0.

pub fn ctmrb4c0int(&mut self) -> CTMRB4C0INT_W

Bit 9 - Counter/Timer B4 interrupt based on COMPR0.

pub fn ctmra4c0int(&mut self) -> CTMRA4C0INT_W

Bit 8 - Counter/Timer A4 interrupt based on COMPR0.

pub fn ctmrb3c0int(&mut self) -> CTMRB3C0INT_W

Bit 7 - Counter/Timer B3 interrupt based on COMPR0.

pub fn ctmra3c0int(&mut self) -> CTMRA3C0INT_W

Bit 6 - Counter/Timer A3 interrupt based on COMPR0.

pub fn ctmrb2c0int(&mut self) -> CTMRB2C0INT_W

Bit 5 - Counter/Timer B2 interrupt based on COMPR0.

pub fn ctmra2c0int(&mut self) -> CTMRA2C0INT_W

Bit 4 - Counter/Timer A2 interrupt based on COMPR0.

pub fn ctmrb1c0int(&mut self) -> CTMRB1C0INT_W

Bit 3 - Counter/Timer B1 interrupt based on COMPR0.

pub fn ctmra1c0int(&mut self) -> CTMRA1C0INT_W

Bit 2 - Counter/Timer A1 interrupt based on COMPR0.

pub fn ctmrb0c0int(&mut self) -> CTMRB0C0INT_W

Bit 1 - Counter/Timer B0 interrupt based on COMPR0.

pub fn ctmra0c0int(&mut self) -> CTMRA0C0INT_W

Bit 0 - Counter/Timer A0 interrupt based on COMPR0.

impl W<u32, Reg<u32, _STMINTEN>>

pub fn captured(&mut self) -> CAPTURED_W

Bit 12 - CAPTURE register D has grabbed the value in the counter

pub fn capturec(&mut self) -> CAPTUREC_W

Bit 11 - CAPTURE register C has grabbed the value in the counter

pub fn captureb(&mut self) -> CAPTUREB_W

Bit 10 - CAPTURE register B has grabbed the value in the counter

pub fn capturea(&mut self) -> CAPTUREA_W

Bit 9 - CAPTURE register A has grabbed the value in the counter

pub fn overflow(&mut self) -> OVERFLOW_W

Bit 8 - COUNTER over flowed from 0xFFFFFFFF back to 0x00000000.

pub fn compareh(&mut self) -> COMPAREH_W

Bit 7 - COUNTER is greater than or equal to COMPARE register H.

pub fn compareg(&mut self) -> COMPAREG_W

Bit 6 - COUNTER is greater than or equal to COMPARE register G.

pub fn comparef(&mut self) -> COMPAREF_W

Bit 5 - COUNTER is greater than or equal to COMPARE register F.

pub fn comparee(&mut self) -> COMPAREE_W

Bit 4 - COUNTER is greater than or equal to COMPARE register E.

pub fn compared(&mut self) -> COMPARED_W

Bit 3 - COUNTER is greater than or equal to COMPARE register D.

pub fn comparec(&mut self) -> COMPAREC_W

Bit 2 - COUNTER is greater than or equal to COMPARE register C.

pub fn compareb(&mut self) -> COMPAREB_W

Bit 1 - COUNTER is greater than or equal to COMPARE register B.

pub fn comparea(&mut self) -> COMPAREA_W

Bit 0 - COUNTER is greater than or equal to COMPARE register A.

impl W<u32, Reg<u32, _STMINTSTAT>>

pub fn captured(&mut self) -> CAPTURED_W

Bit 12 - CAPTURE register D has grabbed the value in the counter

pub fn capturec(&mut self) -> CAPTUREC_W

Bit 11 - CAPTURE register C has grabbed the value in the counter

pub fn captureb(&mut self) -> CAPTUREB_W

Bit 10 - CAPTURE register B has grabbed the value in the counter

pub fn capturea(&mut self) -> CAPTUREA_W

Bit 9 - CAPTURE register A has grabbed the value in the counter

pub fn overflow(&mut self) -> OVERFLOW_W

Bit 8 - COUNTER over flowed from 0xFFFFFFFF back to 0x00000000.

pub fn compareh(&mut self) -> COMPAREH_W

Bit 7 - COUNTER is greater than or equal to COMPARE register H.

pub fn compareg(&mut self) -> COMPAREG_W

Bit 6 - COUNTER is greater than or equal to COMPARE register G.

pub fn comparef(&mut self) -> COMPAREF_W

Bit 5 - COUNTER is greater than or equal to COMPARE register F.

pub fn comparee(&mut self) -> COMPAREE_W

Bit 4 - COUNTER is greater than or equal to COMPARE register E.

pub fn compared(&mut self) -> COMPARED_W

Bit 3 - COUNTER is greater than or equal to COMPARE register D.

pub fn comparec(&mut self) -> COMPAREC_W

Bit 2 - COUNTER is greater than or equal to COMPARE register C.

pub fn compareb(&mut self) -> COMPAREB_W

Bit 1 - COUNTER is greater than or equal to COMPARE register B.

pub fn comparea(&mut self) -> COMPAREA_W

Bit 0 - COUNTER is greater than or equal to COMPARE register A.

impl W<u32, Reg<u32, _STMINTCLR>>

pub fn captured(&mut self) -> CAPTURED_W

Bit 12 - CAPTURE register D has grabbed the value in the counter

pub fn capturec(&mut self) -> CAPTUREC_W

Bit 11 - CAPTURE register C has grabbed the value in the counter

pub fn captureb(&mut self) -> CAPTUREB_W

Bit 10 - CAPTURE register B has grabbed the value in the counter

pub fn capturea(&mut self) -> CAPTUREA_W

Bit 9 - CAPTURE register A has grabbed the value in the counter

pub fn overflow(&mut self) -> OVERFLOW_W

Bit 8 - COUNTER over flowed from 0xFFFFFFFF back to 0x00000000.

pub fn compareh(&mut self) -> COMPAREH_W

Bit 7 - COUNTER is greater than or equal to COMPARE register H.

pub fn compareg(&mut self) -> COMPAREG_W

Bit 6 - COUNTER is greater than or equal to COMPARE register G.

pub fn comparef(&mut self) -> COMPAREF_W

Bit 5 - COUNTER is greater than or equal to COMPARE register F.

pub fn comparee(&mut self) -> COMPAREE_W

Bit 4 - COUNTER is greater than or equal to COMPARE register E.

pub fn compared(&mut self) -> COMPARED_W

Bit 3 - COUNTER is greater than or equal to COMPARE register D.

pub fn comparec(&mut self) -> COMPAREC_W

Bit 2 - COUNTER is greater than or equal to COMPARE register C.

pub fn compareb(&mut self) -> COMPAREB_W

Bit 1 - COUNTER is greater than or equal to COMPARE register B.

pub fn comparea(&mut self) -> COMPAREA_W

Bit 0 - COUNTER is greater than or equal to COMPARE register A.

impl W<u32, Reg<u32, _STMINTSET>>

pub fn captured(&mut self) -> CAPTURED_W

Bit 12 - CAPTURE register D has grabbed the value in the counter

pub fn capturec(&mut self) -> CAPTUREC_W

Bit 11 - CAPTURE register C has grabbed the value in the counter

pub fn captureb(&mut self) -> CAPTUREB_W

Bit 10 - CAPTURE register B has grabbed the value in the counter

pub fn capturea(&mut self) -> CAPTUREA_W

Bit 9 - CAPTURE register A has grabbed the value in the counter

pub fn overflow(&mut self) -> OVERFLOW_W

Bit 8 - COUNTER over flowed from 0xFFFFFFFF back to 0x00000000.

pub fn compareh(&mut self) -> COMPAREH_W

Bit 7 - COUNTER is greater than or equal to COMPARE register H.

pub fn compareg(&mut self) -> COMPAREG_W

Bit 6 - COUNTER is greater than or equal to COMPARE register G.

pub fn comparef(&mut self) -> COMPAREF_W

Bit 5 - COUNTER is greater than or equal to COMPARE register F.

pub fn comparee(&mut self) -> COMPAREE_W

Bit 4 - COUNTER is greater than or equal to COMPARE register E.

pub fn compared(&mut self) -> COMPARED_W

Bit 3 - COUNTER is greater than or equal to COMPARE register D.

pub fn comparec(&mut self) -> COMPAREC_W

Bit 2 - COUNTER is greater than or equal to COMPARE register C.

pub fn compareb(&mut self) -> COMPAREB_W

Bit 1 - COUNTER is greater than or equal to COMPARE register B.

pub fn comparea(&mut self) -> COMPAREA_W

Bit 0 - COUNTER is greater than or equal to COMPARE register A.

impl W<u32, Reg<u32, _PADREGA>>

pub fn pad3pwrup(&mut self) -> PAD3PWRUP_W

Bit 30 - Pad 3 VDD power switch enable

pub fn pad3fncsel(&mut self) -> PAD3FNCSEL_W

Bits 27:29 - Pad 3 function select

pub fn pad3strng(&mut self) -> PAD3STRNG_W

Bit 26 - Pad 3 drive strength.

pub fn pad3inpen(&mut self) -> PAD3INPEN_W

Bit 25 - Pad 3 input enable.

pub fn pad3pull(&mut self) -> PAD3PULL_W

Bit 24 - Pad 3 pullup enable

pub fn pad2fncsel(&mut self) -> PAD2FNCSEL_W

Bits 19:21 - Pad 2 function select

pub fn pad2strng(&mut self) -> PAD2STRNG_W

Bit 18 - Pad 2 drive strength

pub fn pad2inpen(&mut self) -> PAD2INPEN_W

Bit 17 - Pad 2 input enable

pub fn pad2pull(&mut self) -> PAD2PULL_W

Bit 16 - Pad 2 pullup enable

pub fn pad1rsel(&mut self) -> PAD1RSEL_W

Bits 14:15 - Pad 1 pullup resistor selection.

pub fn pad1fncsel(&mut self) -> PAD1FNCSEL_W

Bits 11:13 - Pad 1 function select

pub fn pad1strng(&mut self) -> PAD1STRNG_W

Bit 10 - Pad 1 drive strength

pub fn pad1inpen(&mut self) -> PAD1INPEN_W

Bit 9 - Pad 1 input enable

pub fn pad1pull(&mut self) -> PAD1PULL_W

Bit 8 - Pad 1 pullup enable

pub fn pad0rsel(&mut self) -> PAD0RSEL_W

Bits 6:7 - Pad 0 pullup resistor selection.

pub fn pad0fncsel(&mut self) -> PAD0FNCSEL_W

Bits 3:5 - Pad 0 function select

pub fn pad0strng(&mut self) -> PAD0STRNG_W

Bit 2 - Pad 0 drive strength

pub fn pad0inpen(&mut self) -> PAD0INPEN_W

Bit 1 - Pad 0 input enable

pub fn pad0pull(&mut self) -> PAD0PULL_W

Bit 0 - Pad 0 pullup enable

impl W<u32, Reg<u32, _PADREGB>>

pub fn pad7fncsel(&mut self) -> PAD7FNCSEL_W

Bits 27:29 - Pad 7 function select

pub fn pad7strng(&mut self) -> PAD7STRNG_W

Bit 26 - Pad 7 drive strength

pub fn pad7inpen(&mut self) -> PAD7INPEN_W

Bit 25 - Pad 7 input enable

pub fn pad7pull(&mut self) -> PAD7PULL_W

Bit 24 - Pad 7 pullup enable

pub fn pad6rsel(&mut self) -> PAD6RSEL_W

Bits 22:23 - Pad 6 pullup resistor selection.

pub fn pad6fncsel(&mut self) -> PAD6FNCSEL_W

Bits 19:21 - Pad 6 function select

pub fn pad6strng(&mut self) -> PAD6STRNG_W

Bit 18 - Pad 6 drive strength

pub fn pad6inpen(&mut self) -> PAD6INPEN_W

Bit 17 - Pad 6 input enable

pub fn pad6pull(&mut self) -> PAD6PULL_W

Bit 16 - Pad 6 pullup enable

pub fn pad5rsel(&mut self) -> PAD5RSEL_W

Bits 14:15 - Pad 5 pullup resistor selection.

pub fn pad5fncsel(&mut self) -> PAD5FNCSEL_W

Bits 11:13 - Pad 5 function select

pub fn pad5strng(&mut self) -> PAD5STRNG_W

Bit 10 - Pad 5 drive strength

pub fn pad5inpen(&mut self) -> PAD5INPEN_W

Bit 9 - Pad 5 input enable

pub fn pad5pull(&mut self) -> PAD5PULL_W

Bit 8 - Pad 5 pullup enable

pub fn pad4fncsel(&mut self) -> PAD4FNCSEL_W

Bits 3:5 - Pad 4 function select

pub fn pad4strng(&mut self) -> PAD4STRNG_W

Bit 2 - Pad 4 drive strength

pub fn pad4inpen(&mut self) -> PAD4INPEN_W

Bit 1 - Pad 4 input enable

pub fn pad4pull(&mut self) -> PAD4PULL_W

Bit 0 - Pad 4 pullup enable

impl W<u32, Reg<u32, _PADREGC>>

pub fn pad11fncsel(&mut self) -> PAD11FNCSEL_W

Bits 27:29 - Pad 11 function select

pub fn pad11strng(&mut self) -> PAD11STRNG_W

Bit 26 - Pad 11 drive strength

pub fn pad11inpen(&mut self) -> PAD11INPEN_W

Bit 25 - Pad 11 input enable

pub fn pad11pull(&mut self) -> PAD11PULL_W

Bit 24 - Pad 11 pullup enable

pub fn pad10fncsel(&mut self) -> PAD10FNCSEL_W

Bits 19:21 - Pad 10 function select

pub fn pad10strng(&mut self) -> PAD10STRNG_W

Bit 18 - Pad 10 drive strength

pub fn pad10inpen(&mut self) -> PAD10INPEN_W

Bit 17 - Pad 10 input enable

pub fn pad10pull(&mut self) -> PAD10PULL_W

Bit 16 - Pad 10 pullup enable

pub fn pad9rsel(&mut self) -> PAD9RSEL_W

Bits 14:15 - Pad 9 pullup resistor selection

pub fn pad9fncsel(&mut self) -> PAD9FNCSEL_W

Bits 11:13 - Pad 9 function select

pub fn pad9strng(&mut self) -> PAD9STRNG_W

Bit 10 - Pad 9 drive strength

pub fn pad9inpen(&mut self) -> PAD9INPEN_W

Bit 9 - Pad 9 input enable

pub fn pad9pull(&mut self) -> PAD9PULL_W

Bit 8 - Pad 9 pullup enable

pub fn pad8rsel(&mut self) -> PAD8RSEL_W

Bits 6:7 - Pad 8 pullup resistor selection.

pub fn pad8fncsel(&mut self) -> PAD8FNCSEL_W

Bits 3:5 - Pad 8 function select

pub fn pad8strng(&mut self) -> PAD8STRNG_W

Bit 2 - Pad 8 drive strength

pub fn pad8inpen(&mut self) -> PAD8INPEN_W

Bit 1 - Pad 8 input enable

pub fn pad8pull(&mut self) -> PAD8PULL_W

Bit 0 - Pad 8 pullup enable

impl W<u32, Reg<u32, _PADREGD>>

pub fn pad15fncsel(&mut self) -> PAD15FNCSEL_W

Bits 27:29 - Pad 15 function select

pub fn pad15strng(&mut self) -> PAD15STRNG_W

Bit 26 - Pad 15 drive strength

pub fn pad15inpen(&mut self) -> PAD15INPEN_W

Bit 25 - Pad 15 input enable

pub fn pad15pull(&mut self) -> PAD15PULL_W

Bit 24 - Pad 15 pullup enable

pub fn pad14fncsel(&mut self) -> PAD14FNCSEL_W

Bits 19:21 - Pad 14 function select

pub fn pad14strng(&mut self) -> PAD14STRNG_W

Bit 18 - Pad 14 drive strength

pub fn pad14inpen(&mut self) -> PAD14INPEN_W

Bit 17 - Pad 14 input enable

pub fn pad14pull(&mut self) -> PAD14PULL_W

Bit 16 - Pad 14 pullup enable

pub fn pad13fncsel(&mut self) -> PAD13FNCSEL_W

Bits 11:13 - Pad 13 function select

pub fn pad13strng(&mut self) -> PAD13STRNG_W

Bit 10 - Pad 13 drive strength

pub fn pad13inpen(&mut self) -> PAD13INPEN_W

Bit 9 - Pad 13 input enable

pub fn pad13pull(&mut self) -> PAD13PULL_W

Bit 8 - Pad 13 pullup enable

pub fn pad12fncsel(&mut self) -> PAD12FNCSEL_W

Bits 3:5 - Pad 12 function select

pub fn pad12strng(&mut self) -> PAD12STRNG_W

Bit 2 - Pad 12 drive strength

pub fn pad12inpen(&mut self) -> PAD12INPEN_W

Bit 1 - Pad 12 input enable

pub fn pad12pull(&mut self) -> PAD12PULL_W

Bit 0 - Pad 12 pullup enable

impl W<u32, Reg<u32, _PADREGE>>

pub fn pad19fncsel(&mut self) -> PAD19FNCSEL_W

Bits 27:29 - Pad 19 function select

pub fn pad19strng(&mut self) -> PAD19STRNG_W

Bit 26 - Pad 19 drive strength

pub fn pad19inpen(&mut self) -> PAD19INPEN_W

Bit 25 - Pad 19 input enable

pub fn pad19pull(&mut self) -> PAD19PULL_W

Bit 24 - Pad 19 pullup enable

pub fn pad18fncsel(&mut self) -> PAD18FNCSEL_W

Bits 19:21 - Pad 18 function select

pub fn pad18strng(&mut self) -> PAD18STRNG_W

Bit 18 - Pad 18 drive strength

pub fn pad18inpen(&mut self) -> PAD18INPEN_W

Bit 17 - Pad 18 input enable

pub fn pad18pull(&mut self) -> PAD18PULL_W

Bit 16 - Pad 18 pullup enable

pub fn pad17fncsel(&mut self) -> PAD17FNCSEL_W

Bits 11:13 - Pad 17 function select

pub fn pad17strng(&mut self) -> PAD17STRNG_W

Bit 10 - Pad 17 drive strength

pub fn pad17inpen(&mut self) -> PAD17INPEN_W

Bit 9 - Pad 17 input enable

pub fn pad17pull(&mut self) -> PAD17PULL_W

Bit 8 - Pad 17 pullup enable

pub fn pad16fncsel(&mut self) -> PAD16FNCSEL_W

Bits 3:5 - Pad 16 function select

pub fn pad16strng(&mut self) -> PAD16STRNG_W

Bit 2 - Pad 16 drive strength

pub fn pad16inpen(&mut self) -> PAD16INPEN_W

Bit 1 - Pad 16 input enable

pub fn pad16pull(&mut self) -> PAD16PULL_W

Bit 0 - Pad 16 pullup enable

impl W<u32, Reg<u32, _PADREGF>>

pub fn pad23fncsel(&mut self) -> PAD23FNCSEL_W

Bits 27:29 - Pad 23 function select

pub fn pad23strng(&mut self) -> PAD23STRNG_W

Bit 26 - Pad 23 drive strength

pub fn pad23inpen(&mut self) -> PAD23INPEN_W

Bit 25 - Pad 23 input enable

pub fn pad23pull(&mut self) -> PAD23PULL_W

Bit 24 - Pad 23 pullup enable

pub fn pad22fncsel(&mut self) -> PAD22FNCSEL_W

Bits 19:21 - Pad 22 function select

pub fn pad22strng(&mut self) -> PAD22STRNG_W

Bit 18 - Pad 22 drive strength

pub fn pad22inpen(&mut self) -> PAD22INPEN_W

Bit 17 - Pad 22 input enable

pub fn pad22pull(&mut self) -> PAD22PULL_W

Bit 16 - Pad 22 pullup enable

pub fn pad21fncsel(&mut self) -> PAD21FNCSEL_W

Bits 11:13 - Pad 21 function select

pub fn pad21strng(&mut self) -> PAD21STRNG_W

Bit 10 - Pad 21 drive strength

pub fn pad21inpen(&mut self) -> PAD21INPEN_W

Bit 9 - Pad 21 input enable

pub fn pad21pull(&mut self) -> PAD21PULL_W

Bit 8 - Pad 21 pullup enable

pub fn pad20fncsel(&mut self) -> PAD20FNCSEL_W

Bits 3:5 - Pad 20 function select

pub fn pad20strng(&mut self) -> PAD20STRNG_W

Bit 2 - Pad 20 drive strength

pub fn pad20inpen(&mut self) -> PAD20INPEN_W

Bit 1 - Pad 20 input enable

pub fn pad20pull(&mut self) -> PAD20PULL_W

Bit 0 - Pad 20 pulldown enable

impl W<u32, Reg<u32, _PADREGG>>

pub fn pad27rsel(&mut self) -> PAD27RSEL_W

Bits 30:31 - Pad 27 pullup resistor selection.

pub fn pad27fncsel(&mut self) -> PAD27FNCSEL_W

Bits 27:29 - Pad 27 function select

pub fn pad27strng(&mut self) -> PAD27STRNG_W

Bit 26 - Pad 27 drive strength

pub fn pad27inpen(&mut self) -> PAD27INPEN_W

Bit 25 - Pad 27 input enable

pub fn pad27pull(&mut self) -> PAD27PULL_W

Bit 24 - Pad 27 pullup enable

pub fn pad26fncsel(&mut self) -> PAD26FNCSEL_W

Bits 19:21 - Pad 26 function select

pub fn pad26strng(&mut self) -> PAD26STRNG_W

Bit 18 - Pad 26 drive strength

pub fn pad26inpen(&mut self) -> PAD26INPEN_W

Bit 17 - Pad 26 input enable

pub fn pad26pull(&mut self) -> PAD26PULL_W

Bit 16 - Pad 26 pullup enable

pub fn pad25rsel(&mut self) -> PAD25RSEL_W

Bits 14:15 - Pad 25 pullup resistor selection.

pub fn pad25fncsel(&mut self) -> PAD25FNCSEL_W

Bits 11:13 - Pad 25 function select

pub fn pad25strng(&mut self) -> PAD25STRNG_W

Bit 10 - Pad 25 drive strength

pub fn pad25inpen(&mut self) -> PAD25INPEN_W

Bit 9 - Pad 25 input enable

pub fn pad25pull(&mut self) -> PAD25PULL_W

Bit 8 - Pad 25 pullup enable

pub fn pad24fncsel(&mut self) -> PAD24FNCSEL_W

Bits 3:5 - Pad 24 function select

pub fn pad24strng(&mut self) -> PAD24STRNG_W

Bit 2 - Pad 24 drive strength

pub fn pad24inpen(&mut self) -> PAD24INPEN_W

Bit 1 - Pad 24 input enable

pub fn pad24pull(&mut self) -> PAD24PULL_W

Bit 0 - Pad 24 pullup enable

impl W<u32, Reg<u32, _PADREGH>>

pub fn pad31fncsel(&mut self) -> PAD31FNCSEL_W

Bits 27:29 - Pad 31 function select

pub fn pad31strng(&mut self) -> PAD31STRNG_W

Bit 26 - Pad 31 drive strength

pub fn pad31inpen(&mut self) -> PAD31INPEN_W

Bit 25 - Pad 31 input enable

pub fn pad31pull(&mut self) -> PAD31PULL_W

Bit 24 - Pad 31 pullup enable

pub fn pad30fncsel(&mut self) -> PAD30FNCSEL_W

Bits 19:21 - Pad 30 function select

pub fn pad30strng(&mut self) -> PAD30STRNG_W

Bit 18 - Pad 30 drive strength

pub fn pad30inpen(&mut self) -> PAD30INPEN_W

Bit 17 - Pad 30 input enable

pub fn pad30pull(&mut self) -> PAD30PULL_W

Bit 16 - Pad 30 pullup enable

pub fn pad29fncsel(&mut self) -> PAD29FNCSEL_W

Bits 11:13 - Pad 29 function select

pub fn pad29strng(&mut self) -> PAD29STRNG_W

Bit 10 - Pad 29 drive strength

pub fn pad29inpen(&mut self) -> PAD29INPEN_W

Bit 9 - Pad 29 input enable

pub fn pad29pull(&mut self) -> PAD29PULL_W

Bit 8 - Pad 29 pullup enable

pub fn pad28fncsel(&mut self) -> PAD28FNCSEL_W

Bits 3:5 - Pad 28 function select

pub fn pad28strng(&mut self) -> PAD28STRNG_W

Bit 2 - Pad 28 drive strength

pub fn pad28inpen(&mut self) -> PAD28INPEN_W

Bit 1 - Pad 28 input enable

pub fn pad28pull(&mut self) -> PAD28PULL_W

Bit 0 - Pad 28 pullup enable

impl W<u32, Reg<u32, _PADREGI>>

pub fn pad35fncsel(&mut self) -> PAD35FNCSEL_W

Bits 27:29 - Pad 35 function select

pub fn pad35strng(&mut self) -> PAD35STRNG_W

Bit 26 - Pad 35 drive strength

pub fn pad35inpen(&mut self) -> PAD35INPEN_W

Bit 25 - Pad 35 input enable

pub fn pad35pull(&mut self) -> PAD35PULL_W

Bit 24 - Pad 35 pullup enable

pub fn pad34fncsel(&mut self) -> PAD34FNCSEL_W

Bits 19:21 - Pad 34 function select

pub fn pad34strng(&mut self) -> PAD34STRNG_W

Bit 18 - Pad 34 drive strength

pub fn pad34inpen(&mut self) -> PAD34INPEN_W

Bit 17 - Pad 34 input enable

pub fn pad34pull(&mut self) -> PAD34PULL_W

Bit 16 - Pad 34 pullup enable

pub fn pad33fncsel(&mut self) -> PAD33FNCSEL_W

Bits 11:13 - Pad 33 function select

pub fn pad33strng(&mut self) -> PAD33STRNG_W

Bit 10 - Pad 33 drive strength

pub fn pad33inpen(&mut self) -> PAD33INPEN_W

Bit 9 - Pad 33 input enable

pub fn pad33pull(&mut self) -> PAD33PULL_W

Bit 8 - Pad 33 pullup enable

pub fn pad32fncsel(&mut self) -> PAD32FNCSEL_W

Bits 3:5 - Pad 32 function select

pub fn pad32strng(&mut self) -> PAD32STRNG_W

Bit 2 - Pad 32 drive strength

pub fn pad32inpen(&mut self) -> PAD32INPEN_W

Bit 1 - Pad 32 input enable

pub fn pad32pull(&mut self) -> PAD32PULL_W

Bit 0 - Pad 32 pullup enable

impl W<u32, Reg<u32, _PADREGJ>>

pub fn pad39rsel(&mut self) -> PAD39RSEL_W

Bits 30:31 - Pad 39 pullup resistor selection.

pub fn pad39fncsel(&mut self) -> PAD39FNCSEL_W

Bits 27:29 - Pad 39 function select

pub fn pad39strng(&mut self) -> PAD39STRNG_W

Bit 26 - Pad 39 drive strength

pub fn pad39inpen(&mut self) -> PAD39INPEN_W

Bit 25 - Pad 39 input enable

pub fn pad39pull(&mut self) -> PAD39PULL_W

Bit 24 - Pad 39 pullup enable

pub fn pad38fncsel(&mut self) -> PAD38FNCSEL_W

Bits 19:21 - Pad 38 function select

pub fn pad38strng(&mut self) -> PAD38STRNG_W

Bit 18 - Pad 38 drive strength

pub fn pad38inpen(&mut self) -> PAD38INPEN_W

Bit 17 - Pad 38 input enable

pub fn pad38pull(&mut self) -> PAD38PULL_W

Bit 16 - Pad 38 pullup enable

pub fn pad37pwrdn(&mut self) -> PAD37PWRDN_W

Bit 15 - Pad 37 VSS power switch enable

pub fn pad37fncsel(&mut self) -> PAD37FNCSEL_W

Bits 11:13 - Pad 37 function select

pub fn pad37strng(&mut self) -> PAD37STRNG_W

Bit 10 - Pad 37 drive strength

pub fn pad37inpen(&mut self) -> PAD37INPEN_W

Bit 9 - Pad 37 input enable

pub fn pad37pull(&mut self) -> PAD37PULL_W

Bit 8 - Pad 37 pullup enable

pub fn pad36fncsel(&mut self) -> PAD36FNCSEL_W

Bits 3:5 - Pad 36 function select

pub fn pad36strng(&mut self) -> PAD36STRNG_W

Bit 2 - Pad 36 drive strength

pub fn pad36inpen(&mut self) -> PAD36INPEN_W

Bit 1 - Pad 36 input enable

pub fn pad36pull(&mut self) -> PAD36PULL_W

Bit 0 - Pad 36 pullup enable

impl W<u32, Reg<u32, _PADREGK>>

pub fn pad43rsel(&mut self) -> PAD43RSEL_W

Bits 30:31 - Pad 43 pullup resistor selection.

pub fn pad43fncsel(&mut self) -> PAD43FNCSEL_W

Bits 27:29 - Pad 43 function select

pub fn pad43strng(&mut self) -> PAD43STRNG_W

Bit 26 - Pad 43 drive strength

pub fn pad43inpen(&mut self) -> PAD43INPEN_W

Bit 25 - Pad 43 input enable

pub fn pad43pull(&mut self) -> PAD43PULL_W

Bit 24 - Pad 43 pullup enable

pub fn pad42rsel(&mut self) -> PAD42RSEL_W

Bits 22:23 - Pad 42 pullup resistor selection.

pub fn pad42fncsel(&mut self) -> PAD42FNCSEL_W

Bits 19:21 - Pad 42 function select

pub fn pad42strng(&mut self) -> PAD42STRNG_W

Bit 18 - Pad 42 drive strength

pub fn pad42inpen(&mut self) -> PAD42INPEN_W

Bit 17 - Pad 42 input enable

pub fn pad42pull(&mut self) -> PAD42PULL_W

Bit 16 - Pad 42 pullup enable

pub fn pad41pwrdn(&mut self) -> PAD41PWRDN_W

Bit 15 - Pad 41 power switch enable

pub fn pad41fncsel(&mut self) -> PAD41FNCSEL_W

Bits 11:13 - Pad 41 function select

pub fn pad41strng(&mut self) -> PAD41STRNG_W

Bit 10 - Pad 41 drive strength

pub fn pad41inpen(&mut self) -> PAD41INPEN_W

Bit 9 - Pad 41 input enable

pub fn pad41pull(&mut self) -> PAD41PULL_W

Bit 8 - Pad 41 pullup enable

pub fn pad40rsel(&mut self) -> PAD40RSEL_W

Bits 6:7 - Pad 40 pullup resistor selection.

pub fn pad40fncsel(&mut self) -> PAD40FNCSEL_W

Bits 3:5 - Pad 40 function select

pub fn pad40strng(&mut self) -> PAD40STRNG_W

Bit 2 - Pad 40 drive strength

pub fn pad40inpen(&mut self) -> PAD40INPEN_W

Bit 1 - Pad 40 input enable

pub fn pad40pull(&mut self) -> PAD40PULL_W

Bit 0 - Pad 40 pullup enable

impl W<u32, Reg<u32, _PADREGL>>

pub fn pad47fncsel(&mut self) -> PAD47FNCSEL_W

Bits 27:29 - Pad 47 function select

pub fn pad47strng(&mut self) -> PAD47STRNG_W

Bit 26 - Pad 47 drive strength

pub fn pad47inpen(&mut self) -> PAD47INPEN_W

Bit 25 - Pad 47 input enable

pub fn pad47pull(&mut self) -> PAD47PULL_W

Bit 24 - Pad 47 pullup enable

pub fn pad46fncsel(&mut self) -> PAD46FNCSEL_W

Bits 19:21 - Pad 46 function select

pub fn pad46strng(&mut self) -> PAD46STRNG_W

Bit 18 - Pad 46 drive strength

pub fn pad46inpen(&mut self) -> PAD46INPEN_W

Bit 17 - Pad 46 input enable

pub fn pad46pull(&mut self) -> PAD46PULL_W

Bit 16 - Pad 46 pullup enable

pub fn pad45fncsel(&mut self) -> PAD45FNCSEL_W

Bits 11:13 - Pad 45 function select

pub fn pad45strng(&mut self) -> PAD45STRNG_W

Bit 10 - Pad 45 drive strength

pub fn pad45inpen(&mut self) -> PAD45INPEN_W

Bit 9 - Pad 45 input enable

pub fn pad45pull(&mut self) -> PAD45PULL_W

Bit 8 - Pad 45 pullup enable

pub fn pad44fncsel(&mut self) -> PAD44FNCSEL_W

Bits 3:5 - Pad 44 function select

pub fn pad44strng(&mut self) -> PAD44STRNG_W

Bit 2 - Pad 44 drive strength

pub fn pad44inpen(&mut self) -> PAD44INPEN_W

Bit 1 - Pad 44 input enable

pub fn pad44pull(&mut self) -> PAD44PULL_W

Bit 0 - Pad 44 pullup enable

impl W<u32, Reg<u32, _PADREGM>>

pub fn pad51fncsel(&mut self) -> PAD51FNCSEL_W

Bits 27:29 - Pad 51 function select

pub fn pad51strng(&mut self) -> PAD51STRNG_W

Bit 26 - Pad 51 drive strength

pub fn pad51inpen(&mut self) -> PAD51INPEN_W

Bit 25 - Pad 51 input enable

pub fn pad51pull(&mut self) -> PAD51PULL_W

Bit 24 - Pad 51 pullup enable

pub fn pad50fncsel(&mut self) -> PAD50FNCSEL_W

Bits 19:21 - Pad 50 function select

pub fn pad50strng(&mut self) -> PAD50STRNG_W

Bit 18 - Pad 50 drive strength

pub fn pad50inpen(&mut self) -> PAD50INPEN_W

Bit 17 - Pad 50 input enable

pub fn pad50pull(&mut self) -> PAD50PULL_W

Bit 16 - Pad 50 pullup enable

pub fn pad49rsel(&mut self) -> PAD49RSEL_W

Bits 14:15 - Pad 49 pullup resistor selection.

pub fn pad49fncsel(&mut self) -> PAD49FNCSEL_W

Bits 11:13 - Pad 49 function select

pub fn pad49strng(&mut self) -> PAD49STRNG_W

Bit 10 - Pad 49 drive strength

pub fn pad49inpen(&mut self) -> PAD49INPEN_W

Bit 9 - Pad 49 input enable

pub fn pad49pull(&mut self) -> PAD49PULL_W

Bit 8 - Pad 49 pullup enable

pub fn pad48rsel(&mut self) -> PAD48RSEL_W

Bits 6:7 - Pad 48 pullup resistor selection.

pub fn pad48fncsel(&mut self) -> PAD48FNCSEL_W

Bits 3:5 - Pad 48 function select

pub fn pad48strng(&mut self) -> PAD48STRNG_W

Bit 2 - Pad 48 drive strength

pub fn pad48inpen(&mut self) -> PAD48INPEN_W

Bit 1 - Pad 48 input enable

pub fn pad48pull(&mut self) -> PAD48PULL_W

Bit 0 - Pad 48 pullup enable

impl W<u32, Reg<u32, _PADREGN>>

pub fn pad55fncsel(&mut self) -> PAD55FNCSEL_W

Bits 27:29 - Pad 55 function select

pub fn pad55strng(&mut self) -> PAD55STRNG_W

Bit 26 - Pad 55 drive strength

pub fn pad55inpen(&mut self) -> PAD55INPEN_W

Bit 25 - Pad 55 input enable

pub fn pad55pull(&mut self) -> PAD55PULL_W

Bit 24 - Pad 55 pullup enable

pub fn pad54fncsel(&mut self) -> PAD54FNCSEL_W

Bits 19:21 - Pad 54 function select

pub fn pad54strng(&mut self) -> PAD54STRNG_W

Bit 18 - Pad 54 drive strength

pub fn pad54inpen(&mut self) -> PAD54INPEN_W

Bit 17 - Pad 54 input enable

pub fn pad54pull(&mut self) -> PAD54PULL_W

Bit 16 - Pad 54 pullup enable

pub fn pad53fncsel(&mut self) -> PAD53FNCSEL_W

Bits 11:13 - Pad 53 function select

pub fn pad53strng(&mut self) -> PAD53STRNG_W

Bit 10 - Pad 53 drive strength

pub fn pad53inpen(&mut self) -> PAD53INPEN_W

Bit 9 - Pad 53 input enable

pub fn pad53pull(&mut self) -> PAD53PULL_W

Bit 8 - Pad 53 pullup enable

pub fn pad52fncsel(&mut self) -> PAD52FNCSEL_W

Bits 3:5 - Pad 52 function select

pub fn pad52strng(&mut self) -> PAD52STRNG_W

Bit 2 - Pad 52 drive strength

pub fn pad52inpen(&mut self) -> PAD52INPEN_W

Bit 1 - Pad 52 input enable

pub fn pad52pull(&mut self) -> PAD52PULL_W

Bit 0 - Pad 52 pullup enable

impl W<u32, Reg<u32, _PADREGO>>

pub fn pad59fncsel(&mut self) -> PAD59FNCSEL_W

Bits 27:29 - Pad 59 function select

pub fn pad59strng(&mut self) -> PAD59STRNG_W

Bit 26 - Pad 59 drive strength

pub fn pad59inpen(&mut self) -> PAD59INPEN_W

Bit 25 - Pad 59 input enable

pub fn pad59pull(&mut self) -> PAD59PULL_W

Bit 24 - Pad 59 pullup enable

pub fn pad58fncsel(&mut self) -> PAD58FNCSEL_W

Bits 19:21 - Pad 58 function select

pub fn pad58strng(&mut self) -> PAD58STRNG_W

Bit 18 - Pad 58 drive strength

pub fn pad58inpen(&mut self) -> PAD58INPEN_W

Bit 17 - Pad 58 input enable

pub fn pad58pull(&mut self) -> PAD58PULL_W

Bit 16 - Pad 58 pullup enable

pub fn pad57fncsel(&mut self) -> PAD57FNCSEL_W

Bits 11:13 - Pad 57 function select

pub fn pad57strng(&mut self) -> PAD57STRNG_W

Bit 10 - Pad 57 drive strength

pub fn pad57inpen(&mut self) -> PAD57INPEN_W

Bit 9 - Pad 57 input enable

pub fn pad57pull(&mut self) -> PAD57PULL_W

Bit 8 - Pad 57 pullup enable

pub fn pad56fncsel(&mut self) -> PAD56FNCSEL_W

Bits 3:5 - Pad 56 function select

pub fn pad56strng(&mut self) -> PAD56STRNG_W

Bit 2 - Pad 56 drive strength

pub fn pad56inpen(&mut self) -> PAD56INPEN_W

Bit 1 - Pad 56 input enable

pub fn pad56pull(&mut self) -> PAD56PULL_W

Bit 0 - Pad 56 pullup enable

impl W<u32, Reg<u32, _PADREGP>>

pub fn pad63fncsel(&mut self) -> PAD63FNCSEL_W

Bits 27:29 - Pad 63 function select

pub fn pad63strng(&mut self) -> PAD63STRNG_W

Bit 26 - Pad 63 drive strength

pub fn pad63inpen(&mut self) -> PAD63INPEN_W

Bit 25 - Pad 63 input enable

pub fn pad63pull(&mut self) -> PAD63PULL_W

Bit 24 - Pad 63 pullup enable

pub fn pad62fncsel(&mut self) -> PAD62FNCSEL_W

Bits 19:21 - Pad 62 function select

pub fn pad62strng(&mut self) -> PAD62STRNG_W

Bit 18 - Pad 62 drive strength

pub fn pad62inpen(&mut self) -> PAD62INPEN_W

Bit 17 - Pad 62 input enable

pub fn pad62pull(&mut self) -> PAD62PULL_W

Bit 16 - Pad 62 pullup enable

pub fn pad61fncsel(&mut self) -> PAD61FNCSEL_W

Bits 11:13 - Pad 61 function select

pub fn pad61strng(&mut self) -> PAD61STRNG_W

Bit 10 - Pad 61 drive strength

pub fn pad61inpen(&mut self) -> PAD61INPEN_W

Bit 9 - Pad 61 input enable

pub fn pad61pull(&mut self) -> PAD61PULL_W

Bit 8 - Pad 61 pullup enable

pub fn pad60fncsel(&mut self) -> PAD60FNCSEL_W

Bits 3:5 - Pad 60 function select

pub fn pad60strng(&mut self) -> PAD60STRNG_W

Bit 2 - Pad 60 drive strength

pub fn pad60inpen(&mut self) -> PAD60INPEN_W

Bit 1 - Pad 60 input enable

pub fn pad60pull(&mut self) -> PAD60PULL_W

Bit 0 - Pad 60 pullup enable

impl W<u32, Reg<u32, _PADREGQ>>

pub fn pad67fncsel(&mut self) -> PAD67FNCSEL_W

Bits 27:29 - Pad 67 function select

pub fn pad67strng(&mut self) -> PAD67STRNG_W

Bit 26 - Pad 67 drive strength

pub fn pad67inpen(&mut self) -> PAD67INPEN_W

Bit 25 - Pad 67 input enable

pub fn pad67pull(&mut self) -> PAD67PULL_W

Bit 24 - Pad 67 pullup enable

pub fn pad66fncsel(&mut self) -> PAD66FNCSEL_W

Bits 19:21 - Pad 66 function select

pub fn pad66strng(&mut self) -> PAD66STRNG_W

Bit 18 - Pad 66 drive strength

pub fn pad66inpen(&mut self) -> PAD66INPEN_W

Bit 17 - Pad 66 input enable

pub fn pad66pull(&mut self) -> PAD66PULL_W

Bit 16 - Pad 66 pullup enable

pub fn pad65fncsel(&mut self) -> PAD65FNCSEL_W

Bits 11:13 - Pad 65 function select

pub fn pad65strng(&mut self) -> PAD65STRNG_W

Bit 10 - Pad 65 drive strength

pub fn pad65inpen(&mut self) -> PAD65INPEN_W

Bit 9 - Pad 65 input enable

pub fn pad65pull(&mut self) -> PAD65PULL_W

Bit 8 - Pad 65 pullup enable

pub fn pad64fncsel(&mut self) -> PAD64FNCSEL_W

Bits 3:5 - Pad 64 function select

pub fn pad64strng(&mut self) -> PAD64STRNG_W

Bit 2 - Pad 64 drive strength

pub fn pad64inpen(&mut self) -> PAD64INPEN_W

Bit 1 - Pad 64 input enable

pub fn pad64pull(&mut self) -> PAD64PULL_W

Bit 0 - Pad 64 pullup enable

impl W<u32, Reg<u32, _PADREGR>>

pub fn pad71fncsel(&mut self) -> PAD71FNCSEL_W

Bits 27:29 - Pad 71 function select

pub fn pad71strng(&mut self) -> PAD71STRNG_W

Bit 26 - Pad 71 drive strength

pub fn pad71inpen(&mut self) -> PAD71INPEN_W

Bit 25 - Pad 71 input enable

pub fn pad71pull(&mut self) -> PAD71PULL_W

Bit 24 - Pad 71 pullup enable

pub fn pad70fncsel(&mut self) -> PAD70FNCSEL_W

Bits 19:21 - Pad 70 function select

pub fn pad70strng(&mut self) -> PAD70STRNG_W

Bit 18 - Pad 70 drive strength

pub fn pad70inpen(&mut self) -> PAD70INPEN_W

Bit 17 - Pad 70 input enable

pub fn pad70pull(&mut self) -> PAD70PULL_W

Bit 16 - Pad 70 pullup enable

pub fn pad69fncsel(&mut self) -> PAD69FNCSEL_W

Bits 11:13 - Pad 69 function select

pub fn pad69strng(&mut self) -> PAD69STRNG_W

Bit 10 - Pad 69 drive strength

pub fn pad69inpen(&mut self) -> PAD69INPEN_W

Bit 9 - Pad 69 input enable

pub fn pad69pull(&mut self) -> PAD69PULL_W

Bit 8 - Pad 69 pullup enable

pub fn pad68fncsel(&mut self) -> PAD68FNCSEL_W

Bits 3:5 - Pad 68 function select

pub fn pad68strng(&mut self) -> PAD68STRNG_W

Bit 2 - Pad 68 drive strength

pub fn pad68inpen(&mut self) -> PAD68INPEN_W

Bit 1 - Pad 68 input enable

pub fn pad68pull(&mut self) -> PAD68PULL_W

Bit 0 - Pad 68 pullup enable

impl W<u32, Reg<u32, _PADREGS>>

pub fn pad73fncsel(&mut self) -> PAD73FNCSEL_W

Bits 11:13 - Pad 73 function select

pub fn pad73strng(&mut self) -> PAD73STRNG_W

Bit 10 - Pad 73 drive strength

pub fn pad73inpen(&mut self) -> PAD73INPEN_W

Bit 9 - Pad 73 input enable

pub fn pad73pull(&mut self) -> PAD73PULL_W

Bit 8 - Pad 73 pullup enable

pub fn pad72fncsel(&mut self) -> PAD72FNCSEL_W

Bits 3:5 - Pad 72 function select

pub fn pad72strng(&mut self) -> PAD72STRNG_W

Bit 2 - Pad 72 drive strength

pub fn pad72inpen(&mut self) -> PAD72INPEN_W

Bit 1 - Pad 72 input enable

pub fn pad72pull(&mut self) -> PAD72PULL_W

Bit 0 - Pad 72 pullup enable

impl W<u32, Reg<u32, _CFGA>>

pub fn gpio7intd(&mut self) -> GPIO7INTD_W

Bit 31 - GPIO7 interrupt direction, nCE polarity.

pub fn gpio7outcfg(&mut self) -> GPIO7OUTCFG_W

Bits 29:30 - GPIO7 output configuration.

pub fn gpio7incfg(&mut self) -> GPIO7INCFG_W

Bit 28 - GPIO7 input enable.

pub fn gpio6intd(&mut self) -> GPIO6INTD_W

Bit 27 - GPIO6 interrupt direction, nCE polarity.

pub fn gpio6outcfg(&mut self) -> GPIO6OUTCFG_W

Bits 25:26 - GPIO6 output configuration.

pub fn gpio6incfg(&mut self) -> GPIO6INCFG_W

Bit 24 - GPIO6 input enable.

pub fn gpio5intd(&mut self) -> GPIO5INTD_W

Bit 23 - GPIO5 interrupt direction, nCE polarity.

pub fn gpio5outcfg(&mut self) -> GPIO5OUTCFG_W

Bits 21:22 - GPIO5 output configuration.

pub fn gpio5incfg(&mut self) -> GPIO5INCFG_W

Bit 20 - GPIO5 input enable.

pub fn gpio4intd(&mut self) -> GPIO4INTD_W

Bit 19 - GPIO4 interrupt direction, nCE polarity.

pub fn gpio4outcfg(&mut self) -> GPIO4OUTCFG_W

Bits 17:18 - GPIO4 output configuration.

pub fn gpio4incfg(&mut self) -> GPIO4INCFG_W

Bit 16 - GPIO4 input enable.

pub fn gpio3intd(&mut self) -> GPIO3INTD_W

Bit 15 - GPIO3 interrupt direction, nCE polarity.

pub fn gpio3outcfg(&mut self) -> GPIO3OUTCFG_W

Bits 13:14 - GPIO3 output configuration.

pub fn gpio3incfg(&mut self) -> GPIO3INCFG_W

Bit 12 - GPIO3 input enable.

pub fn gpio2intd(&mut self) -> GPIO2INTD_W

Bit 11 - GPIO2 interrupt direction, nCE polarity.

pub fn gpio2outcfg(&mut self) -> GPIO2OUTCFG_W

Bits 9:10 - GPIO2 output configuration.

pub fn gpio2incfg(&mut self) -> GPIO2INCFG_W

Bit 8 - GPIO2 input enable.

pub fn gpio1intd(&mut self) -> GPIO1INTD_W

Bit 7 - GPIO1 interrupt direction, nCE polarity.

pub fn gpio1outcfg(&mut self) -> GPIO1OUTCFG_W

Bits 5:6 - GPIO1 output configuration.

pub fn gpio1incfg(&mut self) -> GPIO1INCFG_W

Bit 4 - GPIO1 input enable.

pub fn gpio0intd(&mut self) -> GPIO0INTD_W

Bit 3 - GPIO0 interrupt direction, nCE polarity.

pub fn gpio0outcfg(&mut self) -> GPIO0OUTCFG_W

Bits 1:2 - GPIO0 output configuration.

pub fn gpio0incfg(&mut self) -> GPIO0INCFG_W

Bit 0 - GPIO0 input enable.

impl W<u32, Reg<u32, _CFGB>>

pub fn gpio15intd(&mut self) -> GPIO15INTD_W

Bit 31 - GPIO15 interrupt direction, nCE polarity.

pub fn gpio15outcfg(&mut self) -> GPIO15OUTCFG_W

Bits 29:30 - GPIO15 output configuration.

pub fn gpio15incfg(&mut self) -> GPIO15INCFG_W

Bit 28 - GPIO15 input enable.

pub fn gpio14intd(&mut self) -> GPIO14INTD_W

Bit 27 - GPIO14 interrupt direction, nCE polarity.

pub fn gpio14outcfg(&mut self) -> GPIO14OUTCFG_W

Bits 25:26 - GPIO14 output configuration.

pub fn gpio14incfg(&mut self) -> GPIO14INCFG_W

Bit 24 - GPIO14 input enable.

pub fn gpio13intd(&mut self) -> GPIO13INTD_W

Bit 23 - GPIO13 interrupt direction, nCE polarity.

pub fn gpio13outcfg(&mut self) -> GPIO13OUTCFG_W

Bits 21:22 - GPIO13 output configuration.

pub fn gpio13incfg(&mut self) -> GPIO13INCFG_W

Bit 20 - GPIO13 input enable.

pub fn gpio12intd(&mut self) -> GPIO12INTD_W

Bit 19 - GPIO12 interrupt direction, nCE polarity.

pub fn gpio12outcfg(&mut self) -> GPIO12OUTCFG_W

Bits 17:18 - GPIO12 output configuration.

pub fn gpio12incfg(&mut self) -> GPIO12INCFG_W

Bit 16 - GPIO12 input enable.

pub fn gpio11intd(&mut self) -> GPIO11INTD_W

Bit 15 - GPIO11 interrupt direction, nCE polarity.

pub fn gpio11outcfg(&mut self) -> GPIO11OUTCFG_W

Bits 13:14 - GPIO11 output configuration.

pub fn gpio11incfg(&mut self) -> GPIO11INCFG_W

Bit 12 - GPIO11 input enable.

pub fn gpio10intd(&mut self) -> GPIO10INTD_W

Bit 11 - GPIO10 interrupt direction, nCE polarity.

pub fn gpio10outcfg(&mut self) -> GPIO10OUTCFG_W

Bits 9:10 - GPIO10 output configuration.

pub fn gpio10incfg(&mut self) -> GPIO10INCFG_W

Bit 8 - GPIO10 input enable.

pub fn gpio9intd(&mut self) -> GPIO9INTD_W

Bit 7 - GPIO9 interrupt direction, nCE polarity.

pub fn gpio9outcfg(&mut self) -> GPIO9OUTCFG_W

Bits 5:6 - GPIO9 output configuration.

pub fn gpio9incfg(&mut self) -> GPIO9INCFG_W

Bit 4 - GPIO9 input enable.

pub fn gpio8intd(&mut self) -> GPIO8INTD_W

Bit 3 - GPIO8 interrupt direction, nCE polarity.

pub fn gpio8outcfg(&mut self) -> GPIO8OUTCFG_W

Bits 1:2 - GPIO8 output configuration.

pub fn gpio8incfg(&mut self) -> GPIO8INCFG_W

Bit 0 - GPIO8 input enable.

impl W<u32, Reg<u32, _CFGC>>

pub fn gpio23intd(&mut self) -> GPIO23INTD_W

Bit 31 - GPIO23 interrupt direction, nCE polarity.

pub fn gpio23outcfg(&mut self) -> GPIO23OUTCFG_W

Bits 29:30 - GPIO23 output configuration.

pub fn gpio23incfg(&mut self) -> GPIO23INCFG_W

Bit 28 - GPIO23 input enable.

pub fn gpio22intd(&mut self) -> GPIO22INTD_W

Bit 27 - GPIO22 interrupt direction, nCE polarity.

pub fn gpio22outcfg(&mut self) -> GPIO22OUTCFG_W

Bits 25:26 - GPIO22 output configuration.

pub fn gpio22incfg(&mut self) -> GPIO22INCFG_W

Bit 24 - GPIO22 input enable.

pub fn gpio21intd(&mut self) -> GPIO21INTD_W

Bit 23 - GPIO21 interrupt direction, nCE polarity.

pub fn gpio21outcfg(&mut self) -> GPIO21OUTCFG_W

Bits 21:22 - GPIO21 output configuration.

pub fn gpio21incfg(&mut self) -> GPIO21INCFG_W

Bit 20 - GPIO21 input enable.

pub fn gpio20intd(&mut self) -> GPIO20INTD_W

Bit 19 - GPIO20 interrupt direction, nCE polarity.

pub fn gpio20outcfg(&mut self) -> GPIO20OUTCFG_W

Bits 17:18 - GPIO20 output configuration.

pub fn gpio20incfg(&mut self) -> GPIO20INCFG_W

Bit 16 - GPIO20 input enable.

pub fn gpio19intd(&mut self) -> GPIO19INTD_W

Bit 15 - GPIO19 interrupt direction, nCE polarity.

pub fn gpio19outcfg(&mut self) -> GPIO19OUTCFG_W

Bits 13:14 - GPIO19 output configuration.

pub fn gpio19incfg(&mut self) -> GPIO19INCFG_W

Bit 12 - GPIO19 input enable.

pub fn gpio18intd(&mut self) -> GPIO18INTD_W

Bit 11 - GPIO18 interrupt direction, nCE polarity.

pub fn gpio18outcfg(&mut self) -> GPIO18OUTCFG_W

Bits 9:10 - GPIO18 output configuration.

pub fn gpio18incfg(&mut self) -> GPIO18INCFG_W

Bit 8 - GPIO18 input enable.

pub fn gpio17intd(&mut self) -> GPIO17INTD_W

Bit 7 - GPIO17 interrupt direction, nCE polarity.

pub fn gpio17outcfg(&mut self) -> GPIO17OUTCFG_W

Bits 5:6 - GPIO17 output configuration.

pub fn gpio17incfg(&mut self) -> GPIO17INCFG_W

Bit 4 - GPIO17 input enable.

pub fn gpio16intd(&mut self) -> GPIO16INTD_W

Bit 3 - GPIO16 interrupt direction, nCE polarity.

pub fn gpio16outcfg(&mut self) -> GPIO16OUTCFG_W

Bits 1:2 - GPIO16 output configuration.

pub fn gpio16incfg(&mut self) -> GPIO16INCFG_W

Bit 0 - GPIO16 input enable.

impl W<u32, Reg<u32, _CFGD>>

pub fn gpio31intd(&mut self) -> GPIO31INTD_W

Bit 31 - GPIO31 interrupt direction, nCE polarity.

pub fn gpio31outcfg(&mut self) -> GPIO31OUTCFG_W

Bits 29:30 - GPIO31 output configuration.

pub fn gpio31incfg(&mut self) -> GPIO31INCFG_W

Bit 28 - GPIO31 input enable.

pub fn gpio30intd(&mut self) -> GPIO30INTD_W

Bit 27 - GPIO30 interrupt direction, nCE polarity.

pub fn gpio30outcfg(&mut self) -> GPIO30OUTCFG_W

Bits 25:26 - GPIO30 output configuration.

pub fn gpio30incfg(&mut self) -> GPIO30INCFG_W

Bit 24 - GPIO30 input enable.

pub fn gpio29intd(&mut self) -> GPIO29INTD_W

Bit 23 - GPIO29 interrupt direction, nCE polarity.

pub fn gpio29outcfg(&mut self) -> GPIO29OUTCFG_W

Bits 21:22 - GPIO29 output configuration.

pub fn gpio29incfg(&mut self) -> GPIO29INCFG_W

Bit 20 - GPIO29 input enable.

pub fn gpio28intd(&mut self) -> GPIO28INTD_W

Bit 19 - GPIO28 interrupt direction, nCE polarity.

pub fn gpio28outcfg(&mut self) -> GPIO28OUTCFG_W

Bits 17:18 - GPIO28 output configuration.

pub fn gpio28incfg(&mut self) -> GPIO28INCFG_W

Bit 16 - GPIO28 input enable.

pub fn gpio27intd(&mut self) -> GPIO27INTD_W

Bit 15 - GPIO27 interrupt direction, nCE polarity.

pub fn gpio27outcfg(&mut self) -> GPIO27OUTCFG_W

Bits 13:14 - GPIO27 output configuration.

pub fn gpio27incfg(&mut self) -> GPIO27INCFG_W

Bit 12 - GPIO27 input enable.

pub fn gpio26intd(&mut self) -> GPIO26INTD_W

Bit 11 - GPIO26 interrupt direction, nCE polarity.

pub fn gpio26outcfg(&mut self) -> GPIO26OUTCFG_W

Bits 9:10 - GPIO26 output configuration.

pub fn gpio26incfg(&mut self) -> GPIO26INCFG_W

Bit 8 - GPIO26 input enable.

pub fn gpio25intd(&mut self) -> GPIO25INTD_W

Bit 7 - GPIO25 interrupt direction, nCE polarity.

pub fn gpio25outcfg(&mut self) -> GPIO25OUTCFG_W

Bits 5:6 - GPIO25 output configuration.

pub fn gpio25incfg(&mut self) -> GPIO25INCFG_W

Bit 4 - GPIO25 input enable.

pub fn gpio24intd(&mut self) -> GPIO24INTD_W

Bit 3 - GPIO24 interrupt direction, nCE polarity.

pub fn gpio24outcfg(&mut self) -> GPIO24OUTCFG_W

Bits 1:2 - GPIO24 output configuration.

pub fn gpio24incfg(&mut self) -> GPIO24INCFG_W

Bit 0 - GPIO24 input enable.

impl W<u32, Reg<u32, _CFGE>>

pub fn gpio39intd(&mut self) -> GPIO39INTD_W

Bit 31 - GPIO39 interrupt direction, nCE polarity.

pub fn gpio39outcfg(&mut self) -> GPIO39OUTCFG_W

Bits 29:30 - GPIO39 output configuration.

pub fn gpio39incfg(&mut self) -> GPIO39INCFG_W

Bit 28 - GPIO39 input enable.

pub fn gpio38intd(&mut self) -> GPIO38INTD_W

Bit 27 - GPIO38 interrupt direction, nCE polarity.

pub fn gpio38outcfg(&mut self) -> GPIO38OUTCFG_W

Bits 25:26 - GPIO38 output configuration.

pub fn gpio38incfg(&mut self) -> GPIO38INCFG_W

Bit 24 - GPIO38 input enable.

pub fn gpio37intd(&mut self) -> GPIO37INTD_W

Bit 23 - GPIO37 interrupt direction, nCE polarity.

pub fn gpio37outcfg(&mut self) -> GPIO37OUTCFG_W

Bits 21:22 - GPIO37 output configuration.

pub fn gpio37incfg(&mut self) -> GPIO37INCFG_W

Bit 20 - GPIO37 input enable.

pub fn gpio36intd(&mut self) -> GPIO36INTD_W

Bit 19 - GPIO36 interrupt direction, nCE polarity.

pub fn gpio36outcfg(&mut self) -> GPIO36OUTCFG_W

Bits 17:18 - GPIO36 output configuration.

pub fn gpio36incfg(&mut self) -> GPIO36INCFG_W

Bit 16 - GPIO36 input enable.

pub fn gpio35intd(&mut self) -> GPIO35INTD_W

Bit 15 - GPIO35 interrupt direction, nCE polarity.

pub fn gpio35outcfg(&mut self) -> GPIO35OUTCFG_W

Bits 13:14 - GPIO35 output configuration.

pub fn gpio35incfg(&mut self) -> GPIO35INCFG_W

Bit 12 - GPIO35 input enable.

pub fn gpio34intd(&mut self) -> GPIO34INTD_W

Bit 11 - GPIO34 interrupt direction, nCE polarity.

pub fn gpio34outcfg(&mut self) -> GPIO34OUTCFG_W

Bits 9:10 - GPIO34 output configuration.

pub fn gpio34incfg(&mut self) -> GPIO34INCFG_W

Bit 8 - GPIO34 input enable.

pub fn gpio33intd(&mut self) -> GPIO33INTD_W

Bit 7 - GPIO33 interrupt direction, nCE polarity.

pub fn gpio33outcfg(&mut self) -> GPIO33OUTCFG_W

Bits 5:6 - GPIO33 output configuration.

pub fn gpio33incfg(&mut self) -> GPIO33INCFG_W

Bit 4 - GPIO33 input enable.

pub fn gpio32intd(&mut self) -> GPIO32INTD_W

Bit 3 - GPIO32 interrupt direction, nCE polarity.

pub fn gpio32outcfg(&mut self) -> GPIO32OUTCFG_W

Bits 1:2 - GPIO32 output configuration.

pub fn gpio32incfg(&mut self) -> GPIO32INCFG_W

Bit 0 - GPIO32 input enable.

impl W<u32, Reg<u32, _CFGF>>

pub fn gpio47intd(&mut self) -> GPIO47INTD_W

Bit 31 - GPIO47 interrupt direction, nCE polarity.

pub fn gpio47outcfg(&mut self) -> GPIO47OUTCFG_W

Bits 29:30 - GPIO47 output configuration.

pub fn gpio47incfg(&mut self) -> GPIO47INCFG_W

Bit 28 - GPIO47 input enable.

pub fn gpio46intd(&mut self) -> GPIO46INTD_W

Bit 27 - GPIO46 interrupt direction, nCE polarity.

pub fn gpio46outcfg(&mut self) -> GPIO46OUTCFG_W

Bits 25:26 - GPIO46 output configuration.

pub fn gpio46incfg(&mut self) -> GPIO46INCFG_W

Bit 24 - GPIO46 input enable.

pub fn gpio45intd(&mut self) -> GPIO45INTD_W

Bit 23 - GPIO45 interrupt direction, nCE polarity.

pub fn gpio45outcfg(&mut self) -> GPIO45OUTCFG_W

Bits 21:22 - GPIO45 output configuration.

pub fn gpio45incfg(&mut self) -> GPIO45INCFG_W

Bit 20 - GPIO45 input enable.

pub fn gpio44intd(&mut self) -> GPIO44INTD_W

Bit 19 - GPIO44 interrupt direction, nCE polarity.

pub fn gpio44outcfg(&mut self) -> GPIO44OUTCFG_W

Bits 17:18 - GPIO44 output configuration.

pub fn gpio44incfg(&mut self) -> GPIO44INCFG_W

Bit 16 - GPIO44 input enable.

pub fn gpio43intd(&mut self) -> GPIO43INTD_W

Bit 15 - GPIO43 interrupt direction, nCE polarity.

pub fn gpio43outcfg(&mut self) -> GPIO43OUTCFG_W

Bits 13:14 - GPIO43 output configuration.

pub fn gpio43incfg(&mut self) -> GPIO43INCFG_W

Bit 12 - GPIO43 input enable.

pub fn gpio42intd(&mut self) -> GPIO42INTD_W

Bit 11 - GPIO42 interrupt direction, nCE polarity.

pub fn gpio42outcfg(&mut self) -> GPIO42OUTCFG_W

Bits 9:10 - GPIO42 output configuration.

pub fn gpio42incfg(&mut self) -> GPIO42INCFG_W

Bit 8 - GPIO42 input enable.

pub fn gpio41intd(&mut self) -> GPIO41INTD_W

Bit 7 - GPIO41 interrupt direction, nCE polarity.

pub fn gpio41outcfg(&mut self) -> GPIO41OUTCFG_W

Bits 5:6 - GPIO41 output configuration.

pub fn gpio41incfg(&mut self) -> GPIO41INCFG_W

Bit 4 - GPIO41 input enable.

pub fn gpio40intd(&mut self) -> GPIO40INTD_W

Bit 3 - GPIO40 interrupt direction, nCE polarity.

pub fn gpio40outcfg(&mut self) -> GPIO40OUTCFG_W

Bits 1:2 - GPIO40 output configuration.

pub fn gpio40incfg(&mut self) -> GPIO40INCFG_W

Bit 0 - GPIO40 input enable.

impl W<u32, Reg<u32, _CFGG>>

pub fn gpio55intd(&mut self) -> GPIO55INTD_W

Bit 31 - GPIO55 interrupt direction, nCE polarity.

pub fn gpio55outcfg(&mut self) -> GPIO55OUTCFG_W

Bits 29:30 - GPIO55 output configuration.

pub fn gpio55incfg(&mut self) -> GPIO55INCFG_W

Bit 28 - GPIO55 input enable.

pub fn gpio54intd(&mut self) -> GPIO54INTD_W

Bit 27 - GPIO54 interrupt direction, nCE polarity.

pub fn gpio54outcfg(&mut self) -> GPIO54OUTCFG_W

Bits 25:26 - GPIO54 output configuration.

pub fn gpio54incfg(&mut self) -> GPIO54INCFG_W

Bit 24 - GPIO54 input enable.

pub fn gpio53intd(&mut self) -> GPIO53INTD_W

Bit 23 - GPIO53 interrupt direction, nCE polarity.

pub fn gpio53outcfg(&mut self) -> GPIO53OUTCFG_W

Bits 21:22 - GPIO53 output configuration.

pub fn gpio53incfg(&mut self) -> GPIO53INCFG_W

Bit 20 - GPIO53 input enable.

pub fn gpio52intd(&mut self) -> GPIO52INTD_W

Bit 19 - GPIO52 interrupt direction, nCE polarity.

pub fn gpio52outcfg(&mut self) -> GPIO52OUTCFG_W

Bits 17:18 - GPIO52 output configuration.

pub fn gpio52incfg(&mut self) -> GPIO52INCFG_W

Bit 16 - GPIO52 input enable.

pub fn gpio51intd(&mut self) -> GPIO51INTD_W

Bit 15 - GPIO51 interrupt direction, nCE polarity.

pub fn gpio51outcfg(&mut self) -> GPIO51OUTCFG_W

Bits 13:14 - GPIO51 output configuration.

pub fn gpio51incfg(&mut self) -> GPIO51INCFG_W

Bit 12 - GPIO51 input enable.

pub fn gpio50intd(&mut self) -> GPIO50INTD_W

Bit 11 - GPIO50 interrupt direction, nCE polarity.

pub fn gpio50outcfg(&mut self) -> GPIO50OUTCFG_W

Bits 9:10 - GPIO50 output configuration.

pub fn gpio50incfg(&mut self) -> GPIO50INCFG_W

Bit 8 - GPIO50 input enable.

pub fn gpio49intd(&mut self) -> GPIO49INTD_W

Bit 7 - GPIO49 interrupt direction, nCE polarity.

pub fn gpio49outcfg(&mut self) -> GPIO49OUTCFG_W

Bits 5:6 - GPIO49 output configuration.

pub fn gpio49incfg(&mut self) -> GPIO49INCFG_W

Bit 4 - GPIO49 input enable.

pub fn gpio48intd(&mut self) -> GPIO48INTD_W

Bit 3 - GPIO48 interrupt direction, nCE polarity.

pub fn gpio48outcfg(&mut self) -> GPIO48OUTCFG_W

Bits 1:2 - GPIO48 output configuration.

pub fn gpio48incfg(&mut self) -> GPIO48INCFG_W

Bit 0 - GPIO48 input enable.

impl W<u32, Reg<u32, _CFGH>>

pub fn gpio63intd(&mut self) -> GPIO63INTD_W

Bit 31 - GPIO63 interrupt direction, nCE polarity.

pub fn gpio63outcfg(&mut self) -> GPIO63OUTCFG_W

Bits 29:30 - GPIO63 output configuration.

pub fn gpio63incfg(&mut self) -> GPIO63INCFG_W

Bit 28 - GPIO63 input enable.

pub fn gpio62intd(&mut self) -> GPIO62INTD_W

Bit 27 - GPIO62 interrupt direction, nCE polarity.

pub fn gpio62outcfg(&mut self) -> GPIO62OUTCFG_W

Bits 25:26 - GPIO62 output configuration.

pub fn gpio62incfg(&mut self) -> GPIO62INCFG_W

Bit 24 - GPIO62 input enable.

pub fn gpio61intd(&mut self) -> GPIO61INTD_W

Bit 23 - GPIO61 interrupt direction, nCE polarity.

pub fn gpio61outcfg(&mut self) -> GPIO61OUTCFG_W

Bits 21:22 - GPIO61 output configuration.

pub fn gpio61incfg(&mut self) -> GPIO61INCFG_W

Bit 20 - GPIO61 input enable.

pub fn gpio60intd(&mut self) -> GPIO60INTD_W

Bit 19 - GPIO60 interrupt direction, nCE polarity.

pub fn gpio60outcfg(&mut self) -> GPIO60OUTCFG_W

Bits 17:18 - GPIO60 output configuration.

pub fn gpio60incfg(&mut self) -> GPIO60INCFG_W

Bit 16 - GPIO60 input enable.

pub fn gpio59intd(&mut self) -> GPIO59INTD_W

Bit 15 - GPIO59 interrupt direction, nCE polarity.

pub fn gpio59outcfg(&mut self) -> GPIO59OUTCFG_W

Bits 13:14 - GPIO59 output configuration.

pub fn gpio59incfg(&mut self) -> GPIO59INCFG_W

Bit 12 - GPIO59 input enable.

pub fn gpio58intd(&mut self) -> GPIO58INTD_W

Bit 11 - GPIO58 interrupt direction, nCE polarity.

pub fn gpio58outcfg(&mut self) -> GPIO58OUTCFG_W

Bits 9:10 - GPIO58 output configuration.

pub fn gpio58incfg(&mut self) -> GPIO58INCFG_W

Bit 8 - GPIO58 input enable.

pub fn gpio57intd(&mut self) -> GPIO57INTD_W

Bit 7 - GPIO57 interrupt direction, nCE polarity.

pub fn gpio57outcfg(&mut self) -> GPIO57OUTCFG_W

Bits 5:6 - GPIO57 output configuration.

pub fn gpio57incfg(&mut self) -> GPIO57INCFG_W

Bit 4 - GPIO57 input enable.

pub fn gpio56intd(&mut self) -> GPIO56INTD_W

Bit 3 - GPIO56 interrupt direction, nCE polarity.

pub fn gpio56outcfg(&mut self) -> GPIO56OUTCFG_W

Bits 1:2 - GPIO56 output configuration.

pub fn gpio56incfg(&mut self) -> GPIO56INCFG_W

Bit 0 - GPIO56 input enable.

impl W<u32, Reg<u32, _CFGI>>

pub fn gpio71intd(&mut self) -> GPIO71INTD_W

Bit 31 - GPIO71 interrupt direction, nCE polarity.

pub fn gpio71outcfg(&mut self) -> GPIO71OUTCFG_W

Bits 29:30 - GPIO71 output configuration.

pub fn gpio71incfg(&mut self) -> GPIO71INCFG_W

Bit 28 - GPIO71 input enable.

pub fn gpio70intd(&mut self) -> GPIO70INTD_W

Bit 27 - GPIO70 interrupt direction, nCE polarity.

pub fn gpio70outcfg(&mut self) -> GPIO70OUTCFG_W

Bits 25:26 - GPIO70 output configuration.

pub fn gpio70incfg(&mut self) -> GPIO70INCFG_W

Bit 24 - GPIO70 input enable.

pub fn gpio69intd(&mut self) -> GPIO69INTD_W

Bit 23 - GPIO69 interrupt direction, nCE polarity.

pub fn gpio69outcfg(&mut self) -> GPIO69OUTCFG_W

Bits 21:22 - GPIO69 output configuration.

pub fn gpio69incfg(&mut self) -> GPIO69INCFG_W

Bit 20 - GPIO69 input enable.

pub fn gpio68intd(&mut self) -> GPIO68INTD_W

Bit 19 - GPIO68 interrupt direction, nCE polarity.

pub fn gpio68outcfg(&mut self) -> GPIO68OUTCFG_W

Bits 17:18 - GPIO68 output configuration.

pub fn gpio68incfg(&mut self) -> GPIO68INCFG_W

Bit 16 - GPIO68 input enable.

pub fn gpio67intd(&mut self) -> GPIO67INTD_W

Bit 15 - GPIO67 interrupt direction, nCE polarity.

pub fn gpio67outcfg(&mut self) -> GPIO67OUTCFG_W

Bits 13:14 - GPIO67 output configuration.

pub fn gpio67incfg(&mut self) -> GPIO67INCFG_W

Bit 12 - GPIO67 input enable.

pub fn gpio66intd(&mut self) -> GPIO66INTD_W

Bit 11 - GPIO66 interrupt direction, nCE polarity.

pub fn gpio66outcfg(&mut self) -> GPIO66OUTCFG_W

Bits 9:10 - GPIO66 output configuration.

pub fn gpio66incfg(&mut self) -> GPIO66INCFG_W

Bit 8 - GPIO66 input enable.

pub fn gpio65intd(&mut self) -> GPIO65INTD_W

Bit 7 - GPIO65 interrupt direction, nCE polarity.

pub fn gpio65outcfg(&mut self) -> GPIO65OUTCFG_W

Bits 5:6 - GPIO65 output configuration.

pub fn gpio65incfg(&mut self) -> GPIO65INCFG_W

Bit 4 - GPIO65 input enable.

pub fn gpio64intd(&mut self) -> GPIO64INTD_W

Bit 3 - GPIO64 interrupt direction, nCE polarity.

pub fn gpio64outcfg(&mut self) -> GPIO64OUTCFG_W

Bits 1:2 - GPIO64 output configuration.

pub fn gpio64incfg(&mut self) -> GPIO64INCFG_W

Bit 0 - GPIO64 input enable.

impl W<u32, Reg<u32, _CFGJ>>

pub fn gpio73intd(&mut self) -> GPIO73INTD_W

Bit 7 - GPIO73 interrupt direction, nCE polarity.

pub fn gpio73outcfg(&mut self) -> GPIO73OUTCFG_W

Bits 5:6 - GPIO73 output configuration.

pub fn gpio73incfg(&mut self) -> GPIO73INCFG_W

Bit 4 - GPIO73 input enable.

pub fn gpio72intd(&mut self) -> GPIO72INTD_W

Bit 3 - GPIO72 interrupt direction, nCE polarity.

pub fn gpio72outcfg(&mut self) -> GPIO72OUTCFG_W

Bits 1:2 - GPIO72 output configuration.

pub fn gpio72incfg(&mut self) -> GPIO72INCFG_W

Bit 0 - GPIO72 input enable.

impl W<u32, Reg<u32, _PADKEY>>

pub fn padkey(&mut self) -> PADKEY_W

Bits 0:31 - Key register value.

impl W<u32, Reg<u32, _RDA>>

pub fn rda(&mut self) -> RDA_W

Bits 0:31 - GPIO31-0 read data.

impl W<u32, Reg<u32, _RDB>>

pub fn rdb(&mut self) -> RDB_W

Bits 0:31 - GPIO63-32 read data.

impl W<u32, Reg<u32, _RDC>>

pub fn rdc(&mut self) -> RDC_W

Bits 0:9 - GPIO73-64 read data.

impl W<u32, Reg<u32, _WTA>>

pub fn wta(&mut self) -> WTA_W

Bits 0:31 - GPIO31-0 write data.

impl W<u32, Reg<u32, _WTB>>

pub fn wtb(&mut self) -> WTB_W

Bits 0:31 - GPIO63-32 write data.

impl W<u32, Reg<u32, _WTC>>

pub fn wtc(&mut self) -> WTC_W

Bits 0:9 - GPIO73-64 write data.

impl W<u32, Reg<u32, _WTSA>>

pub fn wtsa(&mut self) -> WTSA_W

Bits 0:31 - Set the GPIO31-0 write data.

impl W<u32, Reg<u32, _WTSB>>

pub fn wtsb(&mut self) -> WTSB_W

Bits 0:31 - Set the GPIO63-32 write data.

impl W<u32, Reg<u32, _WTSC>>

pub fn wtsc(&mut self) -> WTSC_W

Bits 0:9 - Set the GPIO73-64 write data.

impl W<u32, Reg<u32, _WTCA>>

pub fn wtca(&mut self) -> WTCA_W

Bits 0:31 - Clear the GPIO31-0 write data.

impl W<u32, Reg<u32, _WTCB>>

pub fn wtcb(&mut self) -> WTCB_W

Bits 0:31 - Clear the GPIO63-32 write data.

impl W<u32, Reg<u32, _WTCC>>

pub fn wtcb(&mut self) -> WTCB_W

Bits 0:9 - Clear the GPIO73-64 write data.

impl W<u32, Reg<u32, _ENA>>

pub fn ena(&mut self) -> ENA_W

Bits 0:31 - GPIO31-0 output enables

impl W<u32, Reg<u32, _ENB>>

pub fn enb(&mut self) -> ENB_W

Bits 0:31 - GPIO63-32 output enables

impl W<u32, Reg<u32, _ENC>>

pub fn enc(&mut self) -> ENC_W

Bits 0:9 - GPIO73-64 output enables

impl W<u32, Reg<u32, _ENSA>>

pub fn ensa(&mut self) -> ENSA_W

Bits 0:31 - Set the GPIO31-0 output enables

impl W<u32, Reg<u32, _ENSB>>

pub fn ensb(&mut self) -> ENSB_W

Bits 0:31 - Set the GPIO63-32 output enables

impl W<u32, Reg<u32, _ENSC>>

pub fn ensc(&mut self) -> ENSC_W

Bits 0:9 - Set the GPIO73-64 output enables

impl W<u32, Reg<u32, _ENCA>>

pub fn enca(&mut self) -> ENCA_W

Bits 0:31 - Clear the GPIO31-0 output enables

impl W<u32, Reg<u32, _ENCB>>

pub fn encb(&mut self) -> ENCB_W

Bits 0:31 - Clear the GPIO49-32 output enables

impl W<u32, Reg<u32, _ENCC>>

pub fn encc(&mut self) -> ENCC_W

Bits 0:9 - Clear the GPIO73-64 output enables

impl W<u32, Reg<u32, _STMRCAP>>

pub fn stpol3(&mut self) -> STPOL3_W

Bit 31 - STIMER Capture 3 Polarity.

pub fn stsel3(&mut self) -> STSEL3_W

Bits 24:30 - STIMER Capture 3 Select.

pub fn stpol2(&mut self) -> STPOL2_W

Bit 23 - STIMER Capture 2 Polarity.

pub fn stsel2(&mut self) -> STSEL2_W

Bits 16:22 - STIMER Capture 2 Select.

pub fn stpol1(&mut self) -> STPOL1_W

Bit 15 - STIMER Capture 1 Polarity.

pub fn stsel1(&mut self) -> STSEL1_W

Bits 8:14 - STIMER Capture 1 Select.

pub fn stpol0(&mut self) -> STPOL0_W

Bit 7 - STIMER Capture 0 Polarity.

pub fn stsel0(&mut self) -> STSEL0_W

Bits 0:6 - STIMER Capture 0 Select.

impl W<u32, Reg<u32, _IOM0IRQ>>

pub fn iom0irq(&mut self) -> IOM0IRQ_W

Bits 0:6 - IOMSTR0 IRQ pad select.

impl W<u32, Reg<u32, _IOM1IRQ>>

pub fn iom1irq(&mut self) -> IOM1IRQ_W

Bits 0:6 - IOMSTR1 IRQ pad select.

impl W<u32, Reg<u32, _IOM2IRQ>>

pub fn iom2irq(&mut self) -> IOM2IRQ_W

Bits 0:6 - IOMSTR2 IRQ pad select.

impl W<u32, Reg<u32, _IOM3IRQ>>

pub fn iom3irq(&mut self) -> IOM3IRQ_W

Bits 0:6 - IOMSTR3 IRQ pad select.

impl W<u32, Reg<u32, _IOM4IRQ>>

pub fn iom4irq(&mut self) -> IOM4IRQ_W

Bits 0:6 - IOMSTR4 IRQ pad select.

impl W<u32, Reg<u32, _IOM5IRQ>>

pub fn iom5irq(&mut self) -> IOM5IRQ_W

Bits 0:6 - IOMSTR5 IRQ pad select.

impl W<u32, Reg<u32, _BLEIFIRQ>>

pub fn bleifirq(&mut self) -> BLEIFIRQ_W

Bits 0:6 - BLEIF IRQ pad select.

impl W<u32, Reg<u32, _GPIOOBS>>

pub fn obs_data(&mut self) -> OBS_DATA_W

Bits 0:15 - Sample of the data output on the GPIO observation port. May have sampling non-synchronization issues, as the data is not synchronized to the read operation. Intended for debug purposes only

impl W<u32, Reg<u32, _ALTPADCFGA>>

pub fn pad3_sr(&mut self) -> PAD3_SR_W

Bit 28 - Pad 3 slew rate selection.

pub fn pad3_ds1(&mut self) -> PAD3_DS1_W

Bit 24 - Pad 3 high order drive strength selection. Used in conjunction with PAD3STRNG field to set the pad drive strength.

pub fn pad2_sr(&mut self) -> PAD2_SR_W

Bit 20 - Pad 3 slew rate selection.

pub fn pad2_ds1(&mut self) -> PAD2_DS1_W

Bit 16 - Pad 2 high order drive strength selection. Used in conjunction with PAD2STRNG field to set the pad drive strength.

pub fn pad1_sr(&mut self) -> PAD1_SR_W

Bit 12 - Pad 3 slew rate selection.

pub fn pad1_ds1(&mut self) -> PAD1_DS1_W

Bit 8 - Pad 1 high order drive strength selection. Used in conjunction with PAD1STRNG field to set the pad drive strength.

pub fn pad0_sr(&mut self) -> PAD0_SR_W

Bit 4 - Pad 3 slew rate selection.

pub fn pad0_ds1(&mut self) -> PAD0_DS1_W

Bit 0 - Pad 0 high order drive strength selection. Used in conjunction with PAD0STRNG field to set the pad drive strength.

impl W<u32, Reg<u32, _ALTPADCFGB>>

pub fn pad7_sr(&mut self) -> PAD7_SR_W

Bit 28 - Pad 7 slew rate selection.

pub fn pad7_ds1(&mut self) -> PAD7_DS1_W

Bit 24 - Pad 7 high order drive strength selection. Used in conjunction with PAD7STRNG field to set the pad drive strength.

pub fn pad6_sr(&mut self) -> PAD6_SR_W

Bit 20 - Pad 7 slew rate selection.

pub fn pad6_ds1(&mut self) -> PAD6_DS1_W

Bit 16 - Pad 6 high order drive strength selection. Used in conjunction with PAD6STRNG field to set the pad drive strength.

pub fn pad5_sr(&mut self) -> PAD5_SR_W

Bit 12 - Pad 7 slew rate selection.

pub fn pad5_ds1(&mut self) -> PAD5_DS1_W

Bit 8 - Pad 5 high order drive strength selection. Used in conjunction with PAD5STRNG field to set the pad drive strength.

pub fn pad4_sr(&mut self) -> PAD4_SR_W

Bit 4 - Pad 7 slew rate selection.

pub fn pad4_ds1(&mut self) -> PAD4_DS1_W

Bit 0 - Pad 4 high order drive strength selection. Used in conjunction with PAD4STRNG field to set the pad drive strength.

impl W<u32, Reg<u32, _ALTPADCFGC>>

pub fn pad11_sr(&mut self) -> PAD11_SR_W

Bit 28 - Pad 11 slew rate selection.

pub fn pad11_ds1(&mut self) -> PAD11_DS1_W

Bit 24 - Pad 11 high order drive strength selection. Used in conjunction with PAD11STRNG field to set the pad drive strength.

pub fn pad10_sr(&mut self) -> PAD10_SR_W

Bit 20 - Pad 11 slew rate selection.

pub fn pad10_ds1(&mut self) -> PAD10_DS1_W

Bit 16 - Pad 10 high order drive strength selection. Used in conjunction with PAD10STRNG field to set the pad drive strength.

pub fn pad9_sr(&mut self) -> PAD9_SR_W

Bit 12 - Pad 11 slew rate selection.

pub fn pad9_ds1(&mut self) -> PAD9_DS1_W

Bit 8 - Pad 9 high order drive strength selection. Used in conjunction with PAD9STRNG field to set the pad drive strength.

pub fn pad8_sr(&mut self) -> PAD8_SR_W

Bit 4 - Pad 11 slew rate selection.

pub fn pad8_ds1(&mut self) -> PAD8_DS1_W

Bit 0 - Pad 8 high order drive strength selection. Used in conjunction with PAD8STRNG field to set the pad drive strength.

impl W<u32, Reg<u32, _ALTPADCFGD>>

pub fn pad15_sr(&mut self) -> PAD15_SR_W

Bit 28 - Pad 15 slew rate selection.

pub fn pad15_ds1(&mut self) -> PAD15_DS1_W

Bit 24 - Pad 15 high order drive strength selection. Used in conjunction with PAD15STRNG field to set the pad drive strength.

pub fn pad14_sr(&mut self) -> PAD14_SR_W

Bit 20 - Pad 15 slew rate selection.

pub fn pad14_ds1(&mut self) -> PAD14_DS1_W

Bit 16 - Pad 14 high order drive strength selection. Used in conjunction with PAD14STRNG field to set the pad drive strength.

pub fn pad13_sr(&mut self) -> PAD13_SR_W

Bit 12 - Pad 15 slew rate selection.

pub fn pad13_ds1(&mut self) -> PAD13_DS1_W

Bit 8 - Pad 13 high order drive strength selection. Used in conjunction with PAD13STRNG field to set the pad drive strength.

pub fn pad12_sr(&mut self) -> PAD12_SR_W

Bit 4 - Pad 15 slew rate selection.

pub fn pad12_ds1(&mut self) -> PAD12_DS1_W

Bit 0 - Pad 12 high order drive strength selection. Used in conjunction with PAD12STRNG field to set the pad drive strength.

impl W<u32, Reg<u32, _ALTPADCFGE>>

pub fn pad19_sr(&mut self) -> PAD19_SR_W

Bit 28 - Pad 19 slew rate selection.

pub fn pad19_ds1(&mut self) -> PAD19_DS1_W

Bit 24 - Pad 19 high order drive strength selection. Used in conjunction with PAD19STRNG field to set the pad drive strength.

pub fn pad18_sr(&mut self) -> PAD18_SR_W

Bit 20 - Pad 19 slew rate selection.

pub fn pad18_ds1(&mut self) -> PAD18_DS1_W

Bit 16 - Pad 18 high order drive strength selection. Used in conjunction with PAD18STRNG field to set the pad drive strength.

pub fn pad17_sr(&mut self) -> PAD17_SR_W

Bit 12 - Pad 19 slew rate selection.

pub fn pad17_ds1(&mut self) -> PAD17_DS1_W

Bit 8 - Pad 17 high order drive strength selection. Used in conjunction with PAD17STRNG field to set the pad drive strength.

pub fn pad16_sr(&mut self) -> PAD16_SR_W

Bit 4 - Pad 19 slew rate selection.

pub fn pad16_ds1(&mut self) -> PAD16_DS1_W

Bit 0 - Pad 16 high order drive strength selection. Used in conjunction with PAD16STRNG field to set the pad drive strength.

impl W<u32, Reg<u32, _ALTPADCFGF>>

pub fn pad23_sr(&mut self) -> PAD23_SR_W

Bit 28 - Pad 23 slew rate selection.

pub fn pad23_ds1(&mut self) -> PAD23_DS1_W

Bit 24 - Pad 23 high order drive strength selection. Used in conjunction with PAD23STRNG field to set the pad drive strength.

pub fn pad22_sr(&mut self) -> PAD22_SR_W

Bit 20 - Pad 23 slew rate selection.

pub fn pad22_ds1(&mut self) -> PAD22_DS1_W

Bit 16 - Pad 22 high order drive strength selection. Used in conjunction with PAD22STRNG field to set the pad drive strength.

pub fn pad21_sr(&mut self) -> PAD21_SR_W

Bit 12 - Pad 23 slew rate selection.

pub fn pad21_ds1(&mut self) -> PAD21_DS1_W

Bit 8 - Pad 21 high order drive strength selection. Used in conjunction with PAD21STRNG field to set the pad drive strength.

pub fn pad20_sr(&mut self) -> PAD20_SR_W

Bit 4 - Pad 23 slew rate selection.

pub fn pad20_ds1(&mut self) -> PAD20_DS1_W

Bit 0 - Pad 20 high order drive strength selection. Used in conjunction with PAD20STRNG field to set the pad drive strength.

impl W<u32, Reg<u32, _ALTPADCFGG>>

pub fn pad27_sr(&mut self) -> PAD27_SR_W

Bit 28 - Pad 27 slew rate selection.

pub fn pad27_ds1(&mut self) -> PAD27_DS1_W

Bit 24 - Pad 27 high order drive strength selection. Used in conjunction with PAD27STRNG field to set the pad drive strength.

pub fn pad26_sr(&mut self) -> PAD26_SR_W

Bit 20 - Pad 27 slew rate selection.

pub fn pad26_ds1(&mut self) -> PAD26_DS1_W

Bit 16 - Pad 26 high order drive strength selection. Used in conjunction with PAD26STRNG field to set the pad drive strength.

pub fn pad25_sr(&mut self) -> PAD25_SR_W

Bit 12 - Pad 27 slew rate selection.

pub fn pad25_ds1(&mut self) -> PAD25_DS1_W

Bit 8 - Pad 25 high order drive strength selection. Used in conjunction with PAD25STRNG field to set the pad drive strength.

pub fn pad24_sr(&mut self) -> PAD24_SR_W

Bit 4 - Pad 27 slew rate selection.

pub fn pad24_ds1(&mut self) -> PAD24_DS1_W

Bit 0 - Pad 24 high order drive strength selection. Used in conjunction with PAD24STRNG field to set the pad drive strength.

impl W<u32, Reg<u32, _ALTPADCFGH>>

pub fn pad31_sr(&mut self) -> PAD31_SR_W

Bit 28 - Pad 31 slew rate selection.

pub fn pad31_ds1(&mut self) -> PAD31_DS1_W

Bit 24 - Pad 31 high order drive strength selection. Used in conjunction with PAD31STRNG field to set the pad drive strength.

pub fn pad30_sr(&mut self) -> PAD30_SR_W

Bit 20 - Pad 31 slew rate selection.

pub fn pad30_ds1(&mut self) -> PAD30_DS1_W

Bit 16 - Pad 30 high order drive strength selection. Used in conjunction with PAD30STRNG field to set the pad drive strength.

pub fn pad29_sr(&mut self) -> PAD29_SR_W

Bit 12 - Pad 31 slew rate selection.

pub fn pad29_ds1(&mut self) -> PAD29_DS1_W

Bit 8 - Pad 29 high order drive strength selection. Used in conjunction with PAD29STRNG field to set the pad drive strength.

pub fn pad28_sr(&mut self) -> PAD28_SR_W

Bit 4 - Pad 31 slew rate selection.

pub fn pad28_ds1(&mut self) -> PAD28_DS1_W

Bit 0 - Pad 28 high order drive strength selection. Used in conjunction with PAD28STRNG field to set the pad drive strength.

impl W<u32, Reg<u32, _ALTPADCFGI>>

pub fn pad35_sr(&mut self) -> PAD35_SR_W

Bit 28 - Pad 35 slew rate selection.

pub fn pad35_ds1(&mut self) -> PAD35_DS1_W

Bit 24 - Pad 35 high order drive strength selection. Used in conjunction with PAD35STRNG field to set the pad drive strength.

pub fn pad34_sr(&mut self) -> PAD34_SR_W

Bit 20 - Pad 35 slew rate selection.

pub fn pad34_ds1(&mut self) -> PAD34_DS1_W

Bit 16 - Pad 34 high order drive strength selection. Used in conjunction with PAD34STRNG field to set the pad drive strength.

pub fn pad33_sr(&mut self) -> PAD33_SR_W

Bit 12 - Pad 35 slew rate selection.

pub fn pad33_ds1(&mut self) -> PAD33_DS1_W

Bit 8 - Pad 33 high order drive strength selection. Used in conjunction with PAD33STRNG field to set the pad drive strength.

pub fn pad32_sr(&mut self) -> PAD32_SR_W

Bit 4 - Pad 35 slew rate selection.

pub fn pad32_ds1(&mut self) -> PAD32_DS1_W

Bit 0 - Pad 32 high order drive strength selection. Used in conjunction with PAD32STRNG field to set the pad drive strength.

impl W<u32, Reg<u32, _ALTPADCFGJ>>

pub fn pad39_sr(&mut self) -> PAD39_SR_W

Bit 28 - Pad 39 slew rate selection.

pub fn pad39_ds1(&mut self) -> PAD39_DS1_W

Bit 24 - Pad 39 high order drive strength selection. Used in conjunction with PAD39STRNG field to set the pad drive strength.

pub fn pad38_sr(&mut self) -> PAD38_SR_W

Bit 20 - Pad 39 slew rate selection.

pub fn pad38_ds1(&mut self) -> PAD38_DS1_W

Bit 16 - Pad 38 high order drive strength selection. Used in conjunction with PAD38STRNG field to set the pad drive strength.

pub fn pad37_sr(&mut self) -> PAD37_SR_W

Bit 12 - Pad 39 slew rate selection.

pub fn pad37_ds1(&mut self) -> PAD37_DS1_W

Bit 8 - Pad 37 high order drive strength selection. Used in conjunction with PAD37STRNG field to set the pad drive strength.

pub fn pad36_sr(&mut self) -> PAD36_SR_W

Bit 4 - Pad 39 slew rate selection.

pub fn pad36_ds1(&mut self) -> PAD36_DS1_W

Bit 0 - Pad 36 high order drive strength selection. Used in conjunction with PAD36STRNG field to set the pad drive strength.

impl W<u32, Reg<u32, _ALTPADCFGK>>

pub fn pad43_sr(&mut self) -> PAD43_SR_W

Bit 28 - Pad 43 slew rate selection.

pub fn pad43_ds1(&mut self) -> PAD43_DS1_W

Bit 24 - Pad 43 high order drive strength selection. Used in conjunction with PAD43STRNG field to set the pad drive strength.

pub fn pad42_sr(&mut self) -> PAD42_SR_W

Bit 20 - Pad 43 slew rate selection.

pub fn pad42_ds1(&mut self) -> PAD42_DS1_W

Bit 16 - Pad 42 high order drive strength selection. Used in conjunction with PAD42STRNG field to set the pad drive strength.

pub fn pad41_sr(&mut self) -> PAD41_SR_W

Bit 12 - Pad 43 slew rate selection.

pub fn pad41_ds1(&mut self) -> PAD41_DS1_W

Bit 8 - Pad 41 high order drive strength selection. Used in conjunction with PAD41STRNG field to set the pad drive strength.

pub fn pad40_sr(&mut self) -> PAD40_SR_W

Bit 4 - Pad 43 slew rate selection.

pub fn pad40_ds1(&mut self) -> PAD40_DS1_W

Bit 0 - Pad 40 high order drive strength selection. Used in conjunction with PAD40STRNG field to set the pad drive strength.

impl W<u32, Reg<u32, _ALTPADCFGL>>

pub fn pad47_sr(&mut self) -> PAD47_SR_W

Bit 28 - Pad 47 slew rate selection.

pub fn pad47_ds1(&mut self) -> PAD47_DS1_W

Bit 24 - Pad 47 high order drive strength selection. Used in conjunction with PAD47STRNG field to set the pad drive strength.

pub fn pad46_sr(&mut self) -> PAD46_SR_W

Bit 20 - Pad 47 slew rate selection.

pub fn pad46_ds1(&mut self) -> PAD46_DS1_W

Bit 16 - Pad 46 high order drive strength selection. Used in conjunction with PAD46STRNG field to set the pad drive strength.

pub fn pad45_sr(&mut self) -> PAD45_SR_W

Bit 12 - Pad 47 slew rate selection.

pub fn pad45_ds1(&mut self) -> PAD45_DS1_W

Bit 8 - Pad 45 high order drive strength selection. Used in conjunction with PAD45STRNG field to set the pad drive strength.

pub fn pad44_sr(&mut self) -> PAD44_SR_W

Bit 4 - Pad 47 slew rate selection.

pub fn pad44_ds1(&mut self) -> PAD44_DS1_W

Bit 0 - Pad 44 high order drive strength selection. Used in conjunction with PAD44STRNG field to set the pad drive strength.

impl W<u32, Reg<u32, _ALTPADCFGM>>

pub fn pad51_sr(&mut self) -> PAD51_SR_W

Bit 28 - Pad 51 slew rate selection.

pub fn pad51_ds1(&mut self) -> PAD51_DS1_W

Bit 24 - Pad 51 high order drive strength selection. Used in conjunction with PAD51STRNG field to set the pad drive strength.

pub fn pad50_sr(&mut self) -> PAD50_SR_W

Bit 20 - Pad 51 slew rate selection.

pub fn pad50_ds1(&mut self) -> PAD50_DS1_W

Bit 16 - Pad 50 high order drive strength selection. Used in conjunction with PAD50STRNG field to set the pad drive strength.

pub fn pad49_sr(&mut self) -> PAD49_SR_W

Bit 12 - Pad 51 slew rate selection.

pub fn pad49_ds1(&mut self) -> PAD49_DS1_W

Bit 8 - Pad 49 high order drive strength selection. Used in conjunction with PAD49STRNG field to set the pad drive strength.

pub fn pad48_sr(&mut self) -> PAD48_SR_W

Bit 4 - Pad 51 slew rate selection.

pub fn pad48_ds1(&mut self) -> PAD48_DS1_W

Bit 0 - Pad 48 high order drive strength selection. Used in conjunction with PAD48STRNG field to set the pad drive strength.

impl W<u32, Reg<u32, _ALTPADCFGN>>

pub fn pad55_sr(&mut self) -> PAD55_SR_W

Bit 28 - Pad 55 slew rate selection.

pub fn pad55_ds1(&mut self) -> PAD55_DS1_W

Bit 24 - Pad 55 high order drive strength selection. Used in conjunction with PAD55STRNG field to set the pad drive strength.

pub fn pad54_sr(&mut self) -> PAD54_SR_W

Bit 20 - Pad 55 slew rate selection.

pub fn pad54_ds1(&mut self) -> PAD54_DS1_W

Bit 16 - Pad 54 high order drive strength selection. Used in conjunction with PAD54STRNG field to set the pad drive strength.

pub fn pad53_sr(&mut self) -> PAD53_SR_W

Bit 12 - Pad 55 slew rate selection.

pub fn pad53_ds1(&mut self) -> PAD53_DS1_W

Bit 8 - Pad 53 high order drive strength selection. Used in conjunction with PAD53STRNG field to set the pad drive strength.

pub fn pad52_sr(&mut self) -> PAD52_SR_W

Bit 4 - Pad 55 slew rate selection.

pub fn pad52_ds1(&mut self) -> PAD52_DS1_W

Bit 0 - Pad 52 high order drive strength selection. Used in conjunction with PAD52STRNG field to set the pad drive strength.

impl W<u32, Reg<u32, _ALTPADCFGO>>

pub fn pad59_sr(&mut self) -> PAD59_SR_W

Bit 28 - Pad 59 slew rate selection.

pub fn pad59_ds1(&mut self) -> PAD59_DS1_W

Bit 24 - Pad 59 high order drive strength selection. Used in conjunction with PAD59STRNG field to set the pad drive strength.

pub fn pad58_sr(&mut self) -> PAD58_SR_W

Bit 20 - Pad 59 slew rate selection.

pub fn pad58_ds1(&mut self) -> PAD58_DS1_W

Bit 16 - Pad 58 high order drive strength selection. Used in conjunction with PAD58STRNG field to set the pad drive strength.

pub fn pad57_sr(&mut self) -> PAD57_SR_W

Bit 12 - Pad 59 slew rate selection.

pub fn pad57_ds1(&mut self) -> PAD57_DS1_W

Bit 8 - Pad 57 high order drive strength selection. Used in conjunction with PAD57STRNG field to set the pad drive strength.

pub fn pad56_sr(&mut self) -> PAD56_SR_W

Bit 4 - Pad 59 slew rate selection.

pub fn pad56_ds1(&mut self) -> PAD56_DS1_W

Bit 0 - Pad 56 high order drive strength selection. Used in conjunction with PAD56STRNG field to set the pad drive strength.

impl W<u32, Reg<u32, _ALTPADCFGP>>

pub fn pad63_sr(&mut self) -> PAD63_SR_W

Bit 28 - Pad 63 slew rate selection.

pub fn pad63_ds1(&mut self) -> PAD63_DS1_W

Bit 24 - Pad 63 high order drive strength selection. Used in conjunction with PAD63STRNG field to set the pad drive strength.

pub fn pad62_sr(&mut self) -> PAD62_SR_W

Bit 20 - Pad 63 slew rate selection.

pub fn pad62_ds1(&mut self) -> PAD62_DS1_W

Bit 16 - Pad 62 high order drive strength selection. Used in conjunction with PAD62STRNG field to set the pad drive strength.

pub fn pad61_sr(&mut self) -> PAD61_SR_W

Bit 12 - Pad 63 slew rate selection.

pub fn pad61_ds1(&mut self) -> PAD61_DS1_W

Bit 8 - Pad 61 high order drive strength selection. Used in conjunction with PAD61STRNG field to set the pad drive strength.

pub fn pad60_sr(&mut self) -> PAD60_SR_W

Bit 4 - Pad 63 slew rate selection.

pub fn pad60_ds1(&mut self) -> PAD60_DS1_W

Bit 0 - Pad 60 high order drive strength selection. Used in conjunction with PAD60STRNG field to set the pad drive strength.

impl W<u32, Reg<u32, _ALTPADCFGQ>>

pub fn pad67_sr(&mut self) -> PAD67_SR_W

Bit 28 - Pad 67 slew rate selection.

pub fn pad67_ds1(&mut self) -> PAD67_DS1_W

Bit 24 - Pad 67 high order drive strength selection. Used in conjunction with PAD67STRNG field to set the pad drive strength.

pub fn pad66_sr(&mut self) -> PAD66_SR_W

Bit 20 - Pad 67 slew rate selection.

pub fn pad66_ds1(&mut self) -> PAD66_DS1_W

Bit 16 - Pad 66 high order drive strength selection. Used in conjunction with PAD66STRNG field to set the pad drive strength.

pub fn pad65_sr(&mut self) -> PAD65_SR_W

Bit 12 - Pad 67 slew rate selection.

pub fn pad65_ds1(&mut self) -> PAD65_DS1_W

Bit 8 - Pad 65 high order drive strength selection. Used in conjunction with PAD65STRNG field to set the pad drive strength.

pub fn pad64_sr(&mut self) -> PAD64_SR_W

Bit 4 - Pad 67 slew rate selection.

pub fn pad64_ds1(&mut self) -> PAD64_DS1_W

Bit 0 - Pad 64 high order drive strength selection. Used in conjunction with PAD64STRNG field to set the pad drive strength.

impl W<u32, Reg<u32, _ALTPADCFGR>>

pub fn pad71_sr(&mut self) -> PAD71_SR_W

Bit 28 - Pad 71 slew rate selection.

pub fn pad71_ds1(&mut self) -> PAD71_DS1_W

Bit 24 - Pad 71 high order drive strength selection. Used in conjunction with PAD71STRNG field to set the pad drive strength.

pub fn pad70_sr(&mut self) -> PAD70_SR_W

Bit 20 - Pad 71 slew rate selection.

pub fn pad70_ds1(&mut self) -> PAD70_DS1_W

Bit 16 - Pad 70 high order drive strength selection. Used in conjunction with PAD70STRNG field to set the pad drive strength.

pub fn pad69_sr(&mut self) -> PAD69_SR_W

Bit 12 - Pad 71 slew rate selection.

pub fn pad69_ds1(&mut self) -> PAD69_DS1_W

Bit 8 - Pad 69 high order drive strength selection. Used in conjunction with PAD69STRNG field to set the pad drive strength.

pub fn pad68_sr(&mut self) -> PAD68_SR_W

Bit 4 - Pad 71 slew rate selection.

pub fn pad68_ds1(&mut self) -> PAD68_DS1_W

Bit 0 - Pad 68 high order drive strength selection. Used in conjunction with PAD68STRNG field to set the pad drive strength.

impl W<u32, Reg<u32, _ALTPADCFGS>>

pub fn pad73_sr(&mut self) -> PAD73_SR_W

Bit 12 - Pad 73 slew rate selection.

pub fn pad73_ds1(&mut self) -> PAD73_DS1_W

Bit 8 - Pad 73 high order drive strength selection. Used in conjunction with PAD73STRNG field to set the pad drive strength.

pub fn pad72_sr(&mut self) -> PAD72_SR_W

Bit 4 - Pad 72 slew rate selection.

pub fn pad72_ds1(&mut self) -> PAD72_DS1_W

Bit 0 - Pad 72 high order drive strength selection. Used in conjunction with PAD72STRNG field to set the pad drive strength.

impl W<u32, Reg<u32, _SCDET>>

pub fn scdet(&mut self) -> SCDET_W

Bits 0:6 - SCARD card detect pad select.

impl W<u32, Reg<u32, _CTENCFG>>

pub fn en31(&mut self) -> EN31_W

Bit 31 - CT31 Enable

pub fn en30(&mut self) -> EN30_W

Bit 30 - CT30 Enable

pub fn en29(&mut self) -> EN29_W

Bit 29 - CT29 Enable

pub fn en28(&mut self) -> EN28_W

Bit 28 - CT28 Enable

pub fn en27(&mut self) -> EN27_W

Bit 27 - CT27 Enable

pub fn en26(&mut self) -> EN26_W

Bit 26 - CT26 Enable

pub fn en25(&mut self) -> EN25_W

Bit 25 - CT25 Enable

pub fn en24(&mut self) -> EN24_W

Bit 24 - CT24 Enable

pub fn en23(&mut self) -> EN23_W

Bit 23 - CT23 Enable

pub fn en22(&mut self) -> EN22_W

Bit 22 - CT22 Enable

pub fn en21(&mut self) -> EN21_W

Bit 21 - CT21 Enable

pub fn en20(&mut self) -> EN20_W

Bit 20 - CT20 Enable

pub fn en19(&mut self) -> EN19_W

Bit 19 - CT19 Enable

pub fn en18(&mut self) -> EN18_W

Bit 18 - CT18 Enable

pub fn en17(&mut self) -> EN17_W

Bit 17 - CT17 Enable

pub fn en16(&mut self) -> EN16_W

Bit 16 - CT16 Enable

pub fn en15(&mut self) -> EN15_W

Bit 15 - CT15 Enable

pub fn en14(&mut self) -> EN14_W

Bit 14 - CT14 Enable

pub fn en13(&mut self) -> EN13_W

Bit 13 - CT13 Enable

pub fn en12(&mut self) -> EN12_W

Bit 12 - CT12 Enable

pub fn en11(&mut self) -> EN11_W

Bit 11 - CT11 Enable

pub fn en10(&mut self) -> EN10_W

Bit 10 - CT10 Enable

pub fn en9(&mut self) -> EN9_W

Bit 9 - CT9 Enable

pub fn en8(&mut self) -> EN8_W

Bit 8 - CT8 Enable

pub fn en7(&mut self) -> EN7_W

Bit 7 - CT7 Enable

pub fn en6(&mut self) -> EN6_W

Bit 6 - CT6 Enable

pub fn en5(&mut self) -> EN5_W

Bit 5 - CT5 Enable

pub fn en4(&mut self) -> EN4_W

Bit 4 - CT4 Enable

pub fn en3(&mut self) -> EN3_W

Bit 3 - CT3 Enable

pub fn en2(&mut self) -> EN2_W

Bit 2 - CT2 Enable

pub fn en1(&mut self) -> EN1_W

Bit 1 - CT1 Enable

pub fn en0(&mut self) -> EN0_W

Bit 0 - CT0 Enable

impl W<u32, Reg<u32, _INT0EN>>

pub fn gpio31(&mut self) -> GPIO31_W

Bit 31 - GPIO31 interrupt.

pub fn gpio30(&mut self) -> GPIO30_W

Bit 30 - GPIO30 interrupt.

pub fn gpio29(&mut self) -> GPIO29_W

Bit 29 - GPIO29 interrupt.

pub fn gpio28(&mut self) -> GPIO28_W

Bit 28 - GPIO28 interrupt.

pub fn gpio27(&mut self) -> GPIO27_W

Bit 27 - GPIO27 interrupt.

pub fn gpio26(&mut self) -> GPIO26_W

Bit 26 - GPIO26 interrupt.

pub fn gpio25(&mut self) -> GPIO25_W

Bit 25 - GPIO25 interrupt.

pub fn gpio24(&mut self) -> GPIO24_W

Bit 24 - GPIO24 interrupt.

pub fn gpio23(&mut self) -> GPIO23_W

Bit 23 - GPIO23 interrupt.

pub fn gpio22(&mut self) -> GPIO22_W

Bit 22 - GPIO22 interrupt.

pub fn gpio21(&mut self) -> GPIO21_W

Bit 21 - GPIO21 interrupt.

pub fn gpio20(&mut self) -> GPIO20_W

Bit 20 - GPIO20 interrupt.

pub fn gpio19(&mut self) -> GPIO19_W

Bit 19 - GPIO19 interrupt.

pub fn gpio18(&mut self) -> GPIO18_W

Bit 18 - GPIO18interrupt.

pub fn gpio17(&mut self) -> GPIO17_W

Bit 17 - GPIO17 interrupt.

pub fn gpio16(&mut self) -> GPIO16_W

Bit 16 - GPIO16 interrupt.

pub fn gpio15(&mut self) -> GPIO15_W

Bit 15 - GPIO15 interrupt.

pub fn gpio14(&mut self) -> GPIO14_W

Bit 14 - GPIO14 interrupt.

pub fn gpio13(&mut self) -> GPIO13_W

Bit 13 - GPIO13 interrupt.

pub fn gpio12(&mut self) -> GPIO12_W

Bit 12 - GPIO12 interrupt.

pub fn gpio11(&mut self) -> GPIO11_W

Bit 11 - GPIO11 interrupt.

pub fn gpio10(&mut self) -> GPIO10_W

Bit 10 - GPIO10 interrupt.

pub fn gpio9(&mut self) -> GPIO9_W

Bit 9 - GPIO9 interrupt.

pub fn gpio8(&mut self) -> GPIO8_W

Bit 8 - GPIO8 interrupt.

pub fn gpio7(&mut self) -> GPIO7_W

Bit 7 - GPIO7 interrupt.

pub fn gpio6(&mut self) -> GPIO6_W

Bit 6 - GPIO6 interrupt.

pub fn gpio5(&mut self) -> GPIO5_W

Bit 5 - GPIO5 interrupt.

pub fn gpio4(&mut self) -> GPIO4_W

Bit 4 - GPIO4 interrupt.

pub fn gpio3(&mut self) -> GPIO3_W

Bit 3 - GPIO3 interrupt.

pub fn gpio2(&mut self) -> GPIO2_W

Bit 2 - GPIO2 interrupt.

pub fn gpio1(&mut self) -> GPIO1_W

Bit 1 - GPIO1 interrupt.

pub fn gpio0(&mut self) -> GPIO0_W

Bit 0 - GPIO0 interrupt.

impl W<u32, Reg<u32, _INT0STAT>>

pub fn gpio31(&mut self) -> GPIO31_W

Bit 31 - GPIO31 interrupt.

pub fn gpio30(&mut self) -> GPIO30_W

Bit 30 - GPIO30 interrupt.

pub fn gpio29(&mut self) -> GPIO29_W

Bit 29 - GPIO29 interrupt.

pub fn gpio28(&mut self) -> GPIO28_W

Bit 28 - GPIO28 interrupt.

pub fn gpio27(&mut self) -> GPIO27_W

Bit 27 - GPIO27 interrupt.

pub fn gpio26(&mut self) -> GPIO26_W

Bit 26 - GPIO26 interrupt.

pub fn gpio25(&mut self) -> GPIO25_W

Bit 25 - GPIO25 interrupt.

pub fn gpio24(&mut self) -> GPIO24_W

Bit 24 - GPIO24 interrupt.

pub fn gpio23(&mut self) -> GPIO23_W

Bit 23 - GPIO23 interrupt.

pub fn gpio22(&mut self) -> GPIO22_W

Bit 22 - GPIO22 interrupt.

pub fn gpio21(&mut self) -> GPIO21_W

Bit 21 - GPIO21 interrupt.

pub fn gpio20(&mut self) -> GPIO20_W

Bit 20 - GPIO20 interrupt.

pub fn gpio19(&mut self) -> GPIO19_W

Bit 19 - GPIO19 interrupt.

pub fn gpio18(&mut self) -> GPIO18_W

Bit 18 - GPIO18interrupt.

pub fn gpio17(&mut self) -> GPIO17_W

Bit 17 - GPIO17 interrupt.

pub fn gpio16(&mut self) -> GPIO16_W

Bit 16 - GPIO16 interrupt.

pub fn gpio15(&mut self) -> GPIO15_W

Bit 15 - GPIO15 interrupt.

pub fn gpio14(&mut self) -> GPIO14_W

Bit 14 - GPIO14 interrupt.

pub fn gpio13(&mut self) -> GPIO13_W

Bit 13 - GPIO13 interrupt.

pub fn gpio12(&mut self) -> GPIO12_W

Bit 12 - GPIO12 interrupt.

pub fn gpio11(&mut self) -> GPIO11_W

Bit 11 - GPIO11 interrupt.

pub fn gpio10(&mut self) -> GPIO10_W

Bit 10 - GPIO10 interrupt.

pub fn gpio9(&mut self) -> GPIO9_W

Bit 9 - GPIO9 interrupt.

pub fn gpio8(&mut self) -> GPIO8_W

Bit 8 - GPIO8 interrupt.

pub fn gpio7(&mut self) -> GPIO7_W

Bit 7 - GPIO7 interrupt.

pub fn gpio6(&mut self) -> GPIO6_W

Bit 6 - GPIO6 interrupt.

pub fn gpio5(&mut self) -> GPIO5_W

Bit 5 - GPIO5 interrupt.

pub fn gpio4(&mut self) -> GPIO4_W

Bit 4 - GPIO4 interrupt.

pub fn gpio3(&mut self) -> GPIO3_W

Bit 3 - GPIO3 interrupt.

pub fn gpio2(&mut self) -> GPIO2_W

Bit 2 - GPIO2 interrupt.

pub fn gpio1(&mut self) -> GPIO1_W

Bit 1 - GPIO1 interrupt.

pub fn gpio0(&mut self) -> GPIO0_W

Bit 0 - GPIO0 interrupt.

impl W<u32, Reg<u32, _INT0CLR>>

pub fn gpio31(&mut self) -> GPIO31_W

Bit 31 - GPIO31 interrupt.

pub fn gpio30(&mut self) -> GPIO30_W

Bit 30 - GPIO30 interrupt.

pub fn gpio29(&mut self) -> GPIO29_W

Bit 29 - GPIO29 interrupt.

pub fn gpio28(&mut self) -> GPIO28_W

Bit 28 - GPIO28 interrupt.

pub fn gpio27(&mut self) -> GPIO27_W

Bit 27 - GPIO27 interrupt.

pub fn gpio26(&mut self) -> GPIO26_W

Bit 26 - GPIO26 interrupt.

pub fn gpio25(&mut self) -> GPIO25_W

Bit 25 - GPIO25 interrupt.

pub fn gpio24(&mut self) -> GPIO24_W

Bit 24 - GPIO24 interrupt.

pub fn gpio23(&mut self) -> GPIO23_W

Bit 23 - GPIO23 interrupt.

pub fn gpio22(&mut self) -> GPIO22_W

Bit 22 - GPIO22 interrupt.

pub fn gpio21(&mut self) -> GPIO21_W

Bit 21 - GPIO21 interrupt.

pub fn gpio20(&mut self) -> GPIO20_W

Bit 20 - GPIO20 interrupt.

pub fn gpio19(&mut self) -> GPIO19_W

Bit 19 - GPIO19 interrupt.

pub fn gpio18(&mut self) -> GPIO18_W

Bit 18 - GPIO18interrupt.

pub fn gpio17(&mut self) -> GPIO17_W

Bit 17 - GPIO17 interrupt.

pub fn gpio16(&mut self) -> GPIO16_W

Bit 16 - GPIO16 interrupt.

pub fn gpio15(&mut self) -> GPIO15_W

Bit 15 - GPIO15 interrupt.

pub fn gpio14(&mut self) -> GPIO14_W

Bit 14 - GPIO14 interrupt.

pub fn gpio13(&mut self) -> GPIO13_W

Bit 13 - GPIO13 interrupt.

pub fn gpio12(&mut self) -> GPIO12_W

Bit 12 - GPIO12 interrupt.

pub fn gpio11(&mut self) -> GPIO11_W

Bit 11 - GPIO11 interrupt.

pub fn gpio10(&mut self) -> GPIO10_W

Bit 10 - GPIO10 interrupt.

pub fn gpio9(&mut self) -> GPIO9_W

Bit 9 - GPIO9 interrupt.

pub fn gpio8(&mut self) -> GPIO8_W

Bit 8 - GPIO8 interrupt.

pub fn gpio7(&mut self) -> GPIO7_W

Bit 7 - GPIO7 interrupt.

pub fn gpio6(&mut self) -> GPIO6_W

Bit 6 - GPIO6 interrupt.

pub fn gpio5(&mut self) -> GPIO5_W

Bit 5 - GPIO5 interrupt.

pub fn gpio4(&mut self) -> GPIO4_W

Bit 4 - GPIO4 interrupt.

pub fn gpio3(&mut self) -> GPIO3_W

Bit 3 - GPIO3 interrupt.

pub fn gpio2(&mut self) -> GPIO2_W

Bit 2 - GPIO2 interrupt.

pub fn gpio1(&mut self) -> GPIO1_W

Bit 1 - GPIO1 interrupt.

pub fn gpio0(&mut self) -> GPIO0_W

Bit 0 - GPIO0 interrupt.

impl W<u32, Reg<u32, _INT0SET>>

pub fn gpio31(&mut self) -> GPIO31_W

Bit 31 - GPIO31 interrupt.

pub fn gpio30(&mut self) -> GPIO30_W

Bit 30 - GPIO30 interrupt.

pub fn gpio29(&mut self) -> GPIO29_W

Bit 29 - GPIO29 interrupt.

pub fn gpio28(&mut self) -> GPIO28_W

Bit 28 - GPIO28 interrupt.

pub fn gpio27(&mut self) -> GPIO27_W

Bit 27 - GPIO27 interrupt.

pub fn gpio26(&mut self) -> GPIO26_W

Bit 26 - GPIO26 interrupt.

pub fn gpio25(&mut self) -> GPIO25_W

Bit 25 - GPIO25 interrupt.

pub fn gpio24(&mut self) -> GPIO24_W

Bit 24 - GPIO24 interrupt.

pub fn gpio23(&mut self) -> GPIO23_W

Bit 23 - GPIO23 interrupt.

pub fn gpio22(&mut self) -> GPIO22_W

Bit 22 - GPIO22 interrupt.

pub fn gpio21(&mut self) -> GPIO21_W

Bit 21 - GPIO21 interrupt.

pub fn gpio20(&mut self) -> GPIO20_W

Bit 20 - GPIO20 interrupt.

pub fn gpio19(&mut self) -> GPIO19_W

Bit 19 - GPIO19 interrupt.

pub fn gpio18(&mut self) -> GPIO18_W

Bit 18 - GPIO18interrupt.

pub fn gpio17(&mut self) -> GPIO17_W

Bit 17 - GPIO17 interrupt.

pub fn gpio16(&mut self) -> GPIO16_W

Bit 16 - GPIO16 interrupt.

pub fn gpio15(&mut self) -> GPIO15_W

Bit 15 - GPIO15 interrupt.

pub fn gpio14(&mut self) -> GPIO14_W

Bit 14 - GPIO14 interrupt.

pub fn gpio13(&mut self) -> GPIO13_W

Bit 13 - GPIO13 interrupt.

pub fn gpio12(&mut self) -> GPIO12_W

Bit 12 - GPIO12 interrupt.

pub fn gpio11(&mut self) -> GPIO11_W

Bit 11 - GPIO11 interrupt.

pub fn gpio10(&mut self) -> GPIO10_W

Bit 10 - GPIO10 interrupt.

pub fn gpio9(&mut self) -> GPIO9_W

Bit 9 - GPIO9 interrupt.

pub fn gpio8(&mut self) -> GPIO8_W

Bit 8 - GPIO8 interrupt.

pub fn gpio7(&mut self) -> GPIO7_W

Bit 7 - GPIO7 interrupt.

pub fn gpio6(&mut self) -> GPIO6_W

Bit 6 - GPIO6 interrupt.

pub fn gpio5(&mut self) -> GPIO5_W

Bit 5 - GPIO5 interrupt.

pub fn gpio4(&mut self) -> GPIO4_W

Bit 4 - GPIO4 interrupt.

pub fn gpio3(&mut self) -> GPIO3_W

Bit 3 - GPIO3 interrupt.

pub fn gpio2(&mut self) -> GPIO2_W

Bit 2 - GPIO2 interrupt.

pub fn gpio1(&mut self) -> GPIO1_W

Bit 1 - GPIO1 interrupt.

pub fn gpio0(&mut self) -> GPIO0_W

Bit 0 - GPIO0 interrupt.

impl W<u32, Reg<u32, _INT1EN>>

pub fn gpio63(&mut self) -> GPIO63_W

Bit 31 - GPIO63 interrupt.

pub fn gpio62(&mut self) -> GPIO62_W

Bit 30 - GPIO62 interrupt.

pub fn gpio61(&mut self) -> GPIO61_W

Bit 29 - GPIO61 interrupt.

pub fn gpio60(&mut self) -> GPIO60_W

Bit 28 - GPIO60 interrupt.

pub fn gpio59(&mut self) -> GPIO59_W

Bit 27 - GPIO59 interrupt.

pub fn gpio58(&mut self) -> GPIO58_W

Bit 26 - GPIO58 interrupt.

pub fn gpio57(&mut self) -> GPIO57_W

Bit 25 - GPIO57 interrupt.

pub fn gpio56(&mut self) -> GPIO56_W

Bit 24 - GPIO56 interrupt.

pub fn gpio55(&mut self) -> GPIO55_W

Bit 23 - GPIO55 interrupt.

pub fn gpio54(&mut self) -> GPIO54_W

Bit 22 - GPIO54 interrupt.

pub fn gpio53(&mut self) -> GPIO53_W

Bit 21 - GPIO53 interrupt.

pub fn gpio52(&mut self) -> GPIO52_W

Bit 20 - GPIO52 interrupt.

pub fn gpio51(&mut self) -> GPIO51_W

Bit 19 - GPIO51 interrupt.

pub fn gpio50(&mut self) -> GPIO50_W

Bit 18 - GPIO50 interrupt.

pub fn gpio49(&mut self) -> GPIO49_W

Bit 17 - GPIO49 interrupt.

pub fn gpio48(&mut self) -> GPIO48_W

Bit 16 - GPIO48 interrupt.

pub fn gpio47(&mut self) -> GPIO47_W

Bit 15 - GPIO47 interrupt.

pub fn gpio46(&mut self) -> GPIO46_W

Bit 14 - GPIO46 interrupt.

pub fn gpio45(&mut self) -> GPIO45_W

Bit 13 - GPIO45 interrupt.

pub fn gpio44(&mut self) -> GPIO44_W

Bit 12 - GPIO44 interrupt.

pub fn gpio43(&mut self) -> GPIO43_W

Bit 11 - GPIO43 interrupt.

pub fn gpio42(&mut self) -> GPIO42_W

Bit 10 - GPIO42 interrupt.

pub fn gpio41(&mut self) -> GPIO41_W

Bit 9 - GPIO41 interrupt.

pub fn gpio40(&mut self) -> GPIO40_W

Bit 8 - GPIO40 interrupt.

pub fn gpio39(&mut self) -> GPIO39_W

Bit 7 - GPIO39 interrupt.

pub fn gpio38(&mut self) -> GPIO38_W

Bit 6 - GPIO38 interrupt.

pub fn gpio37(&mut self) -> GPIO37_W

Bit 5 - GPIO37 interrupt.

pub fn gpio36(&mut self) -> GPIO36_W

Bit 4 - GPIO36 interrupt.

pub fn gpio35(&mut self) -> GPIO35_W

Bit 3 - GPIO35 interrupt.

pub fn gpio34(&mut self) -> GPIO34_W

Bit 2 - GPIO34 interrupt.

pub fn gpio33(&mut self) -> GPIO33_W

Bit 1 - GPIO33 interrupt.

pub fn gpio32(&mut self) -> GPIO32_W

Bit 0 - GPIO32 interrupt.

impl W<u32, Reg<u32, _INT1STAT>>

pub fn gpio63(&mut self) -> GPIO63_W

Bit 31 - GPIO63 interrupt.

pub fn gpio62(&mut self) -> GPIO62_W

Bit 30 - GPIO62 interrupt.

pub fn gpio61(&mut self) -> GPIO61_W

Bit 29 - GPIO61 interrupt.

pub fn gpio60(&mut self) -> GPIO60_W

Bit 28 - GPIO60 interrupt.

pub fn gpio59(&mut self) -> GPIO59_W

Bit 27 - GPIO59 interrupt.

pub fn gpio58(&mut self) -> GPIO58_W

Bit 26 - GPIO58 interrupt.

pub fn gpio57(&mut self) -> GPIO57_W

Bit 25 - GPIO57 interrupt.

pub fn gpio56(&mut self) -> GPIO56_W

Bit 24 - GPIO56 interrupt.

pub fn gpio55(&mut self) -> GPIO55_W

Bit 23 - GPIO55 interrupt.

pub fn gpio54(&mut self) -> GPIO54_W

Bit 22 - GPIO54 interrupt.

pub fn gpio53(&mut self) -> GPIO53_W

Bit 21 - GPIO53 interrupt.

pub fn gpio52(&mut self) -> GPIO52_W

Bit 20 - GPIO52 interrupt.

pub fn gpio51(&mut self) -> GPIO51_W

Bit 19 - GPIO51 interrupt.

pub fn gpio50(&mut self) -> GPIO50_W

Bit 18 - GPIO50 interrupt.

pub fn gpio49(&mut self) -> GPIO49_W

Bit 17 - GPIO49 interrupt.

pub fn gpio48(&mut self) -> GPIO48_W

Bit 16 - GPIO48 interrupt.

pub fn gpio47(&mut self) -> GPIO47_W

Bit 15 - GPIO47 interrupt.

pub fn gpio46(&mut self) -> GPIO46_W

Bit 14 - GPIO46 interrupt.

pub fn gpio45(&mut self) -> GPIO45_W

Bit 13 - GPIO45 interrupt.

pub fn gpio44(&mut self) -> GPIO44_W

Bit 12 - GPIO44 interrupt.

pub fn gpio43(&mut self) -> GPIO43_W

Bit 11 - GPIO43 interrupt.

pub fn gpio42(&mut self) -> GPIO42_W

Bit 10 - GPIO42 interrupt.

pub fn gpio41(&mut self) -> GPIO41_W

Bit 9 - GPIO41 interrupt.

pub fn gpio40(&mut self) -> GPIO40_W

Bit 8 - GPIO40 interrupt.

pub fn gpio39(&mut self) -> GPIO39_W

Bit 7 - GPIO39 interrupt.

pub fn gpio38(&mut self) -> GPIO38_W

Bit 6 - GPIO38 interrupt.

pub fn gpio37(&mut self) -> GPIO37_W

Bit 5 - GPIO37 interrupt.

pub fn gpio36(&mut self) -> GPIO36_W

Bit 4 - GPIO36 interrupt.

pub fn gpio35(&mut self) -> GPIO35_W

Bit 3 - GPIO35 interrupt.

pub fn gpio34(&mut self) -> GPIO34_W

Bit 2 - GPIO34 interrupt.

pub fn gpio33(&mut self) -> GPIO33_W

Bit 1 - GPIO33 interrupt.

pub fn gpio32(&mut self) -> GPIO32_W

Bit 0 - GPIO32 interrupt.

impl W<u32, Reg<u32, _INT1CLR>>

pub fn gpio63(&mut self) -> GPIO63_W

Bit 31 - GPIO63 interrupt.

pub fn gpio62(&mut self) -> GPIO62_W

Bit 30 - GPIO62 interrupt.

pub fn gpio61(&mut self) -> GPIO61_W

Bit 29 - GPIO61 interrupt.

pub fn gpio60(&mut self) -> GPIO60_W

Bit 28 - GPIO60 interrupt.

pub fn gpio59(&mut self) -> GPIO59_W

Bit 27 - GPIO59 interrupt.

pub fn gpio58(&mut self) -> GPIO58_W

Bit 26 - GPIO58 interrupt.

pub fn gpio57(&mut self) -> GPIO57_W

Bit 25 - GPIO57 interrupt.

pub fn gpio56(&mut self) -> GPIO56_W

Bit 24 - GPIO56 interrupt.

pub fn gpio55(&mut self) -> GPIO55_W

Bit 23 - GPIO55 interrupt.

pub fn gpio54(&mut self) -> GPIO54_W

Bit 22 - GPIO54 interrupt.

pub fn gpio53(&mut self) -> GPIO53_W

Bit 21 - GPIO53 interrupt.

pub fn gpio52(&mut self) -> GPIO52_W

Bit 20 - GPIO52 interrupt.

pub fn gpio51(&mut self) -> GPIO51_W

Bit 19 - GPIO51 interrupt.

pub fn gpio50(&mut self) -> GPIO50_W

Bit 18 - GPIO50 interrupt.

pub fn gpio49(&mut self) -> GPIO49_W

Bit 17 - GPIO49 interrupt.

pub fn gpio48(&mut self) -> GPIO48_W

Bit 16 - GPIO48 interrupt.

pub fn gpio47(&mut self) -> GPIO47_W

Bit 15 - GPIO47 interrupt.

pub fn gpio46(&mut self) -> GPIO46_W

Bit 14 - GPIO46 interrupt.

pub fn gpio45(&mut self) -> GPIO45_W

Bit 13 - GPIO45 interrupt.

pub fn gpio44(&mut self) -> GPIO44_W

Bit 12 - GPIO44 interrupt.

pub fn gpio43(&mut self) -> GPIO43_W

Bit 11 - GPIO43 interrupt.

pub fn gpio42(&mut self) -> GPIO42_W

Bit 10 - GPIO42 interrupt.

pub fn gpio41(&mut self) -> GPIO41_W

Bit 9 - GPIO41 interrupt.

pub fn gpio40(&mut self) -> GPIO40_W

Bit 8 - GPIO40 interrupt.

pub fn gpio39(&mut self) -> GPIO39_W

Bit 7 - GPIO39 interrupt.

pub fn gpio38(&mut self) -> GPIO38_W

Bit 6 - GPIO38 interrupt.

pub fn gpio37(&mut self) -> GPIO37_W

Bit 5 - GPIO37 interrupt.

pub fn gpio36(&mut self) -> GPIO36_W

Bit 4 - GPIO36 interrupt.

pub fn gpio35(&mut self) -> GPIO35_W

Bit 3 - GPIO35 interrupt.

pub fn gpio34(&mut self) -> GPIO34_W

Bit 2 - GPIO34 interrupt.

pub fn gpio33(&mut self) -> GPIO33_W

Bit 1 - GPIO33 interrupt.

pub fn gpio32(&mut self) -> GPIO32_W

Bit 0 - GPIO32 interrupt.

impl W<u32, Reg<u32, _INT1SET>>

pub fn gpio63(&mut self) -> GPIO63_W

Bit 31 - GPIO63 interrupt.

pub fn gpio62(&mut self) -> GPIO62_W

Bit 30 - GPIO62 interrupt.

pub fn gpio61(&mut self) -> GPIO61_W

Bit 29 - GPIO61 interrupt.

pub fn gpio60(&mut self) -> GPIO60_W

Bit 28 - GPIO60 interrupt.

pub fn gpio59(&mut self) -> GPIO59_W

Bit 27 - GPIO59 interrupt.

pub fn gpio58(&mut self) -> GPIO58_W

Bit 26 - GPIO58 interrupt.

pub fn gpio57(&mut self) -> GPIO57_W

Bit 25 - GPIO57 interrupt.

pub fn gpio56(&mut self) -> GPIO56_W

Bit 24 - GPIO56 interrupt.

pub fn gpio55(&mut self) -> GPIO55_W

Bit 23 - GPIO55 interrupt.

pub fn gpio54(&mut self) -> GPIO54_W

Bit 22 - GPIO54 interrupt.

pub fn gpio53(&mut self) -> GPIO53_W

Bit 21 - GPIO53 interrupt.

pub fn gpio52(&mut self) -> GPIO52_W

Bit 20 - GPIO52 interrupt.

pub fn gpio51(&mut self) -> GPIO51_W

Bit 19 - GPIO51 interrupt.

pub fn gpio50(&mut self) -> GPIO50_W

Bit 18 - GPIO50 interrupt.

pub fn gpio49(&mut self) -> GPIO49_W

Bit 17 - GPIO49 interrupt.

pub fn gpio48(&mut self) -> GPIO48_W

Bit 16 - GPIO48 interrupt.

pub fn gpio47(&mut self) -> GPIO47_W

Bit 15 - GPIO47 interrupt.

pub fn gpio46(&mut self) -> GPIO46_W

Bit 14 - GPIO46 interrupt.

pub fn gpio45(&mut self) -> GPIO45_W

Bit 13 - GPIO45 interrupt.

pub fn gpio44(&mut self) -> GPIO44_W

Bit 12 - GPIO44 interrupt.

pub fn gpio43(&mut self) -> GPIO43_W

Bit 11 - GPIO43 interrupt.

pub fn gpio42(&mut self) -> GPIO42_W

Bit 10 - GPIO42 interrupt.

pub fn gpio41(&mut self) -> GPIO41_W

Bit 9 - GPIO41 interrupt.

pub fn gpio40(&mut self) -> GPIO40_W

Bit 8 - GPIO40 interrupt.

pub fn gpio39(&mut self) -> GPIO39_W

Bit 7 - GPIO39 interrupt.

pub fn gpio38(&mut self) -> GPIO38_W

Bit 6 - GPIO38 interrupt.

pub fn gpio37(&mut self) -> GPIO37_W

Bit 5 - GPIO37 interrupt.

pub fn gpio36(&mut self) -> GPIO36_W

Bit 4 - GPIO36 interrupt.

pub fn gpio35(&mut self) -> GPIO35_W

Bit 3 - GPIO35 interrupt.

pub fn gpio34(&mut self) -> GPIO34_W

Bit 2 - GPIO34 interrupt.

pub fn gpio33(&mut self) -> GPIO33_W

Bit 1 - GPIO33 interrupt.

pub fn gpio32(&mut self) -> GPIO32_W

Bit 0 - GPIO32 interrupt.

impl W<u32, Reg<u32, _INT2EN>>

pub fn gpio73(&mut self) -> GPIO73_W

Bit 9 - GPIO73 interrupt.

pub fn gpio72(&mut self) -> GPIO72_W

Bit 8 - GPIO72 interrupt.

pub fn gpio71(&mut self) -> GPIO71_W

Bit 7 - GPIO71 interrupt.

pub fn gpio70(&mut self) -> GPIO70_W

Bit 6 - GPIO70 interrupt.

pub fn gpio69(&mut self) -> GPIO69_W

Bit 5 - GPIO69 interrupt.

pub fn gpio68(&mut self) -> GPIO68_W

Bit 4 - GPIO68 interrupt.

pub fn gpio67(&mut self) -> GPIO67_W

Bit 3 - GPIO67 interrupt.

pub fn gpio66(&mut self) -> GPIO66_W

Bit 2 - GPIO66 interrupt.

pub fn gpio65(&mut self) -> GPIO65_W

Bit 1 - GPIO65 interrupt.

pub fn gpio64(&mut self) -> GPIO64_W

Bit 0 - GPIO64 interrupt.

impl W<u32, Reg<u32, _INT2STAT>>

pub fn gpio73(&mut self) -> GPIO73_W

Bit 9 - GPIO73 interrupt.

pub fn gpio72(&mut self) -> GPIO72_W

Bit 8 - GPIO72 interrupt.

pub fn gpio71(&mut self) -> GPIO71_W

Bit 7 - GPIO71 interrupt.

pub fn gpio70(&mut self) -> GPIO70_W

Bit 6 - GPIO70 interrupt.

pub fn gpio69(&mut self) -> GPIO69_W

Bit 5 - GPIO69 interrupt.

pub fn gpio68(&mut self) -> GPIO68_W

Bit 4 - GPIO68 interrupt.

pub fn gpio67(&mut self) -> GPIO67_W

Bit 3 - GPIO67 interrupt.

pub fn gpio66(&mut self) -> GPIO66_W

Bit 2 - GPIO66 interrupt.

pub fn gpio65(&mut self) -> GPIO65_W

Bit 1 - GPIO65 interrupt.

pub fn gpio64(&mut self) -> GPIO64_W

Bit 0 - GPIO64 interrupt.

impl W<u32, Reg<u32, _INT2CLR>>

pub fn gpio73(&mut self) -> GPIO73_W

Bit 9 - GPIO73 interrupt.

pub fn gpio72(&mut self) -> GPIO72_W

Bit 8 - GPIO72 interrupt.

pub fn gpio71(&mut self) -> GPIO71_W

Bit 7 - GPIO71 interrupt.

pub fn gpio70(&mut self) -> GPIO70_W

Bit 6 - GPIO70 interrupt.

pub fn gpio69(&mut self) -> GPIO69_W

Bit 5 - GPIO69 interrupt.

pub fn gpio68(&mut self) -> GPIO68_W

Bit 4 - GPIO68 interrupt.

pub fn gpio67(&mut self) -> GPIO67_W

Bit 3 - GPIO67 interrupt.

pub fn gpio66(&mut self) -> GPIO66_W

Bit 2 - GPIO66 interrupt.

pub fn gpio65(&mut self) -> GPIO65_W

Bit 1 - GPIO65 interrupt.

pub fn gpio64(&mut self) -> GPIO64_W

Bit 0 - GPIO64 interrupt.

impl W<u32, Reg<u32, _INT2SET>>

pub fn gpio73(&mut self) -> GPIO73_W

Bit 9 - GPIO73 interrupt.

pub fn gpio72(&mut self) -> GPIO72_W

Bit 8 - GPIO72 interrupt.

pub fn gpio71(&mut self) -> GPIO71_W

Bit 7 - GPIO71 interrupt.

pub fn gpio70(&mut self) -> GPIO70_W

Bit 6 - GPIO70 interrupt.

pub fn gpio69(&mut self) -> GPIO69_W

Bit 5 - GPIO69 interrupt.

pub fn gpio68(&mut self) -> GPIO68_W

Bit 4 - GPIO68 interrupt.

pub fn gpio67(&mut self) -> GPIO67_W

Bit 3 - GPIO67 interrupt.

pub fn gpio66(&mut self) -> GPIO66_W

Bit 2 - GPIO66 interrupt.

pub fn gpio65(&mut self) -> GPIO65_W

Bit 1 - GPIO65 interrupt.

pub fn gpio64(&mut self) -> GPIO64_W

Bit 0 - GPIO64 interrupt.

impl W<u32, Reg<u32, _DBGCTRL>>

pub fn gclk5(&mut self) -> GCLK5_W

Bit 5 - Gate IOM5 CLK in SPI mode, allowing external input clock

pub fn gclk4(&mut self) -> GCLK4_W

Bit 4 - Gate IOM4 CLK in SPI mode, allowing external input clock

pub fn gclk3(&mut self) -> GCLK3_W

Bit 3 - Gate IOM3 CLK in SPI mode, allowing external input clock

pub fn gclk2(&mut self) -> GCLK2_W

Bit 2 - Gate IOM2 CLK in SPI mode, allowing external input clock

pub fn gclk1(&mut self) -> GCLK1_W

Bit 1 - Gate IOM1 CLK in SPI mode, allowing external input clock

pub fn gclk0(&mut self) -> GCLK0_W

Bit 0 - Gate IOM0 CLK in SPI mode, allowing external input clock

impl W<u32, Reg<u32, _FIFO>>

pub fn fifo(&mut self) -> FIFO_W

Bits 0:31 - FIFO direct access. Only locations 0 - 3F will return valid information.

impl W<u32, Reg<u32, _FIFOPTR>>

pub fn fifo1rem(&mut self) -> FIFO1REM_W

Bits 24:31 - The number of remaining data bytes slots currently in FIFO 1 (written by interface, read by MCU)

pub fn fifo1siz(&mut self) -> FIFO1SIZ_W

Bits 16:23 - The number of valid data bytes currently in FIFO 1 (written by interface, read by MCU)

pub fn fifo0rem(&mut self) -> FIFO0REM_W

Bits 8:15 - The number of remaining data bytes slots currently in FIFO 0 (written by MCU, read by interface)

pub fn fifo0siz(&mut self) -> FIFO0SIZ_W

Bits 0:7 - The number of valid data bytes currently in the FIFO 0 (written by MCU, read by interface)

impl W<u32, Reg<u32, _FIFOTHR>>

pub fn fifowthr(&mut self) -> FIFOWTHR_W

Bits 8:13 - FIFO write threshold in bytes. A value of 0 will disable the write FIFO level from activating the threshold interrupt. If this field is non-zero, it will trigger a threshold interrupt when the write FIFO contains FIFOWTHR free bytes, as indicated by the FIFO0REM field. This is intended to signal when a transfer of FIFOWTHR bytes can be done from the host to the IOM write FIFO to support large IOM write operations.

pub fn fiforthr(&mut self) -> FIFORTHR_W

Bits 0:5 - FIFO read threshold in bytes. A value of 0 will disable the read FIFO level from activating the threshold interrupt. If this field is non-zero, it will trigger a threshold interrupt when the read FIFO contains FIFORTHR valid bytes of data, as indicated by the FIFO1SIZ field. This is intended to signal when a data transfer of FIFORTHR bytes can be done from the IOM module to the host via the read FIFO to support large IOM read operations.

impl W<u32, Reg<u32, _FIFOPOP>>

pub fn fifodout(&mut self) -> FIFODOUT_W

Bits 0:31 - This register will return the read data indicated by the current read pointer on reads. If the POPWR control bit in the FIFOCTRL register is reset (0), the FIFO read pointer will be advanced by one word as a result of the read. If the POPWR bit is set (1), the FIFO read pointer will only be advanced after a write operation to this register. The write data is ignored for this register. If less than a even word multiple is available, and the command is completed, the module will return the word containing these bytes and undetermined data in the unused fields of the word.

impl W<u32, Reg<u32, _FIFOPUSH>>

pub fn fifodin(&mut self) -> FIFODIN_W

Bits 0:31 - This register is used to write the FIFORAM in FIFO mode and will cause a push event to occur to the next open slot within the FIFORAM. Writing to this register will cause the write point to increment by 1 word(4 bytes).

impl W<u32, Reg<u32, _FIFOCTRL>>

pub fn fiforstn(&mut self) -> FIFORSTN_W

Bit 1 - Active low manual reset of the FIFO. Write to 0 to reset FIFO, and then write to 1 to remove the reset.

pub fn popwr(&mut self) -> POPWR_W

Bit 0 - Selects the mode in which 'pop' events are done for the FIFO read operations. A value of '1' will prevent a pop event on a read operation, and will require a write to the FIFOPOP register to create a pop event. A value of '0' in this register will allow a pop event to occur on the read of the FIFOPOP register, and may cause inadvertent FIFO pops when used in a debugging mode.

impl W<u32, Reg<u32, _FIFOLOC>>

pub fn fiforptr(&mut self) -> FIFORPTR_W

Bits 8:11 - Current FIFO read pointer. Used to index into the incoming FIFO (FIFO1), which is used to store read data returned from external devices during a read operation.

pub fn fifowptr(&mut self) -> FIFOWPTR_W

Bits 0:3 - Current FIFO write pointer. Value is the index into the outgoing FIFO (FIFO0), which is used during write operations to external devices.

impl W<u32, Reg<u32, _INTEN>>

pub fn cqerr(&mut self) -> CQERR_W

Bit 14 - Error during command queue operations

pub fn cqupd(&mut self) -> CQUPD_W

Bit 13 - CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the CQ operation.

pub fn cqpaused(&mut self) -> CQPAUSED_W

Bit 12 - Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register, the mask is active in the CQIRQMASK field and the event occurs.

pub fn derr(&mut self) -> DERR_W

Bit 11 - DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified.

pub fn dcmp(&mut self) -> DCMP_W

Bit 10 - DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state

pub fn arb(&mut self) -> ARB_W

Bit 9 - Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus.

pub fn stop(&mut self) -> STOP_W

Bit 8 - STOP command interrupt. Asserted when another master on the bus has signaled a STOP command.

pub fn start(&mut self) -> START_W

Bit 7 - START command interrupt. Asserted when another master on the bus has signaled a START command.

pub fn icmd(&mut self) -> ICMD_W

Bit 6 - illegal command interrupt. Asserted when a command is written when an active command is in progress.

pub fn iacc(&mut self) -> IACC_W

Bit 5 - illegal FIFO access interrupt. Asserted when there is a overflow or underflow event

pub fn nak(&mut self) -> NAK_W

Bit 4 - I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus.

pub fn fovfl(&mut self) -> FOVFL_W

Bit 3 - Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop.

pub fn fundfl(&mut self) -> FUNDFL_W

Bit 2 - Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty FIFO.

pub fn thr(&mut self) -> THR_W

Bit 1 - FIFO Threshold interrupt. For write operations, asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field. For read operations, asserted when the number of valid bytes in the read FIFO equals of exceeds the value set in the RTHR field.

pub fn cmdcmp(&mut self) -> CMDCMP_W

Bit 0 - Command complete interrupt

impl W<u32, Reg<u32, _INTSTAT>>

pub fn cqerr(&mut self) -> CQERR_W

Bit 14 - Error during command queue operations

pub fn cqupd(&mut self) -> CQUPD_W

Bit 13 - CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the CQ operation.

pub fn cqpaused(&mut self) -> CQPAUSED_W

Bit 12 - Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register, the mask is active in the CQIRQMASK field and the event occurs.

pub fn derr(&mut self) -> DERR_W

Bit 11 - DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified.

pub fn dcmp(&mut self) -> DCMP_W

Bit 10 - DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state

pub fn arb(&mut self) -> ARB_W

Bit 9 - Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus.

pub fn stop(&mut self) -> STOP_W

Bit 8 - STOP command interrupt. Asserted when another master on the bus has signaled a STOP command.

pub fn start(&mut self) -> START_W

Bit 7 - START command interrupt. Asserted when another master on the bus has signaled a START command.

pub fn icmd(&mut self) -> ICMD_W

Bit 6 - illegal command interrupt. Asserted when a command is written when an active command is in progress.

pub fn iacc(&mut self) -> IACC_W

Bit 5 - illegal FIFO access interrupt. Asserted when there is a overflow or underflow event

pub fn nak(&mut self) -> NAK_W

Bit 4 - I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus.

pub fn fovfl(&mut self) -> FOVFL_W

Bit 3 - Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop.

pub fn fundfl(&mut self) -> FUNDFL_W

Bit 2 - Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty FIFO.

pub fn thr(&mut self) -> THR_W

Bit 1 - FIFO Threshold interrupt. For write operations, asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field. For read operations, asserted when the number of valid bytes in the read FIFO equals of exceeds the value set in the RTHR field.

pub fn cmdcmp(&mut self) -> CMDCMP_W

Bit 0 - Command complete interrupt

impl W<u32, Reg<u32, _INTCLR>>

pub fn cqerr(&mut self) -> CQERR_W

Bit 14 - Error during command queue operations

pub fn cqupd(&mut self) -> CQUPD_W

Bit 13 - CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the CQ operation.

pub fn cqpaused(&mut self) -> CQPAUSED_W

Bit 12 - Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register, the mask is active in the CQIRQMASK field and the event occurs.

pub fn derr(&mut self) -> DERR_W

Bit 11 - DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified.

pub fn dcmp(&mut self) -> DCMP_W

Bit 10 - DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state

pub fn arb(&mut self) -> ARB_W

Bit 9 - Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus.

pub fn stop(&mut self) -> STOP_W

Bit 8 - STOP command interrupt. Asserted when another master on the bus has signaled a STOP command.

pub fn start(&mut self) -> START_W

Bit 7 - START command interrupt. Asserted when another master on the bus has signaled a START command.

pub fn icmd(&mut self) -> ICMD_W

Bit 6 - illegal command interrupt. Asserted when a command is written when an active command is in progress.

pub fn iacc(&mut self) -> IACC_W

Bit 5 - illegal FIFO access interrupt. Asserted when there is a overflow or underflow event

pub fn nak(&mut self) -> NAK_W

Bit 4 - I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus.

pub fn fovfl(&mut self) -> FOVFL_W

Bit 3 - Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop.

pub fn fundfl(&mut self) -> FUNDFL_W

Bit 2 - Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty FIFO.

pub fn thr(&mut self) -> THR_W

Bit 1 - FIFO Threshold interrupt. For write operations, asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field. For read operations, asserted when the number of valid bytes in the read FIFO equals of exceeds the value set in the RTHR field.

pub fn cmdcmp(&mut self) -> CMDCMP_W

Bit 0 - Command complete interrupt

impl W<u32, Reg<u32, _INTSET>>

pub fn cqerr(&mut self) -> CQERR_W

Bit 14 - Error during command queue operations

pub fn cqupd(&mut self) -> CQUPD_W

Bit 13 - CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the CQ operation.

pub fn cqpaused(&mut self) -> CQPAUSED_W

Bit 12 - Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register, the mask is active in the CQIRQMASK field and the event occurs.

pub fn derr(&mut self) -> DERR_W

Bit 11 - DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified.

pub fn dcmp(&mut self) -> DCMP_W

Bit 10 - DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state

pub fn arb(&mut self) -> ARB_W

Bit 9 - Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus.

pub fn stop(&mut self) -> STOP_W

Bit 8 - STOP command interrupt. Asserted when another master on the bus has signaled a STOP command.

pub fn start(&mut self) -> START_W

Bit 7 - START command interrupt. Asserted when another master on the bus has signaled a START command.

pub fn icmd(&mut self) -> ICMD_W

Bit 6 - illegal command interrupt. Asserted when a command is written when an active command is in progress.

pub fn iacc(&mut self) -> IACC_W

Bit 5 - illegal FIFO access interrupt. Asserted when there is a overflow or underflow event

pub fn nak(&mut self) -> NAK_W

Bit 4 - I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus.

pub fn fovfl(&mut self) -> FOVFL_W

Bit 3 - Write FIFO Overflow interrupt. This occurs when software tries to write to a full FIFO. The current operation does not stop.

pub fn fundfl(&mut self) -> FUNDFL_W

Bit 2 - Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty FIFO.

pub fn thr(&mut self) -> THR_W

Bit 1 - FIFO Threshold interrupt. For write operations, asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field. For read operations, asserted when the number of valid bytes in the read FIFO equals of exceeds the value set in the RTHR field.

pub fn cmdcmp(&mut self) -> CMDCMP_W

Bit 0 - Command complete interrupt

impl W<u32, Reg<u32, _CLKCFG>>

pub fn totper(&mut self) -> TOTPER_W

Bits 24:31 - Clock total clock count minus 1. This provides the total period of the divided clock -1 when the DIVEN is active. The source clock is selected by FSEL. Only applicable when DIVEN = 1.

pub fn lowper(&mut self) -> LOWPER_W

Bits 16:23 - Clock low clock count minus 1. This provides the number of clocks the divided clock will be low when the DIVEN = 1. Only applicable when DIVEN = 1.

pub fn diven(&mut self) -> DIVEN_W

Bit 12 - Enable clock division by TOTPER and LOWPER

pub fn div3(&mut self) -> DIV3_W

Bit 11 - Enable divide by 3 of the source IOCLK. Division by 3 is done before the DIVEN programmable divider, and if enabled will provide the divided by 3 clock as the source to the programmable divider.

pub fn fsel(&mut self) -> FSEL_W

Bits 8:10 - Select the input clock frequency.

pub fn ioclken(&mut self) -> IOCLKEN_W

Bit 0 - Enable for the interface clock. Must be enabled prior to executing any IO operations.

impl W<u32, Reg<u32, _SUBMODCTRL>>

pub fn smod1type(&mut self) -> SMOD1TYPE_W

Bits 5:7 - Submodule 0 module type. This is the I2C Master interface

pub fn smod1en(&mut self) -> SMOD1EN_W

Bit 4 - Submodule 1 enable (1) or disable (0)

pub fn smod0type(&mut self) -> SMOD0TYPE_W

Bits 1:3 - Submodule 0 module type. This is the SPI Master interface.

pub fn smod0en(&mut self) -> SMOD0EN_W

Bit 0 - Submodule 0 enable (1) or disable (0)

impl W<u32, Reg<u32, _CMD>>

pub fn offsetlo(&mut self) -> OFFSETLO_W

Bits 24:31 - This register holds the low order byte of offset to be used in the transaction. The number of offset bytes to use is set with bits 1:0 of the command.

pub fn cmdsel(&mut self) -> CMDSEL_W

Bits 20:21 - Command Specific selection information. Not used in Master I2C. Used as CEn select for Master SPI transactions

pub fn tsize(&mut self) -> TSIZE_W

Bits 8:19 - Defines the transaction size in bytes. The offset transfer is not included in this size.

pub fn cont(&mut self) -> CONT_W

Bit 7 - Continue to hold the bus after the current transaction if set to a 1 with a new command issued.

pub fn offsetcnt(&mut self) -> OFFSETCNT_W

Bits 5:6 - Number of offset bytes to use for the command - 0, 1, 2, 3 are valid selections. The second (byte 1) and third byte (byte 2) are read from the OFFSETHI register, and the low order byte is pulled from this register in the OFFSETLO field. Offset bytes are transmitted highest byte first. EG if OFFSETCNT == 3, OFFSETHI[15:8] will be transmitted first, then OFFSETHI[7:0] then OFFSETLO. If OFFSETCNT == 2, OFFSETHI[7:0] will be transmitted, then OFFSETLO. If OFFSETCNT == 1, only OFFSETLO will be transmitted. Offset bytes are always transmitted MSB first, regardless of the value of the LSB control bit within the module configuration.

pub fn cmd(&mut self) -> CMD_W

Bits 0:4 - Command for submodule.

impl W<u32, Reg<u32, _DCX>>

pub fn dcxen(&mut self) -> DCXEN_W

Bit 4 - DCX Signaling Enable The selected DCX signal (unused CE pin) will be driven low during write of offset byte, and high during transmission of data bytes.

pub fn ce3out(&mut self) -> CE3OUT_W

Bit 3 - Enable DCX output using CE3 output

pub fn ce2out(&mut self) -> CE2OUT_W

Bit 2 - Enable DCX output using CE2 output

pub fn ce1out(&mut self) -> CE1OUT_W

Bit 1 - Enable DCX output using CE1 output

pub fn ce0out(&mut self) -> CE0OUT_W

Bit 0 - Enable DCX output using CE0 output

impl W<u32, Reg<u32, _OFFSETHI>>

pub fn offsethi(&mut self) -> OFFSETHI_W

Bits 0:15 - Holds the high order 2 bytes of the 3 byte addressing/offset field to use with IO commands. The number of offset bytes to use is specified in the command register

impl W<u32, Reg<u32, _CMDSTAT>>

pub fn ctsize(&mut self) -> CTSIZE_W

Bits 8:19 - The current number of bytes still to be transferred with this command. This field will count down to zero.

pub fn cmdstat(&mut self) -> CMDSTAT_W

Bits 5:7 - The current status of the command execution.

pub fn ccmd(&mut self) -> CCMD_W

Bits 0:4 - current command that is being executed

impl W<u32, Reg<u32, _DMATRIGEN>>

pub fn dthren(&mut self) -> DTHREN_W

Bit 1 - Trigger DMA upon THR level reached. For M2P DMA operations (IOM writes), the trigger will assert when the write FIFO has (WTHR/4) number of words free in the write FIFO, and will transfer (WTHR/4) number of words or, if the number of words left to transfer is less than the WTHR value, will transfer the remaining byte count. For P2M DMA operations, the trigger will assert when the read FIFO has (RTHR/4) words available in the read FIFO, and will transfer (RTHR/4) words to SRAM. This trigger will NOT assert when the transaction completes and there are less than RTHR bytes left in the FIFO, since the RTHR has not been reached. In this case, the CMDCMP trigger must also be enabled to transfer the remaining read FIFO data to SRAM.

pub fn dcmdcmpen(&mut self) -> DCMDCMPEN_W

Bit 0 - Trigger DMA upon command complete. Enables the trigger of the DMA when a command is completed. When this event is triggered, the number of words transferred will be the lesser of the remaining TOTCOUNT bytes, or

impl W<u32, Reg<u32, _DMATRIGSTAT>>

pub fn dtotcmp(&mut self) -> DTOTCMP_W

Bit 2 - DMA triggered when DCMDCMP = 0, and the amount of data in the FIFO was enough to complete the DMA operation (greater than or equal to current TOTCOUNT) when the command completed. This trigger is default active when the DCMDCMP trigger is disabled and there is enough data in the FIFO to complete the DMA operation.

pub fn dthr(&mut self) -> DTHR_W

Bit 1 - Triggered DMA from THR event. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA.

pub fn dcmdcmp(&mut self) -> DCMDCMP_W

Bit 0 - Triggered DMA from Command complete event. Bit is read only and can be cleared by disabling the DCMDCMP trigger enable or by disabling DMA.

impl W<u32, Reg<u32, _DMACFG>>

pub fn dpwroff(&mut self) -> DPWROFF_W

Bit 9 - Power off module after DMA is complete. If this bit is active, the module will request to power off the supply it is attached to. If there are other units still requiring power from the same domain, power down will not be performed.

pub fn dmapri(&mut self) -> DMAPRI_W

Bit 8 - Sets the Priority of the DMA request

pub fn dmadir(&mut self) -> DMADIR_W

Bit 1 - Direction

pub fn dmaen(&mut self) -> DMAEN_W

Bit 0 - DMA Enable. Setting this bit to EN will start the DMA operation. This should be the last DMA related register set prior to issuing the command

impl W<u32, Reg<u32, _DMATOTCOUNT>>

pub fn totcount(&mut self) -> TOTCOUNT_W

Bits 0:11 - Triggered DMA from Command complete event occurred. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA.

impl W<u32, Reg<u32, _DMATARGADDR>>

pub fn targaddr28(&mut self) -> TARGADDR28_W

Bit 28 - Bit 28 of the target byte address for source of DMA (either read or write). In cases of non-word aligned addresses, the DMA logic will take care for ensuring only the target bytes are read/written. Setting to '1' will select the SRAM. Setting to '0' will select the flash

pub fn targaddr(&mut self) -> TARGADDR_W

Bits 0:20 - Bits [19:0] of the target byte address for source of DMA (either read or write). The address can be any byte alignment, and does not have to be word aligned. In cases of non-word aligned addresses, the DMA logic will take care for ensuring only the target bytes are read/written.

impl W<u32, Reg<u32, _DMASTAT>>

pub fn dmaerr(&mut self) -> DMAERR_W

Bit 2 - DMA Error. This active high bit signals an error was encountered during the DMA operation. The bit can be cleared by writing to 0. Once set, this bit will remain set until cleared by software.

pub fn dmacpl(&mut self) -> DMACPL_W

Bit 1 - DMA Transfer Complete. This signals the end of the DMA operation. This bit can be cleared by writing to 0, and will also be cleared when a new DMA is started.

pub fn dmatip(&mut self) -> DMATIP_W

Bit 0 - DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data, transferring data, or waiting for priority. All of these will be indicated with a 1. A 0 will indicate that the DMA is fully complete and no further transactions will be done. This bit is read only.

impl W<u32, Reg<u32, _CQCFG>>

pub fn mspiflgsel(&mut self) -> MSPIFLGSEL_W

Bits 2:3 - Selects the MPSI modules used for sourcing the CQFLAG [11:8].

pub fn cqpri(&mut self) -> CQPRI_W

Bit 1 - Sets the Priority of the command queue DMA request

pub fn cqen(&mut self) -> CQEN_W

Bit 0 - Command queue enable. When set, will enable the processing of the command queue and fetches of address/data pairs will proceed from the word address within the CQADDR register. Can be disabled using a CQ executed write to this bit as well.

impl W<u32, Reg<u32, _CQADDR>>

pub fn cqaddr28(&mut self) -> CQADDR28_W

Bit 28 - Bit 28 of target byte address for source of CQ. Used to denote Flash (0) or SRAM (1) access

pub fn cqaddr(&mut self) -> CQADDR_W

Bits 2:20 - Bits 19:2 of target byte address for source of CQ. The buffer must be aligned on a word boundary

impl W<u32, Reg<u32, _CQSTAT>>

pub fn cqerr(&mut self) -> CQERR_W

Bit 2 - Command queue processing Error. This active high bit signals that an error was encountered during the CQ operation.

pub fn cqpaused(&mut self) -> CQPAUSED_W

Bit 1 - Command queue operation is currently paused.

pub fn cqtip(&mut self) -> CQTIP_W

Bit 0 - Command queue Transfer In Progress indicator. 1 will indicate that a CQ transfer is active and this will remain active even when paused waiting for external event.

impl W<u32, Reg<u32, _CQFLAGS>>

pub fn cqirqmask(&mut self) -> CQIRQMASK_W

Bits 16:31 - Mask the bits used to generate the command queue interrupt. A '1' in the bit position will enable the pause event to trigger the interrupt, if the CQWT_int interrupt is enabled. Bits definitions are the same as CQPAUSE

pub fn cqflags(&mut self) -> CQFLAGS_W

Bits 0:15 - Current flag status (read-only). Bits [7:0] are software controllable and bits [15:8] are hardware status.

impl W<u32, Reg<u32, _CQSETCLEAR>>

pub fn cqfclr(&mut self) -> CQFCLR_W

Bits 16:23 - Clear CQFlag status bits. Will clear to 0 any SWFLAG with a '1' in the corresponding bit position of this field

pub fn cqftgl(&mut self) -> CQFTGL_W

Bits 8:15 - Toggle the indicated bit. Will toggle the value of any SWFLAG with a '1' in the corresponding bit position of this field

pub fn cqfset(&mut self) -> CQFSET_W

Bits 0:7 - Set CQFlag status bits. Will set to 1 the value of any SWFLAG with a '1' in the corresponding bit position of this field

impl W<u32, Reg<u32, _CQPAUSEEN>>

pub fn cqpen(&mut self) -> CQPEN_W

Bits 0:15 - Enables the specified event to pause command processing when active

impl W<u32, Reg<u32, _CQCURIDX>>

pub fn cqcuridx(&mut self) -> CQCURIDX_W

Bits 0:7 - Holds 8 bits of data that will be compared with the CQENDIX register field. If the values match, the IDXEQ pause event will be activated, which will cause the pausing of command queue operation if the IDXEQ bit is enabled in CQPAUSEEN.

impl W<u32, Reg<u32, _CQENDIDX>>

pub fn cqendidx(&mut self) -> CQENDIDX_W

Bits 0:7 - Holds 8 bits of data that will be compared with the CQCURIX register field. If the values match, the IDXEQ pause event will be activated, which will cause the pausing of command queue operation if the IDXEQ bit is enabled in CQPAUSEEN.

impl W<u32, Reg<u32, _STATUS>>

pub fn idlest(&mut self) -> IDLEST_W

Bit 2 - indicates if the active I/O state machine is IDLE. Note - The state machine could be in idle state due to hold-offs from data availability, or as the command gets propagated into the logic from the registers.

pub fn cmdact(&mut self) -> CMDACT_W

Bit 1 - Indicates if the active I/O Command is currently processing a transaction, or command is complete, but the FIFO pointers are still synchronizing internally. This bit will go high at the start of the transaction, and will go low when the command is complete, and the data and pointers within the FIFO have been synchronized.

pub fn err(&mut self) -> ERR_W

Bit 0 - Bit has been deprecated. Please refer to the other error indicators. This will always return 0.

impl W<u32, Reg<u32, _MSPICFG>>

pub fn mspirst(&mut self) -> MSPIRST_W

Bit 30 - Not used. To reset the module, toggle the SMOD_EN for the module

pub fn doutdly(&mut self) -> DOUTDLY_W

Bits 27:29 - Delay tap to use for the output signal (MOSI). This give more hold time on the output data

pub fn dindly(&mut self) -> DINDLY_W

Bits 24:26 - Delay tap to use for the input signal (MISO). This gives more hold time on the input data.

pub fn spilsb(&mut self) -> SPILSB_W

Bit 23 - Selects data transfer as MSB first (0) or LSB first (1) for the data portion of the SPI transaction. The offset bytes are always transmitted MSB first.

pub fn rdfcpol(&mut self) -> RDFCPOL_W

Bit 22 - selects the read flow control signal polarity.

pub fn wtfcpol(&mut self) -> WTFCPOL_W

Bit 21 - selects the write flow control signal polarity. The transfers are halted when the selected flow control signal is OPPOSITE polarity of bit. (For example: WTFCPOL = 0 will allow a IRQ=1 to pause transfers).

pub fn wtfcirq(&mut self) -> WTFCIRQ_W

Bit 20 - selects the write mode flow control signal.

pub fn mosiinv(&mut self) -> MOSIINV_W

Bit 18 - inverts MOSI when flow control is enabled.

pub fn rdfc(&mut self) -> RDFC_W

Bit 17 - enables read mode flow control.

pub fn wtfc(&mut self) -> WTFC_W

Bit 16 - enables write mode flow control.

pub fn fulldup(&mut self) -> FULLDUP_W

Bit 2 - Enables full duplex mode for Master SPI write operations. Data will be captured simultaneously into the read FIFO

pub fn spha(&mut self) -> SPHA_W

Bit 1 - selects SPI phase.

pub fn spol(&mut self) -> SPOL_W

Bit 0 - selects SPI polarity.

impl W<u32, Reg<u32, _MI2CCFG>>

pub fn strdis(&mut self) -> STRDIS_W

Bit 24 - Disable detection of clock stretch events smaller than 1 cycle

pub fn smpcnt(&mut self) -> SMPCNT_W

Bits 16:23 - Number of Base clock cycles to wait before sampling the SCL clock to determine if a clock stretch event has occurred

pub fn sdaendly(&mut self) -> SDAENDLY_W

Bits 12:15 - Number of IOCLK cycles to delay the SDA output en (all transitions affected). Used to delay data relative to clock

pub fn sclendly(&mut self) -> SCLENDLY_W

Bits 8:11 - Number of IOCLK cycles to delay the rising edge of the SCL output en (clock will go low on this edge). Used to allow clock shaping.

pub fn mi2crst(&mut self) -> MI2CRST_W

Bit 6 - Not used. To reset the module, toggle the SMOD_EN for the module

pub fn sdadly(&mut self) -> SDADLY_W

Bits 4:5 - Delay to enable on the SDA output. Values are 0x0-0x3.

pub fn arben(&mut self) -> ARBEN_W

Bit 2 - Enables multi-master arbitration for the I2C master. If the bus is known to have only a single master, this function can be disabled to save clock cycles on I2C transactions

pub fn i2clsb(&mut self) -> I2CLSB_W

Bit 1 - Direction of data transmit and receive, MSB(0) or LSB(1) first. Default per I2C specification is MSB first. This applies to both read and write data, and read data will be bit

pub fn addrsz(&mut self) -> ADDRSZ_W

Bit 0 - Sets the I2C master device address size to either 7 bits (0) or 10 bits (1).

impl W<u32, Reg<u32, _DEVCFG>>

pub fn devaddr(&mut self) -> DEVADDR_W

Bits 0:9 - I2C address of the device that the Master will use to target for read/write operations. This can be either a 7-bit or 10-bit address.

impl W<u32, Reg<u32, _IOMDBG>>

pub fn dbgdata(&mut self) -> DBGDATA_W

Bits 3:31 - Debug control for various options. DBGDATA[1:0] is used to select between different debug data available in the DBG0 and DBG1 registers.

pub fn apbclkon(&mut self) -> APBCLKON_W

Bit 2 - APBCLK debug clock control. Enable APB_CLK to be active when this bit is '1'. Otherwise, the clock is controlled with gating from the logic as needed.

pub fn ioclkon(&mut self) -> IOCLKON_W

Bit 1 - IOCLK debug clock control. Enable IO_CLK to be active when this bit is '1'. Otherwise, the clock is controlled with gating from the logic as needed.

pub fn dbgen(&mut self) -> DBGEN_W

Bit 0 - Debug Enable. Setting bit will enable the update of data within this register, otherwise it is clock gated for power savings

impl W<u32, Reg<u32, _FIFOPTR>>

pub fn fifosiz(&mut self) -> FIFOSIZ_W

Bits 8:15 - The number of bytes currently in the hardware FIFO.

pub fn fifoptr(&mut self) -> FIFOPTR_W

Bits 0:7 - Current FIFO pointer.

impl W<u32, Reg<u32, _FIFOCFG>>

pub fn robase(&mut self) -> ROBASE_W

Bits 24:29 - Defines the read-only area. The IO Slave read-only area is situated in LRAM at (ROBASE8) to (FIFOBASE8-1)

pub fn fifomax(&mut self) -> FIFOMAX_W

Bits 8:13 - These bits hold the maximum FIFO address in 8 byte segments. It is also the beginning of the RAM area of the LRAM. Note that no RAM area is configured if FIFOMAX is set to 0x1F.

pub fn fifobase(&mut self) -> FIFOBASE_W

Bits 0:4 - These bits hold the base address of the I/O FIFO in 8 byte segments. The IO Slave FIFO is situated in LRAM at (FIFOBASE8) to (FIFOMAX8-1).

impl W<u32, Reg<u32, _FIFOTHR>>

pub fn fifothr(&mut self) -> FIFOTHR_W

Bits 0:7 - FIFO size interrupt threshold.

impl W<u32, Reg<u32, _FUPD>>

pub fn ioread(&mut self) -> IOREAD_W

Bit 1 - This bit field indicates an IO read is active.

pub fn fifoupd(&mut self) -> FIFOUPD_W

Bit 0 - This bit indicates that a FIFO update is underway.

impl W<u32, Reg<u32, _FIFOCTR>>

pub fn fifoctr(&mut self) -> FIFOCTR_W

Bits 0:9 - Virtual FIFO byte count

impl W<u32, Reg<u32, _FIFOINC>>

pub fn fifoinc(&mut self) -> FIFOINC_W

Bits 0:9 - Increment the Overall FIFO Counter by this value on a write

impl W<u32, Reg<u32, _CFG>>

pub fn ifcen(&mut self) -> IFCEN_W

Bit 31 - IOSLAVE interface enable.

pub fn i2caddr(&mut self) -> I2CADDR_W

Bits 8:19 - 7-bit or 10-bit I2C device address.

pub fn startrd(&mut self) -> STARTRD_W

Bit 4 - This bit holds the cycle to initiate an I/O RAM read.

pub fn lsb(&mut self) -> LSB_W

Bit 2 - This bit selects the transfer bit ordering.

pub fn spol(&mut self) -> SPOL_W

Bit 1 - This bit selects SPI polarity.

pub fn ifcsel(&mut self) -> IFCSEL_W

Bit 0 - This bit selects the I/O interface.

impl W<u32, Reg<u32, _PRENC>>

pub fn prenc(&mut self) -> PRENC_W

Bits 0:4 - These bits hold the priority encode of the REGACC interrupts.

impl W<u32, Reg<u32, _IOINTCTL>>

pub fn iointset(&mut self) -> IOINTSET_W

Bits 24:31 - These bits set the IOINT interrupts when written with a 1.

pub fn iointclr(&mut self) -> IOINTCLR_W

Bit 16 - This bit clears all of the IOINT interrupts when written with a 1.

pub fn ioint(&mut self) -> IOINT_W

Bits 8:15 - These bits read the IOINT interrupts.

pub fn iointen(&mut self) -> IOINTEN_W

Bits 0:7 - These read-only bits indicate whether the IOINT interrupts are enabled.

impl W<u32, Reg<u32, _GENADD>>

pub fn gadata(&mut self) -> GADATA_W

Bits 0:7 - The data supplied on the last General Address reference.

impl W<u32, Reg<u32, _INTEN>>

pub fn xcmpwr(&mut self) -> XCMPWR_W

Bit 9 - Transfer complete interrupt, write to register space.

pub fn xcmpwf(&mut self) -> XCMPWF_W

Bit 8 - Transfer complete interrupt, write to FIFO space.

pub fn xcmprr(&mut self) -> XCMPRR_W

Bit 7 - Transfer complete interrupt, read from register space.

pub fn xcmprf(&mut self) -> XCMPRF_W

Bit 6 - Transfer complete interrupt, read from FIFO space.

pub fn iointw(&mut self) -> IOINTW_W

Bit 5 - IO Write interrupt.

pub fn genad(&mut self) -> GENAD_W

Bit 4 - I2C General Address interrupt.

pub fn frderr(&mut self) -> FRDERR_W

Bit 3 - FIFO Read Error interrupt.

pub fn fundfl(&mut self) -> FUNDFL_W

Bit 2 - FIFO Underflow interrupt.

pub fn fovfl(&mut self) -> FOVFL_W

Bit 1 - FIFO Overflow interrupt.

pub fn fsize(&mut self) -> FSIZE_W

Bit 0 - FIFO Size interrupt.

impl W<u32, Reg<u32, _INTSTAT>>

pub fn xcmpwr(&mut self) -> XCMPWR_W

Bit 9 - Transfer complete interrupt, write to register space.

pub fn xcmpwf(&mut self) -> XCMPWF_W

Bit 8 - Transfer complete interrupt, write to FIFO space.

pub fn xcmprr(&mut self) -> XCMPRR_W

Bit 7 - Transfer complete interrupt, read from register space.

pub fn xcmprf(&mut self) -> XCMPRF_W

Bit 6 - Transfer complete interrupt, read from FIFO space.

pub fn iointw(&mut self) -> IOINTW_W

Bit 5 - IO Write interrupt.

pub fn genad(&mut self) -> GENAD_W

Bit 4 - I2C General Address interrupt.

pub fn frderr(&mut self) -> FRDERR_W

Bit 3 - FIFO Read Error interrupt.

pub fn fundfl(&mut self) -> FUNDFL_W

Bit 2 - FIFO Underflow interrupt.

pub fn fovfl(&mut self) -> FOVFL_W

Bit 1 - FIFO Overflow interrupt.

pub fn fsize(&mut self) -> FSIZE_W

Bit 0 - FIFO Size interrupt.

impl W<u32, Reg<u32, _INTCLR>>

pub fn xcmpwr(&mut self) -> XCMPWR_W

Bit 9 - Transfer complete interrupt, write to register space.

pub fn xcmpwf(&mut self) -> XCMPWF_W

Bit 8 - Transfer complete interrupt, write to FIFO space.

pub fn xcmprr(&mut self) -> XCMPRR_W

Bit 7 - Transfer complete interrupt, read from register space.

pub fn xcmprf(&mut self) -> XCMPRF_W

Bit 6 - Transfer complete interrupt, read from FIFO space.

pub fn iointw(&mut self) -> IOINTW_W

Bit 5 - IO Write interrupt.

pub fn genad(&mut self) -> GENAD_W

Bit 4 - I2C General Address interrupt.

pub fn frderr(&mut self) -> FRDERR_W

Bit 3 - FIFO Read Error interrupt.

pub fn fundfl(&mut self) -> FUNDFL_W

Bit 2 - FIFO Underflow interrupt.

pub fn fovfl(&mut self) -> FOVFL_W

Bit 1 - FIFO Overflow interrupt.

pub fn fsize(&mut self) -> FSIZE_W

Bit 0 - FIFO Size interrupt.

impl W<u32, Reg<u32, _INTSET>>

pub fn xcmpwr(&mut self) -> XCMPWR_W

Bit 9 - Transfer complete interrupt, write to register space.

pub fn xcmpwf(&mut self) -> XCMPWF_W

Bit 8 - Transfer complete interrupt, write to FIFO space.

pub fn xcmprr(&mut self) -> XCMPRR_W

Bit 7 - Transfer complete interrupt, read from register space.

pub fn xcmprf(&mut self) -> XCMPRF_W

Bit 6 - Transfer complete interrupt, read from FIFO space.

pub fn iointw(&mut self) -> IOINTW_W

Bit 5 - IO Write interrupt.

pub fn genad(&mut self) -> GENAD_W

Bit 4 - I2C General Address interrupt.

pub fn frderr(&mut self) -> FRDERR_W

Bit 3 - FIFO Read Error interrupt.

pub fn fundfl(&mut self) -> FUNDFL_W

Bit 2 - FIFO Underflow interrupt.

pub fn fovfl(&mut self) -> FOVFL_W

Bit 1 - FIFO Overflow interrupt.

pub fn fsize(&mut self) -> FSIZE_W

Bit 0 - FIFO Size interrupt.

impl W<u32, Reg<u32, _REGACCINTEN>>

pub fn regacc(&mut self) -> REGACC_W

Bits 0:31 - Register access interrupts.

impl W<u32, Reg<u32, _REGACCINTSTAT>>

pub fn regacc(&mut self) -> REGACC_W

Bits 0:31 - Register access interrupts.

impl W<u32, Reg<u32, _REGACCINTCLR>>

pub fn regacc(&mut self) -> REGACC_W

Bits 0:31 - Register access interrupts.

impl W<u32, Reg<u32, _REGACCINTSET>>

pub fn regacc(&mut self) -> REGACC_W

Bits 0:31 - Register access interrupts.

impl W<u32, Reg<u32, _CHIPPN>>

pub fn partnum(&mut self) -> PARTNUM_W

Bits 0:31 - BCD part number.

impl W<u32, Reg<u32, _CHIPID0>>

pub fn chipid0(&mut self) -> CHIPID0_W

Bits 0:31 - Unique chip ID 0.

impl W<u32, Reg<u32, _CHIPID1>>

pub fn chipid1(&mut self) -> CHIPID1_W

Bits 0:31 - Unique chip ID 1.

impl W<u32, Reg<u32, _CHIPREV>>

pub fn sipart(&mut self) -> SIPART_W

Bits 8:19 - Silicon Part ID

pub fn revmaj(&mut self) -> REVMAJ_W

Bits 4:7 - Major Revision ID.

pub fn revmin(&mut self) -> REVMIN_W

Bits 0:3 - Minor Revision ID.

impl W<u32, Reg<u32, _VENDORID>>

pub fn vendorid(&mut self) -> VENDORID_W

Bits 0:31 - Unique Vendor ID

impl W<u32, Reg<u32, _SKU>>

pub fn secboot(&mut self) -> SECBOOT_W

Bit 2 - Secure boot feature allowed

pub fn allowble(&mut self) -> ALLOWBLE_W

Bit 1 - Allow BLE feature

pub fn allowburst(&mut self) -> ALLOWBURST_W

Bit 0 - Allow Burst feature

impl W<u32, Reg<u32, _FEATUREENABLE>>

pub fn burstavail(&mut self) -> BURSTAVAIL_W

Bit 6 - Availability of Burst functionality

pub fn burstack(&mut self) -> BURSTACK_W

Bit 5 - ACK for BURSTREQ

pub fn burstreq(&mut self) -> BURSTREQ_W

Bit 4 - Controls the Burst functionality

pub fn bleavail(&mut self) -> BLEAVAIL_W

Bit 2 - AVAILABILITY of the BLE functionality

pub fn bleack(&mut self) -> BLEACK_W

Bit 1 - ACK for BLEREQ

pub fn blereq(&mut self) -> BLEREQ_W

Bit 0 - Controls the BLE functionality

impl W<u32, Reg<u32, _DEBUGGER>>

pub fn lockout(&mut self) -> LOCKOUT_W

Bit 0 - Lockout of debugger (SWD).

impl W<u32, Reg<u32, _DMASRAMWRITEPROTECT2>>

pub fn dma_wprot2(&mut self) -> DMA_WPROT2_W

Bits 0:31 - Write protect SRAM from DMA. Each bit provides write protection for an 8KB region of memory. When set to 1, the region will be protected from DMA writes, when set to 0, DMA may write the region.

impl W<u32, Reg<u32, _ADCPWRDLY>>

pub fn adcpwr1(&mut self) -> ADCPWR1_W

Bits 8:15 - ADC Reference Keeper enable delay in 16 ADC CLK increments for ADC_CLKSEL = 0x1, 8 ADC CLOCK increments for ADC_CLKSEL = 0x2.

pub fn adcpwr0(&mut self) -> ADCPWR0_W

Bits 0:7 - ADC Reference Buffer Power Enable delay in 64 ADC CLK increments for ADC_CLKSEL = 0x1, 32 ADC CLOCK increments for ADC_CLKSEL = 0x2.

impl W<u32, Reg<u32, _ADCCAL>>

pub fn adccalibrated(&mut self) -> ADCCALIBRATED_W

Bit 1 - Status for ADC Calibration

pub fn calonpwrup(&mut self) -> CALONPWRUP_W

Bit 0 - Run ADC Calibration on initial power up sequence

impl W<u32, Reg<u32, _ADCBATTLOAD>>

pub fn battload(&mut self) -> BATTLOAD_W

Bit 0 - Enable the ADC battery load resistor

impl W<u32, Reg<u32, _ADCTRIM>>

pub fn adcrfbufibtrim(&mut self) -> ADCRFBUFIBTRIM_W

Bits 11:12 - ADC reference buffer input bias trim

pub fn adcrefbuftrim(&mut self) -> ADCREFBUFTRIM_W

Bits 6:10 - ADC Reference buffer trim

pub fn adcrefkeepibtrim(&mut self) -> ADCREFKEEPIBTRIM_W

Bits 0:1 - ADC Reference Ibias trim

impl W<u32, Reg<u32, _ADCREFCOMP>>

pub fn adcrfcmpen(&mut self) -> ADCRFCMPEN_W

Bit 16 - ADC Reference comparator power down

pub fn adcrefkeeptrim(&mut self) -> ADCREFKEEPTRIM_W

Bits 8:12 - ADC Reference Keeper Trim

pub fn adc_refcomp_out(&mut self) -> ADC_REFCOMP_OUT_W

Bit 0 - Output of the ADC reference comparator

impl W<u32, Reg<u32, _XTALCTRL>>

pub fn xtalicomptrim(&mut self) -> XTALICOMPTRIM_W

Bits 8:9 - XTAL ICOMP trim

pub fn xtalibuftrim(&mut self) -> XTALIBUFTRIM_W

Bits 6:7 - XTAL IBUFF trim

pub fn pwdbodxtal(&mut self) -> PWDBODXTAL_W

Bit 5 - XTAL Power down on brown out.

pub fn pdnbcmprxtal(&mut self) -> PDNBCMPRXTAL_W

Bit 4 - XTAL Oscillator Power Down Comparator.

pub fn pdnbcorextal(&mut self) -> PDNBCOREXTAL_W

Bit 3 - XTAL Oscillator Power Down Core.

pub fn bypcmprxtal(&mut self) -> BYPCMPRXTAL_W

Bit 2 - XTAL Oscillator Bypass Comparator.

pub fn fdbkdsblxtal(&mut self) -> FDBKDSBLXTAL_W

Bit 1 - XTAL Oscillator Disable Feedback.

pub fn xtalswe(&mut self) -> XTALSWE_W

Bit 0 - XTAL Software Override Enable.

impl W<u32, Reg<u32, _XTALGENCTRL>>

pub fn xtalksbiastrim(&mut self) -> XTALKSBIASTRIM_W

Bits 8:13 - XTAL IBIAS Kick start trim. This trim value is used during the startup process to enable a faster lock.

pub fn xtalbiastrim(&mut self) -> XTALBIASTRIM_W

Bits 2:7 - XTAL BIAS trim

pub fn acwarmup(&mut self) -> ACWARMUP_W

Bits 0:1 - Auto-calibration delay control

impl W<u32, Reg<u32, _MISCCTRL>>

pub fn ble_resetn(&mut self) -> BLE_RESETN_W

Bit 5 - BLE reset signal.

pub fn reserved_rw_0(&mut self) -> RESERVED_RW_0_W

Bits 0:4 - Reserved bits, always leave unchanged. The MISCCTRL register must be modified via atomic RMW, leaving this bit field completely unmodified. Failure to do so will result in unpredictable behavior.

impl W<u32, Reg<u32, _BOOTLOADER>>

pub fn secbootonrst(&mut self) -> SECBOOTONRST_W

Bits 30:31 - Indicates whether the secure boot on warm reset is enabled

pub fn secboot(&mut self) -> SECBOOT_W

Bits 28:29 - Indicates whether the secure boot on cold reset is enabled

pub fn secbootfeature(&mut self) -> SECBOOTFEATURE_W

Bits 26:27 - Indicates whether the secure boot feature is enabled.

pub fn protlock(&mut self) -> PROTLOCK_W

Bit 2 - Flash protection lock. Always resets to 1, write 1 to clear. Enables writes to flash protection register set.

pub fn sblock(&mut self) -> SBLOCK_W

Bit 1 - Secure boot lock. Always resets to 1, write 1 to clear. Enables system visibility to bootloader until set.

pub fn bootloaderlow(&mut self) -> BOOTLOADERLOW_W

Bit 0 - Determines whether the bootloader code is visible at address 0x00000000 or not. Resets to 1, write 1 to clear.

impl W<u32, Reg<u32, _SHADOWVALID>>

pub fn info0_valid(&mut self) -> INFO0_VALID_W

Bit 2 - Indicates whether INFO0 contains valid data

pub fn bldsleep(&mut self) -> BLDSLEEP_W

Bit 1 - Indicates whether the bootloader should sleep or deep sleep if no image loaded.

pub fn valid(&mut self) -> VALID_W

Bit 0 - Indicates whether the shadow registers contain valid data from the Flash Information Space.

impl W<u32, Reg<u32, _SCRATCH0>>

pub fn scratch0(&mut self) -> SCRATCH0_W

Bits 0:31 - Scratch register 0.

impl W<u32, Reg<u32, _SCRATCH1>>

pub fn scratch1(&mut self) -> SCRATCH1_W

Bits 0:31 - Scratch register 1.

impl W<u32, Reg<u32, _ICODEFAULTADDR>>

pub fn icodefaultaddr(&mut self) -> ICODEFAULTADDR_W

Bits 0:31 - The ICODE bus address observed when a Bus Fault occurred. Once an address is captured in this field, it is held until the corresponding Fault Observed bit is cleared in the FAULTSTATUS register.

impl W<u32, Reg<u32, _DCODEFAULTADDR>>

pub fn dcodefaultaddr(&mut self) -> DCODEFAULTADDR_W

Bits 0:31 - The DCODE bus address observed when a Bus Fault occurred. Once an address is captured in this field, it is held until the corresponding Fault Observed bit is cleared in the FAULTSTATUS register.

impl W<u32, Reg<u32, _SYSFAULTADDR>>

pub fn sysfaultaddr(&mut self) -> SYSFAULTADDR_W

Bits 0:31 - SYS bus address observed when a Bus Fault occurred. Once an address is captured in this field, it is held until the corresponding Fault Observed bit is cleared in the FAULTSTATUS register.

impl W<u32, Reg<u32, _FAULTSTATUS>>

pub fn sysfault(&mut self) -> SYSFAULT_W

Bit 2 - SYS Bus Decoder Fault Detected bit. When set, a fault has been detected, and the SYSFAULTADDR register will contain the bus address which generated the fault.

pub fn dcodefault(&mut self) -> DCODEFAULT_W

Bit 1 - DCODE Bus Decoder Fault Detected bit. When set, a fault has been detected, and the DCODEFAULTADDR register will contain the bus address which generated the fault.

pub fn icodefault(&mut self) -> ICODEFAULT_W

Bit 0 - The ICODE Bus Decoder Fault Detected bit. When set, a fault has been detected, and the ICODEFAULTADDR register will contain the bus address which generated the fault.

impl W<u32, Reg<u32, _FAULTCAPTUREEN>>

pub fn faultcaptureen(&mut self) -> FAULTCAPTUREEN_W

Bit 0 - Fault Capture Enable field. When set, the Fault Capture monitors are enabled and addresses which generate a hard fault are captured into the FAULTADDR registers.

impl W<u32, Reg<u32, _DBGR1>>

pub fn oneto8(&mut self) -> ONETO8_W

Bits 0:31 - Read-only register for communication validation

impl W<u32, Reg<u32, _DBGR2>>

pub fn coolcode(&mut self) -> COOLCODE_W

Bits 0:31 - Read-only register for communication validation

impl W<u32, Reg<u32, _PMUENABLE>>

pub fn enable(&mut self) -> ENABLE_W

Bit 0 - PMU Enable Control bit. When set, the MCU's PMU will place the MCU into the lowest power consuming Deep Sleep mode upon execution of a WFI instruction (dependent on the setting of the SLEEPDEEP bit in the ARM SCR register). When cleared, regardless of the requested sleep mode, the PMU will not enter the lowest power Deep Sleep mode, instead entering the Sleep mode.

impl W<u32, Reg<u32, _TPIUCTRL>>

pub fn clksel(&mut self) -> CLKSEL_W

Bits 8:10 - This field selects the frequency of the ARM M4 TPIU port.

pub fn enable(&mut self) -> ENABLE_W

Bit 0 - TPIU Enable field. When set, the ARM M4 TPIU is enabled and data can be streamed out of the MCU's SWO port using the ARM ITM and TPIU modules.

impl W<u32, Reg<u32, _OTAPOINTER>>

pub fn otapointer(&mut self) -> OTAPOINTER_W

Bits 2:31 - Flash page pointer with updated OTA image

pub fn otasblupdate(&mut self) -> OTASBLUPDATE_W

Bit 1 - Indicates that the sbl_init has been updated

pub fn otavalid(&mut self) -> OTAVALID_W

Bit 0 - Indicates that an OTA update is valid

impl W<u32, Reg<u32, _SRAMMODE>>

pub fn dprefetch_cache(&mut self) -> DPREFETCH_CACHE_W

Bit 5 - Secondary pre-fetch feature that will cache pre-fetched data across bus wait states (requires DPREFETCH to be set).

pub fn dprefetch(&mut self) -> DPREFETCH_W

Bit 4 - When set, data bus accesses to the SRAM banks will be pre-fetched (normally 2 cycle read access). Use of this mode bit is only recommended if the work flow has a large number of sequential accesses.

pub fn iprefetch_cache(&mut self) -> IPREFETCH_CACHE_W

Bit 1 - Secondary pre-fetch feature that will cache pre-fetched data across bus wait states (requires IPREFETCH to be set).

pub fn iprefetch(&mut self) -> IPREFETCH_W

Bit 0 - When set, instruction accesses to the SRAM banks will be pre-fetched (normally 2 cycle read access). Generally, this mode bit should be set for improved performance when executing instructions from SRAM.

impl W<u32, Reg<u32, _KEXTCLKSEL>>

pub fn kextclksel(&mut self) -> KEXTCLKSEL_W

Bits 0:31 - Key register value.

impl W<u32, Reg<u32, _SIMOBUCK2>>

pub fn reserved_rw_24(&mut self) -> RESERVED_RW_24_W

Bits 24:31 - Reserved bits, always leave unchanged. The SIMOBUCK2 register must be modified via atomic RMW, leaving this bit field completely unmodified. Failure to do so will result in unpredictable behavior.

pub fn simobuckcorelplowtontrim(&mut self) -> SIMOBUCKCORELPLOWTONTRIM_W

Bits 20:23 - simobuck_core_lp_low_ton_trim

pub fn simobuckcorelphightontrim(&mut self) -> SIMOBUCKCORELPHIGHTONTRIM_W

Bits 16:19 - simobuck_core_lp_high_ton_trim

pub fn reserved_rw_0(&mut self) -> RESERVED_RW_0_W

Bits 0:15 - Reserved bits, always leave unchanged. The SIMOBUCK2 register must be modified via atomic RMW, leaving this bit field completely unmodified. Failure to do so will result in unpredictable behavior.

impl W<u32, Reg<u32, _SIMOBUCK3>>

pub fn reserved_rw_31(&mut self) -> RESERVED_RW_31_W

Bit 31 - Reserved bits, always leave unchanged. The SIMOBUCK2 register must be modified via atomic RMW, leaving this bit field completely unmodified. Failure to do so will result in unpredictable behavior.

pub fn simobuckmemlphightontrim(&mut self) -> SIMOBUCKMEMLPHIGHTONTRIM_W

Bits 27:30 - simobuck_mem_lp_high_ton_trim

pub fn reserved_rw_16(&mut self) -> RESERVED_RW_16_W

Bits 16:26 - Reserved bits, always leave unchanged. The SIMOBUCK3 register must be modified via atomic RMW, leaving this bit field completely unmodified. Failure to do so will result in unpredictable behavior.

pub fn simobuckmemlplowtofftrim(&mut self) -> SIMOBUCKMEMLPLOWTOFFTRIM_W

Bits 12:15 - simobuck_mem_lp_low_toff_trim

pub fn simobuckmemlphightofftrim(&mut self) -> SIMOBUCKMEMLPHIGHTOFFTRIM_W

Bits 8:11 - simobuck_mem_lp_high_toff_trim

pub fn simobuckcorelplowtofftrim(&mut self) -> SIMOBUCKCORELPLOWTOFFTRIM_W

Bits 4:7 - simobuck_core_lp_low_toff_trim

pub fn simobuckcorelphightofftrim(&mut self) -> SIMOBUCKCORELPHIGHTOFFTRIM_W

Bits 0:3 - simobuck_core_lp_high_toff_trim

impl W<u32, Reg<u32, _SIMOBUCK4>>

pub fn simobuckcomp2timeouten(&mut self) -> SIMOBUCKCOMP2TIMEOUTEN_W

Bit 24 - simobuck_comp2_timeout_en

pub fn simobuckclkdivsel(&mut self) -> SIMOBUCKCLKDIVSEL_W

Bits 21:22 - simobuck_clkdiv_sel

pub fn simobuckmemlplowtontrim(&mut self) -> SIMOBUCKMEMLPLOWTONTRIM_W

Bits 0:3 - simobuck_mem_lp_low_ton_trim

impl W<u32, Reg<u32, _BLEBUCK2>>

pub fn blebucktond2atrim(&mut self) -> BLEBUCKTOND2ATRIM_W

Bits 12:17 - blebuck_ton_trim

pub fn blebucktonhitrim(&mut self) -> BLEBUCKTONHITRIM_W

Bits 6:11 - blebuck_ton_hi_trim

pub fn blebucktonlowtrim(&mut self) -> BLEBUCKTONLOWTRIM_W

Bits 0:5 - blebuck_ton_low_trim

impl W<u32, Reg<u32, _FLASHWPROT0>>

pub fn fw0bits(&mut self) -> FW0BITS_W

Bits 0:31 - Write protect flash 0x00000000 - 0x0007FFFF. Each bit provides write protection for 16KB chunks of flash data space. Bits are cleared by writing a 1 to the bit. When read, 0 indicates the region is protected. Bits are sticky (can be set when PROTLOCK is 1, but only cleared by reset)

impl W<u32, Reg<u32, _FLASHWPROT1>>

pub fn fw1bits(&mut self) -> FW1BITS_W

Bits 0:31 - Write protect flash 0x00080000 - 0x000FFFFF. Each bit provides write protection for 16KB chunks of flash data space. Bits are cleared by writing a 1 to the bit. When read, 0 indicates the region is protected. Bits are sticky (can be set when PROTLOCK is 1, but only cleared by reset)

impl W<u32, Reg<u32, _FLASHWPROT2>>

pub fn fw2bits(&mut self) -> FW2BITS_W

Bits 0:31 - Write protect flash 0x00100000 - 0x0017FFFF. Each bit provides write protection for 16KB chunks of flash data space. Bits are cleared by writing a 1 to the bit. When read, 0 indicates the region is protected. Bits are sticky (can be set when PROTLOCK is 1, but only cleared by reset)

impl W<u32, Reg<u32, _FLASHWPROT3>>

pub fn fw3bits(&mut self) -> FW3BITS_W

Bits 0:31 - Write protect flash 0x00180000 - 0x001FFFFF. Each bit provides write protection for 16KB chunks of flash data space. Bits are cleared by writing a 1 to the bit. When read, 0 indicates the region is protected. Bits are sticky (can be set when PROTLOCK is 1, but only cleared by reset)

impl W<u32, Reg<u32, _FLASHRPROT0>>

pub fn fr0bits(&mut self) -> FR0BITS_W

Bits 0:31 - Copy (read) protect flash 0x00000000 - 0x0007FFFF. Each bit provides read protection for 16KB chunks of flash. Bits are cleared by writing a 1 to the bit. When read, 0 indicates the region is protected. Bits are sticky (can be set when PROTLOCK is 1, but only cleared by reset)

impl W<u32, Reg<u32, _FLASHRPROT1>>

pub fn fr1bits(&mut self) -> FR1BITS_W

Bits 0:31 - Copy (read) protect flash 0x00080000 - 0x000FFFFF. Each bit provides read protection for 16KB chunks of flash. Bits are cleared by writing a 1 to the bit. When read, 0 indicates the region is protected. Bits are sticky (can be set when PROTLOCK is 1, but only cleared by reset)

impl W<u32, Reg<u32, _FLASHRPROT2>>

pub fn fr2bits(&mut self) -> FR2BITS_W

Bits 0:31 - Copy (read) protect flash 0x00100000 - 0x0017FFFF. Each bit provides read protection for 16KB chunks of flash. Bits are cleared by writing a 1 to the bit. When read, 0 indicates the region is protected. Bits are sticky (can be set when PROTLOCK is 1, but only cleared by reset)

impl W<u32, Reg<u32, _FLASHRPROT3>>

pub fn fr3bits(&mut self) -> FR3BITS_W

Bits 0:31 - Copy (read) protect flash 0x00180000 - 0x001FFFFF. Each bit provides read protection for 16KB chunks of flash. Bits are cleared by writing a 1 to the bit. When read, 0 indicates the region is protected. Bits are sticky (can be set when PROTLOCK is 1, but only cleared by reset)

impl W<u32, Reg<u32, _DMASRAMWRITEPROTECT0>>

pub fn dma_wprot0(&mut self) -> DMA_WPROT0_W

Bits 0:31 - Write protect SRAM from DMA. Each bit provides write protection for an 8KB region of memory. When set to 1, the region will be protected from DMA writes, when set to 0, DMA may write the region.

impl W<u32, Reg<u32, _DMASRAMWRITEPROTECT1>>

pub fn dma_wprot1(&mut self) -> DMA_WPROT1_W

Bits 0:31 - Write protect SRAM from DMA. Each bit provides write protection for an 8KB region of memory. When set to 1, the region will be protected from DMA writes, when set to 0, DMA may write the region.

impl W<u32, Reg<u32, _DMASRAMREADPROTECT0>>

pub fn dma_rprot0(&mut self) -> DMA_RPROT0_W

Bits 0:31 - Read protect SRAM from DMA. Each bit provides write protection for an 8KB region of memory. When set to 1, the region will be protected from DMA reads, when set to 0, DMA may read the region.

impl W<u32, Reg<u32, _DMASRAMREADPROTECT1>>

pub fn dma_rprot1(&mut self) -> DMA_RPROT1_W

Bits 0:31 - Read protect SRAM from DMA. Each bit provides write protection for an 8KB region of memory. When set to 1, the region will be protected from DMA reads, when set to 0, DMA may read the region.

impl W<u32, Reg<u32, _DMASRAMREADPROTECT2>>

pub fn dma_rprot2(&mut self) -> DMA_RPROT2_W

Bits 0:31 - Read protect SRAM from DMA. Each bit provides write protection for an 8KB region of memory. When set to 1, the region will be protected from DMA reads, when set to 0, DMA may read the region.

impl W<u32, Reg<u32, _CTRL>>

pub fn xferbytes(&mut self) -> XFERBYTES_W

Bits 16:31 - Number of bytes to transmit or receive (based on TXRX bit)

pub fn endcx(&mut self) -> ENDCX_W

Bit 12 - Enable DCX signal on data [1]

pub fn pioscramble(&mut self) -> PIOSCRAMBLE_W

Bit 11 - Enables data scrambling for PIO operations. This should only be used for data operations and never for commands to a device.

pub fn txrx(&mut self) -> TXRX_W

Bit 10 - 1 Indicates a TX operation, 0 indicates an RX operation of XFERBYTES

pub fn sendi(&mut self) -> SENDI_W

Bit 9 - Indicates whether an instruction phase should be sent (see INSTR field and ISIZE field in CFG register)

pub fn senda(&mut self) -> SENDA_W

Bit 8 - Indicates whether an address phase should be sent (see ADDR register and ASIZE field in CFG register)

pub fn enturn(&mut self) -> ENTURN_W

Bit 7 - Indicates whether TX->RX turnaround cycles should be enabled for this operation (see TURNAROUND field in CFG register).

pub fn bigendian(&mut self) -> BIGENDIAN_W

Bit 6 - 1 indicates data in FIFO is in big endian format (MSB first); 0 indicates little endian data (default, LSB first).

pub fn cont(&mut self) -> CONT_W

Bit 5 - Continuation transfer. When 1, indicates that the MSPI will hold CE low after the transaction completes. This is included for compatibility with IOM module since the MSPI transfer module can handle most cases in a single transfer. NOTE: CONT functionality only works with CLKDIV=2 (24 MHz).

pub fn enwlat(&mut self) -> ENWLAT_W

Bit 4 - Enable Write Latency Counter (time between address and first data byte). Counter value is WRITELATENCY.

pub fn quadcmd(&mut self) -> QUADCMD_W

Bit 3 - Flag indicating that the operation is a command that should be replicated to both devices in paired QUAD mode. This is typically only used when reading/writing configuration registers in paired flash devices (do not set for memory transfers).

pub fn busy(&mut self) -> BUSY_W

Bit 2 - Command status: 1 indicates controller is busy (command in progress)

pub fn status(&mut self) -> STATUS_W

Bit 1 - Command status: 1 indicates command has completed. Cleared by writing 1 to this bit or starting a new transfer.

pub fn start(&mut self) -> START_W

Bit 0 - Write to 1 to initiate a PIO transaction on the bus (typically the entire register should be written at once with this bit set).

impl W<u32, Reg<u32, _CFG>>

pub fn writelatency(&mut self) -> WRITELATENCY_W

Bits 20:25 - Number of cycles between addressn and TX data. Qualified by ENLAT

pub fn cpol(&mut self) -> CPOL_W

Bit 17 - Serial clock polarity.

pub fn cpha(&mut self) -> CPHA_W

Bit 16 - Serial clock phase.

pub fn turnaround(&mut self) -> TURNAROUND_W

Bits 8:13 - Number of turnaround cycles (for TX->RX transitions). Qualified by ENTURN or XIPENTURN bit field.

pub fn sepio(&mut self) -> SEPIO_W

Bit 7 - Separate IO configuration. This bit should be set when the target device has separate MOSI and MISO pins. Respective IN/OUT bits below should be set to map pins.

pub fn isize(&mut self) -> ISIZE_W

Bit 6 - Instruction Size enum name = I8 value = 0x0 desc = Instruction is 1 byte enum name = I16 value = 0x1 desc = Instruction is 2 bytes

pub fn asize(&mut self) -> ASIZE_W

Bits 4:5 - Address Size. Address bytes to send from ADDR register

pub fn devcfg(&mut self) -> DEVCFG_W

Bits 0:3 - Flash configuration for XIP and AUTO DMA operations. Controls value for SER (Slave Enable) for XIP operations and address generation for DMA/XIP modes. Also used to configure SPIFRF (frame format).

impl W<u32, Reg<u32, _ADDR>>

pub fn addr(&mut self) -> ADDR_W

Bits 0:31 - Optional Address field to send (after optional instruction field) - qualified by ASIZE in CMD register. NOTE: This register is aliased to DMADEVADDR.

impl W<u32, Reg<u32, _INSTR>>

pub fn instr(&mut self) -> INSTR_W

Bits 0:15 - Optional Instruction field to send (1st byte) - qualified by ISEND/ISIZE

impl W<u32, Reg<u32, _TXFIFO>>

pub fn txfifo(&mut self) -> TXFIFO_W

Bits 0:31 - Data to be transmitted. Data should normally be aligned to the LSB (pad the upper bits with zeros) unless BIGENDIAN is set.

impl W<u32, Reg<u32, _RXFIFO>>

pub fn rxfifo(&mut self) -> RXFIFO_W

Bits 0:31 - Receive data. Data is aligned to the LSB (padded zeros on upper bits) unless BIGENDIAN is set.

impl W<u32, Reg<u32, _TXENTRIES>>

pub fn txentries(&mut self) -> TXENTRIES_W

Bits 0:5 - Number of 32-bit words/entries in TX FIFO

impl W<u32, Reg<u32, _RXENTRIES>>

pub fn rxentries(&mut self) -> RXENTRIES_W

Bits 0:5 - Number of 32-bit words/entries in RX FIFO

impl W<u32, Reg<u32, _THRESHOLD>>

pub fn rxthresh(&mut self) -> RXTHRESH_W

Bits 8:13 - Number of entries in TX FIFO that cause RXE interrupt

pub fn txthresh(&mut self) -> TXTHRESH_W

Bits 0:5 - Number of entries in TX FIFO that cause TXF interrupt

impl W<u32, Reg<u32, _MSPICFG>>

pub fn prstn(&mut self) -> PRSTN_W

Bit 31 - Peripheral reset. Master reset to the entire MSPI module (DMA, XIP, and transfer state machines). 1=normal operation, 0=in reset.

pub fn iprstn(&mut self) -> IPRSTN_W

Bit 30 - IP block reset. Write to 0 to put the transfer module in reset or 1 for normal operation. This may be required after error conditions to clear the transfer on the bus.

pub fn fiforeset(&mut self) -> FIFORESET_W

Bit 29 - Reset MSPI FIFO (active high). 1=reset FIFO, 0=normal operation. May be used to manually flush the FIFO in error handling.

pub fn clkdiv(&mut self) -> CLKDIV_W

Bits 8:13 - Clock Divider. Allows dividing 48 MHz base clock by integer multiples. Enumerations are provided for common frequency, but any integer divide from 48 MHz is allowed. Odd divide ratios will result in a 33/66 percent duty cycle with a long low clock pulse (to allow longer round-trip for read data).

pub fn iomsel(&mut self) -> IOMSEL_W

Bits 4:7 - Selects which IOM is selected for CQ handshake status.

pub fn txneg(&mut self) -> TXNEG_W

Bit 3 - Launches TX data a half clock cycle (~10 ns) early. This should normally be programmed to zero (NORMAL).

pub fn rxneg(&mut self) -> RXNEG_W

Bit 2 - Adjusts the RX capture phase to the negedge of the 48MHz internal clock (~10 ns early). For normal operation, it is expected that RXNEG will be set to 0.

pub fn rxcap(&mut self) -> RXCAP_W

Bit 1 - Controls RX data capture phase. A setting of 0 (NORMAL) captures read data at the normal capture point relative to the internal clock launch point. However, to accommodate chip/pad/board delays, a setting of RXCAP of 1 is expected to be used to align the capture point with the return data window. This bit is used in conjunction with RXNEG to provide 4 unique capture points, all about 10 ns apart.

pub fn apbclk(&mut self) -> APBCLK_W

Bit 0 - Enable continuous APB clock. For power-efficient operation, APBCLK should be set to 0.

impl W<u32, Reg<u32, _MSPIDDR>>

pub fn txdqsdelay(&mut self) -> TXDQSDELAY_W

Bits 16:20 - When OVERRIDEDQSDELAY is set this sets the DQS delay line value. In ENABLEDQS mode, this acts as an offset to the computed value (should be set to 0 by default)

pub fn rxdqsdelay(&mut self) -> RXDQSDELAY_W

Bits 8:12 - When OVERRIDEDQSDELAY is set this sets the DQS delay line value. In ENABLEDQS mode, this acts as an offset to the computed value (should be set to 0 by default)

pub fn enablefinedelay(&mut self) -> ENABLEFINEDELAY_W

Bit 6 - Enables use of delay line to provide fine control over traditional RX capture clock.

pub fn overrideddrclkoutdelay(&mut self) -> OVERRIDEDDRCLKOUTDELAY_W

Bit 5 - Override TX delay line with the value in DQSDELAY (for TX clock offset when in QUADDDR mode)

pub fn overriderxdqsdelay(&mut self) -> OVERRIDERXDQSDELAY_W

Bit 4 - Override DQS delay line with the value in DQSDELAY (for RX capture in QUADDDR mode)

pub fn dqssyncneg(&mut self) -> DQSSYNCNEG_W

Bit 3 - Use negative edge of clock for DDR data sync

pub fn enabledqs(&mut self) -> ENABLEDQS_W

Bit 2 - In EMULATEDDR mode, enable DQS for read capture

pub fn quadddr(&mut self) -> QUADDDR_W

Bit 1 - Enables use of delay line to provide fine control over traditional RX capture clock.

pub fn emulateddr(&mut self) -> EMULATEDDR_W

Bit 0 - Drive external clock at 1/2 rate to emulate DDR mode

impl W<u32, Reg<u32, _PADCFG>>

pub fn revcs(&mut self) -> REVCS_W

Bit 21 - Reverse CS connections. Allows CS1 to be associated with lower data lanes and CS0 to be associated with upper data lines

pub fn in3(&mut self) -> IN3_W

Bit 20 - Data Input pad 3 pin muxing: 0=pad[3] 1=pad[7]

pub fn in2(&mut self) -> IN2_W

Bit 19 - Data Input pad 2 pin muxing: 0=pad[2] 1=pad[6]

pub fn in1(&mut self) -> IN1_W

Bit 18 - Data Input pad 1 pin muxing: 0=pad[1] 1=pad[5]

pub fn in0(&mut self) -> IN0_W

Bits 16:17 - Data Input pad 0 pin muxing: 0=pad[0] 1=pad[4] 2=pad[1] 3=pad[5]

pub fn out7(&mut self) -> OUT7_W

Bit 4 - Output pad 7 configuration. 0=data[7] 1=data[3]

pub fn out6(&mut self) -> OUT6_W

Bit 3 - Output pad 6 configuration. 0=data[6] 1=data[2]

pub fn out5(&mut self) -> OUT5_W

Bit 2 - Output pad 5 configuration. 0=data[5] 1=data[1]

pub fn out4(&mut self) -> OUT4_W

Bit 1 - Output pad 4 configuration. 0=data[4] 1=data[0]

pub fn out3(&mut self) -> OUT3_W

Bit 0 - Output pad 3 configuration. 0=data[3] 1=CLK

impl W<u32, Reg<u32, _PADOUTEN>>

pub fn outen(&mut self) -> OUTEN_W

Bits 0:9 - Output pad enable configuration. Indicates which pads should be driven. Bits [3:0] are Quad0 data, [7:4] are Quad1 data, and [8] is clock.

impl W<u32, Reg<u32, _PADOVEREN>>

pub fn overrideen(&mut self) -> OVERRIDEEN_W

Bits 0:9 - Output pad override enable. Bit mask for pad outputs. When set to 1, the values in the OVERRIDE field are driven on the pad (output enable is implicitly set in this mode). [7:0]=data [8]=clock [9]=DM

impl W<u32, Reg<u32, _PADOVER>>

pub fn override_(&mut self) -> OVERRIDE_W

Bits 0:9 - Output pad override value. [7:0]=data [8]=clock [9]=DM

impl W<u32, Reg<u32, _FLASH>>

pub fn xipenwlat(&mut self) -> XIPENWLAT_W

Bit 11 - Enable Write Latency counter for XIP write transactions

pub fn xipmixed(&mut self) -> XIPMIXED_W

Bits 8:10 - Reserved. Set to 0x0

pub fn xipsendi(&mut self) -> XIPSENDI_W

Bit 7 - Indicates whether XIP/AUTO DMA operations should send an instruction (see READINSTR field and ISIZE field in CFG)

pub fn xipsenda(&mut self) -> XIPSENDA_W

Bit 6 - Indicates whether XIP/AUTO DMA operations should send an an address phase (see DMADEVADDR register and ASIZE field in CFG)

pub fn xipenturn(&mut self) -> XIPENTURN_W

Bit 5 - Indicates whether XIP/AUTO DMA operations should enable TX->RX turnaround cycles

pub fn xipbigendian(&mut self) -> XIPBIGENDIAN_W

Bit 4 - Indicates whether XIP/AUTO DMA data transfers are in big or little endian format

pub fn xipack(&mut self) -> XIPACK_W

Bits 2:3 - Controls transmission of Micron XIP acknowledge cycles (Micron Flash devices only)

pub fn xipendcx(&mut self) -> XIPENDCX_W

Bit 1 - Enable DCX signal on data [1] for XIP/DMA operations

pub fn xipen(&mut self) -> XIPEN_W

Bit 0 - Enable the XIP (eXecute In Place) function which effectively enables the address decoding of the MSPI device in the flash/cache address space at address 0x04000000-0x07FFFFFF.

impl W<u32, Reg<u32, _XIPINSTR>>

pub fn readinstr(&mut self) -> READINSTR_W

Bits 16:31 - Read command sent to flash for DMA/XIP operations

pub fn writeinstr(&mut self) -> WRITEINSTR_W

Bits 0:15 - Write command sent for DMA operations

impl W<u32, Reg<u32, _SCRAMBLING>>

pub fn screnable(&mut self) -> SCRENABLE_W

Bit 31 - Enables Data Scrambling Region. When 1 reads and writes to the range will be scrambled. When 0, data will be read/written unmodified. Address range is specified in 64K granularity and the START/END ranges are included within the range.

pub fn scrend(&mut self) -> SCREND_W

Bits 16:25 - Scrambling region end address [25:16] (64K block granularity). The END block is the LAST block included in the scrambled address range.

pub fn scrstart(&mut self) -> SCRSTART_W

Bits 0:9 - Scrambling region start address [25:16] (64K block granularity). The START block is the FIRST block included in the scrambled address range.

impl W<u32, Reg<u32, _INTEN>>

pub fn screrr(&mut self) -> SCRERR_W

Bit 12 - Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address.

pub fn cqerr(&mut self) -> CQERR_W

Bit 11 - Command Queue Error Interrupt

pub fn cqpaused(&mut self) -> CQPAUSED_W

Bit 10 - Command Queue is Paused.

pub fn cqupd(&mut self) -> CQUPD_W

Bit 9 - Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts.

pub fn cqcmp(&mut self) -> CQCMP_W

Bit 8 - Command Queue Complete Interrupt

pub fn derr(&mut self) -> DERR_W

Bit 7 - DMA Error Interrupt

pub fn dcmp(&mut self) -> DCMP_W

Bit 6 - DMA Complete Interrupt

pub fn rxf(&mut self) -> RXF_W

Bit 5 - Receive FIFO full

pub fn rxo(&mut self) -> RXO_W

Bit 4 - Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)

pub fn rxu(&mut self) -> RXU_W

Bit 3 - Receive FIFO underflow (only occurs when SW reads from an empty FIFO)

pub fn txo(&mut self) -> TXO_W

Bit 2 - Transmit FIFO Overflow (only occurs when SW writes to a full FIFO).

pub fn txe(&mut self) -> TXE_W

Bit 1 - Transmit FIFO empty.

pub fn cmdcmp(&mut self) -> CMDCMP_W

Bit 0 - Transfer complete. Note that DMA and CQ operations are layered, so CMDCMP, DCMP, and CQ* can all be signaled simultaneously.

impl W<u32, Reg<u32, _INTSTAT>>

pub fn screrr(&mut self) -> SCRERR_W

Bit 12 - Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address.

pub fn cqerr(&mut self) -> CQERR_W

Bit 11 - Command Queue Error Interrupt

pub fn cqpaused(&mut self) -> CQPAUSED_W

Bit 10 - Command Queue is Paused.

pub fn cqupd(&mut self) -> CQUPD_W

Bit 9 - Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts.

pub fn cqcmp(&mut self) -> CQCMP_W

Bit 8 - Command Queue Complete Interrupt

pub fn derr(&mut self) -> DERR_W

Bit 7 - DMA Error Interrupt

pub fn dcmp(&mut self) -> DCMP_W

Bit 6 - DMA Complete Interrupt

pub fn rxf(&mut self) -> RXF_W

Bit 5 - Receive FIFO full

pub fn rxo(&mut self) -> RXO_W

Bit 4 - Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)

pub fn rxu(&mut self) -> RXU_W

Bit 3 - Receive FIFO underflow (only occurs when SW reads from an empty FIFO)

pub fn txo(&mut self) -> TXO_W

Bit 2 - Transmit FIFO Overflow (only occurs when SW writes to a full FIFO).

pub fn txe(&mut self) -> TXE_W

Bit 1 - Transmit FIFO empty.

pub fn cmdcmp(&mut self) -> CMDCMP_W

Bit 0 - Transfer complete. Note that DMA and CQ operations are layered, so CMDCMP, DCMP, and CQ* can all be signaled simultaneously.

impl W<u32, Reg<u32, _INTCLR>>

pub fn screrr(&mut self) -> SCRERR_W

Bit 12 - Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address.

pub fn cqerr(&mut self) -> CQERR_W

Bit 11 - Command Queue Error Interrupt

pub fn cqpaused(&mut self) -> CQPAUSED_W

Bit 10 - Command Queue is Paused.

pub fn cqupd(&mut self) -> CQUPD_W

Bit 9 - Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts.

pub fn cqcmp(&mut self) -> CQCMP_W

Bit 8 - Command Queue Complete Interrupt

pub fn derr(&mut self) -> DERR_W

Bit 7 - DMA Error Interrupt

pub fn dcmp(&mut self) -> DCMP_W

Bit 6 - DMA Complete Interrupt

pub fn rxf(&mut self) -> RXF_W

Bit 5 - Receive FIFO full

pub fn rxo(&mut self) -> RXO_W

Bit 4 - Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)

pub fn rxu(&mut self) -> RXU_W

Bit 3 - Receive FIFO underflow (only occurs when SW reads from an empty FIFO)

pub fn txo(&mut self) -> TXO_W

Bit 2 - Transmit FIFO Overflow (only occurs when SW writes to a full FIFO).

pub fn txe(&mut self) -> TXE_W

Bit 1 - Transmit FIFO empty.

pub fn cmdcmp(&mut self) -> CMDCMP_W

Bit 0 - Transfer complete. Note that DMA and CQ operations are layered, so CMDCMP, DCMP, and CQ* can all be signaled simultaneously.

impl W<u32, Reg<u32, _INTSET>>

pub fn screrr(&mut self) -> SCRERR_W

Bit 12 - Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address.

pub fn cqerr(&mut self) -> CQERR_W

Bit 11 - Command Queue Error Interrupt

pub fn cqpaused(&mut self) -> CQPAUSED_W

Bit 10 - Command Queue is Paused.

pub fn cqupd(&mut self) -> CQUPD_W

Bit 9 - Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts.

pub fn cqcmp(&mut self) -> CQCMP_W

Bit 8 - Command Queue Complete Interrupt

pub fn derr(&mut self) -> DERR_W

Bit 7 - DMA Error Interrupt

pub fn dcmp(&mut self) -> DCMP_W

Bit 6 - DMA Complete Interrupt

pub fn rxf(&mut self) -> RXF_W

Bit 5 - Receive FIFO full

pub fn rxo(&mut self) -> RXO_W

Bit 4 - Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)

pub fn rxu(&mut self) -> RXU_W

Bit 3 - Receive FIFO underflow (only occurs when SW reads from an empty FIFO)

pub fn txo(&mut self) -> TXO_W

Bit 2 - Transmit FIFO Overflow (only occurs when SW writes to a full FIFO).

pub fn txe(&mut self) -> TXE_W

Bit 1 - Transmit FIFO empty.

pub fn cmdcmp(&mut self) -> CMDCMP_W

Bit 0 - Transfer complete. Note that DMA and CQ operations are layered, so CMDCMP, DCMP, and CQ* can all be signaled simultaneously.

impl W<u32, Reg<u32, _DMACFG>>

pub fn dmapwroff(&mut self) -> DMAPWROFF_W

Bit 18 - Power off MSPI domain upon completion of DMA operation.

pub fn dmapri(&mut self) -> DMAPRI_W

Bits 3:4 - Sets the Priority of the DMA request

pub fn dmadir(&mut self) -> DMADIR_W

Bit 2 - Direction

pub fn dmaen(&mut self) -> DMAEN_W

Bits 0:1 - DMA Enable. Setting this bit to EN will start the DMA operation

impl W<u32, Reg<u32, _DMASTAT>>

pub fn screrr(&mut self) -> SCRERR_W

Bit 3 - Scrambling Access Alignment Error. This active high bit signals that a scrambling operation was specified for a non-word aligned DEVADDR.

pub fn dmaerr(&mut self) -> DMAERR_W

Bit 2 - DMA Error. This active high bit signals that an error was encountered during the DMA operation.

pub fn dmacpl(&mut self) -> DMACPL_W

Bit 1 - DMA Transfer Complete. This signals the end of the DMA operation.

pub fn dmatip(&mut self) -> DMATIP_W

Bit 0 - DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data, transferring data, or waiting for priority. All of these will be indicated with a 1. A 0 will indicate that the DMA is fully complete and no further transactions will be done.

impl W<u32, Reg<u32, _DMATARGADDR>>

pub fn targaddr(&mut self) -> TARGADDR_W

Bits 0:31 - Target byte address for source of DMA (either read or write). In cases of non-word aligned addresses, the DMA logic will take care for ensuring only the target bytes are read/written.

impl W<u32, Reg<u32, _DMADEVADDR>>

pub fn devaddr(&mut self) -> DEVADDR_W

Bits 0:31 - SPI Device address for automated DMA transactions (both read and write).

impl W<u32, Reg<u32, _DMATOTCOUNT>>

pub fn totcount(&mut self) -> TOTCOUNT_W

Bits 0:23 - Total Transfer Count in bytes.

impl W<u32, Reg<u32, _DMABCOUNT>>

pub fn bcount(&mut self) -> BCOUNT_W

Bits 0:7 - Burst transfer size in bytes. This is the number of bytes transferred when a FIFO trigger event occurs. Recommended value is 32.

impl W<u32, Reg<u32, _DMATHRESH>>

pub fn dmarxthresh(&mut self) -> DMARXTHRESH_W

Bits 8:12 - DMA transfer FIFO level trigger. For read operations, DMA is triggered when the FIFO level is greater than this value. For write operations, DMA is triggered when the FIFO level is less than this level. Each DMA operation will consist of BCOUNT bytes.

pub fn dmatxthresh(&mut self) -> DMATXTHRESH_W

Bits 0:4 - DMA transfer FIFO level trigger. For read operations, DMA is triggered when the FIFO level is greater than this value. For write operations, DMA is triggered when the FIFO level is less than this level. Each DMA operation will consist of BCOUNT bytes.

impl W<u32, Reg<u32, _DMABOUNDARY>>

pub fn dmabound(&mut self) -> DMABOUND_W

Bits 12:15 - DMA Address boundary

pub fn dmatimelimit(&mut self) -> DMATIMELIMIT_W

Bits 0:11 - DMA time limit. Can be used to limit the transaction time on the MSPI bus. The count is in 100 ns increments. A value of 0 disables the counter.

impl W<u32, Reg<u32, _CQCFG>>

pub fn cqautoclearmask(&mut self) -> CQAUTOCLEARMASK_W

Bit 3 - Enable clear of CQMASK after each pause operation. This may be useful when using software flags to pause CQ.

pub fn cqpwroff(&mut self) -> CQPWROFF_W

Bit 2 - Power off MSPI domain upon completion of DMA operation.

pub fn cqpri(&mut self) -> CQPRI_W

Bit 1 - Sets the Priority of the command queue DMA request

pub fn cqen(&mut self) -> CQEN_W

Bit 0 - Command queue enable. When set, will enable the processing of the command queue

impl W<u32, Reg<u32, _CQADDR>>

pub fn cqaddr(&mut self) -> CQADDR_W

Bits 0:28 - Address of command queue buffer in SRAM or flash. The buffer address must be aligned to a word boundary.

impl W<u32, Reg<u32, _CQSTAT>>

pub fn cqpaused(&mut self) -> CQPAUSED_W

Bit 3 - Command queue is currently paused status.

pub fn cqerr(&mut self) -> CQERR_W

Bit 2 - Command queue processing Error. This active high bit signals that an error was encountered during the CQ operation.

pub fn cqcpl(&mut self) -> CQCPL_W

Bit 1 - Command queue operation Complete. This signals the end of the command queue operation.

pub fn cqtip(&mut self) -> CQTIP_W

Bit 0 - Command queue Transfer In Progress indicator. 1 will indicate that a CQ transfer is active and this will remain active even when paused waiting for external event.

impl W<u32, Reg<u32, _CQFLAGS>>

pub fn cqflags(&mut self) -> CQFLAGS_W

Bits 0:15 - Current flag status (read-only). Bits [7:0] are software controllable and bits [15:8] are hardware status.

impl W<u32, Reg<u32, _CQSETCLEAR>>

pub fn cqfclr(&mut self) -> CQFCLR_W

Bits 16:23 - Clear CQFlag status bits.

pub fn cqftoggle(&mut self) -> CQFTOGGLE_W

Bits 8:15 - Toggle CQFlag status bits

pub fn cqfset(&mut self) -> CQFSET_W

Bits 0:7 - Set CQFlag status bits. Set has priority over clear if both are high.

impl W<u32, Reg<u32, _CQPAUSE>>

pub fn cqmask(&mut self) -> CQMASK_W

Bits 0:15 - CQ will pause processing when ALL specified events are satisfied -- i.e. when (CQMASK and CQPAUSE)==CQMASK.

impl W<u32, Reg<u32, _CQCURIDX>>

pub fn cqcuridx(&mut self) -> CQCURIDX_W

Bits 0:7 - Can be used to indicate the current position of the command queue by having CQ operations write this field. A CQ hardware status flag indicates when CURIDX and ENDIDX are not equal, allowing SW to pause the CQ processing until the end index is updated.

impl W<u32, Reg<u32, _CQENDIDX>>

pub fn cqendidx(&mut self) -> CQENDIDX_W

Bits 0:7 - Can be used to indicate the end position of the command queue. A CQ hardware status bit indices when CURIDX != ENDIDX so that the CQ can be paused when it reaches the end pointer.

impl W<u32, Reg<u32, _PCFG>>

pub fn lrswap(&mut self) -> LRSWAP_W

Bit 31 - Left/right channel swap.

pub fn pgaright(&mut self) -> PGARIGHT_W

Bits 26:30 - Right channel PGA gain.

pub fn pgaleft(&mut self) -> PGALEFT_W

Bits 21:25 - Left channel PGA gain.

pub fn mclkdiv(&mut self) -> MCLKDIV_W

Bits 17:18 - PDM_CLK frequency divisor.

pub fn sincrate(&mut self) -> SINCRATE_W

Bits 10:16 - SINC decimation rate.

pub fn adchpd(&mut self) -> ADCHPD_W

Bit 9 - High pass filter control.

pub fn hpcutoff(&mut self) -> HPCUTOFF_W

Bits 5:8 - High pass filter coefficients.

pub fn cycles(&mut self) -> CYCLES_W

Bits 2:4 - Number of clocks during gain-setting changes.

pub fn softmute(&mut self) -> SOFTMUTE_W

Bit 1 - Soft mute control.

pub fn pdmcoreen(&mut self) -> PDMCOREEN_W

Bit 0 - Data Streaming Control.

impl W<u32, Reg<u32, _VCFG>>

pub fn ioclken(&mut self) -> IOCLKEN_W

Bit 31 - Enable the IO clock.

pub fn rstb(&mut self) -> RSTB_W

Bit 30 - Reset the IP core.

pub fn pdmclksel(&mut self) -> PDMCLKSEL_W

Bits 27:29 - Select the PDM input clock.

pub fn pdmclken(&mut self) -> PDMCLKEN_W

Bit 26 - Enable the serial clock.

pub fn i2sen(&mut self) -> I2SEN_W

Bit 20 - I2S interface enable.

pub fn bclkinv(&mut self) -> BCLKINV_W

Bit 19 - I2S BCLK input inversion.

pub fn dmickdel(&mut self) -> DMICKDEL_W

Bit 17 - PDM clock sampling delay.

pub fn selap(&mut self) -> SELAP_W

Bit 16 - Select PDM input clock source.

pub fn pcmpack(&mut self) -> PCMPACK_W

Bit 8 - PCM data packing enable.

pub fn chset(&mut self) -> CHSET_W

Bits 3:4 - Set PCM channels.

impl W<u32, Reg<u32, _VOICESTAT>>

pub fn fifocnt(&mut self) -> FIFOCNT_W

Bits 0:5 - Valid 32-bit entries currently in the FIFO.

impl W<u32, Reg<u32, _FIFOREAD>>

pub fn fiforead(&mut self) -> FIFOREAD_W

Bits 0:31 - FIFO read data.

impl W<u32, Reg<u32, _FIFOFLUSH>>

pub fn fifoflush(&mut self) -> FIFOFLUSH_W

Bit 0 - FIFO FLUSH.

impl W<u32, Reg<u32, _FIFOTHR>>

pub fn fifothr(&mut self) -> FIFOTHR_W

Bits 0:4 - FIFO Threshold value. When the FIFO count is equal to, or larger than this value (in words), a THR interrupt is generated (if enabled)

impl W<u32, Reg<u32, _INTEN>>

pub fn derr(&mut self) -> DERR_W

Bit 4 - DMA Error received

pub fn dcmp(&mut self) -> DCMP_W

Bit 3 - DMA completed a transfer

pub fn undfl(&mut self) -> UNDFL_W

Bit 2 - This is the FIFO underflow interrupt.

pub fn ovf(&mut self) -> OVF_W

Bit 1 - This is the FIFO overflow interrupt.

pub fn thr(&mut self) -> THR_W

Bit 0 - This is the FIFO threshold interrupt.

impl W<u32, Reg<u32, _INTSTAT>>

pub fn derr(&mut self) -> DERR_W

Bit 4 - DMA Error received

pub fn dcmp(&mut self) -> DCMP_W

Bit 3 - DMA completed a transfer

pub fn undfl(&mut self) -> UNDFL_W

Bit 2 - This is the FIFO underflow interrupt.

pub fn ovf(&mut self) -> OVF_W

Bit 1 - This is the FIFO overflow interrupt.

pub fn thr(&mut self) -> THR_W

Bit 0 - This is the FIFO threshold interrupt.

impl W<u32, Reg<u32, _INTCLR>>

pub fn derr(&mut self) -> DERR_W

Bit 4 - DMA Error received

pub fn dcmp(&mut self) -> DCMP_W

Bit 3 - DMA completed a transfer

pub fn undfl(&mut self) -> UNDFL_W

Bit 2 - This is the FIFO underflow interrupt.

pub fn ovf(&mut self) -> OVF_W

Bit 1 - This is the FIFO overflow interrupt.

pub fn thr(&mut self) -> THR_W

Bit 0 - This is the FIFO threshold interrupt.

impl W<u32, Reg<u32, _INTSET>>

pub fn derr(&mut self) -> DERR_W

Bit 4 - DMA Error received

pub fn dcmp(&mut self) -> DCMP_W

Bit 3 - DMA completed a transfer

pub fn undfl(&mut self) -> UNDFL_W

Bit 2 - This is the FIFO underflow interrupt.

pub fn ovf(&mut self) -> OVF_W

Bit 1 - This is the FIFO overflow interrupt.

pub fn thr(&mut self) -> THR_W

Bit 0 - This is the FIFO threshold interrupt.

impl W<u32, Reg<u32, _DMATRIGEN>>

pub fn dthr90(&mut self) -> DTHR90_W

Bit 1 - Trigger DMA at FIFO 90 percent full. This signal is also used internally for AUTOHIP function

pub fn dthr(&mut self) -> DTHR_W

Bit 0 - Trigger DMA upon when FIFO is filled to level indicated by the FIFO THRESHOLD,at granularity of 16 bytes only

impl W<u32, Reg<u32, _DMATRIGSTAT>>

pub fn dthr90stat(&mut self) -> DTHR90STAT_W

Bit 1 - Triggered DMA from FIFO reaching 90 percent full

pub fn dthrstat(&mut self) -> DTHRSTAT_W

Bit 0 - Triggered DMA from FIFO reaching threshold

impl W<u32, Reg<u32, _DMACFG>>

pub fn dpwroff(&mut self) -> DPWROFF_W

Bit 10 - Power Off the ADC System upon DMACPL.

pub fn dautohip(&mut self) -> DAUTOHIP_W

Bit 9 - Raise priority to high on FIFO full, and DMAPRI set to low

pub fn dmapri(&mut self) -> DMAPRI_W

Bit 8 - Sets the Priority of the DMA request

pub fn dmadir(&mut self) -> DMADIR_W

Bit 2 - Direction

pub fn dmaen(&mut self) -> DMAEN_W

Bit 0 - DMA Enable

impl W<u32, Reg<u32, _DMATOTCOUNT>>

pub fn totcount(&mut self) -> TOTCOUNT_W

Bits 0:19 - Total Transfer Count. The transfer count must be a multiple of the THR setting to avoid DMA overruns.

impl W<u32, Reg<u32, _DMATARGADDR>>

pub fn utargaddr(&mut self) -> UTARGADDR_W

Bits 21:31 - SRAM Target

pub fn ltargaddr(&mut self) -> LTARGADDR_W

Bits 0:20 - DMA Target Address. This register is not updated with the current address of the DMA, but will remain static with the original address during the DMA transfer.

impl W<u32, Reg<u32, _DMASTAT>>

pub fn dmaerr(&mut self) -> DMAERR_W

Bit 2 - DMA Error

pub fn dmacpl(&mut self) -> DMACPL_W

Bit 1 - DMA Transfer Complete

pub fn dmatip(&mut self) -> DMATIP_W

Bit 0 - DMA Transfer In Progress

impl W<u32, Reg<u32, _SUPPLYSRC>>

pub fn blebucken(&mut self) -> BLEBUCKEN_W

Bit 0 - Enables and Selects the BLE Buck as the supply for the BLE power domain or for Burst LDO. It takes the initial value from Customer INFO space. Buck will be powered up only if there is an active request for BLEH domain or Burst mode and appropriate feature is allowed.

impl W<u32, Reg<u32, _SUPPLYSTATUS>>

pub fn blebuckon(&mut self) -> BLEBUCKON_W

Bit 1 - Indicates whether the BLE (if supported) domain and burst (if supported) domain is supplied from the LDO or the Buck. Buck will be powered up only if there is an active request for BLEH domain or Burst mode and appropriate feature is allowed.

pub fn simobuckon(&mut self) -> SIMOBUCKON_W

Bit 0 - Indicates whether the Core/Mem low-voltage domains are supplied from the LDO or the Buck.

impl W<u32, Reg<u32, _DEVPWREN>>

pub fn pwrblel(&mut self) -> PWRBLEL_W

Bit 15 - Power up BLE controller

pub fn pwrpdm(&mut self) -> PWRPDM_W

Bit 14 - Power up PDM block

pub fn pwrmspi2(&mut self) -> PWRMSPI2_W

Bit 13 - Power up MSPI2 Controller

pub fn pwrmspi1(&mut self) -> PWRMSPI1_W

Bit 12 - Power up MSPI1 Controller

pub fn pwrmspi0(&mut self) -> PWRMSPI0_W

Bit 11 - Power up MSPI0 Controller

pub fn pwrscard(&mut self) -> PWRSCARD_W

Bit 10 - Power up SCARD Controller

pub fn pwradc(&mut self) -> PWRADC_W

Bit 9 - Power up ADC Digital Controller

pub fn pwruart1(&mut self) -> PWRUART1_W

Bit 8 - Power up UART Controller 1

pub fn pwruart0(&mut self) -> PWRUART0_W

Bit 7 - Power up UART Controller 0

pub fn pwriom5(&mut self) -> PWRIOM5_W

Bit 6 - Power up IO Master 5

pub fn pwriom4(&mut self) -> PWRIOM4_W

Bit 5 - Power up IO Master 4

pub fn pwriom3(&mut self) -> PWRIOM3_W

Bit 4 - Power up IO Master 3

pub fn pwriom2(&mut self) -> PWRIOM2_W

Bit 3 - Power up IO Master 2

pub fn pwriom1(&mut self) -> PWRIOM1_W

Bit 2 - Power up IO Master 1

pub fn pwriom0(&mut self) -> PWRIOM0_W

Bit 1 - Power up IO Master 0

pub fn pwrios(&mut self) -> PWRIOS_W

Bit 0 - Power up IO Slave

impl W<u32, Reg<u32, _MEMPWDINSLEEP>>

pub fn cachepwdslp(&mut self) -> CACHEPWDSLP_W

Bit 31 - power down cache in deep sleep

pub fn flash1pwdslp(&mut self) -> FLASH1PWDSLP_W

Bit 14 - Power-down FLASH1 in deep sleep

pub fn flash0pwdslp(&mut self) -> FLASH0PWDSLP_W

Bit 13 - Power-down FLASH0 in deep sleep

pub fn srampwdslp(&mut self) -> SRAMPWDSLP_W

Bits 3:12 - Selects which SRAM banks are powered down in deep sleep mode, causing the contents of the bank to be lost.

pub fn dtcmpwdslp(&mut self) -> DTCMPWDSLP_W

Bits 0:2 - power down DTCM in deep sleep

impl W<u32, Reg<u32, _MEMPWREN>>

pub fn cacheb2(&mut self) -> CACHEB2_W

Bit 31 - Power up Cache Bank 2. This works in conjunction with Cache enable from flash_cache module. To power up cache bank 2, cache has to be enabled and this bit has to be set.

pub fn cacheb0(&mut self) -> CACHEB0_W

Bit 30 - Power up Cache Bank 0. This works in conjunction with Cache enable from flash_cache module. To power up cache bank 0, cache has to be enabled and this bit has to be set.

pub fn flash1(&mut self) -> FLASH1_W

Bit 14 - Power up FLASH group 1 (1MB-2MB)

pub fn flash0(&mut self) -> FLASH0_W

Bit 13 - Power up FLASH group 0 (0MB-1MB)

pub fn sram(&mut self) -> SRAM_W

Bits 3:12 - Power up SRAM groups

pub fn dtcm(&mut self) -> DTCM_W

Bits 0:2 - Power up DTCM

impl W<u32, Reg<u32, _MEMPWRSTATUS>>

pub fn cacheb2(&mut self) -> CACHEB2_W

Bit 16 - This bit is 1 if power is supplied to Cache Bank 2

pub fn cacheb0(&mut self) -> CACHEB0_W

Bit 15 - This bit is 1 if power is supplied to Cache Bank 0

pub fn flash1(&mut self) -> FLASH1_W

Bit 14 - This bit is 1 if power is supplied to FLASH group 1

pub fn flash0(&mut self) -> FLASH0_W

Bit 13 - This bit is 1 if power is supplied to FLASH group 0

pub fn sram9(&mut self) -> SRAM9_W

Bit 12 - This bit is 1 if power is supplied to SRAM GROUP9

pub fn sram8(&mut self) -> SRAM8_W

Bit 11 - This bit is 1 if power is supplied to SRAM GROUP8

pub fn sram7(&mut self) -> SRAM7_W

Bit 10 - This bit is 1 if power is supplied to SRAM GROUP7

pub fn sram6(&mut self) -> SRAM6_W

Bit 9 - This bit is 1 if power is supplied to SRAM GROUP6

pub fn sram5(&mut self) -> SRAM5_W

Bit 8 - This bit is 1 if power is supplied to SRAM GROUP5

pub fn sram4(&mut self) -> SRAM4_W

Bit 7 - This bit is 1 if power is supplied to SRAM GROUP4

pub fn sram3(&mut self) -> SRAM3_W

Bit 6 - This bit is 1 if power is supplied to SRAM GROUP3

pub fn sram2(&mut self) -> SRAM2_W

Bit 5 - This bit is 1 if power is supplied to SRAM GROUP2

pub fn sram1(&mut self) -> SRAM1_W

Bit 4 - This bit is 1 if power is supplied to SRAM GROUP1

pub fn sram0(&mut self) -> SRAM0_W

Bit 3 - This bit is 1 if power is supplied to SRAM GROUP0

pub fn dtcm1(&mut self) -> DTCM1_W

Bit 2 - This bit is 1 if power is supplied to DTCM GROUP1

pub fn dtcm01(&mut self) -> DTCM01_W

Bit 1 - This bit is 1 if power is supplied to DTCM GROUP0_1

pub fn dtcm00(&mut self) -> DTCM00_W

Bit 0 - This bit is 1 if power is supplied to DTCM GROUP0_0

impl W<u32, Reg<u32, _DEVPWRSTATUS>>

pub fn bleh(&mut self) -> BLEH_W

Bit 9 - This bit is 1 if power is supplied to BLEH

pub fn blel(&mut self) -> BLEL_W

Bit 8 - This bit is 1 if power is supplied to BLEL

pub fn pwrpdm(&mut self) -> PWRPDM_W

Bit 7 - This bit is 1 if power is supplied to PDM

pub fn pwrmspi(&mut self) -> PWRMSPI_W

Bit 6 - This bit is 1 if power is supplied to MSPI

pub fn pwradc(&mut self) -> PWRADC_W

Bit 5 - This bit is 1 if power is supplied to ADC

pub fn hcpc(&mut self) -> HCPC_W

Bit 4 - This bit is 1 if power is supplied to HCPC domain (IO MASTER4, 5, 6)

pub fn hcpb(&mut self) -> HCPB_W

Bit 3 - This bit is 1 if power is supplied to HCPB domain (IO MASTER 0, 1, 2)

pub fn hcpa(&mut self) -> HCPA_W

Bit 2 - This bit is 1 if power is supplied to HCPA domain (IO SLAVE, UART0, UART1, SCARD)

pub fn mcuh(&mut self) -> MCUH_W

Bit 1 - This bit is 1 if power is supplied to MCUH

pub fn mcul(&mut self) -> MCUL_W

Bit 0 - This bit is 1 if power is supplied to MCUL

impl W<u32, Reg<u32, _SRAMCTRL>>

pub fn sramlightsleep(&mut self) -> SRAMLIGHTSLEEP_W

Bits 8:19 - Light Sleep enable for each TCM/SRAM bank. When 1, corresponding bank will be put into light sleep. For optimal power, banks should be put into light sleep while the system is active but the bank has minimal or no accesses.

pub fn srammasterclkgate(&mut self) -> SRAMMASTERCLKGATE_W

Bit 2 - This bit is 1 when the master clock gate is enabled (top-level clock gate for entire SRAM block)

pub fn sramclkgate(&mut self) -> SRAMCLKGATE_W

Bit 1 - This bit is 1 if clock gating is allowed for individual system SRAMs

impl W<u32, Reg<u32, _ADCSTATUS>>

pub fn refbufpwd(&mut self) -> REFBUFPWD_W

Bit 5 - This bit indicates that the ADC REFBUF is powered down

pub fn refkeeppwd(&mut self) -> REFKEEPPWD_W

Bit 4 - This bit indicates that the ADC REFKEEP is powered down

pub fn vbatpwd(&mut self) -> VBATPWD_W

Bit 3 - This bit indicates that the ADC VBAT resistor divider is powered down

pub fn vptatpwd(&mut self) -> VPTATPWD_W

Bit 2 - This bit indicates that the ADC temperature sensor input buffer is powered down

pub fn bgtpwd(&mut self) -> BGTPWD_W

Bit 1 - This bit indicates that the ADC Band Gap is powered down

pub fn adcpwd(&mut self) -> ADCPWD_W

Bit 0 - This bit indicates that the ADC is powered down

impl W<u32, Reg<u32, _MISC>>

pub fn memvrlpble(&mut self) -> MEMVRLPBLE_W

Bit 6 - Control Bit to let Mem VR go to lp mode in deep sleep even when BLEL or BLEH is powered on given none of the other domains require it.

pub fn forcememvrlptimers(&mut self) -> FORCEMEMVRLPTIMERS_W

Bit 3 - Control Bit to force Mem VR to LP mode in deep sleep even when hfrc based ctimer or stimer is running.

impl W<u32, Reg<u32, _DEVPWREVENTEN>>

pub fn bursteven(&mut self) -> BURSTEVEN_W

Bit 31 - Control BURST status event

pub fn burstfeatureeven(&mut self) -> BURSTFEATUREEVEN_W

Bit 30 - Control BURSTFEATURE status event

pub fn blefeatureeven(&mut self) -> BLEFEATUREEVEN_W

Bit 29 - Control BLEFEATURE status event

pub fn bleleven(&mut self) -> BLELEVEN_W

Bit 8 - Control BLE power-on status event

pub fn pdmeven(&mut self) -> PDMEVEN_W

Bit 7 - Control PDM power-on status event

pub fn mspieven(&mut self) -> MSPIEVEN_W

Bit 6 - Control MSPI power-on status event

pub fn adceven(&mut self) -> ADCEVEN_W

Bit 5 - Control ADC power-on status event

pub fn hcpceven(&mut self) -> HCPCEVEN_W

Bit 4 - Control HCPC power-on status event

pub fn hcpbeven(&mut self) -> HCPBEVEN_W

Bit 3 - Control HCPB power-on status event

pub fn hcpaeven(&mut self) -> HCPAEVEN_W

Bit 2 - Control HCPA power-on status event

pub fn mcuheven(&mut self) -> MCUHEVEN_W

Bit 1 - Control MCUH power-on status event

pub fn mculeven(&mut self) -> MCULEVEN_W

Bit 0 - Control MCUL power-on status event

impl W<u32, Reg<u32, _MEMPWREVENTEN>>

pub fn cacheb2en(&mut self) -> CACHEB2EN_W

Bit 31 - Control CACHEB2 power-on status event

pub fn cacheb0en(&mut self) -> CACHEB0EN_W

Bit 30 - Control CACHE BANK 0 power-on status event

pub fn flash1en(&mut self) -> FLASH1EN_W

Bit 14 - Control FLASH power-on status event

pub fn flash0en(&mut self) -> FLASH0EN_W

Bit 13 - Control FLASH power-on status event

pub fn sramen(&mut self) -> SRAMEN_W

Bits 3:12 - Control SRAM power-on status event

pub fn dtcmen(&mut self) -> DTCMEN_W

Bits 0:2 - Enable DTCM power-on status event

impl W<u32, Reg<u32, _CFG>>

pub fn wdren(&mut self) -> WDREN_W

Bit 1 - Watchdog Timer Reset Enable. NOTE: The WDT module must also be configured for WDT reset. This includes enabling the RESEN bit in WDTCFG register in Watch dog timer block.

pub fn bodhren(&mut self) -> BODHREN_W

Bit 0 - Brown out high (2.1 V) reset enable.

impl W<u32, Reg<u32, _SWPOI>>

pub fn swpoikey(&mut self) -> SWPOIKEY_W

Bits 0:7 - 0x1B generates a software POI reset. This is a write-only register. Reading from this register will yield only all 0's.

impl W<u32, Reg<u32, _SWPOR>>

pub fn swporkey(&mut self) -> SWPORKEY_W

Bits 0:7 - 0xD4 generates a software POR reset.

impl W<u32, Reg<u32, _TPIURST>>

pub fn tpiurst(&mut self) -> TPIURST_W

Bit 0 - Static reset for the TPIU. Write to '1' to assert reset to TPIU. Write to '0' to clear the reset.

impl W<u32, Reg<u32, _INTEN>>

pub fn bodh(&mut self) -> BODH_W

Bit 0 - Enables an interrupt that triggers when VCC is below BODH level.

impl W<u32, Reg<u32, _INTSTAT>>

pub fn bodh(&mut self) -> BODH_W

Bit 0 - Enables an interrupt that triggers when VCC is below BODH level.

impl W<u32, Reg<u32, _INTCLR>>

pub fn bodh(&mut self) -> BODH_W

Bit 0 - Enables an interrupt that triggers when VCC is below BODH level.

impl W<u32, Reg<u32, _INTSET>>

pub fn bodh(&mut self) -> BODH_W

Bit 0 - Enables an interrupt that triggers when VCC is below BODH level.

impl W<u32, Reg<u32, _STAT>>

pub fn sboot(&mut self) -> SBOOT_W

Bit 31 - Set when booting securely (SBL).

pub fn fboot(&mut self) -> FBOOT_W

Bit 30 - Set if current boot was initiated by soft reset and resulted in Fast Boot (SBL).

pub fn bobstat(&mut self) -> BOBSTAT_W

Bit 10 - A BLE/Burst Regulator Brownout Event occurred (SBL).

pub fn bofstat(&mut self) -> BOFSTAT_W

Bit 9 - A Memory Regulator Brownout Event occurred (SBL).

pub fn bocstat(&mut self) -> BOCSTAT_W

Bit 8 - A Core Regulator Brownout Event occurred (SBL).

pub fn boustat(&mut self) -> BOUSTAT_W

Bit 7 - An Unregulated Supply Brownout Event occurred (SBL).

pub fn wdrstat(&mut self) -> WDRSTAT_W

Bit 6 - Reset was initiated by a Watchdog Timer Reset (SBL).

pub fn dbgrstat(&mut self) -> DBGRSTAT_W

Bit 5 - Reset was a initiated by Debugger Reset (SBL).

pub fn poirstat(&mut self) -> POIRSTAT_W

Bit 4 - Reset was a initiated by Software POI Reset (SBL).

pub fn swrstat(&mut self) -> SWRSTAT_W

Bit 3 - Reset was a initiated by SW POR or AIRCR Reset (SBL).

pub fn borstat(&mut self) -> BORSTAT_W

Bit 2 - Reset was initiated by a Brown-Out Reset (SBL).

pub fn porstat(&mut self) -> PORSTAT_W

Bit 1 - Reset was initiated by a Power-On Reset (SBL).

pub fn exrstat(&mut self) -> EXRSTAT_W

Bit 0 - Reset was initiated by an External Reset (SBL).

impl W<u32, Reg<u32, _CTRLOW>>

pub fn ctrhr(&mut self) -> CTRHR_W

Bits 24:29 - Hours Counter

pub fn ctrmin(&mut self) -> CTRMIN_W

Bits 16:22 - Minutes Counter

pub fn ctrsec(&mut self) -> CTRSEC_W

Bits 8:14 - Seconds Counter

pub fn ctr100(&mut self) -> CTR100_W

Bits 0:7 - 100ths of a second Counter

impl W<u32, Reg<u32, _CTRUP>>

pub fn cterr(&mut self) -> CTERR_W

Bit 31 - Counter read error status. Error is triggered when software reads the lower word of the counters, and fails to read the upper counter within 1/100 second. This is because when the lower counter is read, the upper counter is held off from incrementing until it is read so that the full time stamp can be read.

pub fn ceb(&mut self) -> CEB_W

Bit 28 - Century enable

pub fn cb(&mut self) -> CB_W

Bit 27 - Century

pub fn ctrwkdy(&mut self) -> CTRWKDY_W

Bits 24:26 - Weekdays Counter

pub fn ctryr(&mut self) -> CTRYR_W

Bits 16:23 - Years Counter

pub fn ctrmo(&mut self) -> CTRMO_W

Bits 8:12 - Months Counter

pub fn ctrdate(&mut self) -> CTRDATE_W

Bits 0:5 - Date Counter

impl W<u32, Reg<u32, _ALMLOW>>

pub fn almhr(&mut self) -> ALMHR_W

Bits 24:29 - Hours Alarm

pub fn almmin(&mut self) -> ALMMIN_W

Bits 16:22 - Minutes Alarm

pub fn almsec(&mut self) -> ALMSEC_W

Bits 8:14 - Seconds Alarm

pub fn alm100(&mut self) -> ALM100_W

Bits 0:7 - 100ths of a second Alarm

impl W<u32, Reg<u32, _ALMUP>>

pub fn almwkdy(&mut self) -> ALMWKDY_W

Bits 16:18 - Weekdays Alarm

pub fn almmo(&mut self) -> ALMMO_W

Bits 8:12 - Months Alarm

pub fn almdate(&mut self) -> ALMDATE_W

Bits 0:5 - Date Alarm

impl W<u32, Reg<u32, _RTCCTL>>

pub fn hr1224(&mut self) -> HR1224_W

Bit 5 - Hours Counter mode

pub fn rstop(&mut self) -> RSTOP_W

Bit 4 - RTC input clock control

pub fn rpt(&mut self) -> RPT_W

Bits 1:3 - Alarm repeat interval

pub fn wrtc(&mut self) -> WRTC_W

Bit 0 - Counter write control

impl W<u32, Reg<u32, _INTEN>>

pub fn alm(&mut self) -> ALM_W

Bit 0 - RTC Alarm interrupt

impl W<u32, Reg<u32, _INTSTAT>>

pub fn alm(&mut self) -> ALM_W

Bit 0 - RTC Alarm interrupt

impl W<u32, Reg<u32, _INTCLR>>

pub fn alm(&mut self) -> ALM_W

Bit 0 - RTC Alarm interrupt

impl W<u32, Reg<u32, _INTSET>>

pub fn alm(&mut self) -> ALM_W

Bit 0 - RTC Alarm interrupt

impl W<u32, Reg<u32, _SR>>

pub fn fhf(&mut self) -> FHF_W

Bit 6 - FIFO Half Full.

pub fn ft2rend(&mut self) -> FT2REND_W

Bit 5 - TX to RX finished.

pub fn pe(&mut self) -> PE_W

Bit 4 - Parity Error.

pub fn ovr(&mut self) -> OVR_W

Bit 3 - RX FIFO overflow.

pub fn fer(&mut self) -> FER_W

Bit 2 - Framing error.

pub fn tberbf(&mut self) -> TBERBF_W

Bit 1 - FIFO empty (transmit) or full (receive).

pub fn fne(&mut self) -> FNE_W

Bit 0 - RX FIFO not empty.

impl W<u32, Reg<u32, _IER>>

pub fn fhfen(&mut self) -> FHFEN_W

Bit 6 - FIFO Half Full interrupt enable.

pub fn ft2renden(&mut self) -> FT2RENDEN_W

Bit 5 - TX to RX finished interrupt enable.

pub fn peen(&mut self) -> PEEN_W

Bit 4 - Parity Error interrupt enable.

pub fn ovren(&mut self) -> OVREN_W

Bit 3 - RX FIFOI overflow interrupt enable.

pub fn feren(&mut self) -> FEREN_W

Bit 2 - Framing error interrupt enable.

pub fn tberbfen(&mut self) -> TBERBFEN_W

Bit 1 - FIFO empty (transmit) or full (receive) interrupt enable.

pub fn fneen(&mut self) -> FNEEN_W

Bit 0 - RX FIFO not empty interrupt enable.

impl W<u32, Reg<u32, _TCR>>

pub fn dmamd(&mut self) -> DMAMD_W

Bit 7 - DMA direction.

pub fn fip(&mut self) -> FIP_W

Bit 6 - Parity select.

pub fn autoconv(&mut self) -> AUTOCONV_W

Bit 5 - Automatic conversion.

pub fn prot(&mut self) -> PROT_W

Bit 4 - PROT control.

pub fn tr(&mut self) -> TR_W

Bit 3 - Transmit/receive mode.

pub fn lct(&mut self) -> LCT_W

Bit 2 - Fast TX to RX.

pub fn ss(&mut self) -> SS_W

Bit 1 - Use first byte to configure conversion.

pub fn conv(&mut self) -> CONV_W

Bit 0 - Conversion inversion control.

impl W<u32, Reg<u32, _UCR>>

pub fn retxen(&mut self) -> RETXEN_W

Bit 3 - Enable TX/RX time configuration.

pub fn rstin(&mut self) -> RSTIN_W

Bit 2 - Reset polarity.

pub fn riu(&mut self) -> RIU_W

Bit 1 - ISO7816 reset. This bit is write-only.

pub fn cst(&mut self) -> CST_W

Bit 0 - Clock control.

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W

Bits 0:7 - Data register.

impl W<u32, Reg<u32, _BPRL>>

pub fn bprl(&mut self) -> BPRL_W

Bits 0:7 - Baud rate low

impl W<u32, Reg<u32, _BPRH>>

pub fn bprh(&mut self) -> BPRH_W

Bits 0:3 - Baud rate high

impl W<u32, Reg<u32, _UCR1>>

pub fn enlastb(&mut self) -> ENLASTB_W

Bit 5 - Enable last byte function.

pub fn clkiov(&mut self) -> CLKIOV_W

Bit 4 - Output clock level.

pub fn t1paren(&mut self) -> T1PAREN_W

Bit 3 - Parity check control.

pub fn stsp(&mut self) -> STSP_W

Bit 2 - ETU counter control. This bit is write-only.

pub fn pr(&mut self) -> PR_W

Bit 0 - Query Card Detect.

impl W<u32, Reg<u32, _SR1>>

pub fn idle(&mut self) -> IDLE_W

Bit 3 - ISO7816 idle.

pub fn syncend(&mut self) -> SYNCEND_W

Bit 2 - Write complete synchronization.

pub fn prl(&mut self) -> PRL_W

Bit 1 - Card insert/remove.

pub fn ecntover(&mut self) -> ECNTOVER_W

Bit 0 - ETU counter overflow.

impl W<u32, Reg<u32, _IER1>>

pub fn syncenden(&mut self) -> SYNCENDEN_W

Bit 2 - Write complete synchronization interrupt enable.

pub fn prlen(&mut self) -> PRLEN_W

Bit 1 - Card insert/remove interrupt enable.

pub fn ecntoveren(&mut self) -> ECNTOVEREN_W

Bit 0 - ETU counter overflow interrupt enable.

impl W<u32, Reg<u32, _ECNTL>>

pub fn ecntl(&mut self) -> ECNTL_W

Bits 0:7 - ETU counter low register.

impl W<u32, Reg<u32, _ECNTH>>

pub fn ecnth(&mut self) -> ECNTH_W

Bits 0:7 - ETU counter high register.

impl W<u32, Reg<u32, _GTR>>

pub fn gtr(&mut self) -> GTR_W

Bits 0:7 - Guard time configuration register.

impl W<u32, Reg<u32, _RETXCNT>>

pub fn retxcnt(&mut self) -> RETXCNT_W

Bits 0:3 - Resend count register.

impl W<u32, Reg<u32, _RETXCNTRMI>>

pub fn retxcntrmi(&mut self) -> RETXCNTRMI_W

Bits 0:3 - Resent count inquiry register.

impl W<u32, Reg<u32, _CLKCTRL>>

pub fn apbclken(&mut self) -> APBCLKEN_W

Bit 1 - Enable the SCARD APB clock to run continuously.

pub fn clken(&mut self) -> CLKEN_W

Bit 0 - Enable the serial source clock for SCARD.

impl W<u32, Reg<u32, _CTRL>>

pub fn crcerror(&mut self) -> CRCERROR_W

Bit 31 - CRC Error Status - Set to 1 if an error occurs during a CRC operation. Cleared when CTRL register is written (with any value). Usually indicates an invalid address range.

pub fn function(&mut self) -> FUNCTION_W

Bits 4:7 - Function Select

pub fn enable(&mut self) -> ENABLE_W

Bit 0 - Function Enable. Software should set the ENABLE bit to initiate a CRC operation. Hardware will clear the ENABLE bit upon completion.

impl W<u32, Reg<u32, _SRCADDR>>

pub fn addr(&mut self) -> ADDR_W

Bits 0:31 - Source Buffer Address. Address may be byte aligned, but the length must be a multiple of 4 bits.

impl W<u32, Reg<u32, _LEN>>

pub fn len(&mut self) -> LEN_W

Bits 2:23 - Buffer size (bottom two bits assumed to be zero to ensure a multiple of 4 bytes)

impl W<u32, Reg<u32, _RESULT>>

pub fn crc(&mut self) -> CRC_W

Bits 0:31 - CRC Seed/Result. Software must seed the CRC with 0xFFFFFFFF before starting a CRC operation (unless the CRC is continued from a previous operation).

impl W<u32, Reg<u32, _LOCKCTRL>>

pub fn select(&mut self) -> SELECT_W

Bits 0:7 - LOCK Function Select register.

impl W<u32, Reg<u32, _LOCKSTAT>>

pub fn status(&mut self) -> STATUS_W

Bits 0:31 - LOCK Status register. This register is a bit mask for which resources are currently unlocked. These bits are one-hot per resource.

impl W<u32, Reg<u32, _KEY0>>

pub fn key0(&mut self) -> KEY0_W

Bits 0:31 - Bits [31:0] of the 128-bit key should be written to this register. To protect key values, the register always returns 0x00000000.

impl W<u32, Reg<u32, _KEY1>>

pub fn key1(&mut self) -> KEY1_W

Bits 0:31 - Bits [63:32] of the 128-bit key should be written to this register. To protect key values, the register always returns 0x00000000.

impl W<u32, Reg<u32, _KEY2>>

pub fn key2(&mut self) -> KEY2_W

Bits 0:31 - Bits [95:64] of the 128-bit key should be written to this register. To protect key values, the register always returns 0x00000000.

impl W<u32, Reg<u32, _KEY3>>

pub fn key3(&mut self) -> KEY3_W

Bits 0:31 - Bits [127:96] of the 128-bit key should be written to this register. To protect key values, the register always returns 0x00000000.

impl W<u32, Reg<u32, _DR>>

pub fn oedata(&mut self) -> OEDATA_W

Bit 11 - This is the overrun error indicator.

pub fn bedata(&mut self) -> BEDATA_W

Bit 10 - This is the break error indicator.

pub fn pedata(&mut self) -> PEDATA_W

Bit 9 - This is the parity error indicator.

pub fn fedata(&mut self) -> FEDATA_W

Bit 8 - This is the framing error indicator.

pub fn data(&mut self) -> DATA_W

Bits 0:7 - This is the UART data port.

impl W<u32, Reg<u32, _RSR>>

pub fn oestat(&mut self) -> OESTAT_W

Bit 3 - This is the overrun error indicator.

pub fn bestat(&mut self) -> BESTAT_W

Bit 2 - This is the break error indicator.

pub fn pestat(&mut self) -> PESTAT_W

Bit 1 - This is the parity error indicator.

pub fn festat(&mut self) -> FESTAT_W

Bit 0 - This is the framing error indicator.

impl W<u32, Reg<u32, _FR>>

pub fn txbusy(&mut self) -> TXBUSY_W

Bit 8 - This bit holds the transmit BUSY indicator.

pub fn txfe(&mut self) -> TXFE_W

Bit 7 - This bit holds the transmit FIFO empty indicator.

pub fn rxff(&mut self) -> RXFF_W

Bit 6 - This bit holds the receive FIFO full indicator.

pub fn txff(&mut self) -> TXFF_W

Bit 5 - This bit holds the transmit FIFO full indicator.

pub fn rxfe(&mut self) -> RXFE_W

Bit 4 - This bit holds the receive FIFO empty indicator.

pub fn busy(&mut self) -> BUSY_W

Bit 3 - This bit holds the busy indicator.

pub fn dcd(&mut self) -> DCD_W

Bit 2 - This bit holds the data carrier detect indicator.

pub fn dsr(&mut self) -> DSR_W

Bit 1 - This bit holds the data set ready indicator.

pub fn cts(&mut self) -> CTS_W

Bit 0 - This bit holds the clear to send indicator.

impl W<u32, Reg<u32, _ILPR>>

pub fn ilpdvsr(&mut self) -> ILPDVSR_W

Bits 0:7 - These bits hold the IrDA counter divisor.

impl W<u32, Reg<u32, _IBRD>>

pub fn divint(&mut self) -> DIVINT_W

Bits 0:15 - These bits hold the baud integer divisor.

impl W<u32, Reg<u32, _FBRD>>

pub fn divfrac(&mut self) -> DIVFRAC_W

Bits 0:5 - These bits hold the baud fractional divisor.

impl W<u32, Reg<u32, _LCRH>>

pub fn sps(&mut self) -> SPS_W

Bit 7 - This bit holds the stick parity select.

pub fn wlen(&mut self) -> WLEN_W

Bits 5:6 - These bits hold the write length.

pub fn fen(&mut self) -> FEN_W

Bit 4 - This bit holds the FIFO enable.

pub fn stp2(&mut self) -> STP2_W

Bit 3 - This bit holds the two stop bits select.

pub fn eps(&mut self) -> EPS_W

Bit 2 - This bit holds the even parity select.

pub fn pen(&mut self) -> PEN_W

Bit 1 - This bit holds the parity enable.

pub fn brk(&mut self) -> BRK_W

Bit 0 - This bit holds the break set.

impl W<u32, Reg<u32, _CR>>

pub fn ctsen(&mut self) -> CTSEN_W

Bit 15 - This bit enables CTS hardware flow control.

pub fn rtsen(&mut self) -> RTSEN_W

Bit 14 - This bit enables RTS hardware flow control.

pub fn out2(&mut self) -> OUT2_W

Bit 13 - This bit holds modem Out2.

pub fn out1(&mut self) -> OUT1_W

Bit 12 - This bit holds modem Out1.

pub fn rts(&mut self) -> RTS_W

Bit 11 - This bit enables request to send.

pub fn dtr(&mut self) -> DTR_W

Bit 10 - This bit enables data transmit ready.

pub fn rxe(&mut self) -> RXE_W

Bit 9 - This bit is the receive enable.

pub fn txe(&mut self) -> TXE_W

Bit 8 - This bit is the transmit enable.

pub fn lbe(&mut self) -> LBE_W

Bit 7 - This bit is the loopback enable.

pub fn clksel(&mut self) -> CLKSEL_W

Bits 4:6 - This bit field is the UART clock select.

pub fn clken(&mut self) -> CLKEN_W

Bit 3 - This bit is the UART clock enable.

pub fn sirlp(&mut self) -> SIRLP_W

Bit 2 - This bit is the SIR low power select.

pub fn siren(&mut self) -> SIREN_W

Bit 1 - This bit is the SIR ENDEC enable.

pub fn uarten(&mut self) -> UARTEN_W

Bit 0 - This bit is the UART enable.

impl W<u32, Reg<u32, _IFLS>>

pub fn rxiflsel(&mut self) -> RXIFLSEL_W

Bits 3:5 - These bits hold the receive FIFO interrupt level.

pub fn txiflsel(&mut self) -> TXIFLSEL_W

Bits 0:2 - These bits hold the transmit FIFO interrupt level.

impl W<u32, Reg<u32, _IER>>

pub fn oeim(&mut self) -> OEIM_W

Bit 10 - This bit holds the overflow interrupt enable.

pub fn beim(&mut self) -> BEIM_W

Bit 9 - This bit holds the break error interrupt enable.

pub fn peim(&mut self) -> PEIM_W

Bit 8 - This bit holds the parity error interrupt enable.

pub fn feim(&mut self) -> FEIM_W

Bit 7 - This bit holds the framing error interrupt enable.

pub fn rtim(&mut self) -> RTIM_W

Bit 6 - This bit holds the receive timeout interrupt enable.

pub fn txim(&mut self) -> TXIM_W

Bit 5 - This bit holds the transmit interrupt enable.

pub fn rxim(&mut self) -> RXIM_W

Bit 4 - This bit holds the receive interrupt enable.

pub fn dsrmim(&mut self) -> DSRMIM_W

Bit 3 - This bit holds the modem DSR interrupt enable.

pub fn dcdmim(&mut self) -> DCDMIM_W

Bit 2 - This bit holds the modem DCD interrupt enable.

pub fn ctsmim(&mut self) -> CTSMIM_W

Bit 1 - This bit holds the modem CTS interrupt enable.

pub fn txcmpmim(&mut self) -> TXCMPMIM_W

Bit 0 - This bit holds the modem TXCMP interrupt enable.

impl W<u32, Reg<u32, _IES>>

pub fn oeris(&mut self) -> OERIS_W

Bit 10 - This bit holds the overflow interrupt status.

pub fn beris(&mut self) -> BERIS_W

Bit 9 - This bit holds the break error interrupt status.

pub fn peris(&mut self) -> PERIS_W

Bit 8 - This bit holds the parity error interrupt status.

pub fn feris(&mut self) -> FERIS_W

Bit 7 - This bit holds the framing error interrupt status.

pub fn rtris(&mut self) -> RTRIS_W

Bit 6 - This bit holds the receive timeout interrupt status.

pub fn txris(&mut self) -> TXRIS_W

Bit 5 - This bit holds the transmit interrupt status.

pub fn rxris(&mut self) -> RXRIS_W

Bit 4 - This bit holds the receive interrupt status.

pub fn dsrmris(&mut self) -> DSRMRIS_W

Bit 3 - This bit holds the modem DSR interrupt status.

pub fn dcdmris(&mut self) -> DCDMRIS_W

Bit 2 - This bit holds the modem DCD interrupt status.

pub fn ctsmris(&mut self) -> CTSMRIS_W

Bit 1 - This bit holds the modem CTS interrupt status.

pub fn txcmpmris(&mut self) -> TXCMPMRIS_W

Bit 0 - This bit holds the modem TXCMP interrupt status.

impl W<u32, Reg<u32, _MIS>>

pub fn oemis(&mut self) -> OEMIS_W

Bit 10 - This bit holds the overflow interrupt status masked.

pub fn bemis(&mut self) -> BEMIS_W

Bit 9 - This bit holds the break error interrupt status masked.

pub fn pemis(&mut self) -> PEMIS_W

Bit 8 - This bit holds the parity error interrupt status masked.

pub fn femis(&mut self) -> FEMIS_W

Bit 7 - This bit holds the framing error interrupt status masked.

pub fn rtmis(&mut self) -> RTMIS_W

Bit 6 - This bit holds the receive timeout interrupt status masked.

pub fn txmis(&mut self) -> TXMIS_W

Bit 5 - This bit holds the transmit interrupt status masked.

pub fn rxmis(&mut self) -> RXMIS_W

Bit 4 - This bit holds the receive interrupt status masked.

pub fn dsrmmis(&mut self) -> DSRMMIS_W

Bit 3 - This bit holds the modem DSR interrupt status masked.

pub fn dcdmmis(&mut self) -> DCDMMIS_W

Bit 2 - This bit holds the modem DCD interrupt status masked.

pub fn ctsmmis(&mut self) -> CTSMMIS_W

Bit 1 - This bit holds the modem CTS interrupt status masked.

pub fn txcmpmmis(&mut self) -> TXCMPMMIS_W

Bit 0 - This bit holds the modem TXCMP interrupt status masked.

impl W<u32, Reg<u32, _IEC>>

pub fn oeic(&mut self) -> OEIC_W

Bit 10 - This bit holds the overflow interrupt clear.

pub fn beic(&mut self) -> BEIC_W

Bit 9 - This bit holds the break error interrupt clear.

pub fn peic(&mut self) -> PEIC_W

Bit 8 - This bit holds the parity error interrupt clear.

pub fn feic(&mut self) -> FEIC_W

Bit 7 - This bit holds the framing error interrupt clear.

pub fn rtic(&mut self) -> RTIC_W

Bit 6 - This bit holds the receive timeout interrupt clear.

pub fn txic(&mut self) -> TXIC_W

Bit 5 - This bit holds the transmit interrupt clear.

pub fn rxic(&mut self) -> RXIC_W

Bit 4 - This bit holds the receive interrupt clear.

pub fn dsrmic(&mut self) -> DSRMIC_W

Bit 3 - This bit holds the modem DSR interrupt clear.

pub fn dcdmic(&mut self) -> DCDMIC_W

Bit 2 - This bit holds the modem DCD interrupt clear.

pub fn ctsmic(&mut self) -> CTSMIC_W

Bit 1 - This bit holds the modem CTS interrupt clear.

pub fn txcmpmic(&mut self) -> TXCMPMIC_W

Bit 0 - This bit holds the modem TXCMP interrupt clear.

impl W<u32, Reg<u32, _CFG>>

pub fn lvlsel(&mut self) -> LVLSEL_W

Bits 16:19 - When the reference input NSEL is set to NSEL_DAC, this bit field selects the voltage level for the negative input to the comparator.

pub fn nsel(&mut self) -> NSEL_W

Bits 8:9 - This bit field selects the negative input to the comparator.

pub fn psel(&mut self) -> PSEL_W

Bits 0:1 - This bit field selects the positive input to the comparator.

impl W<u32, Reg<u32, _STAT>>

pub fn pwdstat(&mut self) -> PWDSTAT_W

Bit 1 - This bit indicates the power down state of the voltage comparator.

pub fn cmpout(&mut self) -> CMPOUT_W

Bit 0 - This bit is 1 if the positive input of the comparator is greater than the negative input.

impl W<u32, Reg<u32, _PWDKEY>>

pub fn pwdkey(&mut self) -> PWDKEY_W

Bits 0:31 - Key register value.

impl W<u32, Reg<u32, _INTEN>>

pub fn outhi(&mut self) -> OUTHI_W

Bit 1 - This bit is the vcompout high interrupt.

pub fn outlow(&mut self) -> OUTLOW_W

Bit 0 - This bit is the vcompout low interrupt.

impl W<u32, Reg<u32, _INTSTAT>>

pub fn outhi(&mut self) -> OUTHI_W

Bit 1 - This bit is the vcompout high interrupt.

pub fn outlow(&mut self) -> OUTLOW_W

Bit 0 - This bit is the vcompout low interrupt.

impl W<u32, Reg<u32, _INTCLR>>

pub fn outhi(&mut self) -> OUTHI_W

Bit 1 - This bit is the vcompout high interrupt.

pub fn outlow(&mut self) -> OUTLOW_W

Bit 0 - This bit is the vcompout low interrupt.

impl W<u32, Reg<u32, _INTSET>>

pub fn outhi(&mut self) -> OUTHI_W

Bit 1 - This bit is the vcompout high interrupt.

pub fn outlow(&mut self) -> OUTLOW_W

Bit 0 - This bit is the vcompout low interrupt.

impl W<u32, Reg<u32, _CFG>>

pub fn clksel(&mut self) -> CLKSEL_W

Bits 24:26 - Select the frequency for the WDT. All values not enumerated below are undefined.

pub fn intval(&mut self) -> INTVAL_W

Bits 16:23 - This bit field is the compare value for counter bits 7:0 to generate a watchdog interrupt.

pub fn resval(&mut self) -> RESVAL_W

Bits 8:15 - This bit field is the compare value for counter bits 7:0 to generate a watchdog reset. This will cause a software reset.

pub fn resen(&mut self) -> RESEN_W

Bit 2 - This bit field enables the WDT reset. This needs to be set together with the WDREN bit in REG_RSTGEN_CFG register (in reset gen) to trigger the reset.

pub fn inten(&mut self) -> INTEN_W

Bit 1 - This bit field enables the WDT interrupt. Note : This bit must be set before the interrupt status bit will reflect a watchdog timer expiration. The IER interrupt register must also be enabled for a WDT interrupt to be sent to the NVIC.

pub fn wdten(&mut self) -> WDTEN_W

Bit 0 - This bit field enables the WDT.

impl W<u32, Reg<u32, _RSTRT>>

pub fn rstrt(&mut self) -> RSTRT_W

Bits 0:7 - Writing 0xB2 to WDTRSTRT restarts the watchdog timer. This is a write only register. Reading this register will only provide all 0.

impl W<u32, Reg<u32, _LOCK>>

pub fn lock(&mut self) -> LOCK_W

Bits 0:7 - Writing 0x3A locks the watchdog timer. Once locked, the WDTCFG reg cannot be written and WDTEN is set.

impl W<u32, Reg<u32, _COUNT>>

pub fn count(&mut self) -> COUNT_W

Bits 0:7 - Read-Only current value of the WDT counter

impl W<u32, Reg<u32, _INTEN>>

pub fn wdtint(&mut self) -> WDTINT_W

Bit 0 - Watchdog Timer Interrupt.

impl W<u32, Reg<u32, _INTSTAT>>

pub fn wdtint(&mut self) -> WDTINT_W

Bit 0 - Watchdog Timer Interrupt.

impl W<u32, Reg<u32, _INTCLR>>

pub fn wdtint(&mut self) -> WDTINT_W

Bit 0 - Watchdog Timer Interrupt.

impl W<u32, Reg<u32, _INTSET>>

pub fn wdtint(&mut self) -> WDTINT_W

Bit 0 - Watchdog Timer Interrupt.