ambiq_apollo3_pac2/iom0/
intstat.rs

1#[doc = "Register `INTSTAT` reader"]
2pub struct R(crate::R<INTSTAT_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<INTSTAT_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<INTSTAT_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<INTSTAT_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `INTSTAT` writer"]
17pub struct W(crate::W<INTSTAT_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<INTSTAT_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<INTSTAT_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<INTSTAT_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `CQERR` reader - Error during command queue operations"]
38pub struct CQERR_R(crate::FieldReader<bool, bool>);
39impl CQERR_R {
40    pub(crate) fn new(bits: bool) -> Self {
41        CQERR_R(crate::FieldReader::new(bits))
42    }
43}
44impl core::ops::Deref for CQERR_R {
45    type Target = crate::FieldReader<bool, bool>;
46    #[inline(always)]
47    fn deref(&self) -> &Self::Target {
48        &self.0
49    }
50}
51#[doc = "Field `CQERR` writer - Error during command queue operations"]
52pub struct CQERR_W<'a> {
53    w: &'a mut W,
54}
55impl<'a> CQERR_W<'a> {
56    #[doc = r"Sets the field bit"]
57    #[inline(always)]
58    pub fn set_bit(self) -> &'a mut W {
59        self.bit(true)
60    }
61    #[doc = r"Clears the field bit"]
62    #[inline(always)]
63    pub fn clear_bit(self) -> &'a mut W {
64        self.bit(false)
65    }
66    #[doc = r"Writes raw bits to the field"]
67    #[inline(always)]
68    pub fn bit(self, value: bool) -> &'a mut W {
69        self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14);
70        self.w
71    }
72}
73#[doc = "Field `CQUPD` reader - CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the CQ operation."]
74pub struct CQUPD_R(crate::FieldReader<bool, bool>);
75impl CQUPD_R {
76    pub(crate) fn new(bits: bool) -> Self {
77        CQUPD_R(crate::FieldReader::new(bits))
78    }
79}
80impl core::ops::Deref for CQUPD_R {
81    type Target = crate::FieldReader<bool, bool>;
82    #[inline(always)]
83    fn deref(&self) -> &Self::Target {
84        &self.0
85    }
86}
87#[doc = "Field `CQUPD` writer - CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the CQ operation."]
88pub struct CQUPD_W<'a> {
89    w: &'a mut W,
90}
91impl<'a> CQUPD_W<'a> {
92    #[doc = r"Sets the field bit"]
93    #[inline(always)]
94    pub fn set_bit(self) -> &'a mut W {
95        self.bit(true)
96    }
97    #[doc = r"Clears the field bit"]
98    #[inline(always)]
99    pub fn clear_bit(self) -> &'a mut W {
100        self.bit(false)
101    }
102    #[doc = r"Writes raw bits to the field"]
103    #[inline(always)]
104    pub fn bit(self, value: bool) -> &'a mut W {
105        self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13);
106        self.w
107    }
108}
109#[doc = "Field `CQPAUSED` reader - Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register, the mask is active in the CQIRQMASK field and the event occurs."]
110pub struct CQPAUSED_R(crate::FieldReader<bool, bool>);
111impl CQPAUSED_R {
112    pub(crate) fn new(bits: bool) -> Self {
113        CQPAUSED_R(crate::FieldReader::new(bits))
114    }
115}
116impl core::ops::Deref for CQPAUSED_R {
117    type Target = crate::FieldReader<bool, bool>;
118    #[inline(always)]
119    fn deref(&self) -> &Self::Target {
120        &self.0
121    }
122}
123#[doc = "Field `CQPAUSED` writer - Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register, the mask is active in the CQIRQMASK field and the event occurs."]
124pub struct CQPAUSED_W<'a> {
125    w: &'a mut W,
126}
127impl<'a> CQPAUSED_W<'a> {
128    #[doc = r"Sets the field bit"]
129    #[inline(always)]
130    pub fn set_bit(self) -> &'a mut W {
131        self.bit(true)
132    }
133    #[doc = r"Clears the field bit"]
134    #[inline(always)]
135    pub fn clear_bit(self) -> &'a mut W {
136        self.bit(false)
137    }
138    #[doc = r"Writes raw bits to the field"]
139    #[inline(always)]
140    pub fn bit(self, value: bool) -> &'a mut W {
141        self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12);
142        self.w
143    }
144}
145#[doc = "Field `DERR` reader - DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified."]
146pub struct DERR_R(crate::FieldReader<bool, bool>);
147impl DERR_R {
148    pub(crate) fn new(bits: bool) -> Self {
149        DERR_R(crate::FieldReader::new(bits))
150    }
151}
152impl core::ops::Deref for DERR_R {
153    type Target = crate::FieldReader<bool, bool>;
154    #[inline(always)]
155    fn deref(&self) -> &Self::Target {
156        &self.0
157    }
158}
159#[doc = "Field `DERR` writer - DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified."]
160pub struct DERR_W<'a> {
161    w: &'a mut W,
162}
163impl<'a> DERR_W<'a> {
164    #[doc = r"Sets the field bit"]
165    #[inline(always)]
166    pub fn set_bit(self) -> &'a mut W {
167        self.bit(true)
168    }
169    #[doc = r"Clears the field bit"]
170    #[inline(always)]
171    pub fn clear_bit(self) -> &'a mut W {
172        self.bit(false)
173    }
174    #[doc = r"Writes raw bits to the field"]
175    #[inline(always)]
176    pub fn bit(self, value: bool) -> &'a mut W {
177        self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11);
178        self.w
179    }
180}
181#[doc = "Field `DCMP` reader - DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state"]
182pub struct DCMP_R(crate::FieldReader<bool, bool>);
183impl DCMP_R {
184    pub(crate) fn new(bits: bool) -> Self {
185        DCMP_R(crate::FieldReader::new(bits))
186    }
187}
188impl core::ops::Deref for DCMP_R {
189    type Target = crate::FieldReader<bool, bool>;
190    #[inline(always)]
191    fn deref(&self) -> &Self::Target {
192        &self.0
193    }
194}
195#[doc = "Field `DCMP` writer - DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state"]
196pub struct DCMP_W<'a> {
197    w: &'a mut W,
198}
199impl<'a> DCMP_W<'a> {
200    #[doc = r"Sets the field bit"]
201    #[inline(always)]
202    pub fn set_bit(self) -> &'a mut W {
203        self.bit(true)
204    }
205    #[doc = r"Clears the field bit"]
206    #[inline(always)]
207    pub fn clear_bit(self) -> &'a mut W {
208        self.bit(false)
209    }
210    #[doc = r"Writes raw bits to the field"]
211    #[inline(always)]
212    pub fn bit(self, value: bool) -> &'a mut W {
213        self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10);
214        self.w
215    }
216}
217#[doc = "Field `ARB` reader - Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus."]
218pub struct ARB_R(crate::FieldReader<bool, bool>);
219impl ARB_R {
220    pub(crate) fn new(bits: bool) -> Self {
221        ARB_R(crate::FieldReader::new(bits))
222    }
223}
224impl core::ops::Deref for ARB_R {
225    type Target = crate::FieldReader<bool, bool>;
226    #[inline(always)]
227    fn deref(&self) -> &Self::Target {
228        &self.0
229    }
230}
231#[doc = "Field `ARB` writer - Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus."]
232pub struct ARB_W<'a> {
233    w: &'a mut W,
234}
235impl<'a> ARB_W<'a> {
236    #[doc = r"Sets the field bit"]
237    #[inline(always)]
238    pub fn set_bit(self) -> &'a mut W {
239        self.bit(true)
240    }
241    #[doc = r"Clears the field bit"]
242    #[inline(always)]
243    pub fn clear_bit(self) -> &'a mut W {
244        self.bit(false)
245    }
246    #[doc = r"Writes raw bits to the field"]
247    #[inline(always)]
248    pub fn bit(self, value: bool) -> &'a mut W {
249        self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9);
250        self.w
251    }
252}
253#[doc = "Field `STOP` reader - STOP command interrupt. Asserted when another master on the bus has signaled a STOP command."]
254pub struct STOP_R(crate::FieldReader<bool, bool>);
255impl STOP_R {
256    pub(crate) fn new(bits: bool) -> Self {
257        STOP_R(crate::FieldReader::new(bits))
258    }
259}
260impl core::ops::Deref for STOP_R {
261    type Target = crate::FieldReader<bool, bool>;
262    #[inline(always)]
263    fn deref(&self) -> &Self::Target {
264        &self.0
265    }
266}
267#[doc = "Field `STOP` writer - STOP command interrupt. Asserted when another master on the bus has signaled a STOP command."]
268pub struct STOP_W<'a> {
269    w: &'a mut W,
270}
271impl<'a> STOP_W<'a> {
272    #[doc = r"Sets the field bit"]
273    #[inline(always)]
274    pub fn set_bit(self) -> &'a mut W {
275        self.bit(true)
276    }
277    #[doc = r"Clears the field bit"]
278    #[inline(always)]
279    pub fn clear_bit(self) -> &'a mut W {
280        self.bit(false)
281    }
282    #[doc = r"Writes raw bits to the field"]
283    #[inline(always)]
284    pub fn bit(self, value: bool) -> &'a mut W {
285        self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8);
286        self.w
287    }
288}
289#[doc = "Field `START` reader - START command interrupt. Asserted when another master on the bus has signaled a START command."]
290pub struct START_R(crate::FieldReader<bool, bool>);
291impl START_R {
292    pub(crate) fn new(bits: bool) -> Self {
293        START_R(crate::FieldReader::new(bits))
294    }
295}
296impl core::ops::Deref for START_R {
297    type Target = crate::FieldReader<bool, bool>;
298    #[inline(always)]
299    fn deref(&self) -> &Self::Target {
300        &self.0
301    }
302}
303#[doc = "Field `START` writer - START command interrupt. Asserted when another master on the bus has signaled a START command."]
304pub struct START_W<'a> {
305    w: &'a mut W,
306}
307impl<'a> START_W<'a> {
308    #[doc = r"Sets the field bit"]
309    #[inline(always)]
310    pub fn set_bit(self) -> &'a mut W {
311        self.bit(true)
312    }
313    #[doc = r"Clears the field bit"]
314    #[inline(always)]
315    pub fn clear_bit(self) -> &'a mut W {
316        self.bit(false)
317    }
318    #[doc = r"Writes raw bits to the field"]
319    #[inline(always)]
320    pub fn bit(self, value: bool) -> &'a mut W {
321        self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7);
322        self.w
323    }
324}
325#[doc = "Field `ICMD` reader - illegal command interrupt. Asserted when a command is written when an active command is in progress."]
326pub struct ICMD_R(crate::FieldReader<bool, bool>);
327impl ICMD_R {
328    pub(crate) fn new(bits: bool) -> Self {
329        ICMD_R(crate::FieldReader::new(bits))
330    }
331}
332impl core::ops::Deref for ICMD_R {
333    type Target = crate::FieldReader<bool, bool>;
334    #[inline(always)]
335    fn deref(&self) -> &Self::Target {
336        &self.0
337    }
338}
339#[doc = "Field `ICMD` writer - illegal command interrupt. Asserted when a command is written when an active command is in progress."]
340pub struct ICMD_W<'a> {
341    w: &'a mut W,
342}
343impl<'a> ICMD_W<'a> {
344    #[doc = r"Sets the field bit"]
345    #[inline(always)]
346    pub fn set_bit(self) -> &'a mut W {
347        self.bit(true)
348    }
349    #[doc = r"Clears the field bit"]
350    #[inline(always)]
351    pub fn clear_bit(self) -> &'a mut W {
352        self.bit(false)
353    }
354    #[doc = r"Writes raw bits to the field"]
355    #[inline(always)]
356    pub fn bit(self, value: bool) -> &'a mut W {
357        self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6);
358        self.w
359    }
360}
361#[doc = "Field `IACC` reader - illegal FIFO access interrupt. Asserted when there is a overflow or underflow event"]
362pub struct IACC_R(crate::FieldReader<bool, bool>);
363impl IACC_R {
364    pub(crate) fn new(bits: bool) -> Self {
365        IACC_R(crate::FieldReader::new(bits))
366    }
367}
368impl core::ops::Deref for IACC_R {
369    type Target = crate::FieldReader<bool, bool>;
370    #[inline(always)]
371    fn deref(&self) -> &Self::Target {
372        &self.0
373    }
374}
375#[doc = "Field `IACC` writer - illegal FIFO access interrupt. Asserted when there is a overflow or underflow event"]
376pub struct IACC_W<'a> {
377    w: &'a mut W,
378}
379impl<'a> IACC_W<'a> {
380    #[doc = r"Sets the field bit"]
381    #[inline(always)]
382    pub fn set_bit(self) -> &'a mut W {
383        self.bit(true)
384    }
385    #[doc = r"Clears the field bit"]
386    #[inline(always)]
387    pub fn clear_bit(self) -> &'a mut W {
388        self.bit(false)
389    }
390    #[doc = r"Writes raw bits to the field"]
391    #[inline(always)]
392    pub fn bit(self, value: bool) -> &'a mut W {
393        self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5);
394        self.w
395    }
396}
397#[doc = "Field `NAK` reader - I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus."]
398pub struct NAK_R(crate::FieldReader<bool, bool>);
399impl NAK_R {
400    pub(crate) fn new(bits: bool) -> Self {
401        NAK_R(crate::FieldReader::new(bits))
402    }
403}
404impl core::ops::Deref for NAK_R {
405    type Target = crate::FieldReader<bool, bool>;
406    #[inline(always)]
407    fn deref(&self) -> &Self::Target {
408        &self.0
409    }
410}
411#[doc = "Field `NAK` writer - I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus."]
412pub struct NAK_W<'a> {
413    w: &'a mut W,
414}
415impl<'a> NAK_W<'a> {
416    #[doc = r"Sets the field bit"]
417    #[inline(always)]
418    pub fn set_bit(self) -> &'a mut W {
419        self.bit(true)
420    }
421    #[doc = r"Clears the field bit"]
422    #[inline(always)]
423    pub fn clear_bit(self) -> &'a mut W {
424        self.bit(false)
425    }
426    #[doc = r"Writes raw bits to the field"]
427    #[inline(always)]
428    pub fn bit(self, value: bool) -> &'a mut W {
429        self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4);
430        self.w
431    }
432}
433#[doc = "Field `FOVFL` reader - Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop."]
434pub struct FOVFL_R(crate::FieldReader<bool, bool>);
435impl FOVFL_R {
436    pub(crate) fn new(bits: bool) -> Self {
437        FOVFL_R(crate::FieldReader::new(bits))
438    }
439}
440impl core::ops::Deref for FOVFL_R {
441    type Target = crate::FieldReader<bool, bool>;
442    #[inline(always)]
443    fn deref(&self) -> &Self::Target {
444        &self.0
445    }
446}
447#[doc = "Field `FOVFL` writer - Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop."]
448pub struct FOVFL_W<'a> {
449    w: &'a mut W,
450}
451impl<'a> FOVFL_W<'a> {
452    #[doc = r"Sets the field bit"]
453    #[inline(always)]
454    pub fn set_bit(self) -> &'a mut W {
455        self.bit(true)
456    }
457    #[doc = r"Clears the field bit"]
458    #[inline(always)]
459    pub fn clear_bit(self) -> &'a mut W {
460        self.bit(false)
461    }
462    #[doc = r"Writes raw bits to the field"]
463    #[inline(always)]
464    pub fn bit(self, value: bool) -> &'a mut W {
465        self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3);
466        self.w
467    }
468}
469#[doc = "Field `FUNDFL` reader - Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo."]
470pub struct FUNDFL_R(crate::FieldReader<bool, bool>);
471impl FUNDFL_R {
472    pub(crate) fn new(bits: bool) -> Self {
473        FUNDFL_R(crate::FieldReader::new(bits))
474    }
475}
476impl core::ops::Deref for FUNDFL_R {
477    type Target = crate::FieldReader<bool, bool>;
478    #[inline(always)]
479    fn deref(&self) -> &Self::Target {
480        &self.0
481    }
482}
483#[doc = "Field `FUNDFL` writer - Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo."]
484pub struct FUNDFL_W<'a> {
485    w: &'a mut W,
486}
487impl<'a> FUNDFL_W<'a> {
488    #[doc = r"Sets the field bit"]
489    #[inline(always)]
490    pub fn set_bit(self) -> &'a mut W {
491        self.bit(true)
492    }
493    #[doc = r"Clears the field bit"]
494    #[inline(always)]
495    pub fn clear_bit(self) -> &'a mut W {
496        self.bit(false)
497    }
498    #[doc = r"Writes raw bits to the field"]
499    #[inline(always)]
500    pub fn bit(self, value: bool) -> &'a mut W {
501        self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
502        self.w
503    }
504}
505#[doc = "Field `THR` reader - FIFO Threshold interrupt. For write operations, asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field. For read operations, asserted when the number of valid bytes in the read FIFO equals of exceeds the value set in the RTHR field."]
506pub struct THR_R(crate::FieldReader<bool, bool>);
507impl THR_R {
508    pub(crate) fn new(bits: bool) -> Self {
509        THR_R(crate::FieldReader::new(bits))
510    }
511}
512impl core::ops::Deref for THR_R {
513    type Target = crate::FieldReader<bool, bool>;
514    #[inline(always)]
515    fn deref(&self) -> &Self::Target {
516        &self.0
517    }
518}
519#[doc = "Field `THR` writer - FIFO Threshold interrupt. For write operations, asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field. For read operations, asserted when the number of valid bytes in the read FIFO equals of exceeds the value set in the RTHR field."]
520pub struct THR_W<'a> {
521    w: &'a mut W,
522}
523impl<'a> THR_W<'a> {
524    #[doc = r"Sets the field bit"]
525    #[inline(always)]
526    pub fn set_bit(self) -> &'a mut W {
527        self.bit(true)
528    }
529    #[doc = r"Clears the field bit"]
530    #[inline(always)]
531    pub fn clear_bit(self) -> &'a mut W {
532        self.bit(false)
533    }
534    #[doc = r"Writes raw bits to the field"]
535    #[inline(always)]
536    pub fn bit(self, value: bool) -> &'a mut W {
537        self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
538        self.w
539    }
540}
541#[doc = "Field `CMDCMP` reader - Command Complete interrupt. Asserted when the current operation has completed. For repeated commands, this will only be asserted when the final repeated command is completed."]
542pub struct CMDCMP_R(crate::FieldReader<bool, bool>);
543impl CMDCMP_R {
544    pub(crate) fn new(bits: bool) -> Self {
545        CMDCMP_R(crate::FieldReader::new(bits))
546    }
547}
548impl core::ops::Deref for CMDCMP_R {
549    type Target = crate::FieldReader<bool, bool>;
550    #[inline(always)]
551    fn deref(&self) -> &Self::Target {
552        &self.0
553    }
554}
555#[doc = "Field `CMDCMP` writer - Command Complete interrupt. Asserted when the current operation has completed. For repeated commands, this will only be asserted when the final repeated command is completed."]
556pub struct CMDCMP_W<'a> {
557    w: &'a mut W,
558}
559impl<'a> CMDCMP_W<'a> {
560    #[doc = r"Sets the field bit"]
561    #[inline(always)]
562    pub fn set_bit(self) -> &'a mut W {
563        self.bit(true)
564    }
565    #[doc = r"Clears the field bit"]
566    #[inline(always)]
567    pub fn clear_bit(self) -> &'a mut W {
568        self.bit(false)
569    }
570    #[doc = r"Writes raw bits to the field"]
571    #[inline(always)]
572    pub fn bit(self, value: bool) -> &'a mut W {
573        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
574        self.w
575    }
576}
577impl R {
578    #[doc = "Bit 14 - Error during command queue operations"]
579    #[inline(always)]
580    pub fn cqerr(&self) -> CQERR_R {
581        CQERR_R::new(((self.bits >> 14) & 0x01) != 0)
582    }
583    #[doc = "Bit 13 - CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the CQ operation."]
584    #[inline(always)]
585    pub fn cqupd(&self) -> CQUPD_R {
586        CQUPD_R::new(((self.bits >> 13) & 0x01) != 0)
587    }
588    #[doc = "Bit 12 - Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register, the mask is active in the CQIRQMASK field and the event occurs."]
589    #[inline(always)]
590    pub fn cqpaused(&self) -> CQPAUSED_R {
591        CQPAUSED_R::new(((self.bits >> 12) & 0x01) != 0)
592    }
593    #[doc = "Bit 11 - DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified."]
594    #[inline(always)]
595    pub fn derr(&self) -> DERR_R {
596        DERR_R::new(((self.bits >> 11) & 0x01) != 0)
597    }
598    #[doc = "Bit 10 - DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state"]
599    #[inline(always)]
600    pub fn dcmp(&self) -> DCMP_R {
601        DCMP_R::new(((self.bits >> 10) & 0x01) != 0)
602    }
603    #[doc = "Bit 9 - Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus."]
604    #[inline(always)]
605    pub fn arb(&self) -> ARB_R {
606        ARB_R::new(((self.bits >> 9) & 0x01) != 0)
607    }
608    #[doc = "Bit 8 - STOP command interrupt. Asserted when another master on the bus has signaled a STOP command."]
609    #[inline(always)]
610    pub fn stop(&self) -> STOP_R {
611        STOP_R::new(((self.bits >> 8) & 0x01) != 0)
612    }
613    #[doc = "Bit 7 - START command interrupt. Asserted when another master on the bus has signaled a START command."]
614    #[inline(always)]
615    pub fn start(&self) -> START_R {
616        START_R::new(((self.bits >> 7) & 0x01) != 0)
617    }
618    #[doc = "Bit 6 - illegal command interrupt. Asserted when a command is written when an active command is in progress."]
619    #[inline(always)]
620    pub fn icmd(&self) -> ICMD_R {
621        ICMD_R::new(((self.bits >> 6) & 0x01) != 0)
622    }
623    #[doc = "Bit 5 - illegal FIFO access interrupt. Asserted when there is a overflow or underflow event"]
624    #[inline(always)]
625    pub fn iacc(&self) -> IACC_R {
626        IACC_R::new(((self.bits >> 5) & 0x01) != 0)
627    }
628    #[doc = "Bit 4 - I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus."]
629    #[inline(always)]
630    pub fn nak(&self) -> NAK_R {
631        NAK_R::new(((self.bits >> 4) & 0x01) != 0)
632    }
633    #[doc = "Bit 3 - Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop."]
634    #[inline(always)]
635    pub fn fovfl(&self) -> FOVFL_R {
636        FOVFL_R::new(((self.bits >> 3) & 0x01) != 0)
637    }
638    #[doc = "Bit 2 - Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo."]
639    #[inline(always)]
640    pub fn fundfl(&self) -> FUNDFL_R {
641        FUNDFL_R::new(((self.bits >> 2) & 0x01) != 0)
642    }
643    #[doc = "Bit 1 - FIFO Threshold interrupt. For write operations, asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field. For read operations, asserted when the number of valid bytes in the read FIFO equals of exceeds the value set in the RTHR field."]
644    #[inline(always)]
645    pub fn thr(&self) -> THR_R {
646        THR_R::new(((self.bits >> 1) & 0x01) != 0)
647    }
648    #[doc = "Bit 0 - Command Complete interrupt. Asserted when the current operation has completed. For repeated commands, this will only be asserted when the final repeated command is completed."]
649    #[inline(always)]
650    pub fn cmdcmp(&self) -> CMDCMP_R {
651        CMDCMP_R::new((self.bits & 0x01) != 0)
652    }
653}
654impl W {
655    #[doc = "Bit 14 - Error during command queue operations"]
656    #[inline(always)]
657    pub fn cqerr(&mut self) -> CQERR_W {
658        CQERR_W { w: self }
659    }
660    #[doc = "Bit 13 - CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the CQ operation."]
661    #[inline(always)]
662    pub fn cqupd(&mut self) -> CQUPD_W {
663        CQUPD_W { w: self }
664    }
665    #[doc = "Bit 12 - Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register, the mask is active in the CQIRQMASK field and the event occurs."]
666    #[inline(always)]
667    pub fn cqpaused(&mut self) -> CQPAUSED_W {
668        CQPAUSED_W { w: self }
669    }
670    #[doc = "Bit 11 - DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified."]
671    #[inline(always)]
672    pub fn derr(&mut self) -> DERR_W {
673        DERR_W { w: self }
674    }
675    #[doc = "Bit 10 - DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state"]
676    #[inline(always)]
677    pub fn dcmp(&mut self) -> DCMP_W {
678        DCMP_W { w: self }
679    }
680    #[doc = "Bit 9 - Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus."]
681    #[inline(always)]
682    pub fn arb(&mut self) -> ARB_W {
683        ARB_W { w: self }
684    }
685    #[doc = "Bit 8 - STOP command interrupt. Asserted when another master on the bus has signaled a STOP command."]
686    #[inline(always)]
687    pub fn stop(&mut self) -> STOP_W {
688        STOP_W { w: self }
689    }
690    #[doc = "Bit 7 - START command interrupt. Asserted when another master on the bus has signaled a START command."]
691    #[inline(always)]
692    pub fn start(&mut self) -> START_W {
693        START_W { w: self }
694    }
695    #[doc = "Bit 6 - illegal command interrupt. Asserted when a command is written when an active command is in progress."]
696    #[inline(always)]
697    pub fn icmd(&mut self) -> ICMD_W {
698        ICMD_W { w: self }
699    }
700    #[doc = "Bit 5 - illegal FIFO access interrupt. Asserted when there is a overflow or underflow event"]
701    #[inline(always)]
702    pub fn iacc(&mut self) -> IACC_W {
703        IACC_W { w: self }
704    }
705    #[doc = "Bit 4 - I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus."]
706    #[inline(always)]
707    pub fn nak(&mut self) -> NAK_W {
708        NAK_W { w: self }
709    }
710    #[doc = "Bit 3 - Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop."]
711    #[inline(always)]
712    pub fn fovfl(&mut self) -> FOVFL_W {
713        FOVFL_W { w: self }
714    }
715    #[doc = "Bit 2 - Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo."]
716    #[inline(always)]
717    pub fn fundfl(&mut self) -> FUNDFL_W {
718        FUNDFL_W { w: self }
719    }
720    #[doc = "Bit 1 - FIFO Threshold interrupt. For write operations, asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field. For read operations, asserted when the number of valid bytes in the read FIFO equals of exceeds the value set in the RTHR field."]
721    #[inline(always)]
722    pub fn thr(&mut self) -> THR_W {
723        THR_W { w: self }
724    }
725    #[doc = "Bit 0 - Command Complete interrupt. Asserted when the current operation has completed. For repeated commands, this will only be asserted when the final repeated command is completed."]
726    #[inline(always)]
727    pub fn cmdcmp(&mut self) -> CMDCMP_W {
728        CMDCMP_W { w: self }
729    }
730    #[doc = "Writes raw bits to the register."]
731    #[inline(always)]
732    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
733        self.0.bits(bits);
734        self
735    }
736}
737#[doc = "IO Master Interrupts: Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intstat](index.html) module"]
738pub struct INTSTAT_SPEC;
739impl crate::RegisterSpec for INTSTAT_SPEC {
740    type Ux = u32;
741}
742#[doc = "`read()` method returns [intstat::R](R) reader structure"]
743impl crate::Readable for INTSTAT_SPEC {
744    type Reader = R;
745}
746#[doc = "`write(|w| ..)` method takes [intstat::W](W) writer structure"]
747impl crate::Writable for INTSTAT_SPEC {
748    type Writer = W;
749}
750#[doc = "`reset()` method sets INTSTAT to value 0"]
751impl crate::Resettable for INTSTAT_SPEC {
752    #[inline(always)]
753    fn reset_value() -> Self::Ux {
754        0
755    }
756}
ambiq_apollo3_pac2/iom0/intstat.rs

ambiq_apollo3_pac2/iom0/
intstat.rs
