ambiq_apollo3_pac2/cachectrl/
ctrl.rs

1#[doc = "Register `CTRL` reader"]
2pub struct R(crate::R<CTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CTRL` writer"]
17pub struct W(crate::W<CTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `FLASH1_SLM_ENABLE` reader - Enable Flash Sleep Mode. Write to 1 to put flash 1 into sleep mode. NOTE: there is a 5us latency after waking flash until the first access will be returned."]
38pub struct FLASH1_SLM_ENABLE_R(crate::FieldReader<bool, bool>);
39impl FLASH1_SLM_ENABLE_R {
40    pub(crate) fn new(bits: bool) -> Self {
41        FLASH1_SLM_ENABLE_R(crate::FieldReader::new(bits))
42    }
43}
44impl core::ops::Deref for FLASH1_SLM_ENABLE_R {
45    type Target = crate::FieldReader<bool, bool>;
46    #[inline(always)]
47    fn deref(&self) -> &Self::Target {
48        &self.0
49    }
50}
51#[doc = "Field `FLASH1_SLM_ENABLE` writer - Enable Flash Sleep Mode. Write to 1 to put flash 1 into sleep mode. NOTE: there is a 5us latency after waking flash until the first access will be returned."]
52pub struct FLASH1_SLM_ENABLE_W<'a> {
53    w: &'a mut W,
54}
55impl<'a> FLASH1_SLM_ENABLE_W<'a> {
56    #[doc = r"Sets the field bit"]
57    #[inline(always)]
58    pub fn set_bit(self) -> &'a mut W {
59        self.bit(true)
60    }
61    #[doc = r"Clears the field bit"]
62    #[inline(always)]
63    pub fn clear_bit(self) -> &'a mut W {
64        self.bit(false)
65    }
66    #[doc = r"Writes raw bits to the field"]
67    #[inline(always)]
68    pub fn bit(self, value: bool) -> &'a mut W {
69        self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10);
70        self.w
71    }
72}
73#[doc = "Field `FLASH1_SLM_DISABLE` reader - Disable Flash Sleep Mode. Write 1 to wake flash1 from sleep mode (reading the array will also automatically wake it)."]
74pub struct FLASH1_SLM_DISABLE_R(crate::FieldReader<bool, bool>);
75impl FLASH1_SLM_DISABLE_R {
76    pub(crate) fn new(bits: bool) -> Self {
77        FLASH1_SLM_DISABLE_R(crate::FieldReader::new(bits))
78    }
79}
80impl core::ops::Deref for FLASH1_SLM_DISABLE_R {
81    type Target = crate::FieldReader<bool, bool>;
82    #[inline(always)]
83    fn deref(&self) -> &Self::Target {
84        &self.0
85    }
86}
87#[doc = "Field `FLASH1_SLM_DISABLE` writer - Disable Flash Sleep Mode. Write 1 to wake flash1 from sleep mode (reading the array will also automatically wake it)."]
88pub struct FLASH1_SLM_DISABLE_W<'a> {
89    w: &'a mut W,
90}
91impl<'a> FLASH1_SLM_DISABLE_W<'a> {
92    #[doc = r"Sets the field bit"]
93    #[inline(always)]
94    pub fn set_bit(self) -> &'a mut W {
95        self.bit(true)
96    }
97    #[doc = r"Clears the field bit"]
98    #[inline(always)]
99    pub fn clear_bit(self) -> &'a mut W {
100        self.bit(false)
101    }
102    #[doc = r"Writes raw bits to the field"]
103    #[inline(always)]
104    pub fn bit(self, value: bool) -> &'a mut W {
105        self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9);
106        self.w
107    }
108}
109#[doc = "Field `FLASH1_SLM_STATUS` reader - Flash Sleep Mode Status. 1 indicates that flash1 is in sleep mode, 0 indicates flash1 is in normal mode."]
110pub struct FLASH1_SLM_STATUS_R(crate::FieldReader<bool, bool>);
111impl FLASH1_SLM_STATUS_R {
112    pub(crate) fn new(bits: bool) -> Self {
113        FLASH1_SLM_STATUS_R(crate::FieldReader::new(bits))
114    }
115}
116impl core::ops::Deref for FLASH1_SLM_STATUS_R {
117    type Target = crate::FieldReader<bool, bool>;
118    #[inline(always)]
119    fn deref(&self) -> &Self::Target {
120        &self.0
121    }
122}
123#[doc = "Field `FLASH1_SLM_STATUS` writer - Flash Sleep Mode Status. 1 indicates that flash1 is in sleep mode, 0 indicates flash1 is in normal mode."]
124pub struct FLASH1_SLM_STATUS_W<'a> {
125    w: &'a mut W,
126}
127impl<'a> FLASH1_SLM_STATUS_W<'a> {
128    #[doc = r"Sets the field bit"]
129    #[inline(always)]
130    pub fn set_bit(self) -> &'a mut W {
131        self.bit(true)
132    }
133    #[doc = r"Clears the field bit"]
134    #[inline(always)]
135    pub fn clear_bit(self) -> &'a mut W {
136        self.bit(false)
137    }
138    #[doc = r"Writes raw bits to the field"]
139    #[inline(always)]
140    pub fn bit(self, value: bool) -> &'a mut W {
141        self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8);
142        self.w
143    }
144}
145#[doc = "Field `FLASH0_SLM_ENABLE` reader - Enable Flash Sleep Mode. Write to 1 to put flash 0 into sleep mode. NOTE: there is a 5us latency after waking flash until the first access will be returned."]
146pub struct FLASH0_SLM_ENABLE_R(crate::FieldReader<bool, bool>);
147impl FLASH0_SLM_ENABLE_R {
148    pub(crate) fn new(bits: bool) -> Self {
149        FLASH0_SLM_ENABLE_R(crate::FieldReader::new(bits))
150    }
151}
152impl core::ops::Deref for FLASH0_SLM_ENABLE_R {
153    type Target = crate::FieldReader<bool, bool>;
154    #[inline(always)]
155    fn deref(&self) -> &Self::Target {
156        &self.0
157    }
158}
159#[doc = "Field `FLASH0_SLM_ENABLE` writer - Enable Flash Sleep Mode. Write to 1 to put flash 0 into sleep mode. NOTE: there is a 5us latency after waking flash until the first access will be returned."]
160pub struct FLASH0_SLM_ENABLE_W<'a> {
161    w: &'a mut W,
162}
163impl<'a> FLASH0_SLM_ENABLE_W<'a> {
164    #[doc = r"Sets the field bit"]
165    #[inline(always)]
166    pub fn set_bit(self) -> &'a mut W {
167        self.bit(true)
168    }
169    #[doc = r"Clears the field bit"]
170    #[inline(always)]
171    pub fn clear_bit(self) -> &'a mut W {
172        self.bit(false)
173    }
174    #[doc = r"Writes raw bits to the field"]
175    #[inline(always)]
176    pub fn bit(self, value: bool) -> &'a mut W {
177        self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6);
178        self.w
179    }
180}
181#[doc = "Field `FLASH0_SLM_DISABLE` reader - Disable Flash Sleep Mode. Write 1 to wake flash0 from sleep mode (reading the array will also automatically wake it)."]
182pub struct FLASH0_SLM_DISABLE_R(crate::FieldReader<bool, bool>);
183impl FLASH0_SLM_DISABLE_R {
184    pub(crate) fn new(bits: bool) -> Self {
185        FLASH0_SLM_DISABLE_R(crate::FieldReader::new(bits))
186    }
187}
188impl core::ops::Deref for FLASH0_SLM_DISABLE_R {
189    type Target = crate::FieldReader<bool, bool>;
190    #[inline(always)]
191    fn deref(&self) -> &Self::Target {
192        &self.0
193    }
194}
195#[doc = "Field `FLASH0_SLM_DISABLE` writer - Disable Flash Sleep Mode. Write 1 to wake flash0 from sleep mode (reading the array will also automatically wake it)."]
196pub struct FLASH0_SLM_DISABLE_W<'a> {
197    w: &'a mut W,
198}
199impl<'a> FLASH0_SLM_DISABLE_W<'a> {
200    #[doc = r"Sets the field bit"]
201    #[inline(always)]
202    pub fn set_bit(self) -> &'a mut W {
203        self.bit(true)
204    }
205    #[doc = r"Clears the field bit"]
206    #[inline(always)]
207    pub fn clear_bit(self) -> &'a mut W {
208        self.bit(false)
209    }
210    #[doc = r"Writes raw bits to the field"]
211    #[inline(always)]
212    pub fn bit(self, value: bool) -> &'a mut W {
213        self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5);
214        self.w
215    }
216}
217#[doc = "Field `FLASH0_SLM_STATUS` reader - Flash Sleep Mode Status. 1 indicates that flash0 is in sleep mode, 0 indicates flash0 is in normal mode."]
218pub struct FLASH0_SLM_STATUS_R(crate::FieldReader<bool, bool>);
219impl FLASH0_SLM_STATUS_R {
220    pub(crate) fn new(bits: bool) -> Self {
221        FLASH0_SLM_STATUS_R(crate::FieldReader::new(bits))
222    }
223}
224impl core::ops::Deref for FLASH0_SLM_STATUS_R {
225    type Target = crate::FieldReader<bool, bool>;
226    #[inline(always)]
227    fn deref(&self) -> &Self::Target {
228        &self.0
229    }
230}
231#[doc = "Field `FLASH0_SLM_STATUS` writer - Flash Sleep Mode Status. 1 indicates that flash0 is in sleep mode, 0 indicates flash0 is in normal mode."]
232pub struct FLASH0_SLM_STATUS_W<'a> {
233    w: &'a mut W,
234}
235impl<'a> FLASH0_SLM_STATUS_W<'a> {
236    #[doc = r"Sets the field bit"]
237    #[inline(always)]
238    pub fn set_bit(self) -> &'a mut W {
239        self.bit(true)
240    }
241    #[doc = r"Clears the field bit"]
242    #[inline(always)]
243    pub fn clear_bit(self) -> &'a mut W {
244        self.bit(false)
245    }
246    #[doc = r"Writes raw bits to the field"]
247    #[inline(always)]
248    pub fn bit(self, value: bool) -> &'a mut W {
249        self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4);
250        self.w
251    }
252}
253#[doc = "Field `CACHE_READY` reader - Cache Ready Status (enabled and not processing an invalidate operation)"]
254pub struct CACHE_READY_R(crate::FieldReader<bool, bool>);
255impl CACHE_READY_R {
256    pub(crate) fn new(bits: bool) -> Self {
257        CACHE_READY_R(crate::FieldReader::new(bits))
258    }
259}
260impl core::ops::Deref for CACHE_READY_R {
261    type Target = crate::FieldReader<bool, bool>;
262    #[inline(always)]
263    fn deref(&self) -> &Self::Target {
264        &self.0
265    }
266}
267#[doc = "Field `CACHE_READY` writer - Cache Ready Status (enabled and not processing an invalidate operation)"]
268pub struct CACHE_READY_W<'a> {
269    w: &'a mut W,
270}
271impl<'a> CACHE_READY_W<'a> {
272    #[doc = r"Sets the field bit"]
273    #[inline(always)]
274    pub fn set_bit(self) -> &'a mut W {
275        self.bit(true)
276    }
277    #[doc = r"Clears the field bit"]
278    #[inline(always)]
279    pub fn clear_bit(self) -> &'a mut W {
280        self.bit(false)
281    }
282    #[doc = r"Writes raw bits to the field"]
283    #[inline(always)]
284    pub fn bit(self, value: bool) -> &'a mut W {
285        self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
286        self.w
287    }
288}
289#[doc = "Reset Cache Statistics. When written to a 1, the cache monitor counters will be cleared. The monitor counters can be reset only when the CACHECFG.ENABLE_MONITOR bit is set.\n\nValue on reset: 0"]
290#[derive(Clone, Copy, Debug, PartialEq)]
291pub enum RESET_STAT_A {
292    #[doc = "1: Clear Cache Stats value."]
293    CLEAR = 1,
294}
295impl From<RESET_STAT_A> for bool {
296    #[inline(always)]
297    fn from(variant: RESET_STAT_A) -> Self {
298        variant as u8 != 0
299    }
300}
301#[doc = "Field `RESET_STAT` reader - Reset Cache Statistics. When written to a 1, the cache monitor counters will be cleared. The monitor counters can be reset only when the CACHECFG.ENABLE_MONITOR bit is set."]
302pub struct RESET_STAT_R(crate::FieldReader<bool, RESET_STAT_A>);
303impl RESET_STAT_R {
304    pub(crate) fn new(bits: bool) -> Self {
305        RESET_STAT_R(crate::FieldReader::new(bits))
306    }
307    #[doc = r"Get enumerated values variant"]
308    #[inline(always)]
309    pub fn variant(&self) -> Option<RESET_STAT_A> {
310        match self.bits {
311            true => Some(RESET_STAT_A::CLEAR),
312            _ => None,
313        }
314    }
315    #[doc = "Checks if the value of the field is `CLEAR`"]
316    #[inline(always)]
317    pub fn is_clear(&self) -> bool {
318        **self == RESET_STAT_A::CLEAR
319    }
320}
321impl core::ops::Deref for RESET_STAT_R {
322    type Target = crate::FieldReader<bool, RESET_STAT_A>;
323    #[inline(always)]
324    fn deref(&self) -> &Self::Target {
325        &self.0
326    }
327}
328#[doc = "Field `RESET_STAT` writer - Reset Cache Statistics. When written to a 1, the cache monitor counters will be cleared. The monitor counters can be reset only when the CACHECFG.ENABLE_MONITOR bit is set."]
329pub struct RESET_STAT_W<'a> {
330    w: &'a mut W,
331}
332impl<'a> RESET_STAT_W<'a> {
333    #[doc = r"Writes `variant` to the field"]
334    #[inline(always)]
335    pub fn variant(self, variant: RESET_STAT_A) -> &'a mut W {
336        self.bit(variant.into())
337    }
338    #[doc = "Clear Cache Stats value."]
339    #[inline(always)]
340    pub fn clear(self) -> &'a mut W {
341        self.variant(RESET_STAT_A::CLEAR)
342    }
343    #[doc = r"Sets the field bit"]
344    #[inline(always)]
345    pub fn set_bit(self) -> &'a mut W {
346        self.bit(true)
347    }
348    #[doc = r"Clears the field bit"]
349    #[inline(always)]
350    pub fn clear_bit(self) -> &'a mut W {
351        self.bit(false)
352    }
353    #[doc = r"Writes raw bits to the field"]
354    #[inline(always)]
355    pub fn bit(self, value: bool) -> &'a mut W {
356        self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
357        self.w
358    }
359}
360#[doc = "Field `INVALIDATE` reader - Writing a 1 to this bitfield invalidates the flash cache contents."]
361pub struct INVALIDATE_R(crate::FieldReader<bool, bool>);
362impl INVALIDATE_R {
363    pub(crate) fn new(bits: bool) -> Self {
364        INVALIDATE_R(crate::FieldReader::new(bits))
365    }
366}
367impl core::ops::Deref for INVALIDATE_R {
368    type Target = crate::FieldReader<bool, bool>;
369    #[inline(always)]
370    fn deref(&self) -> &Self::Target {
371        &self.0
372    }
373}
374#[doc = "Field `INVALIDATE` writer - Writing a 1 to this bitfield invalidates the flash cache contents."]
375pub struct INVALIDATE_W<'a> {
376    w: &'a mut W,
377}
378impl<'a> INVALIDATE_W<'a> {
379    #[doc = r"Sets the field bit"]
380    #[inline(always)]
381    pub fn set_bit(self) -> &'a mut W {
382        self.bit(true)
383    }
384    #[doc = r"Clears the field bit"]
385    #[inline(always)]
386    pub fn clear_bit(self) -> &'a mut W {
387        self.bit(false)
388    }
389    #[doc = r"Writes raw bits to the field"]
390    #[inline(always)]
391    pub fn bit(self, value: bool) -> &'a mut W {
392        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
393        self.w
394    }
395}
396impl R {
397    #[doc = "Bit 10 - Enable Flash Sleep Mode. Write to 1 to put flash 1 into sleep mode. NOTE: there is a 5us latency after waking flash until the first access will be returned."]
398    #[inline(always)]
399    pub fn flash1_slm_enable(&self) -> FLASH1_SLM_ENABLE_R {
400        FLASH1_SLM_ENABLE_R::new(((self.bits >> 10) & 0x01) != 0)
401    }
402    #[doc = "Bit 9 - Disable Flash Sleep Mode. Write 1 to wake flash1 from sleep mode (reading the array will also automatically wake it)."]
403    #[inline(always)]
404    pub fn flash1_slm_disable(&self) -> FLASH1_SLM_DISABLE_R {
405        FLASH1_SLM_DISABLE_R::new(((self.bits >> 9) & 0x01) != 0)
406    }
407    #[doc = "Bit 8 - Flash Sleep Mode Status. 1 indicates that flash1 is in sleep mode, 0 indicates flash1 is in normal mode."]
408    #[inline(always)]
409    pub fn flash1_slm_status(&self) -> FLASH1_SLM_STATUS_R {
410        FLASH1_SLM_STATUS_R::new(((self.bits >> 8) & 0x01) != 0)
411    }
412    #[doc = "Bit 6 - Enable Flash Sleep Mode. Write to 1 to put flash 0 into sleep mode. NOTE: there is a 5us latency after waking flash until the first access will be returned."]
413    #[inline(always)]
414    pub fn flash0_slm_enable(&self) -> FLASH0_SLM_ENABLE_R {
415        FLASH0_SLM_ENABLE_R::new(((self.bits >> 6) & 0x01) != 0)
416    }
417    #[doc = "Bit 5 - Disable Flash Sleep Mode. Write 1 to wake flash0 from sleep mode (reading the array will also automatically wake it)."]
418    #[inline(always)]
419    pub fn flash0_slm_disable(&self) -> FLASH0_SLM_DISABLE_R {
420        FLASH0_SLM_DISABLE_R::new(((self.bits >> 5) & 0x01) != 0)
421    }
422    #[doc = "Bit 4 - Flash Sleep Mode Status. 1 indicates that flash0 is in sleep mode, 0 indicates flash0 is in normal mode."]
423    #[inline(always)]
424    pub fn flash0_slm_status(&self) -> FLASH0_SLM_STATUS_R {
425        FLASH0_SLM_STATUS_R::new(((self.bits >> 4) & 0x01) != 0)
426    }
427    #[doc = "Bit 2 - Cache Ready Status (enabled and not processing an invalidate operation)"]
428    #[inline(always)]
429    pub fn cache_ready(&self) -> CACHE_READY_R {
430        CACHE_READY_R::new(((self.bits >> 2) & 0x01) != 0)
431    }
432    #[doc = "Bit 1 - Reset Cache Statistics. When written to a 1, the cache monitor counters will be cleared. The monitor counters can be reset only when the CACHECFG.ENABLE_MONITOR bit is set."]
433    #[inline(always)]
434    pub fn reset_stat(&self) -> RESET_STAT_R {
435        RESET_STAT_R::new(((self.bits >> 1) & 0x01) != 0)
436    }
437    #[doc = "Bit 0 - Writing a 1 to this bitfield invalidates the flash cache contents."]
438    #[inline(always)]
439    pub fn invalidate(&self) -> INVALIDATE_R {
440        INVALIDATE_R::new((self.bits & 0x01) != 0)
441    }
442}
443impl W {
444    #[doc = "Bit 10 - Enable Flash Sleep Mode. Write to 1 to put flash 1 into sleep mode. NOTE: there is a 5us latency after waking flash until the first access will be returned."]
445    #[inline(always)]
446    pub fn flash1_slm_enable(&mut self) -> FLASH1_SLM_ENABLE_W {
447        FLASH1_SLM_ENABLE_W { w: self }
448    }
449    #[doc = "Bit 9 - Disable Flash Sleep Mode. Write 1 to wake flash1 from sleep mode (reading the array will also automatically wake it)."]
450    #[inline(always)]
451    pub fn flash1_slm_disable(&mut self) -> FLASH1_SLM_DISABLE_W {
452        FLASH1_SLM_DISABLE_W { w: self }
453    }
454    #[doc = "Bit 8 - Flash Sleep Mode Status. 1 indicates that flash1 is in sleep mode, 0 indicates flash1 is in normal mode."]
455    #[inline(always)]
456    pub fn flash1_slm_status(&mut self) -> FLASH1_SLM_STATUS_W {
457        FLASH1_SLM_STATUS_W { w: self }
458    }
459    #[doc = "Bit 6 - Enable Flash Sleep Mode. Write to 1 to put flash 0 into sleep mode. NOTE: there is a 5us latency after waking flash until the first access will be returned."]
460    #[inline(always)]
461    pub fn flash0_slm_enable(&mut self) -> FLASH0_SLM_ENABLE_W {
462        FLASH0_SLM_ENABLE_W { w: self }
463    }
464    #[doc = "Bit 5 - Disable Flash Sleep Mode. Write 1 to wake flash0 from sleep mode (reading the array will also automatically wake it)."]
465    #[inline(always)]
466    pub fn flash0_slm_disable(&mut self) -> FLASH0_SLM_DISABLE_W {
467        FLASH0_SLM_DISABLE_W { w: self }
468    }
469    #[doc = "Bit 4 - Flash Sleep Mode Status. 1 indicates that flash0 is in sleep mode, 0 indicates flash0 is in normal mode."]
470    #[inline(always)]
471    pub fn flash0_slm_status(&mut self) -> FLASH0_SLM_STATUS_W {
472        FLASH0_SLM_STATUS_W { w: self }
473    }
474    #[doc = "Bit 2 - Cache Ready Status (enabled and not processing an invalidate operation)"]
475    #[inline(always)]
476    pub fn cache_ready(&mut self) -> CACHE_READY_W {
477        CACHE_READY_W { w: self }
478    }
479    #[doc = "Bit 1 - Reset Cache Statistics. When written to a 1, the cache monitor counters will be cleared. The monitor counters can be reset only when the CACHECFG.ENABLE_MONITOR bit is set."]
480    #[inline(always)]
481    pub fn reset_stat(&mut self) -> RESET_STAT_W {
482        RESET_STAT_W { w: self }
483    }
484    #[doc = "Bit 0 - Writing a 1 to this bitfield invalidates the flash cache contents."]
485    #[inline(always)]
486    pub fn invalidate(&mut self) -> INVALIDATE_W {
487        INVALIDATE_W { w: self }
488    }
489    #[doc = "Writes raw bits to the register."]
490    #[inline(always)]
491    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
492        self.0.bits(bits);
493        self
494    }
495}
496#[doc = "Cache Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"]
497pub struct CTRL_SPEC;
498impl crate::RegisterSpec for CTRL_SPEC {
499    type Ux = u32;
500}
501#[doc = "`read()` method returns [ctrl::R](R) reader structure"]
502impl crate::Readable for CTRL_SPEC {
503    type Reader = R;
504}
505#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"]
506impl crate::Writable for CTRL_SPEC {
507    type Writer = W;
508}
509#[doc = "`reset()` method sets CTRL to value 0"]
510impl crate::Resettable for CTRL_SPEC {
511    #[inline(always)]
512    fn reset_value() -> Self::Ux {
513        0
514    }
515}
ambiq_apollo3_pac2/cachectrl/ctrl.rs

ambiq_apollo3_pac2/cachectrl/
ctrl.rs
