Struct ambiq_apollo3_pac::mspi::intclr::W

pub struct W { /* fields omitted */ }

Value to write to the register

Methods

impl W

pub fn reset_value() -> W

Reset value of the register

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register

pub fn screrr(&mut self) -> _SCRERRW

Bit 12 - Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address.

pub fn cqerr(&mut self) -> _CQERRW

Bit 11 - Command Queue Error Interrupt

pub fn cqpaused(&mut self) -> _CQPAUSEDW

Bit 10 - Command Queue is Paused.

pub fn cqupd(&mut self) -> _CQUPDW

Bit 9 - Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts.

pub fn cqcmp(&mut self) -> _CQCMPW

Bit 8 - Command Queue Complete Interrupt

pub fn derr(&mut self) -> _DERRW

Bit 7 - DMA Error Interrupt

pub fn dcmp(&mut self) -> _DCMPW

Bit 6 - DMA Complete Interrupt

pub fn rxf(&mut self) -> _RXFW

Bit 5 - Receive FIFO full

pub fn rxo(&mut self) -> _RXOW

Bit 4 - Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)

pub fn rxu(&mut self) -> _RXUW

Bit 3 - Receive FIFO underflow (only occurs when SW reads from an empty FIFO)

pub fn txo(&mut self) -> _TXOW

Bit 2 - Transmit FIFO Overflow (only occurs when SW writes to a full FIFO).

pub fn txe(&mut self) -> _TXEW

Bit 1 - Transmit FIFO empty.

pub fn cmdcmp(&mut self) -> _CMDCMPW

Bit 0 - Transfer complete. Note that DMA and CQ operations are layered, so CMDCMP, DCMP, and CQ* can all be signalled simultaneously