Struct ambiq_apollo3_pac::adc::cfg::R

pub struct R { /* fields omitted */ }

Value read from the register

Methods

impl R

pub fn bits(&self) -> u32

Value of the register as raw bits

pub fn clksel(&self) -> CLKSELR

Bits 24:25 - Select the source and frequency for the ADC clock. All values not enumerated below are undefined.

pub fn trigpol(&self) -> TRIGPOLR

Bit 19 - This bit selects the ADC trigger polarity for external off chip triggers.

pub fn trigsel(&self) -> TRIGSELR

Bits 16:18 - Select the ADC trigger source.

pub fn dfiforden(&self) -> DFIFORDENR

Bit 12 - Destructive FIFO Read Enable. Setting this will enable FIFO pop upon reading the FIFOPR register.

pub fn refsel(&self) -> REFSELR

Bits 8:9 - Select the ADC reference voltage.

pub fn ckmode(&self) -> CKMODER

Bit 4 - Clock mode register

pub fn lpmode(&self) -> LPMODER

Bit 3 - Select power mode to enter between active scans.

pub fn rpten(&self) -> RPTENR

Bit 2 - This bit enables Repeating Scan Mode.

pub fn adcen(&self) -> ADCENR

Bit 0 - This bit enables the ADC module. While the ADC is enabled, the ADCCFG and SLOT Configuration regsiter settings must remain stable and unchanged. All configuration register settings, slot configuration settings and window comparison settings should be written prior to setting the ADCEN bit to '1'.