[−][src]Module ambiq_apollo1_pac::uart::cr

Control Register

Structs

CLKEN_W	Write proxy for field `CLKEN`
CLKSEL_W	Write proxy for field `CLKSEL`
CTSEN_W	Write proxy for field `CTSEN`
DTR_W	Write proxy for field `DTR`
LBE_W	Write proxy for field `LBE`
OUT1_W	Write proxy for field `OUT1`
OUT2_W	Write proxy for field `OUT2`
RTSEN_W	Write proxy for field `RTSEN`
RTS_W	Write proxy for field `RTS`
RXE_W	Write proxy for field `RXE`
SIREN_W	Write proxy for field `SIREN`
SIRLP_W	Write proxy for field `SIRLP`
TXE_W	Write proxy for field `TXE`
UARTEN_W	Write proxy for field `UARTEN`

Enums

This bitfield is the UART clock select.

Type Definitions

CLKEN_R	Reader of field `CLKEN`
CLKSEL_R	Reader of field `CLKSEL`
CTSEN_R	Reader of field `CTSEN`
DTR_R	Reader of field `DTR`
LBE_R	Reader of field `LBE`
OUT1_R	Reader of field `OUT1`
OUT2_R	Reader of field `OUT2`
R	Reader of register CR
RTSEN_R	Reader of field `RTSEN`
RTS_R	Reader of field `RTS`
RXE_R	Reader of field `RXE`
SIREN_R	Reader of field `SIREN`
SIRLP_R	Reader of field `SIRLP`
TXE_R	Reader of field `TXE`
UARTEN_R	Reader of field `UARTEN`
W	Writer for register CR