Type Definition ambiq_apollo1_pac::adc::sl7cfg::R

type R = R<u32, SL7CFG>;

Reader of register SL7CFG

Methods

impl R

pub fn adsel7(&self) -> ADSEL7_R

Bits 24:26 - Select the number of measurements to average in the accumulate divide module for this slot.

pub fn thsel7(&self) -> THSEL7_R

Bits 16:18 - Select track and hold delay for this slot. NOTE: The track and hold delay must be less than 50us for correct operation. When the ADC is configured to use the 1.5Mhz clock, the track and hold delay cannot exceed 64 clocks.

pub fn chsel7(&self) -> CHSEL7_R

Bits 8:11 - Select one of the 13 channel inputs for this slot.

pub fn wcen7(&self) -> WCEN7_R

Bit 1 - This bit enables the window compare function for slot 7.

pub fn slen7(&self) -> SLEN7_R

Bit 0 - This bit enables slot 7 for ADC conversions.