Type Definition ambiq_apollo1_pac::adc::cfg::W

type W = W<u32, CFG>;

Writer for register CFG

Methods

impl W

pub fn clksel(&mut self) -> CLKSEL_W

Bits 24:26 - Select the source and frequency for the ADC clock. All values not enumerated below are undefined.

pub fn trigpol(&mut self) -> TRIGPOL_W

Bit 20 - This bit selects the ADC trigger polarity for external off chip triggers.

pub fn trigsel(&mut self) -> TRIGSEL_W

Bits 16:19 - Select the ADC trigger source.

pub fn refsel(&mut self) -> REFSEL_W

Bits 8:9 - Select the ADC reference voltage.

pub fn battload(&mut self) -> BATTLOAD_W

Bit 7 - Control 500 Ohm battery load resistor.

pub fn opmode(&mut self) -> OPMODE_W

Bits 5:6 - Select the sample rate mode. It adjusts the current in the ADC for higher sample rates. A 12MHz ADC clock can result in a sample rate up to 1Msps depending on the trigger or repeating mode rate. A 1.5MHz ADC clock can result in a sample rate up 125K sps. NOTE: All other values not specified below are undefined.

pub fn lpmode(&mut self) -> LPMODE_W

Bits 3:4 - Select power mode to enter between active scans.

pub fn rpten(&mut self) -> RPTEN_W

Bit 2 - This bit enables Repeating Scan Mode.

pub fn tmpspwr(&mut self) -> TMPSPWR_W

Bit 1 - This enables power to the temperature sensor module. After setting this bit, the temperature sensor will remain powered down while the ADC is power is disconnected (i.e, when the ADC PWDSTAT is 2'b10).

pub fn adcen(&mut self) -> ADCEN_W

Bit 0 - This bit enables the ADC module. While the ADC is enabled, the ADCCFG and SLOT Configuration regsiter settings must remain stable and unchanged.