Type Definition ambiq_apollo1_pac::adc::cfg::R

type R = R<u32, CFG>;

Reader of register CFG

Methods

impl R

pub fn clksel(&self) -> CLKSEL_R

Bits 24:26 - Select the source and frequency for the ADC clock. All values not enumerated below are undefined.

pub fn trigpol(&self) -> TRIGPOL_R

Bit 20 - This bit selects the ADC trigger polarity for external off chip triggers.

pub fn trigsel(&self) -> TRIGSEL_R

Bits 16:19 - Select the ADC trigger source.

pub fn refsel(&self) -> REFSEL_R

Bits 8:9 - Select the ADC reference voltage.

pub fn battload(&self) -> BATTLOAD_R

Bit 7 - Control 500 Ohm battery load resistor.

pub fn opmode(&self) -> OPMODE_R

Bits 5:6 - Select the sample rate mode. It adjusts the current in the ADC for higher sample rates. A 12MHz ADC clock can result in a sample rate up to 1Msps depending on the trigger or repeating mode rate. A 1.5MHz ADC clock can result in a sample rate up 125K sps. NOTE: All other values not specified below are undefined.

pub fn lpmode(&self) -> LPMODE_R

Bits 3:4 - Select power mode to enter between active scans.

pub fn rpten(&self) -> RPTEN_R

Bit 2 - This bit enables Repeating Scan Mode.

pub fn tmpspwr(&self) -> TMPSPWR_R

Bit 1 - This enables power to the temperature sensor module. After setting this bit, the temperature sensor will remain powered down while the ADC is power is disconnected (i.e, when the ADC PWDSTAT is 2'b10).

pub fn adcen(&self) -> ADCEN_R

Bit 0 - This bit enables the ADC module. While the ADC is enabled, the ADCCFG and SLOT Configuration regsiter settings must remain stable and unchanged.