1#[doc = "Register `CCR3` reader"]
2pub type R = crate::R<CCR3_SPEC>;
3#[doc = "Register `CCR3` writer"]
4pub type W = crate::W<CCR3_SPEC>;
5#[doc = "Field `EN` reader - Channel enable"]
6pub type EN_R = crate::BitReader;
7#[doc = "Field `EN` writer - Channel enable"]
8pub type EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
9#[doc = "Field `TCIE` reader - Transfer complete interrupt enable"]
10pub type TCIE_R = crate::BitReader;
11#[doc = "Field `TCIE` writer - Transfer complete interrupt enable"]
12pub type TCIE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
13#[doc = "Field `HTIE` reader - Half Transfer interrupt enable"]
14pub type HTIE_R = crate::BitReader;
15#[doc = "Field `HTIE` writer - Half Transfer interrupt enable"]
16pub type HTIE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
17#[doc = "Field `TEIE` reader - Transfer error interrupt enable"]
18pub type TEIE_R = crate::BitReader;
19#[doc = "Field `TEIE` writer - Transfer error interrupt enable"]
20pub type TEIE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
21#[doc = "Field `DIR` reader - Data transfer direction"]
22pub type DIR_R = crate::BitReader;
23#[doc = "Field `DIR` writer - Data transfer direction"]
24pub type DIR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
25#[doc = "Field `CIRC` reader - Circular mode"]
26pub type CIRC_R = crate::BitReader;
27#[doc = "Field `CIRC` writer - Circular mode"]
28pub type CIRC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
29#[doc = "Field `PINC` reader - Peripheral increment mode"]
30pub type PINC_R = crate::BitReader;
31#[doc = "Field `PINC` writer - Peripheral increment mode"]
32pub type PINC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
33#[doc = "Field `MINC` reader - Memory increment mode"]
34pub type MINC_R = crate::BitReader;
35#[doc = "Field `MINC` writer - Memory increment mode"]
36pub type MINC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
37#[doc = "Field `PSIZE` reader - Peripheral size"]
38pub type PSIZE_R = crate::FieldReader;
39#[doc = "Field `PSIZE` writer - Peripheral size"]
40pub type PSIZE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>;
41#[doc = "Field `MSIZE` reader - Memory size"]
42pub type MSIZE_R = crate::FieldReader;
43#[doc = "Field `MSIZE` writer - Memory size"]
44pub type MSIZE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>;
45#[doc = "Field `PL` reader - Channel Priority level"]
46pub type PL_R = crate::FieldReader;
47#[doc = "Field `PL` writer - Channel Priority level"]
48pub type PL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>;
49#[doc = "Field `MEM2MEM` reader - Memory to memory mode"]
50pub type MEM2MEM_R = crate::BitReader;
51#[doc = "Field `MEM2MEM` writer - Memory to memory mode"]
52pub type MEM2MEM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
53impl R {
54 #[doc = "Bit 0 - Channel enable"]
55 #[inline(always)]
56 pub fn en(&self) -> EN_R {
57 EN_R::new((self.bits & 1) != 0)
58 }
59 #[doc = "Bit 1 - Transfer complete interrupt enable"]
60 #[inline(always)]
61 pub fn tcie(&self) -> TCIE_R {
62 TCIE_R::new(((self.bits >> 1) & 1) != 0)
63 }
64 #[doc = "Bit 2 - Half Transfer interrupt enable"]
65 #[inline(always)]
66 pub fn htie(&self) -> HTIE_R {
67 HTIE_R::new(((self.bits >> 2) & 1) != 0)
68 }
69 #[doc = "Bit 3 - Transfer error interrupt enable"]
70 #[inline(always)]
71 pub fn teie(&self) -> TEIE_R {
72 TEIE_R::new(((self.bits >> 3) & 1) != 0)
73 }
74 #[doc = "Bit 4 - Data transfer direction"]
75 #[inline(always)]
76 pub fn dir(&self) -> DIR_R {
77 DIR_R::new(((self.bits >> 4) & 1) != 0)
78 }
79 #[doc = "Bit 5 - Circular mode"]
80 #[inline(always)]
81 pub fn circ(&self) -> CIRC_R {
82 CIRC_R::new(((self.bits >> 5) & 1) != 0)
83 }
84 #[doc = "Bit 6 - Peripheral increment mode"]
85 #[inline(always)]
86 pub fn pinc(&self) -> PINC_R {
87 PINC_R::new(((self.bits >> 6) & 1) != 0)
88 }
89 #[doc = "Bit 7 - Memory increment mode"]
90 #[inline(always)]
91 pub fn minc(&self) -> MINC_R {
92 MINC_R::new(((self.bits >> 7) & 1) != 0)
93 }
94 #[doc = "Bits 8:9 - Peripheral size"]
95 #[inline(always)]
96 pub fn psize(&self) -> PSIZE_R {
97 PSIZE_R::new(((self.bits >> 8) & 3) as u8)
98 }
99 #[doc = "Bits 10:11 - Memory size"]
100 #[inline(always)]
101 pub fn msize(&self) -> MSIZE_R {
102 MSIZE_R::new(((self.bits >> 10) & 3) as u8)
103 }
104 #[doc = "Bits 12:13 - Channel Priority level"]
105 #[inline(always)]
106 pub fn pl(&self) -> PL_R {
107 PL_R::new(((self.bits >> 12) & 3) as u8)
108 }
109 #[doc = "Bit 14 - Memory to memory mode"]
110 #[inline(always)]
111 pub fn mem2mem(&self) -> MEM2MEM_R {
112 MEM2MEM_R::new(((self.bits >> 14) & 1) != 0)
113 }
114}
115impl W {
116 #[doc = "Bit 0 - Channel enable"]
117 #[inline(always)]
118 #[must_use]
119 pub fn en(&mut self) -> EN_W<CCR3_SPEC, 0> {
120 EN_W::new(self)
121 }
122 #[doc = "Bit 1 - Transfer complete interrupt enable"]
123 #[inline(always)]
124 #[must_use]
125 pub fn tcie(&mut self) -> TCIE_W<CCR3_SPEC, 1> {
126 TCIE_W::new(self)
127 }
128 #[doc = "Bit 2 - Half Transfer interrupt enable"]
129 #[inline(always)]
130 #[must_use]
131 pub fn htie(&mut self) -> HTIE_W<CCR3_SPEC, 2> {
132 HTIE_W::new(self)
133 }
134 #[doc = "Bit 3 - Transfer error interrupt enable"]
135 #[inline(always)]
136 #[must_use]
137 pub fn teie(&mut self) -> TEIE_W<CCR3_SPEC, 3> {
138 TEIE_W::new(self)
139 }
140 #[doc = "Bit 4 - Data transfer direction"]
141 #[inline(always)]
142 #[must_use]
143 pub fn dir(&mut self) -> DIR_W<CCR3_SPEC, 4> {
144 DIR_W::new(self)
145 }
146 #[doc = "Bit 5 - Circular mode"]
147 #[inline(always)]
148 #[must_use]
149 pub fn circ(&mut self) -> CIRC_W<CCR3_SPEC, 5> {
150 CIRC_W::new(self)
151 }
152 #[doc = "Bit 6 - Peripheral increment mode"]
153 #[inline(always)]
154 #[must_use]
155 pub fn pinc(&mut self) -> PINC_W<CCR3_SPEC, 6> {
156 PINC_W::new(self)
157 }
158 #[doc = "Bit 7 - Memory increment mode"]
159 #[inline(always)]
160 #[must_use]
161 pub fn minc(&mut self) -> MINC_W<CCR3_SPEC, 7> {
162 MINC_W::new(self)
163 }
164 #[doc = "Bits 8:9 - Peripheral size"]
165 #[inline(always)]
166 #[must_use]
167 pub fn psize(&mut self) -> PSIZE_W<CCR3_SPEC, 8> {
168 PSIZE_W::new(self)
169 }
170 #[doc = "Bits 10:11 - Memory size"]
171 #[inline(always)]
172 #[must_use]
173 pub fn msize(&mut self) -> MSIZE_W<CCR3_SPEC, 10> {
174 MSIZE_W::new(self)
175 }
176 #[doc = "Bits 12:13 - Channel Priority level"]
177 #[inline(always)]
178 #[must_use]
179 pub fn pl(&mut self) -> PL_W<CCR3_SPEC, 12> {
180 PL_W::new(self)
181 }
182 #[doc = "Bit 14 - Memory to memory mode"]
183 #[inline(always)]
184 #[must_use]
185 pub fn mem2mem(&mut self) -> MEM2MEM_W<CCR3_SPEC, 14> {
186 MEM2MEM_W::new(self)
187 }
188 #[doc = r" Writes raw bits to the register."]
189 #[doc = r""]
190 #[doc = r" # Safety"]
191 #[doc = r""]
192 #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
193 #[inline(always)]
194 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
195 self.bits = bits;
196 self
197 }
198}
199#[doc = "DMA channel configuration register (DMA_CCR)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccr3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
200pub struct CCR3_SPEC;
201impl crate::RegisterSpec for CCR3_SPEC {
202 type Ux = u32;
203}
204#[doc = "`read()` method returns [`ccr3::R`](R) reader structure"]
205impl crate::Readable for CCR3_SPEC {}
206#[doc = "`write(|w| ..)` method takes [`ccr3::W`](W) writer structure"]
207impl crate::Writable for CCR3_SPEC {
208 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
209 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
210}
211#[doc = "`reset()` method sets CCR3 to value 0"]
212impl crate::Resettable for CCR3_SPEC {
213 const RESET_VALUE: Self::Ux = 0;
214}