Crate aclint

Expand description

Rust support for RISC-V ACLINT (Advanced Core Local Interruptor) peripheral.

RISC-V ACLINT is defined in https://github.com/riscv/riscv-aclint.

Structs§

MSIP: One MSIP register.
MSWI: Machine-level Software Interrupt Device (MSWI).
MTIME: MTIME register.
MTIMECMP: One MTIMECMP register.
MTIMER: Machine-level Timer Device (MTIMER).
SETSSIP: One SETSSIP register.
SSWI: Supervisor-level Software Interrupt Device (SSWI).
SifiveClint: Sifive CLINT device.