aarch64_define/
lib.rs

1//! aarch64 架构以及一些配置定义
2#![no_std]
3#![allow(non_upper_case_globals)]
4#![allow(missing_docs)]
5
6use core::mem::{offset_of, size_of};
7
8/// aarch64 pt 寄存器
9///
10/// 保证 C ABI 兼容并且 16 字节对齐
11#[repr(C)]
12pub struct Ptregs {
13    regs_x0: u64,
14    regs_x1: u64,
15    regs_x2: u64,
16    regs_x3: u64,
17    regs_x4: u64,
18    regs_x5: u64,
19    regs_x6: u64,
20    regs_x7: u64,
21    regs_x8: u64,
22    regs_x9: u64,
23    regs_x10: u64,
24    regs_x11: u64,
25    regs_x12: u64,
26    regs_x13: u64,
27    regs_x14: u64,
28    regs_x15: u64,
29    regs_x16: u64,
30    regs_x17: u64,
31    regs_x18: u64,
32    regs_x19: u64,
33    regs_x20: u64,
34    regs_x21: u64,
35    regs_x22: u64,
36    regs_x23: u64,
37    regs_x24: u64,
38    regs_x25: u64,
39    regs_x26: u64,
40    regs_x27: u64,
41    regs_x28: u64,
42    regs_x29: u64,
43    regs_x30: u64,
44    sp: u64,
45    pc: u64,
46    pstate: u64,
47
48    orig_x0: u64,
49    syscallno: i32,
50    unused2: u32,
51    orig_addr_limit: u64,
52    unused: u64,
53    stackframe: [u64; 2],
54}
55
56impl Ptregs {
57    /// 获取`pc`
58    pub fn get_pc(&self) -> u64 {
59        self.pc
60    }
61
62    /// 获取`pstate`
63    pub fn get_pstate(&self) -> u64 {
64        self.pstate
65    }
66
67    /// 获取`orig_addr_limit`
68    pub fn get_orig_addr_limit(&self) -> u64 {
69        self.orig_addr_limit
70    }
71}
72
73/// x0 寄存器偏移
74pub const S_X0: usize = offset_of!(Ptregs, regs_x0);
75/// x1 寄存器偏移
76pub const S_X1: usize = offset_of!(Ptregs, regs_x1);
77/// x2 寄存器偏移
78pub const S_X2: usize = offset_of!(Ptregs, regs_x2);
79/// x3 寄存器偏移
80pub const S_X3: usize = offset_of!(Ptregs, regs_x3);
81/// x4 寄存器偏移
82pub const S_X4: usize = offset_of!(Ptregs, regs_x4);
83/// x5 寄存器偏移
84pub const S_X5: usize = offset_of!(Ptregs, regs_x5);
85/// x6 寄存器偏移
86pub const S_X6: usize = offset_of!(Ptregs, regs_x6);
87/// x7 寄存器偏移
88pub const S_X7: usize = offset_of!(Ptregs, regs_x7);
89/// x8 寄存器偏移
90pub const S_X8: usize = offset_of!(Ptregs, regs_x8);
91/// x9 寄存器偏移
92pub const S_X9: usize = offset_of!(Ptregs, regs_x9);
93/// x10 寄存器偏移
94pub const S_X10: usize = offset_of!(Ptregs, regs_x10);
95/// x11 寄存器偏移
96pub const S_X11: usize = offset_of!(Ptregs, regs_x11);
97/// x12 寄存器偏移
98pub const S_X12: usize = offset_of!(Ptregs, regs_x12);
99/// x13 寄存器偏移
100pub const S_X13: usize = offset_of!(Ptregs, regs_x13);
101/// x14 寄存器偏移
102pub const S_X14: usize = offset_of!(Ptregs, regs_x14);
103/// x15 寄存器偏移
104pub const S_X15: usize = offset_of!(Ptregs, regs_x15);
105/// x16 寄存器偏移
106pub const S_X16: usize = offset_of!(Ptregs, regs_x16);
107/// x17 寄存器偏移
108pub const S_X17: usize = offset_of!(Ptregs, regs_x17);
109/// x18 寄存器偏移
110pub const S_X18: usize = offset_of!(Ptregs, regs_x18);
111/// x19 寄存器偏移
112pub const S_X19: usize = offset_of!(Ptregs, regs_x19);
113/// x20 寄存器偏移
114pub const S_X20: usize = offset_of!(Ptregs, regs_x20);
115/// x21 寄存器偏移
116pub const S_X21: usize = offset_of!(Ptregs, regs_x21);
117/// x22 寄存器偏移
118pub const S_X22: usize = offset_of!(Ptregs, regs_x22);
119/// x23 寄存器偏移
120pub const S_X23: usize = offset_of!(Ptregs, regs_x23);
121/// x24 寄存器偏移
122pub const S_X24: usize = offset_of!(Ptregs, regs_x24);
123/// x25 寄存器偏移
124pub const S_X25: usize = offset_of!(Ptregs, regs_x25);
125/// x26 寄存器偏移
126pub const S_X26: usize = offset_of!(Ptregs, regs_x26);
127/// x27 寄存器偏移
128pub const S_X27: usize = offset_of!(Ptregs, regs_x27);
129/// x28 寄存器偏移
130pub const S_X28: usize = offset_of!(Ptregs, regs_x28);
131/// x29 寄存器偏移
132pub const S_X29: usize = offset_of!(Ptregs, regs_x29);
133/// lr 寄存器偏移
134pub const S_LR: usize = offset_of!(Ptregs, regs_x30);
135/// sp 寄存器偏移
136pub const S_SP: usize = offset_of!(Ptregs, sp);
137/// pc 寄存器偏移
138pub const S_PC: usize = offset_of!(Ptregs, pc);
139/// pstate 寄存器偏移
140pub const S_PSTATE: usize = offset_of!(Ptregs, pstate);
141/// 原始 x0 数据存储偏移
142pub const S_ORIG_X0: usize = offset_of!(Ptregs, orig_x0);
143/// 原始系统调用号偏移
144pub const S_SYSCALLNO: usize = offset_of!(Ptregs, syscallno);
145/// 原始地址限制存储偏移
146pub const S_ORIG_ADDR_LIMIT: usize = offset_of!(Ptregs, orig_addr_limit);
147/// 栈帧地址偏移
148pub const S_STACKFRAME: usize = offset_of!(Ptregs, stackframe);
149/// 帧栈总大小
150pub const S_FRAME_SIZE: usize = size_of::<Ptregs>();
151
152#[cfg(test)]
153mod test {
154    use super::*;
155
156    #[test]
157    fn test() {
158        assert_eq!(S_X0, 0);
159        assert_eq!(S_X1, 8);
160        assert_eq!(S_X2, 16);
161        assert_eq!(S_X3, 24);
162        assert_eq!(S_X4, 32);
163        assert_eq!(S_X5, 40);
164        assert_eq!(S_X6, 48);
165        assert_eq!(S_X7, 56);
166        assert_eq!(S_X8, 64);
167        assert_eq!(S_X9, 72);
168        assert_eq!(S_X10, 80);
169        assert_eq!(S_X11, 88);
170        assert_eq!(S_X12, 96);
171        assert_eq!(S_X13, 104);
172        assert_eq!(S_X14, 112);
173        assert_eq!(S_X15, 120);
174        assert_eq!(S_X16, 128);
175        assert_eq!(S_X17, 136);
176        assert_eq!(S_X18, 144);
177        assert_eq!(S_X19, 152);
178        assert_eq!(S_X20, 160);
179        assert_eq!(S_X21, 168);
180        assert_eq!(S_X22, 176);
181        assert_eq!(S_X23, 184);
182        assert_eq!(S_X24, 192);
183        assert_eq!(S_X25, 200);
184        assert_eq!(S_X26, 208);
185        assert_eq!(S_X27, 216);
186        assert_eq!(S_X28, 224);
187        assert_eq!(S_X29, 232);
188        assert_eq!(S_LR, 240);
189        assert_eq!(S_SP, 248);
190        assert_eq!(S_PC, 256);
191        assert_eq!(S_PSTATE, 264);
192        assert_eq!(S_ORIG_X0, 272);
193        assert_eq!(S_SYSCALLNO, 280);
194        assert_eq!(S_ORIG_ADDR_LIMIT, 288);
195        assert_eq!(S_STACKFRAME, 304);
196        assert_eq!(S_FRAME_SIZE, 320);
197    }
198}
199
200/// 虚拟地址 bit 数
201pub const VA_BITS: usize = 48;
202
203/// 物理地址 bit 数
204pub const PA_BITS: usize = 48;
205
206/// 内核起始虚拟地址
207///
208/// 最大到 2G
209pub const KIMAGE_START: usize = 0xffff000000000000;
210
211/// 内核 io 空间起始地址
212///
213/// 最大 16G
214pub const KIO_VADDR: usize = 0xffff001000000000;
215/// 内核 io 空间结束地址
216pub const KIO_VADDR_END: usize = 0xffff001400000000;
217
218/// 内核线性空间起始地址
219///
220/// 最大到 16G
221pub const KMEM_VADDR: usize = 0xffff002000000000;
222/// 内核线性空间结束地址
223pub const KMEM_VADDR_END: usize = 0xffff002400000000;
224
225/// 内核页结构空间起始地址
226///
227/// 最大到 16G
228pub const KPAGE_VADDR: usize = 0xffff003000000000;
229/// 内核页结构空间结束地址
230pub const KPAGE_VADDR_END: usize = 0xffff003400000000;
231
232/// el2 级别标识
233pub const CurrentEL_EL2: usize = 2 << 2;
234
235/// el1 系统寄存器预留1
236pub const SCTLR_EL1_RES1: usize = 1 << 11 | 1 << 20 | 1 << 22 | 1 << 28 | 1 << 29;
237/// el2 系统寄存器预留2
238pub const SCTLR_EL2_RES1: usize =
239    1 << 4 | 1 << 5 | 1 << 11 | 1 << 16 | 1 << 18 | 1 << 22 | 1 << 23 | 1 << 28 | 1 << 29;
240
241/// el1 小端
242pub const ENDIAN_SET_EL1: usize = 0;
243/// el2 小端
244pub const ENDIAN_SET_EL2: usize = 0;
245
246/// boot 在 el1
247pub const BOOT_CPU_MODE_EL1: usize = 0xe11;
248/// boot 在 el2
249pub const BOOT_CPU_MODE_EL2: usize = 0xe12;
250
251/// SPSR bit F
252pub const PSR_F_BIT: usize = 0x00000040;
253/// SPSR bit I
254pub const PSR_I_BIT: usize = 0x00000080;
255/// SPSR bit A
256pub const PSR_A_BIT: usize = 0x00000100;
257/// SPSR bit D
258pub const PSR_D_BIT: usize = 0x00000200;
259
260/// psr el0t
261pub const PSR_MODE_EL0t: usize = 0x00000000;
262/// psr el1t
263pub const PSR_MODE_EL1t: usize = 0x00000004;
264/// psr el1h
265pub const PSR_MODE_EL1h: usize = 0x00000005;
266/// psr el2t
267pub const PSR_MODE_EL2t: usize = 0x00000008;
268/// psr el2h
269pub const PSR_MODE_EL2h: usize = 0x00000009;
270/// psr el3t
271pub const PSR_MODE_EL3t: usize = 0x0000000c;
272/// psr el3h
273pub const PSR_MODE_EL3h: usize = 0x0000000d;
274/// psr mask
275pub const PSR_MODE_MASK: usize = 0x0000000f;
276
277/// psr mode32
278pub const PSR_MODE32_BIT: usize = 0x00000010;
279
280/// nGnRnE
281pub const MT_DEVICE_nGnRnE: usize = 0;
282/// nGnRE
283pub const MT_DEVICE_nGnRE: usize = 1;
284/// GRE
285pub const MT_DEVICE_GRE: usize = 2;
286/// NC
287pub const MT_NORMAL_NC: usize = 3;
288/// NORMAL
289pub const MT_NORMAL: usize = 4;
290/// WT
291pub const MT_NORMAL_WT: usize = 5;
292
293/// 内存域属性
294///
295/// Memory region attributes for LPAE:
296///
297/// ```text
298///  n = AttrIndx[2:0]
299///      n   MAIR
300///  DEVICE_nGnRnE   000    00000000
301///  DEVICE_nGnRE    001    00000100
302///  DEVICE_GRE      010    00001100
303///  NORMAL_NC       011    01000100
304///  NORMAL          100    11111111
305///  NORMAL_WT       101    10111011
306/// ```
307pub const MAIR_ATTR: usize = (0x04 << (MT_DEVICE_nGnRE * 8))
308    | (0x0c << (MT_DEVICE_GRE * 8))
309    | (0x44 << (MT_NORMAL_NC * 8))
310    | (0xff << (MT_NORMAL * 8))
311    | (0xbb << (MT_NORMAL_WT * 8));
312
313/// pgd 页表 type
314pub const PGD_TYPE_TABLE: usize = 3;
315/// pgd 页表特权级不可执行
316pub const PGD_TABLE_PXN: usize = 1 << 59;
317/// pgd 页表非特权级不可执行
318pub const PGD_TABLE_UXN: usize = 1 << 60;
319
320/// pud 页表 type
321pub const PUD_TYPE_TABLE: usize = 3;
322/// pud 页表特权级不可执行
323pub const PUD_TABLE_PXN: usize = 1 << 59;
324/// pud 页表非特权级不可执行
325pub const PUD_TABLE_UXN: usize = 1 << 58;
326
327/// pmd 页表 type
328pub const PMD_TYPE_TABLE: usize = 3;
329/// pmd 页表特权级不可执行
330pub const PMD_TABLE_PXN: usize = 1 << 59;
331/// pmd 页表非特权级不可执行
332pub const PMD_TABLE_UXN: usize = 1 << 58;
333
334/// pud 段
335pub const PUD_TYPE_SECT: usize = 1 << 0;
336/// pud af
337pub const PUD_TYPE_AF: usize = 1 << 10;
338/// pud
339pub const PUD_SECT_S: usize = 3 << 8;
340/// pud flags
341pub const SWAPPER_PUD_FLAGS: usize = PUD_TYPE_SECT | PUD_TYPE_AF | PUD_SECT_S;
342
343/// 默认的 mmu flags, 可读可写可执行
344pub const SWAPPER_MM_NORMALFLAGS: usize = (MT_NORMAL << 2) | SWAPPER_PUD_FLAGS;
345/// 默认的 mmu flags, NC IO 读写
346pub const SWAPPER_MM_IOFLAGS: usize = (MT_DEVICE_nGnRE << 2) | SWAPPER_PUD_FLAGS;
347
348/// pgd 偏移
349pub const PGD_SHIFT: usize = 39;
350/// pgd 大小 512G
351pub const PGD_SIZE: usize = 0x8000000000;
352/// pgd mask
353pub const PGD_MASK: usize = 0xffffff8000000000;
354/// pgd 数量
355pub const PTRS_PER_PGD: usize = 512;
356
357/// pud 偏移
358pub const PUD_SHIFT: usize = 30;
359/// pud 大小 1G
360pub const PUD_SIZE: usize = 0x40000000;
361/// pud mask
362pub const PUD_MASK: usize = 0xffffffffc0000000;
363/// pud 数量
364pub const PTRS_PER_PUD: usize = 512;
365
366/// pmd 偏移
367pub const PMD_SHIFT: usize = 21;
368/// pmd 大小 2M
369pub const PMD_SIZE: usize = 0x200000;
370/// pmd mask
371pub const PMD_MASK: usize = 0xffffffffffe00000;
372/// pmd 数量
373pub const PTRS_PER_PMD: usize = 512;
374
375/// pte 偏移
376pub const PTE_SHIFT: usize = 12;
377/// pte 大小 4K
378pub const PTE_SIZE: usize = 0x1000;
379/// pte mask
380pub const PTE_MASK: usize = 0xfffffffffffff000;
381/// pte 数量
382pub const PTRS_PER_PTE: usize = 512;
383
384/// 页大小
385pub const PAGE_SIZE: usize = PTE_SIZE;
386
387/// 线程栈大小(包括 irq 栈) 16K
388pub const THREAD_STACK_SIZE: usize = 1 << 14;
389
390/// `SCTLR_ELx_DSSBS`
391pub const SCTLR_ELx_DSSBS: usize = 1 << 44;
392/// `SCTLR_ELx_ENIA`
393pub const SCTLR_ELx_ENIA: usize = 1 << 31;
394/// `SCTLR_ELx_ENIB`
395pub const SCTLR_ELx_ENIB: usize = 1 << 30;
396/// `SCTLR_ELx_ENDA`
397pub const SCTLR_ELx_ENDA: usize = 1 << 27;
398/// `SCTLR_ELx_EE`
399pub const SCTLR_ELx_EE: usize = 1 << 25;
400/// `SCTLR_ELx_IESB`
401pub const SCTLR_ELx_IESB: usize = 1 << 21;
402/// `SCTLR_ELx_WXN`
403pub const SCTLR_ELx_WXN: usize = 1 << 19;
404/// `SCTLR_ELx_ENDB`
405pub const SCTLR_ELx_ENDB: usize = 1 << 13;
406/// `SCTLR_ELx_I`
407pub const SCTLR_ELx_I: usize = 1 << 12;
408/// `SCTLR_ELx_SA`
409pub const SCTLR_ELx_SA: usize = 1 << 3;
410/// `SCTLR_ELx_C`
411pub const SCTLR_ELx_C: usize = 1 << 2;
412/// `SCTLR_ELx_A`
413pub const SCTLR_ELx_A: usize = 1 << 1;
414/// `SCTLR_ELx_M`
415pub const SCTLR_ELx_M: usize = 1 << 0;
416
417/// `SCTLR_EL1_UCI`
418pub const SCTLR_EL1_UCI: usize = 1 << 26;
419/// `SCTLR_EL1_E0E`
420pub const SCTLR_EL1_E0E: usize = 1 << 24;
421/// `SCTLR_EL1_SPAN`
422pub const SCTLR_EL1_SPAN: usize = 1 << 23;
423/// `SCTLR_EL1_NTWE`
424pub const SCTLR_EL1_NTWE: usize = 1 << 18;
425/// `SCTLR_EL1_NTWI`
426pub const SCTLR_EL1_NTWI: usize = 1 << 16;
427/// `SCTLR_EL1_UCT`
428pub const SCTLR_EL1_UCT: usize = 1 << 15;
429/// `SCTLR_EL1_DZE`
430pub const SCTLR_EL1_DZE: usize = 1 << 14;
431/// `SCTLR_EL1_UMA`
432pub const SCTLR_EL1_UMA: usize = 1 << 9;
433/// `SCTLR_EL1_SED`
434pub const SCTLR_EL1_SED: usize = 1 << 8;
435/// `SCTLR_EL1_ITD`
436pub const SCTLR_EL1_ITD: usize = 1 << 7;
437/// `SCTLR_EL1_CP15BEN`
438pub const SCTLR_EL1_CP15BEN: usize = 1 << 5;
439/// `SCTLR_EL1_SA0`
440pub const SCTLR_EL1_SA0: usize = 1 << 4;
441
442/// `SCTLR_EL1_SET`
443pub const SCTLR_EL1_SET: usize = SCTLR_ELx_M
444    | SCTLR_ELx_C
445    | SCTLR_ELx_SA
446    | SCTLR_EL1_SA0
447    | SCTLR_EL1_SED
448    | SCTLR_ELx_I
449    | SCTLR_EL1_DZE
450    | SCTLR_EL1_UCT
451    | SCTLR_EL1_NTWE
452    | SCTLR_ELx_IESB
453    | SCTLR_EL1_SPAN
454    | ENDIAN_SET_EL1
455    | SCTLR_EL1_UCI
456    | SCTLR_EL1_RES1;
457
458/// `TCR_T0SZ_OFFSET`
459pub const TCR_T0SZ_OFFSET: usize = 0;
460/// `TCR_T1SZ_OFFSET`
461pub const TCR_T1SZ_OFFSET: usize = 16;
462/// `TCR_T0SZ`
463pub const TCR_T0SZ: usize = (64 - VA_BITS) << TCR_T0SZ_OFFSET;
464/// `TCR_T1SZ`
465pub const TCR_T1SZ: usize = (64 - VA_BITS) << TCR_T1SZ_OFFSET;
466/// `TCR_TxSZ`
467pub const TCR_TxSZ: usize = TCR_T0SZ | TCR_T1SZ;
468/// `TCR_TxSZ_WIDTH`
469pub const TCR_TxSZ_WIDTH: usize = 6;
470
471/// `TCR_IRGN0_SHIFT`
472pub const TCR_IRGN0_SHIFT: usize = 8;
473/// `TCR_IRGN1_SHIFT`
474pub const TCR_IRGN1_SHIFT: usize = 24;
475/// `TCR_IRGN0_WBWA`
476pub const TCR_IRGN0_WBWA: usize = 1 << TCR_IRGN0_SHIFT;
477/// `TCR_IRGN1_WBWA`
478pub const TCR_IRGN1_WBWA: usize = 1 << TCR_IRGN1_SHIFT;
479/// `TCR_IRGN_WBWA`
480pub const TCR_IRGN_WBWA: usize = TCR_IRGN0_WBWA | TCR_IRGN1_WBWA;
481
482/// `TCR_ORGN0_SHIFT`
483pub const TCR_ORGN0_SHIFT: usize = 10;
484/// `TCR_ORGN1_SHIFT`
485pub const TCR_ORGN1_SHIFT: usize = 26;
486/// `TCR_ORGN0_WBWA`
487pub const TCR_ORGN0_WBWA: usize = 1 << TCR_ORGN0_SHIFT;
488/// `TCR_ORGN1_WBWA`
489pub const TCR_ORGN1_WBWA: usize = 1 << TCR_ORGN1_SHIFT;
490/// `TCR_ORGN_WBWA`
491pub const TCR_ORGN_WBWA: usize = TCR_ORGN0_WBWA | TCR_ORGN1_WBWA;
492
493/// `TCR_SH0_SHIFT`
494pub const TCR_SH0_SHIFT: usize = 12;
495/// `TCR_SH1_SHIFT`
496pub const TCR_SH1_SHIFT: usize = 28;
497/// `TCR_SH0_INNER`
498pub const TCR_SH0_INNER: usize = 3 << TCR_SH0_SHIFT;
499/// `TCR_SH1_INNER`
500pub const TCR_SH1_INNER: usize = 3 << TCR_SH1_SHIFT;
501/// `TCR_SHARED`
502pub const TCR_SHARED: usize = TCR_SH0_INNER | TCR_SH1_INNER;
503
504/// `TCR_TG0_SHIFT`
505pub const TCR_TG0_SHIFT: usize = 14;
506/// `TCR_TG1_SHIFT`
507pub const TCR_TG1_SHIFT: usize = 30;
508/// `TCR_TG0_4K`
509pub const TCR_TG0_4K: usize = 0 << TCR_TG0_SHIFT;
510/// `TCR_TG1_4K`
511pub const TCR_TG1_4K: usize = 2 << TCR_TG1_SHIFT;
512
513/// `TCR_CACHE_FLAGS`
514pub const TCR_CACHE_FLAGS: usize = TCR_IRGN_WBWA | TCR_ORGN_WBWA;
515/// `TCR_SMP_FLAGS`
516pub const TCR_SMP_FLAGS: usize = TCR_SHARED;
517/// `TCR_TG_FLAGS`
518pub const TCR_TG_FLAGS: usize = TCR_TG0_4K | TCR_TG1_4K;
519
520/// `TCR_A1`
521pub const TCR_A1: usize = 1 << 22;
522/// `TCR_ASID16`
523pub const TCR_ASID16: usize = 1 << 36;
524/// `TCR_TBI0`
525pub const TCR_TBI0: usize = 1 << 37;
526
527/// `ID_AA64MMFR0_PARANGE_48`
528pub const ID_AA64MMFR0_PARANGE_48: usize = 0x5;
529/// `ID_AA64MMFR0_PARANGE_MAX`
530pub const ID_AA64MMFR0_PARANGE_MAX: usize = ID_AA64MMFR0_PARANGE_48;
531/// `ID_AA64MMFR0_PARANGE_SHIFT`
532pub const ID_AA64MMFR0_PARANGE_SHIFT: usize = 0;
533/// `TCR_IPS_SHIFT`
534pub const TCR_IPS_SHIFT: usize = 32;
535
536/// `ID_AA64MMFR0_TGRAN4_SHIFT`
537pub const ID_AA64MMFR0_TGRAN4_SHIFT: usize = 28;
538/// `ID_AA64MMFR0_TGRAN4_SUPPORTED`
539pub const ID_AA64MMFR0_TGRAN4_SUPPORTED: usize = 0;
540/// `ID_AA64MMFR0_TGRAN_SHIFT`
541pub const ID_AA64MMFR0_TGRAN_SHIFT: usize = ID_AA64MMFR0_TGRAN4_SHIFT;
542/// `ID_AA64MMFR0_TGRAN_SUPPORTED`
543pub const ID_AA64MMFR0_TGRAN_SUPPORTED: usize = ID_AA64MMFR0_TGRAN4_SUPPORTED;
544
545/// `KERNEL_DS`
546pub const KERNEL_DS: usize = usize::MAX;
547/// `USER_DS`
548pub const USER_DS: usize = (1 << VA_BITS) - 1;
549
550/// `NO_SYSCALL`
551pub const NO_SYSCALL: isize = -1;
552
553/// `BUG_BRK_IMM`
554pub const BUG_BRK_IMM: usize = 0x800;
555
556pub const ESR_ELx_EC_UNKNOWN: usize = 0x00;
557pub const ESR_ELx_EC_WFx: usize = 0x01;
558// Unallocated EC: 0x02
559pub const ESR_ELx_EC_CP15_32: usize = 0x03;
560pub const ESR_ELx_EC_CP15_64: usize = 0x04;
561pub const ESR_ELx_EC_CP14_MR: usize = 0x05;
562pub const ESR_ELx_EC_CP14_LS: usize = 0x06;
563pub const ESR_ELx_EC_FP_ASIMD: usize = 0x07;
564pub const ESR_ELx_EC_CP10_ID: usize = 0x08; // EL2 only
565pub const ESR_ELx_EC_PAC: usize = 0x09; // EL2 and above
566// Unallocated EC: 0x0A - 0x0B
567pub const ESR_ELx_EC_CP14_64: usize = 0x0C;
568// Unallocated EC: 0x0d
569pub const ESR_ELx_EC_ILL: usize = 0x0E;
570// Unallocated EC: 0x0F - 0x10
571pub const ESR_ELx_EC_SVC32: usize = 0x11;
572pub const ESR_ELx_EC_HVC32: usize = 0x12; // EL2 only
573pub const ESR_ELx_EC_SMC32: usize = 0x13; // EL2 and above
574// Unallocated EC: 0x14
575pub const ESR_ELx_EC_SVC64: usize = 0x15;
576pub const ESR_ELx_EC_HVC64: usize = 0x16; // EL2 and above
577pub const ESR_ELx_EC_SMC64: usize = 0x17; // EL2 and above
578pub const ESR_ELx_EC_SYS64: usize = 0x18;
579pub const ESR_ELx_EC_SVE: usize = 0x19;
580// Unallocated EC: 0x1A - 0x1E
581pub const ESR_ELx_EC_IMP_DEF: usize = 0x1f; // EL3 only
582pub const ESR_ELx_EC_IABT_LOW: usize = 0x20;
583pub const ESR_ELx_EC_IABT_CUR: usize = 0x21;
584pub const ESR_ELx_EC_PC_ALIGN: usize = 0x22;
585// Unallocated EC: 0x23
586pub const ESR_ELx_EC_DABT_LOW: usize = 0x24;
587pub const ESR_ELx_EC_DABT_CUR: usize = 0x25;
588pub const ESR_ELx_EC_SP_ALIGN: usize = 0x26;
589// Unallocated EC: 0x27
590pub const ESR_ELx_EC_FP_EXC32: usize = 0x28;
591// Unallocated EC: 0x29 - 0x2B
592pub const ESR_ELx_EC_FP_EXC64: usize = 0x2C;
593// Unallocated EC: 0x2D - 0x2E
594pub const ESR_ELx_EC_SERROR: usize = 0x2F;
595pub const ESR_ELx_EC_BREAKPT_LOW: usize = 0x30;
596pub const ESR_ELx_EC_BREAKPT_CUR: usize = 0x31;
597pub const ESR_ELx_EC_SOFTSTP_LOW: usize = 0x32;
598pub const ESR_ELx_EC_SOFTSTP_CUR: usize = 0x33;
599pub const ESR_ELx_EC_WATCHPT_LOW: usize = 0x34;
600pub const ESR_ELx_EC_WATCHPT_CUR: usize = 0x35;
601// Unallocated EC: 0x36 - 0x37
602pub const ESR_ELx_EC_BKPT32: usize = 0x38;
603// Unallocated EC: 0x39
604pub const ESR_ELx_EC_VECTOR32: usize = 0x3A; // EL2 only
605// Unallocted EC: 0x3B
606pub const ESR_ELx_EC_BRK64: usize = 0x3C;
607// Unallocated EC: 0x3D - 0x3F
608pub const ESR_ELx_EC_MAX: usize = 0x3F;
609
610pub const ESR_ELx_EC_SHIFT: usize = 26;
611pub const ESR_ELx_EC_MASK: usize = (0x3F) << ESR_ELx_EC_SHIFT;
612pub const fn esr_elx_ec(esr: usize) -> usize {
613    ((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT
614}
615
616pub const ESR_ELx_IL_SHIFT: usize = 25;
617pub const ESR_ELx_IL: usize = (1) << ESR_ELx_IL_SHIFT;
618pub const ESR_ELx_ISS_MASK: usize = ESR_ELx_IL - 1;
619
620// ISS field definitions shared by different classes
621pub const ESR_ELx_WNR_SHIFT: usize = 6;
622pub const ESR_ELx_WNR: usize = (1) << ESR_ELx_WNR_SHIFT;
623
624// Asynchronous Error Type
625pub const ESR_ELx_IDS_SHIFT: usize = 24;
626pub const ESR_ELx_IDS: usize = (1) << ESR_ELx_IDS_SHIFT;
627pub const ESR_ELx_AET_SHIFT: usize = 10;
628pub const ESR_ELx_AET: usize = (0x7) << ESR_ELx_AET_SHIFT;
629
630pub const ESR_ELx_AET_UC: usize = (0) << ESR_ELx_AET_SHIFT;
631pub const ESR_ELx_AET_UEU: usize = (1) << ESR_ELx_AET_SHIFT;
632pub const ESR_ELx_AET_UEO: usize = (2) << ESR_ELx_AET_SHIFT;
633pub const ESR_ELx_AET_UER: usize = (3) << ESR_ELx_AET_SHIFT;
634pub const ESR_ELx_AET_CE: usize = (6) << ESR_ELx_AET_SHIFT;
635
636// Shared ISS field definitions for Data/Instruction aborts
637pub const ESR_ELx_SET_SHIFT: usize = 11;
638pub const ESR_ELx_SET_MASK: usize = (3) << ESR_ELx_SET_SHIFT;
639pub const ESR_ELx_FnV_SHIFT: usize = 10;
640pub const ESR_ELx_FnV: usize = (1) << ESR_ELx_FnV_SHIFT;
641pub const ESR_ELx_EA_SHIFT: usize = 9;
642pub const ESR_ELx_EA: usize = (1) << ESR_ELx_EA_SHIFT;
643pub const ESR_ELx_S1PTW_SHIFT: usize = 7;
644pub const ESR_ELx_S1PTW: usize = (1) << ESR_ELx_S1PTW_SHIFT;
645
646// Shared ISS fault status code(IFSC/DFSC) for Data/Instruction aborts
647pub const ESR_ELx_FSC: usize = 0x3F;
648pub const ESR_ELx_FSC_TYPE: usize = 0x3C;
649pub const ESR_ELx_FSC_EXTABT: usize = 0x10;
650pub const ESR_ELx_FSC_SERROR: usize = 0x11;
651pub const ESR_ELx_FSC_ACCESS: usize = 0x08;
652pub const ESR_ELx_FSC_FAT: usize = 0x04;
653pub const ESR_ELx_FSC_PERM: usize = 0x0C;
654
655// ISS field definitions for Data Aborts
656pub const ESR_ELx_ISV_SHIFT: usize = 24;
657pub const ESR_ELx_ISV: usize = (1) << ESR_ELx_ISV_SHIFT;
658pub const ESR_ELx_SAS_SHIFT: usize = 22;
659pub const ESR_ELx_SAS: usize = (3) << ESR_ELx_SAS_SHIFT;
660pub const ESR_ELx_SSE_SHIFT: usize = 21;
661pub const ESR_ELx_SSE: usize = (1) << ESR_ELx_SSE_SHIFT;
662pub const ESR_ELx_SRT_SHIFT: usize = 16;
663pub const ESR_ELx_SRT_MASK: usize = (0x1F) << ESR_ELx_SRT_SHIFT;
664pub const ESR_ELx_SF_SHIFT: usize = 15;
665pub const ESR_ELx_SF: usize = (1) << ESR_ELx_SF_SHIFT;
666pub const ESR_ELx_AR_SHIFT: usize = 14;
667pub const ESR_ELx_AR: usize = (1) << ESR_ELx_AR_SHIFT;
668pub const ESR_ELx_CM_SHIFT: usize = 8;
669pub const ESR_ELx_CM: usize = (1) << ESR_ELx_CM_SHIFT;
670
671// ISS field definitions for exceptions taken in to Hyp
672pub const ESR_ELx_CV: usize = (1) << 24;
673pub const ESR_ELx_COND_SHIFT: usize = 20;
674pub const ESR_ELx_COND_MASK: usize = (0xF) << ESR_ELx_COND_SHIFT;
675pub const ESR_ELx_WFx_ISS_TI: usize = (1) << 0;
676pub const ESR_ELx_WFx_ISS_WFI: usize = 0;
677pub const ESR_ELx_WFx_ISS_WFE: usize = (1) << 0;
678pub const ESR_ELx_xVC_IMM_MASK: usize = (1 << 16) - 1;
679
680pub const DISR_EL1_IDS: usize = (1) << 24;
681// DISR_EL1 and ESR_ELx share the bottom 13 bits, but the RES0 bits may mean
682// different things in the future...
683pub const DISR_EL1_ESR_MASK: usize = ESR_ELx_AET | ESR_ELx_EA | ESR_ELx_FSC;
684
685// ESR value templates for specific events
686pub const ESR_ELx_WFx_MASK: usize = ESR_ELx_EC_MASK | ESR_ELx_WFx_ISS_TI;
687pub const ESR_ELx_WFx_WFI_VAL: usize = (ESR_ELx_EC_WFx << ESR_ELx_EC_SHIFT) | ESR_ELx_WFx_ISS_WFI;
688
689pub const fn esr_elx_val_brk64(imm: usize) -> usize {
690    (ESR_ELx_EC_BRK64 << ESR_ELx_EC_SHIFT) | ESR_ELx_IL | ((imm) & 0xffff)
691}
692
693// ISS field definitions for System instruction traps
694pub const ESR_ELx_SYS64_ISS_RES0_SHIFT: usize = 22;
695pub const ESR_ELx_SYS64_ISS_RES0_MASK: usize = (0x7) << ESR_ELx_SYS64_ISS_RES0_SHIFT;
696pub const ESR_ELx_SYS64_ISS_DIR_MASK: usize = 0x1;
697pub const ESR_ELx_SYS64_ISS_DIR_READ: usize = 0x1;
698pub const ESR_ELx_SYS64_ISS_DIR_WRITE: usize = 0x0;
699
700pub const ESR_ELx_SYS64_ISS_RT_SHIFT: usize = 5;
701pub const ESR_ELx_SYS64_ISS_RT_MASK: usize = (0x1f) << ESR_ELx_SYS64_ISS_RT_SHIFT;
702pub const ESR_ELx_SYS64_ISS_CRM_SHIFT: usize = 1;
703pub const ESR_ELx_SYS64_ISS_CRM_MASK: usize = (0xf) << ESR_ELx_SYS64_ISS_CRM_SHIFT;
704pub const ESR_ELx_SYS64_ISS_CRN_SHIFT: usize = 10;
705pub const ESR_ELx_SYS64_ISS_CRN_MASK: usize = (0xf) << ESR_ELx_SYS64_ISS_CRN_SHIFT;
706pub const ESR_ELx_SYS64_ISS_OP1_SHIFT: usize = 14;
707pub const ESR_ELx_SYS64_ISS_OP1_MASK: usize = (0x7) << ESR_ELx_SYS64_ISS_OP1_SHIFT;
708pub const ESR_ELx_SYS64_ISS_OP2_SHIFT: usize = 17;
709pub const ESR_ELx_SYS64_ISS_OP2_MASK: usize = (0x7) << ESR_ELx_SYS64_ISS_OP2_SHIFT;
710pub const ESR_ELx_SYS64_ISS_OP0_SHIFT: usize = 20;
711pub const ESR_ELx_SYS64_ISS_OP0_MASK: usize = (0x3) << ESR_ELx_SYS64_ISS_OP0_SHIFT;
712pub const ESR_ELx_SYS64_ISS_SYS_MASK: usize = ESR_ELx_SYS64_ISS_OP0_MASK
713    | ESR_ELx_SYS64_ISS_OP1_MASK
714    | ESR_ELx_SYS64_ISS_OP2_MASK
715    | ESR_ELx_SYS64_ISS_CRN_MASK
716    | ESR_ELx_SYS64_ISS_CRM_MASK;
717pub const fn esr_elx_sys64_iss_sys_val(
718    op0: usize,
719    op1: usize,
720    op2: usize,
721    crn: usize,
722    crm: usize,
723) -> usize {
724    ((op0) << ESR_ELx_SYS64_ISS_OP0_SHIFT)
725        | ((op1) << ESR_ELx_SYS64_ISS_OP1_SHIFT)
726        | ((op2) << ESR_ELx_SYS64_ISS_OP2_SHIFT)
727        | ((crn) << ESR_ELx_SYS64_ISS_CRN_SHIFT)
728        | ((crm) << ESR_ELx_SYS64_ISS_CRM_SHIFT)
729}
730
731pub const ESR_ELx_SYS64_ISS_SYS_OP_MASK: usize =
732    ESR_ELx_SYS64_ISS_SYS_MASK | ESR_ELx_SYS64_ISS_DIR_MASK;
733pub const fn esr_elx_sys64_iss_rt(esr: usize) -> usize {
734    ((esr) & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT
735}
736
737// User space cache operations have the following sysreg encoding
738// in System instructions.
739// op0=1, op1=3, op2=1, crn=7, crm={ 5, 10, 11, 12, 14 }, WRITE (L=0)
740pub const ESR_ELx_SYS64_ISS_CRM_DC_CIVAC: usize = 14;
741pub const ESR_ELx_SYS64_ISS_CRM_DC_CVAP: usize = 12;
742pub const ESR_ELx_SYS64_ISS_CRM_DC_CVAU: usize = 11;
743pub const ESR_ELx_SYS64_ISS_CRM_DC_CVAC: usize = 10;
744pub const ESR_ELx_SYS64_ISS_CRM_IC_IVAU: usize = 5;
745
746pub const ESR_ELx_SYS64_ISS_EL0_CACHE_OP_MASK: usize = ESR_ELx_SYS64_ISS_OP0_MASK
747    | ESR_ELx_SYS64_ISS_OP1_MASK
748    | ESR_ELx_SYS64_ISS_OP2_MASK
749    | ESR_ELx_SYS64_ISS_CRN_MASK
750    | ESR_ELx_SYS64_ISS_DIR_MASK;
751pub const ESR_ELx_SYS64_ISS_EL0_CACHE_OP_VAL: usize =
752    esr_elx_sys64_iss_sys_val(1, 3, 1, 7, 0) | ESR_ELx_SYS64_ISS_DIR_WRITE;
753// User space MRS operations which are supported for emulation
754// have the following sysreg encoding in System instructions.
755// op0 = 3, op1= 0, crn = 0, {crm = 0, 4-7}, READ (L = 1)
756pub const ESR_ELx_SYS64_ISS_SYS_MRS_OP_MASK: usize = ESR_ELx_SYS64_ISS_OP0_MASK
757    | ESR_ELx_SYS64_ISS_OP1_MASK
758    | ESR_ELx_SYS64_ISS_CRN_MASK
759    | ESR_ELx_SYS64_ISS_DIR_MASK;
760pub const ESR_ELx_SYS64_ISS_SYS_MRS_OP_VAL: usize =
761    esr_elx_sys64_iss_sys_val(3, 0, 0, 0, 0) | ESR_ELx_SYS64_ISS_DIR_READ;
762
763pub const ESR_ELx_SYS64_ISS_SYS_CTR: usize = esr_elx_sys64_iss_sys_val(3, 3, 1, 0, 0);
764pub const ESR_ELx_SYS64_ISS_SYS_CTR_READ: usize =
765    ESR_ELx_SYS64_ISS_SYS_CTR | ESR_ELx_SYS64_ISS_DIR_READ;
766
767pub const ESR_ELx_SYS64_ISS_SYS_CNTVCT: usize =
768    esr_elx_sys64_iss_sys_val(3, 3, 2, 14, 0) | ESR_ELx_SYS64_ISS_DIR_READ;
769
770pub const ESR_ELx_SYS64_ISS_SYS_CNTFRQ: usize =
771    esr_elx_sys64_iss_sys_val(3, 3, 0, 14, 0) | ESR_ELx_SYS64_ISS_DIR_READ;
772
773pub const fn esr_sys64_to_sysreg(e: usize) -> usize {
774    sys_reg(
775        ((e) & ESR_ELx_SYS64_ISS_OP0_MASK) >> ESR_ELx_SYS64_ISS_OP0_SHIFT,
776        ((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >> ESR_ELx_SYS64_ISS_OP1_SHIFT,
777        ((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >> ESR_ELx_SYS64_ISS_CRN_SHIFT,
778        ((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >> ESR_ELx_SYS64_ISS_CRM_SHIFT,
779        ((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >> ESR_ELx_SYS64_ISS_OP2_SHIFT,
780    )
781}
782
783pub const fn esr_cp15_to_sysreg(e: usize) -> usize {
784    sys_reg(
785        3,
786        ((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >> ESR_ELx_SYS64_ISS_OP1_SHIFT,
787        ((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >> ESR_ELx_SYS64_ISS_CRN_SHIFT,
788        ((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >> ESR_ELx_SYS64_ISS_CRM_SHIFT,
789        ((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >> ESR_ELx_SYS64_ISS_OP2_SHIFT,
790    )
791}
792
793// ISS field definitions for floating-point exception traps
794// (FP_EXC_32/FP_EXC_64).
795//
796// (The FPEXC_* constants are used instead for common bits.)
797
798pub const ESR_ELx_FP_EXC_TFV: usize = (1) << 23;
799
800// ISS field definitions for CP15 accesses
801pub const ESR_ELx_CP15_32_ISS_DIR_MASK: usize = 0x1;
802pub const ESR_ELx_CP15_32_ISS_DIR_READ: usize = 0x1;
803pub const ESR_ELx_CP15_32_ISS_DIR_WRITE: usize = 0x0;
804
805pub const ESR_ELx_CP15_32_ISS_RT_SHIFT: usize = 5;
806pub const ESR_ELx_CP15_32_ISS_RT_MASK: usize = (0x1f) << ESR_ELx_CP15_32_ISS_RT_SHIFT;
807pub const ESR_ELx_CP15_32_ISS_CRM_SHIFT: usize = 1;
808pub const ESR_ELx_CP15_32_ISS_CRM_MASK: usize = (0xf) << ESR_ELx_CP15_32_ISS_CRM_SHIFT;
809pub const ESR_ELx_CP15_32_ISS_CRN_SHIFT: usize = 10;
810pub const ESR_ELx_CP15_32_ISS_CRN_MASK: usize = (0xf) << ESR_ELx_CP15_32_ISS_CRN_SHIFT;
811pub const ESR_ELx_CP15_32_ISS_OP1_SHIFT: usize = 14;
812pub const ESR_ELx_CP15_32_ISS_OP1_MASK: usize = (0x7) << ESR_ELx_CP15_32_ISS_OP1_SHIFT;
813pub const ESR_ELx_CP15_32_ISS_OP2_SHIFT: usize = 17;
814pub const ESR_ELx_CP15_32_ISS_OP2_MASK: usize = (0x7) << ESR_ELx_CP15_32_ISS_OP2_SHIFT;
815
816pub const ESR_ELx_CP15_32_ISS_SYS_MASK: usize = ESR_ELx_CP15_32_ISS_OP1_MASK
817    | ESR_ELx_CP15_32_ISS_OP2_MASK
818    | ESR_ELx_CP15_32_ISS_CRN_MASK
819    | ESR_ELx_CP15_32_ISS_CRM_MASK
820    | ESR_ELx_CP15_32_ISS_DIR_MASK;
821pub const fn esr_elx_cp15_32_iss_sys_val(op1: usize, op2: usize, crn: usize, crm: usize) -> usize {
822    ((op1) << ESR_ELx_CP15_32_ISS_OP1_SHIFT)
823        | ((op2) << ESR_ELx_CP15_32_ISS_OP2_SHIFT)
824        | ((crn) << ESR_ELx_CP15_32_ISS_CRN_SHIFT)
825        | ((crm) << ESR_ELx_CP15_32_ISS_CRM_SHIFT)
826}
827
828pub const ESR_ELx_CP15_64_ISS_DIR_MASK: usize = 0x1;
829pub const ESR_ELx_CP15_64_ISS_DIR_READ: usize = 0x1;
830pub const ESR_ELx_CP15_64_ISS_DIR_WRITE: usize = 0x0;
831
832pub const ESR_ELx_CP15_64_ISS_RT_SHIFT: usize = 5;
833pub const ESR_ELx_CP15_64_ISS_RT_MASK: usize = (0x1f) << ESR_ELx_CP15_64_ISS_RT_SHIFT;
834
835pub const ESR_ELx_CP15_64_ISS_RT2_SHIFT: usize = 10;
836pub const ESR_ELx_CP15_64_ISS_RT2_MASK: usize = (0x1f) << ESR_ELx_CP15_64_ISS_RT2_SHIFT;
837
838pub const ESR_ELx_CP15_64_ISS_OP1_SHIFT: usize = 16;
839pub const ESR_ELx_CP15_64_ISS_OP1_MASK: usize = (0xf) << ESR_ELx_CP15_64_ISS_OP1_SHIFT;
840pub const ESR_ELx_CP15_64_ISS_CRM_SHIFT: usize = 1;
841pub const ESR_ELx_CP15_64_ISS_CRM_MASK: usize = (0xf) << ESR_ELx_CP15_64_ISS_CRM_SHIFT;
842
843pub const fn esr_elx_cp15_64_iss_sys_val(op1: usize, crm: usize) -> usize {
844    ((op1) << ESR_ELx_CP15_64_ISS_OP1_SHIFT) | ((crm) << ESR_ELx_CP15_64_ISS_CRM_SHIFT)
845}
846
847pub const ESR_ELx_CP15_64_ISS_SYS_MASK: usize =
848    ESR_ELx_CP15_64_ISS_OP1_MASK | ESR_ELx_CP15_64_ISS_CRM_MASK | ESR_ELx_CP15_64_ISS_DIR_MASK;
849
850pub const ESR_ELx_CP15_64_ISS_SYS_CNTVCT: usize =
851    esr_elx_cp15_64_iss_sys_val(1, 14) | ESR_ELx_CP15_64_ISS_DIR_READ;
852
853pub const ESR_ELx_CP15_32_ISS_SYS_CNTFRQ: usize =
854    esr_elx_cp15_32_iss_sys_val(0, 0, 14, 0) | ESR_ELx_CP15_32_ISS_DIR_READ;
855
856pub const fn esr_is_data_abort(esr: usize) -> bool {
857    let ec = esr_elx_ec(esr);
858    ec == ESR_ELx_EC_DABT_LOW || ec == ESR_ELx_EC_DABT_CUR
859}
860
861// ARMv8 ARM reserves the following encoding for system registers:
862// (Ref: ARMv8 ARM, Section: "System instruction class encoding overview",
863//  C5.2, version:ARM DDI 0487A.f)
864// 	[20-19] : Op0
865// 	[18-16] : Op1
866// 	[15-12] : CRn
867// 	[11-8]  : CRm
868// 	[7-5]   : Op2
869pub const Op0_shift: usize = 19;
870pub const Op0_mask: usize = 0x3;
871pub const Op1_shift: usize = 16;
872pub const Op1_mask: usize = 0x7;
873pub const CRn_shift: usize = 12;
874pub const CRn_mask: usize = 0xf;
875pub const CRm_shift: usize = 8;
876pub const CRm_mask: usize = 0xf;
877pub const Op2_shift: usize = 5;
878pub const Op2_mask: usize = 0x7;
879
880pub const fn sys_reg(op0: usize, op1: usize, crn: usize, crm: usize, op2: usize) -> usize {
881    ((op0) << Op0_shift)
882        | ((op1) << Op1_shift)
883        | ((crn) << CRn_shift)
884        | ((crm) << CRm_shift)
885        | ((op2) << Op2_shift)
886}
887
888/// `TIF_NEED_RESCHED`
889pub const TIF_NEED_RESCHED: usize = 1;
890
891/// `_TIF_WORK_MASK`
892pub const _TIF_WORK_MASK: usize = 1 << TIF_NEED_RESCHED;
aarch64_define/lib.rs

aarch64_define/
lib.rs
