aarch64_cpu/registers/
id_aa64mmfr1_el1.rs

1// SPDX-License-Identifier: Apache-2.0 OR MIT
2//
3// Copyright (c) 2018-2023 by the author(s)
4//
5// Author(s):
6//   - Ali Saidi <alisaidi@amazon.com>
7
8//! AArch64 Memory Model Feature Register 1 - EL1
9//!
10//! Provides information about the implemented memory model and memory
11//! management support in AArch64 state.
12
13use tock_registers::{interfaces::Readable, register_bitfields};
14
15register_bitfields! {u64,
16    pub ID_AA64MMFR1_EL1 [
17        /// Support for configurable trapping delay of WFE instructions
18        TWED OFFSET(32) NUMBITS(4) [
19            /// Delaying the trapping of WFE instructions isn't supported
20            Unsupported = 0b0000,
21            /// Delaying the trapping of WFE instructions is supported
22            Supported = 0xb0001,
23        ],
24
25        /// Execute-never control at stage2 is distinct for EL0 and EL1
26        XNX OFFSET(28) NUMBITS(4) [
27            /// There are not distinct stage2 execute never controls for EL1 and EL0
28            Unsupported = 0b0000,
29            /// There are distinct stage2 execute never controls for EL1 and EL0
30            Supported = 0xb0001,
31        ],
32
33        /// Speculative reads can generate SError Interrupts
34        SpecSEI OFFSET(24) NUMBITS(4) [
35            /// PE never generates SError interrupts on a speculative read
36            Never = 0b0000,
37            /// PE may generate SError interrupts on a speculative read
38            Maybe = 0b0001
39        ],
40
41        /// Privileged Access Never support
42        PAN OFFSET(20) NUMBITS(4) [
43            /// Privileged Access Never isn't supported
44            Unsupported = 0b0000,
45            /// Privileged Access Never is supported
46            Supported = 0xb0001,
47            /// Privileged Access Never is supported along with AT instruction support
48            SupportedAT = 0xb0010,
49            /// Enhanced Privileged Access Never is supported
50            SupportedEPAN = 0xb0011,
51        ],
52
53        /// Limited Ordered regions support
54        LO OFFSET(16) NUMBITS(4) [
55            /// Limited Ordered regions aren't supported
56            Unsupported = 0b0000,
57            /// Limited Ordered regions are supported
58            Supported = 0xb0001,
59        ],
60
61        /// Hierarchical Permission can be disabled in TCRs
62        HPDS OFFSET(12) NUMBITS(4) [
63            /// HPDS aren't supported
64            Unsupported = 0b0000,
65            /// HPDS are supported
66            Supported = 0xb0001,
67        ],
68
69        /// Virtualization Host Extensions
70        VH OFFSET(8) NUMBITS(4) [
71            /// Virtualization Host Extensions aren't supported
72            Unsupported = 0b0000,
73            /// Virtualization Host Extensions are supported
74            Supported = 0xb0001,
75        ],
76
77        /// Number of VMID bits that are supported
78        VMIDBits OFFSET(4) NUMBITS(4) [
79            /// 8 bits of VMID are supported
80            Bits8 = 0b0000,
81            /// 16 bits of VMID are supported
82            Bits16 = 0b0010,
83        ],
84
85        /// Hardware updates to Access and Dirty flags in translation tables
86        HAFDBS OFFSET(0) NUMBITS(4) [
87            /// Not supported
88            Unsupported = 0b0000,
89            /// Access flag is supported
90            AccessOnly = 0xb0001,
91            /// Access and dirty flags are supported
92            AccessDirty = 0b0010,
93        ],
94    ]
95}
96
97pub struct Reg;
98
99impl Readable for Reg {
100    type T = u64;
101    type R = ID_AA64MMFR1_EL1::Register;
102
103    sys_coproc_read_raw!(u64, "ID_AA64MMFR1_EL1", "x");
104}
105
106pub const ID_AA64MMFR1_EL1: Reg = Reg;
aarch64_cpu/registers/id_aa64mmfr1_el1.rs

aarch64_cpu/registers/
id_aa64mmfr1_el1.rs
