aarch64_cpu/registers/
cnthctl_el2.rs

1// SPDX-License-Identifier: Apache-2.0 OR MIT
2//
3// Copyright (c) 2018-2023 by the author(s)
4//
5// Author(s):
6//   - Andre Richter <andre.o.richter@gmail.com>
7
8//! Counter-timer Hypervisor Control register - EL2
9//!
10//! Controls the generation of an event stream from the physical counter, and
11//! access from Non-secure EL1 to the physical counter and the Non-secure EL1
12//! physical timer.
13
14use tock_registers::{
15    interfaces::{Readable, Writeable},
16    register_bitfields,
17};
18
19// When HCR_EL2.E2H == 0:
20// TODO: Figure out how we can differentiate depending on HCR_EL2.E2H state
21//
22// For now, implement the HCR_EL2.E2H == 0 version
23register_bitfields! {u64,
24    pub CNTHCTL_EL2 [
25        /// Traps Non-secure EL0 and EL1 accesses to the physical timer registers to EL2.
26        ///
27        /// 0 From AArch64 state: Non-secure EL0 and EL1 accesses to the CNTP_CTL_EL0,
28        ///   CNTP_CVAL_EL0, and CNTP_TVAL_EL0 are trapped to EL2, unless it is trapped by
29        ///   CNTKCTL_EL1.EL0PTEN.
30        ///
31        ///   From AArch32 state: Non-secure EL0 and EL1 accesses to the CNTP_CTL, CNTP_CVAL, and
32        ///   CNTP_TVAL are trapped to EL2, unless it is trapped by CNTKCTL_EL1.EL0PTEN or
33        ///   CNTKCTL.PL0PTEN.
34        ///
35        /// 1 This control does not cause any instructions to be trapped.
36        ///
37        /// If EL3 is implemented and EL2 is not implemented, behavior is as if this bit is 1 other
38        /// than for the purpose of a direct read.
39        EL1PCEN  OFFSET(1) NUMBITS(1) [],
40
41        /// Traps Non-secure EL0 and EL1 accesses to the physical counter register to EL2.
42        ///
43        /// 0 From AArch64 state: Non-secure EL0 and EL1 accesses to the CNTPCT_EL0 are trapped to
44        ///   EL2, unless it is trapped by CNTKCTL_EL1.EL0PCTEN.
45        ///
46        ///   From AArch32 state: Non-secure EL0 and EL1 accesses to the CNTPCT are trapped to EL2,
47        ///   unless it is trapped by CNTKCTL_EL1.EL0PCTEN or CNTKCTL.PL0PCTEN.
48        ///
49        /// 1 This control does not cause any instructions to be trapped.
50        ///
51        /// If EL3 is implemented and EL2 is not implemented, behavior is as if this bit is 1 other
52        /// than for the purpose of a direct read.
53        EL1PCTEN OFFSET(0) NUMBITS(1) []
54    ]
55}
56
57pub struct Reg;
58
59impl Readable for Reg {
60    type T = u64;
61    type R = CNTHCTL_EL2::Register;
62
63    sys_coproc_read_raw!(u64, "CNTHCTL_EL2", "x");
64}
65
66impl Writeable for Reg {
67    type T = u64;
68    type R = CNTHCTL_EL2::Register;
69
70    sys_coproc_write_raw!(u64, "CNTHCTL_EL2", "x");
71}
72
73pub const CNTHCTL_EL2: Reg = Reg {};
aarch64_cpu/registers/cnthctl_el2.rs

aarch64_cpu/registers/
cnthctl_el2.rs
