aarch64_cpu/registers/
ttbr0_el1.rs

1// SPDX-License-Identifier: Apache-2.0 OR MIT
2//
3// Copyright (c) 2018-2023 by the author(s)
4//
5// Author(s):
6//   - Andre Richter <andre.o.richter@gmail.com>
7
8//! Translation Table Base Register 0 - EL1
9//!
10//! Holds the base address of the translation table for the initial lookup for stage 1 of the
11//! translation of an address from the lower VA range in the EL1&0 translation regime, and other
12//! information for this translation regime.
13
14use tock_registers::{
15    interfaces::{Readable, Writeable},
16    register_bitfields,
17};
18
19register_bitfields! {u64,
20    pub TTBR0_EL1 [
21        /// An ASID for the translation table base address. The TCR_EL1.A1 field selects either
22        /// TTBR0_EL1.ASID or TTBR1_EL1.ASID.
23        ///
24        /// If the implementation has only 8 bits of ASID, then the upper 8 bits of this field are
25        /// RES 0.
26        ASID  OFFSET(48) NUMBITS(16) [],
27
28        /// Translation table base address
29        BADDR OFFSET(1) NUMBITS(47) [],
30
31        /// Common not Private
32        CnP   OFFSET(0) NUMBITS(1) []
33    ]
34}
35
36pub struct Reg;
37
38impl Readable for Reg {
39    type T = u64;
40    type R = TTBR0_EL1::Register;
41
42    sys_coproc_read_raw!(u64, "TTBR0_EL1", "x");
43}
44
45impl Writeable for Reg {
46    type T = u64;
47    type R = TTBR0_EL1::Register;
48
49    sys_coproc_write_raw!(u64, "TTBR0_EL1", "x");
50}
51
52impl Reg {
53    #[inline(always)]
54    pub fn get_baddr(&self) -> u64 {
55        self.read(TTBR0_EL1::BADDR) << 1
56    }
57
58    #[inline(always)]
59    pub fn set_baddr(&self, addr: u64) {
60        self.write(TTBR0_EL1::BADDR.val(addr >> 1));
61    }
62}
63
64pub const TTBR0_EL1: Reg = Reg {};
aarch64_cpu/registers/ttbr0_el1.rs

aarch64_cpu/registers/
ttbr0_el1.rs
