aarch64_cpu/lib.rs
1// SPDX-License-Identifier: Apache-2.0 OR MIT
2//
3// Copyright (c) 2018-2023 by the author(s)
4//
5// Author(s):
6// - Andre Richter <andre.o.richter@gmail.com>
7
8//! Low level access to processors using the AArch64 execution state.
9//!
10//! ## Usage
11//!
12//! Please note that for using this crate's [register definitions](src/registers) (as provided by
13//! `aarch64_cpu::registers::*`), you need to also import [`Readable`](registers::Readable) and
14//! [`Writeable`](registers::Writeable).
15//!
16//! ### Example
17//!
18//! Check out https://github.com/rust-embedded/rust-raspberrypi-OS-tutorials for usage examples.
19//! Listed below is a snippet of `rust-raspberrypi-OS-tutorials`'s early boot code.
20//!
21//! ```rust
22//! use aarch64_cpu::{asm, registers::*};
23//!
24//! // Some parts omitted for brevity.
25//!
26//! unsafe fn prepare_el2_to_el1_transition(
27//! virt_boot_core_stack_end_exclusive_addr: u64,
28//! virt_kernel_init_addr: u64,
29//! ) {
30//! // Enable timer counter registers for EL1.
31//! CNTHCTL_EL2.write(CNTHCTL_EL2::EL1PCEN::SET + CNTHCTL_EL2::EL1PCTEN::SET);
32//!
33//! // No offset for reading the counters.
34//! CNTVOFF_EL2.set(0);
35//!
36//! // Set EL1 execution state to AArch64.
37//! HCR_EL2.write(HCR_EL2::RW::EL1IsAarch64);
38//!
39//! // Set up a simulated exception return.
40//! SPSR_EL2.write(
41//! SPSR_EL2::D::Masked
42//! + SPSR_EL2::A::Masked
43//! + SPSR_EL2::I::Masked
44//! + SPSR_EL2::F::Masked
45//! + SPSR_EL2::M::EL1h,
46//! );
47//! }
48//! ```
49//!
50//! ## Disclaimer
51//!
52//! Descriptive comments in the source files are taken from the [ARM Architecture Reference Manual
53//! ARMv8, for ARMv8-A architecture
54//! profile](https://static.docs.arm.com/ddi0487/ca/DDI0487C_a_armv8_arm.pdf?_ga=2.266626254.1122218691.1534883460-1326731866.1530967873).
55
56#![no_std]
57
58pub mod asm;
59pub mod registers;