aarch64_cpu/registers/
spsr_el3.rs

1// SPDX-License-Identifier: Apache-2.0 OR MIT
2//
3// Copyright (c) 2018-2023 by the author(s)
4//
5// Author(s):
6//   - Andre Richter <andre.o.richter@gmail.com>
7//   - Berkus Decker <berkus+github@metta.systems>
8
9//! Saved Program Status Register - EL3
10//!
11//! Holds the saved process state when an exception is taken to EL3.
12
13use tock_registers::{
14    interfaces::{Readable, Writeable},
15    register_bitfields,
16};
17
18register_bitfields! {u64,
19    pub SPSR_EL3 [
20        /// Negative condition flag.
21        ///
22        /// Set to the value of the N condition flag on taking an exception to EL3, and copied to
23        /// the N condition flag on executing an exception return operation in EL3.
24        ///
25        /// Set to 1 if the result of the last flag-setting instruction was negative.
26        N OFFSET(31) NUMBITS(1) [],
27
28        /// Zero condition flag.
29        ///
30        /// Set to the value of the Z condition flag on taking an exception to EL3, and copied to
31        /// the Z condition flag on executing an exception return operation in EL3.
32        ///
33        /// Set to 1 if the result of the last flag-setting instruction was zero, and to 0
34        /// otherwise. A result of zero often indicates an equal result from a comparison.
35        Z OFFSET(30) NUMBITS(1) [],
36
37        /// Carry condition flag.
38        ///
39        /// Set to the value of the C condition flag on taking an exception to EL3, and copied to
40        /// the C condition flag on executing an exception return operation in EL3.
41        ///
42        /// Set to 1 if the last flag-setting instruction resulted in a carry condition, for example
43        /// an unsigned overflow on an addition.
44        C OFFSET(29) NUMBITS(1) [],
45
46        /// Overflow condition flag.
47        ///
48        /// Set to the value of the V condition flag on taking an exception to EL3, and copied to
49        /// the V condition flag on executing an exception return operation in EL3.
50        ///
51        /// Set to 1 if the last flag-setting instruction resulted in an overflow condition, for
52        /// example a signed overflow on an addition.
53        V OFFSET(28) NUMBITS(1) [],
54
55        /// Software step. Shows the value of PSTATE.SS immediately before the exception was taken.
56        SS OFFSET(21) NUMBITS(1) [],
57
58        /// Illegal Execution state bit. Shows the value of PSTATE.IL immediately before the
59        /// exception was taken.
60        IL OFFSET(20) NUMBITS(1) [],
61
62        /// Process state D mask. The possible values of this bit are:
63        ///
64        /// 0 Watchpoint, Breakpoint, and Software Step exceptions targeted at the current Exception
65        ///   level are not masked.
66        ///
67        /// 1 Watchpoint, Breakpoint, and Software Step exceptions targeted at the current Exception
68        ///   level are masked.
69        ///
70        /// When the target Exception level of the debug exception is higher than the current
71        /// Exception level, the exception is not masked by this bit.
72        D OFFSET(9) NUMBITS(1) [
73            Unmasked = 0,
74            Masked = 1
75        ],
76
77        /// SError interrupt mask bit. The possible values of this bit are:
78        ///
79        /// 0 Exception not masked.
80        /// 1 Exception masked.
81        A OFFSET(8) NUMBITS(1) [
82            Unmasked = 0,
83            Masked = 1
84        ],
85
86        /// IRQ mask bit. The possible values of this bit are:
87        ///
88        /// 0 Exception not masked.
89        /// 1 Exception masked.
90        I OFFSET(7) NUMBITS(1) [
91            Unmasked = 0,
92            Masked = 1
93        ],
94
95        /// FIQ mask bit. The possible values of this bit are:
96        ///
97        /// 0 Exception not masked.
98        /// 1 Exception masked.
99        F OFFSET(6) NUMBITS(1) [
100            Unmasked = 0,
101            Masked = 1
102        ],
103
104        /// AArch64 state (Exception level and selected SP) that an exception was taken from. The
105        /// possible values are:
106        ///
107        /// M[3:0] | State
108        /// --------------
109        /// 0b0000 | EL0t
110        /// 0b0100 | EL1t
111        /// 0b0101 | EL1h
112        /// 0b1000 | EL2t
113        /// 0b1001 | EL2h
114        /// 0b1100 | EL3t
115        /// 0b1101 | EL3h
116        ///
117        /// Other values are reserved, and returning to an Exception level that is using AArch64
118        /// with a reserved value in this field is treated as an illegal exception return.
119        ///
120        /// The bits in this field are interpreted as follows:
121        ///   - M[3:2] holds the Exception Level.
122        ///   - M[1] is unused and is RES 0 for all non-reserved values.
123        ///   - M[0] is used to select the SP:
124        ///     - 0 means the SP is always SP0.
125        ///     - 1 means the exception SP is determined by the EL.
126        M OFFSET(0) NUMBITS(4) [
127            EL0t = 0b0000,
128            EL1t = 0b0100,
129            EL1h = 0b0101,
130            EL2t = 0b1000,
131            EL2h = 0b1001,
132            EL3t = 0b1100,
133            EL3h = 0b1101
134        ]
135    ]
136}
137
138pub struct Reg;
139
140impl Readable for Reg {
141    type T = u64;
142    type R = SPSR_EL3::Register;
143
144    sys_coproc_read_raw!(u64, "SPSR_EL3", "x");
145}
146
147impl Writeable for Reg {
148    type T = u64;
149    type R = SPSR_EL3::Register;
150
151    sys_coproc_write_raw!(u64, "SPSR_EL3", "x");
152}
153
154pub const SPSR_EL3: Reg = Reg {};
aarch64_cpu/registers/spsr_el3.rs

aarch64_cpu/registers/
spsr_el3.rs
